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Commit 99dbdd98f271899e023d52b3f4c2bf67cdd7eb56

Authored by Tushar Behera
Committed by Kukjin Kim
1 parent 2473f713ec
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

ARM: S3C24XX: Use common macro to define resources on dev-uart.c 

Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

Showing 1 changed file with 16 additions and 40 deletions Inline Diff

arch/arm/mach-s3c24xx/common.c
Diff comments   View file @ 99dbdd9
1 /* linux/arch/arm/plat-s3c24xx/cpu.c 1 /* linux/arch/arm/plat-s3c24xx/cpu.c
2 * 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics 3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/ 4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
6 * 6 *
7 * Common code for S3C24XX machines 7 * Common code for S3C24XX machines
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */ 22 */
23 23
24 24
25 #include <linux/init.h> 25 #include <linux/init.h>
26 #include <linux/module.h> 26 #include <linux/module.h>
27 #include <linux/interrupt.h> 27 #include <linux/interrupt.h>
28 #include <linux/ioport.h> 28 #include <linux/ioport.h>
29 #include <linux/serial_core.h> 29 #include <linux/serial_core.h>
30 #include <linux/platform_device.h> 30 #include <linux/platform_device.h>
31 #include <linux/delay.h> 31 #include <linux/delay.h>
32 #include <linux/io.h> 32 #include <linux/io.h>
33 33
34 #include <mach/hardware.h> 34 #include <mach/hardware.h>
35 #include <mach/regs-clock.h> 35 #include <mach/regs-clock.h>
36 #include <asm/irq.h> 36 #include <asm/irq.h>
37 #include <asm/cacheflush.h> 37 #include <asm/cacheflush.h>
38 #include <asm/system_info.h> 38 #include <asm/system_info.h>
39 #include <asm/system_misc.h> 39 #include <asm/system_misc.h>
40 40
41 #include <asm/mach/arch.h> 41 #include <asm/mach/arch.h>
42 #include <asm/mach/map.h> 42 #include <asm/mach/map.h>
43 43
44 #include <mach/regs-clock.h> 44 #include <mach/regs-clock.h>
45 #include <mach/regs-gpio.h> 45 #include <mach/regs-gpio.h>
46 #include <plat/regs-serial.h> 46 #include <plat/regs-serial.h>
47 47
48 #include <plat/cpu.h> 48 #include <plat/cpu.h>
49 #include <plat/devs.h> 49 #include <plat/devs.h>
50 #include <plat/clock.h> 50 #include <plat/clock.h>
51 #include <plat/s3c2410.h> 51 #include <plat/s3c2410.h>
52 #include <plat/s3c2412.h> 52 #include <plat/s3c2412.h>
53 #include <plat/s3c2416.h> 53 #include <plat/s3c2416.h>
54 #include <plat/s3c244x.h> 54 #include <plat/s3c244x.h>
55 #include <plat/s3c2443.h> 55 #include <plat/s3c2443.h>
56 #include <plat/cpu-freq.h> 56 #include <plat/cpu-freq.h>
57 #include <plat/pll.h> 57 #include <plat/pll.h>
58 58
59 /* table of supported CPUs */ 59 /* table of supported CPUs */
60 60
61 static const char name_s3c2410[] = "S3C2410"; 61 static const char name_s3c2410[] = "S3C2410";
62 static const char name_s3c2412[] = "S3C2412"; 62 static const char name_s3c2412[] = "S3C2412";
63 static const char name_s3c2416[] = "S3C2416/S3C2450"; 63 static const char name_s3c2416[] = "S3C2416/S3C2450";
64 static const char name_s3c2440[] = "S3C2440"; 64 static const char name_s3c2440[] = "S3C2440";
65 static const char name_s3c2442[] = "S3C2442"; 65 static const char name_s3c2442[] = "S3C2442";
66 static const char name_s3c2442b[] = "S3C2442B"; 66 static const char name_s3c2442b[] = "S3C2442B";
67 static const char name_s3c2443[] = "S3C2443"; 67 static const char name_s3c2443[] = "S3C2443";
68 static const char name_s3c2410a[] = "S3C2410A"; 68 static const char name_s3c2410a[] = "S3C2410A";
69 static const char name_s3c2440a[] = "S3C2440A"; 69 static const char name_s3c2440a[] = "S3C2440A";
70 70
71 static struct cpu_table cpu_ids[] __initdata = { 71 static struct cpu_table cpu_ids[] __initdata = {
72 { 72 {
73 .idcode = 0x32410000, 73 .idcode = 0x32410000,
74 .idmask = 0xffffffff, 74 .idmask = 0xffffffff,
75 .map_io = s3c2410_map_io, 75 .map_io = s3c2410_map_io,
76 .init_clocks = s3c2410_init_clocks, 76 .init_clocks = s3c2410_init_clocks,
77 .init_uarts = s3c2410_init_uarts, 77 .init_uarts = s3c2410_init_uarts,
78 .init = s3c2410_init, 78 .init = s3c2410_init,
79 .name = name_s3c2410 79 .name = name_s3c2410
80 }, 80 },
81 { 81 {
82 .idcode = 0x32410002, 82 .idcode = 0x32410002,
83 .idmask = 0xffffffff, 83 .idmask = 0xffffffff,
84 .map_io = s3c2410_map_io, 84 .map_io = s3c2410_map_io,
85 .init_clocks = s3c2410_init_clocks, 85 .init_clocks = s3c2410_init_clocks,
86 .init_uarts = s3c2410_init_uarts, 86 .init_uarts = s3c2410_init_uarts,
87 .init = s3c2410a_init, 87 .init = s3c2410a_init,
88 .name = name_s3c2410a 88 .name = name_s3c2410a
89 }, 89 },
90 { 90 {
91 .idcode = 0x32440000, 91 .idcode = 0x32440000,
92 .idmask = 0xffffffff, 92 .idmask = 0xffffffff,
93 .map_io = s3c2440_map_io, 93 .map_io = s3c2440_map_io,
94 .init_clocks = s3c244x_init_clocks, 94 .init_clocks = s3c244x_init_clocks,
95 .init_uarts = s3c244x_init_uarts, 95 .init_uarts = s3c244x_init_uarts,
96 .init = s3c2440_init, 96 .init = s3c2440_init,
97 .name = name_s3c2440 97 .name = name_s3c2440
98 }, 98 },
99 { 99 {
100 .idcode = 0x32440001, 100 .idcode = 0x32440001,
101 .idmask = 0xffffffff, 101 .idmask = 0xffffffff,
102 .map_io = s3c2440_map_io, 102 .map_io = s3c2440_map_io,
103 .init_clocks = s3c244x_init_clocks, 103 .init_clocks = s3c244x_init_clocks,
104 .init_uarts = s3c244x_init_uarts, 104 .init_uarts = s3c244x_init_uarts,
105 .init = s3c2440_init, 105 .init = s3c2440_init,
106 .name = name_s3c2440a 106 .name = name_s3c2440a
107 }, 107 },
108 { 108 {
109 .idcode = 0x32440aaa, 109 .idcode = 0x32440aaa,
110 .idmask = 0xffffffff, 110 .idmask = 0xffffffff,
111 .map_io = s3c2442_map_io, 111 .map_io = s3c2442_map_io,
112 .init_clocks = s3c244x_init_clocks, 112 .init_clocks = s3c244x_init_clocks,
113 .init_uarts = s3c244x_init_uarts, 113 .init_uarts = s3c244x_init_uarts,
114 .init = s3c2442_init, 114 .init = s3c2442_init,
115 .name = name_s3c2442 115 .name = name_s3c2442
116 }, 116 },
117 { 117 {
118 .idcode = 0x32440aab, 118 .idcode = 0x32440aab,
119 .idmask = 0xffffffff, 119 .idmask = 0xffffffff,
120 .map_io = s3c2442_map_io, 120 .map_io = s3c2442_map_io,
121 .init_clocks = s3c244x_init_clocks, 121 .init_clocks = s3c244x_init_clocks,
122 .init_uarts = s3c244x_init_uarts, 122 .init_uarts = s3c244x_init_uarts,
123 .init = s3c2442_init, 123 .init = s3c2442_init,
124 .name = name_s3c2442b 124 .name = name_s3c2442b
125 }, 125 },
126 { 126 {
127 .idcode = 0x32412001, 127 .idcode = 0x32412001,
128 .idmask = 0xffffffff, 128 .idmask = 0xffffffff,
129 .map_io = s3c2412_map_io, 129 .map_io = s3c2412_map_io,
130 .init_clocks = s3c2412_init_clocks, 130 .init_clocks = s3c2412_init_clocks,
131 .init_uarts = s3c2412_init_uarts, 131 .init_uarts = s3c2412_init_uarts,
132 .init = s3c2412_init, 132 .init = s3c2412_init,
133 .name = name_s3c2412, 133 .name = name_s3c2412,
134 }, 134 },
135 { /* a newer version of the s3c2412 */ 135 { /* a newer version of the s3c2412 */
136 .idcode = 0x32412003, 136 .idcode = 0x32412003,
137 .idmask = 0xffffffff, 137 .idmask = 0xffffffff,
138 .map_io = s3c2412_map_io, 138 .map_io = s3c2412_map_io,
139 .init_clocks = s3c2412_init_clocks, 139 .init_clocks = s3c2412_init_clocks,
140 .init_uarts = s3c2412_init_uarts, 140 .init_uarts = s3c2412_init_uarts,
141 .init = s3c2412_init, 141 .init = s3c2412_init,
142 .name = name_s3c2412, 142 .name = name_s3c2412,
143 }, 143 },
144 { /* a strange version of the s3c2416 */ 144 { /* a strange version of the s3c2416 */
145 .idcode = 0x32450003, 145 .idcode = 0x32450003,
146 .idmask = 0xffffffff, 146 .idmask = 0xffffffff,
147 .map_io = s3c2416_map_io, 147 .map_io = s3c2416_map_io,
148 .init_clocks = s3c2416_init_clocks, 148 .init_clocks = s3c2416_init_clocks,
149 .init_uarts = s3c2416_init_uarts, 149 .init_uarts = s3c2416_init_uarts,
150 .init = s3c2416_init, 150 .init = s3c2416_init,
151 .name = name_s3c2416, 151 .name = name_s3c2416,
152 }, 152 },
153 { 153 {
154 .idcode = 0x32443001, 154 .idcode = 0x32443001,
155 .idmask = 0xffffffff, 155 .idmask = 0xffffffff,
156 .map_io = s3c2443_map_io, 156 .map_io = s3c2443_map_io,
157 .init_clocks = s3c2443_init_clocks, 157 .init_clocks = s3c2443_init_clocks,
158 .init_uarts = s3c2443_init_uarts, 158 .init_uarts = s3c2443_init_uarts,
159 .init = s3c2443_init, 159 .init = s3c2443_init,
160 .name = name_s3c2443, 160 .name = name_s3c2443,
161 }, 161 },
162 }; 162 };
163 163
164 /* minimal IO mapping */ 164 /* minimal IO mapping */
165 165
166 static struct map_desc s3c_iodesc[] __initdata = { 166 static struct map_desc s3c_iodesc[] __initdata = {
167 IODESC_ENT(GPIO), 167 IODESC_ENT(GPIO),
168 IODESC_ENT(IRQ), 168 IODESC_ENT(IRQ),
169 IODESC_ENT(MEMCTRL), 169 IODESC_ENT(MEMCTRL),
170 IODESC_ENT(UART) 170 IODESC_ENT(UART)
171 }; 171 };
172 172
173 /* read cpu identificaiton code */ 173 /* read cpu identificaiton code */
174 174
175 static unsigned long s3c24xx_read_idcode_v5(void) 175 static unsigned long s3c24xx_read_idcode_v5(void)
176 { 176 {
177 #if defined(CONFIG_CPU_S3C2416) 177 #if defined(CONFIG_CPU_S3C2416)
178 /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */ 178 /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
179 179
180 u32 gs = __raw_readl(S3C24XX_GSTATUS1); 180 u32 gs = __raw_readl(S3C24XX_GSTATUS1);
181 181
182 /* test for s3c2416 or similar device */ 182 /* test for s3c2416 or similar device */
183 if ((gs >> 16) == 0x3245) 183 if ((gs >> 16) == 0x3245)
184 return gs; 184 return gs;
185 #endif 185 #endif
186 186
187 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) 187 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
188 return __raw_readl(S3C2412_GSTATUS1); 188 return __raw_readl(S3C2412_GSTATUS1);
189 #else 189 #else
190 return 1UL; /* don't look like an 2400 */ 190 return 1UL; /* don't look like an 2400 */
191 #endif 191 #endif
192 } 192 }
193 193
194 static unsigned long s3c24xx_read_idcode_v4(void) 194 static unsigned long s3c24xx_read_idcode_v4(void)
195 { 195 {
196 return __raw_readl(S3C2410_GSTATUS1); 196 return __raw_readl(S3C2410_GSTATUS1);
197 } 197 }
198 198
199 static void s3c24xx_default_idle(void) 199 static void s3c24xx_default_idle(void)
200 { 200 {
201 unsigned long tmp; 201 unsigned long tmp;
202 int i; 202 int i;
203 203
204 /* idle the system by using the idle mode which will wait for an 204 /* idle the system by using the idle mode which will wait for an
205 * interrupt to happen before restarting the system. 205 * interrupt to happen before restarting the system.
206 */ 206 */
207 207
208 /* Warning: going into idle state upsets jtag scanning */ 208 /* Warning: going into idle state upsets jtag scanning */
209 209
210 __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE, 210 __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
211 S3C2410_CLKCON); 211 S3C2410_CLKCON);
212 212
213 /* the samsung port seems to do a loop and then unset idle.. */ 213 /* the samsung port seems to do a loop and then unset idle.. */
214 for (i = 0; i < 50; i++) 214 for (i = 0; i < 50; i++)
215 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */ 215 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
216 216
217 /* this bit is not cleared on re-start... */ 217 /* this bit is not cleared on re-start... */
218 218
219 __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE, 219 __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
220 S3C2410_CLKCON); 220 S3C2410_CLKCON);
221 } 221 }
222 222
223 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) 223 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
224 { 224 {
225 arm_pm_idle = s3c24xx_default_idle; 225 arm_pm_idle = s3c24xx_default_idle;
226 226
227 /* initialise the io descriptors we need for initialisation */ 227 /* initialise the io descriptors we need for initialisation */
228 iotable_init(mach_desc, size); 228 iotable_init(mach_desc, size);
229 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); 229 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
230 230
231 if (cpu_architecture() >= CPU_ARCH_ARMv5) { 231 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
232 samsung_cpu_id = s3c24xx_read_idcode_v5(); 232 samsung_cpu_id = s3c24xx_read_idcode_v5();
233 } else { 233 } else {
234 samsung_cpu_id = s3c24xx_read_idcode_v4(); 234 samsung_cpu_id = s3c24xx_read_idcode_v4();
235 } 235 }
236 s3c24xx_init_cpu(); 236 s3c24xx_init_cpu();
237 237
238 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); 238 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
239 } 239 }
240 240
241 /* Serial port registrations */ 241 /* Serial port registrations */
242 242
243 static struct resource s3c2410_uart0_resource[] = { 243 static struct resource s3c2410_uart0_resource[] = {
244 [0] = { 244 [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
245 .start = S3C2410_PA_UART0, 245 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
246 .end = S3C2410_PA_UART0 + 0x3fff, 246 IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
247 .flags = IORESOURCE_MEM, 247 NULL, IORESOURCE_IRQ)
248 },
249 [1] = {
250 .start = IRQ_S3CUART_RX0,
251 .end = IRQ_S3CUART_ERR0,
252 .flags = IORESOURCE_IRQ,
253 }
254 }; 248 };
255 249
256 static struct resource s3c2410_uart1_resource[] = { 250 static struct resource s3c2410_uart1_resource[] = {
257 [0] = { 251 [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
258 .start = S3C2410_PA_UART1, 252 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
259 .end = S3C2410_PA_UART1 + 0x3fff, 253 IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
260 .flags = IORESOURCE_MEM, 254 NULL, IORESOURCE_IRQ)
261 },
262 [1] = {
263 .start = IRQ_S3CUART_RX1,
264 .end = IRQ_S3CUART_ERR1,
265 .flags = IORESOURCE_IRQ,
266 }
267 }; 255 };
268 256
269 static struct resource s3c2410_uart2_resource[] = { 257 static struct resource s3c2410_uart2_resource[] = {
270 [0] = { 258 [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
271 .start = S3C2410_PA_UART2, 259 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
272 .end = S3C2410_PA_UART2 + 0x3fff, 260 IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
273 .flags = IORESOURCE_MEM, 261 NULL, IORESOURCE_IRQ)
274 },
275 [1] = {
276 .start = IRQ_S3CUART_RX2,
277 .end = IRQ_S3CUART_ERR2,
278 .flags = IORESOURCE_IRQ,
279 }
280 }; 262 };
281 263
282 static struct resource s3c2410_uart3_resource[] = { 264 static struct resource s3c2410_uart3_resource[] = {
283 [0] = { 265 [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
284 .start = S3C2443_PA_UART3, 266 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
285 .end = S3C2443_PA_UART3 + 0x3fff, 267 IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
286 .flags = IORESOURCE_MEM, 268 NULL, IORESOURCE_IRQ)
287 },
288 [1] = {
289 .start = IRQ_S3CUART_RX3,
290 .end = IRQ_S3CUART_ERR3,
291 .flags = IORESOURCE_IRQ,
292 },
293 }; 269 };
294 270
295 struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { 271 struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
296 [0] = { 272 [0] = {
297 .resources = s3c2410_uart0_resource, 273 .resources = s3c2410_uart0_resource,
298 .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource), 274 .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
299 }, 275 },
300 [1] = { 276 [1] = {
301 .resources = s3c2410_uart1_resource, 277 .resources = s3c2410_uart1_resource,
302 .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource), 278 .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
303 }, 279 },
304 [2] = { 280 [2] = {
305 .resources = s3c2410_uart2_resource, 281 .resources = s3c2410_uart2_resource,
306 .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), 282 .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
307 }, 283 },
308 [3] = { 284 [3] = {
309 .resources = s3c2410_uart3_resource, 285 .resources = s3c2410_uart3_resource,
310 .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource), 286 .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
311 }, 287 },
312 }; 288 };
313 289
314 /* initialise all the clocks */ 290 /* initialise all the clocks */
315 291
316 void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, 292 void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
317 unsigned long hclk, 293 unsigned long hclk,
318 unsigned long pclk) 294 unsigned long pclk)
319 { 295 {
320 clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), 296 clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
321 clk_xtal.rate); 297 clk_xtal.rate);
322 298
323 clk_mpll.rate = fclk; 299 clk_mpll.rate = fclk;
324 clk_h.rate = hclk; 300 clk_h.rate = hclk;
325 clk_p.rate = pclk; 301 clk_p.rate = pclk;
326 clk_f.rate = fclk; 302 clk_f.rate = fclk;
327 } 303 }
328 304