Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit 9dd90c5db0401061009183e6407feff3724ebc8b

Authored by Rhyland Klein
Committed by Mark Brown
1 parent 5f1cba63a3
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

ASoC: max98095: add jack detection 

This change adds the logic to support using the jack detect mechanism built
in to the codec to detect both when a jack was inserted and what type of
jack is present.

This change also supports the use of an external mechanism for headphone
detection. If this mechanism exists, when the max98095_jack_detect function
is called, the hp_jack is simply passed NULL.

This change supports both simple headphones, powered headphones, microphones
and headsets with both headphones and a mic.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

Showing 3 changed files with 191 additions and 1 deletions Inline Diff

include/sound/max98095.h
Diff comments   View file @ 9dd90c5
1 /* 1 /*
2 * Platform data for MAX98095 2 * Platform data for MAX98095
3 * 3 *
4 * Copyright 2011 Maxim Integrated Products 4 * Copyright 2011 Maxim Integrated Products
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your 8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version. 9 * option) any later version.
10 * 10 *
11 */ 11 */
12 12
13 #ifndef __SOUND_MAX98095_PDATA_H__ 13 #ifndef __SOUND_MAX98095_PDATA_H__
14 #define __SOUND_MAX98095_PDATA_H__ 14 #define __SOUND_MAX98095_PDATA_H__
15 15
16 /* Equalizer filter response configuration */ 16 /* Equalizer filter response configuration */
17 struct max98095_eq_cfg { 17 struct max98095_eq_cfg {
18 const char *name; 18 const char *name;
19 unsigned int rate; 19 unsigned int rate;
20 u16 band1[5]; 20 u16 band1[5];
21 u16 band2[5]; 21 u16 band2[5];
22 u16 band3[5]; 22 u16 band3[5];
23 u16 band4[5]; 23 u16 band4[5];
24 u16 band5[5]; 24 u16 band5[5];
25 }; 25 };
26 26
27 /* Biquad filter response configuration */ 27 /* Biquad filter response configuration */
28 struct max98095_biquad_cfg { 28 struct max98095_biquad_cfg {
29 const char *name; 29 const char *name;
30 unsigned int rate; 30 unsigned int rate;
31 u16 band1[5]; 31 u16 band1[5];
32 u16 band2[5]; 32 u16 band2[5];
33 }; 33 };
34 34
35 /* codec platform data */ 35 /* codec platform data */
36 struct max98095_pdata { 36 struct max98095_pdata {
37 37
38 /* Equalizers for DAI1 and DAI2 */ 38 /* Equalizers for DAI1 and DAI2 */
39 struct max98095_eq_cfg *eq_cfg; 39 struct max98095_eq_cfg *eq_cfg;
40 unsigned int eq_cfgcnt; 40 unsigned int eq_cfgcnt;
41 41
42 /* Biquad filter for DAI1 and DAI2 */ 42 /* Biquad filter for DAI1 and DAI2 */
43 struct max98095_biquad_cfg *bq_cfg; 43 struct max98095_biquad_cfg *bq_cfg;
44 unsigned int bq_cfgcnt; 44 unsigned int bq_cfgcnt;
45 45
46 /* Analog/digital microphone configuration: 46 /* Analog/digital microphone configuration:
47 * 0 = analog microphone input (normal setting) 47 * 0 = analog microphone input (normal setting)
48 * 1 = digital microphone input 48 * 1 = digital microphone input
49 */ 49 */
50 unsigned int digmic_left_mode:1; 50 unsigned int digmic_left_mode:1;
51 unsigned int digmic_right_mode:1; 51 unsigned int digmic_right_mode:1;
52
53 /* Pin5 is the mechanical method of sensing jack insertion
54 * but it is something that might not be supported.
55 * 0 = PIN5 not supported
56 * 1 = PIN5 supported
57 */
58 int jack_detect_pin5en:1;
59
60 /* Slew amount for jack detection. Calculated as 4 * (delay + 1).
61 * Default delay is 24 to get a time of 100ms.
62 */
63 unsigned int jack_detect_delay;
52 }; 64 };
53 65
54 #endif 66 #endif
55 67
sound/soc/codecs/max98095.c
Diff comments   View file @ 9dd90c5
1 /* 1 /*
2 * max98095.c -- MAX98095 ALSA SoC Audio driver 2 * max98095.c -- MAX98095 ALSA SoC Audio driver
3 * 3 *
4 * Copyright 2011 Maxim Integrated Products 4 * Copyright 2011 Maxim Integrated Products
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11 #include <linux/module.h> 11 #include <linux/module.h>
12 #include <linux/moduleparam.h> 12 #include <linux/moduleparam.h>
13 #include <linux/kernel.h> 13 #include <linux/kernel.h>
14 #include <linux/init.h> 14 #include <linux/init.h>
15 #include <linux/delay.h> 15 #include <linux/delay.h>
16 #include <linux/pm.h> 16 #include <linux/pm.h>
17 #include <linux/i2c.h> 17 #include <linux/i2c.h>
18 #include <sound/core.h> 18 #include <sound/core.h>
19 #include <sound/pcm.h> 19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h> 20 #include <sound/pcm_params.h>
21 #include <sound/soc.h> 21 #include <sound/soc.h>
22 #include <sound/initval.h> 22 #include <sound/initval.h>
23 #include <sound/tlv.h> 23 #include <sound/tlv.h>
24 #include <linux/slab.h> 24 #include <linux/slab.h>
25 #include <asm/div64.h> 25 #include <asm/div64.h>
26 #include <sound/max98095.h> 26 #include <sound/max98095.h>
27 #include <sound/jack.h>
27 #include "max98095.h" 28 #include "max98095.h"
28 29
29 enum max98095_type { 30 enum max98095_type {
30 MAX98095, 31 MAX98095,
31 }; 32 };
32 33
33 struct max98095_cdata { 34 struct max98095_cdata {
34 unsigned int rate; 35 unsigned int rate;
35 unsigned int fmt; 36 unsigned int fmt;
36 int eq_sel; 37 int eq_sel;
37 int bq_sel; 38 int bq_sel;
38 }; 39 };
39 40
40 struct max98095_priv { 41 struct max98095_priv {
41 enum max98095_type devtype; 42 enum max98095_type devtype;
42 struct max98095_pdata *pdata; 43 struct max98095_pdata *pdata;
43 unsigned int sysclk; 44 unsigned int sysclk;
44 struct max98095_cdata dai[3]; 45 struct max98095_cdata dai[3];
45 const char **eq_texts; 46 const char **eq_texts;
46 const char **bq_texts; 47 const char **bq_texts;
47 struct soc_enum eq_enum; 48 struct soc_enum eq_enum;
48 struct soc_enum bq_enum; 49 struct soc_enum bq_enum;
49 int eq_textcnt; 50 int eq_textcnt;
50 int bq_textcnt; 51 int bq_textcnt;
51 u8 lin_state; 52 u8 lin_state;
52 unsigned int mic1pre; 53 unsigned int mic1pre;
53 unsigned int mic2pre; 54 unsigned int mic2pre;
55 struct snd_soc_jack *headphone_jack;
56 struct snd_soc_jack *mic_jack;
54 }; 57 };
55 58
56 static const u8 max98095_reg_def[M98095_REG_CNT] = { 59 static const u8 max98095_reg_def[M98095_REG_CNT] = {
57 0x00, /* 00 */ 60 0x00, /* 00 */
58 0x00, /* 01 */ 61 0x00, /* 01 */
59 0x00, /* 02 */ 62 0x00, /* 02 */
60 0x00, /* 03 */ 63 0x00, /* 03 */
61 0x00, /* 04 */ 64 0x00, /* 04 */
62 0x00, /* 05 */ 65 0x00, /* 05 */
63 0x00, /* 06 */ 66 0x00, /* 06 */
64 0x00, /* 07 */ 67 0x00, /* 07 */
65 0x00, /* 08 */ 68 0x00, /* 08 */
66 0x00, /* 09 */ 69 0x00, /* 09 */
67 0x00, /* 0A */ 70 0x00, /* 0A */
68 0x00, /* 0B */ 71 0x00, /* 0B */
69 0x00, /* 0C */ 72 0x00, /* 0C */
70 0x00, /* 0D */ 73 0x00, /* 0D */
71 0x00, /* 0E */ 74 0x00, /* 0E */
72 0x00, /* 0F */ 75 0x00, /* 0F */
73 0x00, /* 10 */ 76 0x00, /* 10 */
74 0x00, /* 11 */ 77 0x00, /* 11 */
75 0x00, /* 12 */ 78 0x00, /* 12 */
76 0x00, /* 13 */ 79 0x00, /* 13 */
77 0x00, /* 14 */ 80 0x00, /* 14 */
78 0x00, /* 15 */ 81 0x00, /* 15 */
79 0x00, /* 16 */ 82 0x00, /* 16 */
80 0x00, /* 17 */ 83 0x00, /* 17 */
81 0x00, /* 18 */ 84 0x00, /* 18 */
82 0x00, /* 19 */ 85 0x00, /* 19 */
83 0x00, /* 1A */ 86 0x00, /* 1A */
84 0x00, /* 1B */ 87 0x00, /* 1B */
85 0x00, /* 1C */ 88 0x00, /* 1C */
86 0x00, /* 1D */ 89 0x00, /* 1D */
87 0x00, /* 1E */ 90 0x00, /* 1E */
88 0x00, /* 1F */ 91 0x00, /* 1F */
89 0x00, /* 20 */ 92 0x00, /* 20 */
90 0x00, /* 21 */ 93 0x00, /* 21 */
91 0x00, /* 22 */ 94 0x00, /* 22 */
92 0x00, /* 23 */ 95 0x00, /* 23 */
93 0x00, /* 24 */ 96 0x00, /* 24 */
94 0x00, /* 25 */ 97 0x00, /* 25 */
95 0x00, /* 26 */ 98 0x00, /* 26 */
96 0x00, /* 27 */ 99 0x00, /* 27 */
97 0x00, /* 28 */ 100 0x00, /* 28 */
98 0x00, /* 29 */ 101 0x00, /* 29 */
99 0x00, /* 2A */ 102 0x00, /* 2A */
100 0x00, /* 2B */ 103 0x00, /* 2B */
101 0x00, /* 2C */ 104 0x00, /* 2C */
102 0x00, /* 2D */ 105 0x00, /* 2D */
103 0x00, /* 2E */ 106 0x00, /* 2E */
104 0x00, /* 2F */ 107 0x00, /* 2F */
105 0x00, /* 30 */ 108 0x00, /* 30 */
106 0x00, /* 31 */ 109 0x00, /* 31 */
107 0x00, /* 32 */ 110 0x00, /* 32 */
108 0x00, /* 33 */ 111 0x00, /* 33 */
109 0x00, /* 34 */ 112 0x00, /* 34 */
110 0x00, /* 35 */ 113 0x00, /* 35 */
111 0x00, /* 36 */ 114 0x00, /* 36 */
112 0x00, /* 37 */ 115 0x00, /* 37 */
113 0x00, /* 38 */ 116 0x00, /* 38 */
114 0x00, /* 39 */ 117 0x00, /* 39 */
115 0x00, /* 3A */ 118 0x00, /* 3A */
116 0x00, /* 3B */ 119 0x00, /* 3B */
117 0x00, /* 3C */ 120 0x00, /* 3C */
118 0x00, /* 3D */ 121 0x00, /* 3D */
119 0x00, /* 3E */ 122 0x00, /* 3E */
120 0x00, /* 3F */ 123 0x00, /* 3F */
121 0x00, /* 40 */ 124 0x00, /* 40 */
122 0x00, /* 41 */ 125 0x00, /* 41 */
123 0x00, /* 42 */ 126 0x00, /* 42 */
124 0x00, /* 43 */ 127 0x00, /* 43 */
125 0x00, /* 44 */ 128 0x00, /* 44 */
126 0x00, /* 45 */ 129 0x00, /* 45 */
127 0x00, /* 46 */ 130 0x00, /* 46 */
128 0x00, /* 47 */ 131 0x00, /* 47 */
129 0x00, /* 48 */ 132 0x00, /* 48 */
130 0x00, /* 49 */ 133 0x00, /* 49 */
131 0x00, /* 4A */ 134 0x00, /* 4A */
132 0x00, /* 4B */ 135 0x00, /* 4B */
133 0x00, /* 4C */ 136 0x00, /* 4C */
134 0x00, /* 4D */ 137 0x00, /* 4D */
135 0x00, /* 4E */ 138 0x00, /* 4E */
136 0x00, /* 4F */ 139 0x00, /* 4F */
137 0x00, /* 50 */ 140 0x00, /* 50 */
138 0x00, /* 51 */ 141 0x00, /* 51 */
139 0x00, /* 52 */ 142 0x00, /* 52 */
140 0x00, /* 53 */ 143 0x00, /* 53 */
141 0x00, /* 54 */ 144 0x00, /* 54 */
142 0x00, /* 55 */ 145 0x00, /* 55 */
143 0x00, /* 56 */ 146 0x00, /* 56 */
144 0x00, /* 57 */ 147 0x00, /* 57 */
145 0x00, /* 58 */ 148 0x00, /* 58 */
146 0x00, /* 59 */ 149 0x00, /* 59 */
147 0x00, /* 5A */ 150 0x00, /* 5A */
148 0x00, /* 5B */ 151 0x00, /* 5B */
149 0x00, /* 5C */ 152 0x00, /* 5C */
150 0x00, /* 5D */ 153 0x00, /* 5D */
151 0x00, /* 5E */ 154 0x00, /* 5E */
152 0x00, /* 5F */ 155 0x00, /* 5F */
153 0x00, /* 60 */ 156 0x00, /* 60 */
154 0x00, /* 61 */ 157 0x00, /* 61 */
155 0x00, /* 62 */ 158 0x00, /* 62 */
156 0x00, /* 63 */ 159 0x00, /* 63 */
157 0x00, /* 64 */ 160 0x00, /* 64 */
158 0x00, /* 65 */ 161 0x00, /* 65 */
159 0x00, /* 66 */ 162 0x00, /* 66 */
160 0x00, /* 67 */ 163 0x00, /* 67 */
161 0x00, /* 68 */ 164 0x00, /* 68 */
162 0x00, /* 69 */ 165 0x00, /* 69 */
163 0x00, /* 6A */ 166 0x00, /* 6A */
164 0x00, /* 6B */ 167 0x00, /* 6B */
165 0x00, /* 6C */ 168 0x00, /* 6C */
166 0x00, /* 6D */ 169 0x00, /* 6D */
167 0x00, /* 6E */ 170 0x00, /* 6E */
168 0x00, /* 6F */ 171 0x00, /* 6F */
169 0x00, /* 70 */ 172 0x00, /* 70 */
170 0x00, /* 71 */ 173 0x00, /* 71 */
171 0x00, /* 72 */ 174 0x00, /* 72 */
172 0x00, /* 73 */ 175 0x00, /* 73 */
173 0x00, /* 74 */ 176 0x00, /* 74 */
174 0x00, /* 75 */ 177 0x00, /* 75 */
175 0x00, /* 76 */ 178 0x00, /* 76 */
176 0x00, /* 77 */ 179 0x00, /* 77 */
177 0x00, /* 78 */ 180 0x00, /* 78 */
178 0x00, /* 79 */ 181 0x00, /* 79 */
179 0x00, /* 7A */ 182 0x00, /* 7A */
180 0x00, /* 7B */ 183 0x00, /* 7B */
181 0x00, /* 7C */ 184 0x00, /* 7C */
182 0x00, /* 7D */ 185 0x00, /* 7D */
183 0x00, /* 7E */ 186 0x00, /* 7E */
184 0x00, /* 7F */ 187 0x00, /* 7F */
185 0x00, /* 80 */ 188 0x00, /* 80 */
186 0x00, /* 81 */ 189 0x00, /* 81 */
187 0x00, /* 82 */ 190 0x00, /* 82 */
188 0x00, /* 83 */ 191 0x00, /* 83 */
189 0x00, /* 84 */ 192 0x00, /* 84 */
190 0x00, /* 85 */ 193 0x00, /* 85 */
191 0x00, /* 86 */ 194 0x00, /* 86 */
192 0x00, /* 87 */ 195 0x00, /* 87 */
193 0x00, /* 88 */ 196 0x00, /* 88 */
194 0x00, /* 89 */ 197 0x00, /* 89 */
195 0x00, /* 8A */ 198 0x00, /* 8A */
196 0x00, /* 8B */ 199 0x00, /* 8B */
197 0x00, /* 8C */ 200 0x00, /* 8C */
198 0x00, /* 8D */ 201 0x00, /* 8D */
199 0x00, /* 8E */ 202 0x00, /* 8E */
200 0x00, /* 8F */ 203 0x00, /* 8F */
201 0x00, /* 90 */ 204 0x00, /* 90 */
202 0x00, /* 91 */ 205 0x00, /* 91 */
203 0x30, /* 92 */ 206 0x30, /* 92 */
204 0xF0, /* 93 */ 207 0xF0, /* 93 */
205 0x00, /* 94 */ 208 0x00, /* 94 */
206 0x00, /* 95 */ 209 0x00, /* 95 */
207 0x3F, /* 96 */ 210 0x3F, /* 96 */
208 0x00, /* 97 */ 211 0x00, /* 97 */
209 0x00, /* 98 */ 212 0x00, /* 98 */
210 0x00, /* 99 */ 213 0x00, /* 99 */
211 0x00, /* 9A */ 214 0x00, /* 9A */
212 0x00, /* 9B */ 215 0x00, /* 9B */
213 0x00, /* 9C */ 216 0x00, /* 9C */
214 0x00, /* 9D */ 217 0x00, /* 9D */
215 0x00, /* 9E */ 218 0x00, /* 9E */
216 0x00, /* 9F */ 219 0x00, /* 9F */
217 0x00, /* A0 */ 220 0x00, /* A0 */
218 0x00, /* A1 */ 221 0x00, /* A1 */
219 0x00, /* A2 */ 222 0x00, /* A2 */
220 0x00, /* A3 */ 223 0x00, /* A3 */
221 0x00, /* A4 */ 224 0x00, /* A4 */
222 0x00, /* A5 */ 225 0x00, /* A5 */
223 0x00, /* A6 */ 226 0x00, /* A6 */
224 0x00, /* A7 */ 227 0x00, /* A7 */
225 0x00, /* A8 */ 228 0x00, /* A8 */
226 0x00, /* A9 */ 229 0x00, /* A9 */
227 0x00, /* AA */ 230 0x00, /* AA */
228 0x00, /* AB */ 231 0x00, /* AB */
229 0x00, /* AC */ 232 0x00, /* AC */
230 0x00, /* AD */ 233 0x00, /* AD */
231 0x00, /* AE */ 234 0x00, /* AE */
232 0x00, /* AF */ 235 0x00, /* AF */
233 0x00, /* B0 */ 236 0x00, /* B0 */
234 0x00, /* B1 */ 237 0x00, /* B1 */
235 0x00, /* B2 */ 238 0x00, /* B2 */
236 0x00, /* B3 */ 239 0x00, /* B3 */
237 0x00, /* B4 */ 240 0x00, /* B4 */
238 0x00, /* B5 */ 241 0x00, /* B5 */
239 0x00, /* B6 */ 242 0x00, /* B6 */
240 0x00, /* B7 */ 243 0x00, /* B7 */
241 0x00, /* B8 */ 244 0x00, /* B8 */
242 0x00, /* B9 */ 245 0x00, /* B9 */
243 0x00, /* BA */ 246 0x00, /* BA */
244 0x00, /* BB */ 247 0x00, /* BB */
245 0x00, /* BC */ 248 0x00, /* BC */
246 0x00, /* BD */ 249 0x00, /* BD */
247 0x00, /* BE */ 250 0x00, /* BE */
248 0x00, /* BF */ 251 0x00, /* BF */
249 0x00, /* C0 */ 252 0x00, /* C0 */
250 0x00, /* C1 */ 253 0x00, /* C1 */
251 0x00, /* C2 */ 254 0x00, /* C2 */
252 0x00, /* C3 */ 255 0x00, /* C3 */
253 0x00, /* C4 */ 256 0x00, /* C4 */
254 0x00, /* C5 */ 257 0x00, /* C5 */
255 0x00, /* C6 */ 258 0x00, /* C6 */
256 0x00, /* C7 */ 259 0x00, /* C7 */
257 0x00, /* C8 */ 260 0x00, /* C8 */
258 0x00, /* C9 */ 261 0x00, /* C9 */
259 0x00, /* CA */ 262 0x00, /* CA */
260 0x00, /* CB */ 263 0x00, /* CB */
261 0x00, /* CC */ 264 0x00, /* CC */
262 0x00, /* CD */ 265 0x00, /* CD */
263 0x00, /* CE */ 266 0x00, /* CE */
264 0x00, /* CF */ 267 0x00, /* CF */
265 0x00, /* D0 */ 268 0x00, /* D0 */
266 0x00, /* D1 */ 269 0x00, /* D1 */
267 0x00, /* D2 */ 270 0x00, /* D2 */
268 0x00, /* D3 */ 271 0x00, /* D3 */
269 0x00, /* D4 */ 272 0x00, /* D4 */
270 0x00, /* D5 */ 273 0x00, /* D5 */
271 0x00, /* D6 */ 274 0x00, /* D6 */
272 0x00, /* D7 */ 275 0x00, /* D7 */
273 0x00, /* D8 */ 276 0x00, /* D8 */
274 0x00, /* D9 */ 277 0x00, /* D9 */
275 0x00, /* DA */ 278 0x00, /* DA */
276 0x00, /* DB */ 279 0x00, /* DB */
277 0x00, /* DC */ 280 0x00, /* DC */
278 0x00, /* DD */ 281 0x00, /* DD */
279 0x00, /* DE */ 282 0x00, /* DE */
280 0x00, /* DF */ 283 0x00, /* DF */
281 0x00, /* E0 */ 284 0x00, /* E0 */
282 0x00, /* E1 */ 285 0x00, /* E1 */
283 0x00, /* E2 */ 286 0x00, /* E2 */
284 0x00, /* E3 */ 287 0x00, /* E3 */
285 0x00, /* E4 */ 288 0x00, /* E4 */
286 0x00, /* E5 */ 289 0x00, /* E5 */
287 0x00, /* E6 */ 290 0x00, /* E6 */
288 0x00, /* E7 */ 291 0x00, /* E7 */
289 0x00, /* E8 */ 292 0x00, /* E8 */
290 0x00, /* E9 */ 293 0x00, /* E9 */
291 0x00, /* EA */ 294 0x00, /* EA */
292 0x00, /* EB */ 295 0x00, /* EB */
293 0x00, /* EC */ 296 0x00, /* EC */
294 0x00, /* ED */ 297 0x00, /* ED */
295 0x00, /* EE */ 298 0x00, /* EE */
296 0x00, /* EF */ 299 0x00, /* EF */
297 0x00, /* F0 */ 300 0x00, /* F0 */
298 0x00, /* F1 */ 301 0x00, /* F1 */
299 0x00, /* F2 */ 302 0x00, /* F2 */
300 0x00, /* F3 */ 303 0x00, /* F3 */
301 0x00, /* F4 */ 304 0x00, /* F4 */
302 0x00, /* F5 */ 305 0x00, /* F5 */
303 0x00, /* F6 */ 306 0x00, /* F6 */
304 0x00, /* F7 */ 307 0x00, /* F7 */
305 0x00, /* F8 */ 308 0x00, /* F8 */
306 0x00, /* F9 */ 309 0x00, /* F9 */
307 0x00, /* FA */ 310 0x00, /* FA */
308 0x00, /* FB */ 311 0x00, /* FB */
309 0x00, /* FC */ 312 0x00, /* FC */
310 0x00, /* FD */ 313 0x00, /* FD */
311 0x00, /* FE */ 314 0x00, /* FE */
312 0x00, /* FF */ 315 0x00, /* FF */
313 }; 316 };
314 317
315 static struct { 318 static struct {
316 int readable; 319 int readable;
317 int writable; 320 int writable;
318 } max98095_access[M98095_REG_CNT] = { 321 } max98095_access[M98095_REG_CNT] = {
319 { 0x00, 0x00 }, /* 00 */ 322 { 0x00, 0x00 }, /* 00 */
320 { 0xFF, 0x00 }, /* 01 */ 323 { 0xFF, 0x00 }, /* 01 */
321 { 0xFF, 0x00 }, /* 02 */ 324 { 0xFF, 0x00 }, /* 02 */
322 { 0xFF, 0x00 }, /* 03 */ 325 { 0xFF, 0x00 }, /* 03 */
323 { 0xFF, 0x00 }, /* 04 */ 326 { 0xFF, 0x00 }, /* 04 */
324 { 0xFF, 0x00 }, /* 05 */ 327 { 0xFF, 0x00 }, /* 05 */
325 { 0xFF, 0x00 }, /* 06 */ 328 { 0xFF, 0x00 }, /* 06 */
326 { 0xFF, 0x00 }, /* 07 */ 329 { 0xFF, 0x00 }, /* 07 */
327 { 0xFF, 0x00 }, /* 08 */ 330 { 0xFF, 0x00 }, /* 08 */
328 { 0xFF, 0x00 }, /* 09 */ 331 { 0xFF, 0x00 }, /* 09 */
329 { 0xFF, 0x00 }, /* 0A */ 332 { 0xFF, 0x00 }, /* 0A */
330 { 0xFF, 0x00 }, /* 0B */ 333 { 0xFF, 0x00 }, /* 0B */
331 { 0xFF, 0x00 }, /* 0C */ 334 { 0xFF, 0x00 }, /* 0C */
332 { 0xFF, 0x00 }, /* 0D */ 335 { 0xFF, 0x00 }, /* 0D */
333 { 0xFF, 0x00 }, /* 0E */ 336 { 0xFF, 0x00 }, /* 0E */
334 { 0xFF, 0x9F }, /* 0F */ 337 { 0xFF, 0x9F }, /* 0F */
335 { 0xFF, 0xFF }, /* 10 */ 338 { 0xFF, 0xFF }, /* 10 */
336 { 0xFF, 0xFF }, /* 11 */ 339 { 0xFF, 0xFF }, /* 11 */
337 { 0xFF, 0xFF }, /* 12 */ 340 { 0xFF, 0xFF }, /* 12 */
338 { 0xFF, 0xFF }, /* 13 */ 341 { 0xFF, 0xFF }, /* 13 */
339 { 0xFF, 0xFF }, /* 14 */ 342 { 0xFF, 0xFF }, /* 14 */
340 { 0xFF, 0xFF }, /* 15 */ 343 { 0xFF, 0xFF }, /* 15 */
341 { 0xFF, 0xFF }, /* 16 */ 344 { 0xFF, 0xFF }, /* 16 */
342 { 0xFF, 0xFF }, /* 17 */ 345 { 0xFF, 0xFF }, /* 17 */
343 { 0xFF, 0xFF }, /* 18 */ 346 { 0xFF, 0xFF }, /* 18 */
344 { 0xFF, 0xFF }, /* 19 */ 347 { 0xFF, 0xFF }, /* 19 */
345 { 0xFF, 0xFF }, /* 1A */ 348 { 0xFF, 0xFF }, /* 1A */
346 { 0xFF, 0xFF }, /* 1B */ 349 { 0xFF, 0xFF }, /* 1B */
347 { 0xFF, 0xFF }, /* 1C */ 350 { 0xFF, 0xFF }, /* 1C */
348 { 0xFF, 0xFF }, /* 1D */ 351 { 0xFF, 0xFF }, /* 1D */
349 { 0xFF, 0x77 }, /* 1E */ 352 { 0xFF, 0x77 }, /* 1E */
350 { 0xFF, 0x77 }, /* 1F */ 353 { 0xFF, 0x77 }, /* 1F */
351 { 0xFF, 0x77 }, /* 20 */ 354 { 0xFF, 0x77 }, /* 20 */
352 { 0xFF, 0x77 }, /* 21 */ 355 { 0xFF, 0x77 }, /* 21 */
353 { 0xFF, 0x77 }, /* 22 */ 356 { 0xFF, 0x77 }, /* 22 */
354 { 0xFF, 0x77 }, /* 23 */ 357 { 0xFF, 0x77 }, /* 23 */
355 { 0xFF, 0xFF }, /* 24 */ 358 { 0xFF, 0xFF }, /* 24 */
356 { 0xFF, 0x7F }, /* 25 */ 359 { 0xFF, 0x7F }, /* 25 */
357 { 0xFF, 0x31 }, /* 26 */ 360 { 0xFF, 0x31 }, /* 26 */
358 { 0xFF, 0xFF }, /* 27 */ 361 { 0xFF, 0xFF }, /* 27 */
359 { 0xFF, 0xFF }, /* 28 */ 362 { 0xFF, 0xFF }, /* 28 */
360 { 0xFF, 0xFF }, /* 29 */ 363 { 0xFF, 0xFF }, /* 29 */
361 { 0xFF, 0xF7 }, /* 2A */ 364 { 0xFF, 0xF7 }, /* 2A */
362 { 0xFF, 0x2F }, /* 2B */ 365 { 0xFF, 0x2F }, /* 2B */
363 { 0xFF, 0xEF }, /* 2C */ 366 { 0xFF, 0xEF }, /* 2C */
364 { 0xFF, 0xFF }, /* 2D */ 367 { 0xFF, 0xFF }, /* 2D */
365 { 0xFF, 0xFF }, /* 2E */ 368 { 0xFF, 0xFF }, /* 2E */
366 { 0xFF, 0xFF }, /* 2F */ 369 { 0xFF, 0xFF }, /* 2F */
367 { 0xFF, 0xFF }, /* 30 */ 370 { 0xFF, 0xFF }, /* 30 */
368 { 0xFF, 0xFF }, /* 31 */ 371 { 0xFF, 0xFF }, /* 31 */
369 { 0xFF, 0xFF }, /* 32 */ 372 { 0xFF, 0xFF }, /* 32 */
370 { 0xFF, 0xFF }, /* 33 */ 373 { 0xFF, 0xFF }, /* 33 */
371 { 0xFF, 0xF7 }, /* 34 */ 374 { 0xFF, 0xF7 }, /* 34 */
372 { 0xFF, 0x2F }, /* 35 */ 375 { 0xFF, 0x2F }, /* 35 */
373 { 0xFF, 0xCF }, /* 36 */ 376 { 0xFF, 0xCF }, /* 36 */
374 { 0xFF, 0xFF }, /* 37 */ 377 { 0xFF, 0xFF }, /* 37 */
375 { 0xFF, 0xFF }, /* 38 */ 378 { 0xFF, 0xFF }, /* 38 */
376 { 0xFF, 0xFF }, /* 39 */ 379 { 0xFF, 0xFF }, /* 39 */
377 { 0xFF, 0xFF }, /* 3A */ 380 { 0xFF, 0xFF }, /* 3A */
378 { 0xFF, 0xFF }, /* 3B */ 381 { 0xFF, 0xFF }, /* 3B */
379 { 0xFF, 0xFF }, /* 3C */ 382 { 0xFF, 0xFF }, /* 3C */
380 { 0xFF, 0xFF }, /* 3D */ 383 { 0xFF, 0xFF }, /* 3D */
381 { 0xFF, 0xF7 }, /* 3E */ 384 { 0xFF, 0xF7 }, /* 3E */
382 { 0xFF, 0x2F }, /* 3F */ 385 { 0xFF, 0x2F }, /* 3F */
383 { 0xFF, 0xCF }, /* 40 */ 386 { 0xFF, 0xCF }, /* 40 */
384 { 0xFF, 0xFF }, /* 41 */ 387 { 0xFF, 0xFF }, /* 41 */
385 { 0xFF, 0x77 }, /* 42 */ 388 { 0xFF, 0x77 }, /* 42 */
386 { 0xFF, 0xFF }, /* 43 */ 389 { 0xFF, 0xFF }, /* 43 */
387 { 0xFF, 0xFF }, /* 44 */ 390 { 0xFF, 0xFF }, /* 44 */
388 { 0xFF, 0xFF }, /* 45 */ 391 { 0xFF, 0xFF }, /* 45 */
389 { 0xFF, 0xFF }, /* 46 */ 392 { 0xFF, 0xFF }, /* 46 */
390 { 0xFF, 0xFF }, /* 47 */ 393 { 0xFF, 0xFF }, /* 47 */
391 { 0xFF, 0xFF }, /* 48 */ 394 { 0xFF, 0xFF }, /* 48 */
392 { 0xFF, 0x0F }, /* 49 */ 395 { 0xFF, 0x0F }, /* 49 */
393 { 0xFF, 0xFF }, /* 4A */ 396 { 0xFF, 0xFF }, /* 4A */
394 { 0xFF, 0xFF }, /* 4B */ 397 { 0xFF, 0xFF }, /* 4B */
395 { 0xFF, 0x3F }, /* 4C */ 398 { 0xFF, 0x3F }, /* 4C */
396 { 0xFF, 0x3F }, /* 4D */ 399 { 0xFF, 0x3F }, /* 4D */
397 { 0xFF, 0x3F }, /* 4E */ 400 { 0xFF, 0x3F }, /* 4E */
398 { 0xFF, 0xFF }, /* 4F */ 401 { 0xFF, 0xFF }, /* 4F */
399 { 0xFF, 0x7F }, /* 50 */ 402 { 0xFF, 0x7F }, /* 50 */
400 { 0xFF, 0x7F }, /* 51 */ 403 { 0xFF, 0x7F }, /* 51 */
401 { 0xFF, 0x0F }, /* 52 */ 404 { 0xFF, 0x0F }, /* 52 */
402 { 0xFF, 0x3F }, /* 53 */ 405 { 0xFF, 0x3F }, /* 53 */
403 { 0xFF, 0x3F }, /* 54 */ 406 { 0xFF, 0x3F }, /* 54 */
404 { 0xFF, 0x3F }, /* 55 */ 407 { 0xFF, 0x3F }, /* 55 */
405 { 0xFF, 0xFF }, /* 56 */ 408 { 0xFF, 0xFF }, /* 56 */
406 { 0xFF, 0xFF }, /* 57 */ 409 { 0xFF, 0xFF }, /* 57 */
407 { 0xFF, 0xBF }, /* 58 */ 410 { 0xFF, 0xBF }, /* 58 */
408 { 0xFF, 0x1F }, /* 59 */ 411 { 0xFF, 0x1F }, /* 59 */
409 { 0xFF, 0xBF }, /* 5A */ 412 { 0xFF, 0xBF }, /* 5A */
410 { 0xFF, 0x1F }, /* 5B */ 413 { 0xFF, 0x1F }, /* 5B */
411 { 0xFF, 0xBF }, /* 5C */ 414 { 0xFF, 0xBF }, /* 5C */
412 { 0xFF, 0x3F }, /* 5D */ 415 { 0xFF, 0x3F }, /* 5D */
413 { 0xFF, 0x3F }, /* 5E */ 416 { 0xFF, 0x3F }, /* 5E */
414 { 0xFF, 0x7F }, /* 5F */ 417 { 0xFF, 0x7F }, /* 5F */
415 { 0xFF, 0x7F }, /* 60 */ 418 { 0xFF, 0x7F }, /* 60 */
416 { 0xFF, 0x47 }, /* 61 */ 419 { 0xFF, 0x47 }, /* 61 */
417 { 0xFF, 0x9F }, /* 62 */ 420 { 0xFF, 0x9F }, /* 62 */
418 { 0xFF, 0x9F }, /* 63 */ 421 { 0xFF, 0x9F }, /* 63 */
419 { 0xFF, 0x9F }, /* 64 */ 422 { 0xFF, 0x9F }, /* 64 */
420 { 0xFF, 0x9F }, /* 65 */ 423 { 0xFF, 0x9F }, /* 65 */
421 { 0xFF, 0x9F }, /* 66 */ 424 { 0xFF, 0x9F }, /* 66 */
422 { 0xFF, 0xBF }, /* 67 */ 425 { 0xFF, 0xBF }, /* 67 */
423 { 0xFF, 0xBF }, /* 68 */ 426 { 0xFF, 0xBF }, /* 68 */
424 { 0xFF, 0xFF }, /* 69 */ 427 { 0xFF, 0xFF }, /* 69 */
425 { 0xFF, 0xFF }, /* 6A */ 428 { 0xFF, 0xFF }, /* 6A */
426 { 0xFF, 0x7F }, /* 6B */ 429 { 0xFF, 0x7F }, /* 6B */
427 { 0xFF, 0xF7 }, /* 6C */ 430 { 0xFF, 0xF7 }, /* 6C */
428 { 0xFF, 0xFF }, /* 6D */ 431 { 0xFF, 0xFF }, /* 6D */
429 { 0xFF, 0xFF }, /* 6E */ 432 { 0xFF, 0xFF }, /* 6E */
430 { 0xFF, 0x1F }, /* 6F */ 433 { 0xFF, 0x1F }, /* 6F */
431 { 0xFF, 0xF7 }, /* 70 */ 434 { 0xFF, 0xF7 }, /* 70 */
432 { 0xFF, 0xFF }, /* 71 */ 435 { 0xFF, 0xFF }, /* 71 */
433 { 0xFF, 0xFF }, /* 72 */ 436 { 0xFF, 0xFF }, /* 72 */
434 { 0xFF, 0x1F }, /* 73 */ 437 { 0xFF, 0x1F }, /* 73 */
435 { 0xFF, 0xF7 }, /* 74 */ 438 { 0xFF, 0xF7 }, /* 74 */
436 { 0xFF, 0xFF }, /* 75 */ 439 { 0xFF, 0xFF }, /* 75 */
437 { 0xFF, 0xFF }, /* 76 */ 440 { 0xFF, 0xFF }, /* 76 */
438 { 0xFF, 0x1F }, /* 77 */ 441 { 0xFF, 0x1F }, /* 77 */
439 { 0xFF, 0xF7 }, /* 78 */ 442 { 0xFF, 0xF7 }, /* 78 */
440 { 0xFF, 0xFF }, /* 79 */ 443 { 0xFF, 0xFF }, /* 79 */
441 { 0xFF, 0xFF }, /* 7A */ 444 { 0xFF, 0xFF }, /* 7A */
442 { 0xFF, 0x1F }, /* 7B */ 445 { 0xFF, 0x1F }, /* 7B */
443 { 0xFF, 0xF7 }, /* 7C */ 446 { 0xFF, 0xF7 }, /* 7C */
444 { 0xFF, 0xFF }, /* 7D */ 447 { 0xFF, 0xFF }, /* 7D */
445 { 0xFF, 0xFF }, /* 7E */ 448 { 0xFF, 0xFF }, /* 7E */
446 { 0xFF, 0x1F }, /* 7F */ 449 { 0xFF, 0x1F }, /* 7F */
447 { 0xFF, 0xF7 }, /* 80 */ 450 { 0xFF, 0xF7 }, /* 80 */
448 { 0xFF, 0xFF }, /* 81 */ 451 { 0xFF, 0xFF }, /* 81 */
449 { 0xFF, 0xFF }, /* 82 */ 452 { 0xFF, 0xFF }, /* 82 */
450 { 0xFF, 0x1F }, /* 83 */ 453 { 0xFF, 0x1F }, /* 83 */
451 { 0xFF, 0x7F }, /* 84 */ 454 { 0xFF, 0x7F }, /* 84 */
452 { 0xFF, 0x0F }, /* 85 */ 455 { 0xFF, 0x0F }, /* 85 */
453 { 0xFF, 0xD8 }, /* 86 */ 456 { 0xFF, 0xD8 }, /* 86 */
454 { 0xFF, 0xFF }, /* 87 */ 457 { 0xFF, 0xFF }, /* 87 */
455 { 0xFF, 0xEF }, /* 88 */ 458 { 0xFF, 0xEF }, /* 88 */
456 { 0xFF, 0xFE }, /* 89 */ 459 { 0xFF, 0xFE }, /* 89 */
457 { 0xFF, 0xFE }, /* 8A */ 460 { 0xFF, 0xFE }, /* 8A */
458 { 0xFF, 0xFF }, /* 8B */ 461 { 0xFF, 0xFF }, /* 8B */
459 { 0xFF, 0xFF }, /* 8C */ 462 { 0xFF, 0xFF }, /* 8C */
460 { 0xFF, 0x3F }, /* 8D */ 463 { 0xFF, 0x3F }, /* 8D */
461 { 0xFF, 0xFF }, /* 8E */ 464 { 0xFF, 0xFF }, /* 8E */
462 { 0xFF, 0x3F }, /* 8F */ 465 { 0xFF, 0x3F }, /* 8F */
463 { 0xFF, 0x8F }, /* 90 */ 466 { 0xFF, 0x8F }, /* 90 */
464 { 0xFF, 0xFF }, /* 91 */ 467 { 0xFF, 0xFF }, /* 91 */
465 { 0xFF, 0x3F }, /* 92 */ 468 { 0xFF, 0x3F }, /* 92 */
466 { 0xFF, 0xFF }, /* 93 */ 469 { 0xFF, 0xFF }, /* 93 */
467 { 0xFF, 0xFF }, /* 94 */ 470 { 0xFF, 0xFF }, /* 94 */
468 { 0xFF, 0x0F }, /* 95 */ 471 { 0xFF, 0x0F }, /* 95 */
469 { 0xFF, 0x3F }, /* 96 */ 472 { 0xFF, 0x3F }, /* 96 */
470 { 0xFF, 0x8C }, /* 97 */ 473 { 0xFF, 0x8C }, /* 97 */
471 { 0x00, 0x00 }, /* 98 */ 474 { 0x00, 0x00 }, /* 98 */
472 { 0x00, 0x00 }, /* 99 */ 475 { 0x00, 0x00 }, /* 99 */
473 { 0x00, 0x00 }, /* 9A */ 476 { 0x00, 0x00 }, /* 9A */
474 { 0x00, 0x00 }, /* 9B */ 477 { 0x00, 0x00 }, /* 9B */
475 { 0x00, 0x00 }, /* 9C */ 478 { 0x00, 0x00 }, /* 9C */
476 { 0x00, 0x00 }, /* 9D */ 479 { 0x00, 0x00 }, /* 9D */
477 { 0x00, 0x00 }, /* 9E */ 480 { 0x00, 0x00 }, /* 9E */
478 { 0x00, 0x00 }, /* 9F */ 481 { 0x00, 0x00 }, /* 9F */
479 { 0x00, 0x00 }, /* A0 */ 482 { 0x00, 0x00 }, /* A0 */
480 { 0x00, 0x00 }, /* A1 */ 483 { 0x00, 0x00 }, /* A1 */
481 { 0x00, 0x00 }, /* A2 */ 484 { 0x00, 0x00 }, /* A2 */
482 { 0x00, 0x00 }, /* A3 */ 485 { 0x00, 0x00 }, /* A3 */
483 { 0x00, 0x00 }, /* A4 */ 486 { 0x00, 0x00 }, /* A4 */
484 { 0x00, 0x00 }, /* A5 */ 487 { 0x00, 0x00 }, /* A5 */
485 { 0x00, 0x00 }, /* A6 */ 488 { 0x00, 0x00 }, /* A6 */
486 { 0x00, 0x00 }, /* A7 */ 489 { 0x00, 0x00 }, /* A7 */
487 { 0x00, 0x00 }, /* A8 */ 490 { 0x00, 0x00 }, /* A8 */
488 { 0x00, 0x00 }, /* A9 */ 491 { 0x00, 0x00 }, /* A9 */
489 { 0x00, 0x00 }, /* AA */ 492 { 0x00, 0x00 }, /* AA */
490 { 0x00, 0x00 }, /* AB */ 493 { 0x00, 0x00 }, /* AB */
491 { 0x00, 0x00 }, /* AC */ 494 { 0x00, 0x00 }, /* AC */
492 { 0x00, 0x00 }, /* AD */ 495 { 0x00, 0x00 }, /* AD */
493 { 0x00, 0x00 }, /* AE */ 496 { 0x00, 0x00 }, /* AE */
494 { 0x00, 0x00 }, /* AF */ 497 { 0x00, 0x00 }, /* AF */
495 { 0x00, 0x00 }, /* B0 */ 498 { 0x00, 0x00 }, /* B0 */
496 { 0x00, 0x00 }, /* B1 */ 499 { 0x00, 0x00 }, /* B1 */
497 { 0x00, 0x00 }, /* B2 */ 500 { 0x00, 0x00 }, /* B2 */
498 { 0x00, 0x00 }, /* B3 */ 501 { 0x00, 0x00 }, /* B3 */
499 { 0x00, 0x00 }, /* B4 */ 502 { 0x00, 0x00 }, /* B4 */
500 { 0x00, 0x00 }, /* B5 */ 503 { 0x00, 0x00 }, /* B5 */
501 { 0x00, 0x00 }, /* B6 */ 504 { 0x00, 0x00 }, /* B6 */
502 { 0x00, 0x00 }, /* B7 */ 505 { 0x00, 0x00 }, /* B7 */
503 { 0x00, 0x00 }, /* B8 */ 506 { 0x00, 0x00 }, /* B8 */
504 { 0x00, 0x00 }, /* B9 */ 507 { 0x00, 0x00 }, /* B9 */
505 { 0x00, 0x00 }, /* BA */ 508 { 0x00, 0x00 }, /* BA */
506 { 0x00, 0x00 }, /* BB */ 509 { 0x00, 0x00 }, /* BB */
507 { 0x00, 0x00 }, /* BC */ 510 { 0x00, 0x00 }, /* BC */
508 { 0x00, 0x00 }, /* BD */ 511 { 0x00, 0x00 }, /* BD */
509 { 0x00, 0x00 }, /* BE */ 512 { 0x00, 0x00 }, /* BE */
510 { 0x00, 0x00 }, /* BF */ 513 { 0x00, 0x00 }, /* BF */
511 { 0x00, 0x00 }, /* C0 */ 514 { 0x00, 0x00 }, /* C0 */
512 { 0x00, 0x00 }, /* C1 */ 515 { 0x00, 0x00 }, /* C1 */
513 { 0x00, 0x00 }, /* C2 */ 516 { 0x00, 0x00 }, /* C2 */
514 { 0x00, 0x00 }, /* C3 */ 517 { 0x00, 0x00 }, /* C3 */
515 { 0x00, 0x00 }, /* C4 */ 518 { 0x00, 0x00 }, /* C4 */
516 { 0x00, 0x00 }, /* C5 */ 519 { 0x00, 0x00 }, /* C5 */
517 { 0x00, 0x00 }, /* C6 */ 520 { 0x00, 0x00 }, /* C6 */
518 { 0x00, 0x00 }, /* C7 */ 521 { 0x00, 0x00 }, /* C7 */
519 { 0x00, 0x00 }, /* C8 */ 522 { 0x00, 0x00 }, /* C8 */
520 { 0x00, 0x00 }, /* C9 */ 523 { 0x00, 0x00 }, /* C9 */
521 { 0x00, 0x00 }, /* CA */ 524 { 0x00, 0x00 }, /* CA */
522 { 0x00, 0x00 }, /* CB */ 525 { 0x00, 0x00 }, /* CB */
523 { 0x00, 0x00 }, /* CC */ 526 { 0x00, 0x00 }, /* CC */
524 { 0x00, 0x00 }, /* CD */ 527 { 0x00, 0x00 }, /* CD */
525 { 0x00, 0x00 }, /* CE */ 528 { 0x00, 0x00 }, /* CE */
526 { 0x00, 0x00 }, /* CF */ 529 { 0x00, 0x00 }, /* CF */
527 { 0x00, 0x00 }, /* D0 */ 530 { 0x00, 0x00 }, /* D0 */
528 { 0x00, 0x00 }, /* D1 */ 531 { 0x00, 0x00 }, /* D1 */
529 { 0x00, 0x00 }, /* D2 */ 532 { 0x00, 0x00 }, /* D2 */
530 { 0x00, 0x00 }, /* D3 */ 533 { 0x00, 0x00 }, /* D3 */
531 { 0x00, 0x00 }, /* D4 */ 534 { 0x00, 0x00 }, /* D4 */
532 { 0x00, 0x00 }, /* D5 */ 535 { 0x00, 0x00 }, /* D5 */
533 { 0x00, 0x00 }, /* D6 */ 536 { 0x00, 0x00 }, /* D6 */
534 { 0x00, 0x00 }, /* D7 */ 537 { 0x00, 0x00 }, /* D7 */
535 { 0x00, 0x00 }, /* D8 */ 538 { 0x00, 0x00 }, /* D8 */
536 { 0x00, 0x00 }, /* D9 */ 539 { 0x00, 0x00 }, /* D9 */
537 { 0x00, 0x00 }, /* DA */ 540 { 0x00, 0x00 }, /* DA */
538 { 0x00, 0x00 }, /* DB */ 541 { 0x00, 0x00 }, /* DB */
539 { 0x00, 0x00 }, /* DC */ 542 { 0x00, 0x00 }, /* DC */
540 { 0x00, 0x00 }, /* DD */ 543 { 0x00, 0x00 }, /* DD */
541 { 0x00, 0x00 }, /* DE */ 544 { 0x00, 0x00 }, /* DE */
542 { 0x00, 0x00 }, /* DF */ 545 { 0x00, 0x00 }, /* DF */
543 { 0x00, 0x00 }, /* E0 */ 546 { 0x00, 0x00 }, /* E0 */
544 { 0x00, 0x00 }, /* E1 */ 547 { 0x00, 0x00 }, /* E1 */
545 { 0x00, 0x00 }, /* E2 */ 548 { 0x00, 0x00 }, /* E2 */
546 { 0x00, 0x00 }, /* E3 */ 549 { 0x00, 0x00 }, /* E3 */
547 { 0x00, 0x00 }, /* E4 */ 550 { 0x00, 0x00 }, /* E4 */
548 { 0x00, 0x00 }, /* E5 */ 551 { 0x00, 0x00 }, /* E5 */
549 { 0x00, 0x00 }, /* E6 */ 552 { 0x00, 0x00 }, /* E6 */
550 { 0x00, 0x00 }, /* E7 */ 553 { 0x00, 0x00 }, /* E7 */
551 { 0x00, 0x00 }, /* E8 */ 554 { 0x00, 0x00 }, /* E8 */
552 { 0x00, 0x00 }, /* E9 */ 555 { 0x00, 0x00 }, /* E9 */
553 { 0x00, 0x00 }, /* EA */ 556 { 0x00, 0x00 }, /* EA */
554 { 0x00, 0x00 }, /* EB */ 557 { 0x00, 0x00 }, /* EB */
555 { 0x00, 0x00 }, /* EC */ 558 { 0x00, 0x00 }, /* EC */
556 { 0x00, 0x00 }, /* ED */ 559 { 0x00, 0x00 }, /* ED */
557 { 0x00, 0x00 }, /* EE */ 560 { 0x00, 0x00 }, /* EE */
558 { 0x00, 0x00 }, /* EF */ 561 { 0x00, 0x00 }, /* EF */
559 { 0x00, 0x00 }, /* F0 */ 562 { 0x00, 0x00 }, /* F0 */
560 { 0x00, 0x00 }, /* F1 */ 563 { 0x00, 0x00 }, /* F1 */
561 { 0x00, 0x00 }, /* F2 */ 564 { 0x00, 0x00 }, /* F2 */
562 { 0x00, 0x00 }, /* F3 */ 565 { 0x00, 0x00 }, /* F3 */
563 { 0x00, 0x00 }, /* F4 */ 566 { 0x00, 0x00 }, /* F4 */
564 { 0x00, 0x00 }, /* F5 */ 567 { 0x00, 0x00 }, /* F5 */
565 { 0x00, 0x00 }, /* F6 */ 568 { 0x00, 0x00 }, /* F6 */
566 { 0x00, 0x00 }, /* F7 */ 569 { 0x00, 0x00 }, /* F7 */
567 { 0x00, 0x00 }, /* F8 */ 570 { 0x00, 0x00 }, /* F8 */
568 { 0x00, 0x00 }, /* F9 */ 571 { 0x00, 0x00 }, /* F9 */
569 { 0x00, 0x00 }, /* FA */ 572 { 0x00, 0x00 }, /* FA */
570 { 0x00, 0x00 }, /* FB */ 573 { 0x00, 0x00 }, /* FB */
571 { 0x00, 0x00 }, /* FC */ 574 { 0x00, 0x00 }, /* FC */
572 { 0x00, 0x00 }, /* FD */ 575 { 0x00, 0x00 }, /* FD */
573 { 0x00, 0x00 }, /* FE */ 576 { 0x00, 0x00 }, /* FE */
574 { 0xFF, 0x00 }, /* FF */ 577 { 0xFF, 0x00 }, /* FF */
575 }; 578 };
576 579
577 static int max98095_readable(struct snd_soc_codec *codec, unsigned int reg) 580 static int max98095_readable(struct snd_soc_codec *codec, unsigned int reg)
578 { 581 {
579 if (reg >= M98095_REG_CNT) 582 if (reg >= M98095_REG_CNT)
580 return 0; 583 return 0;
581 return max98095_access[reg].readable != 0; 584 return max98095_access[reg].readable != 0;
582 } 585 }
583 586
584 static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg) 587 static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg)
585 { 588 {
586 if (reg > M98095_REG_MAX_CACHED) 589 if (reg > M98095_REG_MAX_CACHED)
587 return 1; 590 return 1;
588 591
589 switch (reg) { 592 switch (reg) {
590 case M98095_000_HOST_DATA: 593 case M98095_000_HOST_DATA:
591 case M98095_001_HOST_INT_STS: 594 case M98095_001_HOST_INT_STS:
592 case M98095_002_HOST_RSP_STS: 595 case M98095_002_HOST_RSP_STS:
593 case M98095_003_HOST_CMD_STS: 596 case M98095_003_HOST_CMD_STS:
594 case M98095_004_CODEC_STS: 597 case M98095_004_CODEC_STS:
595 case M98095_005_DAI1_ALC_STS: 598 case M98095_005_DAI1_ALC_STS:
596 case M98095_006_DAI2_ALC_STS: 599 case M98095_006_DAI2_ALC_STS:
597 case M98095_007_JACK_AUTO_STS: 600 case M98095_007_JACK_AUTO_STS:
598 case M98095_008_JACK_MANUAL_STS: 601 case M98095_008_JACK_MANUAL_STS:
599 case M98095_009_JACK_VBAT_STS: 602 case M98095_009_JACK_VBAT_STS:
600 case M98095_00A_ACC_ADC_STS: 603 case M98095_00A_ACC_ADC_STS:
601 case M98095_00B_MIC_NG_AGC_STS: 604 case M98095_00B_MIC_NG_AGC_STS:
602 case M98095_00C_SPK_L_VOLT_STS: 605 case M98095_00C_SPK_L_VOLT_STS:
603 case M98095_00D_SPK_R_VOLT_STS: 606 case M98095_00D_SPK_R_VOLT_STS:
604 case M98095_00E_TEMP_SENSOR_STS: 607 case M98095_00E_TEMP_SENSOR_STS:
605 return 1; 608 return 1;
606 } 609 }
607 610
608 return 0; 611 return 0;
609 } 612 }
610 613
611 /* 614 /*
612 * Filter coefficients are in a separate register segment 615 * Filter coefficients are in a separate register segment
613 * and they share the address space of the normal registers. 616 * and they share the address space of the normal registers.
614 * The coefficient registers do not need or share the cache. 617 * The coefficient registers do not need or share the cache.
615 */ 618 */
616 static int max98095_hw_write(struct snd_soc_codec *codec, unsigned int reg, 619 static int max98095_hw_write(struct snd_soc_codec *codec, unsigned int reg,
617 unsigned int value) 620 unsigned int value)
618 { 621 {
619 int ret; 622 int ret;
620 623
621 codec->cache_bypass = 1; 624 codec->cache_bypass = 1;
622 ret = snd_soc_write(codec, reg, value); 625 ret = snd_soc_write(codec, reg, value);
623 codec->cache_bypass = 0; 626 codec->cache_bypass = 0;
624 627
625 return ret ? -EIO : 0; 628 return ret ? -EIO : 0;
626 } 629 }
627 630
628 /* 631 /*
629 * Load equalizer DSP coefficient configurations registers 632 * Load equalizer DSP coefficient configurations registers
630 */ 633 */
631 static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai, 634 static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai,
632 unsigned int band, u16 *coefs) 635 unsigned int band, u16 *coefs)
633 { 636 {
634 unsigned int eq_reg; 637 unsigned int eq_reg;
635 unsigned int i; 638 unsigned int i;
636 639
637 BUG_ON(band > 4); 640 BUG_ON(band > 4);
638 BUG_ON(dai > 1); 641 BUG_ON(dai > 1);
639 642
640 /* Load the base register address */ 643 /* Load the base register address */
641 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE; 644 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
642 645
643 /* Add the band address offset, note adjustment for word address */ 646 /* Add the band address offset, note adjustment for word address */
644 eq_reg += band * (M98095_COEFS_PER_BAND << 1); 647 eq_reg += band * (M98095_COEFS_PER_BAND << 1);
645 648
646 /* Step through the registers and coefs */ 649 /* Step through the registers and coefs */
647 for (i = 0; i < M98095_COEFS_PER_BAND; i++) { 650 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
648 max98095_hw_write(codec, eq_reg++, M98095_BYTE1(coefs[i])); 651 max98095_hw_write(codec, eq_reg++, M98095_BYTE1(coefs[i]));
649 max98095_hw_write(codec, eq_reg++, M98095_BYTE0(coefs[i])); 652 max98095_hw_write(codec, eq_reg++, M98095_BYTE0(coefs[i]));
650 } 653 }
651 } 654 }
652 655
653 /* 656 /*
654 * Load biquad filter coefficient configurations registers 657 * Load biquad filter coefficient configurations registers
655 */ 658 */
656 static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai, 659 static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai,
657 unsigned int band, u16 *coefs) 660 unsigned int band, u16 *coefs)
658 { 661 {
659 unsigned int bq_reg; 662 unsigned int bq_reg;
660 unsigned int i; 663 unsigned int i;
661 664
662 BUG_ON(band > 1); 665 BUG_ON(band > 1);
663 BUG_ON(dai > 1); 666 BUG_ON(dai > 1);
664 667
665 /* Load the base register address */ 668 /* Load the base register address */
666 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE; 669 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
667 670
668 /* Add the band address offset, note adjustment for word address */ 671 /* Add the band address offset, note adjustment for word address */
669 bq_reg += band * (M98095_COEFS_PER_BAND << 1); 672 bq_reg += band * (M98095_COEFS_PER_BAND << 1);
670 673
671 /* Step through the registers and coefs */ 674 /* Step through the registers and coefs */
672 for (i = 0; i < M98095_COEFS_PER_BAND; i++) { 675 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
673 max98095_hw_write(codec, bq_reg++, M98095_BYTE1(coefs[i])); 676 max98095_hw_write(codec, bq_reg++, M98095_BYTE1(coefs[i]));
674 max98095_hw_write(codec, bq_reg++, M98095_BYTE0(coefs[i])); 677 max98095_hw_write(codec, bq_reg++, M98095_BYTE0(coefs[i]));
675 } 678 }
676 } 679 }
677 680
678 static const char * const max98095_fltr_mode[] = { "Voice", "Music" }; 681 static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
679 static const struct soc_enum max98095_dai1_filter_mode_enum[] = { 682 static const struct soc_enum max98095_dai1_filter_mode_enum[] = {
680 SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 7, 2, max98095_fltr_mode), 683 SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 7, 2, max98095_fltr_mode),
681 }; 684 };
682 static const struct soc_enum max98095_dai2_filter_mode_enum[] = { 685 static const struct soc_enum max98095_dai2_filter_mode_enum[] = {
683 SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 7, 2, max98095_fltr_mode), 686 SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 7, 2, max98095_fltr_mode),
684 }; 687 };
685 688
686 static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" }; 689 static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
687 690
688 static const struct soc_enum max98095_extmic_enum = 691 static const struct soc_enum max98095_extmic_enum =
689 SOC_ENUM_SINGLE(M98095_087_CFG_MIC, 0, 3, max98095_extmic_text); 692 SOC_ENUM_SINGLE(M98095_087_CFG_MIC, 0, 3, max98095_extmic_text);
690 693
691 static const struct snd_kcontrol_new max98095_extmic_mux = 694 static const struct snd_kcontrol_new max98095_extmic_mux =
692 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum); 695 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
693 696
694 static const char * const max98095_linein_text[] = { "INA", "INB" }; 697 static const char * const max98095_linein_text[] = { "INA", "INB" };
695 698
696 static const struct soc_enum max98095_linein_enum = 699 static const struct soc_enum max98095_linein_enum =
697 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 6, 2, max98095_linein_text); 700 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 6, 2, max98095_linein_text);
698 701
699 static const struct snd_kcontrol_new max98095_linein_mux = 702 static const struct snd_kcontrol_new max98095_linein_mux =
700 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum); 703 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
701 704
702 static const char * const max98095_line_mode_text[] = { 705 static const char * const max98095_line_mode_text[] = {
703 "Stereo", "Differential"}; 706 "Stereo", "Differential"};
704 707
705 static const struct soc_enum max98095_linein_mode_enum = 708 static const struct soc_enum max98095_linein_mode_enum =
706 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 7, 2, max98095_line_mode_text); 709 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 7, 2, max98095_line_mode_text);
707 710
708 static const struct soc_enum max98095_lineout_mode_enum = 711 static const struct soc_enum max98095_lineout_mode_enum =
709 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 4, 2, max98095_line_mode_text); 712 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 4, 2, max98095_line_mode_text);
710 713
711 static const char * const max98095_dai_fltr[] = { 714 static const char * const max98095_dai_fltr[] = {
712 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k", 715 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
713 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"}; 716 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
714 static const struct soc_enum max98095_dai1_dac_filter_enum[] = { 717 static const struct soc_enum max98095_dai1_dac_filter_enum[] = {
715 SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 0, 6, max98095_dai_fltr), 718 SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 0, 6, max98095_dai_fltr),
716 }; 719 };
717 static const struct soc_enum max98095_dai2_dac_filter_enum[] = { 720 static const struct soc_enum max98095_dai2_dac_filter_enum[] = {
718 SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 0, 6, max98095_dai_fltr), 721 SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 0, 6, max98095_dai_fltr),
719 }; 722 };
720 static const struct soc_enum max98095_dai3_dac_filter_enum[] = { 723 static const struct soc_enum max98095_dai3_dac_filter_enum[] = {
721 SOC_ENUM_SINGLE(M98095_042_DAI3_FILTERS, 0, 6, max98095_dai_fltr), 724 SOC_ENUM_SINGLE(M98095_042_DAI3_FILTERS, 0, 6, max98095_dai_fltr),
722 }; 725 };
723 726
724 static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol, 727 static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
725 struct snd_ctl_elem_value *ucontrol) 728 struct snd_ctl_elem_value *ucontrol)
726 { 729 {
727 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 730 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
728 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 731 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
729 unsigned int sel = ucontrol->value.integer.value[0]; 732 unsigned int sel = ucontrol->value.integer.value[0];
730 733
731 max98095->mic1pre = sel; 734 max98095->mic1pre = sel;
732 snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK, 735 snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
733 (1+sel)<<M98095_MICPRE_SHIFT); 736 (1+sel)<<M98095_MICPRE_SHIFT);
734 737
735 return 0; 738 return 0;
736 } 739 }
737 740
738 static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol, 741 static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
739 struct snd_ctl_elem_value *ucontrol) 742 struct snd_ctl_elem_value *ucontrol)
740 { 743 {
741 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 744 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
742 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 745 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
743 746
744 ucontrol->value.integer.value[0] = max98095->mic1pre; 747 ucontrol->value.integer.value[0] = max98095->mic1pre;
745 return 0; 748 return 0;
746 } 749 }
747 750
748 static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol, 751 static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
749 struct snd_ctl_elem_value *ucontrol) 752 struct snd_ctl_elem_value *ucontrol)
750 { 753 {
751 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 754 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
752 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 755 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
753 unsigned int sel = ucontrol->value.integer.value[0]; 756 unsigned int sel = ucontrol->value.integer.value[0];
754 757
755 max98095->mic2pre = sel; 758 max98095->mic2pre = sel;
756 snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK, 759 snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
757 (1+sel)<<M98095_MICPRE_SHIFT); 760 (1+sel)<<M98095_MICPRE_SHIFT);
758 761
759 return 0; 762 return 0;
760 } 763 }
761 764
762 static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol, 765 static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
763 struct snd_ctl_elem_value *ucontrol) 766 struct snd_ctl_elem_value *ucontrol)
764 { 767 {
765 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 768 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
766 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 769 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
767 770
768 ucontrol->value.integer.value[0] = max98095->mic2pre; 771 ucontrol->value.integer.value[0] = max98095->mic2pre;
769 return 0; 772 return 0;
770 } 773 }
771 774
772 static const unsigned int max98095_micboost_tlv[] = { 775 static const unsigned int max98095_micboost_tlv[] = {
773 TLV_DB_RANGE_HEAD(2), 776 TLV_DB_RANGE_HEAD(2),
774 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 777 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
775 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), 778 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
776 }; 779 };
777 780
778 static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0); 781 static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
779 static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0); 782 static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
780 static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0); 783 static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
781 784
782 static const unsigned int max98095_hp_tlv[] = { 785 static const unsigned int max98095_hp_tlv[] = {
783 TLV_DB_RANGE_HEAD(5), 786 TLV_DB_RANGE_HEAD(5),
784 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 787 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
785 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 788 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
786 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 789 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
787 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 790 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
788 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), 791 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
789 }; 792 };
790 793
791 static const unsigned int max98095_spk_tlv[] = { 794 static const unsigned int max98095_spk_tlv[] = {
792 TLV_DB_RANGE_HEAD(4), 795 TLV_DB_RANGE_HEAD(4),
793 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0), 796 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
794 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0), 797 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
795 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0), 798 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
796 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0), 799 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0),
797 }; 800 };
798 801
799 static const unsigned int max98095_rcv_lout_tlv[] = { 802 static const unsigned int max98095_rcv_lout_tlv[] = {
800 TLV_DB_RANGE_HEAD(5), 803 TLV_DB_RANGE_HEAD(5),
801 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 804 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
802 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 805 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
803 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 806 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
804 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 807 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
805 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), 808 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
806 }; 809 };
807 810
808 static const unsigned int max98095_lin_tlv[] = { 811 static const unsigned int max98095_lin_tlv[] = {
809 TLV_DB_RANGE_HEAD(3), 812 TLV_DB_RANGE_HEAD(3),
810 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0), 813 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
811 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0), 814 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
812 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), 815 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
813 }; 816 };
814 817
815 static const struct snd_kcontrol_new max98095_snd_controls[] = { 818 static const struct snd_kcontrol_new max98095_snd_controls[] = {
816 819
817 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L, 820 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
818 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv), 821 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
819 822
820 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L, 823 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
821 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv), 824 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
822 825
823 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV, 826 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
824 0, 31, 0, max98095_rcv_lout_tlv), 827 0, 31, 0, max98095_rcv_lout_tlv),
825 828
826 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1, 829 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
827 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv), 830 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
828 831
829 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L, 832 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
830 M98095_065_LVL_HP_R, 7, 1, 1), 833 M98095_065_LVL_HP_R, 7, 1, 1),
831 834
832 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L, 835 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
833 M98095_068_LVL_SPK_R, 7, 1, 1), 836 M98095_068_LVL_SPK_R, 7, 1, 1),
834 837
835 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1), 838 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
836 839
837 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1, 840 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
838 M98095_063_LVL_LINEOUT2, 7, 1, 1), 841 M98095_063_LVL_LINEOUT2, 7, 1, 1),
839 842
840 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1, 843 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
841 max98095_mic_tlv), 844 max98095_mic_tlv),
842 845
843 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1, 846 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
844 max98095_mic_tlv), 847 max98095_mic_tlv),
845 848
846 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 849 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
847 M98095_05F_LVL_MIC1, 5, 2, 0, 850 M98095_05F_LVL_MIC1, 5, 2, 0,
848 max98095_mic1pre_get, max98095_mic1pre_set, 851 max98095_mic1pre_get, max98095_mic1pre_set,
849 max98095_micboost_tlv), 852 max98095_micboost_tlv),
850 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 853 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
851 M98095_060_LVL_MIC2, 5, 2, 0, 854 M98095_060_LVL_MIC2, 5, 2, 0,
852 max98095_mic2pre_get, max98095_mic2pre_set, 855 max98095_mic2pre_get, max98095_mic2pre_set,
853 max98095_micboost_tlv), 856 max98095_micboost_tlv),
854 857
855 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1, 858 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
856 max98095_lin_tlv), 859 max98095_lin_tlv),
857 860
858 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1, 861 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
859 max98095_adc_tlv), 862 max98095_adc_tlv),
860 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1, 863 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
861 max98095_adc_tlv), 864 max98095_adc_tlv),
862 865
863 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0, 866 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
864 max98095_adcboost_tlv), 867 max98095_adcboost_tlv),
865 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0, 868 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
866 max98095_adcboost_tlv), 869 max98095_adcboost_tlv),
867 870
868 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0), 871 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
869 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0), 872 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
870 873
871 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0), 874 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
872 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0), 875 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
873 876
874 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum), 877 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
875 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum), 878 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
876 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum), 879 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
877 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum), 880 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
878 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum), 881 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
879 882
880 SOC_ENUM("Linein Mode", max98095_linein_mode_enum), 883 SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
881 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum), 884 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
882 }; 885 };
883 886
884 /* Left speaker mixer switch */ 887 /* Left speaker mixer switch */
885 static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = { 888 static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
886 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0), 889 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
887 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0), 890 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
888 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), 891 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
889 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), 892 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
890 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0), 893 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
891 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0), 894 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
892 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0), 895 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
893 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0), 896 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
894 }; 897 };
895 898
896 /* Right speaker mixer switch */ 899 /* Right speaker mixer switch */
897 static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = { 900 static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
898 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0), 901 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
899 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0), 902 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
900 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), 903 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
901 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), 904 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
902 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0), 905 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
903 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0), 906 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
904 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0), 907 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
905 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0), 908 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
906 }; 909 };
907 910
908 /* Left headphone mixer switch */ 911 /* Left headphone mixer switch */
909 static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = { 912 static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
910 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0), 913 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
911 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0), 914 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
912 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0), 915 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
913 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0), 916 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
914 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0), 917 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
915 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0), 918 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
916 }; 919 };
917 920
918 /* Right headphone mixer switch */ 921 /* Right headphone mixer switch */
919 static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = { 922 static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
920 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0), 923 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
921 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0), 924 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
922 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0), 925 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
923 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0), 926 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
924 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0), 927 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
925 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0), 928 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
926 }; 929 };
927 930
928 /* Receiver earpiece mixer switch */ 931 /* Receiver earpiece mixer switch */
929 static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = { 932 static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
930 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0), 933 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
931 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0), 934 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
932 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0), 935 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
933 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0), 936 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
934 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0), 937 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
935 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0), 938 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
936 }; 939 };
937 940
938 /* Left lineout mixer switch */ 941 /* Left lineout mixer switch */
939 static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = { 942 static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
940 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0), 943 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
941 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0), 944 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
942 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0), 945 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
943 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0), 946 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
944 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0), 947 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
945 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0), 948 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
946 }; 949 };
947 950
948 /* Right lineout mixer switch */ 951 /* Right lineout mixer switch */
949 static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = { 952 static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
950 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0), 953 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
951 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0), 954 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
952 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0), 955 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
953 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0), 956 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
954 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0), 957 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
955 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0), 958 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
956 }; 959 };
957 960
958 /* Left ADC mixer switch */ 961 /* Left ADC mixer switch */
959 static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = { 962 static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
960 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0), 963 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
961 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0), 964 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
962 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0), 965 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
963 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0), 966 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
964 }; 967 };
965 968
966 /* Right ADC mixer switch */ 969 /* Right ADC mixer switch */
967 static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = { 970 static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
968 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0), 971 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
969 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0), 972 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
970 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0), 973 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
971 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0), 974 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
972 }; 975 };
973 976
974 static int max98095_mic_event(struct snd_soc_dapm_widget *w, 977 static int max98095_mic_event(struct snd_soc_dapm_widget *w,
975 struct snd_kcontrol *kcontrol, int event) 978 struct snd_kcontrol *kcontrol, int event)
976 { 979 {
977 struct snd_soc_codec *codec = w->codec; 980 struct snd_soc_codec *codec = w->codec;
978 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 981 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
979 982
980 switch (event) { 983 switch (event) {
981 case SND_SOC_DAPM_POST_PMU: 984 case SND_SOC_DAPM_POST_PMU:
982 if (w->reg == M98095_05F_LVL_MIC1) { 985 if (w->reg == M98095_05F_LVL_MIC1) {
983 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 986 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
984 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT); 987 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
985 } else { 988 } else {
986 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 989 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
987 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT); 990 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
988 } 991 }
989 break; 992 break;
990 case SND_SOC_DAPM_POST_PMD: 993 case SND_SOC_DAPM_POST_PMD:
991 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0); 994 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0);
992 break; 995 break;
993 default: 996 default:
994 return -EINVAL; 997 return -EINVAL;
995 } 998 }
996 999
997 return 0; 1000 return 0;
998 } 1001 }
999 1002
1000 /* 1003 /*
1001 * The line inputs are stereo inputs with the left and right 1004 * The line inputs are stereo inputs with the left and right
1002 * channels sharing a common PGA power control signal. 1005 * channels sharing a common PGA power control signal.
1003 */ 1006 */
1004 static int max98095_line_pga(struct snd_soc_dapm_widget *w, 1007 static int max98095_line_pga(struct snd_soc_dapm_widget *w,
1005 int event, u8 channel) 1008 int event, u8 channel)
1006 { 1009 {
1007 struct snd_soc_codec *codec = w->codec; 1010 struct snd_soc_codec *codec = w->codec;
1008 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1011 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1009 u8 *state; 1012 u8 *state;
1010 1013
1011 BUG_ON(!((channel == 1) || (channel == 2))); 1014 BUG_ON(!((channel == 1) || (channel == 2)));
1012 1015
1013 state = &max98095->lin_state; 1016 state = &max98095->lin_state;
1014 1017
1015 switch (event) { 1018 switch (event) {
1016 case SND_SOC_DAPM_POST_PMU: 1019 case SND_SOC_DAPM_POST_PMU:
1017 *state |= channel; 1020 *state |= channel;
1018 snd_soc_update_bits(codec, w->reg, 1021 snd_soc_update_bits(codec, w->reg,
1019 (1 << w->shift), (1 << w->shift)); 1022 (1 << w->shift), (1 << w->shift));
1020 break; 1023 break;
1021 case SND_SOC_DAPM_POST_PMD: 1024 case SND_SOC_DAPM_POST_PMD:
1022 *state &= ~channel; 1025 *state &= ~channel;
1023 if (*state == 0) { 1026 if (*state == 0) {
1024 snd_soc_update_bits(codec, w->reg, 1027 snd_soc_update_bits(codec, w->reg,
1025 (1 << w->shift), 0); 1028 (1 << w->shift), 0);
1026 } 1029 }
1027 break; 1030 break;
1028 default: 1031 default:
1029 return -EINVAL; 1032 return -EINVAL;
1030 } 1033 }
1031 1034
1032 return 0; 1035 return 0;
1033 } 1036 }
1034 1037
1035 static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w, 1038 static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
1036 struct snd_kcontrol *k, int event) 1039 struct snd_kcontrol *k, int event)
1037 { 1040 {
1038 return max98095_line_pga(w, event, 1); 1041 return max98095_line_pga(w, event, 1);
1039 } 1042 }
1040 1043
1041 static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w, 1044 static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
1042 struct snd_kcontrol *k, int event) 1045 struct snd_kcontrol *k, int event)
1043 { 1046 {
1044 return max98095_line_pga(w, event, 2); 1047 return max98095_line_pga(w, event, 2);
1045 } 1048 }
1046 1049
1047 /* 1050 /*
1048 * The stereo line out mixer outputs to two stereo line outs. 1051 * The stereo line out mixer outputs to two stereo line outs.
1049 * The 2nd pair has a separate set of enables. 1052 * The 2nd pair has a separate set of enables.
1050 */ 1053 */
1051 static int max98095_lineout_event(struct snd_soc_dapm_widget *w, 1054 static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
1052 struct snd_kcontrol *kcontrol, int event) 1055 struct snd_kcontrol *kcontrol, int event)
1053 { 1056 {
1054 struct snd_soc_codec *codec = w->codec; 1057 struct snd_soc_codec *codec = w->codec;
1055 1058
1056 switch (event) { 1059 switch (event) {
1057 case SND_SOC_DAPM_POST_PMU: 1060 case SND_SOC_DAPM_POST_PMU:
1058 snd_soc_update_bits(codec, w->reg, 1061 snd_soc_update_bits(codec, w->reg,
1059 (1 << (w->shift+2)), (1 << (w->shift+2))); 1062 (1 << (w->shift+2)), (1 << (w->shift+2)));
1060 break; 1063 break;
1061 case SND_SOC_DAPM_POST_PMD: 1064 case SND_SOC_DAPM_POST_PMD:
1062 snd_soc_update_bits(codec, w->reg, 1065 snd_soc_update_bits(codec, w->reg,
1063 (1 << (w->shift+2)), 0); 1066 (1 << (w->shift+2)), 0);
1064 break; 1067 break;
1065 default: 1068 default:
1066 return -EINVAL; 1069 return -EINVAL;
1067 } 1070 }
1068 1071
1069 return 0; 1072 return 0;
1070 } 1073 }
1071 1074
1072 static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = { 1075 static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
1073 1076
1074 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0), 1077 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
1075 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0), 1078 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
1076 1079
1077 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", 1080 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
1078 M98095_091_PWR_EN_OUT, 0, 0), 1081 M98095_091_PWR_EN_OUT, 0, 0),
1079 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", 1082 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
1080 M98095_091_PWR_EN_OUT, 1, 0), 1083 M98095_091_PWR_EN_OUT, 1, 0),
1081 SND_SOC_DAPM_DAC("DACM2", "Aux Playback", 1084 SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
1082 M98095_091_PWR_EN_OUT, 2, 0), 1085 M98095_091_PWR_EN_OUT, 2, 0),
1083 SND_SOC_DAPM_DAC("DACM3", "Voice Playback", 1086 SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
1084 M98095_091_PWR_EN_OUT, 2, 0), 1087 M98095_091_PWR_EN_OUT, 2, 0),
1085 1088
1086 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT, 1089 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
1087 6, 0, NULL, 0), 1090 6, 0, NULL, 0),
1088 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT, 1091 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
1089 7, 0, NULL, 0), 1092 7, 0, NULL, 0),
1090 1093
1091 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT, 1094 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
1092 4, 0, NULL, 0), 1095 4, 0, NULL, 0),
1093 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT, 1096 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
1094 5, 0, NULL, 0), 1097 5, 0, NULL, 0),
1095 1098
1096 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT, 1099 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
1097 3, 0, NULL, 0), 1100 3, 0, NULL, 0),
1098 1101
1099 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT, 1102 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
1100 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), 1103 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
1101 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT, 1104 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
1102 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), 1105 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
1103 1106
1104 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, 1107 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
1105 &max98095_extmic_mux), 1108 &max98095_extmic_mux),
1106 1109
1107 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0, 1110 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
1108 &max98095_linein_mux), 1111 &max98095_linein_mux),
1109 1112
1110 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 1113 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1111 &max98095_left_hp_mixer_controls[0], 1114 &max98095_left_hp_mixer_controls[0],
1112 ARRAY_SIZE(max98095_left_hp_mixer_controls)), 1115 ARRAY_SIZE(max98095_left_hp_mixer_controls)),
1113 1116
1114 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 1117 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1115 &max98095_right_hp_mixer_controls[0], 1118 &max98095_right_hp_mixer_controls[0],
1116 ARRAY_SIZE(max98095_right_hp_mixer_controls)), 1119 ARRAY_SIZE(max98095_right_hp_mixer_controls)),
1117 1120
1118 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 1121 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1119 &max98095_left_speaker_mixer_controls[0], 1122 &max98095_left_speaker_mixer_controls[0],
1120 ARRAY_SIZE(max98095_left_speaker_mixer_controls)), 1123 ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
1121 1124
1122 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 1125 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1123 &max98095_right_speaker_mixer_controls[0], 1126 &max98095_right_speaker_mixer_controls[0],
1124 ARRAY_SIZE(max98095_right_speaker_mixer_controls)), 1127 ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
1125 1128
1126 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0, 1129 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
1127 &max98095_mono_rcv_mixer_controls[0], 1130 &max98095_mono_rcv_mixer_controls[0],
1128 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)), 1131 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
1129 1132
1130 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0, 1133 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
1131 &max98095_left_lineout_mixer_controls[0], 1134 &max98095_left_lineout_mixer_controls[0],
1132 ARRAY_SIZE(max98095_left_lineout_mixer_controls)), 1135 ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
1133 1136
1134 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0, 1137 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
1135 &max98095_right_lineout_mixer_controls[0], 1138 &max98095_right_lineout_mixer_controls[0],
1136 ARRAY_SIZE(max98095_right_lineout_mixer_controls)), 1139 ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
1137 1140
1138 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1141 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1139 &max98095_left_ADC_mixer_controls[0], 1142 &max98095_left_ADC_mixer_controls[0],
1140 ARRAY_SIZE(max98095_left_ADC_mixer_controls)), 1143 ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
1141 1144
1142 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1145 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1143 &max98095_right_ADC_mixer_controls[0], 1146 &max98095_right_ADC_mixer_controls[0],
1144 ARRAY_SIZE(max98095_right_ADC_mixer_controls)), 1147 ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
1145 1148
1146 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1, 1149 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
1147 5, 0, NULL, 0, max98095_mic_event, 1150 5, 0, NULL, 0, max98095_mic_event,
1148 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1151 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1149 1152
1150 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2, 1153 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
1151 5, 0, NULL, 0, max98095_mic_event, 1154 5, 0, NULL, 0, max98095_mic_event,
1152 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1155 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1153 1156
1154 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN, 1157 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
1155 7, 0, NULL, 0, max98095_pga_in1_event, 1158 7, 0, NULL, 0, max98095_pga_in1_event,
1156 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1159 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1157 1160
1158 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN, 1161 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
1159 7, 0, NULL, 0, max98095_pga_in2_event, 1162 7, 0, NULL, 0, max98095_pga_in2_event,
1160 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1163 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1161 1164
1162 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0), 1165 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
1163 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0), 1166 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
1164 1167
1165 SND_SOC_DAPM_OUTPUT("HPL"), 1168 SND_SOC_DAPM_OUTPUT("HPL"),
1166 SND_SOC_DAPM_OUTPUT("HPR"), 1169 SND_SOC_DAPM_OUTPUT("HPR"),
1167 SND_SOC_DAPM_OUTPUT("SPKL"), 1170 SND_SOC_DAPM_OUTPUT("SPKL"),
1168 SND_SOC_DAPM_OUTPUT("SPKR"), 1171 SND_SOC_DAPM_OUTPUT("SPKR"),
1169 SND_SOC_DAPM_OUTPUT("RCV"), 1172 SND_SOC_DAPM_OUTPUT("RCV"),
1170 SND_SOC_DAPM_OUTPUT("OUT1"), 1173 SND_SOC_DAPM_OUTPUT("OUT1"),
1171 SND_SOC_DAPM_OUTPUT("OUT2"), 1174 SND_SOC_DAPM_OUTPUT("OUT2"),
1172 SND_SOC_DAPM_OUTPUT("OUT3"), 1175 SND_SOC_DAPM_OUTPUT("OUT3"),
1173 SND_SOC_DAPM_OUTPUT("OUT4"), 1176 SND_SOC_DAPM_OUTPUT("OUT4"),
1174 1177
1175 SND_SOC_DAPM_INPUT("MIC1"), 1178 SND_SOC_DAPM_INPUT("MIC1"),
1176 SND_SOC_DAPM_INPUT("MIC2"), 1179 SND_SOC_DAPM_INPUT("MIC2"),
1177 SND_SOC_DAPM_INPUT("INA1"), 1180 SND_SOC_DAPM_INPUT("INA1"),
1178 SND_SOC_DAPM_INPUT("INA2"), 1181 SND_SOC_DAPM_INPUT("INA2"),
1179 SND_SOC_DAPM_INPUT("INB1"), 1182 SND_SOC_DAPM_INPUT("INB1"),
1180 SND_SOC_DAPM_INPUT("INB2"), 1183 SND_SOC_DAPM_INPUT("INB2"),
1181 }; 1184 };
1182 1185
1183 static const struct snd_soc_dapm_route max98095_audio_map[] = { 1186 static const struct snd_soc_dapm_route max98095_audio_map[] = {
1184 /* Left headphone output mixer */ 1187 /* Left headphone output mixer */
1185 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"}, 1188 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
1186 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"}, 1189 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
1187 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1190 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1188 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1191 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1189 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"}, 1192 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
1190 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"}, 1193 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
1191 1194
1192 /* Right headphone output mixer */ 1195 /* Right headphone output mixer */
1193 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"}, 1196 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
1194 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"}, 1197 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
1195 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1198 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1196 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1199 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1197 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"}, 1200 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
1198 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"}, 1201 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
1199 1202
1200 /* Left speaker output mixer */ 1203 /* Left speaker output mixer */
1201 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"}, 1204 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
1202 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"}, 1205 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
1203 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, 1206 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
1204 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, 1207 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
1205 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1208 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1206 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1209 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1207 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"}, 1210 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
1208 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"}, 1211 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
1209 1212
1210 /* Right speaker output mixer */ 1213 /* Right speaker output mixer */
1211 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"}, 1214 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
1212 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"}, 1215 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
1213 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, 1216 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
1214 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, 1217 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
1215 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1218 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1216 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1219 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1217 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"}, 1220 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
1218 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"}, 1221 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
1219 1222
1220 /* Earpiece/Receiver output mixer */ 1223 /* Earpiece/Receiver output mixer */
1221 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"}, 1224 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
1222 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"}, 1225 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
1223 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1226 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1224 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1227 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1225 {"Receiver Mixer", "IN1 Switch", "IN1 Input"}, 1228 {"Receiver Mixer", "IN1 Switch", "IN1 Input"},
1226 {"Receiver Mixer", "IN2 Switch", "IN2 Input"}, 1229 {"Receiver Mixer", "IN2 Switch", "IN2 Input"},
1227 1230
1228 /* Left Lineout output mixer */ 1231 /* Left Lineout output mixer */
1229 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"}, 1232 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
1230 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"}, 1233 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
1231 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, 1234 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
1232 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, 1235 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
1233 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"}, 1236 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
1234 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"}, 1237 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
1235 1238
1236 /* Right lineout output mixer */ 1239 /* Right lineout output mixer */
1237 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"}, 1240 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
1238 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"}, 1241 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
1239 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, 1242 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
1240 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, 1243 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
1241 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"}, 1244 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
1242 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"}, 1245 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
1243 1246
1244 {"HP Left Out", NULL, "Left Headphone Mixer"}, 1247 {"HP Left Out", NULL, "Left Headphone Mixer"},
1245 {"HP Right Out", NULL, "Right Headphone Mixer"}, 1248 {"HP Right Out", NULL, "Right Headphone Mixer"},
1246 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 1249 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1247 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 1250 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1248 {"RCV Mono Out", NULL, "Receiver Mixer"}, 1251 {"RCV Mono Out", NULL, "Receiver Mixer"},
1249 {"LINE Left Out", NULL, "Left Lineout Mixer"}, 1252 {"LINE Left Out", NULL, "Left Lineout Mixer"},
1250 {"LINE Right Out", NULL, "Right Lineout Mixer"}, 1253 {"LINE Right Out", NULL, "Right Lineout Mixer"},
1251 1254
1252 {"HPL", NULL, "HP Left Out"}, 1255 {"HPL", NULL, "HP Left Out"},
1253 {"HPR", NULL, "HP Right Out"}, 1256 {"HPR", NULL, "HP Right Out"},
1254 {"SPKL", NULL, "SPK Left Out"}, 1257 {"SPKL", NULL, "SPK Left Out"},
1255 {"SPKR", NULL, "SPK Right Out"}, 1258 {"SPKR", NULL, "SPK Right Out"},
1256 {"RCV", NULL, "RCV Mono Out"}, 1259 {"RCV", NULL, "RCV Mono Out"},
1257 {"OUT1", NULL, "LINE Left Out"}, 1260 {"OUT1", NULL, "LINE Left Out"},
1258 {"OUT2", NULL, "LINE Right Out"}, 1261 {"OUT2", NULL, "LINE Right Out"},
1259 {"OUT3", NULL, "LINE Left Out"}, 1262 {"OUT3", NULL, "LINE Left Out"},
1260 {"OUT4", NULL, "LINE Right Out"}, 1263 {"OUT4", NULL, "LINE Right Out"},
1261 1264
1262 /* Left ADC input mixer */ 1265 /* Left ADC input mixer */
1263 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1266 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1264 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1267 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1265 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"}, 1268 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
1266 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"}, 1269 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
1267 1270
1268 /* Right ADC input mixer */ 1271 /* Right ADC input mixer */
1269 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1272 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1270 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1273 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1271 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"}, 1274 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
1272 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"}, 1275 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
1273 1276
1274 /* Inputs */ 1277 /* Inputs */
1275 {"ADCL", NULL, "Left ADC Mixer"}, 1278 {"ADCL", NULL, "Left ADC Mixer"},
1276 {"ADCR", NULL, "Right ADC Mixer"}, 1279 {"ADCR", NULL, "Right ADC Mixer"},
1277 1280
1278 {"IN1 Input", NULL, "INA1"}, 1281 {"IN1 Input", NULL, "INA1"},
1279 {"IN2 Input", NULL, "INA2"}, 1282 {"IN2 Input", NULL, "INA2"},
1280 1283
1281 {"MIC1 Input", NULL, "MIC1"}, 1284 {"MIC1 Input", NULL, "MIC1"},
1282 {"MIC2 Input", NULL, "MIC2"}, 1285 {"MIC2 Input", NULL, "MIC2"},
1283 }; 1286 };
1284 1287
1285 static int max98095_add_widgets(struct snd_soc_codec *codec) 1288 static int max98095_add_widgets(struct snd_soc_codec *codec)
1286 { 1289 {
1287 snd_soc_add_codec_controls(codec, max98095_snd_controls, 1290 snd_soc_add_codec_controls(codec, max98095_snd_controls,
1288 ARRAY_SIZE(max98095_snd_controls)); 1291 ARRAY_SIZE(max98095_snd_controls));
1289 1292
1290 return 0; 1293 return 0;
1291 } 1294 }
1292 1295
1293 /* codec mclk clock divider coefficients */ 1296 /* codec mclk clock divider coefficients */
1294 static const struct { 1297 static const struct {
1295 u32 rate; 1298 u32 rate;
1296 u8 sr; 1299 u8 sr;
1297 } rate_table[] = { 1300 } rate_table[] = {
1298 {8000, 0x01}, 1301 {8000, 0x01},
1299 {11025, 0x02}, 1302 {11025, 0x02},
1300 {16000, 0x03}, 1303 {16000, 0x03},
1301 {22050, 0x04}, 1304 {22050, 0x04},
1302 {24000, 0x05}, 1305 {24000, 0x05},
1303 {32000, 0x06}, 1306 {32000, 0x06},
1304 {44100, 0x07}, 1307 {44100, 0x07},
1305 {48000, 0x08}, 1308 {48000, 0x08},
1306 {88200, 0x09}, 1309 {88200, 0x09},
1307 {96000, 0x0A}, 1310 {96000, 0x0A},
1308 }; 1311 };
1309 1312
1310 static int rate_value(int rate, u8 *value) 1313 static int rate_value(int rate, u8 *value)
1311 { 1314 {
1312 int i; 1315 int i;
1313 1316
1314 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 1317 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
1315 if (rate_table[i].rate >= rate) { 1318 if (rate_table[i].rate >= rate) {
1316 *value = rate_table[i].sr; 1319 *value = rate_table[i].sr;
1317 return 0; 1320 return 0;
1318 } 1321 }
1319 } 1322 }
1320 *value = rate_table[0].sr; 1323 *value = rate_table[0].sr;
1321 return -EINVAL; 1324 return -EINVAL;
1322 } 1325 }
1323 1326
1324 static int max98095_dai1_hw_params(struct snd_pcm_substream *substream, 1327 static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
1325 struct snd_pcm_hw_params *params, 1328 struct snd_pcm_hw_params *params,
1326 struct snd_soc_dai *dai) 1329 struct snd_soc_dai *dai)
1327 { 1330 {
1328 struct snd_soc_codec *codec = dai->codec; 1331 struct snd_soc_codec *codec = dai->codec;
1329 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1332 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1330 struct max98095_cdata *cdata; 1333 struct max98095_cdata *cdata;
1331 unsigned long long ni; 1334 unsigned long long ni;
1332 unsigned int rate; 1335 unsigned int rate;
1333 u8 regval; 1336 u8 regval;
1334 1337
1335 cdata = &max98095->dai[0]; 1338 cdata = &max98095->dai[0];
1336 1339
1337 rate = params_rate(params); 1340 rate = params_rate(params);
1338 1341
1339 switch (params_format(params)) { 1342 switch (params_format(params)) {
1340 case SNDRV_PCM_FORMAT_S16_LE: 1343 case SNDRV_PCM_FORMAT_S16_LE:
1341 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, 1344 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1342 M98095_DAI_WS, 0); 1345 M98095_DAI_WS, 0);
1343 break; 1346 break;
1344 case SNDRV_PCM_FORMAT_S24_LE: 1347 case SNDRV_PCM_FORMAT_S24_LE:
1345 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, 1348 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1346 M98095_DAI_WS, M98095_DAI_WS); 1349 M98095_DAI_WS, M98095_DAI_WS);
1347 break; 1350 break;
1348 default: 1351 default:
1349 return -EINVAL; 1352 return -EINVAL;
1350 } 1353 }
1351 1354
1352 if (rate_value(rate, &regval)) 1355 if (rate_value(rate, &regval))
1353 return -EINVAL; 1356 return -EINVAL;
1354 1357
1355 snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE, 1358 snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE,
1356 M98095_CLKMODE_MASK, regval); 1359 M98095_CLKMODE_MASK, regval);
1357 cdata->rate = rate; 1360 cdata->rate = rate;
1358 1361
1359 /* Configure NI when operating as master */ 1362 /* Configure NI when operating as master */
1360 if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) { 1363 if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
1361 if (max98095->sysclk == 0) { 1364 if (max98095->sysclk == 0) {
1362 dev_err(codec->dev, "Invalid system clock frequency\n"); 1365 dev_err(codec->dev, "Invalid system clock frequency\n");
1363 return -EINVAL; 1366 return -EINVAL;
1364 } 1367 }
1365 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1368 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1366 * (unsigned long long int)rate; 1369 * (unsigned long long int)rate;
1367 do_div(ni, (unsigned long long int)max98095->sysclk); 1370 do_div(ni, (unsigned long long int)max98095->sysclk);
1368 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, 1371 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1369 (ni >> 8) & 0x7F); 1372 (ni >> 8) & 0x7F);
1370 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, 1373 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1371 ni & 0xFF); 1374 ni & 0xFF);
1372 } 1375 }
1373 1376
1374 /* Update sample rate mode */ 1377 /* Update sample rate mode */
1375 if (rate < 50000) 1378 if (rate < 50000)
1376 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, 1379 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1377 M98095_DAI_DHF, 0); 1380 M98095_DAI_DHF, 0);
1378 else 1381 else
1379 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, 1382 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1380 M98095_DAI_DHF, M98095_DAI_DHF); 1383 M98095_DAI_DHF, M98095_DAI_DHF);
1381 1384
1382 return 0; 1385 return 0;
1383 } 1386 }
1384 1387
1385 static int max98095_dai2_hw_params(struct snd_pcm_substream *substream, 1388 static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
1386 struct snd_pcm_hw_params *params, 1389 struct snd_pcm_hw_params *params,
1387 struct snd_soc_dai *dai) 1390 struct snd_soc_dai *dai)
1388 { 1391 {
1389 struct snd_soc_codec *codec = dai->codec; 1392 struct snd_soc_codec *codec = dai->codec;
1390 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1393 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1391 struct max98095_cdata *cdata; 1394 struct max98095_cdata *cdata;
1392 unsigned long long ni; 1395 unsigned long long ni;
1393 unsigned int rate; 1396 unsigned int rate;
1394 u8 regval; 1397 u8 regval;
1395 1398
1396 cdata = &max98095->dai[1]; 1399 cdata = &max98095->dai[1];
1397 1400
1398 rate = params_rate(params); 1401 rate = params_rate(params);
1399 1402
1400 switch (params_format(params)) { 1403 switch (params_format(params)) {
1401 case SNDRV_PCM_FORMAT_S16_LE: 1404 case SNDRV_PCM_FORMAT_S16_LE:
1402 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, 1405 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1403 M98095_DAI_WS, 0); 1406 M98095_DAI_WS, 0);
1404 break; 1407 break;
1405 case SNDRV_PCM_FORMAT_S24_LE: 1408 case SNDRV_PCM_FORMAT_S24_LE:
1406 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, 1409 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1407 M98095_DAI_WS, M98095_DAI_WS); 1410 M98095_DAI_WS, M98095_DAI_WS);
1408 break; 1411 break;
1409 default: 1412 default:
1410 return -EINVAL; 1413 return -EINVAL;
1411 } 1414 }
1412 1415
1413 if (rate_value(rate, &regval)) 1416 if (rate_value(rate, &regval))
1414 return -EINVAL; 1417 return -EINVAL;
1415 1418
1416 snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE, 1419 snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE,
1417 M98095_CLKMODE_MASK, regval); 1420 M98095_CLKMODE_MASK, regval);
1418 cdata->rate = rate; 1421 cdata->rate = rate;
1419 1422
1420 /* Configure NI when operating as master */ 1423 /* Configure NI when operating as master */
1421 if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) { 1424 if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
1422 if (max98095->sysclk == 0) { 1425 if (max98095->sysclk == 0) {
1423 dev_err(codec->dev, "Invalid system clock frequency\n"); 1426 dev_err(codec->dev, "Invalid system clock frequency\n");
1424 return -EINVAL; 1427 return -EINVAL;
1425 } 1428 }
1426 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1429 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1427 * (unsigned long long int)rate; 1430 * (unsigned long long int)rate;
1428 do_div(ni, (unsigned long long int)max98095->sysclk); 1431 do_div(ni, (unsigned long long int)max98095->sysclk);
1429 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, 1432 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1430 (ni >> 8) & 0x7F); 1433 (ni >> 8) & 0x7F);
1431 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, 1434 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1432 ni & 0xFF); 1435 ni & 0xFF);
1433 } 1436 }
1434 1437
1435 /* Update sample rate mode */ 1438 /* Update sample rate mode */
1436 if (rate < 50000) 1439 if (rate < 50000)
1437 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, 1440 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1438 M98095_DAI_DHF, 0); 1441 M98095_DAI_DHF, 0);
1439 else 1442 else
1440 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, 1443 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1441 M98095_DAI_DHF, M98095_DAI_DHF); 1444 M98095_DAI_DHF, M98095_DAI_DHF);
1442 1445
1443 return 0; 1446 return 0;
1444 } 1447 }
1445 1448
1446 static int max98095_dai3_hw_params(struct snd_pcm_substream *substream, 1449 static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
1447 struct snd_pcm_hw_params *params, 1450 struct snd_pcm_hw_params *params,
1448 struct snd_soc_dai *dai) 1451 struct snd_soc_dai *dai)
1449 { 1452 {
1450 struct snd_soc_codec *codec = dai->codec; 1453 struct snd_soc_codec *codec = dai->codec;
1451 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1454 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1452 struct max98095_cdata *cdata; 1455 struct max98095_cdata *cdata;
1453 unsigned long long ni; 1456 unsigned long long ni;
1454 unsigned int rate; 1457 unsigned int rate;
1455 u8 regval; 1458 u8 regval;
1456 1459
1457 cdata = &max98095->dai[2]; 1460 cdata = &max98095->dai[2];
1458 1461
1459 rate = params_rate(params); 1462 rate = params_rate(params);
1460 1463
1461 switch (params_format(params)) { 1464 switch (params_format(params)) {
1462 case SNDRV_PCM_FORMAT_S16_LE: 1465 case SNDRV_PCM_FORMAT_S16_LE:
1463 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, 1466 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1464 M98095_DAI_WS, 0); 1467 M98095_DAI_WS, 0);
1465 break; 1468 break;
1466 case SNDRV_PCM_FORMAT_S24_LE: 1469 case SNDRV_PCM_FORMAT_S24_LE:
1467 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, 1470 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1468 M98095_DAI_WS, M98095_DAI_WS); 1471 M98095_DAI_WS, M98095_DAI_WS);
1469 break; 1472 break;
1470 default: 1473 default:
1471 return -EINVAL; 1474 return -EINVAL;
1472 } 1475 }
1473 1476
1474 if (rate_value(rate, &regval)) 1477 if (rate_value(rate, &regval))
1475 return -EINVAL; 1478 return -EINVAL;
1476 1479
1477 snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE, 1480 snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE,
1478 M98095_CLKMODE_MASK, regval); 1481 M98095_CLKMODE_MASK, regval);
1479 cdata->rate = rate; 1482 cdata->rate = rate;
1480 1483
1481 /* Configure NI when operating as master */ 1484 /* Configure NI when operating as master */
1482 if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) { 1485 if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
1483 if (max98095->sysclk == 0) { 1486 if (max98095->sysclk == 0) {
1484 dev_err(codec->dev, "Invalid system clock frequency\n"); 1487 dev_err(codec->dev, "Invalid system clock frequency\n");
1485 return -EINVAL; 1488 return -EINVAL;
1486 } 1489 }
1487 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1490 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1488 * (unsigned long long int)rate; 1491 * (unsigned long long int)rate;
1489 do_div(ni, (unsigned long long int)max98095->sysclk); 1492 do_div(ni, (unsigned long long int)max98095->sysclk);
1490 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, 1493 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1491 (ni >> 8) & 0x7F); 1494 (ni >> 8) & 0x7F);
1492 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, 1495 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1493 ni & 0xFF); 1496 ni & 0xFF);
1494 } 1497 }
1495 1498
1496 /* Update sample rate mode */ 1499 /* Update sample rate mode */
1497 if (rate < 50000) 1500 if (rate < 50000)
1498 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, 1501 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1499 M98095_DAI_DHF, 0); 1502 M98095_DAI_DHF, 0);
1500 else 1503 else
1501 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, 1504 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1502 M98095_DAI_DHF, M98095_DAI_DHF); 1505 M98095_DAI_DHF, M98095_DAI_DHF);
1503 1506
1504 return 0; 1507 return 0;
1505 } 1508 }
1506 1509
1507 static int max98095_dai_set_sysclk(struct snd_soc_dai *dai, 1510 static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
1508 int clk_id, unsigned int freq, int dir) 1511 int clk_id, unsigned int freq, int dir)
1509 { 1512 {
1510 struct snd_soc_codec *codec = dai->codec; 1513 struct snd_soc_codec *codec = dai->codec;
1511 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1514 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1512 1515
1513 /* Requested clock frequency is already setup */ 1516 /* Requested clock frequency is already setup */
1514 if (freq == max98095->sysclk) 1517 if (freq == max98095->sysclk)
1515 return 0; 1518 return 0;
1516 1519
1517 /* Setup clocks for slave mode, and using the PLL 1520 /* Setup clocks for slave mode, and using the PLL
1518 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1521 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1519 * 0x02 (when master clk is 20MHz to 40MHz).. 1522 * 0x02 (when master clk is 20MHz to 40MHz)..
1520 * 0x03 (when master clk is 40MHz to 60MHz).. 1523 * 0x03 (when master clk is 40MHz to 60MHz)..
1521 */ 1524 */
1522 if ((freq >= 10000000) && (freq < 20000000)) { 1525 if ((freq >= 10000000) && (freq < 20000000)) {
1523 snd_soc_write(codec, M98095_026_SYS_CLK, 0x10); 1526 snd_soc_write(codec, M98095_026_SYS_CLK, 0x10);
1524 } else if ((freq >= 20000000) && (freq < 40000000)) { 1527 } else if ((freq >= 20000000) && (freq < 40000000)) {
1525 snd_soc_write(codec, M98095_026_SYS_CLK, 0x20); 1528 snd_soc_write(codec, M98095_026_SYS_CLK, 0x20);
1526 } else if ((freq >= 40000000) && (freq < 60000000)) { 1529 } else if ((freq >= 40000000) && (freq < 60000000)) {
1527 snd_soc_write(codec, M98095_026_SYS_CLK, 0x30); 1530 snd_soc_write(codec, M98095_026_SYS_CLK, 0x30);
1528 } else { 1531 } else {
1529 dev_err(codec->dev, "Invalid master clock frequency\n"); 1532 dev_err(codec->dev, "Invalid master clock frequency\n");
1530 return -EINVAL; 1533 return -EINVAL;
1531 } 1534 }
1532 1535
1533 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1536 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1534 1537
1535 max98095->sysclk = freq; 1538 max98095->sysclk = freq;
1536 return 0; 1539 return 0;
1537 } 1540 }
1538 1541
1539 static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai, 1542 static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1540 unsigned int fmt) 1543 unsigned int fmt)
1541 { 1544 {
1542 struct snd_soc_codec *codec = codec_dai->codec; 1545 struct snd_soc_codec *codec = codec_dai->codec;
1543 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1546 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1544 struct max98095_cdata *cdata; 1547 struct max98095_cdata *cdata;
1545 u8 regval = 0; 1548 u8 regval = 0;
1546 1549
1547 cdata = &max98095->dai[0]; 1550 cdata = &max98095->dai[0];
1548 1551
1549 if (fmt != cdata->fmt) { 1552 if (fmt != cdata->fmt) {
1550 cdata->fmt = fmt; 1553 cdata->fmt = fmt;
1551 1554
1552 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1555 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1553 case SND_SOC_DAIFMT_CBS_CFS: 1556 case SND_SOC_DAIFMT_CBS_CFS:
1554 /* Slave mode PLL */ 1557 /* Slave mode PLL */
1555 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, 1558 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1556 0x80); 1559 0x80);
1557 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, 1560 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1558 0x00); 1561 0x00);
1559 break; 1562 break;
1560 case SND_SOC_DAIFMT_CBM_CFM: 1563 case SND_SOC_DAIFMT_CBM_CFM:
1561 /* Set to master mode */ 1564 /* Set to master mode */
1562 regval |= M98095_DAI_MAS; 1565 regval |= M98095_DAI_MAS;
1563 break; 1566 break;
1564 case SND_SOC_DAIFMT_CBS_CFM: 1567 case SND_SOC_DAIFMT_CBS_CFM:
1565 case SND_SOC_DAIFMT_CBM_CFS: 1568 case SND_SOC_DAIFMT_CBM_CFS:
1566 default: 1569 default:
1567 dev_err(codec->dev, "Clock mode unsupported"); 1570 dev_err(codec->dev, "Clock mode unsupported");
1568 return -EINVAL; 1571 return -EINVAL;
1569 } 1572 }
1570 1573
1571 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1574 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1572 case SND_SOC_DAIFMT_I2S: 1575 case SND_SOC_DAIFMT_I2S:
1573 regval |= M98095_DAI_DLY; 1576 regval |= M98095_DAI_DLY;
1574 break; 1577 break;
1575 case SND_SOC_DAIFMT_LEFT_J: 1578 case SND_SOC_DAIFMT_LEFT_J:
1576 break; 1579 break;
1577 default: 1580 default:
1578 return -EINVAL; 1581 return -EINVAL;
1579 } 1582 }
1580 1583
1581 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1584 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1582 case SND_SOC_DAIFMT_NB_NF: 1585 case SND_SOC_DAIFMT_NB_NF:
1583 break; 1586 break;
1584 case SND_SOC_DAIFMT_NB_IF: 1587 case SND_SOC_DAIFMT_NB_IF:
1585 regval |= M98095_DAI_WCI; 1588 regval |= M98095_DAI_WCI;
1586 break; 1589 break;
1587 case SND_SOC_DAIFMT_IB_NF: 1590 case SND_SOC_DAIFMT_IB_NF:
1588 regval |= M98095_DAI_BCI; 1591 regval |= M98095_DAI_BCI;
1589 break; 1592 break;
1590 case SND_SOC_DAIFMT_IB_IF: 1593 case SND_SOC_DAIFMT_IB_IF:
1591 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1594 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1592 break; 1595 break;
1593 default: 1596 default:
1594 return -EINVAL; 1597 return -EINVAL;
1595 } 1598 }
1596 1599
1597 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, 1600 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1598 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1601 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1599 M98095_DAI_WCI, regval); 1602 M98095_DAI_WCI, regval);
1600 1603
1601 snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64); 1604 snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
1602 } 1605 }
1603 1606
1604 return 0; 1607 return 0;
1605 } 1608 }
1606 1609
1607 static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai, 1610 static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1608 unsigned int fmt) 1611 unsigned int fmt)
1609 { 1612 {
1610 struct snd_soc_codec *codec = codec_dai->codec; 1613 struct snd_soc_codec *codec = codec_dai->codec;
1611 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1614 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1612 struct max98095_cdata *cdata; 1615 struct max98095_cdata *cdata;
1613 u8 regval = 0; 1616 u8 regval = 0;
1614 1617
1615 cdata = &max98095->dai[1]; 1618 cdata = &max98095->dai[1];
1616 1619
1617 if (fmt != cdata->fmt) { 1620 if (fmt != cdata->fmt) {
1618 cdata->fmt = fmt; 1621 cdata->fmt = fmt;
1619 1622
1620 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1623 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1621 case SND_SOC_DAIFMT_CBS_CFS: 1624 case SND_SOC_DAIFMT_CBS_CFS:
1622 /* Slave mode PLL */ 1625 /* Slave mode PLL */
1623 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, 1626 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1624 0x80); 1627 0x80);
1625 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, 1628 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1626 0x00); 1629 0x00);
1627 break; 1630 break;
1628 case SND_SOC_DAIFMT_CBM_CFM: 1631 case SND_SOC_DAIFMT_CBM_CFM:
1629 /* Set to master mode */ 1632 /* Set to master mode */
1630 regval |= M98095_DAI_MAS; 1633 regval |= M98095_DAI_MAS;
1631 break; 1634 break;
1632 case SND_SOC_DAIFMT_CBS_CFM: 1635 case SND_SOC_DAIFMT_CBS_CFM:
1633 case SND_SOC_DAIFMT_CBM_CFS: 1636 case SND_SOC_DAIFMT_CBM_CFS:
1634 default: 1637 default:
1635 dev_err(codec->dev, "Clock mode unsupported"); 1638 dev_err(codec->dev, "Clock mode unsupported");
1636 return -EINVAL; 1639 return -EINVAL;
1637 } 1640 }
1638 1641
1639 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1642 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1640 case SND_SOC_DAIFMT_I2S: 1643 case SND_SOC_DAIFMT_I2S:
1641 regval |= M98095_DAI_DLY; 1644 regval |= M98095_DAI_DLY;
1642 break; 1645 break;
1643 case SND_SOC_DAIFMT_LEFT_J: 1646 case SND_SOC_DAIFMT_LEFT_J:
1644 break; 1647 break;
1645 default: 1648 default:
1646 return -EINVAL; 1649 return -EINVAL;
1647 } 1650 }
1648 1651
1649 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1652 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1650 case SND_SOC_DAIFMT_NB_NF: 1653 case SND_SOC_DAIFMT_NB_NF:
1651 break; 1654 break;
1652 case SND_SOC_DAIFMT_NB_IF: 1655 case SND_SOC_DAIFMT_NB_IF:
1653 regval |= M98095_DAI_WCI; 1656 regval |= M98095_DAI_WCI;
1654 break; 1657 break;
1655 case SND_SOC_DAIFMT_IB_NF: 1658 case SND_SOC_DAIFMT_IB_NF:
1656 regval |= M98095_DAI_BCI; 1659 regval |= M98095_DAI_BCI;
1657 break; 1660 break;
1658 case SND_SOC_DAIFMT_IB_IF: 1661 case SND_SOC_DAIFMT_IB_IF:
1659 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1662 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1660 break; 1663 break;
1661 default: 1664 default:
1662 return -EINVAL; 1665 return -EINVAL;
1663 } 1666 }
1664 1667
1665 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, 1668 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1666 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1669 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1667 M98095_DAI_WCI, regval); 1670 M98095_DAI_WCI, regval);
1668 1671
1669 snd_soc_write(codec, M98095_035_DAI2_CLOCK, 1672 snd_soc_write(codec, M98095_035_DAI2_CLOCK,
1670 M98095_DAI_BSEL64); 1673 M98095_DAI_BSEL64);
1671 } 1674 }
1672 1675
1673 return 0; 1676 return 0;
1674 } 1677 }
1675 1678
1676 static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai, 1679 static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
1677 unsigned int fmt) 1680 unsigned int fmt)
1678 { 1681 {
1679 struct snd_soc_codec *codec = codec_dai->codec; 1682 struct snd_soc_codec *codec = codec_dai->codec;
1680 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1683 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1681 struct max98095_cdata *cdata; 1684 struct max98095_cdata *cdata;
1682 u8 regval = 0; 1685 u8 regval = 0;
1683 1686
1684 cdata = &max98095->dai[2]; 1687 cdata = &max98095->dai[2];
1685 1688
1686 if (fmt != cdata->fmt) { 1689 if (fmt != cdata->fmt) {
1687 cdata->fmt = fmt; 1690 cdata->fmt = fmt;
1688 1691
1689 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1692 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1690 case SND_SOC_DAIFMT_CBS_CFS: 1693 case SND_SOC_DAIFMT_CBS_CFS:
1691 /* Slave mode PLL */ 1694 /* Slave mode PLL */
1692 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, 1695 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1693 0x80); 1696 0x80);
1694 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, 1697 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1695 0x00); 1698 0x00);
1696 break; 1699 break;
1697 case SND_SOC_DAIFMT_CBM_CFM: 1700 case SND_SOC_DAIFMT_CBM_CFM:
1698 /* Set to master mode */ 1701 /* Set to master mode */
1699 regval |= M98095_DAI_MAS; 1702 regval |= M98095_DAI_MAS;
1700 break; 1703 break;
1701 case SND_SOC_DAIFMT_CBS_CFM: 1704 case SND_SOC_DAIFMT_CBS_CFM:
1702 case SND_SOC_DAIFMT_CBM_CFS: 1705 case SND_SOC_DAIFMT_CBM_CFS:
1703 default: 1706 default:
1704 dev_err(codec->dev, "Clock mode unsupported"); 1707 dev_err(codec->dev, "Clock mode unsupported");
1705 return -EINVAL; 1708 return -EINVAL;
1706 } 1709 }
1707 1710
1708 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1711 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1709 case SND_SOC_DAIFMT_I2S: 1712 case SND_SOC_DAIFMT_I2S:
1710 regval |= M98095_DAI_DLY; 1713 regval |= M98095_DAI_DLY;
1711 break; 1714 break;
1712 case SND_SOC_DAIFMT_LEFT_J: 1715 case SND_SOC_DAIFMT_LEFT_J:
1713 break; 1716 break;
1714 default: 1717 default:
1715 return -EINVAL; 1718 return -EINVAL;
1716 } 1719 }
1717 1720
1718 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1721 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1719 case SND_SOC_DAIFMT_NB_NF: 1722 case SND_SOC_DAIFMT_NB_NF:
1720 break; 1723 break;
1721 case SND_SOC_DAIFMT_NB_IF: 1724 case SND_SOC_DAIFMT_NB_IF:
1722 regval |= M98095_DAI_WCI; 1725 regval |= M98095_DAI_WCI;
1723 break; 1726 break;
1724 case SND_SOC_DAIFMT_IB_NF: 1727 case SND_SOC_DAIFMT_IB_NF:
1725 regval |= M98095_DAI_BCI; 1728 regval |= M98095_DAI_BCI;
1726 break; 1729 break;
1727 case SND_SOC_DAIFMT_IB_IF: 1730 case SND_SOC_DAIFMT_IB_IF:
1728 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1731 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1729 break; 1732 break;
1730 default: 1733 default:
1731 return -EINVAL; 1734 return -EINVAL;
1732 } 1735 }
1733 1736
1734 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, 1737 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1735 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1738 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1736 M98095_DAI_WCI, regval); 1739 M98095_DAI_WCI, regval);
1737 1740
1738 snd_soc_write(codec, M98095_03F_DAI3_CLOCK, 1741 snd_soc_write(codec, M98095_03F_DAI3_CLOCK,
1739 M98095_DAI_BSEL64); 1742 M98095_DAI_BSEL64);
1740 } 1743 }
1741 1744
1742 return 0; 1745 return 0;
1743 } 1746 }
1744 1747
1745 static int max98095_set_bias_level(struct snd_soc_codec *codec, 1748 static int max98095_set_bias_level(struct snd_soc_codec *codec,
1746 enum snd_soc_bias_level level) 1749 enum snd_soc_bias_level level)
1747 { 1750 {
1748 int ret; 1751 int ret;
1749 1752
1750 switch (level) { 1753 switch (level) {
1751 case SND_SOC_BIAS_ON: 1754 case SND_SOC_BIAS_ON:
1752 break; 1755 break;
1753 1756
1754 case SND_SOC_BIAS_PREPARE: 1757 case SND_SOC_BIAS_PREPARE:
1755 break; 1758 break;
1756 1759
1757 case SND_SOC_BIAS_STANDBY: 1760 case SND_SOC_BIAS_STANDBY:
1758 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1761 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1759 ret = snd_soc_cache_sync(codec); 1762 ret = snd_soc_cache_sync(codec);
1760 1763
1761 if (ret != 0) { 1764 if (ret != 0) {
1762 dev_err(codec->dev, "Failed to sync cache: %d\n", ret); 1765 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1763 return ret; 1766 return ret;
1764 } 1767 }
1765 } 1768 }
1766 1769
1767 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, 1770 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1768 M98095_MBEN, M98095_MBEN); 1771 M98095_MBEN, M98095_MBEN);
1769 break; 1772 break;
1770 1773
1771 case SND_SOC_BIAS_OFF: 1774 case SND_SOC_BIAS_OFF:
1772 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, 1775 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1773 M98095_MBEN, 0); 1776 M98095_MBEN, 0);
1774 codec->cache_sync = 1; 1777 codec->cache_sync = 1;
1775 break; 1778 break;
1776 } 1779 }
1777 codec->dapm.bias_level = level; 1780 codec->dapm.bias_level = level;
1778 return 0; 1781 return 0;
1779 } 1782 }
1780 1783
1781 #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000 1784 #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
1782 #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 1785 #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1783 1786
1784 static const struct snd_soc_dai_ops max98095_dai1_ops = { 1787 static const struct snd_soc_dai_ops max98095_dai1_ops = {
1785 .set_sysclk = max98095_dai_set_sysclk, 1788 .set_sysclk = max98095_dai_set_sysclk,
1786 .set_fmt = max98095_dai1_set_fmt, 1789 .set_fmt = max98095_dai1_set_fmt,
1787 .hw_params = max98095_dai1_hw_params, 1790 .hw_params = max98095_dai1_hw_params,
1788 }; 1791 };
1789 1792
1790 static const struct snd_soc_dai_ops max98095_dai2_ops = { 1793 static const struct snd_soc_dai_ops max98095_dai2_ops = {
1791 .set_sysclk = max98095_dai_set_sysclk, 1794 .set_sysclk = max98095_dai_set_sysclk,
1792 .set_fmt = max98095_dai2_set_fmt, 1795 .set_fmt = max98095_dai2_set_fmt,
1793 .hw_params = max98095_dai2_hw_params, 1796 .hw_params = max98095_dai2_hw_params,
1794 }; 1797 };
1795 1798
1796 static const struct snd_soc_dai_ops max98095_dai3_ops = { 1799 static const struct snd_soc_dai_ops max98095_dai3_ops = {
1797 .set_sysclk = max98095_dai_set_sysclk, 1800 .set_sysclk = max98095_dai_set_sysclk,
1798 .set_fmt = max98095_dai3_set_fmt, 1801 .set_fmt = max98095_dai3_set_fmt,
1799 .hw_params = max98095_dai3_hw_params, 1802 .hw_params = max98095_dai3_hw_params,
1800 }; 1803 };
1801 1804
1802 static struct snd_soc_dai_driver max98095_dai[] = { 1805 static struct snd_soc_dai_driver max98095_dai[] = {
1803 { 1806 {
1804 .name = "HiFi", 1807 .name = "HiFi",
1805 .playback = { 1808 .playback = {
1806 .stream_name = "HiFi Playback", 1809 .stream_name = "HiFi Playback",
1807 .channels_min = 1, 1810 .channels_min = 1,
1808 .channels_max = 2, 1811 .channels_max = 2,
1809 .rates = MAX98095_RATES, 1812 .rates = MAX98095_RATES,
1810 .formats = MAX98095_FORMATS, 1813 .formats = MAX98095_FORMATS,
1811 }, 1814 },
1812 .capture = { 1815 .capture = {
1813 .stream_name = "HiFi Capture", 1816 .stream_name = "HiFi Capture",
1814 .channels_min = 1, 1817 .channels_min = 1,
1815 .channels_max = 2, 1818 .channels_max = 2,
1816 .rates = MAX98095_RATES, 1819 .rates = MAX98095_RATES,
1817 .formats = MAX98095_FORMATS, 1820 .formats = MAX98095_FORMATS,
1818 }, 1821 },
1819 .ops = &max98095_dai1_ops, 1822 .ops = &max98095_dai1_ops,
1820 }, 1823 },
1821 { 1824 {
1822 .name = "Aux", 1825 .name = "Aux",
1823 .playback = { 1826 .playback = {
1824 .stream_name = "Aux Playback", 1827 .stream_name = "Aux Playback",
1825 .channels_min = 1, 1828 .channels_min = 1,
1826 .channels_max = 1, 1829 .channels_max = 1,
1827 .rates = MAX98095_RATES, 1830 .rates = MAX98095_RATES,
1828 .formats = MAX98095_FORMATS, 1831 .formats = MAX98095_FORMATS,
1829 }, 1832 },
1830 .ops = &max98095_dai2_ops, 1833 .ops = &max98095_dai2_ops,
1831 }, 1834 },
1832 { 1835 {
1833 .name = "Voice", 1836 .name = "Voice",
1834 .playback = { 1837 .playback = {
1835 .stream_name = "Voice Playback", 1838 .stream_name = "Voice Playback",
1836 .channels_min = 1, 1839 .channels_min = 1,
1837 .channels_max = 1, 1840 .channels_max = 1,
1838 .rates = MAX98095_RATES, 1841 .rates = MAX98095_RATES,
1839 .formats = MAX98095_FORMATS, 1842 .formats = MAX98095_FORMATS,
1840 }, 1843 },
1841 .ops = &max98095_dai3_ops, 1844 .ops = &max98095_dai3_ops,
1842 } 1845 }
1843 1846
1844 }; 1847 };
1845 1848
1846 static int max98095_get_eq_channel(const char *name) 1849 static int max98095_get_eq_channel(const char *name)
1847 { 1850 {
1848 if (strcmp(name, "EQ1 Mode") == 0) 1851 if (strcmp(name, "EQ1 Mode") == 0)
1849 return 0; 1852 return 0;
1850 if (strcmp(name, "EQ2 Mode") == 0) 1853 if (strcmp(name, "EQ2 Mode") == 0)
1851 return 1; 1854 return 1;
1852 return -EINVAL; 1855 return -EINVAL;
1853 } 1856 }
1854 1857
1855 static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol, 1858 static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
1856 struct snd_ctl_elem_value *ucontrol) 1859 struct snd_ctl_elem_value *ucontrol)
1857 { 1860 {
1858 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1861 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1859 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1862 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1860 struct max98095_pdata *pdata = max98095->pdata; 1863 struct max98095_pdata *pdata = max98095->pdata;
1861 int channel = max98095_get_eq_channel(kcontrol->id.name); 1864 int channel = max98095_get_eq_channel(kcontrol->id.name);
1862 struct max98095_cdata *cdata; 1865 struct max98095_cdata *cdata;
1863 int sel = ucontrol->value.integer.value[0]; 1866 int sel = ucontrol->value.integer.value[0];
1864 struct max98095_eq_cfg *coef_set; 1867 struct max98095_eq_cfg *coef_set;
1865 int fs, best, best_val, i; 1868 int fs, best, best_val, i;
1866 int regmask, regsave; 1869 int regmask, regsave;
1867 1870
1868 BUG_ON(channel > 1); 1871 BUG_ON(channel > 1);
1869 1872
1870 if (!pdata || !max98095->eq_textcnt) 1873 if (!pdata || !max98095->eq_textcnt)
1871 return 0; 1874 return 0;
1872 1875
1873 if (sel >= pdata->eq_cfgcnt) 1876 if (sel >= pdata->eq_cfgcnt)
1874 return -EINVAL; 1877 return -EINVAL;
1875 1878
1876 cdata = &max98095->dai[channel]; 1879 cdata = &max98095->dai[channel];
1877 cdata->eq_sel = sel; 1880 cdata->eq_sel = sel;
1878 fs = cdata->rate; 1881 fs = cdata->rate;
1879 1882
1880 /* Find the selected configuration with nearest sample rate */ 1883 /* Find the selected configuration with nearest sample rate */
1881 best = 0; 1884 best = 0;
1882 best_val = INT_MAX; 1885 best_val = INT_MAX;
1883 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1886 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1884 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 && 1887 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
1885 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1888 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1886 best = i; 1889 best = i;
1887 best_val = abs(pdata->eq_cfg[i].rate - fs); 1890 best_val = abs(pdata->eq_cfg[i].rate - fs);
1888 } 1891 }
1889 } 1892 }
1890 1893
1891 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 1894 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1892 pdata->eq_cfg[best].name, 1895 pdata->eq_cfg[best].name,
1893 pdata->eq_cfg[best].rate, fs); 1896 pdata->eq_cfg[best].rate, fs);
1894 1897
1895 coef_set = &pdata->eq_cfg[best]; 1898 coef_set = &pdata->eq_cfg[best];
1896 1899
1897 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN; 1900 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
1898 1901
1899 /* Disable filter while configuring, and save current on/off state */ 1902 /* Disable filter while configuring, and save current on/off state */
1900 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); 1903 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
1901 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); 1904 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
1902 1905
1903 mutex_lock(&codec->mutex); 1906 mutex_lock(&codec->mutex);
1904 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); 1907 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1905 m98095_eq_band(codec, channel, 0, coef_set->band1); 1908 m98095_eq_band(codec, channel, 0, coef_set->band1);
1906 m98095_eq_band(codec, channel, 1, coef_set->band2); 1909 m98095_eq_band(codec, channel, 1, coef_set->band2);
1907 m98095_eq_band(codec, channel, 2, coef_set->band3); 1910 m98095_eq_band(codec, channel, 2, coef_set->band3);
1908 m98095_eq_band(codec, channel, 3, coef_set->band4); 1911 m98095_eq_band(codec, channel, 3, coef_set->band4);
1909 m98095_eq_band(codec, channel, 4, coef_set->band5); 1912 m98095_eq_band(codec, channel, 4, coef_set->band5);
1910 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); 1913 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
1911 mutex_unlock(&codec->mutex); 1914 mutex_unlock(&codec->mutex);
1912 1915
1913 /* Restore the original on/off state */ 1916 /* Restore the original on/off state */
1914 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); 1917 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
1915 return 0; 1918 return 0;
1916 } 1919 }
1917 1920
1918 static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol, 1921 static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
1919 struct snd_ctl_elem_value *ucontrol) 1922 struct snd_ctl_elem_value *ucontrol)
1920 { 1923 {
1921 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1924 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1922 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1925 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1923 int channel = max98095_get_eq_channel(kcontrol->id.name); 1926 int channel = max98095_get_eq_channel(kcontrol->id.name);
1924 struct max98095_cdata *cdata; 1927 struct max98095_cdata *cdata;
1925 1928
1926 cdata = &max98095->dai[channel]; 1929 cdata = &max98095->dai[channel];
1927 ucontrol->value.enumerated.item[0] = cdata->eq_sel; 1930 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1928 1931
1929 return 0; 1932 return 0;
1930 } 1933 }
1931 1934
1932 static void max98095_handle_eq_pdata(struct snd_soc_codec *codec) 1935 static void max98095_handle_eq_pdata(struct snd_soc_codec *codec)
1933 { 1936 {
1934 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1937 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1935 struct max98095_pdata *pdata = max98095->pdata; 1938 struct max98095_pdata *pdata = max98095->pdata;
1936 struct max98095_eq_cfg *cfg; 1939 struct max98095_eq_cfg *cfg;
1937 unsigned int cfgcnt; 1940 unsigned int cfgcnt;
1938 int i, j; 1941 int i, j;
1939 const char **t; 1942 const char **t;
1940 int ret; 1943 int ret;
1941 1944
1942 struct snd_kcontrol_new controls[] = { 1945 struct snd_kcontrol_new controls[] = {
1943 SOC_ENUM_EXT("EQ1 Mode", 1946 SOC_ENUM_EXT("EQ1 Mode",
1944 max98095->eq_enum, 1947 max98095->eq_enum,
1945 max98095_get_eq_enum, 1948 max98095_get_eq_enum,
1946 max98095_put_eq_enum), 1949 max98095_put_eq_enum),
1947 SOC_ENUM_EXT("EQ2 Mode", 1950 SOC_ENUM_EXT("EQ2 Mode",
1948 max98095->eq_enum, 1951 max98095->eq_enum,
1949 max98095_get_eq_enum, 1952 max98095_get_eq_enum,
1950 max98095_put_eq_enum), 1953 max98095_put_eq_enum),
1951 }; 1954 };
1952 1955
1953 cfg = pdata->eq_cfg; 1956 cfg = pdata->eq_cfg;
1954 cfgcnt = pdata->eq_cfgcnt; 1957 cfgcnt = pdata->eq_cfgcnt;
1955 1958
1956 /* Setup an array of texts for the equalizer enum. 1959 /* Setup an array of texts for the equalizer enum.
1957 * This is based on Mark Brown's equalizer driver code. 1960 * This is based on Mark Brown's equalizer driver code.
1958 */ 1961 */
1959 max98095->eq_textcnt = 0; 1962 max98095->eq_textcnt = 0;
1960 max98095->eq_texts = NULL; 1963 max98095->eq_texts = NULL;
1961 for (i = 0; i < cfgcnt; i++) { 1964 for (i = 0; i < cfgcnt; i++) {
1962 for (j = 0; j < max98095->eq_textcnt; j++) { 1965 for (j = 0; j < max98095->eq_textcnt; j++) {
1963 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0) 1966 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
1964 break; 1967 break;
1965 } 1968 }
1966 1969
1967 if (j != max98095->eq_textcnt) 1970 if (j != max98095->eq_textcnt)
1968 continue; 1971 continue;
1969 1972
1970 /* Expand the array */ 1973 /* Expand the array */
1971 t = krealloc(max98095->eq_texts, 1974 t = krealloc(max98095->eq_texts,
1972 sizeof(char *) * (max98095->eq_textcnt + 1), 1975 sizeof(char *) * (max98095->eq_textcnt + 1),
1973 GFP_KERNEL); 1976 GFP_KERNEL);
1974 if (t == NULL) 1977 if (t == NULL)
1975 continue; 1978 continue;
1976 1979
1977 /* Store the new entry */ 1980 /* Store the new entry */
1978 t[max98095->eq_textcnt] = cfg[i].name; 1981 t[max98095->eq_textcnt] = cfg[i].name;
1979 max98095->eq_textcnt++; 1982 max98095->eq_textcnt++;
1980 max98095->eq_texts = t; 1983 max98095->eq_texts = t;
1981 } 1984 }
1982 1985
1983 /* Now point the soc_enum to .texts array items */ 1986 /* Now point the soc_enum to .texts array items */
1984 max98095->eq_enum.texts = max98095->eq_texts; 1987 max98095->eq_enum.texts = max98095->eq_texts;
1985 max98095->eq_enum.max = max98095->eq_textcnt; 1988 max98095->eq_enum.max = max98095->eq_textcnt;
1986 1989
1987 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 1990 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
1988 if (ret != 0) 1991 if (ret != 0)
1989 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret); 1992 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
1990 } 1993 }
1991 1994
1992 static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"}; 1995 static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"};
1993 1996
1994 static int max98095_get_bq_channel(struct snd_soc_codec *codec, 1997 static int max98095_get_bq_channel(struct snd_soc_codec *codec,
1995 const char *name) 1998 const char *name)
1996 { 1999 {
1997 int i; 2000 int i;
1998 2001
1999 for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++) 2002 for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++)
2000 if (strcmp(name, bq_mode_name[i]) == 0) 2003 if (strcmp(name, bq_mode_name[i]) == 0)
2001 return i; 2004 return i;
2002 2005
2003 /* Shouldn't happen */ 2006 /* Shouldn't happen */
2004 dev_err(codec->dev, "Bad biquad channel name '%s'\n", name); 2007 dev_err(codec->dev, "Bad biquad channel name '%s'\n", name);
2005 return -EINVAL; 2008 return -EINVAL;
2006 } 2009 }
2007 2010
2008 static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol, 2011 static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
2009 struct snd_ctl_elem_value *ucontrol) 2012 struct snd_ctl_elem_value *ucontrol)
2010 { 2013 {
2011 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 2014 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2012 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2015 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2013 struct max98095_pdata *pdata = max98095->pdata; 2016 struct max98095_pdata *pdata = max98095->pdata;
2014 int channel = max98095_get_bq_channel(codec, kcontrol->id.name); 2017 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
2015 struct max98095_cdata *cdata; 2018 struct max98095_cdata *cdata;
2016 int sel = ucontrol->value.integer.value[0]; 2019 int sel = ucontrol->value.integer.value[0];
2017 struct max98095_biquad_cfg *coef_set; 2020 struct max98095_biquad_cfg *coef_set;
2018 int fs, best, best_val, i; 2021 int fs, best, best_val, i;
2019 int regmask, regsave; 2022 int regmask, regsave;
2020 2023
2021 if (channel < 0) 2024 if (channel < 0)
2022 return channel; 2025 return channel;
2023 2026
2024 if (!pdata || !max98095->bq_textcnt) 2027 if (!pdata || !max98095->bq_textcnt)
2025 return 0; 2028 return 0;
2026 2029
2027 if (sel >= pdata->bq_cfgcnt) 2030 if (sel >= pdata->bq_cfgcnt)
2028 return -EINVAL; 2031 return -EINVAL;
2029 2032
2030 cdata = &max98095->dai[channel]; 2033 cdata = &max98095->dai[channel];
2031 cdata->bq_sel = sel; 2034 cdata->bq_sel = sel;
2032 fs = cdata->rate; 2035 fs = cdata->rate;
2033 2036
2034 /* Find the selected configuration with nearest sample rate */ 2037 /* Find the selected configuration with nearest sample rate */
2035 best = 0; 2038 best = 0;
2036 best_val = INT_MAX; 2039 best_val = INT_MAX;
2037 for (i = 0; i < pdata->bq_cfgcnt; i++) { 2040 for (i = 0; i < pdata->bq_cfgcnt; i++) {
2038 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 && 2041 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
2039 abs(pdata->bq_cfg[i].rate - fs) < best_val) { 2042 abs(pdata->bq_cfg[i].rate - fs) < best_val) {
2040 best = i; 2043 best = i;
2041 best_val = abs(pdata->bq_cfg[i].rate - fs); 2044 best_val = abs(pdata->bq_cfg[i].rate - fs);
2042 } 2045 }
2043 } 2046 }
2044 2047
2045 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 2048 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
2046 pdata->bq_cfg[best].name, 2049 pdata->bq_cfg[best].name,
2047 pdata->bq_cfg[best].rate, fs); 2050 pdata->bq_cfg[best].rate, fs);
2048 2051
2049 coef_set = &pdata->bq_cfg[best]; 2052 coef_set = &pdata->bq_cfg[best];
2050 2053
2051 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN; 2054 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
2052 2055
2053 /* Disable filter while configuring, and save current on/off state */ 2056 /* Disable filter while configuring, and save current on/off state */
2054 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); 2057 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
2055 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); 2058 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
2056 2059
2057 mutex_lock(&codec->mutex); 2060 mutex_lock(&codec->mutex);
2058 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); 2061 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
2059 m98095_biquad_band(codec, channel, 0, coef_set->band1); 2062 m98095_biquad_band(codec, channel, 0, coef_set->band1);
2060 m98095_biquad_band(codec, channel, 1, coef_set->band2); 2063 m98095_biquad_band(codec, channel, 1, coef_set->band2);
2061 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); 2064 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
2062 mutex_unlock(&codec->mutex); 2065 mutex_unlock(&codec->mutex);
2063 2066
2064 /* Restore the original on/off state */ 2067 /* Restore the original on/off state */
2065 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); 2068 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
2066 return 0; 2069 return 0;
2067 } 2070 }
2068 2071
2069 static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol, 2072 static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
2070 struct snd_ctl_elem_value *ucontrol) 2073 struct snd_ctl_elem_value *ucontrol)
2071 { 2074 {
2072 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 2075 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2073 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2076 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2074 int channel = max98095_get_bq_channel(codec, kcontrol->id.name); 2077 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
2075 struct max98095_cdata *cdata; 2078 struct max98095_cdata *cdata;
2076 2079
2077 if (channel < 0) 2080 if (channel < 0)
2078 return channel; 2081 return channel;
2079 2082
2080 cdata = &max98095->dai[channel]; 2083 cdata = &max98095->dai[channel];
2081 ucontrol->value.enumerated.item[0] = cdata->bq_sel; 2084 ucontrol->value.enumerated.item[0] = cdata->bq_sel;
2082 2085
2083 return 0; 2086 return 0;
2084 } 2087 }
2085 2088
2086 static void max98095_handle_bq_pdata(struct snd_soc_codec *codec) 2089 static void max98095_handle_bq_pdata(struct snd_soc_codec *codec)
2087 { 2090 {
2088 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2091 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2089 struct max98095_pdata *pdata = max98095->pdata; 2092 struct max98095_pdata *pdata = max98095->pdata;
2090 struct max98095_biquad_cfg *cfg; 2093 struct max98095_biquad_cfg *cfg;
2091 unsigned int cfgcnt; 2094 unsigned int cfgcnt;
2092 int i, j; 2095 int i, j;
2093 const char **t; 2096 const char **t;
2094 int ret; 2097 int ret;
2095 2098
2096 struct snd_kcontrol_new controls[] = { 2099 struct snd_kcontrol_new controls[] = {
2097 SOC_ENUM_EXT((char *)bq_mode_name[0], 2100 SOC_ENUM_EXT((char *)bq_mode_name[0],
2098 max98095->bq_enum, 2101 max98095->bq_enum,
2099 max98095_get_bq_enum, 2102 max98095_get_bq_enum,
2100 max98095_put_bq_enum), 2103 max98095_put_bq_enum),
2101 SOC_ENUM_EXT((char *)bq_mode_name[1], 2104 SOC_ENUM_EXT((char *)bq_mode_name[1],
2102 max98095->bq_enum, 2105 max98095->bq_enum,
2103 max98095_get_bq_enum, 2106 max98095_get_bq_enum,
2104 max98095_put_bq_enum), 2107 max98095_put_bq_enum),
2105 }; 2108 };
2106 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name)); 2109 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name));
2107 2110
2108 cfg = pdata->bq_cfg; 2111 cfg = pdata->bq_cfg;
2109 cfgcnt = pdata->bq_cfgcnt; 2112 cfgcnt = pdata->bq_cfgcnt;
2110 2113
2111 /* Setup an array of texts for the biquad enum. 2114 /* Setup an array of texts for the biquad enum.
2112 * This is based on Mark Brown's equalizer driver code. 2115 * This is based on Mark Brown's equalizer driver code.
2113 */ 2116 */
2114 max98095->bq_textcnt = 0; 2117 max98095->bq_textcnt = 0;
2115 max98095->bq_texts = NULL; 2118 max98095->bq_texts = NULL;
2116 for (i = 0; i < cfgcnt; i++) { 2119 for (i = 0; i < cfgcnt; i++) {
2117 for (j = 0; j < max98095->bq_textcnt; j++) { 2120 for (j = 0; j < max98095->bq_textcnt; j++) {
2118 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0) 2121 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
2119 break; 2122 break;
2120 } 2123 }
2121 2124
2122 if (j != max98095->bq_textcnt) 2125 if (j != max98095->bq_textcnt)
2123 continue; 2126 continue;
2124 2127
2125 /* Expand the array */ 2128 /* Expand the array */
2126 t = krealloc(max98095->bq_texts, 2129 t = krealloc(max98095->bq_texts,
2127 sizeof(char *) * (max98095->bq_textcnt + 1), 2130 sizeof(char *) * (max98095->bq_textcnt + 1),
2128 GFP_KERNEL); 2131 GFP_KERNEL);
2129 if (t == NULL) 2132 if (t == NULL)
2130 continue; 2133 continue;
2131 2134
2132 /* Store the new entry */ 2135 /* Store the new entry */
2133 t[max98095->bq_textcnt] = cfg[i].name; 2136 t[max98095->bq_textcnt] = cfg[i].name;
2134 max98095->bq_textcnt++; 2137 max98095->bq_textcnt++;
2135 max98095->bq_texts = t; 2138 max98095->bq_texts = t;
2136 } 2139 }
2137 2140
2138 /* Now point the soc_enum to .texts array items */ 2141 /* Now point the soc_enum to .texts array items */
2139 max98095->bq_enum.texts = max98095->bq_texts; 2142 max98095->bq_enum.texts = max98095->bq_texts;
2140 max98095->bq_enum.max = max98095->bq_textcnt; 2143 max98095->bq_enum.max = max98095->bq_textcnt;
2141 2144
2142 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 2145 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
2143 if (ret != 0) 2146 if (ret != 0)
2144 dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret); 2147 dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret);
2145 } 2148 }
2146 2149
2147 static void max98095_handle_pdata(struct snd_soc_codec *codec) 2150 static void max98095_handle_pdata(struct snd_soc_codec *codec)
2148 { 2151 {
2149 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2152 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2150 struct max98095_pdata *pdata = max98095->pdata; 2153 struct max98095_pdata *pdata = max98095->pdata;
2151 u8 regval = 0; 2154 u8 regval = 0;
2152 2155
2153 if (!pdata) { 2156 if (!pdata) {
2154 dev_dbg(codec->dev, "No platform data\n"); 2157 dev_dbg(codec->dev, "No platform data\n");
2155 return; 2158 return;
2156 } 2159 }
2157 2160
2158 /* Configure mic for analog/digital mic mode */ 2161 /* Configure mic for analog/digital mic mode */
2159 if (pdata->digmic_left_mode) 2162 if (pdata->digmic_left_mode)
2160 regval |= M98095_DIGMIC_L; 2163 regval |= M98095_DIGMIC_L;
2161 2164
2162 if (pdata->digmic_right_mode) 2165 if (pdata->digmic_right_mode)
2163 regval |= M98095_DIGMIC_R; 2166 regval |= M98095_DIGMIC_R;
2164 2167
2165 snd_soc_write(codec, M98095_087_CFG_MIC, regval); 2168 snd_soc_write(codec, M98095_087_CFG_MIC, regval);
2166 2169
2167 /* Configure equalizers */ 2170 /* Configure equalizers */
2168 if (pdata->eq_cfgcnt) 2171 if (pdata->eq_cfgcnt)
2169 max98095_handle_eq_pdata(codec); 2172 max98095_handle_eq_pdata(codec);
2170 2173
2171 /* Configure bi-quad filters */ 2174 /* Configure bi-quad filters */
2172 if (pdata->bq_cfgcnt) 2175 if (pdata->bq_cfgcnt)
2173 max98095_handle_bq_pdata(codec); 2176 max98095_handle_bq_pdata(codec);
2174 } 2177 }
2175 2178
2179 static irqreturn_t max98095_report_jack(int irq, void *data)
2180 {
2181 struct snd_soc_codec *codec = data;
2182 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2183 unsigned int value;
2184 int hp_report = 0;
2185 int mic_report = 0;
2186
2187 /* Read the Jack Status Register */
2188 value = snd_soc_read(codec, M98095_007_JACK_AUTO_STS);
2189
2190 /* If ddone is not set, then detection isn't finished yet */
2191 if ((value & M98095_DDONE) == 0)
2192 return IRQ_NONE;
2193
2194 /* if hp, check its bit, and if set, clear it */
2195 if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
2196 max98095->headphone_jack)
2197 hp_report |= SND_JACK_HEADPHONE;
2198
2199 /* if mic, check its bit, and if set, clear it */
2200 if ((value & M98095_MIC_IN) && max98095->mic_jack)
2201 mic_report |= SND_JACK_MICROPHONE;
2202
2203 if (max98095->headphone_jack == max98095->mic_jack) {
2204 snd_soc_jack_report(max98095->headphone_jack,
2205 hp_report | mic_report,
2206 SND_JACK_HEADSET);
2207 } else {
2208 if (max98095->headphone_jack)
2209 snd_soc_jack_report(max98095->headphone_jack,
2210 hp_report, SND_JACK_HEADPHONE);
2211 if (max98095->mic_jack)
2212 snd_soc_jack_report(max98095->mic_jack,
2213 mic_report, SND_JACK_MICROPHONE);
2214 }
2215
2216 return IRQ_HANDLED;
2217 }
2218
2219 int max98095_jack_detect_enable(struct snd_soc_codec *codec)
2220 {
2221 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2222 int ret = 0;
2223 int detect_enable = M98095_JDEN;
2224 unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
2225
2226 if (max98095->pdata->jack_detect_pin5en)
2227 detect_enable |= M98095_PIN5EN;
2228
2229 if (max98095->jack_detect_delay)
2230 slew = max98095->jack_detect_delay;
2231
2232 ret = snd_soc_write(codec, M98095_08E_JACK_DC_SLEW, slew);
2233 if (ret < 0) {
2234 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2235 return ret;
2236 }
2237
2238 /* configure auto detection to be enabled */
2239 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, detect_enable);
2240 if (ret < 0) {
2241 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2242 return ret;
2243 }
2244
2245 return ret;
2246 }
2247
2248 int max98095_jack_detect_disable(struct snd_soc_codec *codec)
2249 {
2250 int ret = 0;
2251
2252 /* configure auto detection to be disabled */
2253 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, 0x0);
2254 if (ret < 0) {
2255 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2256 return ret;
2257 }
2258
2259 return ret;
2260 }
2261
2262 int max98095_jack_detect(struct snd_soc_codec *codec,
2263 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
2264 {
2265 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2266 struct i2c_client *client = to_i2c_client(codec->dev);
2267 int ret = 0;
2268
2269 max98095->headphone_jack = hp_jack;
2270 max98095->mic_jack = mic_jack;
2271
2272 /* only progress if we have at least 1 jack pointer */
2273 if (!hp_jack && !mic_jack)
2274 return -EINVAL;
2275
2276 max98095_jack_detect_enable(codec);
2277
2278 /* enable interrupts for headphone jack detection */
2279 ret = snd_soc_update_bits(codec, M98095_013_JACK_INT_EN,
2280 M98095_IDDONE, M98095_IDDONE);
2281 if (ret < 0) {
2282 dev_err(codec->dev, "Failed to cfg jack irqs %d\n", ret);
2283 return ret;
2284 }
2285
2286 max98095_report_jack(client->irq, codec);
2287 return 0;
2288 }
2289
2176 #ifdef CONFIG_PM 2290 #ifdef CONFIG_PM
2177 static int max98095_suspend(struct snd_soc_codec *codec) 2291 static int max98095_suspend(struct snd_soc_codec *codec)
2178 { 2292 {
2293 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2294
2295 if (max98095->headphone_jack || max98095->mic_jack)
2296 max98095_jack_detect_disable(codec);
2297
2179 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); 2298 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
2180 2299
2181 return 0; 2300 return 0;
2182 } 2301 }
2183 2302
2184 static int max98095_resume(struct snd_soc_codec *codec) 2303 static int max98095_resume(struct snd_soc_codec *codec)
2185 { 2304 {
2305 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2306 struct i2c_client *client = to_i2c_client(codec->dev);
2307
2186 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2308 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2187 2309
2310 if (max98095->headphone_jack || max98095->mic_jack) {
2311 max98095_jack_detect_enable(codec);
2312 max98095_report_jack(client->irq, codec);
2313 }
2314
2188 return 0; 2315 return 0;
2189 } 2316 }
2190 #else 2317 #else
2191 #define max98095_suspend NULL 2318 #define max98095_suspend NULL
2192 #define max98095_resume NULL 2319 #define max98095_resume NULL
2193 #endif 2320 #endif
2194 2321
2195 static int max98095_reset(struct snd_soc_codec *codec) 2322 static int max98095_reset(struct snd_soc_codec *codec)
2196 { 2323 {
2197 int i, ret; 2324 int i, ret;
2198 2325
2199 /* Gracefully reset the DSP core and the codec hardware 2326 /* Gracefully reset the DSP core and the codec hardware
2200 * in a proper sequence */ 2327 * in a proper sequence */
2201 ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0); 2328 ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0);
2202 if (ret < 0) { 2329 if (ret < 0) {
2203 dev_err(codec->dev, "Failed to reset DSP: %d\n", ret); 2330 dev_err(codec->dev, "Failed to reset DSP: %d\n", ret);
2204 return ret; 2331 return ret;
2205 } 2332 }
2206 2333
2207 ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0); 2334 ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0);
2208 if (ret < 0) { 2335 if (ret < 0) {
2209 dev_err(codec->dev, "Failed to reset codec: %d\n", ret); 2336 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
2210 return ret; 2337 return ret;
2211 } 2338 }
2212 2339
2213 /* Reset to hardware default for registers, as there is not 2340 /* Reset to hardware default for registers, as there is not
2214 * a soft reset hardware control register */ 2341 * a soft reset hardware control register */
2215 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { 2342 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
2216 ret = snd_soc_write(codec, i, max98095_reg_def[i]); 2343 ret = snd_soc_write(codec, i, max98095_reg_def[i]);
2217 if (ret < 0) { 2344 if (ret < 0) {
2218 dev_err(codec->dev, "Failed to reset: %d\n", ret); 2345 dev_err(codec->dev, "Failed to reset: %d\n", ret);
2219 return ret; 2346 return ret;
2220 } 2347 }
2221 } 2348 }
2222 2349
2223 return ret; 2350 return ret;
2224 } 2351 }
2225 2352
2226 static int max98095_probe(struct snd_soc_codec *codec) 2353 static int max98095_probe(struct snd_soc_codec *codec)
2227 { 2354 {
2228 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2355 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2229 struct max98095_cdata *cdata; 2356 struct max98095_cdata *cdata;
2357 struct i2c_client *client;
2230 int ret = 0; 2358 int ret = 0;
2231 2359
2232 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 2360 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
2233 if (ret != 0) { 2361 if (ret != 0) {
2234 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 2362 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2235 return ret; 2363 return ret;
2236 } 2364 }
2237 2365
2238 /* reset the codec, the DSP core, and disable all interrupts */ 2366 /* reset the codec, the DSP core, and disable all interrupts */
2239 max98095_reset(codec); 2367 max98095_reset(codec);
2240 2368
2369 client = to_i2c_client(codec->dev);
2370
2241 /* initialize private data */ 2371 /* initialize private data */
2242 2372
2243 max98095->sysclk = (unsigned)-1; 2373 max98095->sysclk = (unsigned)-1;
2244 max98095->eq_textcnt = 0; 2374 max98095->eq_textcnt = 0;
2245 max98095->bq_textcnt = 0; 2375 max98095->bq_textcnt = 0;
2246 2376
2247 cdata = &max98095->dai[0]; 2377 cdata = &max98095->dai[0];
2248 cdata->rate = (unsigned)-1; 2378 cdata->rate = (unsigned)-1;
2249 cdata->fmt = (unsigned)-1; 2379 cdata->fmt = (unsigned)-1;
2250 cdata->eq_sel = 0; 2380 cdata->eq_sel = 0;
2251 cdata->bq_sel = 0; 2381 cdata->bq_sel = 0;
2252 2382
2253 cdata = &max98095->dai[1]; 2383 cdata = &max98095->dai[1];
2254 cdata->rate = (unsigned)-1; 2384 cdata->rate = (unsigned)-1;
2255 cdata->fmt = (unsigned)-1; 2385 cdata->fmt = (unsigned)-1;
2256 cdata->eq_sel = 0; 2386 cdata->eq_sel = 0;
2257 cdata->bq_sel = 0; 2387 cdata->bq_sel = 0;
2258 2388
2259 cdata = &max98095->dai[2]; 2389 cdata = &max98095->dai[2];
2260 cdata->rate = (unsigned)-1; 2390 cdata->rate = (unsigned)-1;
2261 cdata->fmt = (unsigned)-1; 2391 cdata->fmt = (unsigned)-1;
2262 cdata->eq_sel = 0; 2392 cdata->eq_sel = 0;
2263 cdata->bq_sel = 0; 2393 cdata->bq_sel = 0;
2264 2394
2265 max98095->lin_state = 0; 2395 max98095->lin_state = 0;
2266 max98095->mic1pre = 0; 2396 max98095->mic1pre = 0;
2267 max98095->mic2pre = 0; 2397 max98095->mic2pre = 0;
2268 2398
2399 if (client->irq) {
2400 /* register an audio interrupt */
2401 ret = request_threaded_irq(client->irq, NULL,
2402 max98095_report_jack,
2403 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2404 "max98095", codec);
2405 if (ret) {
2406 dev_err(codec->dev, "Failed to request IRQ: %d\n", ret);
2407 goto err_access;
2408 }
2409 }
2410
2269 ret = snd_soc_read(codec, M98095_0FF_REV_ID); 2411 ret = snd_soc_read(codec, M98095_0FF_REV_ID);
2270 if (ret < 0) { 2412 if (ret < 0) {
2271 dev_err(codec->dev, "Failure reading hardware revision: %d\n", 2413 dev_err(codec->dev, "Failure reading hardware revision: %d\n",
2272 ret); 2414 ret);
2273 goto err_access; 2415 goto err_irq;
2274 } 2416 }
2275 dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A'); 2417 dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
2276 2418
2277 snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV); 2419 snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV);
2278 2420
2279 /* initialize registers cache to hardware default */ 2421 /* initialize registers cache to hardware default */
2280 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2422 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2281 2423
2282 snd_soc_write(codec, M98095_048_MIX_DAC_LR, 2424 snd_soc_write(codec, M98095_048_MIX_DAC_LR,
2283 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR); 2425 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
2284 2426
2285 snd_soc_write(codec, M98095_049_MIX_DAC_M, 2427 snd_soc_write(codec, M98095_049_MIX_DAC_M,
2286 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM); 2428 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
2287 2429
2288 snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM); 2430 snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
2289 snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL); 2431 snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL);
2290 snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL); 2432 snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL);
2291 2433
2292 snd_soc_write(codec, M98095_02C_DAI1_IOCFG, 2434 snd_soc_write(codec, M98095_02C_DAI1_IOCFG,
2293 M98095_S1NORMAL|M98095_SDATA); 2435 M98095_S1NORMAL|M98095_SDATA);
2294 2436
2295 snd_soc_write(codec, M98095_036_DAI2_IOCFG, 2437 snd_soc_write(codec, M98095_036_DAI2_IOCFG,
2296 M98095_S2NORMAL|M98095_SDATA); 2438 M98095_S2NORMAL|M98095_SDATA);
2297 2439
2298 snd_soc_write(codec, M98095_040_DAI3_IOCFG, 2440 snd_soc_write(codec, M98095_040_DAI3_IOCFG,
2299 M98095_S3NORMAL|M98095_SDATA); 2441 M98095_S3NORMAL|M98095_SDATA);
2300 2442
2301 max98095_handle_pdata(codec); 2443 max98095_handle_pdata(codec);
2302 2444
2303 /* take the codec out of the shut down */ 2445 /* take the codec out of the shut down */
2304 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN, 2446 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN,
2305 M98095_SHDNRUN); 2447 M98095_SHDNRUN);
2306 2448
2307 max98095_add_widgets(codec); 2449 max98095_add_widgets(codec);
2308 2450
2451 return 0;
2452
2453 err_irq:
2454 if (client->irq)
2455 free_irq(client->irq, codec);
2309 err_access: 2456 err_access:
2310 return ret; 2457 return ret;
2311 } 2458 }
2312 2459
2313 static int max98095_remove(struct snd_soc_codec *codec) 2460 static int max98095_remove(struct snd_soc_codec *codec)
2314 { 2461 {
2462 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2463 struct i2c_client *client = to_i2c_client(codec->dev);
2464
2315 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); 2465 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
2466
2467 if (max98095->headphone_jack || max98095->mic_jack)
2468 max98095_jack_detect_disable(codec);
2469
2470 if (client->irq)
2471 free_irq(client->irq, codec);
2316 2472
2317 return 0; 2473 return 0;
2318 } 2474 }
2319 2475
2320 static struct snd_soc_codec_driver soc_codec_dev_max98095 = { 2476 static struct snd_soc_codec_driver soc_codec_dev_max98095 = {
2321 .probe = max98095_probe, 2477 .probe = max98095_probe,
2322 .remove = max98095_remove, 2478 .remove = max98095_remove,
2323 .suspend = max98095_suspend, 2479 .suspend = max98095_suspend,
2324 .resume = max98095_resume, 2480 .resume = max98095_resume,
2325 .set_bias_level = max98095_set_bias_level, 2481 .set_bias_level = max98095_set_bias_level,
2326 .reg_cache_size = ARRAY_SIZE(max98095_reg_def), 2482 .reg_cache_size = ARRAY_SIZE(max98095_reg_def),
2327 .reg_word_size = sizeof(u8), 2483 .reg_word_size = sizeof(u8),
2328 .reg_cache_default = max98095_reg_def, 2484 .reg_cache_default = max98095_reg_def,
2329 .readable_register = max98095_readable, 2485 .readable_register = max98095_readable,
2330 .volatile_register = max98095_volatile, 2486 .volatile_register = max98095_volatile,
2331 .dapm_widgets = max98095_dapm_widgets, 2487 .dapm_widgets = max98095_dapm_widgets,
2332 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets), 2488 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
2333 .dapm_routes = max98095_audio_map, 2489 .dapm_routes = max98095_audio_map,
2334 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map), 2490 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map),
2335 }; 2491 };
2336 2492
2337 static int max98095_i2c_probe(struct i2c_client *i2c, 2493 static int max98095_i2c_probe(struct i2c_client *i2c,
2338 const struct i2c_device_id *id) 2494 const struct i2c_device_id *id)
2339 { 2495 {
2340 struct max98095_priv *max98095; 2496 struct max98095_priv *max98095;
2341 int ret; 2497 int ret;
2342 2498
2343 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv), 2499 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv),
2344 GFP_KERNEL); 2500 GFP_KERNEL);
2345 if (max98095 == NULL) 2501 if (max98095 == NULL)
2346 return -ENOMEM; 2502 return -ENOMEM;
2347 2503
2348 max98095->devtype = id->driver_data; 2504 max98095->devtype = id->driver_data;
2349 i2c_set_clientdata(i2c, max98095); 2505 i2c_set_clientdata(i2c, max98095);
2350 max98095->pdata = i2c->dev.platform_data; 2506 max98095->pdata = i2c->dev.platform_data;
2351 2507
2352 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095, 2508 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095,
2353 max98095_dai, ARRAY_SIZE(max98095_dai)); 2509 max98095_dai, ARRAY_SIZE(max98095_dai));
2354 return ret; 2510 return ret;
2355 } 2511 }
2356 2512
2357 static int __devexit max98095_i2c_remove(struct i2c_client *client) 2513 static int __devexit max98095_i2c_remove(struct i2c_client *client)
2358 { 2514 {
2359 snd_soc_unregister_codec(&client->dev); 2515 snd_soc_unregister_codec(&client->dev);
2360 return 0; 2516 return 0;
2361 } 2517 }
2362 2518
2363 static const struct i2c_device_id max98095_i2c_id[] = { 2519 static const struct i2c_device_id max98095_i2c_id[] = {
2364 { "max98095", MAX98095 }, 2520 { "max98095", MAX98095 },
2365 { } 2521 { }
2366 }; 2522 };
2367 MODULE_DEVICE_TABLE(i2c, max98095_i2c_id); 2523 MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
2368 2524
2369 static struct i2c_driver max98095_i2c_driver = { 2525 static struct i2c_driver max98095_i2c_driver = {
2370 .driver = { 2526 .driver = {
2371 .name = "max98095", 2527 .name = "max98095",
2372 .owner = THIS_MODULE, 2528 .owner = THIS_MODULE,
2373 }, 2529 },
2374 .probe = max98095_i2c_probe, 2530 .probe = max98095_i2c_probe,
2375 .remove = __devexit_p(max98095_i2c_remove), 2531 .remove = __devexit_p(max98095_i2c_remove),
2376 .id_table = max98095_i2c_id, 2532 .id_table = max98095_i2c_id,
2377 }; 2533 };
2378 2534
2379 static int __init max98095_init(void) 2535 static int __init max98095_init(void)
2380 { 2536 {
2381 int ret; 2537 int ret;
2382 2538
2383 ret = i2c_add_driver(&max98095_i2c_driver); 2539 ret = i2c_add_driver(&max98095_i2c_driver);
2384 if (ret) 2540 if (ret)
2385 pr_err("Failed to register max98095 I2C driver: %d\n", ret); 2541 pr_err("Failed to register max98095 I2C driver: %d\n", ret);
2386 2542
2387 return ret; 2543 return ret;
2388 } 2544 }
2389 module_init(max98095_init); 2545 module_init(max98095_init);
2390 2546
2391 static void __exit max98095_exit(void) 2547 static void __exit max98095_exit(void)
2392 { 2548 {
2393 i2c_del_driver(&max98095_i2c_driver); 2549 i2c_del_driver(&max98095_i2c_driver);
2394 } 2550 }
2395 module_exit(max98095_exit); 2551 module_exit(max98095_exit);
2396 2552
2397 MODULE_DESCRIPTION("ALSA SoC MAX98095 driver"); 2553 MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
2398 MODULE_AUTHOR("Peter Hsiang"); 2554 MODULE_AUTHOR("Peter Hsiang");
2399 MODULE_LICENSE("GPL"); 2555 MODULE_LICENSE("GPL");
2400 2556
sound/soc/codecs/max98095.h
Diff comments   View file @ 9dd90c5
1 /* 1 /*
2 * max98095.h -- MAX98095 ALSA SoC Audio driver 2 * max98095.h -- MAX98095 ALSA SoC Audio driver
3 * 3 *
4 * Copyright 2011 Maxim Integrated Products 4 * Copyright 2011 Maxim Integrated Products
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11 #ifndef _MAX98095_H 11 #ifndef _MAX98095_H
12 #define _MAX98095_H 12 #define _MAX98095_H
13 13
14 /* 14 /*
15 * MAX98095 Registers Definition 15 * MAX98095 Registers Definition
16 */ 16 */
17 17
18 #define M98095_000_HOST_DATA 0x00 18 #define M98095_000_HOST_DATA 0x00
19 #define M98095_001_HOST_INT_STS 0x01 19 #define M98095_001_HOST_INT_STS 0x01
20 #define M98095_002_HOST_RSP_STS 0x02 20 #define M98095_002_HOST_RSP_STS 0x02
21 #define M98095_003_HOST_CMD_STS 0x03 21 #define M98095_003_HOST_CMD_STS 0x03
22 #define M98095_004_CODEC_STS 0x04 22 #define M98095_004_CODEC_STS 0x04
23 #define M98095_005_DAI1_ALC_STS 0x05 23 #define M98095_005_DAI1_ALC_STS 0x05
24 #define M98095_006_DAI2_ALC_STS 0x06 24 #define M98095_006_DAI2_ALC_STS 0x06
25 #define M98095_007_JACK_AUTO_STS 0x07 25 #define M98095_007_JACK_AUTO_STS 0x07
26 #define M98095_008_JACK_MANUAL_STS 0x08 26 #define M98095_008_JACK_MANUAL_STS 0x08
27 #define M98095_009_JACK_VBAT_STS 0x09 27 #define M98095_009_JACK_VBAT_STS 0x09
28 #define M98095_00A_ACC_ADC_STS 0x0A 28 #define M98095_00A_ACC_ADC_STS 0x0A
29 #define M98095_00B_MIC_NG_AGC_STS 0x0B 29 #define M98095_00B_MIC_NG_AGC_STS 0x0B
30 #define M98095_00C_SPK_L_VOLT_STS 0x0C 30 #define M98095_00C_SPK_L_VOLT_STS 0x0C
31 #define M98095_00D_SPK_R_VOLT_STS 0x0D 31 #define M98095_00D_SPK_R_VOLT_STS 0x0D
32 #define M98095_00E_TEMP_SENSOR_STS 0x0E 32 #define M98095_00E_TEMP_SENSOR_STS 0x0E
33 #define M98095_00F_HOST_CFG 0x0F 33 #define M98095_00F_HOST_CFG 0x0F
34 #define M98095_010_HOST_INT_CFG 0x10 34 #define M98095_010_HOST_INT_CFG 0x10
35 #define M98095_011_HOST_INT_EN 0x11 35 #define M98095_011_HOST_INT_EN 0x11
36 #define M98095_012_CODEC_INT_EN 0x12 36 #define M98095_012_CODEC_INT_EN 0x12
37 #define M98095_013_JACK_INT_EN 0x13 37 #define M98095_013_JACK_INT_EN 0x13
38 #define M98095_014_JACK_INT_EN 0x14 38 #define M98095_014_JACK_INT_EN 0x14
39 #define M98095_015_DEC 0x15 39 #define M98095_015_DEC 0x15
40 #define M98095_016_RESERVED 0x16 40 #define M98095_016_RESERVED 0x16
41 #define M98095_017_RESERVED 0x17 41 #define M98095_017_RESERVED 0x17
42 #define M98095_018_KEYCODE3 0x18 42 #define M98095_018_KEYCODE3 0x18
43 #define M98095_019_KEYCODE2 0x19 43 #define M98095_019_KEYCODE2 0x19
44 #define M98095_01A_KEYCODE1 0x1A 44 #define M98095_01A_KEYCODE1 0x1A
45 #define M98095_01B_KEYCODE0 0x1B 45 #define M98095_01B_KEYCODE0 0x1B
46 #define M98095_01C_OEMCODE1 0x1C 46 #define M98095_01C_OEMCODE1 0x1C
47 #define M98095_01D_OEMCODE0 0x1D 47 #define M98095_01D_OEMCODE0 0x1D
48 #define M98095_01E_XCFG1 0x1E 48 #define M98095_01E_XCFG1 0x1E
49 #define M98095_01F_XCFG2 0x1F 49 #define M98095_01F_XCFG2 0x1F
50 #define M98095_020_XCFG3 0x20 50 #define M98095_020_XCFG3 0x20
51 #define M98095_021_XCFG4 0x21 51 #define M98095_021_XCFG4 0x21
52 #define M98095_022_XCFG5 0x22 52 #define M98095_022_XCFG5 0x22
53 #define M98095_023_XCFG6 0x23 53 #define M98095_023_XCFG6 0x23
54 #define M98095_024_XGPIO 0x24 54 #define M98095_024_XGPIO 0x24
55 #define M98095_025_XCLKCFG 0x25 55 #define M98095_025_XCLKCFG 0x25
56 #define M98095_026_SYS_CLK 0x26 56 #define M98095_026_SYS_CLK 0x26
57 #define M98095_027_DAI1_CLKMODE 0x27 57 #define M98095_027_DAI1_CLKMODE 0x27
58 #define M98095_028_DAI1_CLKCFG_HI 0x28 58 #define M98095_028_DAI1_CLKCFG_HI 0x28
59 #define M98095_029_DAI1_CLKCFG_LO 0x29 59 #define M98095_029_DAI1_CLKCFG_LO 0x29
60 #define M98095_02A_DAI1_FORMAT 0x2A 60 #define M98095_02A_DAI1_FORMAT 0x2A
61 #define M98095_02B_DAI1_CLOCK 0x2B 61 #define M98095_02B_DAI1_CLOCK 0x2B
62 #define M98095_02C_DAI1_IOCFG 0x2C 62 #define M98095_02C_DAI1_IOCFG 0x2C
63 #define M98095_02D_DAI1_TDM 0x2D 63 #define M98095_02D_DAI1_TDM 0x2D
64 #define M98095_02E_DAI1_FILTERS 0x2E 64 #define M98095_02E_DAI1_FILTERS 0x2E
65 #define M98095_02F_DAI1_LVL1 0x2F 65 #define M98095_02F_DAI1_LVL1 0x2F
66 #define M98095_030_DAI1_LVL2 0x30 66 #define M98095_030_DAI1_LVL2 0x30
67 #define M98095_031_DAI2_CLKMODE 0x31 67 #define M98095_031_DAI2_CLKMODE 0x31
68 #define M98095_032_DAI2_CLKCFG_HI 0x32 68 #define M98095_032_DAI2_CLKCFG_HI 0x32
69 #define M98095_033_DAI2_CLKCFG_LO 0x33 69 #define M98095_033_DAI2_CLKCFG_LO 0x33
70 #define M98095_034_DAI2_FORMAT 0x34 70 #define M98095_034_DAI2_FORMAT 0x34
71 #define M98095_035_DAI2_CLOCK 0x35 71 #define M98095_035_DAI2_CLOCK 0x35
72 #define M98095_036_DAI2_IOCFG 0x36 72 #define M98095_036_DAI2_IOCFG 0x36
73 #define M98095_037_DAI2_TDM 0x37 73 #define M98095_037_DAI2_TDM 0x37
74 #define M98095_038_DAI2_FILTERS 0x38 74 #define M98095_038_DAI2_FILTERS 0x38
75 #define M98095_039_DAI2_LVL1 0x39 75 #define M98095_039_DAI2_LVL1 0x39
76 #define M98095_03A_DAI2_LVL2 0x3A 76 #define M98095_03A_DAI2_LVL2 0x3A
77 #define M98095_03B_DAI3_CLKMODE 0x3B 77 #define M98095_03B_DAI3_CLKMODE 0x3B
78 #define M98095_03C_DAI3_CLKCFG_HI 0x3C 78 #define M98095_03C_DAI3_CLKCFG_HI 0x3C
79 #define M98095_03D_DAI3_CLKCFG_LO 0x3D 79 #define M98095_03D_DAI3_CLKCFG_LO 0x3D
80 #define M98095_03E_DAI3_FORMAT 0x3E 80 #define M98095_03E_DAI3_FORMAT 0x3E
81 #define M98095_03F_DAI3_CLOCK 0x3F 81 #define M98095_03F_DAI3_CLOCK 0x3F
82 #define M98095_040_DAI3_IOCFG 0x40 82 #define M98095_040_DAI3_IOCFG 0x40
83 #define M98095_041_DAI3_TDM 0x41 83 #define M98095_041_DAI3_TDM 0x41
84 #define M98095_042_DAI3_FILTERS 0x42 84 #define M98095_042_DAI3_FILTERS 0x42
85 #define M98095_043_DAI3_LVL1 0x43 85 #define M98095_043_DAI3_LVL1 0x43
86 #define M98095_044_DAI3_LVL2 0x44 86 #define M98095_044_DAI3_LVL2 0x44
87 #define M98095_045_CFG_DSP 0x45 87 #define M98095_045_CFG_DSP 0x45
88 #define M98095_046_DAC_CTRL1 0x46 88 #define M98095_046_DAC_CTRL1 0x46
89 #define M98095_047_DAC_CTRL2 0x47 89 #define M98095_047_DAC_CTRL2 0x47
90 #define M98095_048_MIX_DAC_LR 0x48 90 #define M98095_048_MIX_DAC_LR 0x48
91 #define M98095_049_MIX_DAC_M 0x49 91 #define M98095_049_MIX_DAC_M 0x49
92 #define M98095_04A_MIX_ADC_LEFT 0x4A 92 #define M98095_04A_MIX_ADC_LEFT 0x4A
93 #define M98095_04B_MIX_ADC_RIGHT 0x4B 93 #define M98095_04B_MIX_ADC_RIGHT 0x4B
94 #define M98095_04C_MIX_HP_LEFT 0x4C 94 #define M98095_04C_MIX_HP_LEFT 0x4C
95 #define M98095_04D_MIX_HP_RIGHT 0x4D 95 #define M98095_04D_MIX_HP_RIGHT 0x4D
96 #define M98095_04E_CFG_HP 0x4E 96 #define M98095_04E_CFG_HP 0x4E
97 #define M98095_04F_MIX_RCV 0x4F 97 #define M98095_04F_MIX_RCV 0x4F
98 #define M98095_050_MIX_SPK_LEFT 0x50 98 #define M98095_050_MIX_SPK_LEFT 0x50
99 #define M98095_051_MIX_SPK_RIGHT 0x51 99 #define M98095_051_MIX_SPK_RIGHT 0x51
100 #define M98095_052_MIX_SPK_CFG 0x52 100 #define M98095_052_MIX_SPK_CFG 0x52
101 #define M98095_053_MIX_LINEOUT1 0x53 101 #define M98095_053_MIX_LINEOUT1 0x53
102 #define M98095_054_MIX_LINEOUT2 0x54 102 #define M98095_054_MIX_LINEOUT2 0x54
103 #define M98095_055_MIX_LINEOUT_CFG 0x55 103 #define M98095_055_MIX_LINEOUT_CFG 0x55
104 #define M98095_056_LVL_SIDETONE_DAI12 0x56 104 #define M98095_056_LVL_SIDETONE_DAI12 0x56
105 #define M98095_057_LVL_SIDETONE_DAI3 0x57 105 #define M98095_057_LVL_SIDETONE_DAI3 0x57
106 #define M98095_058_LVL_DAI1_PLAY 0x58 106 #define M98095_058_LVL_DAI1_PLAY 0x58
107 #define M98095_059_LVL_DAI1_EQ 0x59 107 #define M98095_059_LVL_DAI1_EQ 0x59
108 #define M98095_05A_LVL_DAI2_PLAY 0x5A 108 #define M98095_05A_LVL_DAI2_PLAY 0x5A
109 #define M98095_05B_LVL_DAI2_EQ 0x5B 109 #define M98095_05B_LVL_DAI2_EQ 0x5B
110 #define M98095_05C_LVL_DAI3_PLAY 0x5C 110 #define M98095_05C_LVL_DAI3_PLAY 0x5C
111 #define M98095_05D_LVL_ADC_L 0x5D 111 #define M98095_05D_LVL_ADC_L 0x5D
112 #define M98095_05E_LVL_ADC_R 0x5E 112 #define M98095_05E_LVL_ADC_R 0x5E
113 #define M98095_05F_LVL_MIC1 0x5F 113 #define M98095_05F_LVL_MIC1 0x5F
114 #define M98095_060_LVL_MIC2 0x60 114 #define M98095_060_LVL_MIC2 0x60
115 #define M98095_061_LVL_LINEIN 0x61 115 #define M98095_061_LVL_LINEIN 0x61
116 #define M98095_062_LVL_LINEOUT1 0x62 116 #define M98095_062_LVL_LINEOUT1 0x62
117 #define M98095_063_LVL_LINEOUT2 0x63 117 #define M98095_063_LVL_LINEOUT2 0x63
118 #define M98095_064_LVL_HP_L 0x64 118 #define M98095_064_LVL_HP_L 0x64
119 #define M98095_065_LVL_HP_R 0x65 119 #define M98095_065_LVL_HP_R 0x65
120 #define M98095_066_LVL_RCV 0x66 120 #define M98095_066_LVL_RCV 0x66
121 #define M98095_067_LVL_SPK_L 0x67 121 #define M98095_067_LVL_SPK_L 0x67
122 #define M98095_068_LVL_SPK_R 0x68 122 #define M98095_068_LVL_SPK_R 0x68
123 #define M98095_069_MICAGC_CFG 0x69 123 #define M98095_069_MICAGC_CFG 0x69
124 #define M98095_06A_MICAGC_THRESH 0x6A 124 #define M98095_06A_MICAGC_THRESH 0x6A
125 #define M98095_06B_SPK_NOISEGATE 0x6B 125 #define M98095_06B_SPK_NOISEGATE 0x6B
126 #define M98095_06C_DAI1_ALC1_TIME 0x6C 126 #define M98095_06C_DAI1_ALC1_TIME 0x6C
127 #define M98095_06D_DAI1_ALC1_COMP 0x6D 127 #define M98095_06D_DAI1_ALC1_COMP 0x6D
128 #define M98095_06E_DAI1_ALC1_EXPN 0x6E 128 #define M98095_06E_DAI1_ALC1_EXPN 0x6E
129 #define M98095_06F_DAI1_ALC1_GAIN 0x6F 129 #define M98095_06F_DAI1_ALC1_GAIN 0x6F
130 #define M98095_070_DAI1_ALC2_TIME 0x70 130 #define M98095_070_DAI1_ALC2_TIME 0x70
131 #define M98095_071_DAI1_ALC2_COMP 0x71 131 #define M98095_071_DAI1_ALC2_COMP 0x71
132 #define M98095_072_DAI1_ALC2_EXPN 0x72 132 #define M98095_072_DAI1_ALC2_EXPN 0x72
133 #define M98095_073_DAI1_ALC2_GAIN 0x73 133 #define M98095_073_DAI1_ALC2_GAIN 0x73
134 #define M98095_074_DAI1_ALC3_TIME 0x74 134 #define M98095_074_DAI1_ALC3_TIME 0x74
135 #define M98095_075_DAI1_ALC3_COMP 0x75 135 #define M98095_075_DAI1_ALC3_COMP 0x75
136 #define M98095_076_DAI1_ALC3_EXPN 0x76 136 #define M98095_076_DAI1_ALC3_EXPN 0x76
137 #define M98095_077_DAI1_ALC3_GAIN 0x77 137 #define M98095_077_DAI1_ALC3_GAIN 0x77
138 #define M98095_078_DAI2_ALC1_TIME 0x78 138 #define M98095_078_DAI2_ALC1_TIME 0x78
139 #define M98095_079_DAI2_ALC1_COMP 0x79 139 #define M98095_079_DAI2_ALC1_COMP 0x79
140 #define M98095_07A_DAI2_ALC1_EXPN 0x7A 140 #define M98095_07A_DAI2_ALC1_EXPN 0x7A
141 #define M98095_07B_DAI2_ALC1_GAIN 0x7B 141 #define M98095_07B_DAI2_ALC1_GAIN 0x7B
142 #define M98095_07C_DAI2_ALC2_TIME 0x7C 142 #define M98095_07C_DAI2_ALC2_TIME 0x7C
143 #define M98095_07D_DAI2_ALC2_COMP 0x7D 143 #define M98095_07D_DAI2_ALC2_COMP 0x7D
144 #define M98095_07E_DAI2_ALC2_EXPN 0x7E 144 #define M98095_07E_DAI2_ALC2_EXPN 0x7E
145 #define M98095_07F_DAI2_ALC2_GAIN 0x7F 145 #define M98095_07F_DAI2_ALC2_GAIN 0x7F
146 #define M98095_080_DAI2_ALC3_TIME 0x80 146 #define M98095_080_DAI2_ALC3_TIME 0x80
147 #define M98095_081_DAI2_ALC3_COMP 0x81 147 #define M98095_081_DAI2_ALC3_COMP 0x81
148 #define M98095_082_DAI2_ALC3_EXPN 0x82 148 #define M98095_082_DAI2_ALC3_EXPN 0x82
149 #define M98095_083_DAI2_ALC3_GAIN 0x83 149 #define M98095_083_DAI2_ALC3_GAIN 0x83
150 #define M98095_084_HP_NOISE_GATE 0x84 150 #define M98095_084_HP_NOISE_GATE 0x84
151 #define M98095_085_AUX_ADC 0x85 151 #define M98095_085_AUX_ADC 0x85
152 #define M98095_086_CFG_LINE 0x86 152 #define M98095_086_CFG_LINE 0x86
153 #define M98095_087_CFG_MIC 0x87 153 #define M98095_087_CFG_MIC 0x87
154 #define M98095_088_CFG_LEVEL 0x88 154 #define M98095_088_CFG_LEVEL 0x88
155 #define M98095_089_JACK_DET_AUTO 0x89 155 #define M98095_089_JACK_DET_AUTO 0x89
156 #define M98095_08A_JACK_DET_MANUAL 0x8A 156 #define M98095_08A_JACK_DET_MANUAL 0x8A
157 #define M98095_08B_JACK_KEYSCAN_DBC 0x8B 157 #define M98095_08B_JACK_KEYSCAN_DBC 0x8B
158 #define M98095_08C_JACK_KEYSCAN_DLY 0x8C 158 #define M98095_08C_JACK_KEYSCAN_DLY 0x8C
159 #define M98095_08D_JACK_KEY_THRESH 0x8D 159 #define M98095_08D_JACK_KEY_THRESH 0x8D
160 #define M98095_08E_JACK_DC_SLEW 0x8E 160 #define M98095_08E_JACK_DC_SLEW 0x8E
161 #define M98095_08F_JACK_TEST_CFG 0x8F 161 #define M98095_08F_JACK_TEST_CFG 0x8F
162 #define M98095_090_PWR_EN_IN 0x90 162 #define M98095_090_PWR_EN_IN 0x90
163 #define M98095_091_PWR_EN_OUT 0x91 163 #define M98095_091_PWR_EN_OUT 0x91
164 #define M98095_092_PWR_EN_OUT 0x92 164 #define M98095_092_PWR_EN_OUT 0x92
165 #define M98095_093_BIAS_CTRL 0x93 165 #define M98095_093_BIAS_CTRL 0x93
166 #define M98095_094_PWR_DAC_21 0x94 166 #define M98095_094_PWR_DAC_21 0x94
167 #define M98095_095_PWR_DAC_03 0x95 167 #define M98095_095_PWR_DAC_03 0x95
168 #define M98095_096_PWR_DAC_CK 0x96 168 #define M98095_096_PWR_DAC_CK 0x96
169 #define M98095_097_PWR_SYS 0x97 169 #define M98095_097_PWR_SYS 0x97
170 170
171 #define M98095_0FF_REV_ID 0xFF 171 #define M98095_0FF_REV_ID 0xFF
172 172
173 #define M98095_REG_CNT (0xFF+1) 173 #define M98095_REG_CNT (0xFF+1)
174 #define M98095_REG_MAX_CACHED 0X97 174 #define M98095_REG_MAX_CACHED 0X97
175 175
176 /* MAX98095 Registers Bit Fields */ 176 /* MAX98095 Registers Bit Fields */
177 177
178 /* M98095_007_JACK_AUTO_STS */
179 #define M98095_MIC_IN (1<<3)
180 #define M98095_LO_IN (1<<5)
181 #define M98095_HP_IN (1<<6)
182 #define M98095_DDONE (1<<7)
183
178 /* M98095_00F_HOST_CFG */ 184 /* M98095_00F_HOST_CFG */
179 #define M98095_SEG (1<<0) 185 #define M98095_SEG (1<<0)
180 #define M98095_XTEN (1<<1) 186 #define M98095_XTEN (1<<1)
181 #define M98095_MDLLEN (1<<2) 187 #define M98095_MDLLEN (1<<2)
182 188
189 /* M98095_013_JACK_INT_EN */
190 #define M98095_IMIC_IN (1<<3)
191 #define M98095_ILO_IN (1<<5)
192 #define M98095_IHP_IN (1<<6)
193 #define M98095_IDDONE (1<<7)
194
183 /* M98095_027_DAI1_CLKMODE, M98095_031_DAI2_CLKMODE, M98095_03B_DAI3_CLKMODE */ 195 /* M98095_027_DAI1_CLKMODE, M98095_031_DAI2_CLKMODE, M98095_03B_DAI3_CLKMODE */
184 #define M98095_CLKMODE_MASK 0xFF 196 #define M98095_CLKMODE_MASK 0xFF
185 197
186 /* M98095_02A_DAI1_FORMAT, M98095_034_DAI2_FORMAT, M98095_03E_DAI3_FORMAT */ 198 /* M98095_02A_DAI1_FORMAT, M98095_034_DAI2_FORMAT, M98095_03E_DAI3_FORMAT */
187 #define M98095_DAI_MAS (1<<7) 199 #define M98095_DAI_MAS (1<<7)
188 #define M98095_DAI_WCI (1<<6) 200 #define M98095_DAI_WCI (1<<6)
189 #define M98095_DAI_BCI (1<<5) 201 #define M98095_DAI_BCI (1<<5)
190 #define M98095_DAI_DLY (1<<4) 202 #define M98095_DAI_DLY (1<<4)
191 #define M98095_DAI_TDM (1<<2) 203 #define M98095_DAI_TDM (1<<2)
192 #define M98095_DAI_FSW (1<<1) 204 #define M98095_DAI_FSW (1<<1)
193 #define M98095_DAI_WS (1<<0) 205 #define M98095_DAI_WS (1<<0)
194 206
195 /* M98095_02B_DAI1_CLOCK, M98095_035_DAI2_CLOCK, M98095_03F_DAI3_CLOCK */ 207 /* M98095_02B_DAI1_CLOCK, M98095_035_DAI2_CLOCK, M98095_03F_DAI3_CLOCK */
196 #define M98095_DAI_BSEL64 (1<<0) 208 #define M98095_DAI_BSEL64 (1<<0)
197 #define M98095_DAI_DOSR_DIV2 (0<<5) 209 #define M98095_DAI_DOSR_DIV2 (0<<5)
198 #define M98095_DAI_DOSR_DIV4 (1<<5) 210 #define M98095_DAI_DOSR_DIV4 (1<<5)
199 211
200 /* M98095_02C_DAI1_IOCFG, M98095_036_DAI2_IOCFG, M98095_040_DAI3_IOCFG */ 212 /* M98095_02C_DAI1_IOCFG, M98095_036_DAI2_IOCFG, M98095_040_DAI3_IOCFG */
201 #define M98095_S1NORMAL (1<<6) 213 #define M98095_S1NORMAL (1<<6)
202 #define M98095_S2NORMAL (2<<6) 214 #define M98095_S2NORMAL (2<<6)
203 #define M98095_S3NORMAL (3<<6) 215 #define M98095_S3NORMAL (3<<6)
204 #define M98095_SDATA (3<<0) 216 #define M98095_SDATA (3<<0)
205 217
206 /* M98095_02E_DAI1_FILTERS, M98095_038_DAI2_FILTERS, M98095_042_DAI3_FILTERS */ 218 /* M98095_02E_DAI1_FILTERS, M98095_038_DAI2_FILTERS, M98095_042_DAI3_FILTERS */
207 #define M98095_DAI_DHF (1<<3) 219 #define M98095_DAI_DHF (1<<3)
208 220
209 /* M98095_045_DSP_CFG */ 221 /* M98095_045_DSP_CFG */
210 #define M98095_DSPNORMAL (5<<4) 222 #define M98095_DSPNORMAL (5<<4)
211 223
212 /* M98095_048_MIX_DAC_LR */ 224 /* M98095_048_MIX_DAC_LR */
213 #define M98095_DAI1L_TO_DACR (1<<7) 225 #define M98095_DAI1L_TO_DACR (1<<7)
214 #define M98095_DAI1R_TO_DACR (1<<6) 226 #define M98095_DAI1R_TO_DACR (1<<6)
215 #define M98095_DAI2M_TO_DACR (1<<5) 227 #define M98095_DAI2M_TO_DACR (1<<5)
216 #define M98095_DAI1L_TO_DACL (1<<3) 228 #define M98095_DAI1L_TO_DACL (1<<3)
217 #define M98095_DAI1R_TO_DACL (1<<2) 229 #define M98095_DAI1R_TO_DACL (1<<2)
218 #define M98095_DAI2M_TO_DACL (1<<1) 230 #define M98095_DAI2M_TO_DACL (1<<1)
219 #define M98095_DAI3M_TO_DACL (1<<0) 231 #define M98095_DAI3M_TO_DACL (1<<0)
220 232
221 /* M98095_049_MIX_DAC_M */ 233 /* M98095_049_MIX_DAC_M */
222 #define M98095_DAI1L_TO_DACM (1<<3) 234 #define M98095_DAI1L_TO_DACM (1<<3)
223 #define M98095_DAI1R_TO_DACM (1<<2) 235 #define M98095_DAI1R_TO_DACM (1<<2)
224 #define M98095_DAI2M_TO_DACM (1<<1) 236 #define M98095_DAI2M_TO_DACM (1<<1)
225 #define M98095_DAI3M_TO_DACM (1<<0) 237 #define M98095_DAI3M_TO_DACM (1<<0)
226 238
227 /* M98095_04E_MIX_HP_CFG */ 239 /* M98095_04E_MIX_HP_CFG */
228 #define M98095_HPNORMAL (3<<4) 240 #define M98095_HPNORMAL (3<<4)
229 241
230 /* M98095_05F_LVL_MIC1, M98095_060_LVL_MIC2 */ 242 /* M98095_05F_LVL_MIC1, M98095_060_LVL_MIC2 */
231 #define M98095_MICPRE_MASK (3<<5) 243 #define M98095_MICPRE_MASK (3<<5)
232 #define M98095_MICPRE_SHIFT 5 244 #define M98095_MICPRE_SHIFT 5
233 245
234 /* M98095_064_LVL_HP_L, M98095_065_LVL_HP_R */ 246 /* M98095_064_LVL_HP_L, M98095_065_LVL_HP_R */
235 #define M98095_HP_MUTE (1<<7) 247 #define M98095_HP_MUTE (1<<7)
236 248
237 /* M98095_066_LVL_RCV */ 249 /* M98095_066_LVL_RCV */
238 #define M98095_REC_MUTE (1<<7) 250 #define M98095_REC_MUTE (1<<7)
239 251
240 /* M98095_067_LVL_SPK_L, M98095_068_LVL_SPK_R */ 252 /* M98095_067_LVL_SPK_L, M98095_068_LVL_SPK_R */
241 #define M98095_SP_MUTE (1<<7) 253 #define M98095_SP_MUTE (1<<7)
242 254
243 /* M98095_087_CFG_MIC */ 255 /* M98095_087_CFG_MIC */
244 #define M98095_MICSEL_MASK (3<<0) 256 #define M98095_MICSEL_MASK (3<<0)
245 #define M98095_DIGMIC_L (1<<2) 257 #define M98095_DIGMIC_L (1<<2)
246 #define M98095_DIGMIC_R (1<<3) 258 #define M98095_DIGMIC_R (1<<3)
247 #define M98095_DIGMIC2L (1<<4) 259 #define M98095_DIGMIC2L (1<<4)
248 #define M98095_DIGMIC2R (1<<5) 260 #define M98095_DIGMIC2R (1<<5)
249 261
250 /* M98095_088_CFG_LEVEL */ 262 /* M98095_088_CFG_LEVEL */
251 #define M98095_VSEN (1<<6) 263 #define M98095_VSEN (1<<6)
252 #define M98095_ZDEN (1<<5) 264 #define M98095_ZDEN (1<<5)
253 #define M98095_BQ2EN (1<<3) 265 #define M98095_BQ2EN (1<<3)
254 #define M98095_BQ1EN (1<<2) 266 #define M98095_BQ1EN (1<<2)
255 #define M98095_EQ2EN (1<<1) 267 #define M98095_EQ2EN (1<<1)
256 #define M98095_EQ1EN (1<<0) 268 #define M98095_EQ1EN (1<<0)
257 269
270 /* M98095_089_JACK_DET_AUTO */
271 #define M98095_PIN5EN (1<<2)
272 #define M98095_JDEN (1<<7)
273
258 /* M98095_090_PWR_EN_IN */ 274 /* M98095_090_PWR_EN_IN */
259 #define M98095_INEN (1<<7) 275 #define M98095_INEN (1<<7)
260 #define M98095_MB2EN (1<<3) 276 #define M98095_MB2EN (1<<3)
261 #define M98095_MB1EN (1<<2) 277 #define M98095_MB1EN (1<<2)
262 #define M98095_MBEN (3<<2) 278 #define M98095_MBEN (3<<2)
263 #define M98095_ADREN (1<<1) 279 #define M98095_ADREN (1<<1)
264 #define M98095_ADLEN (1<<0) 280 #define M98095_ADLEN (1<<0)
265 281
266 /* M98095_091_PWR_EN_OUT */ 282 /* M98095_091_PWR_EN_OUT */
267 #define M98095_HPLEN (1<<7) 283 #define M98095_HPLEN (1<<7)
268 #define M98095_HPREN (1<<6) 284 #define M98095_HPREN (1<<6)
269 #define M98095_SPLEN (1<<5) 285 #define M98095_SPLEN (1<<5)
270 #define M98095_SPREN (1<<4) 286 #define M98095_SPREN (1<<4)
271 #define M98095_RECEN (1<<3) 287 #define M98095_RECEN (1<<3)
272 #define M98095_DALEN (1<<1) 288 #define M98095_DALEN (1<<1)
273 #define M98095_DAREN (1<<0) 289 #define M98095_DAREN (1<<0)
274 290
275 /* M98095_092_PWR_EN_OUT */ 291 /* M98095_092_PWR_EN_OUT */
276 #define M98095_SPK_FIXEDSPECTRUM (0<<4) 292 #define M98095_SPK_FIXEDSPECTRUM (0<<4)
277 #define M98095_SPK_SPREADSPECTRUM (1<<4) 293 #define M98095_SPK_SPREADSPECTRUM (1<<4)
278 294
279 /* M98095_097_PWR_SYS */ 295 /* M98095_097_PWR_SYS */
280 #define M98095_SHDNRUN (1<<7) 296 #define M98095_SHDNRUN (1<<7)
281 #define M98095_PERFMODE (1<<3) 297 #define M98095_PERFMODE (1<<3)
282 #define M98095_HPPLYBACK (1<<2) 298 #define M98095_HPPLYBACK (1<<2)
283 #define M98095_PWRSV8K (1<<1) 299 #define M98095_PWRSV8K (1<<1)
284 #define M98095_PWRSV (1<<0) 300 #define M98095_PWRSV (1<<0)
285 301
286 #define M98095_COEFS_PER_BAND 5 302 #define M98095_COEFS_PER_BAND 5
287 303
288 #define M98095_BYTE1(w) ((w >> 8) & 0xff) 304 #define M98095_BYTE1(w) ((w >> 8) & 0xff)
289 #define M98095_BYTE0(w) (w & 0xff) 305 #define M98095_BYTE0(w) (w & 0xff)
290 306
291 /* Equalizer filter coefficients */ 307 /* Equalizer filter coefficients */
292 #define M98095_110_DAI1_EQ_BASE 0x10 308 #define M98095_110_DAI1_EQ_BASE 0x10
293 #define M98095_142_DAI2_EQ_BASE 0x42 309 #define M98095_142_DAI2_EQ_BASE 0x42
294 310
295 /* Biquad filter coefficients */ 311 /* Biquad filter coefficients */
296 #define M98095_174_DAI1_BQ_BASE 0x74 312 #define M98095_174_DAI1_BQ_BASE 0x74
297 #define M98095_17E_DAI2_BQ_BASE 0x7E 313 #define M98095_17E_DAI2_BQ_BASE 0x7E
314
315 /* Default Delay used in Slew Rate Calculation for Jack detection */
316 #define M98095_DEFAULT_SLEW_DELAY 0x18
317
318 extern int max98095_jack_detect(struct snd_soc_codec *codec,
319 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack);
298 320
299 #endif 321 #endif
300 322