Doug / smarc-fsl-linux-kernel

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/*

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/*

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*

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*

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* Derived from Intel e1000 driver

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* Derived from Intel e1000 driver

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*

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*

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* This program is free software; you can redistribute it and/or modify it

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* This program is free software; you can redistribute it and/or modify it

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* under the terms of the GNU General Public License as published by the Free

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* under the terms of the GNU General Public License as published by the Free

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* Software Foundation; either version 2 of the License, or (at your option)

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* Software Foundation; either version 2 of the License, or (at your option)

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* any later version.

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* any later version.

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*

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*

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* This program is distributed in the hope that it will be useful, but WITHOUT

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* This program is distributed in the hope that it will be useful, but WITHOUT

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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

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* more details.

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* more details.

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*

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*

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* You should have received a copy of the GNU General Public License along with

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* You should have received a copy of the GNU General Public License along with

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* this program; if not, write to the Free Software Foundation, Inc., 59

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* this program; if not, write to the Free Software Foundation, Inc., 59

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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.

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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.

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*/

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*/

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#include <asm/atomic.h>

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#include <asm/atomic.h>

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#include <linux/crc32.h>

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#include <linux/crc32.h>

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#include <linux/dma-mapping.h>

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#include <linux/dma-mapping.h>

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#include <linux/etherdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/ethtool.h>

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#include <linux/ethtool.h>

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#include <linux/hardirq.h>

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#include <linux/hardirq.h>

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#include <linux/if_vlan.h>

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#include <linux/if_vlan.h>

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#include <linux/in.h>

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#include <linux/in.h>

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#include <linux/interrupt.h>

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#include <linux/interrupt.h>

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#include <linux/ip.h>

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#include <linux/ip.h>

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#include <linux/irqflags.h>

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#include <linux/irqflags.h>

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#include <linux/irqreturn.h>

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#include <linux/irqreturn.h>

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#include <linux/mii.h>

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#include <linux/mii.h>

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#include <linux/net.h>

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#include <linux/net.h>

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#include <linux/netdevice.h>

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#include <linux/netdevice.h>

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#include <linux/pci.h>

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#include <linux/pci.h>

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#include <linux/pci_ids.h>

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#include <linux/pci_ids.h>

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#include <linux/pm.h>

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#include <linux/pm.h>

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#include <linux/skbuff.h>

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#include <linux/skbuff.h>

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#include <linux/spinlock.h>

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#include <linux/spinlock.h>

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#include <linux/string.h>

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#include <linux/string.h>

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#include <linux/tcp.h>

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#include <linux/tcp.h>

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#include <linux/timer.h>

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#include <linux/timer.h>

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#include <linux/types.h>

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#include <linux/types.h>

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#include <linux/workqueue.h>

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#include <linux/workqueue.h>

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#include "atl2.h"

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#include "atl2.h"

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#define ATL2_DRV_VERSION "2.2.3"

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#define ATL2_DRV_VERSION "2.2.3"

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static char atl2_driver_name[] = "atl2";

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static char atl2_driver_name[] = "atl2";

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static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";

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static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";

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static char atl2_driver_version[] = ATL2_DRV_VERSION;

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static char atl2_driver_version[] = ATL2_DRV_VERSION;

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MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");

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MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");

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MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");

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MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");

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MODULE_LICENSE("GPL");

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MODULE_LICENSE("GPL");

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MODULE_VERSION(ATL2_DRV_VERSION);

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MODULE_VERSION(ATL2_DRV_VERSION);

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/*

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/*

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* atl2_pci_tbl - PCI Device ID Table

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* atl2_pci_tbl - PCI Device ID Table

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*/

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*/

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static struct pci_device_id atl2_pci_tbl[] = {

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static struct pci_device_id atl2_pci_tbl[] = {

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{PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},

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{PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},

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/* required last entry */

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/* required last entry */

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{0,}

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{0,}

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};

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};

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MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);

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MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);

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static void atl2_set_ethtool_ops(struct net_device *netdev);

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static void atl2_set_ethtool_ops(struct net_device *netdev);

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static void atl2_check_options(struct atl2_adapter *adapter);

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static void atl2_check_options(struct atl2_adapter *adapter);

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/*

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/*

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* atl2_sw_init - Initialize general software structures (struct atl2_adapter)

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* atl2_sw_init - Initialize general software structures (struct atl2_adapter)

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* @adapter: board private structure to initialize

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* @adapter: board private structure to initialize

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*

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*

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* atl2_sw_init initializes the Adapter private data structure.

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* atl2_sw_init initializes the Adapter private data structure.

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* Fields are initialized based on PCI device information and

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* Fields are initialized based on PCI device information and

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* OS network device settings (MTU size).

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* OS network device settings (MTU size).

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*/

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*/

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static int __devinit atl2_sw_init(struct atl2_adapter *adapter)

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static int __devinit atl2_sw_init(struct atl2_adapter *adapter)

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{

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{

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struct atl2_hw *hw = &adapter->hw;

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struct atl2_hw *hw = &adapter->hw;

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struct pci_dev *pdev = adapter->pdev;

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struct pci_dev *pdev = adapter->pdev;

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/* PCI config space info */

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/* PCI config space info */

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hw->vendor_id = pdev->vendor;

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hw->vendor_id = pdev->vendor;

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hw->device_id = pdev->device;

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hw->device_id = pdev->device;

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hw->subsystem_vendor_id = pdev->subsystem_vendor;

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hw->subsystem_vendor_id = pdev->subsystem_vendor;

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hw->subsystem_id = pdev->subsystem_device;

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hw->subsystem_id = pdev->subsystem_device;

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pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);

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pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);

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pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);

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pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);

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adapter->wol = 0;

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adapter->wol = 0;

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adapter->ict = 50000; /* ~100ms */

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adapter->ict = 50000; /* ~100ms */

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adapter->link_speed = SPEED_0; /* hardware init */

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adapter->link_speed = SPEED_0; /* hardware init */

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adapter->link_duplex = FULL_DUPLEX;

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adapter->link_duplex = FULL_DUPLEX;

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hw->phy_configured = false;

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hw->phy_configured = false;

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hw->preamble_len = 7;

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hw->preamble_len = 7;

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hw->ipgt = 0x60;

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hw->ipgt = 0x60;

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hw->min_ifg = 0x50;

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hw->min_ifg = 0x50;

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hw->ipgr1 = 0x40;

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hw->ipgr1 = 0x40;

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hw->ipgr2 = 0x60;

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hw->ipgr2 = 0x60;

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hw->retry_buf = 2;

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hw->retry_buf = 2;

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hw->max_retry = 0xf;

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hw->max_retry = 0xf;

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hw->lcol = 0x37;

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hw->lcol = 0x37;

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hw->jam_ipg = 7;

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hw->jam_ipg = 7;

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hw->fc_rxd_hi = 0;

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hw->fc_rxd_hi = 0;

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hw->fc_rxd_lo = 0;

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hw->fc_rxd_lo = 0;

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hw->max_frame_size = adapter->netdev->mtu;

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hw->max_frame_size = adapter->netdev->mtu;

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spin_lock_init(&adapter->stats_lock);

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spin_lock_init(&adapter->stats_lock);

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set_bit(__ATL2_DOWN, &adapter->flags);

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set_bit(__ATL2_DOWN, &adapter->flags);

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return 0;

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return 0;

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}

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}

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/*

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/*

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* atl2_set_multi - Multicast and Promiscuous mode set

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* atl2_set_multi - Multicast and Promiscuous mode set

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* @netdev: network interface device structure

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* @netdev: network interface device structure

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*

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*

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* The set_multi entry point is called whenever the multicast address

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* The set_multi entry point is called whenever the multicast address

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* list or the network interface flags are updated. This routine is

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* list or the network interface flags are updated. This routine is

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* responsible for configuring the hardware for proper multicast,

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* responsible for configuring the hardware for proper multicast,

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* promiscuous mode, and all-multi behavior.

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* promiscuous mode, and all-multi behavior.

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*/

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*/

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static void atl2_set_multi(struct net_device *netdev)

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static void atl2_set_multi(struct net_device *netdev)

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{

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{

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struct atl2_adapter *adapter = netdev_priv(netdev);

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struct atl2_adapter *adapter = netdev_priv(netdev);

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struct atl2_hw *hw = &adapter->hw;

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struct atl2_hw *hw = &adapter->hw;

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struct dev_mc_list *mc_ptr;

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struct dev_mc_list *mc_ptr;

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u32 rctl;

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u32 rctl;

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u32 hash_value;

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u32 hash_value;

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/* Check for Promiscuous and All Multicast modes */

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/* Check for Promiscuous and All Multicast modes */

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rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);

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rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);

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if (netdev->flags & IFF_PROMISC) {

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if (netdev->flags & IFF_PROMISC) {

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rctl |= MAC_CTRL_PROMIS_EN;

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rctl |= MAC_CTRL_PROMIS_EN;

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} else if (netdev->flags & IFF_ALLMULTI) {

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} else if (netdev->flags & IFF_ALLMULTI) {

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rctl |= MAC_CTRL_MC_ALL_EN;

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rctl |= MAC_CTRL_MC_ALL_EN;

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rctl &= ~MAC_CTRL_PROMIS_EN;

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rctl &= ~MAC_CTRL_PROMIS_EN;

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} else

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} else

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rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);

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rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);

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ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);

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ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);

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/* clear the old settings from the multicast hash table */

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/* clear the old settings from the multicast hash table */

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ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);

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ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);

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ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);

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ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);

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/* comoute mc addresses' hash value ,and put it into hash table */

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/* comoute mc addresses' hash value ,and put it into hash table */

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for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {

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for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {

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hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);

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hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);

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atl2_hash_set(hw, hash_value);

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atl2_hash_set(hw, hash_value);

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}

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}

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}

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}

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static void init_ring_ptrs(struct atl2_adapter *adapter)

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static void init_ring_ptrs(struct atl2_adapter *adapter)

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{

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{

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/* Read / Write Ptr Initialize: */

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/* Read / Write Ptr Initialize: */

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adapter->txd_write_ptr = 0;

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adapter->txd_write_ptr = 0;

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atomic_set(&adapter->txd_read_ptr, 0);

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atomic_set(&adapter->txd_read_ptr, 0);

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adapter->rxd_read_ptr = 0;

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adapter->rxd_read_ptr = 0;

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adapter->rxd_write_ptr = 0;

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adapter->rxd_write_ptr = 0;

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atomic_set(&adapter->txs_write_ptr, 0);

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atomic_set(&adapter->txs_write_ptr, 0);

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adapter->txs_next_clear = 0;

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adapter->txs_next_clear = 0;

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}

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}

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/*

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/*

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* atl2_configure - Configure Transmit&Receive Unit after Reset

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* atl2_configure - Configure Transmit&Receive Unit after Reset

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* @adapter: board private structure

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* @adapter: board private structure

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*

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*

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* Configure the Tx /Rx unit of the MAC after a reset.

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* Configure the Tx /Rx unit of the MAC after a reset.

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*/

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*/

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static int atl2_configure(struct atl2_adapter *adapter)

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static int atl2_configure(struct atl2_adapter *adapter)

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{

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{

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struct atl2_hw *hw = &adapter->hw;

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struct atl2_hw *hw = &adapter->hw;

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u32 value;

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u32 value;

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/* clear interrupt status */

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/* clear interrupt status */

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ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);

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ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);

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/* set MAC Address */

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/* set MAC Address */

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value = (((u32)hw->mac_addr[2]) << 24) |

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value = (((u32)hw->mac_addr[2]) << 24) |

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(((u32)hw->mac_addr[3]) << 16) |

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(((u32)hw->mac_addr[3]) << 16) |

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(((u32)hw->mac_addr[4]) << 8) |

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(((u32)hw->mac_addr[4]) << 8) |

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(((u32)hw->mac_addr[5]));

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(((u32)hw->mac_addr[5]));

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ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);

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ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);

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value = (((u32)hw->mac_addr[0]) << 8) |

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value = (((u32)hw->mac_addr[0]) << 8) |

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(((u32)hw->mac_addr[1]));

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(((u32)hw->mac_addr[1]));

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ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);

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ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);

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/* HI base address */

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/* HI base address */

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ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,

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ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,

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(u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));

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(u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));

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/* LO base address */

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/* LO base address */

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ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,

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ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,

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(u32)(adapter->txd_dma & 0x00000000ffffffffULL));

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(u32)(adapter->txd_dma & 0x00000000ffffffffULL));

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ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,

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ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,

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(u32)(adapter->txs_dma & 0x00000000ffffffffULL));

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(u32)(adapter->txs_dma & 0x00000000ffffffffULL));

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ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,

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ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,

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(u32)(adapter->rxd_dma & 0x00000000ffffffffULL));

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(u32)(adapter->rxd_dma & 0x00000000ffffffffULL));

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/* element count */

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/* element count */

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ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));

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ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));

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ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);

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ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);

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ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);

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ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);

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/* config Internal SRAM */

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/* config Internal SRAM */

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/*

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/*

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ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);

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ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);

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ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);

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ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);

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*/

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*/

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/* config IPG/IFG */

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/* config IPG/IFG */

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value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<

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value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<

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MAC_IPG_IFG_IPGT_SHIFT) |

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MAC_IPG_IFG_IPGT_SHIFT) |

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(((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<

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(((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<

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MAC_IPG_IFG_MIFG_SHIFT) |

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MAC_IPG_IFG_MIFG_SHIFT) |

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(((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<

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(((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<

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MAC_IPG_IFG_IPGR1_SHIFT)|

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MAC_IPG_IFG_IPGR1_SHIFT)|

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(((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<

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(((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<

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MAC_IPG_IFG_IPGR2_SHIFT);

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MAC_IPG_IFG_IPGR2_SHIFT);

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ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);

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ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);

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/* config Half-Duplex Control */

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/* config Half-Duplex Control */

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value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |

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value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |

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(((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<

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(((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<

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MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |

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MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |

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MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |

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MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |

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(0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |

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(0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |

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(((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<

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(((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<

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MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);

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MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);

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ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);

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ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);

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/* set Interrupt Moderator Timer */

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/* set Interrupt Moderator Timer */

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ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);

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ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);

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ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);

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ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);

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/* set Interrupt Clear Timer */

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/* set Interrupt Clear Timer */

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ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);

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ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);

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/* set MTU */

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/* set MTU */

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ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +

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ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +

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ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);

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ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);

257

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/* 1590 */

258

/* 1590 */

259

ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);

259

ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);

260

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/* flow control */

261

/* flow control */

262

ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);

262

ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);

263

ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);

263

ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);

264

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/* Init mailbox */

265

/* Init mailbox */

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ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);

266

ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);

267

ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);

267

ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);

268

269

/* enable DMA read/write */

269

/* enable DMA read/write */

270

ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);

270

ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);

271

ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);

271

ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);

272

273

value = ATL2_READ_REG(&adapter->hw, REG_ISR);

273

value = ATL2_READ_REG(&adapter->hw, REG_ISR);

274

if ((value & ISR_PHY_LINKDOWN) != 0)

274

if ((value & ISR_PHY_LINKDOWN) != 0)

275

value = 1; /* config failed */

275

value = 1; /* config failed */

276

else

276

else

277

value = 0;

277

value = 0;

278

279

/* clear all interrupt status */

279

/* clear all interrupt status */

280

ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);

280

ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);

281

ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);

281

ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);

282

return value;

282

return value;

283

}

283

}

284

285

/*

285

/*

286

* atl2_setup_ring_resources - allocate Tx / RX descriptor resources

286

* atl2_setup_ring_resources - allocate Tx / RX descriptor resources

287

* @adapter: board private structure

287

* @adapter: board private structure

288

*

288

*

289

* Return 0 on success, negative on failure

289

* Return 0 on success, negative on failure

290

*/

290

*/

291

static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)

291

static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)

292

{

292

{

293

struct pci_dev *pdev = adapter->pdev;

293

struct pci_dev *pdev = adapter->pdev;

294

int size;

294

int size;

295

u8 offset = 0;

295

u8 offset = 0;

296

297

/* real ring DMA buffer */

297

/* real ring DMA buffer */

298

adapter->ring_size = size =

298

adapter->ring_size = size =

299

adapter->txd_ring_size * 1 + 7 + /* dword align */

299

adapter->txd_ring_size * 1 + 7 + /* dword align */

300

adapter->txs_ring_size * 4 + 7 + /* dword align */

300

adapter->txs_ring_size * 4 + 7 + /* dword align */

301

adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */

301

adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */

302

303

adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,

303

adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,

304

&adapter->ring_dma);

304

&adapter->ring_dma);

305

if (!adapter->ring_vir_addr)

305

if (!adapter->ring_vir_addr)

306

return -ENOMEM;

306

return -ENOMEM;

307

memset(adapter->ring_vir_addr, 0, adapter->ring_size);

307

memset(adapter->ring_vir_addr, 0, adapter->ring_size);

308

309

/* Init TXD Ring */

309

/* Init TXD Ring */

310

adapter->txd_dma = adapter->ring_dma ;

310

adapter->txd_dma = adapter->ring_dma ;

311

offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;

311

offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;

312

adapter->txd_dma += offset;

312

adapter->txd_dma += offset;

313

adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +

313

adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +

314

offset);

314

offset);

315

316

/* Init TXS Ring */

316

/* Init TXS Ring */

317

adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;

317

adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;

318

offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;

318

offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;

319

adapter->txs_dma += offset;

319

adapter->txs_dma += offset;

320

adapter->txs_ring = (struct tx_pkt_status *)

320

adapter->txs_ring = (struct tx_pkt_status *)

321

(((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));

321

(((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));

322

323

/* Init RXD Ring */

323

/* Init RXD Ring */

324

adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;

324

adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;

325

offset = (adapter->rxd_dma & 127) ?

325

offset = (adapter->rxd_dma & 127) ?

326

(128 - (adapter->rxd_dma & 127)) : 0;

326

(128 - (adapter->rxd_dma & 127)) : 0;

327

if (offset > 7)

327

if (offset > 7)

328

offset -= 8;

328

offset -= 8;

329

else

329

else

330

offset += (128 - 8);

330

offset += (128 - 8);

331

332

adapter->rxd_dma += offset;

332

adapter->rxd_dma += offset;

333

adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +

333

adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +

334

(adapter->txs_ring_size * 4 + offset));

334

(adapter->txs_ring_size * 4 + offset));

335

336

/*

336

/*

337

* Read / Write Ptr Initialize:

337

* Read / Write Ptr Initialize:

338

* init_ring_ptrs(adapter);

338

* init_ring_ptrs(adapter);

339

*/

339

*/

340

return 0;

340

return 0;

341

}

341

}

342

343

/*

343

/*

344

* atl2_irq_enable - Enable default interrupt generation settings

344

* atl2_irq_enable - Enable default interrupt generation settings

345

* @adapter: board private structure

345

* @adapter: board private structure

346

*/

346

*/

347

static inline void atl2_irq_enable(struct atl2_adapter *adapter)

347

static inline void atl2_irq_enable(struct atl2_adapter *adapter)

348

{

348

{

349

ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);

349

ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);

350

ATL2_WRITE_FLUSH(&adapter->hw);

350

ATL2_WRITE_FLUSH(&adapter->hw);

351

}

351

}

352

353

/*

353

/*

354

* atl2_irq_disable - Mask off interrupt generation on the NIC

354

* atl2_irq_disable - Mask off interrupt generation on the NIC

355

* @adapter: board private structure

355

* @adapter: board private structure

356

*/

356

*/

357

static inline void atl2_irq_disable(struct atl2_adapter *adapter)

357

static inline void atl2_irq_disable(struct atl2_adapter *adapter)

358

{

358

{

359

ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);

359

ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);

360

ATL2_WRITE_FLUSH(&adapter->hw);

360

ATL2_WRITE_FLUSH(&adapter->hw);

361

synchronize_irq(adapter->pdev->irq);

361

synchronize_irq(adapter->pdev->irq);

362

}

362

}

363

364

#ifdef NETIF_F_HW_VLAN_TX

364

#ifdef NETIF_F_HW_VLAN_TX

365

static void atl2_vlan_rx_register(struct net_device *netdev,

365

static void atl2_vlan_rx_register(struct net_device *netdev,

366

struct vlan_group *grp)

366

struct vlan_group *grp)

367

{

367

{

368

struct atl2_adapter *adapter = netdev_priv(netdev);

368

struct atl2_adapter *adapter = netdev_priv(netdev);

369

u32 ctrl;

369

u32 ctrl;

370

371

atl2_irq_disable(adapter);

371

atl2_irq_disable(adapter);

372

adapter->vlgrp = grp;

372

adapter->vlgrp = grp;

373

374

if (grp) {

374

if (grp) {

375

/* enable VLAN tag insert/strip */

375

/* enable VLAN tag insert/strip */

376

ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);

376

ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);

377

ctrl |= MAC_CTRL_RMV_VLAN;

377

ctrl |= MAC_CTRL_RMV_VLAN;

378

ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);

378

ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);

379

} else {

379

} else {

380

/* disable VLAN tag insert/strip */

380

/* disable VLAN tag insert/strip */

381

ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);

381

ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);

382

ctrl &= ~MAC_CTRL_RMV_VLAN;

382

ctrl &= ~MAC_CTRL_RMV_VLAN;

383

ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);

383

ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);

384

}

384

}

385

386

atl2_irq_enable(adapter);

386

atl2_irq_enable(adapter);

387

}

387

}

388

389

static void atl2_restore_vlan(struct atl2_adapter *adapter)

389

static void atl2_restore_vlan(struct atl2_adapter *adapter)

390

{

390

{

391

atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);

391

atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);

392

}

392

}

393

#endif

393

#endif

394

395

static void atl2_intr_rx(struct atl2_adapter *adapter)

395

static void atl2_intr_rx(struct atl2_adapter *adapter)

396

{

396

{

397

struct net_device *netdev = adapter->netdev;

397

struct net_device *netdev = adapter->netdev;

398

struct rx_desc *rxd;

398

struct rx_desc *rxd;

399

struct sk_buff *skb;

399

struct sk_buff *skb;

400

401

do {

401

do {

402

rxd = adapter->rxd_ring+adapter->rxd_write_ptr;

402

rxd = adapter->rxd_ring+adapter->rxd_write_ptr;

403

if (!rxd->status.update)

403

if (!rxd->status.update)

404

break; /* end of tx */

404

break; /* end of tx */

405

406

/* clear this flag at once */

406

/* clear this flag at once */

407

rxd->status.update = 0;

407

rxd->status.update = 0;

408

409

if (rxd->status.ok && rxd->status.pkt_size >= 60) {

409

if (rxd->status.ok && rxd->status.pkt_size >= 60) {

410

int rx_size = (int)(rxd->status.pkt_size - 4);

410

int rx_size = (int)(rxd->status.pkt_size - 4);

411

/* alloc new buffer */

411

/* alloc new buffer */

412

skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN);

412

skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN);

413

if (NULL == skb) {

413

if (NULL == skb) {

414

printk(KERN_WARNING

414

printk(KERN_WARNING

415

"%s: Mem squeeze, deferring packet.\n",

415

"%s: Mem squeeze, deferring packet.\n",

416

netdev->name);

416

netdev->name);

417

/*

417

/*

418

* Check that some rx space is free. If not,

418

* Check that some rx space is free. If not,

419

* free one and mark stats->rx_dropped++.

419

* free one and mark stats->rx_dropped++.

420

*/

420

*/

421

netdev->stats.rx_dropped++;

421

netdev->stats.rx_dropped++;

422

break;

422

break;

423

}

423

}

424

skb_reserve(skb, NET_IP_ALIGN);

424

skb_reserve(skb, NET_IP_ALIGN);

425

skb->dev = netdev;

425

skb->dev = netdev;

426

memcpy(skb->data, rxd->packet, rx_size);

426

memcpy(skb->data, rxd->packet, rx_size);

427

skb_put(skb, rx_size);

427

skb_put(skb, rx_size);

428

skb->protocol = eth_type_trans(skb, netdev);

428

skb->protocol = eth_type_trans(skb, netdev);

429

#ifdef NETIF_F_HW_VLAN_TX

429

#ifdef NETIF_F_HW_VLAN_TX

430

if (adapter->vlgrp && (rxd->status.vlan)) {

430

if (adapter->vlgrp && (rxd->status.vlan)) {

431

u16 vlan_tag = (rxd->status.vtag>>4) |

431

u16 vlan_tag = (rxd->status.vtag>>4) |

432

((rxd->status.vtag&7) << 13) |

432

((rxd->status.vtag&7) << 13) |

433

((rxd->status.vtag&8) << 9);

433

((rxd->status.vtag&8) << 9);

434

vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);

434

vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);

435

} else

435

} else

436

#endif

436

#endif

437

netif_rx(skb);

437

netif_rx(skb);

438

netdev->stats.rx_bytes += rx_size;

438

netdev->stats.rx_bytes += rx_size;

439

netdev->stats.rx_packets++;

439

netdev->stats.rx_packets++;

440

} else {

440

} else {

441

netdev->stats.rx_errors++;

441

netdev->stats.rx_errors++;

442

443

if (rxd->status.ok && rxd->status.pkt_size <= 60)

443

if (rxd->status.ok && rxd->status.pkt_size <= 60)

444

netdev->stats.rx_length_errors++;

444

netdev->stats.rx_length_errors++;

445

if (rxd->status.mcast)

445

if (rxd->status.mcast)

446

netdev->stats.multicast++;

446

netdev->stats.multicast++;

447

if (rxd->status.crc)

447

if (rxd->status.crc)

448

netdev->stats.rx_crc_errors++;

448

netdev->stats.rx_crc_errors++;

449

if (rxd->status.align)

449

if (rxd->status.align)

450

netdev->stats.rx_frame_errors++;

450

netdev->stats.rx_frame_errors++;

451

}

451

}

452

453

/* advance write ptr */

453

/* advance write ptr */

454

if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)

454

if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)

455

adapter->rxd_write_ptr = 0;

455

adapter->rxd_write_ptr = 0;

456

} while (1);

456

} while (1);

457

458

/* update mailbox? */

458

/* update mailbox? */

459

adapter->rxd_read_ptr = adapter->rxd_write_ptr;

459

adapter->rxd_read_ptr = adapter->rxd_write_ptr;

460

ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);

460

ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);

461

}

461

}

462

463

static void atl2_intr_tx(struct atl2_adapter *adapter)

463

static void atl2_intr_tx(struct atl2_adapter *adapter)

464

{

464

{

465

struct net_device *netdev = adapter->netdev;

465

struct net_device *netdev = adapter->netdev;

466

u32 txd_read_ptr;

466

u32 txd_read_ptr;

467

u32 txs_write_ptr;

467

u32 txs_write_ptr;

468

struct tx_pkt_status *txs;

468

struct tx_pkt_status *txs;

469

struct tx_pkt_header *txph;

469

struct tx_pkt_header *txph;

470

int free_hole = 0;

470

int free_hole = 0;

471

472

do {

472

do {

473

txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);

473

txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);

474

txs = adapter->txs_ring + txs_write_ptr;

474

txs = adapter->txs_ring + txs_write_ptr;

475

if (!txs->update)

475

if (!txs->update)

476

break; /* tx stop here */

476

break; /* tx stop here */

477

478

free_hole = 1;

478

free_hole = 1;

479

txs->update = 0;

479

txs->update = 0;

480

481

if (++txs_write_ptr == adapter->txs_ring_size)

481

if (++txs_write_ptr == adapter->txs_ring_size)

482

txs_write_ptr = 0;

482

txs_write_ptr = 0;

483

atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);

483

atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);

484

485

txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);

485

txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);

486

txph = (struct tx_pkt_header *)

486

txph = (struct tx_pkt_header *)

487

(((u8 *)adapter->txd_ring) + txd_read_ptr);

487

(((u8 *)adapter->txd_ring) + txd_read_ptr);

488

489

if (txph->pkt_size != txs->pkt_size) {

489

if (txph->pkt_size != txs->pkt_size) {

490

struct tx_pkt_status *old_txs = txs;

490

struct tx_pkt_status *old_txs = txs;

491

printk(KERN_WARNING

491

printk(KERN_WARNING

492

"%s: txs packet size not consistent with txd"

492

"%s: txs packet size not consistent with txd"

493

" txd_:0x%08x, txs_:0x%08x!\n",

493

" txd_:0x%08x, txs_:0x%08x!\n",

494

adapter->netdev->name,

494

adapter->netdev->name,

495

*(u32 *)txph, *(u32 *)txs);

495

*(u32 *)txph, *(u32 *)txs);

496

printk(KERN_WARNING

496

printk(KERN_WARNING

497

"txd read ptr: 0x%x\n",

497

"txd read ptr: 0x%x\n",

498

txd_read_ptr);

498

txd_read_ptr);

499

txs = adapter->txs_ring + txs_write_ptr;

499

txs = adapter->txs_ring + txs_write_ptr;

500

printk(KERN_WARNING

500

printk(KERN_WARNING

501

"txs-behind:0x%08x\n",

501

"txs-behind:0x%08x\n",

502

*(u32 *)txs);

502

*(u32 *)txs);

503

if (txs_write_ptr < 2) {

503

if (txs_write_ptr < 2) {

504

txs = adapter->txs_ring +

504

txs = adapter->txs_ring +

505

(adapter->txs_ring_size +

505

(adapter->txs_ring_size +

506

txs_write_ptr - 2);

506

txs_write_ptr - 2);

507

} else {

507

} else {

508

txs = adapter->txs_ring + (txs_write_ptr - 2);

508

txs = adapter->txs_ring + (txs_write_ptr - 2);

509

}

509

}

510

printk(KERN_WARNING

510

printk(KERN_WARNING

511

"txs-before:0x%08x\n",

511

"txs-before:0x%08x\n",

512

*(u32 *)txs);

512

*(u32 *)txs);

513

txs = old_txs;

513

txs = old_txs;

514

}

514

}

515

516

/* 4for TPH */

516

/* 4for TPH */

517

txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);

517

txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);

518

if (txd_read_ptr >= adapter->txd_ring_size)

518

if (txd_read_ptr >= adapter->txd_ring_size)

519

txd_read_ptr -= adapter->txd_ring_size;

519

txd_read_ptr -= adapter->txd_ring_size;

520

521

atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);

521

atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);

522

523

/* tx statistics: */

523

/* tx statistics: */

524

if (txs->ok) {

524

if (txs->ok) {

525

netdev->stats.tx_bytes += txs->pkt_size;

525

netdev->stats.tx_bytes += txs->pkt_size;

526

netdev->stats.tx_packets++;

526

netdev->stats.tx_packets++;

527

}

527

}

528

else

528

else

529

netdev->stats.tx_errors++;

529

netdev->stats.tx_errors++;

530

531

if (txs->defer)

531

if (txs->defer)

532

netdev->stats.collisions++;

532

netdev->stats.collisions++;

533

if (txs->abort_col)

533

if (txs->abort_col)

534

netdev->stats.tx_aborted_errors++;

534

netdev->stats.tx_aborted_errors++;

535

if (txs->late_col)

535

if (txs->late_col)

536

netdev->stats.tx_window_errors++;

536

netdev->stats.tx_window_errors++;

537

if (txs->underun)

537

if (txs->underun)

538

netdev->stats.tx_fifo_errors++;

538

netdev->stats.tx_fifo_errors++;

539

} while (1);

539

} while (1);

540

541

if (free_hole) {

541

if (free_hole) {

542

if (netif_queue_stopped(adapter->netdev) &&

542

if (netif_queue_stopped(adapter->netdev) &&

543

netif_carrier_ok(adapter->netdev))

543

netif_carrier_ok(adapter->netdev))

544

netif_wake_queue(adapter->netdev);

544

netif_wake_queue(adapter->netdev);

545

}

545

}

546

}

546

}

547

548

static void atl2_check_for_link(struct atl2_adapter *adapter)

548

static void atl2_check_for_link(struct atl2_adapter *adapter)

549

{

549

{

550

struct net_device *netdev = adapter->netdev;

550

struct net_device *netdev = adapter->netdev;

551

u16 phy_data = 0;

551

u16 phy_data = 0;

552

553

spin_lock(&adapter->stats_lock);

553

spin_lock(&adapter->stats_lock);

554

atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);

554

atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);

555

atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);

555

atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);

556

spin_unlock(&adapter->stats_lock);

556

spin_unlock(&adapter->stats_lock);

557

558

/* notify upper layer link down ASAP */

558

/* notify upper layer link down ASAP */

559

if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */

559

if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */

560

if (netif_carrier_ok(netdev)) { /* old link state: Up */

560

if (netif_carrier_ok(netdev)) { /* old link state: Up */

561

printk(KERN_INFO "%s: %s NIC Link is Down\n",

561

printk(KERN_INFO "%s: %s NIC Link is Down\n",

562

atl2_driver_name, netdev->name);

562

atl2_driver_name, netdev->name);

563

adapter->link_speed = SPEED_0;

563

adapter->link_speed = SPEED_0;

564

netif_carrier_off(netdev);

564

netif_carrier_off(netdev);

565

netif_stop_queue(netdev);

565

netif_stop_queue(netdev);

566

}

566

}

567

}

567

}

568

schedule_work(&adapter->link_chg_task);

568

schedule_work(&adapter->link_chg_task);

569

}

569

}

570

571

static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)

571

static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)

572

{

572

{

573

u16 phy_data;

573

u16 phy_data;

574

spin_lock(&adapter->stats_lock);

574

spin_lock(&adapter->stats_lock);

575

atl2_read_phy_reg(&adapter->hw, 19, &phy_data);

575

atl2_read_phy_reg(&adapter->hw, 19, &phy_data);

576

spin_unlock(&adapter->stats_lock);

576

spin_unlock(&adapter->stats_lock);

577

}

577

}

578

579

/*

579

/*

580

* atl2_intr - Interrupt Handler

580

* atl2_intr - Interrupt Handler

581

* @irq: interrupt number

581

* @irq: interrupt number

582

* @data: pointer to a network interface device structure

582

* @data: pointer to a network interface device structure

583

* @pt_regs: CPU registers structure

583

* @pt_regs: CPU registers structure

584

*/

584

*/

585

static irqreturn_t atl2_intr(int irq, void *data)

585

static irqreturn_t atl2_intr(int irq, void *data)

586

{

586

{

587

struct atl2_adapter *adapter = netdev_priv(data);

587

struct atl2_adapter *adapter = netdev_priv(data);

588

struct atl2_hw *hw = &adapter->hw;

588

struct atl2_hw *hw = &adapter->hw;

589

u32 status;

589

u32 status;

590

591

status = ATL2_READ_REG(hw, REG_ISR);

591

status = ATL2_READ_REG(hw, REG_ISR);

592

if (0 == status)

592

if (0 == status)

593

return IRQ_NONE;

593

return IRQ_NONE;

594

595

/* link event */

595

/* link event */

596

if (status & ISR_PHY)

596

if (status & ISR_PHY)

597

atl2_clear_phy_int(adapter);

597

atl2_clear_phy_int(adapter);

598

599

/* clear ISR status, and Enable CMB DMA/Disable Interrupt */

599

/* clear ISR status, and Enable CMB DMA/Disable Interrupt */

600

ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);

600

ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);

601

602

/* check if PCIE PHY Link down */

602

/* check if PCIE PHY Link down */

603

if (status & ISR_PHY_LINKDOWN) {

603

if (status & ISR_PHY_LINKDOWN) {

604

if (netif_running(adapter->netdev)) { /* reset MAC */

604

if (netif_running(adapter->netdev)) { /* reset MAC */

605

ATL2_WRITE_REG(hw, REG_ISR, 0);

605

ATL2_WRITE_REG(hw, REG_ISR, 0);

606

ATL2_WRITE_REG(hw, REG_IMR, 0);

606

ATL2_WRITE_REG(hw, REG_IMR, 0);

607

ATL2_WRITE_FLUSH(hw);

607

ATL2_WRITE_FLUSH(hw);

608

schedule_work(&adapter->reset_task);

608

schedule_work(&adapter->reset_task);

609

return IRQ_HANDLED;

609

return IRQ_HANDLED;

610

}

610

}

611

}

611

}

612

613

/* check if DMA read/write error? */

613

/* check if DMA read/write error? */

614

if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {

614

if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {

615

ATL2_WRITE_REG(hw, REG_ISR, 0);

615

ATL2_WRITE_REG(hw, REG_ISR, 0);

616

ATL2_WRITE_REG(hw, REG_IMR, 0);

616

ATL2_WRITE_REG(hw, REG_IMR, 0);

617

ATL2_WRITE_FLUSH(hw);

617

ATL2_WRITE_FLUSH(hw);

618

schedule_work(&adapter->reset_task);

618

schedule_work(&adapter->reset_task);

619

return IRQ_HANDLED;

619

return IRQ_HANDLED;

620

}

620

}

621

622

/* link event */

622

/* link event */

623

if (status & (ISR_PHY | ISR_MANUAL)) {

623

if (status & (ISR_PHY | ISR_MANUAL)) {

624

adapter->netdev->stats.tx_carrier_errors++;

624

adapter->netdev->stats.tx_carrier_errors++;

625

atl2_check_for_link(adapter);

625

atl2_check_for_link(adapter);

626

}

626

}

627

628

/* transmit event */

628

/* transmit event */

629

if (status & ISR_TX_EVENT)

629

if (status & ISR_TX_EVENT)

630

atl2_intr_tx(adapter);

630

atl2_intr_tx(adapter);

631

632

/* rx exception */

632

/* rx exception */

633

if (status & ISR_RX_EVENT)

633

if (status & ISR_RX_EVENT)

634

atl2_intr_rx(adapter);

634

atl2_intr_rx(adapter);

635

636

/* re-enable Interrupt */

636

/* re-enable Interrupt */

637

ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);

637

ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);

638

return IRQ_HANDLED;

638

return IRQ_HANDLED;

639

}

639

}

640

641

static int atl2_request_irq(struct atl2_adapter *adapter)

641

static int atl2_request_irq(struct atl2_adapter *adapter)

642

{

642

{

643

struct net_device *netdev = adapter->netdev;

643

struct net_device *netdev = adapter->netdev;

644

int flags, err = 0;

644

int flags, err = 0;

645

646

flags = IRQF_SHARED;

646

flags = IRQF_SHARED;

647

#ifdef CONFIG_PCI_MSI

648

adapter->have_msi = true;

647

adapter->have_msi = true;

649

err = pci_enable_msi(adapter->pdev);

648

err = pci_enable_msi(adapter->pdev);

650

if (err)

649

if (err)

651

adapter->have_msi = false;

650

adapter->have_msi = false;

652

651

653

if (adapter->have_msi)

652

if (adapter->have_msi)

654

flags &= ~IRQF_SHARED;

653

flags &= ~IRQF_SHARED;

655

#endif

656

654

657

return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name,

655

return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name,

658

netdev);

656

netdev);

659

}

657

}

660

658

661

/*

659

/*

662

* atl2_free_ring_resources - Free Tx / RX descriptor Resources

660

* atl2_free_ring_resources - Free Tx / RX descriptor Resources

663

* @adapter: board private structure

661

* @adapter: board private structure

664

*

662

*

665

* Free all transmit software resources

663

* Free all transmit software resources

666

*/

664

*/

667

static void atl2_free_ring_resources(struct atl2_adapter *adapter)

665

static void atl2_free_ring_resources(struct atl2_adapter *adapter)

668

{

666

{

669

struct pci_dev *pdev = adapter->pdev;

667

struct pci_dev *pdev = adapter->pdev;

670

pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,

668

pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,

671

adapter->ring_dma);

669

adapter->ring_dma);

672

}

670

}

673

671

674

/*

672

/*

675

* atl2_open - Called when a network interface is made active

673

* atl2_open - Called when a network interface is made active

676

* @netdev: network interface device structure

674

* @netdev: network interface device structure

677

*

675

*

678

* Returns 0 on success, negative value on failure

676

* Returns 0 on success, negative value on failure

679

*

677

*

680

* The open entry point is called when a network interface is made

678

* The open entry point is called when a network interface is made

681

* active by the system (IFF_UP). At this point all resources needed

679

* active by the system (IFF_UP). At this point all resources needed

682

* for transmit and receive operations are allocated, the interrupt

680

* for transmit and receive operations are allocated, the interrupt

683

* handler is registered with the OS, the watchdog timer is started,

681

* handler is registered with the OS, the watchdog timer is started,

684

* and the stack is notified that the interface is ready.

682

* and the stack is notified that the interface is ready.

685

*/

683

*/

686

static int atl2_open(struct net_device *netdev)

684

static int atl2_open(struct net_device *netdev)

687

{

685

{

688

struct atl2_adapter *adapter = netdev_priv(netdev);

686

struct atl2_adapter *adapter = netdev_priv(netdev);

689

int err;

687

int err;

690

u32 val;

688

u32 val;

691

689

692

/* disallow open during test */

690

/* disallow open during test */

693

if (test_bit(__ATL2_TESTING, &adapter->flags))

691

if (test_bit(__ATL2_TESTING, &adapter->flags))

694

return -EBUSY;

692

return -EBUSY;

695

693

696

/* allocate transmit descriptors */

694

/* allocate transmit descriptors */

697

err = atl2_setup_ring_resources(adapter);

695

err = atl2_setup_ring_resources(adapter);

698

if (err)

696

if (err)

699

return err;

697

return err;

700

698

701

err = atl2_init_hw(&adapter->hw);

699

err = atl2_init_hw(&adapter->hw);

702

if (err) {

700

if (err) {

703

err = -EIO;

701

err = -EIO;

704

goto err_init_hw;

702

goto err_init_hw;

705

}

703

}

706

704

707

/* hardware has been reset, we need to reload some things */

705

/* hardware has been reset, we need to reload some things */

708

atl2_set_multi(netdev);

706

atl2_set_multi(netdev);

709

init_ring_ptrs(adapter);

707

init_ring_ptrs(adapter);

710

708

711

#ifdef NETIF_F_HW_VLAN_TX

709

#ifdef NETIF_F_HW_VLAN_TX

712

atl2_restore_vlan(adapter);

710

atl2_restore_vlan(adapter);

713

#endif

711

#endif

714

712

715

if (atl2_configure(adapter)) {

713

if (atl2_configure(adapter)) {

716

err = -EIO;

714

err = -EIO;

717

goto err_config;

715

goto err_config;

718

}

716

}

719

717

720

err = atl2_request_irq(adapter);

718

err = atl2_request_irq(adapter);

721

if (err)

719

if (err)

722

goto err_req_irq;

720

goto err_req_irq;

723

721

724

clear_bit(__ATL2_DOWN, &adapter->flags);

722

clear_bit(__ATL2_DOWN, &adapter->flags);

725

723

726

mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));

724

mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));

727

725

728

val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);

726

val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);

729

ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,

727

ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,

730

val | MASTER_CTRL_MANUAL_INT);

728

val | MASTER_CTRL_MANUAL_INT);

731

729

732

atl2_irq_enable(adapter);

730

atl2_irq_enable(adapter);

733

731

734

return 0;

732

return 0;

735

733

736

err_init_hw:

734

err_init_hw:

737

err_req_irq:

735

err_req_irq:

738

err_config:

736

err_config:

739

atl2_free_ring_resources(adapter);

737

atl2_free_ring_resources(adapter);

740

atl2_reset_hw(&adapter->hw);

738

atl2_reset_hw(&adapter->hw);

741

739

742

return err;

740

return err;

743

}

741

}

744

742

745

static void atl2_down(struct atl2_adapter *adapter)

743

static void atl2_down(struct atl2_adapter *adapter)

746

{

744

{

747

struct net_device *netdev = adapter->netdev;

745

struct net_device *netdev = adapter->netdev;

748

746

749

/* signal that we're down so the interrupt handler does not

747

/* signal that we're down so the interrupt handler does not

750

* reschedule our watchdog timer */

748

* reschedule our watchdog timer */

751

set_bit(__ATL2_DOWN, &adapter->flags);

749

set_bit(__ATL2_DOWN, &adapter->flags);

752

750

753

netif_tx_disable(netdev);

751

netif_tx_disable(netdev);

754

752

755

/* reset MAC to disable all RX/TX */

753

/* reset MAC to disable all RX/TX */

756

atl2_reset_hw(&adapter->hw);

754

atl2_reset_hw(&adapter->hw);

757

msleep(1);

755

msleep(1);

758

756

759

atl2_irq_disable(adapter);

757

atl2_irq_disable(adapter);

760

758

761

del_timer_sync(&adapter->watchdog_timer);

759

del_timer_sync(&adapter->watchdog_timer);

762

del_timer_sync(&adapter->phy_config_timer);

760

del_timer_sync(&adapter->phy_config_timer);

763

clear_bit(0, &adapter->cfg_phy);

761

clear_bit(0, &adapter->cfg_phy);

764

762

765

netif_carrier_off(netdev);

763

netif_carrier_off(netdev);

766

adapter->link_speed = SPEED_0;

764

adapter->link_speed = SPEED_0;

767

adapter->link_duplex = -1;

765

adapter->link_duplex = -1;

768

}

766

}

769

767

770

static void atl2_free_irq(struct atl2_adapter *adapter)

768

static void atl2_free_irq(struct atl2_adapter *adapter)

771

{

769

{

772

struct net_device *netdev = adapter->netdev;

770

struct net_device *netdev = adapter->netdev;

773

771

774

free_irq(adapter->pdev->irq, netdev);

772

free_irq(adapter->pdev->irq, netdev);

775

773

776

#ifdef CONFIG_PCI_MSI

774

#ifdef CONFIG_PCI_MSI

777

if (adapter->have_msi)

775

if (adapter->have_msi)

778

pci_disable_msi(adapter->pdev);

776

pci_disable_msi(adapter->pdev);

779

#endif

777

#endif

780

}

778

}

781

779

782

/*

780

/*

783

* atl2_close - Disables a network interface

781

* atl2_close - Disables a network interface

784

* @netdev: network interface device structure

782

* @netdev: network interface device structure

785

*

783

*

786

* Returns 0, this is not allowed to fail

784

* Returns 0, this is not allowed to fail

787

*

785

*

788

* The close entry point is called when an interface is de-activated

786

* The close entry point is called when an interface is de-activated

789

* by the OS. The hardware is still under the drivers control, but

787

* by the OS. The hardware is still under the drivers control, but

790

* needs to be disabled. A global MAC reset is issued to stop the

788

* needs to be disabled. A global MAC reset is issued to stop the

791

* hardware, and all transmit and receive resources are freed.

789

* hardware, and all transmit and receive resources are freed.

792

*/

790

*/

793

static int atl2_close(struct net_device *netdev)

791

static int atl2_close(struct net_device *netdev)

794

{

792

{

795

struct atl2_adapter *adapter = netdev_priv(netdev);

793

struct atl2_adapter *adapter = netdev_priv(netdev);

796

794

797

WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));

795

WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));

798

796

799

atl2_down(adapter);

797

atl2_down(adapter);

800

atl2_free_irq(adapter);

798

atl2_free_irq(adapter);

801

atl2_free_ring_resources(adapter);

799

atl2_free_ring_resources(adapter);

802

800

803

return 0;

801

return 0;

804

}

802

}

805

803

806

static inline int TxsFreeUnit(struct atl2_adapter *adapter)

804

static inline int TxsFreeUnit(struct atl2_adapter *adapter)

807

{

805

{

808

u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);

806

u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);

809

807

810

return (adapter->txs_next_clear >= txs_write_ptr) ?

808

return (adapter->txs_next_clear >= txs_write_ptr) ?

811

(int) (adapter->txs_ring_size - adapter->txs_next_clear +

809

(int) (adapter->txs_ring_size - adapter->txs_next_clear +

812

txs_write_ptr - 1) :

810

txs_write_ptr - 1) :

813

(int) (txs_write_ptr - adapter->txs_next_clear - 1);

811

(int) (txs_write_ptr - adapter->txs_next_clear - 1);

814

}

812

}

815

813

816

static inline int TxdFreeBytes(struct atl2_adapter *adapter)

814

static inline int TxdFreeBytes(struct atl2_adapter *adapter)

817

{

815

{

818

u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);

816

u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);

819

817

820

return (adapter->txd_write_ptr >= txd_read_ptr) ?

818

return (adapter->txd_write_ptr >= txd_read_ptr) ?

821

(int) (adapter->txd_ring_size - adapter->txd_write_ptr +

819

(int) (adapter->txd_ring_size - adapter->txd_write_ptr +

822

txd_read_ptr - 1) :

820

txd_read_ptr - 1) :

823

(int) (txd_read_ptr - adapter->txd_write_ptr - 1);

821

(int) (txd_read_ptr - adapter->txd_write_ptr - 1);

824

}

822

}

825

823

826

static int atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)

824

static int atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)

827

{

825

{

828

struct atl2_adapter *adapter = netdev_priv(netdev);

826

struct atl2_adapter *adapter = netdev_priv(netdev);

829

struct tx_pkt_header *txph;

827

struct tx_pkt_header *txph;

830

u32 offset, copy_len;

828

u32 offset, copy_len;

831

int txs_unused;

829

int txs_unused;

832

int txbuf_unused;

830

int txbuf_unused;

833

831

834

if (test_bit(__ATL2_DOWN, &adapter->flags)) {

832

if (test_bit(__ATL2_DOWN, &adapter->flags)) {

835

dev_kfree_skb_any(skb);

833

dev_kfree_skb_any(skb);

836

return NETDEV_TX_OK;

834

return NETDEV_TX_OK;

837

}

835

}

838

836

839

if (unlikely(skb->len <= 0)) {

837

if (unlikely(skb->len <= 0)) {

840

dev_kfree_skb_any(skb);

838

dev_kfree_skb_any(skb);

841

return NETDEV_TX_OK;

839

return NETDEV_TX_OK;

842

}

840

}

843

841

844

txs_unused = TxsFreeUnit(adapter);

842

txs_unused = TxsFreeUnit(adapter);

845

txbuf_unused = TxdFreeBytes(adapter);

843

txbuf_unused = TxdFreeBytes(adapter);

846

844

847

if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||

845

if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||

848

txs_unused < 1) {

846

txs_unused < 1) {

849

/* not enough resources */

847

/* not enough resources */

850

netif_stop_queue(netdev);

848

netif_stop_queue(netdev);

851

return NETDEV_TX_BUSY;

849

return NETDEV_TX_BUSY;

852

}

850

}

853

851

854

offset = adapter->txd_write_ptr;

852

offset = adapter->txd_write_ptr;

855

853

856

txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);

854

txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);

857

855

858

*(u32 *)txph = 0;

856

*(u32 *)txph = 0;

859

txph->pkt_size = skb->len;

857

txph->pkt_size = skb->len;

860

858

861

offset += 4;

859

offset += 4;

862

if (offset >= adapter->txd_ring_size)

860

if (offset >= adapter->txd_ring_size)

863

offset -= adapter->txd_ring_size;

861

offset -= adapter->txd_ring_size;

864

copy_len = adapter->txd_ring_size - offset;

862

copy_len = adapter->txd_ring_size - offset;

865

if (copy_len >= skb->len) {

863

if (copy_len >= skb->len) {

866

memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);

864

memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);

867

offset += ((u32)(skb->len + 3) & ~3);

865

offset += ((u32)(skb->len + 3) & ~3);

868

} else {

866

} else {

869

memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);

867

memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);

870

memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,

868

memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,

871

skb->len-copy_len);

869

skb->len-copy_len);

872

offset = ((u32)(skb->len-copy_len + 3) & ~3);

870

offset = ((u32)(skb->len-copy_len + 3) & ~3);

873

}

871

}

874

#ifdef NETIF_F_HW_VLAN_TX

872

#ifdef NETIF_F_HW_VLAN_TX

875

if (adapter->vlgrp && vlan_tx_tag_present(skb)) {

873

if (adapter->vlgrp && vlan_tx_tag_present(skb)) {

876

u16 vlan_tag = vlan_tx_tag_get(skb);

874

u16 vlan_tag = vlan_tx_tag_get(skb);

877

vlan_tag = (vlan_tag << 4) |

875

vlan_tag = (vlan_tag << 4) |

878

(vlan_tag >> 13) |

876

(vlan_tag >> 13) |

879

((vlan_tag >> 9) & 0x8);

877

((vlan_tag >> 9) & 0x8);

880

txph->ins_vlan = 1;

878

txph->ins_vlan = 1;

881

txph->vlan = vlan_tag;

879

txph->vlan = vlan_tag;

882

}

880

}

883

#endif

881

#endif

884

if (offset >= adapter->txd_ring_size)

882

if (offset >= adapter->txd_ring_size)

885

offset -= adapter->txd_ring_size;

883

offset -= adapter->txd_ring_size;

886

adapter->txd_write_ptr = offset;

884

adapter->txd_write_ptr = offset;

887

885

888

/* clear txs before send */

886

/* clear txs before send */

889

adapter->txs_ring[adapter->txs_next_clear].update = 0;

887

adapter->txs_ring[adapter->txs_next_clear].update = 0;

890

if (++adapter->txs_next_clear == adapter->txs_ring_size)

888

if (++adapter->txs_next_clear == adapter->txs_ring_size)

891

adapter->txs_next_clear = 0;

889

adapter->txs_next_clear = 0;

892

890

893

ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,

891

ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,

894

(adapter->txd_write_ptr >> 2));

892

(adapter->txd_write_ptr >> 2));

895

893

896

mmiowb();

894

mmiowb();

897

netdev->trans_start = jiffies;

895

netdev->trans_start = jiffies;

898

dev_kfree_skb_any(skb);

896

dev_kfree_skb_any(skb);

899

return NETDEV_TX_OK;

897

return NETDEV_TX_OK;

900

}

898

}

901

899

902

/*

900

/*

903

* atl2_change_mtu - Change the Maximum Transfer Unit

901

* atl2_change_mtu - Change the Maximum Transfer Unit

904

* @netdev: network interface device structure

902

* @netdev: network interface device structure

905

* @new_mtu: new value for maximum frame size

903

* @new_mtu: new value for maximum frame size

906

*

904

*

907

* Returns 0 on success, negative on failure

905

* Returns 0 on success, negative on failure

908

*/

906

*/

909

static int atl2_change_mtu(struct net_device *netdev, int new_mtu)

907

static int atl2_change_mtu(struct net_device *netdev, int new_mtu)

910

{

908

{

911

struct atl2_adapter *adapter = netdev_priv(netdev);

909

struct atl2_adapter *adapter = netdev_priv(netdev);

912

struct atl2_hw *hw = &adapter->hw;

910

struct atl2_hw *hw = &adapter->hw;

913

911

914

if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))

912

if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))

915

return -EINVAL;

913

return -EINVAL;

916

914

917

/* set MTU */

915

/* set MTU */

918

if (hw->max_frame_size != new_mtu) {

916

if (hw->max_frame_size != new_mtu) {

919

netdev->mtu = new_mtu;

917

netdev->mtu = new_mtu;

920

ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +

918

ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +

921

VLAN_SIZE + ETHERNET_FCS_SIZE);

919

VLAN_SIZE + ETHERNET_FCS_SIZE);

922

}

920

}

923

921

924

return 0;

922

return 0;

925

}

923

}

926

924

927

/*

925

/*

928

* atl2_set_mac - Change the Ethernet Address of the NIC

926

* atl2_set_mac - Change the Ethernet Address of the NIC

929

* @netdev: network interface device structure

927

* @netdev: network interface device structure

930

* @p: pointer to an address structure

928

* @p: pointer to an address structure

931

*

929

*

932

* Returns 0 on success, negative on failure

930

* Returns 0 on success, negative on failure

933

*/

931

*/

934

static int atl2_set_mac(struct net_device *netdev, void *p)

932

static int atl2_set_mac(struct net_device *netdev, void *p)

935

{

933

{

936

struct atl2_adapter *adapter = netdev_priv(netdev);

934

struct atl2_adapter *adapter = netdev_priv(netdev);

937

struct sockaddr *addr = p;

935

struct sockaddr *addr = p;

938

936

939

if (!is_valid_ether_addr(addr->sa_data))

937

if (!is_valid_ether_addr(addr->sa_data))

940

return -EADDRNOTAVAIL;

938

return -EADDRNOTAVAIL;

941

939

942

if (netif_running(netdev))

940

if (netif_running(netdev))

943

return -EBUSY;

941

return -EBUSY;

944

942

945

memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);

943

memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);

946

memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);

944

memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);

947

945

948

atl2_set_mac_addr(&adapter->hw);

946

atl2_set_mac_addr(&adapter->hw);

949

947

950

return 0;

948

return 0;

951

}

949

}

952

950

953

/*

951

/*

954

* atl2_mii_ioctl -

952

* atl2_mii_ioctl -

955

* @netdev:

953

* @netdev:

956

* @ifreq:

954

* @ifreq:

957

* @cmd:

955

* @cmd:

958

*/

956

*/

959

static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)

957

static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)

960

{

958

{

961

struct atl2_adapter *adapter = netdev_priv(netdev);

959

struct atl2_adapter *adapter = netdev_priv(netdev);

962

struct mii_ioctl_data *data = if_mii(ifr);

960

struct mii_ioctl_data *data = if_mii(ifr);

963

unsigned long flags;

961

unsigned long flags;

964

962

965

switch (cmd) {

963

switch (cmd) {

966

case SIOCGMIIPHY:

964

case SIOCGMIIPHY:

967

data->phy_id = 0;

965

data->phy_id = 0;

968

break;

966

break;

969

case SIOCGMIIREG:

967

case SIOCGMIIREG:

970

if (!capable(CAP_NET_ADMIN))

968

if (!capable(CAP_NET_ADMIN))

971

return -EPERM;

969

return -EPERM;

972

spin_lock_irqsave(&adapter->stats_lock, flags);

970

spin_lock_irqsave(&adapter->stats_lock, flags);

973

if (atl2_read_phy_reg(&adapter->hw,

971

if (atl2_read_phy_reg(&adapter->hw,

974

data->reg_num & 0x1F, &data->val_out)) {

972

data->reg_num & 0x1F, &data->val_out)) {

975

spin_unlock_irqrestore(&adapter->stats_lock, flags);

973

spin_unlock_irqrestore(&adapter->stats_lock, flags);

976

return -EIO;

974

return -EIO;

977

}

975

}

978

spin_unlock_irqrestore(&adapter->stats_lock, flags);

976

spin_unlock_irqrestore(&adapter->stats_lock, flags);

979

break;

977

break;

980

case SIOCSMIIREG:

978

case SIOCSMIIREG:

981

if (!capable(CAP_NET_ADMIN))

979

if (!capable(CAP_NET_ADMIN))

982

return -EPERM;

980

return -EPERM;

983

if (data->reg_num & ~(0x1F))

981

if (data->reg_num & ~(0x1F))

984

return -EFAULT;

982

return -EFAULT;

985

spin_lock_irqsave(&adapter->stats_lock, flags);

983

spin_lock_irqsave(&adapter->stats_lock, flags);

986

if (atl2_write_phy_reg(&adapter->hw, data->reg_num,

984

if (atl2_write_phy_reg(&adapter->hw, data->reg_num,

987

data->val_in)) {

985

data->val_in)) {

988

spin_unlock_irqrestore(&adapter->stats_lock, flags);

986

spin_unlock_irqrestore(&adapter->stats_lock, flags);

989

return -EIO;

987

return -EIO;

990

}

988

}

991

spin_unlock_irqrestore(&adapter->stats_lock, flags);

989

spin_unlock_irqrestore(&adapter->stats_lock, flags);

992

break;

990

break;

993

default:

991

default:

994

return -EOPNOTSUPP;

992

return -EOPNOTSUPP;

995

}

993

}

996

return 0;

994

return 0;

997

}

995

}

998

996

999

/*

997

/*

1000

* atl2_ioctl -

998

* atl2_ioctl -

1001

* @netdev:

999

* @netdev:

1002

* @ifreq:

1000

* @ifreq:

1003

* @cmd:

1001

* @cmd:

1004

*/

1002

*/

1005

static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)

1003

static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)

1006

{

1004

{

1007

switch (cmd) {

1005

switch (cmd) {

1008

case SIOCGMIIPHY:

1006

case SIOCGMIIPHY:

1009

case SIOCGMIIREG:

1007

case SIOCGMIIREG:

1010

case SIOCSMIIREG:

1008

case SIOCSMIIREG:

1011

return atl2_mii_ioctl(netdev, ifr, cmd);

1009

return atl2_mii_ioctl(netdev, ifr, cmd);

1012

#ifdef ETHTOOL_OPS_COMPAT

1010

#ifdef ETHTOOL_OPS_COMPAT

1013

case SIOCETHTOOL:

1011

case SIOCETHTOOL:

1014

return ethtool_ioctl(ifr);

1012

return ethtool_ioctl(ifr);

1015

#endif

1013

#endif

1016

default:

1014

default:

1017

return -EOPNOTSUPP;

1015

return -EOPNOTSUPP;

1018

}

1016

}

1019

}

1017

}

1020

1018

1021

/*

1019

/*

1022

* atl2_tx_timeout - Respond to a Tx Hang

1020

* atl2_tx_timeout - Respond to a Tx Hang

1023

* @netdev: network interface device structure

1021

* @netdev: network interface device structure

1024

*/

1022

*/

1025

static void atl2_tx_timeout(struct net_device *netdev)

1023

static void atl2_tx_timeout(struct net_device *netdev)

1026

{

1024

{

1027

struct atl2_adapter *adapter = netdev_priv(netdev);

1025

struct atl2_adapter *adapter = netdev_priv(netdev);

1028

1026

1029

/* Do the reset outside of interrupt context */

1027

/* Do the reset outside of interrupt context */

1030

schedule_work(&adapter->reset_task);

1028

schedule_work(&adapter->reset_task);

1031

}

1029

}

1032

1030

1033

/*

1031

/*

1034

* atl2_watchdog - Timer Call-back

1032

* atl2_watchdog - Timer Call-back

1035

* @data: pointer to netdev cast into an unsigned long

1033

* @data: pointer to netdev cast into an unsigned long

1036

*/

1034

*/

1037

static void atl2_watchdog(unsigned long data)

1035

static void atl2_watchdog(unsigned long data)

1038

{

1036

{

1039

struct atl2_adapter *adapter = (struct atl2_adapter *) data;

1037

struct atl2_adapter *adapter = (struct atl2_adapter *) data;

1040

1038

1041

if (!test_bit(__ATL2_DOWN, &adapter->flags)) {

1039

if (!test_bit(__ATL2_DOWN, &adapter->flags)) {

1042

u32 drop_rxd, drop_rxs;

1040

u32 drop_rxd, drop_rxs;

1043

unsigned long flags;

1041

unsigned long flags;

1044

1042

1045

spin_lock_irqsave(&adapter->stats_lock, flags);

1043

spin_lock_irqsave(&adapter->stats_lock, flags);

1046

drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);

1044

drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);

1047

drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);

1045

drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);

1048

spin_unlock_irqrestore(&adapter->stats_lock, flags);

1046

spin_unlock_irqrestore(&adapter->stats_lock, flags);

1049

1047

1050

adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;

1048

adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;

1051

1049

1052

/* Reset the timer */

1050

/* Reset the timer */

1053

mod_timer(&adapter->watchdog_timer,

1051

mod_timer(&adapter->watchdog_timer,

1054

round_jiffies(jiffies + 4 * HZ));

1052

round_jiffies(jiffies + 4 * HZ));

1055

}

1053

}

1056

}

1054

}

1057

1055

1058

/*

1056

/*

1059

* atl2_phy_config - Timer Call-back

1057

* atl2_phy_config - Timer Call-back

1060

* @data: pointer to netdev cast into an unsigned long

1058

* @data: pointer to netdev cast into an unsigned long

1061

*/

1059

*/

1062

static void atl2_phy_config(unsigned long data)

1060

static void atl2_phy_config(unsigned long data)

1063

{

1061

{

1064

struct atl2_adapter *adapter = (struct atl2_adapter *) data;

1062

struct atl2_adapter *adapter = (struct atl2_adapter *) data;

1065

struct atl2_hw *hw = &adapter->hw;

1063

struct atl2_hw *hw = &adapter->hw;

1066

unsigned long flags;

1064

unsigned long flags;

1067

1065

1068

spin_lock_irqsave(&adapter->stats_lock, flags);

1066

spin_lock_irqsave(&adapter->stats_lock, flags);

1069

atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);

1067

atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);

1070

atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |

1068

atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |

1071

MII_CR_RESTART_AUTO_NEG);

1069

MII_CR_RESTART_AUTO_NEG);

1072

spin_unlock_irqrestore(&adapter->stats_lock, flags);

1070

spin_unlock_irqrestore(&adapter->stats_lock, flags);

1073

clear_bit(0, &adapter->cfg_phy);

1071

clear_bit(0, &adapter->cfg_phy);

1074

}

1072

}

1075

1073

1076

static int atl2_up(struct atl2_adapter *adapter)

1074

static int atl2_up(struct atl2_adapter *adapter)

1077

{

1075

{

1078

struct net_device *netdev = adapter->netdev;

1076

struct net_device *netdev = adapter->netdev;

1079

int err = 0;

1077

int err = 0;

1080

u32 val;

1078

u32 val;

1081

1079

1082

/* hardware has been reset, we need to reload some things */

1080

/* hardware has been reset, we need to reload some things */

1083

1081

1084

err = atl2_init_hw(&adapter->hw);

1082

err = atl2_init_hw(&adapter->hw);

1085

if (err) {

1083

if (err) {

1086

err = -EIO;

1084

err = -EIO;

1087

return err;

1085

return err;

1088

}

1086

}

1089

1087

1090

atl2_set_multi(netdev);

1088

atl2_set_multi(netdev);

1091

init_ring_ptrs(adapter);

1089

init_ring_ptrs(adapter);

1092

1090

1093

#ifdef NETIF_F_HW_VLAN_TX

1091

#ifdef NETIF_F_HW_VLAN_TX

1094

atl2_restore_vlan(adapter);

1092

atl2_restore_vlan(adapter);

1095

#endif

1093

#endif

1096

1094

1097

if (atl2_configure(adapter)) {

1095

if (atl2_configure(adapter)) {

1098

err = -EIO;

1096

err = -EIO;

1099

goto err_up;

1097

goto err_up;

1100

}

1098

}

1101

1099

1102

clear_bit(__ATL2_DOWN, &adapter->flags);

1100

clear_bit(__ATL2_DOWN, &adapter->flags);

1103

1101

1104

val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);

1102

val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);

1105

ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |

1103

ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |

1106

MASTER_CTRL_MANUAL_INT);

1104

MASTER_CTRL_MANUAL_INT);

1107

1105

1108

atl2_irq_enable(adapter);

1106

atl2_irq_enable(adapter);

1109

1107

1110

err_up:

1108

err_up:

1111

return err;

1109

return err;

1112

}

1110

}

1113

1111

1114

static void atl2_reinit_locked(struct atl2_adapter *adapter)

1112

static void atl2_reinit_locked(struct atl2_adapter *adapter)

1115

{

1113

{

1116

WARN_ON(in_interrupt());

1114

WARN_ON(in_interrupt());

1117

while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))

1115

while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))

1118

msleep(1);

1116

msleep(1);

1119

atl2_down(adapter);

1117

atl2_down(adapter);

1120

atl2_up(adapter);

1118

atl2_up(adapter);

1121

clear_bit(__ATL2_RESETTING, &adapter->flags);

1119

clear_bit(__ATL2_RESETTING, &adapter->flags);

1122

}

1120

}

1123

1121

1124

static void atl2_reset_task(struct work_struct *work)

1122

static void atl2_reset_task(struct work_struct *work)

1125

{

1123

{

1126

struct atl2_adapter *adapter;

1124

struct atl2_adapter *adapter;

1127

adapter = container_of(work, struct atl2_adapter, reset_task);

1125

adapter = container_of(work, struct atl2_adapter, reset_task);

1128

1126

1129

atl2_reinit_locked(adapter);

1127

atl2_reinit_locked(adapter);

1130

}

1128

}

1131

1129

1132

static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)

1130

static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)

1133

{

1131

{

1134

u32 value;

1132

u32 value;

1135

struct atl2_hw *hw = &adapter->hw;

1133

struct atl2_hw *hw = &adapter->hw;

1136

struct net_device *netdev = adapter->netdev;

1134

struct net_device *netdev = adapter->netdev;

1137

1135

1138

/* Config MAC CTRL Register */

1136

/* Config MAC CTRL Register */

1139

value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;

1137

value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;

1140

1138

1141

/* duplex */

1139

/* duplex */

1142

if (FULL_DUPLEX == adapter->link_duplex)

1140

if (FULL_DUPLEX == adapter->link_duplex)

1143

value |= MAC_CTRL_DUPLX;

1141

value |= MAC_CTRL_DUPLX;

1144

1142

1145

/* flow control */

1143

/* flow control */

1146

value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);

1144

value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);

1147

1145

1148

/* PAD & CRC */

1146

/* PAD & CRC */

1149

value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);

1147

value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);

1150

1148

1151

/* preamble length */

1149

/* preamble length */

1152

value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<

1150

value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<

1153

MAC_CTRL_PRMLEN_SHIFT);

1151

MAC_CTRL_PRMLEN_SHIFT);

1154

1152

1155

/* vlan */

1153

/* vlan */

1156

if (adapter->vlgrp)

1154

if (adapter->vlgrp)

1157

value |= MAC_CTRL_RMV_VLAN;

1155

value |= MAC_CTRL_RMV_VLAN;

1158

1156

1159

/* filter mode */

1157

/* filter mode */

1160

value |= MAC_CTRL_BC_EN;

1158

value |= MAC_CTRL_BC_EN;

1161

if (netdev->flags & IFF_PROMISC)

1159

if (netdev->flags & IFF_PROMISC)

1162

value |= MAC_CTRL_PROMIS_EN;

1160

value |= MAC_CTRL_PROMIS_EN;

1163

else if (netdev->flags & IFF_ALLMULTI)

1161

else if (netdev->flags & IFF_ALLMULTI)

1164

value |= MAC_CTRL_MC_ALL_EN;

1162

value |= MAC_CTRL_MC_ALL_EN;

1165

1163

1166

/* half retry buffer */

1164

/* half retry buffer */

1167

value |= (((u32)(adapter->hw.retry_buf &

1165

value |= (((u32)(adapter->hw.retry_buf &

1168

MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);

1166

MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);

1169

1167

1170

ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);

1168

ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);

1171

}

1169

}

1172

1170

1173

static int atl2_check_link(struct atl2_adapter *adapter)

1171

static int atl2_check_link(struct atl2_adapter *adapter)

1174

{

1172

{

1175

struct atl2_hw *hw = &adapter->hw;

1173

struct atl2_hw *hw = &adapter->hw;

1176

struct net_device *netdev = adapter->netdev;

1174

struct net_device *netdev = adapter->netdev;

1177

int ret_val;

1175

int ret_val;

1178

u16 speed, duplex, phy_data;

1176

u16 speed, duplex, phy_data;

1179

int reconfig = 0;

1177

int reconfig = 0;

1180

1178

1181

/* MII_BMSR must read twise */

1179

/* MII_BMSR must read twise */

1182

atl2_read_phy_reg(hw, MII_BMSR, &phy_data);

1180

atl2_read_phy_reg(hw, MII_BMSR, &phy_data);

1183

atl2_read_phy_reg(hw, MII_BMSR, &phy_data);

1181

atl2_read_phy_reg(hw, MII_BMSR, &phy_data);

1184

if (!(phy_data&BMSR_LSTATUS)) { /* link down */

1182

if (!(phy_data&BMSR_LSTATUS)) { /* link down */

1185

if (netif_carrier_ok(netdev)) { /* old link state: Up */

1183

if (netif_carrier_ok(netdev)) { /* old link state: Up */

1186

u32 value;

1184

u32 value;

1187

/* disable rx */

1185

/* disable rx */

1188

value = ATL2_READ_REG(hw, REG_MAC_CTRL);

1186

value = ATL2_READ_REG(hw, REG_MAC_CTRL);

1189

value &= ~MAC_CTRL_RX_EN;

1187

value &= ~MAC_CTRL_RX_EN;

1190

ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);

1188

ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);

1191

adapter->link_speed = SPEED_0;

1189

adapter->link_speed = SPEED_0;

1192

netif_carrier_off(netdev);

1190

netif_carrier_off(netdev);

1193

netif_stop_queue(netdev);

1191

netif_stop_queue(netdev);

1194

}

1192

}

1195

return 0;

1193

return 0;

1196

}

1194

}

1197

1195

1198

/* Link Up */

1196

/* Link Up */

1199

ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);

1197

ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);

1200

if (ret_val)

1198

if (ret_val)

1201

return ret_val;

1199

return ret_val;

1202

switch (hw->MediaType) {

1200

switch (hw->MediaType) {

1203

case MEDIA_TYPE_100M_FULL:

1201

case MEDIA_TYPE_100M_FULL:

1204

if (speed != SPEED_100 || duplex != FULL_DUPLEX)

1202

if (speed != SPEED_100 || duplex != FULL_DUPLEX)

1205

reconfig = 1;

1203

reconfig = 1;

1206

break;

1204

break;

1207

case MEDIA_TYPE_100M_HALF:

1205

case MEDIA_TYPE_100M_HALF:

1208

if (speed != SPEED_100 || duplex != HALF_DUPLEX)

1206

if (speed != SPEED_100 || duplex != HALF_DUPLEX)

1209

reconfig = 1;

1207

reconfig = 1;

1210

break;

1208

break;

1211

case MEDIA_TYPE_10M_FULL:

1209

case MEDIA_TYPE_10M_FULL:

1212

if (speed != SPEED_10 || duplex != FULL_DUPLEX)

1210

if (speed != SPEED_10 || duplex != FULL_DUPLEX)

1213

reconfig = 1;

1211

reconfig = 1;

1214

break;

1212

break;

1215

case MEDIA_TYPE_10M_HALF:

1213

case MEDIA_TYPE_10M_HALF:

1216

if (speed != SPEED_10 || duplex != HALF_DUPLEX)

1214

if (speed != SPEED_10 || duplex != HALF_DUPLEX)

1217

reconfig = 1;

1215

reconfig = 1;

1218

break;

1216

break;

1219

}

1217

}

1220

/* link result is our setting */

1218

/* link result is our setting */

1221

if (reconfig == 0) {

1219

if (reconfig == 0) {

1222

if (adapter->link_speed != speed ||

1220

if (adapter->link_speed != speed ||

1223

adapter->link_duplex != duplex) {

1221

adapter->link_duplex != duplex) {

1224

adapter->link_speed = speed;

1222

adapter->link_speed = speed;

1225

adapter->link_duplex = duplex;

1223

adapter->link_duplex = duplex;

1226

atl2_setup_mac_ctrl(adapter);

1224

atl2_setup_mac_ctrl(adapter);

1227

printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",

1225

printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",

1228

atl2_driver_name, netdev->name,

1226

atl2_driver_name, netdev->name,

1229

adapter->link_speed,

1227

adapter->link_speed,

1230

adapter->link_duplex == FULL_DUPLEX ?

1228

adapter->link_duplex == FULL_DUPLEX ?

1231

"Full Duplex" : "Half Duplex");

1229

"Full Duplex" : "Half Duplex");

1232

}

1230

}

1233

1231

1234

if (!netif_carrier_ok(netdev)) { /* Link down -> Up */

1232

if (!netif_carrier_ok(netdev)) { /* Link down -> Up */

1235

netif_carrier_on(netdev);

1233

netif_carrier_on(netdev);

1236

netif_wake_queue(netdev);

1234

netif_wake_queue(netdev);

1237

}

1235

}

1238

return 0;

1236

return 0;

1239

}

1237

}

1240

1238

1241

/* change original link status */

1239

/* change original link status */

1242

if (netif_carrier_ok(netdev)) {

1240

if (netif_carrier_ok(netdev)) {

1243

u32 value;

1241

u32 value;

1244

/* disable rx */

1242

/* disable rx */

1245

value = ATL2_READ_REG(hw, REG_MAC_CTRL);

1243

value = ATL2_READ_REG(hw, REG_MAC_CTRL);

1246

value &= ~MAC_CTRL_RX_EN;

1244

value &= ~MAC_CTRL_RX_EN;

1247

ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);

1245

ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);

1248

1246

1249

adapter->link_speed = SPEED_0;

1247

adapter->link_speed = SPEED_0;

1250

netif_carrier_off(netdev);

1248

netif_carrier_off(netdev);

1251

netif_stop_queue(netdev);

1249

netif_stop_queue(netdev);

1252

}

1250

}

1253

1251

1254

/* auto-neg, insert timer to re-config phy

1252

/* auto-neg, insert timer to re-config phy

1255

* (if interval smaller than 5 seconds, something strange) */

1253

* (if interval smaller than 5 seconds, something strange) */

1256

if (!test_bit(__ATL2_DOWN, &adapter->flags)) {

1254

if (!test_bit(__ATL2_DOWN, &adapter->flags)) {

1257

if (!test_and_set_bit(0, &adapter->cfg_phy))

1255

if (!test_and_set_bit(0, &adapter->cfg_phy))

1258

mod_timer(&adapter->phy_config_timer,

1256

mod_timer(&adapter->phy_config_timer,

1259

round_jiffies(jiffies + 5 * HZ));

1257

round_jiffies(jiffies + 5 * HZ));

1260

}

1258

}

1261

1259

1262

return 0;

1260

return 0;

1263

}

1261

}

1264

1262

1265

/*

1263

/*

1266

* atl2_link_chg_task - deal with link change event Out of interrupt context

1264

* atl2_link_chg_task - deal with link change event Out of interrupt context

1267

* @netdev: network interface device structure

1265

* @netdev: network interface device structure

1268

*/

1266

*/

1269

static void atl2_link_chg_task(struct work_struct *work)

1267

static void atl2_link_chg_task(struct work_struct *work)

1270

{

1268

{

1271

struct atl2_adapter *adapter;

1269

struct atl2_adapter *adapter;

1272

unsigned long flags;

1270

unsigned long flags;

1273

1271

1274

adapter = container_of(work, struct atl2_adapter, link_chg_task);

1272

adapter = container_of(work, struct atl2_adapter, link_chg_task);

1275

1273

1276

spin_lock_irqsave(&adapter->stats_lock, flags);

1274

spin_lock_irqsave(&adapter->stats_lock, flags);

1277

atl2_check_link(adapter);

1275

atl2_check_link(adapter);

1278

spin_unlock_irqrestore(&adapter->stats_lock, flags);

1276

spin_unlock_irqrestore(&adapter->stats_lock, flags);

1279

}

1277

}

1280

1278

1281

static void atl2_setup_pcicmd(struct pci_dev *pdev)

1279

static void atl2_setup_pcicmd(struct pci_dev *pdev)

1282

{

1280

{

1283

u16 cmd;

1281

u16 cmd;

1284

1282

1285

pci_read_config_word(pdev, PCI_COMMAND, &cmd);

1283

pci_read_config_word(pdev, PCI_COMMAND, &cmd);

1286

1284

1287

if (cmd & PCI_COMMAND_INTX_DISABLE)

1285

if (cmd & PCI_COMMAND_INTX_DISABLE)

1288

cmd &= ~PCI_COMMAND_INTX_DISABLE;

1286

cmd &= ~PCI_COMMAND_INTX_DISABLE;

1289

if (cmd & PCI_COMMAND_IO)

1287

if (cmd & PCI_COMMAND_IO)

1290

cmd &= ~PCI_COMMAND_IO;

1288

cmd &= ~PCI_COMMAND_IO;

1291

if (0 == (cmd & PCI_COMMAND_MEMORY))

1289

if (0 == (cmd & PCI_COMMAND_MEMORY))

1292

cmd |= PCI_COMMAND_MEMORY;

1290

cmd |= PCI_COMMAND_MEMORY;

1293

if (0 == (cmd & PCI_COMMAND_MASTER))

1291

if (0 == (cmd & PCI_COMMAND_MASTER))

1294

cmd |= PCI_COMMAND_MASTER;

1292

cmd |= PCI_COMMAND_MASTER;

1295

pci_write_config_word(pdev, PCI_COMMAND, cmd);

1293

pci_write_config_word(pdev, PCI_COMMAND, cmd);

1296

1294

1297

/*

1295

/*

1298

* some motherboards BIOS(PXE/EFI) driver may set PME

1296

* some motherboards BIOS(PXE/EFI) driver may set PME

1299

* while they transfer control to OS (Windows/Linux)

1297

* while they transfer control to OS (Windows/Linux)

1300

* so we should clear this bit before NIC work normally

1298

* so we should clear this bit before NIC work normally

1301

*/

1299

*/

1302

pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);

1300

pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);

1303

}

1301

}

1304

1302

1305

#ifdef CONFIG_NET_POLL_CONTROLLER

1303

#ifdef CONFIG_NET_POLL_CONTROLLER

1306

static void atl2_poll_controller(struct net_device *netdev)

1304

static void atl2_poll_controller(struct net_device *netdev)

1307

{

1305

{

1308

disable_irq(netdev->irq);

1306

disable_irq(netdev->irq);

1309

atl2_intr(netdev->irq, netdev);

1307

atl2_intr(netdev->irq, netdev);

1310

enable_irq(netdev->irq);

1308

enable_irq(netdev->irq);

1311

}

1309

}

1312

#endif

1310

#endif

1313

1311

1314

1312

1315

static const struct net_device_ops atl2_netdev_ops = {

1313

static const struct net_device_ops atl2_netdev_ops = {

1316

.ndo_open = atl2_open,

1314

.ndo_open = atl2_open,

1317

.ndo_stop = atl2_close,

1315

.ndo_stop = atl2_close,

1318

.ndo_start_xmit = atl2_xmit_frame,

1316

.ndo_start_xmit = atl2_xmit_frame,

1319

.ndo_set_multicast_list = atl2_set_multi,

1317

.ndo_set_multicast_list = atl2_set_multi,

1320

.ndo_validate_addr = eth_validate_addr,

1318

.ndo_validate_addr = eth_validate_addr,

1321

.ndo_set_mac_address = atl2_set_mac,

1319

.ndo_set_mac_address = atl2_set_mac,

1322

.ndo_change_mtu = atl2_change_mtu,

1320

.ndo_change_mtu = atl2_change_mtu,

1323

.ndo_do_ioctl = atl2_ioctl,

1321

.ndo_do_ioctl = atl2_ioctl,

1324

.ndo_tx_timeout = atl2_tx_timeout,

1322

.ndo_tx_timeout = atl2_tx_timeout,

1325

.ndo_vlan_rx_register = atl2_vlan_rx_register,

1323

.ndo_vlan_rx_register = atl2_vlan_rx_register,

1326

#ifdef CONFIG_NET_POLL_CONTROLLER

1324

#ifdef CONFIG_NET_POLL_CONTROLLER

1327

.ndo_poll_controller = atl2_poll_controller,

1325

.ndo_poll_controller = atl2_poll_controller,

1328

#endif

1326

#endif

1329

};

1327

};

1330

1328

1331

/*

1329

/*

1332

* atl2_probe - Device Initialization Routine

1330

* atl2_probe - Device Initialization Routine

1333

* @pdev: PCI device information struct

1331

* @pdev: PCI device information struct

1334

* @ent: entry in atl2_pci_tbl

1332

* @ent: entry in atl2_pci_tbl

1335

*

1333

*

1336

* Returns 0 on success, negative on failure

1334

* Returns 0 on success, negative on failure

1337

*

1335

*

1338

* atl2_probe initializes an adapter identified by a pci_dev structure.

1336

* atl2_probe initializes an adapter identified by a pci_dev structure.

1339

* The OS initialization, configuring of the adapter private structure,

1337

* The OS initialization, configuring of the adapter private structure,

1340

* and a hardware reset occur.

1338

* and a hardware reset occur.

1341

*/

1339

*/

1342

static int __devinit atl2_probe(struct pci_dev *pdev,

1340

static int __devinit atl2_probe(struct pci_dev *pdev,

1343

const struct pci_device_id *ent)

1341

const struct pci_device_id *ent)

1344

{

1342

{

1345

struct net_device *netdev;

1343

struct net_device *netdev;

1346

struct atl2_adapter *adapter;

1344

struct atl2_adapter *adapter;

1347

static int cards_found;

1345

static int cards_found;

1348

unsigned long mmio_start;

1346

unsigned long mmio_start;

1349

int mmio_len;

1347

int mmio_len;

1350

int err;

1348

int err;

1351

1349

1352

cards_found = 0;

1350

cards_found = 0;

1353

1351

1354

err = pci_enable_device(pdev);

1352

err = pci_enable_device(pdev);

1355

if (err)

1353

if (err)

1356

return err;

1354

return err;

1357

1355

1358

/*

1356

/*

1359

* atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA

1357

* atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA

1360

* until the kernel has the proper infrastructure to support 64-bit DMA

1358

* until the kernel has the proper infrastructure to support 64-bit DMA

1361

* on these devices.

1359

* on these devices.

1362

*/

1360

*/

1363

if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) &&

1361

if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) &&

1364

pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {

1362

pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {

1365

printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");

1363

printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");

1366

goto err_dma;

1364

goto err_dma;

1367

}

1365

}

1368

1366

1369

/* Mark all PCI regions associated with PCI device

1367

/* Mark all PCI regions associated with PCI device

1370

* pdev as being reserved by owner atl2_driver_name */

1368

* pdev as being reserved by owner atl2_driver_name */

1371

err = pci_request_regions(pdev, atl2_driver_name);

1369

err = pci_request_regions(pdev, atl2_driver_name);

1372

if (err)

1370

if (err)

1373

goto err_pci_reg;

1371

goto err_pci_reg;

1374

1372

1375

/* Enables bus-mastering on the device and calls

1373

/* Enables bus-mastering on the device and calls

1376

* pcibios_set_master to do the needed arch specific settings */

1374

* pcibios_set_master to do the needed arch specific settings */

1377

pci_set_master(pdev);

1375

pci_set_master(pdev);

1378

1376

1379

err = -ENOMEM;

1377

err = -ENOMEM;

1380

netdev = alloc_etherdev(sizeof(struct atl2_adapter));

1378

netdev = alloc_etherdev(sizeof(struct atl2_adapter));

1381

if (!netdev)

1379

if (!netdev)

1382

goto err_alloc_etherdev;

1380

goto err_alloc_etherdev;

1383

1381

1384

SET_NETDEV_DEV(netdev, &pdev->dev);

1382

SET_NETDEV_DEV(netdev, &pdev->dev);

1385

1383

1386

pci_set_drvdata(pdev, netdev);

1384

pci_set_drvdata(pdev, netdev);

1387

adapter = netdev_priv(netdev);

1385

adapter = netdev_priv(netdev);

1388

adapter->netdev = netdev;

1386

adapter->netdev = netdev;

1389

adapter->pdev = pdev;

1387

adapter->pdev = pdev;

1390

adapter->hw.back = adapter;

1388

adapter->hw.back = adapter;

1391

1389

1392

mmio_start = pci_resource_start(pdev, 0x0);

1390

mmio_start = pci_resource_start(pdev, 0x0);

1393

mmio_len = pci_resource_len(pdev, 0x0);

1391

mmio_len = pci_resource_len(pdev, 0x0);

1394

1392

1395

adapter->hw.mem_rang = (u32)mmio_len;

1393

adapter->hw.mem_rang = (u32)mmio_len;

1396

adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);

1394

adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);

1397

if (!adapter->hw.hw_addr) {

1395

if (!adapter->hw.hw_addr) {

1398

err = -EIO;

1396

err = -EIO;

1399

goto err_ioremap;

1397

goto err_ioremap;

1400

}

1398

}

1401

1399

1402

atl2_setup_pcicmd(pdev);

1400

atl2_setup_pcicmd(pdev);

1403

1401

1404

netdev->netdev_ops = &atl2_netdev_ops;

1402

netdev->netdev_ops = &atl2_netdev_ops;

1405

atl2_set_ethtool_ops(netdev);

1403

atl2_set_ethtool_ops(netdev);

1406

netdev->watchdog_timeo = 5 * HZ;

1404

netdev->watchdog_timeo = 5 * HZ;

1407

strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);

1405

strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);

1408

1406

1409

netdev->mem_start = mmio_start;

1407

netdev->mem_start = mmio_start;

1410

netdev->mem_end = mmio_start + mmio_len;

1408

netdev->mem_end = mmio_start + mmio_len;

1411

adapter->bd_number = cards_found;

1409

adapter->bd_number = cards_found;

1412

adapter->pci_using_64 = false;

1410

adapter->pci_using_64 = false;

1413

1411

1414

/* setup the private structure */

1412

/* setup the private structure */

1415

err = atl2_sw_init(adapter);

1413

err = atl2_sw_init(adapter);

1416

if (err)

1414

if (err)

1417

goto err_sw_init;

1415

goto err_sw_init;

1418

1416

1419

err = -EIO;

1417

err = -EIO;

1420

1418

1421

#ifdef NETIF_F_HW_VLAN_TX

1419

#ifdef NETIF_F_HW_VLAN_TX

1422

netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);

1420

netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);

1423

#endif

1421

#endif

1424

1422

1425

/* Init PHY as early as possible due to power saving issue */

1423

/* Init PHY as early as possible due to power saving issue */

1426

atl2_phy_init(&adapter->hw);

1424

atl2_phy_init(&adapter->hw);

1427

1425

1428

/* reset the controller to

1426

/* reset the controller to

1429

* put the device in a known good starting state */

1427

* put the device in a known good starting state */

1430

1428

1431

if (atl2_reset_hw(&adapter->hw)) {

1429

if (atl2_reset_hw(&adapter->hw)) {

1432

err = -EIO;

1430

err = -EIO;

1433

goto err_reset;

1431

goto err_reset;

1434

}

1432

}

1435

1433

1436

/* copy the MAC address out of the EEPROM */

1434

/* copy the MAC address out of the EEPROM */

1437

atl2_read_mac_addr(&adapter->hw);

1435

atl2_read_mac_addr(&adapter->hw);

1438

memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);

1436

memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);

1439

/* FIXME: do we still need this? */

1437

/* FIXME: do we still need this? */

1440

#ifdef ETHTOOL_GPERMADDR

1438

#ifdef ETHTOOL_GPERMADDR

1441

memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);

1439

memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);

1442

1440

1443

if (!is_valid_ether_addr(netdev->perm_addr)) {

1441

if (!is_valid_ether_addr(netdev->perm_addr)) {

1444

#else

1442

#else

1445

if (!is_valid_ether_addr(netdev->dev_addr)) {

1443

if (!is_valid_ether_addr(netdev->dev_addr)) {

1446

#endif

1444

#endif

1447

err = -EIO;

1445

err = -EIO;

1448

goto err_eeprom;

1446

goto err_eeprom;

1449

}

1447

}

1450

1448

1451

atl2_check_options(adapter);

1449

atl2_check_options(adapter);

1452

1450

1453

init_timer(&adapter->watchdog_timer);

1451

init_timer(&adapter->watchdog_timer);

1454

adapter->watchdog_timer.function = &atl2_watchdog;

1452

adapter->watchdog_timer.function = &atl2_watchdog;

1455

adapter->watchdog_timer.data = (unsigned long) adapter;

1453

adapter->watchdog_timer.data = (unsigned long) adapter;

1456

1454

1457

init_timer(&adapter->phy_config_timer);

1455

init_timer(&adapter->phy_config_timer);

1458

adapter->phy_config_timer.function = &atl2_phy_config;

1456

adapter->phy_config_timer.function = &atl2_phy_config;

1459

adapter->phy_config_timer.data = (unsigned long) adapter;

1457

adapter->phy_config_timer.data = (unsigned long) adapter;

1460

1458

1461

INIT_WORK(&adapter->reset_task, atl2_reset_task);

1459

INIT_WORK(&adapter->reset_task, atl2_reset_task);

1462

INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);

1460

INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);

1463

1461

1464

strcpy(netdev->name, "eth%d"); /* ?? */

1462

strcpy(netdev->name, "eth%d"); /* ?? */

1465

err = register_netdev(netdev);

1463

err = register_netdev(netdev);

1466

if (err)

1464

if (err)

1467

goto err_register;

1465

goto err_register;

1468

1466

1469

/* assume we have no link for now */

1467

/* assume we have no link for now */

1470

netif_carrier_off(netdev);

1468

netif_carrier_off(netdev);

1471

netif_stop_queue(netdev);

1469

netif_stop_queue(netdev);

1472

1470

1473

cards_found++;

1471

cards_found++;

1474

1472

1475

return 0;

1473

return 0;

1476

1474

1477

err_reset:

1475

err_reset:

1478

err_register:

1476

err_register:

1479

err_sw_init:

1477

err_sw_init:

1480

err_eeprom:

1478

err_eeprom:

1481

iounmap(adapter->hw.hw_addr);

1479

iounmap(adapter->hw.hw_addr);

1482

err_ioremap:

1480

err_ioremap:

1483

free_netdev(netdev);

1481

free_netdev(netdev);

1484

err_alloc_etherdev:

1482

err_alloc_etherdev:

1485

pci_release_regions(pdev);

1483

pci_release_regions(pdev);

1486

err_pci_reg:

1484

err_pci_reg:

1487

err_dma:

1485

err_dma:

1488

pci_disable_device(pdev);

1486

pci_disable_device(pdev);

1489

return err;

1487

return err;

1490

}

1488

}

1491

1489

1492

/*

1490

/*

1493

* atl2_remove - Device Removal Routine

1491

* atl2_remove - Device Removal Routine

1494

* @pdev: PCI device information struct

1492

* @pdev: PCI device information struct

1495

*

1493

*

1496

* atl2_remove is called by the PCI subsystem to alert the driver

1494

* atl2_remove is called by the PCI subsystem to alert the driver

1497

* that it should release a PCI device. The could be caused by a

1495

* that it should release a PCI device. The could be caused by a

1498

* Hot-Plug event, or because the driver is going to be removed from

1496

* Hot-Plug event, or because the driver is going to be removed from

1499

* memory.

1497

* memory.

1500

*/

1498

*/

1501

/* FIXME: write the original MAC address back in case it was changed from a

1499

/* FIXME: write the original MAC address back in case it was changed from a

1502

* BIOS-set value, as in atl1 -- CHS */

1500

* BIOS-set value, as in atl1 -- CHS */

1503

static void __devexit atl2_remove(struct pci_dev *pdev)

1501

static void __devexit atl2_remove(struct pci_dev *pdev)

1504

{

1502

{

1505

struct net_device *netdev = pci_get_drvdata(pdev);

1503

struct net_device *netdev = pci_get_drvdata(pdev);

1506

struct atl2_adapter *adapter = netdev_priv(netdev);

1504

struct atl2_adapter *adapter = netdev_priv(netdev);

1507

1505

1508

/* flush_scheduled work may reschedule our watchdog task, so

1506

/* flush_scheduled work may reschedule our watchdog task, so

1509

* explicitly disable watchdog tasks from being rescheduled */

1507

* explicitly disable watchdog tasks from being rescheduled */

1510

set_bit(__ATL2_DOWN, &adapter->flags);

1508

set_bit(__ATL2_DOWN, &adapter->flags);

1511

1509

1512

del_timer_sync(&adapter->watchdog_timer);

1510

del_timer_sync(&adapter->watchdog_timer);

1513

del_timer_sync(&adapter->phy_config_timer);

1511

del_timer_sync(&adapter->phy_config_timer);

1514

1512

1515

flush_scheduled_work();

1513

flush_scheduled_work();

1516

1514

1517

unregister_netdev(netdev);

1515

unregister_netdev(netdev);

1518

1516

1519

atl2_force_ps(&adapter->hw);

1517

atl2_force_ps(&adapter->hw);

1520

1518

1521

iounmap(adapter->hw.hw_addr);

1519

iounmap(adapter->hw.hw_addr);

1522

pci_release_regions(pdev);

1520

pci_release_regions(pdev);

1523

1521

1524

free_netdev(netdev);

1522

free_netdev(netdev);

1525

1523

1526

pci_disable_device(pdev);

1524

pci_disable_device(pdev);

1527

}

1525

}

1528

1526

1529

static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)

1527

static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)

1530

{

1528

{

1531

struct net_device *netdev = pci_get_drvdata(pdev);

1529

struct net_device *netdev = pci_get_drvdata(pdev);

1532

struct atl2_adapter *adapter = netdev_priv(netdev);

1530

struct atl2_adapter *adapter = netdev_priv(netdev);

1533

struct atl2_hw *hw = &adapter->hw;

1531

struct atl2_hw *hw = &adapter->hw;

1534

u16 speed, duplex;

1532

u16 speed, duplex;

1535

u32 ctrl = 0;

1533

u32 ctrl = 0;

1536

u32 wufc = adapter->wol;

1534

u32 wufc = adapter->wol;

1537

1535

1538

#ifdef CONFIG_PM

1536

#ifdef CONFIG_PM

1539

int retval = 0;

1537

int retval = 0;

1540

#endif

1538

#endif

1541

1539

1542

netif_device_detach(netdev);

1540

netif_device_detach(netdev);

1543

1541

1544

if (netif_running(netdev)) {

1542

if (netif_running(netdev)) {

1545

WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));

1543

WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));

1546

atl2_down(adapter);

1544

atl2_down(adapter);

1547

}

1545

}

1548

1546

1549

#ifdef CONFIG_PM

1547

#ifdef CONFIG_PM

1550

retval = pci_save_state(pdev);

1548

retval = pci_save_state(pdev);

1551

if (retval)

1549

if (retval)

1552

return retval;

1550

return retval;

1553

#endif

1551

#endif

1554

1552

1555

atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);

1553

atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);

1556

atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);

1554

atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);

1557

if (ctrl & BMSR_LSTATUS)

1555

if (ctrl & BMSR_LSTATUS)

1558

wufc &= ~ATLX_WUFC_LNKC;

1556

wufc &= ~ATLX_WUFC_LNKC;

1559

1557

1560

if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {

1558

if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {

1561

u32 ret_val;

1559

u32 ret_val;

1562

/* get current link speed & duplex */

1560

/* get current link speed & duplex */

1563

ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);

1561

ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);

1564

if (ret_val) {

1562

if (ret_val) {

1565

printk(KERN_DEBUG

1563

printk(KERN_DEBUG

1566

"%s: get speed&duplex error while suspend\n",

1564

"%s: get speed&duplex error while suspend\n",

1567

atl2_driver_name);

1565

atl2_driver_name);

1568

goto wol_dis;

1566

goto wol_dis;

1569

}

1567

}

1570

1568

1571

ctrl = 0;

1569

ctrl = 0;

1572

1570

1573

/* turn on magic packet wol */

1571

/* turn on magic packet wol */

1574

if (wufc & ATLX_WUFC_MAG)

1572

if (wufc & ATLX_WUFC_MAG)

1575

ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);

1573

ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);

1576

1574

1577

/* ignore Link Chg event when Link is up */

1575

/* ignore Link Chg event when Link is up */

1578

ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);

1576

ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);

1579

1577

1580

/* Config MAC CTRL Register */

1578

/* Config MAC CTRL Register */

1581

ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;

1579

ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;

1582

if (FULL_DUPLEX == adapter->link_duplex)

1580

if (FULL_DUPLEX == adapter->link_duplex)

1583

ctrl |= MAC_CTRL_DUPLX;

1581

ctrl |= MAC_CTRL_DUPLX;

1584

ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);

1582

ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);

1585

ctrl |= (((u32)adapter->hw.preamble_len &

1583

ctrl |= (((u32)adapter->hw.preamble_len &

1586

MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);

1584

MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);

1587

ctrl |= (((u32)(adapter->hw.retry_buf &

1585

ctrl |= (((u32)(adapter->hw.retry_buf &

1588

MAC_CTRL_HALF_LEFT_BUF_MASK)) <<

1586

MAC_CTRL_HALF_LEFT_BUF_MASK)) <<

1589

MAC_CTRL_HALF_LEFT_BUF_SHIFT);

1587

MAC_CTRL_HALF_LEFT_BUF_SHIFT);

1590

if (wufc & ATLX_WUFC_MAG) {

1588

if (wufc & ATLX_WUFC_MAG) {

1591

/* magic packet maybe Broadcast&multicast&Unicast */

1589

/* magic packet maybe Broadcast&multicast&Unicast */

1592

ctrl |= MAC_CTRL_BC_EN;

1590

ctrl |= MAC_CTRL_BC_EN;

1593

}

1591

}

1594

1592

1595

ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);

1593

ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);

1596

1594

1597

/* pcie patch */

1595

/* pcie patch */

1598

ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);

1596

ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);

1599

ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;

1597

ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;

1600

ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);

1598

ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);

1601

ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);

1599

ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);

1602

ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;

1600

ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;

1603

ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);

1601

ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);

1604

1602

1605

pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);

1603

pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);

1606

goto suspend_exit;

1604

goto suspend_exit;

1607

}

1605

}

1608

1606

1609

if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {

1607

if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {

1610

/* link is down, so only LINK CHG WOL event enable */

1608

/* link is down, so only LINK CHG WOL event enable */

1611

ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);

1609

ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);

1612

ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);

1610

ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);

1613

ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);

1611

ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);

1614

1612

1615

/* pcie patch */

1613

/* pcie patch */

1616

ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);

1614

ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);

1617

ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;

1615

ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;

1618

ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);

1616

ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);

1619

ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);

1617

ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);

1620

ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;

1618

ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;

1621

ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);

1619

ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);

1622

1620

1623

hw->phy_configured = false; /* re-init PHY when resume */

1621

hw->phy_configured = false; /* re-init PHY when resume */

1624

1622

1625

pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);

1623

pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);

1626

1624

1627

goto suspend_exit;

1625

goto suspend_exit;

1628

}

1626

}

1629

1627

1630

wol_dis:

1628

wol_dis:

1631

/* WOL disabled */

1629

/* WOL disabled */

1632

ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);

1630

ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);

1633

1631

1634

/* pcie patch */

1632

/* pcie patch */

1635

ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);

1633

ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);

1636

ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;

1634

ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;

1637

ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);

1635

ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);

1638

ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);

1636

ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);

1639

ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;

1637

ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;

1640

ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);

1638

ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);

1641

1639

1642

atl2_force_ps(hw);

1640

atl2_force_ps(hw);

1643

hw->phy_configured = false; /* re-init PHY when resume */

1641

hw->phy_configured = false; /* re-init PHY when resume */

1644

1642

1645

pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);

1643

pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);

1646

1644

1647

suspend_exit:

1645

suspend_exit:

1648

if (netif_running(netdev))

1646

if (netif_running(netdev))

1649

atl2_free_irq(adapter);

1647

atl2_free_irq(adapter);

1650

1648

1651

pci_disable_device(pdev);

1649

pci_disable_device(pdev);

1652

1650

1653

pci_set_power_state(pdev, pci_choose_state(pdev, state));

1651

pci_set_power_state(pdev, pci_choose_state(pdev, state));

1654

1652

1655

return 0;

1653

return 0;

1656

}

1654

}

1657

1655

1658

#ifdef CONFIG_PM

1656

#ifdef CONFIG_PM

1659

static int atl2_resume(struct pci_dev *pdev)

1657

static int atl2_resume(struct pci_dev *pdev)

1660

{

1658

{

1661

struct net_device *netdev = pci_get_drvdata(pdev);

1659

struct net_device *netdev = pci_get_drvdata(pdev);

1662

struct atl2_adapter *adapter = netdev_priv(netdev);

1660

struct atl2_adapter *adapter = netdev_priv(netdev);

1663

u32 err;

1661

u32 err;

1664

1662

1665

pci_set_power_state(pdev, PCI_D0);

1663

pci_set_power_state(pdev, PCI_D0);

1666

pci_restore_state(pdev);

1664

pci_restore_state(pdev);

1667

1665

1668

err = pci_enable_device(pdev);

1666

err = pci_enable_device(pdev);

1669

if (err) {

1667

if (err) {

1670

printk(KERN_ERR

1668

printk(KERN_ERR

1671

"atl2: Cannot enable PCI device from suspend\n");

1669

"atl2: Cannot enable PCI device from suspend\n");

1672

return err;

1670

return err;

1673

}

1671

}

1674

1672

1675

pci_set_master(pdev);

1673

pci_set_master(pdev);

1676

1674

1677

ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */

1675

ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */

1678

1676

1679

pci_enable_wake(pdev, PCI_D3hot, 0);

1677

pci_enable_wake(pdev, PCI_D3hot, 0);

1680

pci_enable_wake(pdev, PCI_D3cold, 0);

1678

pci_enable_wake(pdev, PCI_D3cold, 0);

1681

1679

1682

ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);

1680

ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);

1683

1681

1684

if (netif_running(netdev)) {

1682

if (netif_running(netdev)) {

1685

err = atl2_request_irq(adapter);

1683

err = atl2_request_irq(adapter);

1686

if (err)

1684

if (err)

1687

return err;

1685

return err;

1688

}

1686

}

1689

1687

1690

atl2_reset_hw(&adapter->hw);

1688

atl2_reset_hw(&adapter->hw);

1691

1689

1692

if (netif_running(netdev))

1690

if (netif_running(netdev))

1693

atl2_up(adapter);

1691

atl2_up(adapter);

1694

1692

1695

netif_device_attach(netdev);

1693

netif_device_attach(netdev);

1696

1694

1697

return 0;

1695

return 0;

1698

}

1696

}

1699

#endif

1697

#endif

1700

1698

1701

static void atl2_shutdown(struct pci_dev *pdev)

1699

static void atl2_shutdown(struct pci_dev *pdev)

1702

{

1700

{

1703

atl2_suspend(pdev, PMSG_SUSPEND);

1701

atl2_suspend(pdev, PMSG_SUSPEND);

1704

}

1702

}

1705

1703

1706

static struct pci_driver atl2_driver = {

1704

static struct pci_driver atl2_driver = {

1707

.name = atl2_driver_name,

1705

.name = atl2_driver_name,

1708

.id_table = atl2_pci_tbl,

1706

.id_table = atl2_pci_tbl,

1709

.probe = atl2_probe,

1707

.probe = atl2_probe,

1710

.remove = __devexit_p(atl2_remove),

1708

.remove = __devexit_p(atl2_remove),

1711

/* Power Managment Hooks */

1709

/* Power Managment Hooks */

1712

.suspend = atl2_suspend,

1710

.suspend = atl2_suspend,

1713

#ifdef CONFIG_PM

1711

#ifdef CONFIG_PM

1714

.resume = atl2_resume,

1712

.resume = atl2_resume,

1715

#endif

1713

#endif

1716

.shutdown = atl2_shutdown,

1714

.shutdown = atl2_shutdown,

1717

};

1715

};

1718

1716

1719

/*

1717

/*

1720

* atl2_init_module - Driver Registration Routine

1718

* atl2_init_module - Driver Registration Routine

1721

*

1719

*

1722

* atl2_init_module is the first routine called when the driver is

1720

* atl2_init_module is the first routine called when the driver is

1723

* loaded. All it does is register with the PCI subsystem.

1721

* loaded. All it does is register with the PCI subsystem.

1724

*/

1722

*/

1725

static int __init atl2_init_module(void)

1723

static int __init atl2_init_module(void)

1726

{

1724

{

1727

printk(KERN_INFO "%s - version %s\n", atl2_driver_string,

1725

printk(KERN_INFO "%s - version %s\n", atl2_driver_string,

1728

atl2_driver_version);

1726

atl2_driver_version);

1729

printk(KERN_INFO "%s\n", atl2_copyright);

1727

printk(KERN_INFO "%s\n", atl2_copyright);

1730

return pci_register_driver(&atl2_driver);

1728

return pci_register_driver(&atl2_driver);

1731

}

1729

}

1732

module_init(atl2_init_module);

1730

module_init(atl2_init_module);

1733

1731

1734

/*

1732

/*

1735

* atl2_exit_module - Driver Exit Cleanup Routine

1733

* atl2_exit_module - Driver Exit Cleanup Routine

1736

*

1734

*

1737

* atl2_exit_module is called just before the driver is removed

1735

* atl2_exit_module is called just before the driver is removed

1738

* from memory.

1736

* from memory.

1739

*/

1737

*/

1740

static void __exit atl2_exit_module(void)

1738

static void __exit atl2_exit_module(void)

1741

{

1739

{

1742

pci_unregister_driver(&atl2_driver);

1740

pci_unregister_driver(&atl2_driver);

1743

}

1741

}

1744

module_exit(atl2_exit_module);

1742

module_exit(atl2_exit_module);

1745

1743

1746

static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)

1744

static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)

1747

{

1745

{

1748

struct atl2_adapter *adapter = hw->back;

1746

struct atl2_adapter *adapter = hw->back;

1749

pci_read_config_word(adapter->pdev, reg, value);

1747

pci_read_config_word(adapter->pdev, reg, value);

1750

}

1748

}

1751

1749

1752

static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)

1750

static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)

1753

{

1751

{

1754

struct atl2_adapter *adapter = hw->back;

1752

struct atl2_adapter *adapter = hw->back;

1755

pci_write_config_word(adapter->pdev, reg, *value);

1753

pci_write_config_word(adapter->pdev, reg, *value);

1756

}

1754

}

1757

1755

1758

static int atl2_get_settings(struct net_device *netdev,

1756

static int atl2_get_settings(struct net_device *netdev,

1759

struct ethtool_cmd *ecmd)

1757

struct ethtool_cmd *ecmd)

1760

{

1758

{

1761

struct atl2_adapter *adapter = netdev_priv(netdev);

1759

struct atl2_adapter *adapter = netdev_priv(netdev);

1762

struct atl2_hw *hw = &adapter->hw;

1760

struct atl2_hw *hw = &adapter->hw;

1763

1761

1764

ecmd->supported = (SUPPORTED_10baseT_Half |

1762

ecmd->supported = (SUPPORTED_10baseT_Half |

1765

SUPPORTED_10baseT_Full |

1763

SUPPORTED_10baseT_Full |

1766

SUPPORTED_100baseT_Half |

1764

SUPPORTED_100baseT_Half |

1767

SUPPORTED_100baseT_Full |

1765

SUPPORTED_100baseT_Full |

1768

SUPPORTED_Autoneg |

1766

SUPPORTED_Autoneg |

1769

SUPPORTED_TP);

1767

SUPPORTED_TP);

1770

ecmd->advertising = ADVERTISED_TP;

1768

ecmd->advertising = ADVERTISED_TP;

1771

1769

1772

ecmd->advertising |= ADVERTISED_Autoneg;

1770

ecmd->advertising |= ADVERTISED_Autoneg;

1773

ecmd->advertising |= hw->autoneg_advertised;

1771

ecmd->advertising |= hw->autoneg_advertised;

1774

1772

1775

ecmd->port = PORT_TP;

1773

ecmd->port = PORT_TP;

1776

ecmd->phy_address = 0;

1774

ecmd->phy_address = 0;

1777

ecmd->transceiver = XCVR_INTERNAL;

1775

ecmd->transceiver = XCVR_INTERNAL;

1778

1776

1779

if (adapter->link_speed != SPEED_0) {

1777

if (adapter->link_speed != SPEED_0) {

1780

ecmd->speed = adapter->link_speed;

1778

ecmd->speed = adapter->link_speed;

1781

if (adapter->link_duplex == FULL_DUPLEX)

1779

if (adapter->link_duplex == FULL_DUPLEX)

1782

ecmd->duplex = DUPLEX_FULL;

1780

ecmd->duplex = DUPLEX_FULL;

1783

else

1781

else

1784

ecmd->duplex = DUPLEX_HALF;

1782

ecmd->duplex = DUPLEX_HALF;

1785

} else {

1783

} else {

1786

ecmd->speed = -1;

1784

ecmd->speed = -1;

1787

ecmd->duplex = -1;

1785

ecmd->duplex = -1;

1788

}

1786

}

1789

1787

1790

ecmd->autoneg = AUTONEG_ENABLE;

1788

ecmd->autoneg = AUTONEG_ENABLE;

1791

return 0;

1789

return 0;

1792

}

1790

}

1793

1791

1794

static int atl2_set_settings(struct net_device *netdev,

1792

static int atl2_set_settings(struct net_device *netdev,

1795

struct ethtool_cmd *ecmd)

1793

struct ethtool_cmd *ecmd)

1796

{

1794

{

1797

struct atl2_adapter *adapter = netdev_priv(netdev);

1795

struct atl2_adapter *adapter = netdev_priv(netdev);

1798

struct atl2_hw *hw = &adapter->hw;

1796

struct atl2_hw *hw = &adapter->hw;

1799

1797

1800

while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))

1798

while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))

1801

msleep(1);

1799

msleep(1);

1802

1800

1803

if (ecmd->autoneg == AUTONEG_ENABLE) {

1801

if (ecmd->autoneg == AUTONEG_ENABLE) {

1804

#define MY_ADV_MASK (ADVERTISE_10_HALF | \

1802

#define MY_ADV_MASK (ADVERTISE_10_HALF | \

1805

ADVERTISE_10_FULL | \

1803

ADVERTISE_10_FULL | \

1806

ADVERTISE_100_HALF| \

1804

ADVERTISE_100_HALF| \

1807

ADVERTISE_100_FULL)

1805

ADVERTISE_100_FULL)

1808

1806

1809

if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {

1807

if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {

1810

hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;

1808

hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;

1811

hw->autoneg_advertised = MY_ADV_MASK;

1809

hw->autoneg_advertised = MY_ADV_MASK;

1812

} else if ((ecmd->advertising & MY_ADV_MASK) ==

1810

} else if ((ecmd->advertising & MY_ADV_MASK) ==

1813

ADVERTISE_100_FULL) {

1811

ADVERTISE_100_FULL) {

1814

hw->MediaType = MEDIA_TYPE_100M_FULL;

1812

hw->MediaType = MEDIA_TYPE_100M_FULL;

1815

hw->autoneg_advertised = ADVERTISE_100_FULL;

1813

hw->autoneg_advertised = ADVERTISE_100_FULL;

1816

} else if ((ecmd->advertising & MY_ADV_MASK) ==

1814

} else if ((ecmd->advertising & MY_ADV_MASK) ==

1817

ADVERTISE_100_HALF) {

1815

ADVERTISE_100_HALF) {

1818

hw->MediaType = MEDIA_TYPE_100M_HALF;

1816

hw->MediaType = MEDIA_TYPE_100M_HALF;

1819

hw->autoneg_advertised = ADVERTISE_100_HALF;

1817

hw->autoneg_advertised = ADVERTISE_100_HALF;

1820

} else if ((ecmd->advertising & MY_ADV_MASK) ==

1818

} else if ((ecmd->advertising & MY_ADV_MASK) ==

1821

ADVERTISE_10_FULL) {

1819

ADVERTISE_10_FULL) {

1822

hw->MediaType = MEDIA_TYPE_10M_FULL;

1820

hw->MediaType = MEDIA_TYPE_10M_FULL;

1823

hw->autoneg_advertised = ADVERTISE_10_FULL;

1821

hw->autoneg_advertised = ADVERTISE_10_FULL;

1824

} else if ((ecmd->advertising & MY_ADV_MASK) ==

1822

} else if ((ecmd->advertising & MY_ADV_MASK) ==

1825

ADVERTISE_10_HALF) {

1823

ADVERTISE_10_HALF) {

1826

hw->MediaType = MEDIA_TYPE_10M_HALF;

1824

hw->MediaType = MEDIA_TYPE_10M_HALF;

1827

hw->autoneg_advertised = ADVERTISE_10_HALF;

1825

hw->autoneg_advertised = ADVERTISE_10_HALF;

1828

} else {

1826

} else {

1829

clear_bit(__ATL2_RESETTING, &adapter->flags);

1827

clear_bit(__ATL2_RESETTING, &adapter->flags);

1830

return -EINVAL;

1828

return -EINVAL;

1831

}

1829

}

1832

ecmd->advertising = hw->autoneg_advertised |

1830

ecmd->advertising = hw->autoneg_advertised |

1833

ADVERTISED_TP | ADVERTISED_Autoneg;

1831

ADVERTISED_TP | ADVERTISED_Autoneg;

1834

} else {

1832

} else {

1835

clear_bit(__ATL2_RESETTING, &adapter->flags);

1833

clear_bit(__ATL2_RESETTING, &adapter->flags);

1836

return -EINVAL;

1834

return -EINVAL;

1837

}

1835

}

1838

1836

1839

/* reset the link */

1837

/* reset the link */

1840

if (netif_running(adapter->netdev)) {

1838

if (netif_running(adapter->netdev)) {

1841

atl2_down(adapter);

1839

atl2_down(adapter);

1842

atl2_up(adapter);

1840

atl2_up(adapter);

1843

} else

1841

} else

1844

atl2_reset_hw(&adapter->hw);

1842

atl2_reset_hw(&adapter->hw);

1845

1843

1846

clear_bit(__ATL2_RESETTING, &adapter->flags);

1844

clear_bit(__ATL2_RESETTING, &adapter->flags);

1847

return 0;

1845

return 0;

1848

}

1846

}

1849

1847

1850

static u32 atl2_get_tx_csum(struct net_device *netdev)

1848

static u32 atl2_get_tx_csum(struct net_device *netdev)

1851

{

1849

{

1852

return (netdev->features & NETIF_F_HW_CSUM) != 0;

1850

return (netdev->features & NETIF_F_HW_CSUM) != 0;

1853

}

1851

}

1854

1852

1855

static u32 atl2_get_msglevel(struct net_device *netdev)

1853

static u32 atl2_get_msglevel(struct net_device *netdev)

1856

{

1854

{

1857

return 0;

1855

return 0;

1858

}

1856

}

1859

1857

1860

/*

1858

/*

1861

* It's sane for this to be empty, but we might want to take advantage of this.

1859

* It's sane for this to be empty, but we might want to take advantage of this.

1862

*/

1860

*/

1863

static void atl2_set_msglevel(struct net_device *netdev, u32 data)

1861

static void atl2_set_msglevel(struct net_device *netdev, u32 data)

1864

{

1862

{

1865

}

1863

}

1866

1864

1867

static int atl2_get_regs_len(struct net_device *netdev)

1865

static int atl2_get_regs_len(struct net_device *netdev)

1868

{

1866

{

1869

#define ATL2_REGS_LEN 42

1867

#define ATL2_REGS_LEN 42

1870

return sizeof(u32) * ATL2_REGS_LEN;

1868

return sizeof(u32) * ATL2_REGS_LEN;

1871

}

1869

}

1872

1870

1873

static void atl2_get_regs(struct net_device *netdev,

1871

static void atl2_get_regs(struct net_device *netdev,

1874

struct ethtool_regs *regs, void *p)

1872

struct ethtool_regs *regs, void *p)

1875

{

1873

{

1876

struct atl2_adapter *adapter = netdev_priv(netdev);

1874

struct atl2_adapter *adapter = netdev_priv(netdev);

1877

struct atl2_hw *hw = &adapter->hw;

1875

struct atl2_hw *hw = &adapter->hw;

1878

u32 *regs_buff = p;

1876

u32 *regs_buff = p;

1879

u16 phy_data;

1877

u16 phy_data;

1880

1878

1881

memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);

1879

memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);

1882

1880

1883

regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;

1881

regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;

1884

1882

1885

regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);

1883

regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);

1886

regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);

1884

regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);

1887

regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);

1885

regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);

1888

regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);

1886

regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);

1889

regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);

1887

regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);

1890

regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);

1888

regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);

1891

regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);

1889

regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);

1892

regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);

1890

regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);

1893

regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);

1891

regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);

1894

regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);

1892

regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);

1895

regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);

1893

regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);

1896

regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);

1894

regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);

1897

regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);

1895

regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);

1898

regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);

1896

regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);

1899

regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);

1897

regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);

1900

regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);

1898

regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);

1901

regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);

1899

regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);

1902

regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);

1900

regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);

1903

regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);

1901

regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);

1904

regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);

1902

regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);

1905

regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);

1903

regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);

1906

regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);

1904

regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);

1907

regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);

1905

regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);

1908

regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);

1906

regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);

1909

regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);

1907

regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);

1910

regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);

1908

regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);

1911

regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);

1909

regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);

1912

regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);

1910

regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);

1913

regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);

1911

regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);

1914

regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);

1912

regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);

1915

regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);

1913

regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);

1916

regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);

1914

regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);

1917

regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);

1915

regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);

1918

regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);

1916

regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);

1919

regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);

1917

regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);

1920

regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);

1918

regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);

1921

regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);

1919

regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);

1922

regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);

1920

regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);

1923

regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);

1921

regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);

1924

1922

1925

atl2_read_phy_reg(hw, MII_BMCR, &phy_data);

1923

atl2_read_phy_reg(hw, MII_BMCR, &phy_data);

1926

regs_buff[40] = (u32)phy_data;

1924

regs_buff[40] = (u32)phy_data;

1927

atl2_read_phy_reg(hw, MII_BMSR, &phy_data);

1925

atl2_read_phy_reg(hw, MII_BMSR, &phy_data);

1928

regs_buff[41] = (u32)phy_data;

1926

regs_buff[41] = (u32)phy_data;

1929

}

1927

}

1930

1928

1931

static int atl2_get_eeprom_len(struct net_device *netdev)

1929

static int atl2_get_eeprom_len(struct net_device *netdev)

1932

{

1930

{

1933

struct atl2_adapter *adapter = netdev_priv(netdev);

1931

struct atl2_adapter *adapter = netdev_priv(netdev);

1934

1932

1935

if (!atl2_check_eeprom_exist(&adapter->hw))

1933

if (!atl2_check_eeprom_exist(&adapter->hw))

1936

return 512;

1934

return 512;

1937

else

1935

else

1938

return 0;

1936

return 0;

1939

}

1937

}

1940

1938

1941

static int atl2_get_eeprom(struct net_device *netdev,

1939

static int atl2_get_eeprom(struct net_device *netdev,

1942

struct ethtool_eeprom *eeprom, u8 *bytes)

1940

struct ethtool_eeprom *eeprom, u8 *bytes)

1943

{

1941

{

1944

struct atl2_adapter *adapter = netdev_priv(netdev);

1942

struct atl2_adapter *adapter = netdev_priv(netdev);

1945

struct atl2_hw *hw = &adapter->hw;

1943

struct atl2_hw *hw = &adapter->hw;

1946

u32 *eeprom_buff;

1944

u32 *eeprom_buff;

1947

int first_dword, last_dword;

1945

int first_dword, last_dword;

1948

int ret_val = 0;

1946

int ret_val = 0;

1949

int i;

1947

int i;

1950

1948

1951

if (eeprom->len == 0)

1949

if (eeprom->len == 0)

1952

return -EINVAL;

1950

return -EINVAL;

1953

1951

1954

if (atl2_check_eeprom_exist(hw))

1952

if (atl2_check_eeprom_exist(hw))

1955

return -EINVAL;

1953

return -EINVAL;

1956

1954

1957

eeprom->magic = hw->vendor_id | (hw->device_id << 16);

1955

eeprom->magic = hw->vendor_id | (hw->device_id << 16);

1958

1956

1959

first_dword = eeprom->offset >> 2;

1957

first_dword = eeprom->offset >> 2;

1960

last_dword = (eeprom->offset + eeprom->len - 1) >> 2;

1958

last_dword = (eeprom->offset + eeprom->len - 1) >> 2;

1961

1959

1962

eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),

1960

eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),

1963

GFP_KERNEL);

1961

GFP_KERNEL);

1964

if (!eeprom_buff)

1962

if (!eeprom_buff)

1965

return -ENOMEM;

1963

return -ENOMEM;

1966

1964

1967

for (i = first_dword; i < last_dword; i++) {

1965

for (i = first_dword; i < last_dword; i++) {

1968

if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword])))

1966

if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword])))

1969

return -EIO;

1967

return -EIO;

1970

}

1968

}

1971

1969

1972

memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),

1970

memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),

1973

eeprom->len);

1971

eeprom->len);

1974

kfree(eeprom_buff);

1972

kfree(eeprom_buff);

1975

1973

1976

return ret_val;

1974

return ret_val;

1977

}

1975

}

1978

1976

1979

static int atl2_set_eeprom(struct net_device *netdev,

1977

static int atl2_set_eeprom(struct net_device *netdev,

1980

struct ethtool_eeprom *eeprom, u8 *bytes)

1978

struct ethtool_eeprom *eeprom, u8 *bytes)

1981

{

1979

{

1982

struct atl2_adapter *adapter = netdev_priv(netdev);

1980

struct atl2_adapter *adapter = netdev_priv(netdev);

1983

struct atl2_hw *hw = &adapter->hw;

1981

struct atl2_hw *hw = &adapter->hw;

1984

u32 *eeprom_buff;

1982

u32 *eeprom_buff;

1985

u32 *ptr;

1983

u32 *ptr;

1986

int max_len, first_dword, last_dword, ret_val = 0;

1984

int max_len, first_dword, last_dword, ret_val = 0;

1987

int i;

1985

int i;

1988

1986

1989

if (eeprom->len == 0)

1987

if (eeprom->len == 0)

1990

return -EOPNOTSUPP;

1988

return -EOPNOTSUPP;

1991

1989

1992

if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))

1990

if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))

1993

return -EFAULT;

1991

return -EFAULT;

1994

1992

1995

max_len = 512;

1993

max_len = 512;

1996

1994

1997

first_dword = eeprom->offset >> 2;

1995

first_dword = eeprom->offset >> 2;

1998

last_dword = (eeprom->offset + eeprom->len - 1) >> 2;

1996

last_dword = (eeprom->offset + eeprom->len - 1) >> 2;

1999

eeprom_buff = kmalloc(max_len, GFP_KERNEL);

1997

eeprom_buff = kmalloc(max_len, GFP_KERNEL);

2000

if (!eeprom_buff)

1998

if (!eeprom_buff)

2001

return -ENOMEM;

1999

return -ENOMEM;

2002

2000

2003

ptr = (u32 *)eeprom_buff;

2001

ptr = (u32 *)eeprom_buff;

2004

2002

2005

if (eeprom->offset & 3) {

2003

if (eeprom->offset & 3) {

2006

/* need read/modify/write of first changed EEPROM word */

2004

/* need read/modify/write of first changed EEPROM word */

2007

/* only the second byte of the word is being modified */

2005

/* only the second byte of the word is being modified */

2008

if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))

2006

if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))

2009

return -EIO;

2007

return -EIO;

2010

ptr++;

2008

ptr++;

2011

}

2009

}

2012

if (((eeprom->offset + eeprom->len) & 3)) {

2010

if (((eeprom->offset + eeprom->len) & 3)) {

2013

/*

2011

/*

2014

* need read/modify/write of last changed EEPROM word

2012

* need read/modify/write of last changed EEPROM word

2015

* only the first byte of the word is being modified

2013

* only the first byte of the word is being modified

2016

*/

2014

*/

2017

if (!atl2_read_eeprom(hw, last_dword * 4,

2015

if (!atl2_read_eeprom(hw, last_dword * 4,

2018

&(eeprom_buff[last_dword - first_dword])))

2016

&(eeprom_buff[last_dword - first_dword])))

2019

return -EIO;

2017

return -EIO;

2020

}

2018

}

2021

2019

2022

/* Device's eeprom is always little-endian, word addressable */

2020

/* Device's eeprom is always little-endian, word addressable */

2023

memcpy(ptr, bytes, eeprom->len);

2021

memcpy(ptr, bytes, eeprom->len);

2024

2022

2025

for (i = 0; i < last_dword - first_dword + 1; i++) {

2023

for (i = 0; i < last_dword - first_dword + 1; i++) {

2026

if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))

2024

if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))

2027

return -EIO;

2025

return -EIO;

2028

}

2026

}

2029

2027

2030

kfree(eeprom_buff);

2028

kfree(eeprom_buff);

2031

return ret_val;

2029

return ret_val;

2032

}

2030

}

2033

2031

2034

static void atl2_get_drvinfo(struct net_device *netdev,

2032

static void atl2_get_drvinfo(struct net_device *netdev,

2035

struct ethtool_drvinfo *drvinfo)

2033

struct ethtool_drvinfo *drvinfo)

2036

{

2034

{

2037

struct atl2_adapter *adapter = netdev_priv(netdev);

2035

struct atl2_adapter *adapter = netdev_priv(netdev);

2038

2036

2039

strncpy(drvinfo->driver, atl2_driver_name, 32);

2037

strncpy(drvinfo->driver, atl2_driver_name, 32);

2040

strncpy(drvinfo->version, atl2_driver_version, 32);

2038

strncpy(drvinfo->version, atl2_driver_version, 32);

2041

strncpy(drvinfo->fw_version, "L2", 32);

2039

strncpy(drvinfo->fw_version, "L2", 32);

2042

strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);

2040

strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);

2043

drvinfo->n_stats = 0;

2041

drvinfo->n_stats = 0;

2044

drvinfo->testinfo_len = 0;

2042

drvinfo->testinfo_len = 0;

2045

drvinfo->regdump_len = atl2_get_regs_len(netdev);

2043

drvinfo->regdump_len = atl2_get_regs_len(netdev);

2046

drvinfo->eedump_len = atl2_get_eeprom_len(netdev);

2044

drvinfo->eedump_len = atl2_get_eeprom_len(netdev);

2047

}

2045

}

2048

2046

2049

static void atl2_get_wol(struct net_device *netdev,

2047

static void atl2_get_wol(struct net_device *netdev,

2050

struct ethtool_wolinfo *wol)

2048

struct ethtool_wolinfo *wol)

2051

{

2049

{

2052

struct atl2_adapter *adapter = netdev_priv(netdev);

2050

struct atl2_adapter *adapter = netdev_priv(netdev);

2053

2051

2054

wol->supported = WAKE_MAGIC;

2052

wol->supported = WAKE_MAGIC;

2055

wol->wolopts = 0;

2053

wol->wolopts = 0;

2056

2054

2057

if (adapter->wol & ATLX_WUFC_EX)

2055

if (adapter->wol & ATLX_WUFC_EX)

2058

wol->wolopts |= WAKE_UCAST;

2056

wol->wolopts |= WAKE_UCAST;

2059

if (adapter->wol & ATLX_WUFC_MC)

2057

if (adapter->wol & ATLX_WUFC_MC)

2060

wol->wolopts |= WAKE_MCAST;

2058

wol->wolopts |= WAKE_MCAST;

2061

if (adapter->wol & ATLX_WUFC_BC)

2059

if (adapter->wol & ATLX_WUFC_BC)

2062

wol->wolopts |= WAKE_BCAST;

2060

wol->wolopts |= WAKE_BCAST;

2063

if (adapter->wol & ATLX_WUFC_MAG)

2061

if (adapter->wol & ATLX_WUFC_MAG)

2064

wol->wolopts |= WAKE_MAGIC;

2062

wol->wolopts |= WAKE_MAGIC;

2065

if (adapter->wol & ATLX_WUFC_LNKC)

2063

if (adapter->wol & ATLX_WUFC_LNKC)

2066

wol->wolopts |= WAKE_PHY;

2064

wol->wolopts |= WAKE_PHY;

2067

}

2065

}

2068

2066

2069

static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)

2067

static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)

2070

{

2068

{

2071

struct atl2_adapter *adapter = netdev_priv(netdev);

2069

struct atl2_adapter *adapter = netdev_priv(netdev);

2072

2070

2073

if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))

2071

if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))

2074

return -EOPNOTSUPP;

2072

return -EOPNOTSUPP;

2075

2073

2076

if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST))

2074

if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST))

2077

return -EOPNOTSUPP;

2075

return -EOPNOTSUPP;

2078

2076

2079

/* these settings will always override what we currently have */

2077

/* these settings will always override what we currently have */

2080

adapter->wol = 0;

2078

adapter->wol = 0;

2081

2079

2082

if (wol->wolopts & WAKE_MAGIC)

2080

if (wol->wolopts & WAKE_MAGIC)

2083

adapter->wol |= ATLX_WUFC_MAG;

2081

adapter->wol |= ATLX_WUFC_MAG;

2084

if (wol->wolopts & WAKE_PHY)

2082

if (wol->wolopts & WAKE_PHY)

2085

adapter->wol |= ATLX_WUFC_LNKC;

2083

adapter->wol |= ATLX_WUFC_LNKC;

2086

2084

2087

return 0;

2085

return 0;

2088

}

2086

}

2089

2087

2090

static int atl2_nway_reset(struct net_device *netdev)

2088

static int atl2_nway_reset(struct net_device *netdev)

2091

{

2089

{

2092

struct atl2_adapter *adapter = netdev_priv(netdev);

2090

struct atl2_adapter *adapter = netdev_priv(netdev);

2093

if (netif_running(netdev))

2091

if (netif_running(netdev))

2094

atl2_reinit_locked(adapter);

2092

atl2_reinit_locked(adapter);

2095

return 0;

2093

return 0;

2096

}

2094

}

2097

2095

2098

static struct ethtool_ops atl2_ethtool_ops = {

2096

static struct ethtool_ops atl2_ethtool_ops = {

2099

.get_settings = atl2_get_settings,

2097

.get_settings = atl2_get_settings,

2100

.set_settings = atl2_set_settings,

2098

.set_settings = atl2_set_settings,

2101

.get_drvinfo = atl2_get_drvinfo,

2099

.get_drvinfo = atl2_get_drvinfo,

2102

.get_regs_len = atl2_get_regs_len,

2100

.get_regs_len = atl2_get_regs_len,

2103

.get_regs = atl2_get_regs,

2101

.get_regs = atl2_get_regs,

2104

.get_wol = atl2_get_wol,

2102

.get_wol = atl2_get_wol,

2105

.set_wol = atl2_set_wol,

2103

.set_wol = atl2_set_wol,

2106

.get_msglevel = atl2_get_msglevel,

2104

.get_msglevel = atl2_get_msglevel,

2107

.set_msglevel = atl2_set_msglevel,

2105

.set_msglevel = atl2_set_msglevel,

2108

.nway_reset = atl2_nway_reset,

2106

.nway_reset = atl2_nway_reset,

2109

.get_link = ethtool_op_get_link,

2107

.get_link = ethtool_op_get_link,

2110

.get_eeprom_len = atl2_get_eeprom_len,

2108

.get_eeprom_len = atl2_get_eeprom_len,

2111

.get_eeprom = atl2_get_eeprom,

2109

.get_eeprom = atl2_get_eeprom,

2112

.set_eeprom = atl2_set_eeprom,

2110

.set_eeprom = atl2_set_eeprom,

2113

.get_tx_csum = atl2_get_tx_csum,

2111

.get_tx_csum = atl2_get_tx_csum,

2114

.get_sg = ethtool_op_get_sg,

2112

.get_sg = ethtool_op_get_sg,

2115

.set_sg = ethtool_op_set_sg,

2113

.set_sg = ethtool_op_set_sg,

2116

#ifdef NETIF_F_TSO

2114

#ifdef NETIF_F_TSO

2117

.get_tso = ethtool_op_get_tso,

2115

.get_tso = ethtool_op_get_tso,

2118

#endif

2116

#endif

2119

};

2117

};

2120

2118

2121

static void atl2_set_ethtool_ops(struct net_device *netdev)

2119

static void atl2_set_ethtool_ops(struct net_device *netdev)

2122

{

2120

{

2123

SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);

2121

SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);

2124

}

2122

}

2125

2123

2126

#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \

2124

#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \

2127

(((a) & 0xff00ff00) >> 8))

2125

(((a) & 0xff00ff00) >> 8))

2128

#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))

2126

#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))

2129

#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))

2127

#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))

2130

2128

2131

/*

2129

/*

2132

* Reset the transmit and receive units; mask and clear all interrupts.

2130

* Reset the transmit and receive units; mask and clear all interrupts.

2133

*

2131

*

2134

* hw - Struct containing variables accessed by shared code

2132

* hw - Struct containing variables accessed by shared code

2135

* return : 0 or idle status (if error)

2133

* return : 0 or idle status (if error)

2136

*/

2134

*/

2137

static s32 atl2_reset_hw(struct atl2_hw *hw)

2135

static s32 atl2_reset_hw(struct atl2_hw *hw)

2138

{

2136

{

2139

u32 icr;

2137

u32 icr;

2140

u16 pci_cfg_cmd_word;

2138

u16 pci_cfg_cmd_word;

2141

int i;

2139

int i;

2142

2140

2143

/* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */

2141

/* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */

2144

atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);

2142

atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);

2145

if ((pci_cfg_cmd_word &

2143

if ((pci_cfg_cmd_word &

2146

(CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=

2144

(CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=

2147

(CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {

2145

(CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {

2148

pci_cfg_cmd_word |=

2146

pci_cfg_cmd_word |=

2149

(CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);

2147

(CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);

2150

atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);

2148

atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);

2151

}

2149

}

2152

2150

2153

/* Clear Interrupt mask to stop board from generating

2151

/* Clear Interrupt mask to stop board from generating

2154

* interrupts & Clear any pending interrupt events

2152

* interrupts & Clear any pending interrupt events

2155

*/

2153

*/

2156

/* FIXME */

2154

/* FIXME */

2157

/* ATL2_WRITE_REG(hw, REG_IMR, 0); */

2155

/* ATL2_WRITE_REG(hw, REG_IMR, 0); */

2158

/* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */

2156

/* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */

2159

2157

2160

/* Issue Soft Reset to the MAC. This will reset the chip's

2158

/* Issue Soft Reset to the MAC. This will reset the chip's

2161

* transmit, receive, DMA. It will not effect

2159

* transmit, receive, DMA. It will not effect

2162

* the current PCI configuration. The global reset bit is self-

2160

* the current PCI configuration. The global reset bit is self-

2163

* clearing, and should clear within a microsecond.

2161

* clearing, and should clear within a microsecond.

2164

*/

2162

*/

2165

ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);

2163

ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);

2166

wmb();

2164

wmb();

2167

msleep(1); /* delay about 1ms */

2165

msleep(1); /* delay about 1ms */

2168

2166

2169

/* Wait at least 10ms for All module to be Idle */

2167

/* Wait at least 10ms for All module to be Idle */

2170

for (i = 0; i < 10; i++) {

2168

for (i = 0; i < 10; i++) {

2171

icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);

2169

icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);

2172

if (!icr)

2170

if (!icr)

2173

break;

2171

break;

2174

msleep(1); /* delay 1 ms */

2172

msleep(1); /* delay 1 ms */

2175

cpu_relax();

2173

cpu_relax();

2176

}

2174

}

2177

2175

2178

if (icr)

2176

if (icr)

2179

return icr;

2177

return icr;

2180

2178

2181

return 0;

2179

return 0;

2182

}

2180

}

2183

2181

2184

#define CUSTOM_SPI_CS_SETUP 2

2182

#define CUSTOM_SPI_CS_SETUP 2

2185

#define CUSTOM_SPI_CLK_HI 2

2183

#define CUSTOM_SPI_CLK_HI 2

2186

#define CUSTOM_SPI_CLK_LO 2

2184

#define CUSTOM_SPI_CLK_LO 2

2187

#define CUSTOM_SPI_CS_HOLD 2

2185

#define CUSTOM_SPI_CS_HOLD 2

2188

#define CUSTOM_SPI_CS_HI 3

2186

#define CUSTOM_SPI_CS_HI 3

2189

2187

2190

static struct atl2_spi_flash_dev flash_table[] =

2188

static struct atl2_spi_flash_dev flash_table[] =

2191

{

2189

{

2192

/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */

2190

/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */

2193

{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },

2191

{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },

2194

{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },

2192

{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },

2195

{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },

2193

{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },

2196

};

2194

};

2197

2195

2198

static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)

2196

static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)

2199

{

2197

{

2200

int i;

2198

int i;

2201

u32 value;

2199

u32 value;

2202

2200

2203

ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);

2201

ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);

2204

ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);

2202

ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);

2205

2203

2206

value = SPI_FLASH_CTRL_WAIT_READY |

2204

value = SPI_FLASH_CTRL_WAIT_READY |

2207

(CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<

2205

(CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<

2208

SPI_FLASH_CTRL_CS_SETUP_SHIFT |

2206

SPI_FLASH_CTRL_CS_SETUP_SHIFT |

2209

(CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<

2207

(CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<

2210

SPI_FLASH_CTRL_CLK_HI_SHIFT |

2208

SPI_FLASH_CTRL_CLK_HI_SHIFT |

2211

(CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<

2209

(CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<

2212

SPI_FLASH_CTRL_CLK_LO_SHIFT |

2210

SPI_FLASH_CTRL_CLK_LO_SHIFT |

2213

(CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<

2211

(CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<

2214

SPI_FLASH_CTRL_CS_HOLD_SHIFT |

2212

SPI_FLASH_CTRL_CS_HOLD_SHIFT |

2215

(CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<

2213

(CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<

2216

SPI_FLASH_CTRL_CS_HI_SHIFT |

2214

SPI_FLASH_CTRL_CS_HI_SHIFT |

2217

(0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;

2215

(0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;

2218

2216

2219

ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);

2217

ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);

2220

2218

2221

value |= SPI_FLASH_CTRL_START;

2219

value |= SPI_FLASH_CTRL_START;

2222

2220

2223

ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);

2221

ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);

2224

2222

2225

for (i = 0; i < 10; i++) {

2223

for (i = 0; i < 10; i++) {

2226

msleep(1);

2224

msleep(1);

2227

value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);

2225

value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);

2228

if (!(value & SPI_FLASH_CTRL_START))

2226

if (!(value & SPI_FLASH_CTRL_START))

2229

break;

2227

break;

2230

}

2228

}

2231

2229

2232

if (value & SPI_FLASH_CTRL_START)

2230

if (value & SPI_FLASH_CTRL_START)

2233

return false;

2231

return false;

2234

2232

2235

*buf = ATL2_READ_REG(hw, REG_SPI_DATA);

2233

*buf = ATL2_READ_REG(hw, REG_SPI_DATA);

2236

2234

2237

return true;

2235

return true;

2238

}

2236

}

2239

2237

2240

/*

2238

/*

2241

* get_permanent_address

2239

* get_permanent_address

2242

* return 0 if get valid mac address,

2240

* return 0 if get valid mac address,

2243

*/

2241

*/

2244

static int get_permanent_address(struct atl2_hw *hw)

2242

static int get_permanent_address(struct atl2_hw *hw)

2245

{

2243

{

2246

u32 Addr[2];

2244

u32 Addr[2];

2247

u32 i, Control;

2245

u32 i, Control;

2248

u16 Register;

2246

u16 Register;

2249

u8 EthAddr[NODE_ADDRESS_SIZE];

2247

u8 EthAddr[NODE_ADDRESS_SIZE];

2250

bool KeyValid;

2248

bool KeyValid;

2251

2249

2252

if (is_valid_ether_addr(hw->perm_mac_addr))

2250

if (is_valid_ether_addr(hw->perm_mac_addr))

2253

return 0;

2251

return 0;

2254

2252

2255

Addr[0] = 0;

2253

Addr[0] = 0;

2256

Addr[1] = 0;

2254

Addr[1] = 0;

2257

2255

2258

if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */

2256

if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */

2259

Register = 0;

2257

Register = 0;

2260

KeyValid = false;

2258

KeyValid = false;

2261

2259

2262

/* Read out all EEPROM content */

2260

/* Read out all EEPROM content */

2263

i = 0;

2261

i = 0;

2264

while (1) {

2262

while (1) {

2265

if (atl2_read_eeprom(hw, i + 0x100, &Control)) {

2263

if (atl2_read_eeprom(hw, i + 0x100, &Control)) {

2266

if (KeyValid) {

2264

if (KeyValid) {

2267

if (Register == REG_MAC_STA_ADDR)

2265

if (Register == REG_MAC_STA_ADDR)

2268

Addr[0] = Control;

2266

Addr[0] = Control;

2269

else if (Register ==

2267

else if (Register ==

2270

(REG_MAC_STA_ADDR + 4))

2268

(REG_MAC_STA_ADDR + 4))

2271

Addr[1] = Control;

2269

Addr[1] = Control;

2272

KeyValid = false;

2270

KeyValid = false;

2273

} else if ((Control & 0xff) == 0x5A) {

2271

} else if ((Control & 0xff) == 0x5A) {

2274

KeyValid = true;

2272

KeyValid = true;

2275

Register = (u16) (Control >> 16);

2273

Register = (u16) (Control >> 16);

2276

} else {

2274

} else {

2277

/* assume data end while encount an invalid KEYWORD */

2275

/* assume data end while encount an invalid KEYWORD */

2278

break;

2276

break;

2279

}

2277

}

2280

} else {

2278

} else {

2281

break; /* read error */

2279

break; /* read error */

2282

}

2280

}

2283

i += 4;

2281

i += 4;

2284

}

2282

}

2285

2283

2286

*(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);

2284

*(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);

2287

*(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);

2285

*(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);

2288

2286

2289

if (is_valid_ether_addr(EthAddr)) {

2287

if (is_valid_ether_addr(EthAddr)) {

2290

memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);

2288

memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);

2291

return 0;

2289

return 0;

2292

}

2290

}

2293

return 1;

2291

return 1;

2294

}

2292

}

2295

2293

2296

/* see if SPI flash exists? */

2294

/* see if SPI flash exists? */

2297

Addr[0] = 0;

2295

Addr[0] = 0;

2298

Addr[1] = 0;

2296

Addr[1] = 0;

2299

Register = 0;

2297

Register = 0;

2300

KeyValid = false;

2298

KeyValid = false;

2301

i = 0;

2299

i = 0;

2302

while (1) {

2300

while (1) {

2303

if (atl2_spi_read(hw, i + 0x1f000, &Control)) {

2301

if (atl2_spi_read(hw, i + 0x1f000, &Control)) {

2304

if (KeyValid) {

2302

if (KeyValid) {

2305

if (Register == REG_MAC_STA_ADDR)

2303

if (Register == REG_MAC_STA_ADDR)

2306

Addr[0] = Control;

2304

Addr[0] = Control;

2307

else if (Register == (REG_MAC_STA_ADDR + 4))

2305

else if (Register == (REG_MAC_STA_ADDR + 4))

2308

Addr[1] = Control;

2306

Addr[1] = Control;

2309

KeyValid = false;

2307

KeyValid = false;

2310

} else if ((Control & 0xff) == 0x5A) {

2308

} else if ((Control & 0xff) == 0x5A) {

2311

KeyValid = true;

2309

KeyValid = true;

2312

Register = (u16) (Control >> 16);

2310

Register = (u16) (Control >> 16);

2313

} else {

2311

} else {

2314

break; /* data end */

2312

break; /* data end */

2315

}

2313

}

2316

} else {

2314

} else {

2317

break; /* read error */

2315

break; /* read error */

2318

}

2316

}

2319

i += 4;

2317

i += 4;

2320

}

2318

}

2321

2319

2322

*(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);

2320

*(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);

2323

*(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);

2321

*(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);

2324

if (is_valid_ether_addr(EthAddr)) {

2322

if (is_valid_ether_addr(EthAddr)) {

2325

memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);

2323

memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);

2326

return 0;

2324

return 0;

2327

}

2325

}

2328

/* maybe MAC-address is from BIOS */

2326

/* maybe MAC-address is from BIOS */

2329

Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);

2327

Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);

2330

Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);

2328

Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);

2331

*(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);

2329

*(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);

2332

*(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);

2330

*(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);

2333

2331

2334

if (is_valid_ether_addr(EthAddr)) {

2332

if (is_valid_ether_addr(EthAddr)) {

2335

memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);

2333

memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);

2336

return 0;

2334

return 0;

2337

}

2335

}

2338

2336

2339

return 1;

2337

return 1;

2340

}

2338

}

2341

2339

2342

/*

2340

/*

2343

* Reads the adapter's MAC address from the EEPROM

2341

* Reads the adapter's MAC address from the EEPROM

2344

*

2342

*

2345

* hw - Struct containing variables accessed by shared code

2343

* hw - Struct containing variables accessed by shared code

2346

*/

2344

*/

2347

static s32 atl2_read_mac_addr(struct atl2_hw *hw)

2345

static s32 atl2_read_mac_addr(struct atl2_hw *hw)

2348

{

2346

{

2349

u16 i;

2347

u16 i;

2350

2348

2351

if (get_permanent_address(hw)) {

2349

if (get_permanent_address(hw)) {

2352

/* for test */

2350

/* for test */

2353

/* FIXME: shouldn't we use random_ether_addr() here? */

2351

/* FIXME: shouldn't we use random_ether_addr() here? */

2354

hw->perm_mac_addr[0] = 0x00;

2352

hw->perm_mac_addr[0] = 0x00;

2355

hw->perm_mac_addr[1] = 0x13;

2353

hw->perm_mac_addr[1] = 0x13;

2356

hw->perm_mac_addr[2] = 0x74;

2354

hw->perm_mac_addr[2] = 0x74;

2357

hw->perm_mac_addr[3] = 0x00;

2355

hw->perm_mac_addr[3] = 0x00;

2358

hw->perm_mac_addr[4] = 0x5c;

2356

hw->perm_mac_addr[4] = 0x5c;

2359

hw->perm_mac_addr[5] = 0x38;

2357

hw->perm_mac_addr[5] = 0x38;

2360

}

2358

}

2361

2359

2362

for (i = 0; i < NODE_ADDRESS_SIZE; i++)

2360

for (i = 0; i < NODE_ADDRESS_SIZE; i++)

2363

hw->mac_addr[i] = hw->perm_mac_addr[i];

2361

hw->mac_addr[i] = hw->perm_mac_addr[i];

2364

2362

2365

return 0;

2363

return 0;

2366

}

2364

}

2367

2365

2368

/*

2366

/*

2369

* Hashes an address to determine its location in the multicast table

2367

* Hashes an address to determine its location in the multicast table

2370

*

2368

*

2371

* hw - Struct containing variables accessed by shared code

2369

* hw - Struct containing variables accessed by shared code

2372

* mc_addr - the multicast address to hash

2370

* mc_addr - the multicast address to hash

2373

*

2371

*

2374

* atl2_hash_mc_addr

2372

* atl2_hash_mc_addr

2375

* purpose

2373

* purpose

2376

* set hash value for a multicast address

2374

* set hash value for a multicast address

2377

* hash calcu processing :

2375

* hash calcu processing :

2378

* 1. calcu 32bit CRC for multicast address

2376

* 1. calcu 32bit CRC for multicast address

2379

* 2. reverse crc with MSB to LSB

2377

* 2. reverse crc with MSB to LSB

2380

*/

2378

*/

2381

static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)

2379

static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)

2382

{

2380

{

2383

u32 crc32, value;

2381

u32 crc32, value;

2384

int i;

2382

int i;

2385

2383

2386

value = 0;

2384

value = 0;

2387

crc32 = ether_crc_le(6, mc_addr);

2385

crc32 = ether_crc_le(6, mc_addr);

2388

2386

2389

for (i = 0; i < 32; i++)

2387

for (i = 0; i < 32; i++)

2390

value |= (((crc32 >> i) & 1) << (31 - i));

2388

value |= (((crc32 >> i) & 1) << (31 - i));

2391

2389

2392

return value;

2390

return value;

2393

}

2391

}

2394

2392

2395

/*

2393

/*

2396

* Sets the bit in the multicast table corresponding to the hash value.

2394

* Sets the bit in the multicast table corresponding to the hash value.

2397

*

2395

*

2398

* hw - Struct containing variables accessed by shared code

2396

* hw - Struct containing variables accessed by shared code

2399

* hash_value - Multicast address hash value

2397

* hash_value - Multicast address hash value

2400

*/

2398

*/

2401

static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)

2399

static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)

2402

{

2400

{

2403

u32 hash_bit, hash_reg;

2401

u32 hash_bit, hash_reg;

2404

u32 mta;

2402

u32 mta;

2405

2403

2406

/* The HASH Table is a register array of 2 32-bit registers.

2404

/* The HASH Table is a register array of 2 32-bit registers.

2407

* It is treated like an array of 64 bits. We want to set

2405

* It is treated like an array of 64 bits. We want to set

2408

* bit BitArray[hash_value]. So we figure out what register

2406

* bit BitArray[hash_value]. So we figure out what register

2409

* the bit is in, read it, OR in the new bit, then write

2407

* the bit is in, read it, OR in the new bit, then write

2410

* back the new value. The register is determined by the

2408

* back the new value. The register is determined by the

2411

* upper 7 bits of the hash value and the bit within that

2409

* upper 7 bits of the hash value and the bit within that

2412

* register are determined by the lower 5 bits of the value.

2410

* register are determined by the lower 5 bits of the value.

2413

*/

2411

*/

2414

hash_reg = (hash_value >> 31) & 0x1;

2412

hash_reg = (hash_value >> 31) & 0x1;

2415

hash_bit = (hash_value >> 26) & 0x1F;

2413

hash_bit = (hash_value >> 26) & 0x1F;

2416

2414

2417

mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);

2415

mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);

2418

2416

2419

mta |= (1 << hash_bit);

2417

mta |= (1 << hash_bit);

2420

2418

2421

ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);

2419

ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);

2422

}

2420

}

2423

2421

2424

/*

2422

/*

2425

* atl2_init_pcie - init PCIE module

2423

* atl2_init_pcie - init PCIE module

2426

*/

2424

*/

2427

static void atl2_init_pcie(struct atl2_hw *hw)

2425

static void atl2_init_pcie(struct atl2_hw *hw)

2428

{

2426

{

2429

u32 value;

2427

u32 value;

2430

value = LTSSM_TEST_MODE_DEF;

2428

value = LTSSM_TEST_MODE_DEF;

2431

ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);

2429

ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);

2432

2430

2433

value = PCIE_DLL_TX_CTRL1_DEF;

2431

value = PCIE_DLL_TX_CTRL1_DEF;

2434

ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);

2432

ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);

2435

}

2433

}

2436

2434

2437

static void atl2_init_flash_opcode(struct atl2_hw *hw)

2435

static void atl2_init_flash_opcode(struct atl2_hw *hw)

2438

{

2436

{

2439

if (hw->flash_vendor >= ARRAY_SIZE(flash_table))

2437

if (hw->flash_vendor >= ARRAY_SIZE(flash_table))

2440

hw->flash_vendor = 0; /* ATMEL */

2438

hw->flash_vendor = 0; /* ATMEL */

2441

2439

2442

/* Init OP table */

2440

/* Init OP table */

2443

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,

2441

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,

2444

flash_table[hw->flash_vendor].cmdPROGRAM);

2442

flash_table[hw->flash_vendor].cmdPROGRAM);

2445

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,

2443

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,

2446

flash_table[hw->flash_vendor].cmdSECTOR_ERASE);

2444

flash_table[hw->flash_vendor].cmdSECTOR_ERASE);

2447

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,

2445

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,

2448

flash_table[hw->flash_vendor].cmdCHIP_ERASE);

2446

flash_table[hw->flash_vendor].cmdCHIP_ERASE);

2449

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,

2447

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,

2450

flash_table[hw->flash_vendor].cmdRDID);

2448

flash_table[hw->flash_vendor].cmdRDID);

2451

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,

2449

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,

2452

flash_table[hw->flash_vendor].cmdWREN);

2450

flash_table[hw->flash_vendor].cmdWREN);

2453

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,

2451

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,

2454

flash_table[hw->flash_vendor].cmdRDSR);

2452

flash_table[hw->flash_vendor].cmdRDSR);

2455

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,

2453

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,

2456

flash_table[hw->flash_vendor].cmdWRSR);

2454

flash_table[hw->flash_vendor].cmdWRSR);

2457

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,

2455

ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,

2458

flash_table[hw->flash_vendor].cmdREAD);

2456

flash_table[hw->flash_vendor].cmdREAD);

2459

}

2457

}

2460

2458

2461

/********************************************************************

2459

/********************************************************************

2462

* Performs basic configuration of the adapter.

2460

* Performs basic configuration of the adapter.

2463

*

2461

*

2464

* hw - Struct containing variables accessed by shared code

2462

* hw - Struct containing variables accessed by shared code

2465

* Assumes that the controller has previously been reset and is in a

2463

* Assumes that the controller has previously been reset and is in a

2466

* post-reset uninitialized state. Initializes multicast table,

2464

* post-reset uninitialized state. Initializes multicast table,

2467

* and Calls routines to setup link

2465

* and Calls routines to setup link

2468

* Leaves the transmit and receive units disabled and uninitialized.

2466

* Leaves the transmit and receive units disabled and uninitialized.

2469

********************************************************************/

2467

********************************************************************/

2470

static s32 atl2_init_hw(struct atl2_hw *hw)

2468

static s32 atl2_init_hw(struct atl2_hw *hw)

2471

{

2469

{

2472

u32 ret_val = 0;

2470

u32 ret_val = 0;

2473

2471

2474

atl2_init_pcie(hw);

2472

atl2_init_pcie(hw);

2475

2473

2476

/* Zero out the Multicast HASH table */

2474

/* Zero out the Multicast HASH table */

2477

/* clear the old settings from the multicast hash table */

2475

/* clear the old settings from the multicast hash table */

2478

ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);

2476

ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);

2479

ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);

2477

ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);

2480

2478

2481

atl2_init_flash_opcode(hw);

2479

atl2_init_flash_opcode(hw);

2482

2480

2483

ret_val = atl2_phy_init(hw);

2481

ret_val = atl2_phy_init(hw);

2484

2482

2485

return ret_val;

2483

return ret_val;

2486

}

2484

}

2487

2485

2488

/*

2486

/*

2489

* Detects the current speed and duplex settings of the hardware.

2487

* Detects the current speed and duplex settings of the hardware.

2490

*

2488

*

2491

* hw - Struct containing variables accessed by shared code

2489

* hw - Struct containing variables accessed by shared code

2492

* speed - Speed of the connection

2490

* speed - Speed of the connection

2493

* duplex - Duplex setting of the connection

2491

* duplex - Duplex setting of the connection

2494

*/

2492

*/

2495

static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,

2493

static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,

2496

u16 *duplex)

2494

u16 *duplex)

2497

{

2495

{

2498

s32 ret_val;

2496

s32 ret_val;

2499

u16 phy_data;

2497

u16 phy_data;

2500

2498

2501

/* Read PHY Specific Status Register (17) */

2499

/* Read PHY Specific Status Register (17) */

2502

ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);

2500

ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);

2503

if (ret_val)

2501

if (ret_val)

2504

return ret_val;

2502

return ret_val;

2505

2503

2506

if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))

2504

if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))

2507

return ATLX_ERR_PHY_RES;

2505

return ATLX_ERR_PHY_RES;

2508

2506

2509

switch (phy_data & MII_ATLX_PSSR_SPEED) {

2507

switch (phy_data & MII_ATLX_PSSR_SPEED) {

2510

case MII_ATLX_PSSR_100MBS:

2508

case MII_ATLX_PSSR_100MBS:

2511

*speed = SPEED_100;

2509

*speed = SPEED_100;

2512

break;

2510

break;

2513

case MII_ATLX_PSSR_10MBS:

2511

case MII_ATLX_PSSR_10MBS:

2514

*speed = SPEED_10;

2512

*speed = SPEED_10;

2515

break;

2513

break;

2516

default:

2514

default:

2517

return ATLX_ERR_PHY_SPEED;

2515

return ATLX_ERR_PHY_SPEED;

2518

break;

2516

break;

2519

}

2517

}

2520

2518

2521

if (phy_data & MII_ATLX_PSSR_DPLX)

2519

if (phy_data & MII_ATLX_PSSR_DPLX)

2522

*duplex = FULL_DUPLEX;

2520

*duplex = FULL_DUPLEX;

2523

else

2521

else

2524

*duplex = HALF_DUPLEX;

2522

*duplex = HALF_DUPLEX;

2525

2523

2526

return 0;

2524

return 0;

2527

}

2525

}

2528

2526

2529

/*

2527

/*

2530

* Reads the value from a PHY register

2528

* Reads the value from a PHY register

2531

* hw - Struct containing variables accessed by shared code

2529

* hw - Struct containing variables accessed by shared code

2532

* reg_addr - address of the PHY register to read

2530

* reg_addr - address of the PHY register to read

2533

*/

2531

*/

2534

static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)

2532

static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)

2535

{

2533

{

2536

u32 val;

2534

u32 val;

2537

int i;

2535

int i;

2538

2536

2539

val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |

2537

val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |

2540

MDIO_START |

2538

MDIO_START |

2541

MDIO_SUP_PREAMBLE |

2539

MDIO_SUP_PREAMBLE |

2542

MDIO_RW |

2540

MDIO_RW |

2543

MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;

2541

MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;

2544

ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);

2542

ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);

2545

2543

2546

wmb();

2544

wmb();

2547

2545

2548

for (i = 0; i < MDIO_WAIT_TIMES; i++) {

2546

for (i = 0; i < MDIO_WAIT_TIMES; i++) {

2549

udelay(2);

2547

udelay(2);

2550

val = ATL2_READ_REG(hw, REG_MDIO_CTRL);

2548

val = ATL2_READ_REG(hw, REG_MDIO_CTRL);

2551

if (!(val & (MDIO_START | MDIO_BUSY)))

2549

if (!(val & (MDIO_START | MDIO_BUSY)))

2552

break;

2550

break;

2553

wmb();

2551

wmb();

2554

}

2552

}

2555

if (!(val & (MDIO_START | MDIO_BUSY))) {

2553

if (!(val & (MDIO_START | MDIO_BUSY))) {

2556

*phy_data = (u16)val;

2554

*phy_data = (u16)val;

2557

return 0;

2555

return 0;

2558

}

2556

}

2559

2557

2560

return ATLX_ERR_PHY;

2558

return ATLX_ERR_PHY;

2561

}

2559

}

2562

2560

2563

/*

2561

/*

2564

* Writes a value to a PHY register

2562

* Writes a value to a PHY register

2565

* hw - Struct containing variables accessed by shared code

2563

* hw - Struct containing variables accessed by shared code

2566

* reg_addr - address of the PHY register to write

2564

* reg_addr - address of the PHY register to write

2567

* data - data to write to the PHY

2565

* data - data to write to the PHY

2568

*/

2566

*/

2569

static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)

2567

static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)

2570

{

2568

{

2571

int i;

2569

int i;

2572

u32 val;

2570

u32 val;

2573

2571

2574

val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |

2572

val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |

2575

(reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |

2573

(reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |

2576

MDIO_SUP_PREAMBLE |

2574

MDIO_SUP_PREAMBLE |

2577

MDIO_START |

2575

MDIO_START |

2578

MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;

2576

MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;

2579

ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);

2577

ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);

2580

2578

2581

wmb();

2579

wmb();

2582

2580

2583

for (i = 0; i < MDIO_WAIT_TIMES; i++) {

2581

for (i = 0; i < MDIO_WAIT_TIMES; i++) {

2584

udelay(2);

2582

udelay(2);

2585

val = ATL2_READ_REG(hw, REG_MDIO_CTRL);

2583

val = ATL2_READ_REG(hw, REG_MDIO_CTRL);

2586

if (!(val & (MDIO_START | MDIO_BUSY)))

2584

if (!(val & (MDIO_START | MDIO_BUSY)))

2587

break;

2585

break;

2588

2586

2589

wmb();

2587

wmb();

2590

}

2588

}

2591

2589

2592

if (!(val & (MDIO_START | MDIO_BUSY)))

2590

if (!(val & (MDIO_START | MDIO_BUSY)))

2593

return 0;

2591

return 0;

2594

2592

2595

return ATLX_ERR_PHY;

2593

return ATLX_ERR_PHY;

2596

}

2594

}

2597

2595

2598

/*

2596

/*

2599

* Configures PHY autoneg and flow control advertisement settings

2597

* Configures PHY autoneg and flow control advertisement settings

2600

*

2598

*

2601

* hw - Struct containing variables accessed by shared code

2599

* hw - Struct containing variables accessed by shared code

2602

*/

2600

*/

2603

static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)

2601

static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)

2604

{

2602

{

2605

s32 ret_val;

2603

s32 ret_val;

2606

s16 mii_autoneg_adv_reg;

2604

s16 mii_autoneg_adv_reg;

2607

2605

2608

/* Read the MII Auto-Neg Advertisement Register (Address 4). */

2606

/* Read the MII Auto-Neg Advertisement Register (Address 4). */

2609

mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;

2607

mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;

2610

2608

2611

/* Need to parse autoneg_advertised and set up

2609

/* Need to parse autoneg_advertised and set up

2612

* the appropriate PHY registers. First we will parse for

2610

* the appropriate PHY registers. First we will parse for

2613

* autoneg_advertised software override. Since we can advertise

2611

* autoneg_advertised software override. Since we can advertise

2614

* a plethora of combinations, we need to check each bit

2612

* a plethora of combinations, we need to check each bit

2615

* individually.

2613

* individually.

2616

*/

2614

*/

2617

2615

2618

/* First we clear all the 10/100 mb speed bits in the Auto-Neg

2616

/* First we clear all the 10/100 mb speed bits in the Auto-Neg

2619

* Advertisement Register (Address 4) and the 1000 mb speed bits in

2617

* Advertisement Register (Address 4) and the 1000 mb speed bits in

2620

* the 1000Base-T Control Register (Address 9). */

2618

* the 1000Base-T Control Register (Address 9). */

2621

mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;

2619

mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;

2622

2620

2623

/* Need to parse MediaType and setup the

2621

/* Need to parse MediaType and setup the

2624

* appropriate PHY registers. */

2622

* appropriate PHY registers. */

2625

switch (hw->MediaType) {

2623

switch (hw->MediaType) {

2626

case MEDIA_TYPE_AUTO_SENSOR:

2624

case MEDIA_TYPE_AUTO_SENSOR:

2627

mii_autoneg_adv_reg |=

2625

mii_autoneg_adv_reg |=

2628

(MII_AR_10T_HD_CAPS |

2626

(MII_AR_10T_HD_CAPS |

2629

MII_AR_10T_FD_CAPS |

2627

MII_AR_10T_FD_CAPS |

2630

MII_AR_100TX_HD_CAPS|

2628

MII_AR_100TX_HD_CAPS|

2631

MII_AR_100TX_FD_CAPS);

2629

MII_AR_100TX_FD_CAPS);

2632

hw->autoneg_advertised =

2630

hw->autoneg_advertised =

2633

ADVERTISE_10_HALF |

2631

ADVERTISE_10_HALF |

2634

ADVERTISE_10_FULL |

2632

ADVERTISE_10_FULL |

2635

ADVERTISE_100_HALF|

2633

ADVERTISE_100_HALF|

2636

ADVERTISE_100_FULL;

2634

ADVERTISE_100_FULL;

2637

break;

2635

break;

2638

case MEDIA_TYPE_100M_FULL:

2636

case MEDIA_TYPE_100M_FULL:

2639

mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;

2637

mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;

2640

hw->autoneg_advertised = ADVERTISE_100_FULL;

2638

hw->autoneg_advertised = ADVERTISE_100_FULL;

2641

break;

2639

break;

2642

case MEDIA_TYPE_100M_HALF:

2640

case MEDIA_TYPE_100M_HALF:

2643

mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;

2641

mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;

2644

hw->autoneg_advertised = ADVERTISE_100_HALF;

2642

hw->autoneg_advertised = ADVERTISE_100_HALF;

2645

break;

2643

break;

2646

case MEDIA_TYPE_10M_FULL:

2644

case MEDIA_TYPE_10M_FULL:

2647

mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;

2645

mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;

2648

hw->autoneg_advertised = ADVERTISE_10_FULL;

2646

hw->autoneg_advertised = ADVERTISE_10_FULL;

2649

break;

2647

break;

2650

default:

2648

default:

2651

mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;

2649

mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;

2652

hw->autoneg_advertised = ADVERTISE_10_HALF;

2650

hw->autoneg_advertised = ADVERTISE_10_HALF;

2653

break;

2651

break;

2654

}

2652

}

2655

2653

2656

/* flow control fixed to enable all */

2654

/* flow control fixed to enable all */

2657

mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);

2655

mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);

2658

2656

2659

hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;

2657

hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;

2660

2658

2661

ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);

2659

ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);

2662

2660

2663

if (ret_val)

2661

if (ret_val)

2664

return ret_val;

2662

return ret_val;

2665

2663

2666

return 0;

2664

return 0;

2667

}

2665

}

2668

2666

2669

/*

2667

/*

2670

* Resets the PHY and make all config validate

2668

* Resets the PHY and make all config validate

2671

*

2669

*

2672

* hw - Struct containing variables accessed by shared code

2670

* hw - Struct containing variables accessed by shared code

2673

*

2671

*

2674

* Sets bit 15 and 12 of the MII Control regiser (for F001 bug)

2672

* Sets bit 15 and 12 of the MII Control regiser (for F001 bug)

2675

*/

2673

*/

2676

static s32 atl2_phy_commit(struct atl2_hw *hw)

2674

static s32 atl2_phy_commit(struct atl2_hw *hw)

2677

{

2675

{

2678

s32 ret_val;

2676

s32 ret_val;

2679

u16 phy_data;

2677

u16 phy_data;

2680

2678

2681

phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;

2679

phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;

2682

ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);

2680

ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);

2683

if (ret_val) {

2681

if (ret_val) {

2684

u32 val;

2682

u32 val;

2685

int i;

2683

int i;

2686

/* pcie serdes link may be down ! */

2684

/* pcie serdes link may be down ! */

2687

for (i = 0; i < 25; i++) {

2685

for (i = 0; i < 25; i++) {

2688

msleep(1);

2686

msleep(1);

2689

val = ATL2_READ_REG(hw, REG_MDIO_CTRL);

2687

val = ATL2_READ_REG(hw, REG_MDIO_CTRL);

2690

if (!(val & (MDIO_START | MDIO_BUSY)))

2688

if (!(val & (MDIO_START | MDIO_BUSY)))

2691

break;

2689

break;

2692

}

2690

}

2693

2691

2694

if (0 != (val & (MDIO_START | MDIO_BUSY))) {

2692

if (0 != (val & (MDIO_START | MDIO_BUSY))) {

2695

printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");

2693

printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");

2696

return ret_val;

2694

return ret_val;

2697

}

2695

}

2698

}

2696

}

2699

return 0;

2697

return 0;

2700

}

2698

}

2701

2699

2702

static s32 atl2_phy_init(struct atl2_hw *hw)

2700

static s32 atl2_phy_init(struct atl2_hw *hw)

2703

{

2701

{

2704

s32 ret_val;

2702

s32 ret_val;

2705

u16 phy_val;

2703

u16 phy_val;

2706

2704

2707

if (hw->phy_configured)

2705

if (hw->phy_configured)

2708

return 0;

2706

return 0;

2709

2707

2710

/* Enable PHY */

2708

/* Enable PHY */

2711

ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);

2709

ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);

2712

ATL2_WRITE_FLUSH(hw);

2710

ATL2_WRITE_FLUSH(hw);

2713

msleep(1);

2711

msleep(1);

2714

2712

2715

/* check if the PHY is in powersaving mode */

2713

/* check if the PHY is in powersaving mode */

2716

atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);

2714

atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);

2717

atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);

2715

atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);

2718

2716

2719

/* 024E / 124E 0r 0274 / 1274 ? */

2717

/* 024E / 124E 0r 0274 / 1274 ? */

2720

if (phy_val & 0x1000) {

2718

if (phy_val & 0x1000) {

2721

phy_val &= ~0x1000;

2719

phy_val &= ~0x1000;

2722

atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);

2720

atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);

2723

}

2721

}

2724

2722

2725

msleep(1);

2723

msleep(1);

2726

2724

2727

/*Enable PHY LinkChange Interrupt */

2725

/*Enable PHY LinkChange Interrupt */

2728

ret_val = atl2_write_phy_reg(hw, 18, 0xC00);

2726

ret_val = atl2_write_phy_reg(hw, 18, 0xC00);

2729

if (ret_val)

2727

if (ret_val)

2730

return ret_val;

2728

return ret_val;

2731

2729

2732

/* setup AutoNeg parameters */

2730

/* setup AutoNeg parameters */

2733

ret_val = atl2_phy_setup_autoneg_adv(hw);

2731

ret_val = atl2_phy_setup_autoneg_adv(hw);

2734

if (ret_val)

2732

if (ret_val)

2735

return ret_val;

2733

return ret_val;

2736

2734

2737

/* SW.Reset & En-Auto-Neg to restart Auto-Neg */

2735

/* SW.Reset & En-Auto-Neg to restart Auto-Neg */

2738

ret_val = atl2_phy_commit(hw);

2736

ret_val = atl2_phy_commit(hw);

2739

if (ret_val)

2737

if (ret_val)

2740

return ret_val;

2738

return ret_val;

2741

2739

2742

hw->phy_configured = true;

2740

hw->phy_configured = true;

2743

2741

2744

return ret_val;

2742

return ret_val;

2745

}

2743

}

2746

2744

2747

static void atl2_set_mac_addr(struct atl2_hw *hw)

2745

static void atl2_set_mac_addr(struct atl2_hw *hw)

2748

{

2746

{

2749

u32 value;

2747

u32 value;

2750

/* 00-0B-6A-F6-00-DC

2748

/* 00-0B-6A-F6-00-DC

2751

* 0: 6AF600DC 1: 000B

2749

* 0: 6AF600DC 1: 000B

2752

* low dword */

2750

* low dword */

2753

value = (((u32)hw->mac_addr[2]) << 24) |

2751

value = (((u32)hw->mac_addr[2]) << 24) |

2754

(((u32)hw->mac_addr[3]) << 16) |

2752

(((u32)hw->mac_addr[3]) << 16) |

2755

(((u32)hw->mac_addr[4]) << 8) |

2753

(((u32)hw->mac_addr[4]) << 8) |

2756

(((u32)hw->mac_addr[5]));

2754

(((u32)hw->mac_addr[5]));

2757

ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);

2755

ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);

2758

/* hight dword */

2756

/* hight dword */

2759

value = (((u32)hw->mac_addr[0]) << 8) |

2757

value = (((u32)hw->mac_addr[0]) << 8) |

2760

(((u32)hw->mac_addr[1]));

2758

(((u32)hw->mac_addr[1]));

2761

ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);

2759

ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);

2762

}

2760

}

2763

2761

2764

/*

2762

/*

2765

* check_eeprom_exist

2763

* check_eeprom_exist

2766

* return 0 if eeprom exist

2764

* return 0 if eeprom exist

2767

*/

2765

*/

2768

static int atl2_check_eeprom_exist(struct atl2_hw *hw)

2766

static int atl2_check_eeprom_exist(struct atl2_hw *hw)

2769

{

2767

{

2770

u32 value;

2768

u32 value;

2771

2769

2772

value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);

2770

value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);

2773

if (value & SPI_FLASH_CTRL_EN_VPD) {

2771

if (value & SPI_FLASH_CTRL_EN_VPD) {

2774

value &= ~SPI_FLASH_CTRL_EN_VPD;

2772

value &= ~SPI_FLASH_CTRL_EN_VPD;

2775

ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);

2773

ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);

2776

}

2774

}

2777

value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);

2775

value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);

2778

return ((value & 0xFF00) == 0x6C00) ? 0 : 1;

2776

return ((value & 0xFF00) == 0x6C00) ? 0 : 1;

2779

}

2777

}

2780

2778

2781

/* FIXME: This doesn't look right. -- CHS */

2779

/* FIXME: This doesn't look right. -- CHS */

2782

static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)

2780

static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)

2783

{

2781

{

2784

return true;

2782

return true;

2785

}

2783

}

2786

2784

2787

static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)

2785

static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)

2788

{

2786

{

2789

int i;

2787

int i;

2790

u32 Control;

2788

u32 Control;

2791

2789

2792

if (Offset & 0x3)

2790

if (Offset & 0x3)

2793

return false; /* address do not align */

2791

return false; /* address do not align */

2794

2792

2795

ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);

2793

ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);

2796

Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;

2794

Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;

2797

ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);

2795

ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);

2798

2796

2799

for (i = 0; i < 10; i++) {

2797

for (i = 0; i < 10; i++) {

2800

msleep(2);

2798

msleep(2);

2801

Control = ATL2_READ_REG(hw, REG_VPD_CAP);

2799

Control = ATL2_READ_REG(hw, REG_VPD_CAP);

2802

if (Control & VPD_CAP_VPD_FLAG)

2800

if (Control & VPD_CAP_VPD_FLAG)

2803

break;

2801

break;

2804

}

2802

}

2805

2803

2806

if (Control & VPD_CAP_VPD_FLAG) {

2804

if (Control & VPD_CAP_VPD_FLAG) {

2807

*pValue = ATL2_READ_REG(hw, REG_VPD_DATA);

2805

*pValue = ATL2_READ_REG(hw, REG_VPD_DATA);

2808

return true;

2806

return true;

2809

}

2807

}

2810

return false; /* timeout */

2808

return false; /* timeout */

2811

}

2809

}

2812

2810

2813

static void atl2_force_ps(struct atl2_hw *hw)

2811

static void atl2_force_ps(struct atl2_hw *hw)

2814

{

2812

{

2815

u16 phy_val;

2813

u16 phy_val;

2816

2814

2817

atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);

2815

atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);

2818

atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);

2816

atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);

2819

atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);

2817

atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);

2820

2818

2821

atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);

2819

atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);

2822

atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);

2820

atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);

2823

atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);

2821

atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);

2824

atl2_write_phy_reg(hw, MII_DBG_DATA, 0);

2822

atl2_write_phy_reg(hw, MII_DBG_DATA, 0);

2825

}

2823

}

2826

2824

2827

/* This is the only thing that needs to be changed to adjust the

2825

/* This is the only thing that needs to be changed to adjust the

2828

* maximum number of ports that the driver can manage.

2826

* maximum number of ports that the driver can manage.

2829

*/

2827

*/

2830

#define ATL2_MAX_NIC 4

2828

#define ATL2_MAX_NIC 4

2831

2829

2832

#define OPTION_UNSET -1

2830

#define OPTION_UNSET -1

2833

#define OPTION_DISABLED 0

2831

#define OPTION_DISABLED 0

2834

#define OPTION_ENABLED 1

2832

#define OPTION_ENABLED 1

2835

2833

2836

/* All parameters are treated the same, as an integer array of values.

2834

/* All parameters are treated the same, as an integer array of values.

2837

* This macro just reduces the need to repeat the same declaration code

2835

* This macro just reduces the need to repeat the same declaration code

2838

* over and over (plus this helps to avoid typo bugs).

2836

* over and over (plus this helps to avoid typo bugs).

2839

*/

2837

*/

2840

#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}

2838

#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}

2841

#ifndef module_param_array

2839

#ifndef module_param_array

2842

/* Module Parameters are always initialized to -1, so that the driver

2840

/* Module Parameters are always initialized to -1, so that the driver

2843

* can tell the difference between no user specified value or the

2841

* can tell the difference between no user specified value or the

2844

* user asking for the default value.

2842

* user asking for the default value.

2845

* The true default values are loaded in when atl2_check_options is called.

2843

* The true default values are loaded in when atl2_check_options is called.

2846

*

2844

*

2847

* This is a GCC extension to ANSI C.

2845

* This is a GCC extension to ANSI C.

2848

* See the item "Labeled Elements in Initializers" in the section

2846

* See the item "Labeled Elements in Initializers" in the section

2849

* "Extensions to the C Language Family" of the GCC documentation.

2847

* "Extensions to the C Language Family" of the GCC documentation.

2850

*/

2848

*/

2851

2849

2852

#define ATL2_PARAM(X, desc) \

2850

#define ATL2_PARAM(X, desc) \

2853

static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \

2851

static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \

2854

MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \

2852

MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \

2855

MODULE_PARM_DESC(X, desc);

2853

MODULE_PARM_DESC(X, desc);

2856

#else

2854

#else

2857

#define ATL2_PARAM(X, desc) \

2855

#define ATL2_PARAM(X, desc) \

2858

static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \

2856

static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \

2859

static int num_##X = 0; \

2857

static int num_##X = 0; \

2860

module_param_array_named(X, X, int, &num_##X, 0); \

2858

module_param_array_named(X, X, int, &num_##X, 0); \

2861

MODULE_PARM_DESC(X, desc);

2859

MODULE_PARM_DESC(X, desc);

2862

#endif

2860

#endif

2863

2861

2864

/*

2862

/*

2865

* Transmit Memory Size

2863

* Transmit Memory Size

2866

* Valid Range: 64-2048

2864

* Valid Range: 64-2048

2867

* Default Value: 128

2865

* Default Value: 128

2868

*/

2866

*/

2869

#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */

2867

#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */

2870

#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */

2868

#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */

2871

#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */

2869

#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */

2872

ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");

2870

ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");

2873

2871

2874

/*

2872

/*

2875

* Receive Memory Block Count

2873

* Receive Memory Block Count

2876

* Valid Range: 16-512

2874

* Valid Range: 16-512

2877

* Default Value: 128

2875

* Default Value: 128

2878

*/

2876

*/

2879

#define ATL2_MIN_RXD_COUNT 16

2877

#define ATL2_MIN_RXD_COUNT 16

2880

#define ATL2_MAX_RXD_COUNT 512

2878

#define ATL2_MAX_RXD_COUNT 512

2881

#define ATL2_DEFAULT_RXD_COUNT 64

2879

#define ATL2_DEFAULT_RXD_COUNT 64

2882

ATL2_PARAM(RxMemBlock, "Number of receive memory block");

2880

ATL2_PARAM(RxMemBlock, "Number of receive memory block");

2883

2881

2884

/*

2882

/*

2885

* User Specified MediaType Override

2883

* User Specified MediaType Override

2886

*

2884

*

2887

* Valid Range: 0-5

2885

* Valid Range: 0-5

2888

* - 0 - auto-negotiate at all supported speeds

2886

* - 0 - auto-negotiate at all supported speeds

2889

* - 1 - only link at 1000Mbps Full Duplex

2887

* - 1 - only link at 1000Mbps Full Duplex

2890

* - 2 - only link at 100Mbps Full Duplex

2888

* - 2 - only link at 100Mbps Full Duplex

2891

* - 3 - only link at 100Mbps Half Duplex

2889

* - 3 - only link at 100Mbps Half Duplex

2892

* - 4 - only link at 10Mbps Full Duplex

2890

* - 4 - only link at 10Mbps Full Duplex

2893

* - 5 - only link at 10Mbps Half Duplex

2891

* - 5 - only link at 10Mbps Half Duplex

2894

* Default Value: 0

2892

* Default Value: 0

2895

*/

2893

*/

2896

ATL2_PARAM(MediaType, "MediaType Select");

2894

ATL2_PARAM(MediaType, "MediaType Select");

2897

2895

2898

/*

2896

/*

2899

* Interrupt Moderate Timer in units of 2048 ns (~2 us)

2897

* Interrupt Moderate Timer in units of 2048 ns (~2 us)

2900

* Valid Range: 10-65535

2898

* Valid Range: 10-65535

2901

* Default Value: 45000(90ms)

2899

* Default Value: 45000(90ms)

2902

*/

2900

*/

2903

#define INT_MOD_DEFAULT_CNT 100 /* 200us */

2901

#define INT_MOD_DEFAULT_CNT 100 /* 200us */

2904

#define INT_MOD_MAX_CNT 65000

2902

#define INT_MOD_MAX_CNT 65000

2905

#define INT_MOD_MIN_CNT 50

2903

#define INT_MOD_MIN_CNT 50

2906

ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");

2904

ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");

2907

2905

2908

/*

2906

/*

2909

* FlashVendor

2907

* FlashVendor

2910

* Valid Range: 0-2

2908

* Valid Range: 0-2

2911

* 0 - Atmel

2909

* 0 - Atmel

2912

* 1 - SST

2910

* 1 - SST

2913

* 2 - ST

2911

* 2 - ST

2914

*/

2912

*/

2915

ATL2_PARAM(FlashVendor, "SPI Flash Vendor");

2913

ATL2_PARAM(FlashVendor, "SPI Flash Vendor");

2916

2914

2917

#define AUTONEG_ADV_DEFAULT 0x2F

2915

#define AUTONEG_ADV_DEFAULT 0x2F

2918

#define AUTONEG_ADV_MASK 0x2F

2916

#define AUTONEG_ADV_MASK 0x2F

2919

#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL

2917

#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL

2920

2918

2921

#define FLASH_VENDOR_DEFAULT 0

2919

#define FLASH_VENDOR_DEFAULT 0

2922

#define FLASH_VENDOR_MIN 0

2920

#define FLASH_VENDOR_MIN 0

2923

#define FLASH_VENDOR_MAX 2

2921

#define FLASH_VENDOR_MAX 2

2924

2922

2925

struct atl2_option {

2923

struct atl2_option {

2926

enum { enable_option, range_option, list_option } type;

2924

enum { enable_option, range_option, list_option } type;

2927

char *name;

2925

char *name;

2928

char *err;

2926

char *err;

2929

int def;

2927

int def;

2930

union {

2928

union {

2931

struct { /* range_option info */

2929

struct { /* range_option info */

2932

int min;

2930

int min;

2933

int max;

2931

int max;

2934

} r;

2932

} r;

2935

struct { /* list_option info */

2933

struct { /* list_option info */

2936

int nr;

2934

int nr;

2937

struct atl2_opt_list { int i; char *str; } *p;

2935

struct atl2_opt_list { int i; char *str; } *p;

2938

} l;

2936

} l;

2939

} arg;

2937

} arg;

2940

};

2938

};

2941

2939

2942

static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)

2940

static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)

2943

{

2941

{

2944

int i;

2942

int i;

2945

struct atl2_opt_list *ent;

2943

struct atl2_opt_list *ent;

2946

2944

2947

if (*value == OPTION_UNSET) {

2945

if (*value == OPTION_UNSET) {

2948

*value = opt->def;

2946

*value = opt->def;

2949

return 0;

2947

return 0;

2950

}

2948

}

2951

2949

2952

switch (opt->type) {

2950

switch (opt->type) {

2953

case enable_option:

2951

case enable_option:

2954

switch (*value) {

2952

switch (*value) {

2955

case OPTION_ENABLED:

2953

case OPTION_ENABLED:

2956

printk(KERN_INFO "%s Enabled\n", opt->name);

2954

printk(KERN_INFO "%s Enabled\n", opt->name);

2957

return 0;

2955

return 0;

2958

break;

2956

break;

2959

case OPTION_DISABLED:

2957

case OPTION_DISABLED:

2960

printk(KERN_INFO "%s Disabled\n", opt->name);

2958

printk(KERN_INFO "%s Disabled\n", opt->name);

2961

return 0;

2959

return 0;

2962

break;

2960

break;

2963

}

2961

}

2964

break;

2962

break;

2965

case range_option:

2963

case range_option:

2966

if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {

2964

if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {

2967

printk(KERN_INFO "%s set to %i\n", opt->name, *value);

2965

printk(KERN_INFO "%s set to %i\n", opt->name, *value);

2968

return 0;

2966

return 0;

2969

}

2967

}

2970

break;

2968

break;

2971

case list_option:

2969

case list_option:

2972

for (i = 0; i < opt->arg.l.nr; i++) {

2970

for (i = 0; i < opt->arg.l.nr; i++) {

2973

ent = &opt->arg.l.p[i];

2971

ent = &opt->arg.l.p[i];

2974

if (*value == ent->i) {

2972

if (*value == ent->i) {

2975

if (ent->str[0] != '\0')

2973

if (ent->str[0] != '\0')

2976

printk(KERN_INFO "%s\n", ent->str);

2974

printk(KERN_INFO "%s\n", ent->str);

2977

return 0;

2975

return 0;

2978

}

2976

}

2979

}

2977

}

2980

break;

2978

break;

2981

default:

2979

default:

2982

BUG();

2980

BUG();

2983

}

2981

}

2984

2982

2985

printk(KERN_INFO "Invalid %s specified (%i) %s\n",

2983

printk(KERN_INFO "Invalid %s specified (%i) %s\n",

2986

opt->name, *value, opt->err);

2984

opt->name, *value, opt->err);

2987

*value = opt->def;

2985

*value = opt->def;

2988

return -1;

2986

return -1;

2989

}

2987

}

2990

2988

2991

/*

2989

/*

2992

* atl2_check_options - Range Checking for Command Line Parameters

2990

* atl2_check_options - Range Checking for Command Line Parameters

2993

* @adapter: board private structure

2991

* @adapter: board private structure

2994

*

2992

*

2995

* This routine checks all command line parameters for valid user

2993

* This routine checks all command line parameters for valid user

2996

* input. If an invalid value is given, or if no user specified

2994

* input. If an invalid value is given, or if no user specified

2997

* value exists, a default value is used. The final value is stored

2995

* value exists, a default value is used. The final value is stored

2998

* in a variable in the adapter structure.

2996

* in a variable in the adapter structure.

2999

*/

2997

*/

3000

static void __devinit atl2_check_options(struct atl2_adapter *adapter)

2998

static void __devinit atl2_check_options(struct atl2_adapter *adapter)

3001

{

2999

{

3002

int val;

3000

int val;

3003

struct atl2_option opt;

3001

struct atl2_option opt;

3004

int bd = adapter->bd_number;

3002

int bd = adapter->bd_number;

3005

if (bd >= ATL2_MAX_NIC) {

3003

if (bd >= ATL2_MAX_NIC) {

3006

printk(KERN_NOTICE "Warning: no configuration for board #%i\n",

3004

printk(KERN_NOTICE "Warning: no configuration for board #%i\n",

3007

bd);

3005

bd);

3008

printk(KERN_NOTICE "Using defaults for all values\n");

3006

printk(KERN_NOTICE "Using defaults for all values\n");

3009

#ifndef module_param_array

3007

#ifndef module_param_array

3010

bd = ATL2_MAX_NIC;

3008

bd = ATL2_MAX_NIC;

3011

#endif

3009

#endif

3012

}

3010

}

3013

3011

3014

/* Bytes of Transmit Memory */

3012

/* Bytes of Transmit Memory */

3015

opt.type = range_option;

3013

opt.type = range_option;

3016

opt.name = "Bytes of Transmit Memory";

3014

opt.name = "Bytes of Transmit Memory";

3017

opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);

3015

opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);

3018

opt.def = ATL2_DEFAULT_TX_MEMSIZE;

3016

opt.def = ATL2_DEFAULT_TX_MEMSIZE;

3019

opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;

3017

opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;

3020

opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;

3018

opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;

3021

#ifdef module_param_array

3019

#ifdef module_param_array

3022

if (num_TxMemSize > bd) {

3020

if (num_TxMemSize > bd) {

3023

#endif

3021

#endif

3024

val = TxMemSize[bd];

3022

val = TxMemSize[bd];

3025

atl2_validate_option(&val, &opt);

3023

atl2_validate_option(&val, &opt);

3026

adapter->txd_ring_size = ((u32) val) * 1024;

3024

adapter->txd_ring_size = ((u32) val) * 1024;

3027

#ifdef module_param_array

3025

#ifdef module_param_array

3028

} else

3026

} else

3029

adapter->txd_ring_size = ((u32)opt.def) * 1024;

3027

adapter->txd_ring_size = ((u32)opt.def) * 1024;

3030

#endif

3028

#endif

3031

/* txs ring size: */

3029

/* txs ring size: */

3032

adapter->txs_ring_size = adapter->txd_ring_size / 128;

3030

adapter->txs_ring_size = adapter->txd_ring_size / 128;

3033

if (adapter->txs_ring_size > 160)

3031

if (adapter->txs_ring_size > 160)

3034

adapter->txs_ring_size = 160;

3032

adapter->txs_ring_size = 160;

3035

3033

3036

/* Receive Memory Block Count */

3034

/* Receive Memory Block Count */

3037

opt.type = range_option;

3035

opt.type = range_option;

3038

opt.name = "Number of receive memory block";

3036

opt.name = "Number of receive memory block";

3039

opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);

3037

opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);

3040

opt.def = ATL2_DEFAULT_RXD_COUNT;

3038

opt.def = ATL2_DEFAULT_RXD_COUNT;

3041

opt.arg.r.min = ATL2_MIN_RXD_COUNT;

3039

opt.arg.r.min = ATL2_MIN_RXD_COUNT;

3042

opt.arg.r.max = ATL2_MAX_RXD_COUNT;

3040

opt.arg.r.max = ATL2_MAX_RXD_COUNT;

3043

#ifdef module_param_array

3041

#ifdef module_param_array

3044

if (num_RxMemBlock > bd) {

3042

if (num_RxMemBlock > bd) {

3045

#endif

3043

#endif

3046

val = RxMemBlock[bd];

3044

val = RxMemBlock[bd];

3047

atl2_validate_option(&val, &opt);

3045

atl2_validate_option(&val, &opt);

3048

adapter->rxd_ring_size = (u32)val;

3046

adapter->rxd_ring_size = (u32)val;

3049

/* FIXME */

3047

/* FIXME */

3050

/* ((u16)val)&~1; */ /* even number */

3048

/* ((u16)val)&~1; */ /* even number */

3051

#ifdef module_param_array

3049

#ifdef module_param_array

3052

} else

3050

} else

3053

adapter->rxd_ring_size = (u32)opt.def;

3051

adapter->rxd_ring_size = (u32)opt.def;

3054

#endif

3052

#endif

3055

/* init RXD Flow control value */

3053

/* init RXD Flow control value */

3056

adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;

3054

adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;

3057

adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >

3055

adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >

3058

(adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :

3056

(adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :

3059

(adapter->rxd_ring_size / 12);

3057

(adapter->rxd_ring_size / 12);

3060

3058

3061

/* Interrupt Moderate Timer */

3059

/* Interrupt Moderate Timer */

3062

opt.type = range_option;

3060

opt.type = range_option;

3063

opt.name = "Interrupt Moderate Timer";

3061

opt.name = "Interrupt Moderate Timer";

3064

opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);

3062

opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);

3065

opt.def = INT_MOD_DEFAULT_CNT;

3063

opt.def = INT_MOD_DEFAULT_CNT;

3066

opt.arg.r.min = INT_MOD_MIN_CNT;

3064

opt.arg.r.min = INT_MOD_MIN_CNT;

3067

opt.arg.r.max = INT_MOD_MAX_CNT;

3065

opt.arg.r.max = INT_MOD_MAX_CNT;

3068

#ifdef module_param_array

3066

#ifdef module_param_array

3069

if (num_IntModTimer > bd) {

3067

if (num_IntModTimer > bd) {

3070

#endif

3068

#endif

3071

val = IntModTimer[bd];

3069

val = IntModTimer[bd];

3072

atl2_validate_option(&val, &opt);

3070

atl2_validate_option(&val, &opt);

3073

adapter->imt = (u16) val;

3071

adapter->imt = (u16) val;

3074

#ifdef module_param_array

3072

#ifdef module_param_array

3075

} else

3073

} else

3076

adapter->imt = (u16)(opt.def);

3074

adapter->imt = (u16)(opt.def);

3077

#endif

3075

#endif

3078

/* Flash Vendor */

3076

/* Flash Vendor */

3079

opt.type = range_option;

3077

opt.type = range_option;

3080

opt.name = "SPI Flash Vendor";

3078

opt.name = "SPI Flash Vendor";

3081

opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);

3079

opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);

3082

opt.def = FLASH_VENDOR_DEFAULT;

3080

opt.def = FLASH_VENDOR_DEFAULT;

3083

opt.arg.r.min = FLASH_VENDOR_MIN;

3081

opt.arg.r.min = FLASH_VENDOR_MIN;

3084

opt.arg.r.max = FLASH_VENDOR_MAX;

3082

opt.arg.r.max = FLASH_VENDOR_MAX;

3085

#ifdef module_param_array

3083

#ifdef module_param_array

3086

if (num_FlashVendor > bd) {

3084

if (num_FlashVendor > bd) {

3087

#endif

3085

#endif

3088

val = FlashVendor[bd];

3086

val = FlashVendor[bd];

3089

atl2_validate_option(&val, &opt);

3087

atl2_validate_option(&val, &opt);

3090

adapter->hw.flash_vendor = (u8) val;

3088

adapter->hw.flash_vendor = (u8) val;

3091

#ifdef module_param_array

3089

#ifdef module_param_array

3092

} else

3090

} else

3093

adapter->hw.flash_vendor = (u8)(opt.def);

3091

adapter->hw.flash_vendor = (u8)(opt.def);

3094

#endif

3092

#endif

3095

/* MediaType */

3093

/* MediaType */

3096

opt.type = range_option;

3094

opt.type = range_option;

3097

opt.name = "Speed/Duplex Selection";

3095

opt.name = "Speed/Duplex Selection";

3098

opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);

3096

opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);

3099

opt.def = MEDIA_TYPE_AUTO_SENSOR;

3097

opt.def = MEDIA_TYPE_AUTO_SENSOR;

3100

opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;

3098

opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;

3101

opt.arg.r.max = MEDIA_TYPE_10M_HALF;

3099

opt.arg.r.max = MEDIA_TYPE_10M_HALF;

3102

#ifdef module_param_array

3100

#ifdef module_param_array

3103

if (num_MediaType > bd) {

3101

if (num_MediaType > bd) {

3104

#endif

3102

#endif

3105

val = MediaType[bd];

3103

val = MediaType[bd];

3106

atl2_validate_option(&val, &opt);

3104

atl2_validate_option(&val, &opt);

3107

adapter->hw.MediaType = (u16) val;

3105

adapter->hw.MediaType = (u16) val;

3108

#ifdef module_param_array

3106

#ifdef module_param_array

3109

} else

3107

} else

3110

adapter->hw.MediaType = (u16)(opt.def);

3108

adapter->hw.MediaType = (u16)(opt.def);

3111

#endif

3109

#endif

3112

}

3110

}

3113

3111

GITLAB

atlx: fix warning in drivers/net/atlx/atl2.c

 /*
  * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
  * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
  *
  * Derived from Intel e1000 driver
  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the Free
  * Software Foundation; either version 2 of the License, or (at your option)
  * any later version.
  *
  * This program is distributed in the hope that it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  *
  * You should have received a copy of the GNU General Public License along with
  * this program; if not, write to the Free Software Foundation, Inc., 59
  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  */
 #include <asm/atomic.h>
 #include <linux/crc32.h>
 #include <linux/dma-mapping.h>
 #include <linux/etherdevice.h>
 #include <linux/ethtool.h>
 #include <linux/hardirq.h>
 #include <linux/if_vlan.h>
 #include <linux/in.h>
 #include <linux/interrupt.h>
 #include <linux/ip.h>
 #include <linux/irqflags.h>
 #include <linux/irqreturn.h>
 #include <linux/mii.h>
 #include <linux/net.h>
 #include <linux/netdevice.h>
 #include <linux/pci.h>
 #include <linux/pci_ids.h>
 #include <linux/pm.h>
 #include <linux/skbuff.h>
 #include <linux/spinlock.h>
 #include <linux/string.h>
 #include <linux/tcp.h>
 #include <linux/timer.h>
 #include <linux/types.h>
 #include <linux/workqueue.h>
 #include "atl2.h"
 #define ATL2_DRV_VERSION "2.2.3"
 static char atl2_driver_name[] = "atl2";
 static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
 static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
 static char atl2_driver_version[] = ATL2_DRV_VERSION;
 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(ATL2_DRV_VERSION);
 /*
  * atl2_pci_tbl - PCI Device ID Table
  */
 static struct pci_device_id atl2_pci_tbl[] = {
 	{PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
 	/* required last entry */
 	{0,}
 };
 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
 static void atl2_set_ethtool_ops(struct net_device *netdev);
 static void atl2_check_options(struct atl2_adapter *adapter);
 /*
  * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
  * @adapter: board private structure to initialize
  *
  * atl2_sw_init initializes the Adapter private data structure.
  * Fields are initialized based on PCI device information and
  * OS network device settings (MTU size).
  */
 static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
 {
 	struct atl2_hw *hw = &adapter->hw;
 	struct pci_dev *pdev = adapter->pdev;
 	/* PCI config space info */
 	hw->vendor_id = pdev->vendor;
 	hw->device_id = pdev->device;
 	hw->subsystem_vendor_id = pdev->subsystem_vendor;
 	hw->subsystem_id = pdev->subsystem_device;
 	pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
 	pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
 	adapter->wol = 0;
 	adapter->ict = 50000;  /* ~100ms */
 	adapter->link_speed = SPEED_0;   /* hardware init */
 	adapter->link_duplex = FULL_DUPLEX;
 	hw->phy_configured = false;
 	hw->preamble_len = 7;
 	hw->ipgt = 0x60;
 	hw->min_ifg = 0x50;
 	hw->ipgr1 = 0x40;
 	hw->ipgr2 = 0x60;
 	hw->retry_buf = 2;
 	hw->max_retry = 0xf;
 	hw->lcol = 0x37;
 	hw->jam_ipg = 7;
 	hw->fc_rxd_hi = 0;
 	hw->fc_rxd_lo = 0;
 	hw->max_frame_size = adapter->netdev->mtu;
 	spin_lock_init(&adapter->stats_lock);
 	set_bit(__ATL2_DOWN, &adapter->flags);
 	return 0;
 }
 /*
  * atl2_set_multi - Multicast and Promiscuous mode set
  * @netdev: network interface device structure
  *
  * The set_multi entry point is called whenever the multicast address
  * list or the network interface flags are updated.  This routine is
  * responsible for configuring the hardware for proper multicast,
  * promiscuous mode, and all-multi behavior.
  */
 static void atl2_set_multi(struct net_device *netdev)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	struct atl2_hw *hw = &adapter->hw;
 	struct dev_mc_list *mc_ptr;
 	u32 rctl;
 	u32 hash_value;
 	/* Check for Promiscuous and All Multicast modes */
 	rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
 	if (netdev->flags & IFF_PROMISC) {
 		rctl |= MAC_CTRL_PROMIS_EN;
 	} else if (netdev->flags & IFF_ALLMULTI) {
 		rctl |= MAC_CTRL_MC_ALL_EN;
 		rctl &= ~MAC_CTRL_PROMIS_EN;
 	} else
 		rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
 	ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
 	/* clear the old settings from the multicast hash table */
 	ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
 	ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
 	/* comoute mc addresses' hash value ,and put it into hash table */
 	for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
 		hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);
 		atl2_hash_set(hw, hash_value);
 	}
 }
 static void init_ring_ptrs(struct atl2_adapter *adapter)
 {
 	/* Read / Write Ptr Initialize: */
 	adapter->txd_write_ptr = 0;
 	atomic_set(&adapter->txd_read_ptr, 0);
 	adapter->rxd_read_ptr = 0;
 	adapter->rxd_write_ptr = 0;
 	atomic_set(&adapter->txs_write_ptr, 0);
 	adapter->txs_next_clear = 0;
 }
 /*
  * atl2_configure - Configure Transmit&Receive Unit after Reset
  * @adapter: board private structure
  *
  * Configure the Tx /Rx unit of the MAC after a reset.
  */
 static int atl2_configure(struct atl2_adapter *adapter)
 {
 	struct atl2_hw *hw = &adapter->hw;
 	u32 value;
 	/* clear interrupt status */
 	ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
 	/* set MAC Address */
 	value = (((u32)hw->mac_addr[2]) << 24) |
 		(((u32)hw->mac_addr[3]) << 16) |
 		(((u32)hw->mac_addr[4]) << 8) |
 		(((u32)hw->mac_addr[5]));
 	ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
 	value = (((u32)hw->mac_addr[0]) << 8) |
 		(((u32)hw->mac_addr[1]));
 	ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
 	/* HI base address */
 	ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
 		(u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
 	/* LO base address */
 	ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
 		(u32)(adapter->txd_dma & 0x00000000ffffffffULL));
 	ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
 		(u32)(adapter->txs_dma & 0x00000000ffffffffULL));
 	ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
 		(u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
 	/* element count */
 	ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
 	ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
 	ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM,  (u16)adapter->rxd_ring_size);
 	/* config Internal SRAM */
 /*
     ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
     ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
 */
 	/* config IPG/IFG */
 	value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
 		MAC_IPG_IFG_IPGT_SHIFT) |
 		(((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
 		MAC_IPG_IFG_MIFG_SHIFT) |
 		(((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
 		MAC_IPG_IFG_IPGR1_SHIFT)|
 		(((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
 		MAC_IPG_IFG_IPGR2_SHIFT);
 	ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
 	/* config  Half-Duplex Control */
 	value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
 		(((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
 		MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
 		MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
 		(0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
 		(((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
 		MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
 	ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
 	/* set Interrupt Moderator Timer */
 	ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
 	ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
 	/* set Interrupt Clear Timer */
 	ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
 	/* set MTU */
 	ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
 		ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
 	/* 1590 */
 	ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
 	/* flow control */
 	ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
 	ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
 	/* Init mailbox */
 	ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
 	ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
 	/* enable DMA read/write */
 	ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
 	ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
 	value = ATL2_READ_REG(&adapter->hw, REG_ISR);
 	if ((value & ISR_PHY_LINKDOWN) != 0)
 		value = 1; /* config failed */
 	else
 		value = 0;
 	/* clear all interrupt status */
 	ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
 	ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
 	return value;
 }
 /*
  * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
  * @adapter: board private structure
  *
  * Return 0 on success, negative on failure
  */
 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
 {
 	struct pci_dev *pdev = adapter->pdev;
 	int size;
 	u8 offset = 0;
 	/* real ring DMA buffer */
 	adapter->ring_size = size =
 		adapter->txd_ring_size * 1 + 7 +	/* dword align */
 		adapter->txs_ring_size * 4 + 7 +	/* dword align */
 		adapter->rxd_ring_size * 1536 + 127;	/* 128bytes align */
 	adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
 		&adapter->ring_dma);
 	if (!adapter->ring_vir_addr)
 		return -ENOMEM;
 	memset(adapter->ring_vir_addr, 0, adapter->ring_size);
 	/* Init TXD Ring */
 	adapter->txd_dma = adapter->ring_dma ;
 	offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
 	adapter->txd_dma += offset;
 	adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +
 		offset);
 	/* Init TXS Ring */
 	adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
 	offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
 	adapter->txs_dma += offset;
 	adapter->txs_ring = (struct tx_pkt_status *)
 		(((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
 	/* Init RXD Ring */
 	adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
 	offset = (adapter->rxd_dma & 127) ?
 		(128 - (adapter->rxd_dma & 127)) : 0;
 	if (offset > 7)
 		offset -= 8;
 	else
 		offset += (128 - 8);
 	adapter->rxd_dma += offset;
 	adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
 		(adapter->txs_ring_size * 4 + offset));
 /*
  * Read / Write Ptr Initialize:
  *      init_ring_ptrs(adapter);
  */
 	return 0;
 }
 /*
  * atl2_irq_enable - Enable default interrupt generation settings
  * @adapter: board private structure
  */
 static inline void atl2_irq_enable(struct atl2_adapter *adapter)
 {
 	ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
 	ATL2_WRITE_FLUSH(&adapter->hw);
 }
 /*
  * atl2_irq_disable - Mask off interrupt generation on the NIC
  * @adapter: board private structure
  */
 static inline void atl2_irq_disable(struct atl2_adapter *adapter)
 {
     ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
     ATL2_WRITE_FLUSH(&adapter->hw);
     synchronize_irq(adapter->pdev->irq);
 }
 #ifdef NETIF_F_HW_VLAN_TX
 static void atl2_vlan_rx_register(struct net_device *netdev,
 	struct vlan_group *grp)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	u32 ctrl;
 	atl2_irq_disable(adapter);
 	adapter->vlgrp = grp;
 	if (grp) {
 		/* enable VLAN tag insert/strip */
 		ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
 		ctrl |= MAC_CTRL_RMV_VLAN;
 		ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
 	} else {
 		/* disable VLAN tag insert/strip */
 		ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
 		ctrl &= ~MAC_CTRL_RMV_VLAN;
 		ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
 	}
 	atl2_irq_enable(adapter);
 }
 static void atl2_restore_vlan(struct atl2_adapter *adapter)
 {
 	atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
 }
 #endif
 static void atl2_intr_rx(struct atl2_adapter *adapter)
 {
 	struct net_device *netdev = adapter->netdev;
 	struct rx_desc *rxd;
 	struct sk_buff *skb;
 	do {
 		rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
 		if (!rxd->status.update)
 			break; /* end of tx */
 		/* clear this flag at once */
 		rxd->status.update = 0;
 		if (rxd->status.ok && rxd->status.pkt_size >= 60) {
 			int rx_size = (int)(rxd->status.pkt_size - 4);
 			/* alloc new buffer */
 			skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN);
 			if (NULL == skb) {
 				printk(KERN_WARNING
 					"%s: Mem squeeze, deferring packet.\n",
 					netdev->name);
 				/*
 				 * Check that some rx space is free. If not,
 				 * free one and mark stats->rx_dropped++.
 				 */
 				netdev->stats.rx_dropped++;
 				break;
 			}
 			skb_reserve(skb, NET_IP_ALIGN);
 			skb->dev = netdev;
 			memcpy(skb->data, rxd->packet, rx_size);
 			skb_put(skb, rx_size);
 			skb->protocol = eth_type_trans(skb, netdev);
 #ifdef NETIF_F_HW_VLAN_TX
 			if (adapter->vlgrp && (rxd->status.vlan)) {
 				u16 vlan_tag = (rxd->status.vtag>>4) |
 					((rxd->status.vtag&7) << 13) |
 					((rxd->status.vtag&8) << 9);
 				vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
 			} else
 #endif
 			netif_rx(skb);
 			netdev->stats.rx_bytes += rx_size;
 			netdev->stats.rx_packets++;
 		} else {
 			netdev->stats.rx_errors++;
 			if (rxd->status.ok && rxd->status.pkt_size <= 60)
 				netdev->stats.rx_length_errors++;
 			if (rxd->status.mcast)
 				netdev->stats.multicast++;
 			if (rxd->status.crc)
 				netdev->stats.rx_crc_errors++;
 			if (rxd->status.align)
 				netdev->stats.rx_frame_errors++;
 		}
 		/* advance write ptr */
 		if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
 			adapter->rxd_write_ptr = 0;
 	} while (1);
 	/* update mailbox? */
 	adapter->rxd_read_ptr = adapter->rxd_write_ptr;
 	ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
 }
 static void atl2_intr_tx(struct atl2_adapter *adapter)
 {
 	struct net_device *netdev = adapter->netdev;
 	u32 txd_read_ptr;
 	u32 txs_write_ptr;
 	struct tx_pkt_status *txs;
 	struct tx_pkt_header *txph;
 	int free_hole = 0;
 	do {
 		txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
 		txs = adapter->txs_ring + txs_write_ptr;
 		if (!txs->update)
 			break; /* tx stop here */
 		free_hole = 1;
 		txs->update = 0;
 		if (++txs_write_ptr == adapter->txs_ring_size)
 			txs_write_ptr = 0;
 		atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
 		txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
 		txph = (struct tx_pkt_header *)
 			(((u8 *)adapter->txd_ring) + txd_read_ptr);
 		if (txph->pkt_size != txs->pkt_size) {
 			struct tx_pkt_status *old_txs = txs;
 			printk(KERN_WARNING
 				"%s: txs packet size not consistent with txd"
 				" txd_:0x%08x, txs_:0x%08x!\n",
 				adapter->netdev->name,
 				*(u32 *)txph, *(u32 *)txs);
 			printk(KERN_WARNING
 				"txd read ptr: 0x%x\n",
 				txd_read_ptr);
 			txs = adapter->txs_ring + txs_write_ptr;
 			printk(KERN_WARNING
 				"txs-behind:0x%08x\n",
 				*(u32 *)txs);
 			if (txs_write_ptr < 2) {
 				txs = adapter->txs_ring +
 					(adapter->txs_ring_size +
 					txs_write_ptr - 2);
 			} else {
 				txs = adapter->txs_ring + (txs_write_ptr - 2);
 			}
 			printk(KERN_WARNING
 				"txs-before:0x%08x\n",
 				*(u32 *)txs);
 			txs = old_txs;
 		}
 		 /* 4for TPH */
 		txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
 		if (txd_read_ptr >= adapter->txd_ring_size)
 			txd_read_ptr -= adapter->txd_ring_size;
 		atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
 		/* tx statistics: */
 		if (txs->ok) {
 			netdev->stats.tx_bytes += txs->pkt_size;
 			netdev->stats.tx_packets++;
 		}
 		else
 			netdev->stats.tx_errors++;
 		if (txs->defer)
 			netdev->stats.collisions++;
 		if (txs->abort_col)
 			netdev->stats.tx_aborted_errors++;
 		if (txs->late_col)
 			netdev->stats.tx_window_errors++;
 		if (txs->underun)
 			netdev->stats.tx_fifo_errors++;
 	} while (1);
 	if (free_hole) {
 		if (netif_queue_stopped(adapter->netdev) &&
 			netif_carrier_ok(adapter->netdev))
 			netif_wake_queue(adapter->netdev);
 	}
 }
 static void atl2_check_for_link(struct atl2_adapter *adapter)
 {
 	struct net_device *netdev = adapter->netdev;
 	u16 phy_data = 0;
 	spin_lock(&adapter->stats_lock);
 	atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
 	atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
 	spin_unlock(&adapter->stats_lock);
 	/* notify upper layer link down ASAP */
 	if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
 		if (netif_carrier_ok(netdev)) { /* old link state: Up */
 		printk(KERN_INFO "%s: %s NIC Link is Down\n",
 			atl2_driver_name, netdev->name);
 		adapter->link_speed = SPEED_0;
 		netif_carrier_off(netdev);
 		netif_stop_queue(netdev);
 		}
 	}
 	schedule_work(&adapter->link_chg_task);
 }
 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
 {
 	u16 phy_data;
 	spin_lock(&adapter->stats_lock);
 	atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
 	spin_unlock(&adapter->stats_lock);
 }
 /*
  * atl2_intr - Interrupt Handler
  * @irq: interrupt number
  * @data: pointer to a network interface device structure
  * @pt_regs: CPU registers structure
  */
 static irqreturn_t atl2_intr(int irq, void *data)
 {
 	struct atl2_adapter *adapter = netdev_priv(data);
 	struct atl2_hw *hw = &adapter->hw;
 	u32 status;
 	status = ATL2_READ_REG(hw, REG_ISR);
 	if (0 == status)
 		return IRQ_NONE;
 	/* link event */
 	if (status & ISR_PHY)
 		atl2_clear_phy_int(adapter);
 	/* clear ISR status, and Enable CMB DMA/Disable Interrupt */
 	ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
 	/* check if PCIE PHY Link down */
 	if (status & ISR_PHY_LINKDOWN) {
 		if (netif_running(adapter->netdev)) { /* reset MAC */
 			ATL2_WRITE_REG(hw, REG_ISR, 0);
 			ATL2_WRITE_REG(hw, REG_IMR, 0);
 			ATL2_WRITE_FLUSH(hw);
 			schedule_work(&adapter->reset_task);
 			return IRQ_HANDLED;
 		}
 	}
 	/* check if DMA read/write error? */
 	if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
 		ATL2_WRITE_REG(hw, REG_ISR, 0);
 		ATL2_WRITE_REG(hw, REG_IMR, 0);
 		ATL2_WRITE_FLUSH(hw);
 		schedule_work(&adapter->reset_task);
 		return IRQ_HANDLED;
 	}
 	/* link event */
 	if (status & (ISR_PHY | ISR_MANUAL)) {
 		adapter->netdev->stats.tx_carrier_errors++;
 		atl2_check_for_link(adapter);
 	}
 	/* transmit event */
 	if (status & ISR_TX_EVENT)
 		atl2_intr_tx(adapter);
 	/* rx exception */
 	if (status & ISR_RX_EVENT)
 		atl2_intr_rx(adapter);
 	/* re-enable Interrupt */
 	ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
 	return IRQ_HANDLED;
 }
 static int atl2_request_irq(struct atl2_adapter *adapter)
 {
 	struct net_device *netdev = adapter->netdev;
 	int flags, err = 0;
 	flags = IRQF_SHARED;
-#ifdef CONFIG_PCI_MSI
 	adapter->have_msi = true;
 	err = pci_enable_msi(adapter->pdev);
 	if (err)
 		adapter->have_msi = false;
 	if (adapter->have_msi)
 		flags &= ~IRQF_SHARED;
-#endif
 	return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name,
 		netdev);
 }
 /*
  * atl2_free_ring_resources - Free Tx / RX descriptor Resources
  * @adapter: board private structure
  *
  * Free all transmit software resources
  */
 static void atl2_free_ring_resources(struct atl2_adapter *adapter)
 {
 	struct pci_dev *pdev = adapter->pdev;
 	pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
 		adapter->ring_dma);
 }
 /*
  * atl2_open - Called when a network interface is made active
  * @netdev: network interface device structure
  *
  * Returns 0 on success, negative value on failure
  *
  * The open entry point is called when a network interface is made
  * active by the system (IFF_UP).  At this point all resources needed
  * for transmit and receive operations are allocated, the interrupt
  * handler is registered with the OS, the watchdog timer is started,
  * and the stack is notified that the interface is ready.
  */
 static int atl2_open(struct net_device *netdev)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	int err;
 	u32 val;
 	/* disallow open during test */
 	if (test_bit(__ATL2_TESTING, &adapter->flags))
 		return -EBUSY;
 	/* allocate transmit descriptors */
 	err = atl2_setup_ring_resources(adapter);
 	if (err)
 		return err;
 	err = atl2_init_hw(&adapter->hw);
 	if (err) {
 		err = -EIO;
 		goto err_init_hw;
 	}
 	/* hardware has been reset, we need to reload some things */
 	atl2_set_multi(netdev);
 	init_ring_ptrs(adapter);
 #ifdef NETIF_F_HW_VLAN_TX
 	atl2_restore_vlan(adapter);
 #endif
 	if (atl2_configure(adapter)) {
 		err = -EIO;
 		goto err_config;
 	}
 	err = atl2_request_irq(adapter);
 	if (err)
 		goto err_req_irq;
 	clear_bit(__ATL2_DOWN, &adapter->flags);
 	mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
 	val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
 	ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
 		val | MASTER_CTRL_MANUAL_INT);
 	atl2_irq_enable(adapter);
 	return 0;
 err_init_hw:
 err_req_irq:
 err_config:
 	atl2_free_ring_resources(adapter);
 	atl2_reset_hw(&adapter->hw);
 	return err;
 }
 static void atl2_down(struct atl2_adapter *adapter)
 {
 	struct net_device *netdev = adapter->netdev;
 	/* signal that we're down so the interrupt handler does not
 	 * reschedule our watchdog timer */
 	set_bit(__ATL2_DOWN, &adapter->flags);
 	netif_tx_disable(netdev);
 	/* reset MAC to disable all RX/TX */
 	atl2_reset_hw(&adapter->hw);
 	msleep(1);
 	atl2_irq_disable(adapter);
 	del_timer_sync(&adapter->watchdog_timer);
 	del_timer_sync(&adapter->phy_config_timer);
 	clear_bit(0, &adapter->cfg_phy);
 	netif_carrier_off(netdev);
 	adapter->link_speed = SPEED_0;
 	adapter->link_duplex = -1;
 }
 static void atl2_free_irq(struct atl2_adapter *adapter)
 {
 	struct net_device *netdev = adapter->netdev;
 	free_irq(adapter->pdev->irq, netdev);
 #ifdef CONFIG_PCI_MSI
 	if (adapter->have_msi)
 		pci_disable_msi(adapter->pdev);
 #endif
 }
 /*
  * atl2_close - Disables a network interface
  * @netdev: network interface device structure
  *
  * Returns 0, this is not allowed to fail
  *
  * The close entry point is called when an interface is de-activated
  * by the OS.  The hardware is still under the drivers control, but
  * needs to be disabled.  A global MAC reset is issued to stop the
  * hardware, and all transmit and receive resources are freed.
  */
 static int atl2_close(struct net_device *netdev)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
 	atl2_down(adapter);
 	atl2_free_irq(adapter);
 	atl2_free_ring_resources(adapter);
 	return 0;
 }
 static inline int TxsFreeUnit(struct atl2_adapter *adapter)
 {
 	u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
 	return (adapter->txs_next_clear >= txs_write_ptr) ?
 		(int) (adapter->txs_ring_size - adapter->txs_next_clear +
 		txs_write_ptr - 1) :
 		(int) (txs_write_ptr - adapter->txs_next_clear - 1);
 }
 static inline int TxdFreeBytes(struct atl2_adapter *adapter)
 {
 	u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
 	return (adapter->txd_write_ptr >= txd_read_ptr) ?
 		(int) (adapter->txd_ring_size - adapter->txd_write_ptr +
 		txd_read_ptr - 1) :
 		(int) (txd_read_ptr - adapter->txd_write_ptr - 1);
 }
 static int atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	struct tx_pkt_header *txph;
 	u32 offset, copy_len;
 	int txs_unused;
 	int txbuf_unused;
 	if (test_bit(__ATL2_DOWN, &adapter->flags)) {
 		dev_kfree_skb_any(skb);
 		return NETDEV_TX_OK;
 	}
 	if (unlikely(skb->len <= 0)) {
 		dev_kfree_skb_any(skb);
 		return NETDEV_TX_OK;
 	}
 	txs_unused = TxsFreeUnit(adapter);
 	txbuf_unused = TxdFreeBytes(adapter);
 	if (skb->len + sizeof(struct tx_pkt_header) + 4  > txbuf_unused ||
 		txs_unused < 1) {
 		/* not enough resources */
 		netif_stop_queue(netdev);
 		return NETDEV_TX_BUSY;
 	}
 	offset = adapter->txd_write_ptr;
 	txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
 	*(u32 *)txph = 0;
 	txph->pkt_size = skb->len;
 	offset += 4;
 	if (offset >= adapter->txd_ring_size)
 		offset -= adapter->txd_ring_size;
 	copy_len = adapter->txd_ring_size - offset;
 	if (copy_len >= skb->len) {
 		memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
 		offset += ((u32)(skb->len + 3) & ~3);
 	} else {
 		memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
 		memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
 			skb->len-copy_len);
 		offset = ((u32)(skb->len-copy_len + 3) & ~3);
 	}
 #ifdef NETIF_F_HW_VLAN_TX
 	if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
 		u16 vlan_tag = vlan_tx_tag_get(skb);
 		vlan_tag = (vlan_tag << 4) |
 			(vlan_tag >> 13) |
 			((vlan_tag >> 9) & 0x8);
 		txph->ins_vlan = 1;
 		txph->vlan = vlan_tag;
 	}
 #endif
 	if (offset >= adapter->txd_ring_size)
 		offset -= adapter->txd_ring_size;
 	adapter->txd_write_ptr = offset;
 	/* clear txs before send */
 	adapter->txs_ring[adapter->txs_next_clear].update = 0;
 	if (++adapter->txs_next_clear == adapter->txs_ring_size)
 		adapter->txs_next_clear = 0;
 	ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
 		(adapter->txd_write_ptr >> 2));
 	mmiowb();
 	netdev->trans_start = jiffies;
 	dev_kfree_skb_any(skb);
 	return NETDEV_TX_OK;
 }
 /*
  * atl2_change_mtu - Change the Maximum Transfer Unit
  * @netdev: network interface device structure
  * @new_mtu: new value for maximum frame size
  *
  * Returns 0 on success, negative on failure
  */
 static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	struct atl2_hw *hw = &adapter->hw;
 	if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
 		return -EINVAL;
 	/* set MTU */
 	if (hw->max_frame_size != new_mtu) {
 		netdev->mtu = new_mtu;
 		ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
 			VLAN_SIZE + ETHERNET_FCS_SIZE);
 	}
 	return 0;
 }
 /*
  * atl2_set_mac - Change the Ethernet Address of the NIC
  * @netdev: network interface device structure
  * @p: pointer to an address structure
  *
  * Returns 0 on success, negative on failure
  */
 static int atl2_set_mac(struct net_device *netdev, void *p)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	struct sockaddr *addr = p;
 	if (!is_valid_ether_addr(addr->sa_data))
 		return -EADDRNOTAVAIL;
 	if (netif_running(netdev))
 		return -EBUSY;
 	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
 	memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
 	atl2_set_mac_addr(&adapter->hw);
 	return 0;
 }
 /*
  * atl2_mii_ioctl -
  * @netdev:
  * @ifreq:
  * @cmd:
  */
 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	struct mii_ioctl_data *data = if_mii(ifr);
 	unsigned long flags;
 	switch (cmd) {
 	case SIOCGMIIPHY:
 		data->phy_id = 0;
 		break;
 	case SIOCGMIIREG:
 		if (!capable(CAP_NET_ADMIN))
 			return -EPERM;
 		spin_lock_irqsave(&adapter->stats_lock, flags);
 		if (atl2_read_phy_reg(&adapter->hw,
 			data->reg_num & 0x1F, &data->val_out)) {
 			spin_unlock_irqrestore(&adapter->stats_lock, flags);
 			return -EIO;
 		}
 		spin_unlock_irqrestore(&adapter->stats_lock, flags);
 		break;
 	case SIOCSMIIREG:
 		if (!capable(CAP_NET_ADMIN))
 			return -EPERM;
 		if (data->reg_num & ~(0x1F))
 			return -EFAULT;
 		spin_lock_irqsave(&adapter->stats_lock, flags);
 		if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
 			data->val_in)) {
 			spin_unlock_irqrestore(&adapter->stats_lock, flags);
 			return -EIO;
 		}
 		spin_unlock_irqrestore(&adapter->stats_lock, flags);
 		break;
 	default:
 		return -EOPNOTSUPP;
 	}
 	return 0;
 }
 /*
  * atl2_ioctl -
  * @netdev:
  * @ifreq:
  * @cmd:
  */
 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
 {
 	switch (cmd) {
 	case SIOCGMIIPHY:
 	case SIOCGMIIREG:
 	case SIOCSMIIREG:
 		return atl2_mii_ioctl(netdev, ifr, cmd);
 #ifdef ETHTOOL_OPS_COMPAT
 	case SIOCETHTOOL:
 		return ethtool_ioctl(ifr);
 #endif
 	default:
 		return -EOPNOTSUPP;
 	}
 }
 /*
  * atl2_tx_timeout - Respond to a Tx Hang
  * @netdev: network interface device structure
  */
 static void atl2_tx_timeout(struct net_device *netdev)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	/* Do the reset outside of interrupt context */
 	schedule_work(&adapter->reset_task);
 }
 /*
  * atl2_watchdog - Timer Call-back
  * @data: pointer to netdev cast into an unsigned long
  */
 static void atl2_watchdog(unsigned long data)
 {
 	struct atl2_adapter *adapter = (struct atl2_adapter *) data;
 	if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
 		u32 drop_rxd, drop_rxs;
 		unsigned long flags;
 		spin_lock_irqsave(&adapter->stats_lock, flags);
 		drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
 		drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
 		spin_unlock_irqrestore(&adapter->stats_lock, flags);
 		adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
 		/* Reset the timer */
 		mod_timer(&adapter->watchdog_timer,
 			  round_jiffies(jiffies + 4 * HZ));
 	}
 }
 /*
  * atl2_phy_config - Timer Call-back
  * @data: pointer to netdev cast into an unsigned long
  */
 static void atl2_phy_config(unsigned long data)
 {
 	struct atl2_adapter *adapter = (struct atl2_adapter *) data;
 	struct atl2_hw *hw = &adapter->hw;
 	unsigned long flags;
 	spin_lock_irqsave(&adapter->stats_lock, flags);
 	atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
 	atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
 		MII_CR_RESTART_AUTO_NEG);
 	spin_unlock_irqrestore(&adapter->stats_lock, flags);
 	clear_bit(0, &adapter->cfg_phy);
 }
 static int atl2_up(struct atl2_adapter *adapter)
 {
 	struct net_device *netdev = adapter->netdev;
 	int err = 0;
 	u32 val;
 	/* hardware has been reset, we need to reload some things */
 	err = atl2_init_hw(&adapter->hw);
 	if (err) {
 		err = -EIO;
 		return err;
 	}
 	atl2_set_multi(netdev);
 	init_ring_ptrs(adapter);
 #ifdef NETIF_F_HW_VLAN_TX
 	atl2_restore_vlan(adapter);
 #endif
 	if (atl2_configure(adapter)) {
 		err = -EIO;
 		goto err_up;
 	}
 	clear_bit(__ATL2_DOWN, &adapter->flags);
 	val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
 	ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
 		MASTER_CTRL_MANUAL_INT);
 	atl2_irq_enable(adapter);
 err_up:
 	return err;
 }
 static void atl2_reinit_locked(struct atl2_adapter *adapter)
 {
 	WARN_ON(in_interrupt());
 	while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
 		msleep(1);
 	atl2_down(adapter);
 	atl2_up(adapter);
 	clear_bit(__ATL2_RESETTING, &adapter->flags);
 }
 static void atl2_reset_task(struct work_struct *work)
 {
 	struct atl2_adapter *adapter;
 	adapter = container_of(work, struct atl2_adapter, reset_task);
 	atl2_reinit_locked(adapter);
 }
 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
 {
 	u32 value;
 	struct atl2_hw *hw = &adapter->hw;
 	struct net_device *netdev = adapter->netdev;
 	/* Config MAC CTRL Register */
 	value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
 	/* duplex */
 	if (FULL_DUPLEX == adapter->link_duplex)
 		value |= MAC_CTRL_DUPLX;
 	/* flow control */
 	value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
 	/* PAD & CRC */
 	value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
 	/* preamble length */
 	value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
 		MAC_CTRL_PRMLEN_SHIFT);
 	/* vlan */
 	if (adapter->vlgrp)
 		value |= MAC_CTRL_RMV_VLAN;
 	/* filter mode */
 	value |= MAC_CTRL_BC_EN;
 	if (netdev->flags & IFF_PROMISC)
 		value |= MAC_CTRL_PROMIS_EN;
 	else if (netdev->flags & IFF_ALLMULTI)
 		value |= MAC_CTRL_MC_ALL_EN;
 	/* half retry buffer */
 	value |= (((u32)(adapter->hw.retry_buf &
 		MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
 	ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
 }
 static int atl2_check_link(struct atl2_adapter *adapter)
 {
 	struct atl2_hw *hw = &adapter->hw;
 	struct net_device *netdev = adapter->netdev;
 	int ret_val;
 	u16 speed, duplex, phy_data;
 	int reconfig = 0;
 	/* MII_BMSR must read twise */
 	atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
 	atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
 	if (!(phy_data&BMSR_LSTATUS)) { /* link down */
 		if (netif_carrier_ok(netdev)) { /* old link state: Up */
 			u32 value;
 			/* disable rx */
 			value = ATL2_READ_REG(hw, REG_MAC_CTRL);
 			value &= ~MAC_CTRL_RX_EN;
 			ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
 			adapter->link_speed = SPEED_0;
 			netif_carrier_off(netdev);
 			netif_stop_queue(netdev);
 		}
 		return 0;
 	}
 	/* Link Up */
 	ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
 	if (ret_val)
 		return ret_val;
 	switch (hw->MediaType) {
 	case MEDIA_TYPE_100M_FULL:
 		if (speed  != SPEED_100 || duplex != FULL_DUPLEX)
 			reconfig = 1;
 		break;
 	case MEDIA_TYPE_100M_HALF:
 		if (speed  != SPEED_100 || duplex != HALF_DUPLEX)
 			reconfig = 1;
 		break;
 	case MEDIA_TYPE_10M_FULL:
 		if (speed != SPEED_10 || duplex != FULL_DUPLEX)
 			reconfig = 1;
 		break;
 	case MEDIA_TYPE_10M_HALF:
 		if (speed  != SPEED_10 || duplex != HALF_DUPLEX)
 			reconfig = 1;
 		break;
 	}
 	/* link result is our setting */
 	if (reconfig == 0) {
 		if (adapter->link_speed != speed ||
 			adapter->link_duplex != duplex) {
 			adapter->link_speed = speed;
 			adapter->link_duplex = duplex;
 			atl2_setup_mac_ctrl(adapter);
 			printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
 				atl2_driver_name, netdev->name,
 				adapter->link_speed,
 				adapter->link_duplex == FULL_DUPLEX ?
 					"Full Duplex" : "Half Duplex");
 		}
 		if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
 			netif_carrier_on(netdev);
 			netif_wake_queue(netdev);
 		}
 		return 0;
 	}
 	/* change original link status */
 	if (netif_carrier_ok(netdev)) {
 		u32 value;
 		/* disable rx */
 		value = ATL2_READ_REG(hw, REG_MAC_CTRL);
 		value &= ~MAC_CTRL_RX_EN;
 		ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
 		adapter->link_speed = SPEED_0;
 		netif_carrier_off(netdev);
 		netif_stop_queue(netdev);
 	}
 	/* auto-neg, insert timer to re-config phy
 	 * (if interval smaller than 5 seconds, something strange) */
 	if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
 		if (!test_and_set_bit(0, &adapter->cfg_phy))
 			mod_timer(&adapter->phy_config_timer,
 				  round_jiffies(jiffies + 5 * HZ));
 	}
 	return 0;
 }
 /*
  * atl2_link_chg_task - deal with link change event Out of interrupt context
  * @netdev: network interface device structure
  */
 static void atl2_link_chg_task(struct work_struct *work)
 {
 	struct atl2_adapter *adapter;
 	unsigned long flags;
 	adapter = container_of(work, struct atl2_adapter, link_chg_task);
 	spin_lock_irqsave(&adapter->stats_lock, flags);
 	atl2_check_link(adapter);
 	spin_unlock_irqrestore(&adapter->stats_lock, flags);
 }
 static void atl2_setup_pcicmd(struct pci_dev *pdev)
 {
 	u16 cmd;
 	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
 	if (cmd & PCI_COMMAND_INTX_DISABLE)
 		cmd &= ~PCI_COMMAND_INTX_DISABLE;
 	if (cmd & PCI_COMMAND_IO)
 		cmd &= ~PCI_COMMAND_IO;
 	if (0 == (cmd & PCI_COMMAND_MEMORY))
 		cmd |= PCI_COMMAND_MEMORY;
 	if (0 == (cmd & PCI_COMMAND_MASTER))
 		cmd |= PCI_COMMAND_MASTER;
 	pci_write_config_word(pdev, PCI_COMMAND, cmd);
 	/*
 	 * some motherboards BIOS(PXE/EFI) driver may set PME
 	 * while they transfer control to OS (Windows/Linux)
 	 * so we should clear this bit before NIC work normally
 	 */
 	pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
 }
 #ifdef CONFIG_NET_POLL_CONTROLLER
 static void atl2_poll_controller(struct net_device *netdev)
 {
 	disable_irq(netdev->irq);
 	atl2_intr(netdev->irq, netdev);
 	enable_irq(netdev->irq);
 }
 #endif
 static const struct net_device_ops atl2_netdev_ops = {
 	.ndo_open		= atl2_open,
 	.ndo_stop		= atl2_close,
 	.ndo_start_xmit		= atl2_xmit_frame,
 	.ndo_set_multicast_list	= atl2_set_multi,
 	.ndo_validate_addr	= eth_validate_addr,
 	.ndo_set_mac_address	= atl2_set_mac,
 	.ndo_change_mtu		= atl2_change_mtu,
 	.ndo_do_ioctl		= atl2_ioctl,
 	.ndo_tx_timeout		= atl2_tx_timeout,
 	.ndo_vlan_rx_register	= atl2_vlan_rx_register,
 #ifdef CONFIG_NET_POLL_CONTROLLER
 	.ndo_poll_controller	= atl2_poll_controller,
 #endif
 };
 /*
  * atl2_probe - Device Initialization Routine
  * @pdev: PCI device information struct
  * @ent: entry in atl2_pci_tbl
  *
  * Returns 0 on success, negative on failure
  *
  * atl2_probe initializes an adapter identified by a pci_dev structure.
  * The OS initialization, configuring of the adapter private structure,
  * and a hardware reset occur.
  */
 static int __devinit atl2_probe(struct pci_dev *pdev,
 	const struct pci_device_id *ent)
 {
 	struct net_device *netdev;
 	struct atl2_adapter *adapter;
 	static int cards_found;
 	unsigned long mmio_start;
 	int mmio_len;
 	int err;
 	cards_found = 0;
 	err = pci_enable_device(pdev);
 	if (err)
 		return err;
 	/*
 	 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
 	 * until the kernel has the proper infrastructure to support 64-bit DMA
 	 * on these devices.
 	 */
 	if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) &&
 		pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
 		printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
 		goto err_dma;
 	}
 	/* Mark all PCI regions associated with PCI device
 	 * pdev as being reserved by owner atl2_driver_name */
 	err = pci_request_regions(pdev, atl2_driver_name);
 	if (err)
 		goto err_pci_reg;
 	/* Enables bus-mastering on the device and calls
 	 * pcibios_set_master to do the needed arch specific settings */
 	pci_set_master(pdev);
 	err = -ENOMEM;
 	netdev = alloc_etherdev(sizeof(struct atl2_adapter));
 	if (!netdev)
 		goto err_alloc_etherdev;
 	SET_NETDEV_DEV(netdev, &pdev->dev);
 	pci_set_drvdata(pdev, netdev);
 	adapter = netdev_priv(netdev);
 	adapter->netdev = netdev;
 	adapter->pdev = pdev;
 	adapter->hw.back = adapter;
 	mmio_start = pci_resource_start(pdev, 0x0);
 	mmio_len = pci_resource_len(pdev, 0x0);
 	adapter->hw.mem_rang = (u32)mmio_len;
 	adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
 	if (!adapter->hw.hw_addr) {
 		err = -EIO;
 		goto err_ioremap;
 	}
 	atl2_setup_pcicmd(pdev);
 	netdev->netdev_ops = &atl2_netdev_ops;
 	atl2_set_ethtool_ops(netdev);
 	netdev->watchdog_timeo = 5 * HZ;
 	strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
 	netdev->mem_start = mmio_start;
 	netdev->mem_end = mmio_start + mmio_len;
 	adapter->bd_number = cards_found;
 	adapter->pci_using_64 = false;
 	/* setup the private structure */
 	err = atl2_sw_init(adapter);
 	if (err)
 		goto err_sw_init;
 	err = -EIO;
 #ifdef NETIF_F_HW_VLAN_TX
 	netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
 #endif
 	/* Init PHY as early as possible due to power saving issue  */
 	atl2_phy_init(&adapter->hw);
 	/* reset the controller to
 	 * put the device in a known good starting state */
 	if (atl2_reset_hw(&adapter->hw)) {
 		err = -EIO;
 		goto err_reset;
 	}
 	/* copy the MAC address out of the EEPROM */
 	atl2_read_mac_addr(&adapter->hw);
 	memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
 /* FIXME: do we still need this? */
 #ifdef ETHTOOL_GPERMADDR
 	memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
 	if (!is_valid_ether_addr(netdev->perm_addr)) {
 #else
 	if (!is_valid_ether_addr(netdev->dev_addr)) {
 #endif
 		err = -EIO;
 		goto err_eeprom;
 	}
 	atl2_check_options(adapter);
 	init_timer(&adapter->watchdog_timer);
 	adapter->watchdog_timer.function = &atl2_watchdog;
 	adapter->watchdog_timer.data = (unsigned long) adapter;
 	init_timer(&adapter->phy_config_timer);
 	adapter->phy_config_timer.function = &atl2_phy_config;
 	adapter->phy_config_timer.data = (unsigned long) adapter;
 	INIT_WORK(&adapter->reset_task, atl2_reset_task);
 	INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
 	strcpy(netdev->name, "eth%d"); /* ?? */
 	err = register_netdev(netdev);
 	if (err)
 		goto err_register;
 	/* assume we have no link for now */
 	netif_carrier_off(netdev);
 	netif_stop_queue(netdev);
 	cards_found++;
 	return 0;
 err_reset:
 err_register:
 err_sw_init:
 err_eeprom:
 	iounmap(adapter->hw.hw_addr);
 err_ioremap:
 	free_netdev(netdev);
 err_alloc_etherdev:
 	pci_release_regions(pdev);
 err_pci_reg:
 err_dma:
 	pci_disable_device(pdev);
 	return err;
 }
 /*
  * atl2_remove - Device Removal Routine
  * @pdev: PCI device information struct
  *
  * atl2_remove is called by the PCI subsystem to alert the driver
  * that it should release a PCI device.  The could be caused by a
  * Hot-Plug event, or because the driver is going to be removed from
  * memory.
  */
 /* FIXME: write the original MAC address back in case it was changed from a
  * BIOS-set value, as in atl1 -- CHS */
 static void __devexit atl2_remove(struct pci_dev *pdev)
 {
 	struct net_device *netdev = pci_get_drvdata(pdev);
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	/* flush_scheduled work may reschedule our watchdog task, so
 	 * explicitly disable watchdog tasks from being rescheduled  */
 	set_bit(__ATL2_DOWN, &adapter->flags);
 	del_timer_sync(&adapter->watchdog_timer);
 	del_timer_sync(&adapter->phy_config_timer);
 	flush_scheduled_work();
 	unregister_netdev(netdev);
 	atl2_force_ps(&adapter->hw);
 	iounmap(adapter->hw.hw_addr);
 	pci_release_regions(pdev);
 	free_netdev(netdev);
 	pci_disable_device(pdev);
 }
 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
 {
 	struct net_device *netdev = pci_get_drvdata(pdev);
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	struct atl2_hw *hw = &adapter->hw;
 	u16 speed, duplex;
 	u32 ctrl = 0;
 	u32 wufc = adapter->wol;
 #ifdef CONFIG_PM
 	int retval = 0;
 #endif
 	netif_device_detach(netdev);
 	if (netif_running(netdev)) {
 		WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
 		atl2_down(adapter);
 	}
 #ifdef CONFIG_PM
 	retval = pci_save_state(pdev);
 	if (retval)
 		return retval;
 #endif
 	atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
 	atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
 	if (ctrl & BMSR_LSTATUS)
 		wufc &= ~ATLX_WUFC_LNKC;
 	if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
 		u32 ret_val;
 		/* get current link speed & duplex */
 		ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
 		if (ret_val) {
 			printk(KERN_DEBUG
 				"%s: get speed&duplex error while suspend\n",
 				atl2_driver_name);
 			goto wol_dis;
 		}
 		ctrl = 0;
 		/* turn on magic packet wol */
 		if (wufc & ATLX_WUFC_MAG)
 			ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
 		/* ignore Link Chg event when Link is up */
 		ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
 		/* Config MAC CTRL Register */
 		ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
 		if (FULL_DUPLEX == adapter->link_duplex)
 			ctrl |= MAC_CTRL_DUPLX;
 		ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
 		ctrl |= (((u32)adapter->hw.preamble_len &
 			MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
 		ctrl |= (((u32)(adapter->hw.retry_buf &
 			MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
 			MAC_CTRL_HALF_LEFT_BUF_SHIFT);
 		if (wufc & ATLX_WUFC_MAG) {
 			/* magic packet maybe Broadcast&multicast&Unicast */
 			ctrl |= MAC_CTRL_BC_EN;
 		}
 		ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
 		/* pcie patch */
 		ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
 		ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
 		ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
 		ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
 		ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
 		ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
 		pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
 		goto suspend_exit;
 	}
 	if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
 		/* link is down, so only LINK CHG WOL event enable */
 		ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
 		ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
 		ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
 		/* pcie patch */
 		ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
 		ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
 		ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
 		ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
 		ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
 		ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
 		hw->phy_configured = false; /* re-init PHY when resume */
 		pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
 		goto suspend_exit;
 	}
 wol_dis:
 	/* WOL disabled */
 	ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
 	/* pcie patch */
 	ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
 	ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
 	ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
 	ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
 	ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
 	ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
 	atl2_force_ps(hw);
 	hw->phy_configured = false; /* re-init PHY when resume */
 	pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
 suspend_exit:
 	if (netif_running(netdev))
 		atl2_free_irq(adapter);
 	pci_disable_device(pdev);
 	pci_set_power_state(pdev, pci_choose_state(pdev, state));
 	return 0;
 }
 #ifdef CONFIG_PM
 static int atl2_resume(struct pci_dev *pdev)
 {
 	struct net_device *netdev = pci_get_drvdata(pdev);
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	u32 err;
 	pci_set_power_state(pdev, PCI_D0);
 	pci_restore_state(pdev);
 	err = pci_enable_device(pdev);
 	if (err) {
 		printk(KERN_ERR
 			"atl2: Cannot enable PCI device from suspend\n");
 		return err;
 	}
 	pci_set_master(pdev);
 	ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
 	pci_enable_wake(pdev, PCI_D3hot, 0);
 	pci_enable_wake(pdev, PCI_D3cold, 0);
 	ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
 	if (netif_running(netdev)) {
 		err = atl2_request_irq(adapter);
 		if (err)
 			return err;
 	}
 	atl2_reset_hw(&adapter->hw);
 	if (netif_running(netdev))
 		atl2_up(adapter);
 	netif_device_attach(netdev);
 	return 0;
 }
 #endif
 static void atl2_shutdown(struct pci_dev *pdev)
 {
 	atl2_suspend(pdev, PMSG_SUSPEND);
 }
 static struct pci_driver atl2_driver = {
 	.name     = atl2_driver_name,
 	.id_table = atl2_pci_tbl,
 	.probe    = atl2_probe,
 	.remove   = __devexit_p(atl2_remove),
 	/* Power Managment Hooks */
 	.suspend  = atl2_suspend,
 #ifdef CONFIG_PM
 	.resume   = atl2_resume,
 #endif
 	.shutdown = atl2_shutdown,
 };
 /*
  * atl2_init_module - Driver Registration Routine
  *
  * atl2_init_module is the first routine called when the driver is
  * loaded. All it does is register with the PCI subsystem.
  */
 static int __init atl2_init_module(void)
 {
 	printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
 		atl2_driver_version);
 	printk(KERN_INFO "%s\n", atl2_copyright);
 	return pci_register_driver(&atl2_driver);
 }
 module_init(atl2_init_module);
 /*
  * atl2_exit_module - Driver Exit Cleanup Routine
  *
  * atl2_exit_module is called just before the driver is removed
  * from memory.
  */
 static void __exit atl2_exit_module(void)
 {
 	pci_unregister_driver(&atl2_driver);
 }
 module_exit(atl2_exit_module);
 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
 {
 	struct atl2_adapter *adapter = hw->back;
 	pci_read_config_word(adapter->pdev, reg, value);
 }
 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
 {
 	struct atl2_adapter *adapter = hw->back;
 	pci_write_config_word(adapter->pdev, reg, *value);
 }
 static int atl2_get_settings(struct net_device *netdev,
 	struct ethtool_cmd *ecmd)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	struct atl2_hw *hw = &adapter->hw;
 	ecmd->supported = (SUPPORTED_10baseT_Half |
 		SUPPORTED_10baseT_Full |
 		SUPPORTED_100baseT_Half |
 		SUPPORTED_100baseT_Full |
 		SUPPORTED_Autoneg |
 		SUPPORTED_TP);
 	ecmd->advertising = ADVERTISED_TP;
 	ecmd->advertising |= ADVERTISED_Autoneg;
 	ecmd->advertising |= hw->autoneg_advertised;
 	ecmd->port = PORT_TP;
 	ecmd->phy_address = 0;
 	ecmd->transceiver = XCVR_INTERNAL;
 	if (adapter->link_speed != SPEED_0) {
 		ecmd->speed = adapter->link_speed;
 		if (adapter->link_duplex == FULL_DUPLEX)
 			ecmd->duplex = DUPLEX_FULL;
 		else
 			ecmd->duplex = DUPLEX_HALF;
 	} else {
 		ecmd->speed = -1;
 		ecmd->duplex = -1;
 	}
 	ecmd->autoneg = AUTONEG_ENABLE;
 	return 0;
 }
 static int atl2_set_settings(struct net_device *netdev,
 	struct ethtool_cmd *ecmd)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	struct atl2_hw *hw = &adapter->hw;
 	while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
 		msleep(1);
 	if (ecmd->autoneg == AUTONEG_ENABLE) {
 #define MY_ADV_MASK	(ADVERTISE_10_HALF | \
 			 ADVERTISE_10_FULL | \
 			 ADVERTISE_100_HALF| \
 			 ADVERTISE_100_FULL)
 		if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
 			hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
 			hw->autoneg_advertised =  MY_ADV_MASK;
 		} else if ((ecmd->advertising & MY_ADV_MASK) ==
 				ADVERTISE_100_FULL) {
 			hw->MediaType = MEDIA_TYPE_100M_FULL;
 			hw->autoneg_advertised = ADVERTISE_100_FULL;
 		} else if ((ecmd->advertising & MY_ADV_MASK) ==
 				ADVERTISE_100_HALF) {
 			hw->MediaType = MEDIA_TYPE_100M_HALF;
 			hw->autoneg_advertised = ADVERTISE_100_HALF;
 		} else if ((ecmd->advertising & MY_ADV_MASK) ==
 				ADVERTISE_10_FULL) {
 			hw->MediaType = MEDIA_TYPE_10M_FULL;
 			hw->autoneg_advertised = ADVERTISE_10_FULL;
 		}  else if ((ecmd->advertising & MY_ADV_MASK) ==
 				ADVERTISE_10_HALF) {
 			hw->MediaType = MEDIA_TYPE_10M_HALF;
 			hw->autoneg_advertised = ADVERTISE_10_HALF;
 		} else {
 			clear_bit(__ATL2_RESETTING, &adapter->flags);
 			return -EINVAL;
 		}
 		ecmd->advertising = hw->autoneg_advertised |
 			ADVERTISED_TP | ADVERTISED_Autoneg;
 	} else {
 		clear_bit(__ATL2_RESETTING, &adapter->flags);
 		return -EINVAL;
 	}
 	/* reset the link */
 	if (netif_running(adapter->netdev)) {
 		atl2_down(adapter);
 		atl2_up(adapter);
 	} else
 		atl2_reset_hw(&adapter->hw);
 	clear_bit(__ATL2_RESETTING, &adapter->flags);
 	return 0;
 }
 static u32 atl2_get_tx_csum(struct net_device *netdev)
 {
 	return (netdev->features & NETIF_F_HW_CSUM) != 0;
 }
 static u32 atl2_get_msglevel(struct net_device *netdev)
 {
 	return 0;
 }
 /*
  * It's sane for this to be empty, but we might want to take advantage of this.
  */
 static void atl2_set_msglevel(struct net_device *netdev, u32 data)
 {
 }
 static int atl2_get_regs_len(struct net_device *netdev)
 {
 #define ATL2_REGS_LEN 42
 	return sizeof(u32) * ATL2_REGS_LEN;
 }
 static void atl2_get_regs(struct net_device *netdev,
 	struct ethtool_regs *regs, void *p)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	struct atl2_hw *hw = &adapter->hw;
 	u32 *regs_buff = p;
 	u16 phy_data;
 	memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
 	regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
 	regs_buff[0]  = ATL2_READ_REG(hw, REG_VPD_CAP);
 	regs_buff[1]  = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
 	regs_buff[2]  = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
 	regs_buff[3]  = ATL2_READ_REG(hw, REG_TWSI_CTRL);
 	regs_buff[4]  = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
 	regs_buff[5]  = ATL2_READ_REG(hw, REG_MASTER_CTRL);
 	regs_buff[6]  = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
 	regs_buff[7]  = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
 	regs_buff[8]  = ATL2_READ_REG(hw, REG_PHY_ENABLE);
 	regs_buff[9]  = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
 	regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
 	regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
 	regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
 	regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
 	regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
 	regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
 	regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
 	regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
 	regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
 	regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
 	regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
 	regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
 	regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
 	regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
 	regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
 	regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
 	regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
 	regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
 	regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
 	regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
 	regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
 	regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
 	regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
 	regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
 	regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
 	regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
 	regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
 	regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
 	regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
 	atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
 	regs_buff[40] = (u32)phy_data;
 	atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
 	regs_buff[41] = (u32)phy_data;
 }
 static int atl2_get_eeprom_len(struct net_device *netdev)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	if (!atl2_check_eeprom_exist(&adapter->hw))
 		return 512;
 	else
 		return 0;
 }
 static int atl2_get_eeprom(struct net_device *netdev,
 	struct ethtool_eeprom *eeprom, u8 *bytes)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	struct atl2_hw *hw = &adapter->hw;
 	u32 *eeprom_buff;
 	int first_dword, last_dword;
 	int ret_val = 0;
 	int i;
 	if (eeprom->len == 0)
 		return -EINVAL;
 	if (atl2_check_eeprom_exist(hw))
 		return -EINVAL;
 	eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 	first_dword = eeprom->offset >> 2;
 	last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
 	eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
 		GFP_KERNEL);
 	if (!eeprom_buff)
 		return -ENOMEM;
 	for (i = first_dword; i < last_dword; i++) {
 		if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword])))
 			return -EIO;
 	}
 	memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
 		eeprom->len);
 	kfree(eeprom_buff);
 	return ret_val;
 }
 static int atl2_set_eeprom(struct net_device *netdev,
 	struct ethtool_eeprom *eeprom, u8 *bytes)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	struct atl2_hw *hw = &adapter->hw;
 	u32 *eeprom_buff;
 	u32 *ptr;
 	int max_len, first_dword, last_dword, ret_val = 0;
 	int i;
 	if (eeprom->len == 0)
 		return -EOPNOTSUPP;
 	if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 		return -EFAULT;
 	max_len = 512;
 	first_dword = eeprom->offset >> 2;
 	last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
 	eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 	if (!eeprom_buff)
 		return -ENOMEM;
 	ptr = (u32 *)eeprom_buff;
 	if (eeprom->offset & 3) {
 		/* need read/modify/write of first changed EEPROM word */
 		/* only the second byte of the word is being modified */
 		if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))
 			return -EIO;
 		ptr++;
 	}
 	if (((eeprom->offset + eeprom->len) & 3)) {
 		/*
 		 * need read/modify/write of last changed EEPROM word
 		 * only the first byte of the word is being modified
 		 */
 		if (!atl2_read_eeprom(hw, last_dword * 4,
 			&(eeprom_buff[last_dword - first_dword])))
 			return -EIO;
 	}
 	/* Device's eeprom is always little-endian, word addressable */
 	memcpy(ptr, bytes, eeprom->len);
 	for (i = 0; i < last_dword - first_dword + 1; i++) {
 		if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))
 			return -EIO;
 	}
 	kfree(eeprom_buff);
 	return ret_val;
 }
 static void atl2_get_drvinfo(struct net_device *netdev,
 	struct ethtool_drvinfo *drvinfo)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	strncpy(drvinfo->driver,  atl2_driver_name, 32);
 	strncpy(drvinfo->version, atl2_driver_version, 32);
 	strncpy(drvinfo->fw_version, "L2", 32);
 	strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
 	drvinfo->n_stats = 0;
 	drvinfo->testinfo_len = 0;
 	drvinfo->regdump_len = atl2_get_regs_len(netdev);
 	drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
 }
 static void atl2_get_wol(struct net_device *netdev,
 	struct ethtool_wolinfo *wol)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	wol->supported = WAKE_MAGIC;
 	wol->wolopts = 0;
 	if (adapter->wol & ATLX_WUFC_EX)
 		wol->wolopts |= WAKE_UCAST;
 	if (adapter->wol & ATLX_WUFC_MC)
 		wol->wolopts |= WAKE_MCAST;
 	if (adapter->wol & ATLX_WUFC_BC)
 		wol->wolopts |= WAKE_BCAST;
 	if (adapter->wol & ATLX_WUFC_MAG)
 		wol->wolopts |= WAKE_MAGIC;
 	if (adapter->wol & ATLX_WUFC_LNKC)
 		wol->wolopts |= WAKE_PHY;
 }
 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
 		return -EOPNOTSUPP;
 	if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST))
 		return -EOPNOTSUPP;
 	/* these settings will always override what we currently have */
 	adapter->wol = 0;
 	if (wol->wolopts & WAKE_MAGIC)
 		adapter->wol |= ATLX_WUFC_MAG;
 	if (wol->wolopts & WAKE_PHY)
 		adapter->wol |= ATLX_WUFC_LNKC;
 	return 0;
 }
 static int atl2_nway_reset(struct net_device *netdev)
 {
 	struct atl2_adapter *adapter = netdev_priv(netdev);
 	if (netif_running(netdev))
 		atl2_reinit_locked(adapter);
 	return 0;
 }
 static struct ethtool_ops atl2_ethtool_ops = {
 	.get_settings		= atl2_get_settings,
 	.set_settings		= atl2_set_settings,
 	.get_drvinfo		= atl2_get_drvinfo,
 	.get_regs_len		= atl2_get_regs_len,
 	.get_regs		= atl2_get_regs,
 	.get_wol		= atl2_get_wol,
 	.set_wol		= atl2_set_wol,
 	.get_msglevel		= atl2_get_msglevel,
 	.set_msglevel		= atl2_set_msglevel,
 	.nway_reset		= atl2_nway_reset,
 	.get_link		= ethtool_op_get_link,
 	.get_eeprom_len		= atl2_get_eeprom_len,
 	.get_eeprom		= atl2_get_eeprom,
 	.set_eeprom		= atl2_set_eeprom,
 	.get_tx_csum		= atl2_get_tx_csum,
 	.get_sg			= ethtool_op_get_sg,
 	.set_sg			= ethtool_op_set_sg,
 #ifdef NETIF_F_TSO
 	.get_tso		= ethtool_op_get_tso,
 #endif
 };
 static void atl2_set_ethtool_ops(struct net_device *netdev)
 {
 	SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
 }
 #define LBYTESWAP(a)  ((((a) & 0x00ff00ff) << 8) | \
 	(((a) & 0xff00ff00) >> 8))
 #define LONGSWAP(a)   ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
 #define SHORTSWAP(a)  (((a) << 8) | ((a) >> 8))
 /*
  * Reset the transmit and receive units; mask and clear all interrupts.
  *
  * hw - Struct containing variables accessed by shared code
  * return : 0  or  idle status (if error)
  */
 static s32 atl2_reset_hw(struct atl2_hw *hw)
 {
 	u32 icr;
 	u16 pci_cfg_cmd_word;
 	int i;
 	/* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
 	atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
 	if ((pci_cfg_cmd_word &
 		(CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
 		(CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
 		pci_cfg_cmd_word |=
 			(CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
 		atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
 	}
 	/* Clear Interrupt mask to stop board from generating
 	 * interrupts & Clear any pending interrupt events
 	 */
 	/* FIXME */
 	/* ATL2_WRITE_REG(hw, REG_IMR, 0); */
 	/* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
 	/* Issue Soft Reset to the MAC.  This will reset the chip's
 	 * transmit, receive, DMA.  It will not effect
 	 * the current PCI configuration.  The global reset bit is self-
 	 * clearing, and should clear within a microsecond.
 	 */
 	ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
 	wmb();
 	msleep(1); /* delay about 1ms */
 	/* Wait at least 10ms for All module to be Idle */
 	for (i = 0; i < 10; i++) {
 		icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
 		if (!icr)
 			break;
 		msleep(1); /* delay 1 ms */
 		cpu_relax();
 	}
 	if (icr)
 		return icr;
 	return 0;
 }
 #define CUSTOM_SPI_CS_SETUP        2
 #define CUSTOM_SPI_CLK_HI          2
 #define CUSTOM_SPI_CLK_LO          2
 #define CUSTOM_SPI_CS_HOLD         2
 #define CUSTOM_SPI_CS_HI           3
 static struct atl2_spi_flash_dev flash_table[] =
 {
 /* MFR    WRSR  READ  PROGRAM WREN  WRDI  RDSR  RDID  SECTOR_ERASE CHIP_ERASE */
 {"Atmel", 0x0,  0x03, 0x02,   0x06, 0x04, 0x05, 0x15, 0x52,        0x62 },
 {"SST",   0x01, 0x03, 0x02,   0x06, 0x04, 0x05, 0x90, 0x20,        0x60 },
 {"ST",    0x01, 0x03, 0x02,   0x06, 0x04, 0x05, 0xAB, 0xD8,        0xC7 },
 };
 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
 {
 	int i;
 	u32 value;
 	ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
 	ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
 	value = SPI_FLASH_CTRL_WAIT_READY |
 		(CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
 			SPI_FLASH_CTRL_CS_SETUP_SHIFT |
 		(CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
 			SPI_FLASH_CTRL_CLK_HI_SHIFT |
 		(CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
 			SPI_FLASH_CTRL_CLK_LO_SHIFT |
 		(CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
 			SPI_FLASH_CTRL_CS_HOLD_SHIFT |
 		(CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
 			SPI_FLASH_CTRL_CS_HI_SHIFT |
 		(0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
 	ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
 	value |= SPI_FLASH_CTRL_START;
 	ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
 	for (i = 0; i < 10; i++) {
 		msleep(1);
 		value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
 		if (!(value & SPI_FLASH_CTRL_START))
 			break;
 	}
 	if (value & SPI_FLASH_CTRL_START)
 		return false;
 	*buf = ATL2_READ_REG(hw, REG_SPI_DATA);
 	return true;
 }
 /*
  * get_permanent_address
  * return 0 if get valid mac address,
  */
 static int get_permanent_address(struct atl2_hw *hw)
 {
 	u32 Addr[2];
 	u32 i, Control;
 	u16 Register;
 	u8  EthAddr[NODE_ADDRESS_SIZE];
 	bool KeyValid;
 	if (is_valid_ether_addr(hw->perm_mac_addr))
 		return 0;
 	Addr[0] = 0;
 	Addr[1] = 0;
 	if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
 		Register = 0;
 		KeyValid = false;
 		/* Read out all EEPROM content */
 		i = 0;
 		while (1) {
 			if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
 				if (KeyValid) {
 					if (Register == REG_MAC_STA_ADDR)
 						Addr[0] = Control;
 					else if (Register ==
 						(REG_MAC_STA_ADDR + 4))
 						Addr[1] = Control;
 					KeyValid = false;
 				} else if ((Control & 0xff) == 0x5A) {
 					KeyValid = true;
 					Register = (u16) (Control >> 16);
 				} else {
 			/* assume data end while encount an invalid KEYWORD */
 					break;
 				}
 			} else {
 				break; /* read error */
 			}
 			i += 4;
 		}
 		*(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
 		*(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
 		if (is_valid_ether_addr(EthAddr)) {
 			memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
 			return 0;
 		}
 		return 1;
 	}
 	/* see if SPI flash exists? */
 	Addr[0] = 0;
 	Addr[1] = 0;
 	Register = 0;
 	KeyValid = false;
 	i = 0;
 	while (1) {
 		if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
 			if (KeyValid) {
 				if (Register == REG_MAC_STA_ADDR)
 					Addr[0] = Control;
 				else if (Register == (REG_MAC_STA_ADDR + 4))
 					Addr[1] = Control;
 				KeyValid = false;
 			} else if ((Control & 0xff) == 0x5A) {
 				KeyValid = true;
 				Register = (u16) (Control >> 16);
 			} else {
 				break; /* data end */
 			}
 		} else {
 			break; /* read error */
 		}
 		i += 4;
 	}
 	*(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
 	*(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
 	if (is_valid_ether_addr(EthAddr)) {
 		memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
 		return 0;
 	}
 	/* maybe MAC-address is from BIOS */
 	Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
 	Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
 	*(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
 	*(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
 	if (is_valid_ether_addr(EthAddr)) {
 		memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
 		return 0;
 	}
 	return 1;
 }
 /*
  * Reads the adapter's MAC address from the EEPROM
  *
  * hw - Struct containing variables accessed by shared code
  */
 static s32 atl2_read_mac_addr(struct atl2_hw *hw)
 {
 	u16 i;
 	if (get_permanent_address(hw)) {
 		/* for test */
 		/* FIXME: shouldn't we use random_ether_addr() here? */
 		hw->perm_mac_addr[0] = 0x00;
 		hw->perm_mac_addr[1] = 0x13;
 		hw->perm_mac_addr[2] = 0x74;
 		hw->perm_mac_addr[3] = 0x00;
 		hw->perm_mac_addr[4] = 0x5c;
 		hw->perm_mac_addr[5] = 0x38;
 	}
 	for (i = 0; i < NODE_ADDRESS_SIZE; i++)
 		hw->mac_addr[i] = hw->perm_mac_addr[i];
 	return 0;
 }
 /*
  * Hashes an address to determine its location in the multicast table
  *
  * hw - Struct containing variables accessed by shared code
  * mc_addr - the multicast address to hash
  *
  * atl2_hash_mc_addr
  *  purpose
  *      set hash value for a multicast address
  *      hash calcu processing :
  *          1. calcu 32bit CRC for multicast address
  *          2. reverse crc with MSB to LSB
  */
 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
 {
 	u32 crc32, value;
 	int i;
 	value = 0;
 	crc32 = ether_crc_le(6, mc_addr);
 	for (i = 0; i < 32; i++)
 		value |= (((crc32 >> i) & 1) << (31 - i));
 	return value;
 }
 /*
  * Sets the bit in the multicast table corresponding to the hash value.
  *
  * hw - Struct containing variables accessed by shared code
  * hash_value - Multicast address hash value
  */
 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
 {
 	u32 hash_bit, hash_reg;
 	u32 mta;
 	/* The HASH Table  is a register array of 2 32-bit registers.
 	 * It is treated like an array of 64 bits.  We want to set
 	 * bit BitArray[hash_value]. So we figure out what register
 	 * the bit is in, read it, OR in the new bit, then write
 	 * back the new value.  The register is determined by the
 	 * upper 7 bits of the hash value and the bit within that
 	 * register are determined by the lower 5 bits of the value.
 	 */
 	hash_reg = (hash_value >> 31) & 0x1;
 	hash_bit = (hash_value >> 26) & 0x1F;
 	mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
 	mta |= (1 << hash_bit);
 	ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
 }
 /*
  * atl2_init_pcie - init PCIE module
  */
 static void atl2_init_pcie(struct atl2_hw *hw)
 {
     u32 value;
     value = LTSSM_TEST_MODE_DEF;
     ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
     value = PCIE_DLL_TX_CTRL1_DEF;
     ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
 }
 static void atl2_init_flash_opcode(struct atl2_hw *hw)
 {
 	if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
 		hw->flash_vendor = 0; /* ATMEL */
 	/* Init OP table */
 	ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
 		flash_table[hw->flash_vendor].cmdPROGRAM);
 	ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
 		flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
 	ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
 		flash_table[hw->flash_vendor].cmdCHIP_ERASE);
 	ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
 		flash_table[hw->flash_vendor].cmdRDID);
 	ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
 		flash_table[hw->flash_vendor].cmdWREN);
 	ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
 		flash_table[hw->flash_vendor].cmdRDSR);
 	ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
 		flash_table[hw->flash_vendor].cmdWRSR);
 	ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
 		flash_table[hw->flash_vendor].cmdREAD);
 }
 /********************************************************************
 * Performs basic configuration of the adapter.
 *
 * hw - Struct containing variables accessed by shared code
 * Assumes that the controller has previously been reset and is in a
 * post-reset uninitialized state. Initializes multicast table,
 * and  Calls routines to setup link
 * Leaves the transmit and receive units disabled and uninitialized.
 ********************************************************************/
 static s32 atl2_init_hw(struct atl2_hw *hw)
 {
 	u32 ret_val = 0;
 	atl2_init_pcie(hw);
 	/* Zero out the Multicast HASH table */
 	/* clear the old settings from the multicast hash table */
 	ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
 	ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
 	atl2_init_flash_opcode(hw);
 	ret_val = atl2_phy_init(hw);
 	return ret_val;
 }
 /*
  * Detects the current speed and duplex settings of the hardware.
  *
  * hw - Struct containing variables accessed by shared code
  * speed - Speed of the connection
  * duplex - Duplex setting of the connection
  */
 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
 	u16 *duplex)
 {
 	s32 ret_val;
 	u16 phy_data;
 	/* Read PHY Specific Status Register (17) */
 	ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
 	if (ret_val)
 		return ret_val;
 	if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
 		return ATLX_ERR_PHY_RES;
 	switch (phy_data & MII_ATLX_PSSR_SPEED) {
 	case MII_ATLX_PSSR_100MBS:
 		*speed = SPEED_100;
 		break;
 	case MII_ATLX_PSSR_10MBS:
 		*speed = SPEED_10;
 		break;
 	default:
 		return ATLX_ERR_PHY_SPEED;
 		break;
 	}
 	if (phy_data & MII_ATLX_PSSR_DPLX)
 		*duplex = FULL_DUPLEX;
 	else
 		*duplex = HALF_DUPLEX;
 	return 0;
 }
 /*
  * Reads the value from a PHY register
  * hw - Struct containing variables accessed by shared code
  * reg_addr - address of the PHY register to read
  */
 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
 {
 	u32 val;
 	int i;
 	val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
 		MDIO_START |
 		MDIO_SUP_PREAMBLE |
 		MDIO_RW |
 		MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
 	ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
 	wmb();
 	for (i = 0; i < MDIO_WAIT_TIMES; i++) {
 		udelay(2);
 		val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
 		if (!(val & (MDIO_START | MDIO_BUSY)))
 			break;
 		wmb();
 	}
 	if (!(val & (MDIO_START | MDIO_BUSY))) {
 		*phy_data = (u16)val;
 		return 0;
 	}
 	return ATLX_ERR_PHY;
 }
 /*
  * Writes a value to a PHY register
  * hw - Struct containing variables accessed by shared code
  * reg_addr - address of the PHY register to write
  * data - data to write to the PHY
  */
 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
 {
 	int i;
 	u32 val;
 	val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
 		(reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
 		MDIO_SUP_PREAMBLE |
 		MDIO_START |
 		MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
 	ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
 	wmb();
 	for (i = 0; i < MDIO_WAIT_TIMES; i++) {
 		udelay(2);
 		val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
 		if (!(val & (MDIO_START | MDIO_BUSY)))
 			break;
 		wmb();
 	}
 	if (!(val & (MDIO_START | MDIO_BUSY)))
 		return 0;
 	return ATLX_ERR_PHY;
 }
 /*
  * Configures PHY autoneg and flow control advertisement settings
  *
  * hw - Struct containing variables accessed by shared code
  */
 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
 {
 	s32 ret_val;
 	s16 mii_autoneg_adv_reg;
 	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
 	mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
 	/* Need to parse autoneg_advertised  and set up
 	 * the appropriate PHY registers.  First we will parse for
 	 * autoneg_advertised software override.  Since we can advertise
 	 * a plethora of combinations, we need to check each bit
 	 * individually.
 	 */
 	/* First we clear all the 10/100 mb speed bits in the Auto-Neg
 	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
 	 * the  1000Base-T Control Register (Address 9). */
 	mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
 	/* Need to parse MediaType and setup the
 	 * appropriate PHY registers. */
 	switch (hw->MediaType) {
 	case MEDIA_TYPE_AUTO_SENSOR:
 		mii_autoneg_adv_reg |=
 			(MII_AR_10T_HD_CAPS |
 			MII_AR_10T_FD_CAPS  |
 			MII_AR_100TX_HD_CAPS|
 			MII_AR_100TX_FD_CAPS);
 		hw->autoneg_advertised =
 			ADVERTISE_10_HALF |
 			ADVERTISE_10_FULL |
 			ADVERTISE_100_HALF|
 			ADVERTISE_100_FULL;
 		break;
 	case MEDIA_TYPE_100M_FULL:
 		mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
 		hw->autoneg_advertised = ADVERTISE_100_FULL;
 		break;
 	case MEDIA_TYPE_100M_HALF:
 		mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
 		hw->autoneg_advertised = ADVERTISE_100_HALF;
 		break;
 	case MEDIA_TYPE_10M_FULL:
 		mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
 		hw->autoneg_advertised = ADVERTISE_10_FULL;
 		break;
 	default:
 		mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
 		hw->autoneg_advertised = ADVERTISE_10_HALF;
 		break;
 	}
 	/* flow control fixed to enable all */
 	mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
 	hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
 	ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
 	if (ret_val)
 		return ret_val;
 	return 0;
 }
 /*
  * Resets the PHY and make all config validate
  *
  * hw - Struct containing variables accessed by shared code
  *
  * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
  */
 static s32 atl2_phy_commit(struct atl2_hw *hw)
 {
 	s32 ret_val;
 	u16 phy_data;
 	phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
 	ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
 	if (ret_val) {
 		u32 val;
 		int i;
 		/* pcie serdes link may be down ! */
 		for (i = 0; i < 25; i++) {
 			msleep(1);
 			val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
 			if (!(val & (MDIO_START | MDIO_BUSY)))
 				break;
 		}
 		if (0 != (val & (MDIO_START | MDIO_BUSY))) {
 			printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
 			return ret_val;
 		}
 	}
 	return 0;
 }
 static s32 atl2_phy_init(struct atl2_hw *hw)
 {
 	s32 ret_val;
 	u16 phy_val;
 	if (hw->phy_configured)
 		return 0;
 	/* Enable PHY */
 	ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
 	ATL2_WRITE_FLUSH(hw);
 	msleep(1);
 	/* check if the PHY is in powersaving mode */
 	atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
 	atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
 	/* 024E / 124E 0r 0274 / 1274 ? */
 	if (phy_val & 0x1000) {
 		phy_val &= ~0x1000;
 		atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
 	}
 	msleep(1);
 	/*Enable PHY LinkChange Interrupt */
 	ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
 	if (ret_val)
 		return ret_val;
 	/* setup AutoNeg parameters */
 	ret_val = atl2_phy_setup_autoneg_adv(hw);
 	if (ret_val)
 		return ret_val;
 	/* SW.Reset & En-Auto-Neg to restart Auto-Neg */
 	ret_val = atl2_phy_commit(hw);
 	if (ret_val)
 		return ret_val;
 	hw->phy_configured = true;
 	return ret_val;
 }
 static void atl2_set_mac_addr(struct atl2_hw *hw)
 {
 	u32 value;
 	/* 00-0B-6A-F6-00-DC
 	 * 0:  6AF600DC   1: 000B
 	 * low dword */
 	value = (((u32)hw->mac_addr[2]) << 24) |
 		(((u32)hw->mac_addr[3]) << 16) |
 		(((u32)hw->mac_addr[4]) << 8)  |
 		(((u32)hw->mac_addr[5]));
 	ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
 	/* hight dword */
 	value = (((u32)hw->mac_addr[0]) << 8) |
 		(((u32)hw->mac_addr[1]));
 	ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
 }
 /*
  * check_eeprom_exist
  * return 0 if eeprom exist
  */
 static int atl2_check_eeprom_exist(struct atl2_hw *hw)
 {
 	u32 value;
 	value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
 	if (value & SPI_FLASH_CTRL_EN_VPD) {
 		value &= ~SPI_FLASH_CTRL_EN_VPD;
 		ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
 	}
 	value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
 	return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
 }
 /* FIXME: This doesn't look right. -- CHS */
 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
 {
 	return true;
 }
 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
 {
 	int i;
 	u32    Control;
 	if (Offset & 0x3)
 		return false; /* address do not align */
 	ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
 	Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
 	ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
 	for (i = 0; i < 10; i++) {
 		msleep(2);
 		Control = ATL2_READ_REG(hw, REG_VPD_CAP);
 		if (Control & VPD_CAP_VPD_FLAG)
 			break;
 	}
 	if (Control & VPD_CAP_VPD_FLAG) {
 		*pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
 		return true;
 	}
 	return false; /* timeout */
 }
 static void atl2_force_ps(struct atl2_hw *hw)
 {
 	u16 phy_val;
 	atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
 	atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
 	atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
 	atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
 	atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
 	atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
 	atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
 }
 /* This is the only thing that needs to be changed to adjust the
  * maximum number of ports that the driver can manage.
  */
 #define ATL2_MAX_NIC 4
 #define OPTION_UNSET    -1
 #define OPTION_DISABLED 0
 #define OPTION_ENABLED  1
 /* All parameters are treated the same, as an integer array of values.
  * This macro just reduces the need to repeat the same declaration code
  * over and over (plus this helps to avoid typo bugs).
  */
 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
 #ifndef module_param_array
 /* Module Parameters are always initialized to -1, so that the driver
  * can tell the difference between no user specified value or the
  * user asking for the default value.
  * The true default values are loaded in when atl2_check_options is called.
  *
  * This is a GCC extension to ANSI C.
  * See the item "Labeled Elements in Initializers" in the section
  * "Extensions to the C Language Family" of the GCC documentation.
  */
 #define ATL2_PARAM(X, desc) \
     static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
     MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
     MODULE_PARM_DESC(X, desc);
 #else
 #define ATL2_PARAM(X, desc) \
     static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
     static int num_##X = 0; \
     module_param_array_named(X, X, int, &num_##X, 0); \
     MODULE_PARM_DESC(X, desc);
 #endif
 /*
  * Transmit Memory Size
  * Valid Range: 64-2048
  * Default Value: 128
  */
 #define ATL2_MIN_TX_MEMSIZE		4	/* 4KB */
 #define ATL2_MAX_TX_MEMSIZE		64	/* 64KB */
 #define ATL2_DEFAULT_TX_MEMSIZE		8	/* 8KB */
 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
 /*
  * Receive Memory Block Count
  * Valid Range: 16-512
  * Default Value: 128
  */
 #define ATL2_MIN_RXD_COUNT		16
 #define ATL2_MAX_RXD_COUNT		512
 #define ATL2_DEFAULT_RXD_COUNT		64
 ATL2_PARAM(RxMemBlock, "Number of receive memory block");
 /*
  * User Specified MediaType Override
  *
  * Valid Range: 0-5
  *  - 0    - auto-negotiate at all supported speeds
  *  - 1    - only link at 1000Mbps Full Duplex
  *  - 2    - only link at 100Mbps Full Duplex
  *  - 3    - only link at 100Mbps Half Duplex
  *  - 4    - only link at 10Mbps Full Duplex
  *  - 5    - only link at 10Mbps Half Duplex
  * Default Value: 0
  */
 ATL2_PARAM(MediaType, "MediaType Select");
 /*
  * Interrupt Moderate Timer in units of 2048 ns (~2 us)
  * Valid Range: 10-65535
  * Default Value: 45000(90ms)
  */
 #define INT_MOD_DEFAULT_CNT	100 /* 200us */
 #define INT_MOD_MAX_CNT		65000
 #define INT_MOD_MIN_CNT		50
 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
 /*
  * FlashVendor
  * Valid Range: 0-2
  * 0 - Atmel
  * 1 - SST
  * 2 - ST
  */
 ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
 #define AUTONEG_ADV_DEFAULT	0x2F
 #define AUTONEG_ADV_MASK	0x2F
 #define FLOW_CONTROL_DEFAULT	FLOW_CONTROL_FULL
 #define FLASH_VENDOR_DEFAULT	0
 #define FLASH_VENDOR_MIN	0
 #define FLASH_VENDOR_MAX	2
 struct atl2_option {
 	enum { enable_option, range_option, list_option } type;
 	char *name;
 	char *err;
 	int  def;
 	union {
 		struct { /* range_option info */
 			int min;
 			int max;
 		} r;
 		struct { /* list_option info */
 			int nr;
 			struct atl2_opt_list { int i; char *str; } *p;
 		} l;
 	} arg;
 };
 static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
 {
 	int i;
 	struct atl2_opt_list *ent;
 	if (*value == OPTION_UNSET) {
 		*value = opt->def;
 		return 0;
 	}
 	switch (opt->type) {
 	case enable_option:
 		switch (*value) {
 		case OPTION_ENABLED:
 			printk(KERN_INFO "%s Enabled\n", opt->name);
 			return 0;
 			break;
 		case OPTION_DISABLED:
 			printk(KERN_INFO "%s Disabled\n", opt->name);
 			return 0;
 			break;
 		}
 		break;
 	case range_option:
 		if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
 			printk(KERN_INFO "%s set to %i\n", opt->name, *value);
 			return 0;
 		}
 		break;
 	case list_option:
 		for (i = 0; i < opt->arg.l.nr; i++) {
 			ent = &opt->arg.l.p[i];
 			if (*value == ent->i) {
 				if (ent->str[0] != '\0')
 					printk(KERN_INFO "%s\n", ent->str);
 			return 0;
 			}
 		}
 		break;
 	default:
 		BUG();
 	}
 	printk(KERN_INFO "Invalid %s specified (%i) %s\n",
 		opt->name, *value, opt->err);
 	*value = opt->def;
 	return -1;
 }
 /*
  * atl2_check_options - Range Checking for Command Line Parameters
  * @adapter: board private structure
  *
  * This routine checks all command line parameters for valid user
  * input.  If an invalid value is given, or if no user specified
  * value exists, a default value is used.  The final value is stored
  * in a variable in the adapter structure.
  */
 static void __devinit atl2_check_options(struct atl2_adapter *adapter)
 {
 	int val;
 	struct atl2_option opt;
 	int bd = adapter->bd_number;
 	if (bd >= ATL2_MAX_NIC) {
 		printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
 			bd);
 		printk(KERN_NOTICE "Using defaults for all values\n");
 #ifndef module_param_array
 		bd = ATL2_MAX_NIC;
 #endif
 	}
 	/* Bytes of Transmit Memory */
 	opt.type = range_option;
 	opt.name = "Bytes of Transmit Memory";
 	opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
 	opt.def = ATL2_DEFAULT_TX_MEMSIZE;
 	opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
 	opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
 #ifdef module_param_array
 	if (num_TxMemSize > bd) {
 #endif
 		val = TxMemSize[bd];
 		atl2_validate_option(&val, &opt);
 		adapter->txd_ring_size = ((u32) val) * 1024;
 #ifdef module_param_array
 	} else
 		adapter->txd_ring_size = ((u32)opt.def) * 1024;
 #endif
 	/* txs ring size: */
 	adapter->txs_ring_size = adapter->txd_ring_size / 128;
 	if (adapter->txs_ring_size > 160)
 		adapter->txs_ring_size = 160;
 	/* Receive Memory Block Count */
 	opt.type = range_option;
 	opt.name = "Number of receive memory block";
 	opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
 	opt.def = ATL2_DEFAULT_RXD_COUNT;
 	opt.arg.r.min = ATL2_MIN_RXD_COUNT;
 	opt.arg.r.max = ATL2_MAX_RXD_COUNT;
 #ifdef module_param_array
 	if (num_RxMemBlock > bd) {
 #endif
 		val = RxMemBlock[bd];
 		atl2_validate_option(&val, &opt);
 		adapter->rxd_ring_size = (u32)val;
 		/* FIXME */
 		/* ((u16)val)&~1; */	/* even number */
 #ifdef module_param_array
 	} else
 		adapter->rxd_ring_size = (u32)opt.def;
 #endif
 	/* init RXD Flow control value */
 	adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
 	adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
 		(adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
 		(adapter->rxd_ring_size / 12);
 	/* Interrupt Moderate Timer */
 	opt.type = range_option;
 	opt.name = "Interrupt Moderate Timer";
 	opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
 	opt.def = INT_MOD_DEFAULT_CNT;
 	opt.arg.r.min = INT_MOD_MIN_CNT;
 	opt.arg.r.max = INT_MOD_MAX_CNT;
 #ifdef module_param_array
 	if (num_IntModTimer > bd) {
 #endif
 		val = IntModTimer[bd];
 		atl2_validate_option(&val, &opt);
 		adapter->imt = (u16) val;
 #ifdef module_param_array
 	} else
 		adapter->imt = (u16)(opt.def);
 #endif
 	/* Flash Vendor */
 	opt.type = range_option;
 	opt.name = "SPI Flash Vendor";
 	opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
 	opt.def = FLASH_VENDOR_DEFAULT;
 	opt.arg.r.min = FLASH_VENDOR_MIN;
 	opt.arg.r.max = FLASH_VENDOR_MAX;
 #ifdef module_param_array
 	if (num_FlashVendor > bd) {
 #endif
 		val = FlashVendor[bd];
 		atl2_validate_option(&val, &opt);
 		adapter->hw.flash_vendor = (u8) val;
 #ifdef module_param_array
 	} else
 		adapter->hw.flash_vendor = (u8)(opt.def);
 #endif
 	/* MediaType */
 	opt.type = range_option;
 	opt.name = "Speed/Duplex Selection";
 	opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
 	opt.def = MEDIA_TYPE_AUTO_SENSOR;
 	opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
 	opt.arg.r.max = MEDIA_TYPE_10M_HALF;
 #ifdef module_param_array
 	if (num_MediaType > bd) {
 #endif
 		val = MediaType[bd];
 		atl2_validate_option(&val, &opt);
 		adapter->hw.MediaType = (u16) val;
 #ifdef module_param_array
 	} else
 		adapter->hw.MediaType = (u16)(opt.def);
 #endif
 }