Doug / smarc-fsl-linux-kernel | Embedian Git Server

Commit a28d3af2a26c89aaa6470ca36edb212e05143d67

Authored by Benjamin Herrenschmidt 2006-01-07 08:35:26 +0800

Committed by Paul Mackerras 2006-01-09 12:47:17 +0800

Exists in master and in 7 other branches

[PATCH] 2/5 powerpc: Rework PowerMac i2c part 2

This is the continuation of the previous patch. This one removes the old
PowerMac i2c drivers (i2c-keywest and i2c-pmac-smu) and replaces them
both with a single stub driver that uses the new PowerMac low i2c layer.

Now that i2c-keywest is gone, the low-i2c code is extended to support
interrupt driver transfers. All i2c busses now appear as platform
devices. Compatibility with existing drivers should be maintained as the
i2c bus names have been kept identical, except for the SMU bus but in
that later case, all users has been fixed.

With that patch added, matching a device node to an i2c_adapter becomes
trivial.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

Showing 12 changed files with 563 additions and 1364 deletions Inline Diff

arch/powerpc/platforms/powermac/low_i2c.c
arch/powerpc/platforms/powermac/setup.c
drivers/i2c/busses/Kconfig
drivers/i2c/busses/Makefile
drivers/i2c/busses/i2c-keywest.c
drivers/i2c/busses/i2c-keywest.h
drivers/i2c/busses/i2c-pmac-smu.c
drivers/i2c/busses/i2c-powermac.c
drivers/macintosh/Kconfig
drivers/macintosh/smu.c
drivers/macintosh/windfarm_lm75_sensor.c
include/asm-powerpc/pmac_low_i2c.h

arch/powerpc/platforms/powermac/low_i2c.c

Diff comments View file @ a28d3af

 /*
  * arch/powerpc/platforms/powermac/low_i2c.c
  *
  *  Copyright (C) 2003-2005 Ben. Herrenschmidt (benh@kernel.crashing.org)
  *
  *  This program is free software; you can redistribute it and/or
  *  modify it under the terms of the GNU General Public License
  *  as published by the Free Software Foundation; either version
  *  2 of the License, or (at your option) any later version.
  *
  * The linux i2c layer isn't completely suitable for our needs for various
  * reasons ranging from too late initialisation to semantics not perfectly
  * matching some requirements of the apple platform functions etc...
  *
  * This file thus provides a simple low level unified i2c interface for
  * powermac that covers the various types of i2c busses used in Apple machines.
  * For now, keywest, PMU and SMU, though we could add Cuda, or other bit
  * banging busses found on older chipstes in earlier machines if we ever need
  * one of them.
  *
  * The drivers in this file are synchronous/blocking. In addition, the
  * keywest one is fairly slow due to the use of msleep instead of interrupts
  * as the interrupt is currently used by i2c-keywest. In the long run, we
  * might want to get rid of those high-level interfaces to linux i2c layer
  * either completely (converting all drivers) or replacing them all with a
  * single stub driver on top of this one. Once done, the interrupt will be
  * available for our use.
  */
 #undef DEBUG
 #undef DEBUG_LOW
 #include <linux/config.h>
 #include <linux/types.h>
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/adb.h>
 #include <linux/pmu.h>
 #include <linux/delay.h>
 #include <linux/completion.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/timer.h>
 #include <asm/keylargo.h>
 #include <asm/uninorth.h>
 #include <asm/io.h>
 #include <asm/prom.h>
 #include <asm/machdep.h>
 #include <asm/smu.h>
 #include <asm/pmac_low_i2c.h>
 #ifdef DEBUG
 #define DBG(x...) do {\
 		printk(KERN_DEBUG "low_i2c:" x);	\
 	} while(0)
 #else
 #define DBG(x...)
 #endif
 #ifdef DEBUG_LOW
 #define DBG_LOW(x...) do {\
 		printk(KERN_DEBUG "low_i2c:" x);	\
 	} while(0)
 #else
 #define DBG_LOW(x...)
 #endif
+static int pmac_i2c_force_poll = 1;
 /*
  * A bus structure. Each bus in the system has such a structure associated.
  */
 struct pmac_i2c_bus
 {
 	struct list_head	link;
 	struct device_node	*controller;
 	struct device_node	*busnode;
 	int			type;
 	int			flags;
 	struct i2c_adapter	*adapter;
 	void			*hostdata;
 	int			channel;	/* some hosts have multiple */
 	int			mode;		/* current mode */
 	struct semaphore	sem;
 	int			opened;
 	int			polled;		/* open mode */
+	struct platform_device	*platform_dev;
 	/* ops */
 	int (*open)(struct pmac_i2c_bus *bus);
 	void (*close)(struct pmac_i2c_bus *bus);
 	int (*xfer)(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
 		    u32 subaddr, u8 *data, int len);
 };
 static LIST_HEAD(pmac_i2c_busses);
 /*
  * Keywest implementation
  */
 struct pmac_i2c_host_kw
 {
 	struct semaphore	mutex;		/* Access mutex for use by
 						 * i2c-keywest */
 	void __iomem		*base;		/* register base address */
 	int			bsteps;		/* register stepping */
 	int			speed;		/* speed */
+	int			irq;
+	u8			*data;
+	unsigned		len;
+	int			state;
+	int			rw;
+	int			polled;
+	int			result;
+	struct completion	complete;
+	spinlock_t		lock;
+	struct timer_list	timeout_timer;
 };
 /* Register indices */
 typedef enum {
 	reg_mode = 0,
 	reg_control,
 	reg_status,
 	reg_isr,
 	reg_ier,
 	reg_addr,
 	reg_subaddr,
 	reg_data
 } reg_t;
+/* The Tumbler audio equalizer can be really slow sometimes */
+#define KW_POLL_TIMEOUT		(2*HZ)
 /* Mode register */
 #define KW_I2C_MODE_100KHZ	0x00
 #define KW_I2C_MODE_50KHZ	0x01
 #define KW_I2C_MODE_25KHZ	0x02
 #define KW_I2C_MODE_DUMB	0x00
 #define KW_I2C_MODE_STANDARD	0x04
 #define KW_I2C_MODE_STANDARDSUB	0x08
 #define KW_I2C_MODE_COMBINED	0x0C
 #define KW_I2C_MODE_MODE_MASK	0x0C
 #define KW_I2C_MODE_CHAN_MASK	0xF0
 /* Control register */
 #define KW_I2C_CTL_AAK		0x01
 #define KW_I2C_CTL_XADDR	0x02
 #define KW_I2C_CTL_STOP		0x04
 #define KW_I2C_CTL_START	0x08
 /* Status register */
 #define KW_I2C_STAT_BUSY	0x01
 #define KW_I2C_STAT_LAST_AAK	0x02
 #define KW_I2C_STAT_LAST_RW	0x04
 #define KW_I2C_STAT_SDA		0x08
 #define KW_I2C_STAT_SCL		0x10
 /* IER & ISR registers */
 #define KW_I2C_IRQ_DATA		0x01
 #define KW_I2C_IRQ_ADDR		0x02
 #define KW_I2C_IRQ_STOP		0x04
 #define KW_I2C_IRQ_START	0x08
 #define KW_I2C_IRQ_MASK		0x0F
 /* State machine states */
 enum {
 	state_idle,
 	state_addr,
 	state_read,
 	state_write,
 	state_stop,
 	state_dead
 };
 #define WRONG_STATE(name) do {\
-		printk(KERN_DEBUG "KW: wrong state. Got %s, state: %s (isr: %02x)\n", \
+		printk(KERN_DEBUG "KW: wrong state. Got %s, state: %s " \
-		       name, __kw_state_names[state], isr); \
+		       "(isr: %02x)\n",	\
+		       name, __kw_state_names[host->state], isr); \
 	} while(0)
 static const char *__kw_state_names[] = {
 	"state_idle",
 	"state_addr",
 	"state_read",
 	"state_write",
 	"state_stop",
 	"state_dead"
 };
-static inline u8 __kw_read_reg(struct pmac_i2c_bus *bus, reg_t reg)
+static inline u8 __kw_read_reg(struct pmac_i2c_host_kw *host, reg_t reg)
 {
-	struct pmac_i2c_host_kw *host = bus->hostdata;
 	return readb(host->base + (((unsigned int)reg) << host->bsteps));
 }
-static inline void __kw_write_reg(struct pmac_i2c_bus *bus, reg_t reg, u8 val)
+static inline void __kw_write_reg(struct pmac_i2c_host_kw *host,
+				  reg_t reg, u8 val)
 {
-	struct pmac_i2c_host_kw *host = bus->hostdata;
 	writeb(val, host->base + (((unsigned)reg) << host->bsteps));
-	(void)__kw_read_reg(bus, reg_subaddr);
+	(void)__kw_read_reg(host, reg_subaddr);
 }
-#define kw_write_reg(reg, val)	__kw_write_reg(bus, reg, val)
+#define kw_write_reg(reg, val)	__kw_write_reg(host, reg, val)
-#define kw_read_reg(reg)	__kw_read_reg(bus, reg)
+#define kw_read_reg(reg)	__kw_read_reg(host, reg)
-static u8 kw_i2c_wait_interrupt(struct pmac_i2c_bus* bus)
+static u8 kw_i2c_wait_interrupt(struct pmac_i2c_host_kw *host)
 {
 	int i, j;
 	u8 isr;
 	for (i = 0; i < 1000; i++) {
 		isr = kw_read_reg(reg_isr) & KW_I2C_IRQ_MASK;
 		if (isr != 0)
 			return isr;
 		/* This code is used with the timebase frozen, we cannot rely
 		 * on udelay nor schedule when in polled mode !
 		 * For now, just use a bogus loop....
 		 */
-		if (bus->polled) {
+		if (host->polled) {
-			for (j = 1; j < 1000000; j++)
+			for (j = 1; j < 100000; j++)
 				mb();
 		} else
 			msleep(1);
 	}
 	return isr;
 }
-static int kw_i2c_handle_interrupt(struct pmac_i2c_bus *bus, int state, int rw,
+static void kw_i2c_handle_interrupt(struct pmac_i2c_host_kw *host, u8 isr)
-				   int *rc, u8 **data, int *len, u8 isr)
 {
 	u8 ack;
 	DBG_LOW("kw_handle_interrupt(%s, isr: %x)\n",
-		__kw_state_names[state], isr);
+		__kw_state_names[host->state], isr);
+	if (host->state == state_idle) {
+		printk(KERN_WARNING "low_i2c: Keywest got an out of state"
+		       " interrupt, ignoring\n");
+		kw_write_reg(reg_isr, isr);
+		return;
+	}
 	if (isr == 0) {
-		if (state != state_stop) {
+		if (host->state != state_stop) {
 			DBG_LOW("KW: Timeout !\n");
-			*rc = -EIO;
+			host->result = -EIO;
 			goto stop;
 		}
-		if (state == state_stop) {
+		if (host->state == state_stop) {
 			ack = kw_read_reg(reg_status);
-			if (!(ack & KW_I2C_STAT_BUSY)) {
+			if (ack & KW_I2C_STAT_BUSY)
-				state = state_idle;
+				kw_write_reg(reg_status, 0);
-				kw_write_reg(reg_ier, 0x00);
+			host->state = state_idle;
-			}
+			kw_write_reg(reg_ier, 0x00);
+			if (!host->polled)
+				complete(&host->complete);
 		}
-		return state;
+		return;
 	}
 	if (isr & KW_I2C_IRQ_ADDR) {
 		ack = kw_read_reg(reg_status);
-		if (state != state_addr) {
+		if (host->state != state_addr) {
 			kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
 			WRONG_STATE("KW_I2C_IRQ_ADDR");
-			*rc = -EIO;
+			host->result = -EIO;
 			goto stop;
 		}
 		if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
-			*rc = -ENODEV;
+			host->result = -ENODEV;
 			DBG_LOW("KW: NAK on address\n");
-			return state_stop;
+			host->state = state_stop;
+			return;
 		} else {
-			if (rw) {
+			if (host->len == 0) {
-				state = state_read;
+				kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
-				if (*len > 1)
+				goto stop;
+			}
+			if (host->rw) {
+				host->state = state_read;
+				if (host->len > 1)
 					kw_write_reg(reg_control,
 						     KW_I2C_CTL_AAK);
 			} else {
-				state = state_write;
+				host->state = state_write;
-				kw_write_reg(reg_data, **data);
+				kw_write_reg(reg_data, *(host->data++));
-				(*data)++; (*len)--;
+				host->len--;
 			}
 		}
 		kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
 	}
 	if (isr & KW_I2C_IRQ_DATA) {
-		if (state == state_read) {
+		if (host->state == state_read) {
-			**data = kw_read_reg(reg_data);
+			*(host->data++) = kw_read_reg(reg_data);
-			(*data)++; (*len)--;
+			host->len--;
 			kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
-			if ((*len) == 0)
+			if (host->len == 0)
-				state = state_stop;
+				host->state = state_stop;
-			else if ((*len) == 1)
+			else if (host->len == 1)
 				kw_write_reg(reg_control, 0);
-		} else if (state == state_write) {
+		} else if (host->state == state_write) {
 			ack = kw_read_reg(reg_status);
 			if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
 				DBG_LOW("KW: nack on data write\n");
-				*rc = -EIO;
+				host->result = -EIO;
 				goto stop;
-			} else if (*len) {
+			} else if (host->len) {
-				kw_write_reg(reg_data, **data);
+				kw_write_reg(reg_data, *(host->data++));
-				(*data)++; (*len)--;
+				host->len--;
 			} else {
 				kw_write_reg(reg_control, KW_I2C_CTL_STOP);
-				state = state_stop;
+				host->state = state_stop;
-				*rc = 0;
+				host->result = 0;
 			}
 			kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
 		} else {
 			kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
 			WRONG_STATE("KW_I2C_IRQ_DATA");
-			if (state != state_stop) {
+			if (host->state != state_stop) {
-				*rc = -EIO;
+				host->result = -EIO;
 				goto stop;
 			}
 		}
 	}
 	if (isr & KW_I2C_IRQ_STOP) {
 		kw_write_reg(reg_isr, KW_I2C_IRQ_STOP);
-		if (state != state_stop) {
+		if (host->state != state_stop) {
 			WRONG_STATE("KW_I2C_IRQ_STOP");
-			*rc = -EIO;
+			host->result = -EIO;
 		}
-		return state_idle;
+		host->state = state_idle;
+		if (!host->polled)
+			complete(&host->complete);
 	}
 	if (isr & KW_I2C_IRQ_START)
 		kw_write_reg(reg_isr, KW_I2C_IRQ_START);
-	return state;
+	return;
  stop:
 	kw_write_reg(reg_control, KW_I2C_CTL_STOP);
-	return state_stop;
+	host->state = state_stop;
+	return;
 }
+/* Interrupt handler */
+static irqreturn_t kw_i2c_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+	struct pmac_i2c_host_kw *host = dev_id;
+	unsigned long flags;
+	spin_lock_irqsave(&host->lock, flags);
+	del_timer(&host->timeout_timer);
+	kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
+	if (host->state != state_idle) {
+		host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
+		add_timer(&host->timeout_timer);
+	}
+	spin_unlock_irqrestore(&host->lock, flags);
+	return IRQ_HANDLED;
+}
+static void kw_i2c_timeout(unsigned long data)
+{
+	struct pmac_i2c_host_kw *host = (struct pmac_i2c_host_kw *)data;
+	unsigned long flags;
+	spin_lock_irqsave(&host->lock, flags);
+	kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
+	if (host->state != state_idle) {
+		host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
+		add_timer(&host->timeout_timer);
+	}
+	spin_unlock_irqrestore(&host->lock, flags);
+}
 static int kw_i2c_open(struct pmac_i2c_bus *bus)
 {
 	struct pmac_i2c_host_kw *host = bus->hostdata;
 	down(&host->mutex);
 	return 0;
 }
 static void kw_i2c_close(struct pmac_i2c_bus *bus)
 {
 	struct pmac_i2c_host_kw *host = bus->hostdata;
 	up(&host->mutex);
 }
 static int kw_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
 		       u32 subaddr, u8 *data, int len)
 {
 	struct pmac_i2c_host_kw *host = bus->hostdata;
 	u8 mode_reg = host->speed;
-	int state = state_addr;
+	int use_irq = host->irq != NO_IRQ && !bus->polled;
-	int rc = 0;
 	/* Setup mode & subaddress if any */
 	switch(bus->mode) {
 	case pmac_i2c_mode_dumb:
 		return -EINVAL;
 	case pmac_i2c_mode_std:
 		mode_reg |= KW_I2C_MODE_STANDARD;
 		if (subsize != 0)
 			return -EINVAL;
 		break;
 	case pmac_i2c_mode_stdsub:
 		mode_reg |= KW_I2C_MODE_STANDARDSUB;
 		if (subsize != 1)
 			return -EINVAL;
 		break;
 	case pmac_i2c_mode_combined:
 		mode_reg |= KW_I2C_MODE_COMBINED;
 		if (subsize != 1)
 			return -EINVAL;
 		break;
 	}
 	/* Setup channel & clear pending irqs */
 	kw_write_reg(reg_isr, kw_read_reg(reg_isr));
 	kw_write_reg(reg_mode, mode_reg | (bus->channel << 4));
 	kw_write_reg(reg_status, 0);
 	/* Set up address and r/w bit, strip possible stale bus number from
 	 * address top bits
 	 */
 	kw_write_reg(reg_addr, addrdir & 0xff);
 	/* Set up the sub address */
 	if ((mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB
 	    || (mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_COMBINED)
 		kw_write_reg(reg_subaddr, subaddr);
-	/* Start sending address & disable interrupt*/
+	/* Prepare for async operations */
-	kw_write_reg(reg_ier, 0 /*KW_I2C_IRQ_MASK*/);
+	host->data = data;
+	host->len = len;
+	host->state = state_addr;
+	host->result = 0;
+	host->rw = (addrdir & 1);
+	host->polled = bus->polled;
+	/* Enable interrupt if not using polled mode and interrupt is
+	 * available
+	 */
+	if (use_irq) {
+		/* Clear completion */
+		INIT_COMPLETION(host->complete);
+		/* Ack stale interrupts */
+		kw_write_reg(reg_isr, kw_read_reg(reg_isr));
+		/* Arm timeout */
+		host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
+		add_timer(&host->timeout_timer);
+		/* Enable emission */
+		kw_write_reg(reg_ier, KW_I2C_IRQ_MASK);
+	}
+	/* Start sending address */
 	kw_write_reg(reg_control, KW_I2C_CTL_XADDR);
-	/* State machine, to turn into an interrupt handler in the future */
+	/* Wait for completion */
-	while(state != state_idle) {
+	if (use_irq)
-		u8 isr = kw_i2c_wait_interrupt(bus);
+		wait_for_completion(&host->complete);
-		state = kw_i2c_handle_interrupt(bus, state, addrdir & 1, &rc,
+	else {
-						&data, &len, isr);
+		while(host->state != state_idle) {
+			unsigned long flags;
+			u8 isr = kw_i2c_wait_interrupt(host);
+			spin_lock_irqsave(&host->lock, flags);
+			kw_i2c_handle_interrupt(host, isr);
+			spin_unlock_irqrestore(&host->lock, flags);
+		}
 	}
-	return rc;
+	/* Disable emission */
+	kw_write_reg(reg_ier, 0);
+	return host->result;
 }
 static struct pmac_i2c_host_kw *__init kw_i2c_host_init(struct device_node *np)
 {
 	struct pmac_i2c_host_kw *host;
 	u32			*psteps, *prate, *addrp, steps;
 	host = kzalloc(sizeof(struct pmac_i2c_host_kw), GFP_KERNEL);
 	if (host == NULL) {
 		printk(KERN_ERR "low_i2c: Can't allocate host for %s\n",
 		       np->full_name);
 		return NULL;
 	}
 	/* Apple is kind enough to provide a valid AAPL,address property
 	 * on all i2c keywest nodes so far ... we would have to fallback
 	 * to macio parsing if that wasn't the case
 	 */
 	addrp = (u32 *)get_property(np, "AAPL,address", NULL);
 	if (addrp == NULL) {
 		printk(KERN_ERR "low_i2c: Can't find address for %s\n",
 		       np->full_name);
 		kfree(host);
 		return NULL;
 	}
 	init_MUTEX(&host->mutex);
+	init_completion(&host->complete);
+	spin_lock_init(&host->lock);
+	init_timer(&host->timeout_timer);
+	host->timeout_timer.function = kw_i2c_timeout;
+	host->timeout_timer.data = (unsigned long)host;
 	psteps = (u32 *)get_property(np, "AAPL,address-step", NULL);
 	steps = psteps ? (*psteps) : 0x10;
 	for (host->bsteps = 0; (steps & 0x01) == 0; host->bsteps++)
 		steps >>= 1;
 	/* Select interface rate */
 	host->speed = KW_I2C_MODE_25KHZ;
 	prate = (u32 *)get_property(np, "AAPL,i2c-rate", NULL);
 	if (prate) switch(*prate) {
 	case 100:
 		host->speed = KW_I2C_MODE_100KHZ;
 		break;
 	case 50:
 		host->speed = KW_I2C_MODE_50KHZ;
 		break;
 	case 25:
 		host->speed = KW_I2C_MODE_25KHZ;
 		break;
 	}
+	if (np->n_intrs > 0)
+		host->irq = np->intrs[0].line;
+	else
+		host->irq = NO_IRQ;
-	printk(KERN_INFO "KeyWest i2c @0x%08x %s\n", *addrp, np->full_name);
 	host->base = ioremap((*addrp), 0x1000);
+	if (host->base == NULL) {
+		printk(KERN_ERR "low_i2c: Can't map registers for %s\n",
+		       np->full_name);
+		kfree(host);
+		return NULL;
+	}
+	/* Make sure IRA is disabled */
+	kw_write_reg(reg_ier, 0);
+	/* Request chip interrupt */
+	if (request_irq(host->irq, kw_i2c_irq, SA_SHIRQ, "keywest i2c", host))
+		host->irq = NO_IRQ;
+	printk(KERN_INFO "KeyWest i2c @0x%08x irq %d %s\n",
+	       *addrp, host->irq, np->full_name);
 	return host;
 }
 static void __init kw_i2c_add(struct pmac_i2c_host_kw *host,
 			      struct device_node *controller,
 			      struct device_node *busnode,
 			      int channel)
 {
 	struct pmac_i2c_bus *bus;
 	bus = kzalloc(sizeof(struct pmac_i2c_bus), GFP_KERNEL);
 	if (bus == NULL)
 		return;
 	bus->controller = of_node_get(controller);
 	bus->busnode = of_node_get(busnode);
 	bus->type = pmac_i2c_bus_keywest;
 	bus->hostdata = host;
 	bus->channel = channel;
 	bus->mode = pmac_i2c_mode_std;
 	bus->open = kw_i2c_open;
 	bus->close = kw_i2c_close;
 	bus->xfer = kw_i2c_xfer;
 	init_MUTEX(&bus->sem);
 	if (controller == busnode)
 		bus->flags = pmac_i2c_multibus;
 	list_add(&bus->link, &pmac_i2c_busses);
 	printk(KERN_INFO " channel %d bus %s\n", channel,
 	       (controller == busnode) ? "<multibus>" : busnode->full_name);
 }
 static void __init kw_i2c_probe(void)
 {
 	struct device_node *np, *child, *parent;
 	/* Probe keywest-i2c busses */
 	for (np = NULL;
 	     (np = of_find_compatible_node(np, "i2c","keywest-i2c")) != NULL;){
 		struct pmac_i2c_host_kw *host;
 		int multibus, chans, i;
 		/* Found one, init a host structure */
 		host = kw_i2c_host_init(np);
 		if (host == NULL)
 			continue;
 		/* Now check if we have a multibus setup (old style) or if we
 		 * have proper bus nodes. Note that the "new" way (proper bus
 		 * nodes) might cause us to not create some busses that are
 		 * kept hidden in the device-tree. In the future, we might
 		 * want to work around that by creating busses without a node
 		 * but not for now
 		 */
 		child = of_get_next_child(np, NULL);
 		multibus = !child || strcmp(child->name, "i2c-bus");
 		of_node_put(child);
 		/* For a multibus setup, we get the bus count based on the
 		 * parent type
 		 */
 		if (multibus) {
 			parent = of_get_parent(np);
 			if (parent == NULL)
 				continue;
 			chans = parent->name[0] == 'u' ? 2 : 1;
 			for (i = 0; i < chans; i++)
 				kw_i2c_add(host, np, np, i);
 		} else {
 			for (child = NULL;
 			     (child = of_get_next_child(np, child)) != NULL;) {
 				u32 *reg =
 					(u32 *)get_property(child, "reg", NULL);
 				if (reg == NULL)
 					continue;
 				kw_i2c_add(host, np, child, *reg);
 			}
 		}
 	}
 }
 /*
  *
  * PMU implementation
  *
  */
 #ifdef CONFIG_ADB_PMU
 /*
  * i2c command block to the PMU
  */
 struct pmu_i2c_hdr {
 	u8	bus;
 	u8	mode;
 	u8	bus2;
 	u8	address;
 	u8	sub_addr;
 	u8	comb_addr;
 	u8	count;
 	u8	data[];
 };
 static void pmu_i2c_complete(struct adb_request *req)
 {
 	complete(req->arg);
 }
 static int pmu_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
 			u32 subaddr, u8 *data, int len)
 {
 	struct adb_request *req = bus->hostdata;
 	struct pmu_i2c_hdr *hdr = (struct pmu_i2c_hdr *)&req->data[1];
 	struct completion comp;
 	int read = addrdir & 1;
 	int retry;
 	int rc = 0;
 	/* For now, limit ourselves to 16 bytes transfers */
 	if (len > 16)
 		return -EINVAL;
 	init_completion(&comp);
 	for (retry = 0; retry < 16; retry++) {
 		memset(req, 0, sizeof(struct adb_request));
 		hdr->bus = bus->channel;
 		hdr->count = len;
 		switch(bus->mode) {
 		case pmac_i2c_mode_std:
 			if (subsize != 0)
 				return -EINVAL;
 			hdr->address = addrdir;
 			hdr->mode = PMU_I2C_MODE_SIMPLE;
 			break;
 		case pmac_i2c_mode_stdsub:
 		case pmac_i2c_mode_combined:
 			if (subsize != 1)
 				return -EINVAL;
 			hdr->address = addrdir & 0xfe;
 			hdr->comb_addr = addrdir;
 			hdr->sub_addr = subaddr;
 			if (bus->mode == pmac_i2c_mode_stdsub)
 				hdr->mode = PMU_I2C_MODE_STDSUB;
 			else
 				hdr->mode = PMU_I2C_MODE_COMBINED;
 			break;
 		default:
 			return -EINVAL;
 		}
 		INIT_COMPLETION(comp);
 		req->data[0] = PMU_I2C_CMD;
 		req->reply[0] = 0xff;
 		req->nbytes = sizeof(struct pmu_i2c_hdr) + 1;
 		req->done = pmu_i2c_complete;
 		req->arg = &comp;
-		if (!read) {
+		if (!read && len) {
 			memcpy(hdr->data, data, len);
 			req->nbytes += len;
 		}
 		rc = pmu_queue_request(req);
 		if (rc)
 			return rc;
 		wait_for_completion(&comp);
 		if (req->reply[0] == PMU_I2C_STATUS_OK)
 			break;
 		msleep(15);
 	}
 	if (req->reply[0] != PMU_I2C_STATUS_OK)
 		return -EIO;
 	for (retry = 0; retry < 16; retry++) {
 		memset(req, 0, sizeof(struct adb_request));
 		/* I know that looks like a lot, slow as hell, but darwin
 		 * does it so let's be on the safe side for now
 		 */
 		msleep(15);
 		hdr->bus = PMU_I2C_BUS_STATUS;
 		INIT_COMPLETION(comp);
 		req->data[0] = PMU_I2C_CMD;
 		req->reply[0] = 0xff;
 		req->nbytes = 2;
 		req->done = pmu_i2c_complete;
 		req->arg = &comp;
 		rc = pmu_queue_request(req);
 		if (rc)
 			return rc;
 		wait_for_completion(&comp);
 		if (req->reply[0] == PMU_I2C_STATUS_OK && !read)
 			return 0;
 		if (req->reply[0] == PMU_I2C_STATUS_DATAREAD && read) {
 			int rlen = req->reply_len - 1;
 			if (rlen != len) {
 				printk(KERN_WARNING "low_i2c: PMU returned %d"
 				       " bytes, expected %d !\n", rlen, len);
 				return -EIO;
 			}
-			memcpy(data, &req->reply[1], len);
+			if (len)
+				memcpy(data, &req->reply[1], len);
 			return 0;
 		}
 	}
 	return -EIO;
 }
 static void __init pmu_i2c_probe(void)
 {
 	struct pmac_i2c_bus *bus;
 	struct device_node *busnode;
 	int channel, sz;
 	if (!pmu_present())
 		return;
 	/* There might or might not be a "pmu-i2c" node, we use that
 	 * or via-pmu itself, whatever we find. I haven't seen a machine
 	 * with separate bus nodes, so we assume a multibus setup
 	 */
 	busnode = of_find_node_by_name(NULL, "pmu-i2c");
 	if (busnode == NULL)
 		busnode = of_find_node_by_name(NULL, "via-pmu");
 	if (busnode == NULL)
 		return;
 	printk(KERN_INFO "PMU i2c %s\n", busnode->full_name);
 	/*
 	 * We add bus 1 and 2 only for now, bus 0 is "special"
 	 */
 	for (channel = 1; channel <= 2; channel++) {
 		sz = sizeof(struct pmac_i2c_bus) + sizeof(struct adb_request);
 		bus = kzalloc(sz, GFP_KERNEL);
 		if (bus == NULL)
 			return;
 		bus->controller = busnode;
 		bus->busnode = busnode;
 		bus->type = pmac_i2c_bus_pmu;
 		bus->channel = channel;
 		bus->mode = pmac_i2c_mode_std;
 		bus->hostdata = bus + 1;
 		bus->xfer = pmu_i2c_xfer;
 		init_MUTEX(&bus->sem);
 		bus->flags = pmac_i2c_multibus;
 		list_add(&bus->link, &pmac_i2c_busses);
 		printk(KERN_INFO " channel %d bus <multibus>\n", channel);
 	}
 }
 #endif /* CONFIG_ADB_PMU */
 /*
  *
  * SMU implementation
  *
  */
 #ifdef CONFIG_PMAC_SMU
 static void smu_i2c_complete(struct smu_i2c_cmd *cmd, void *misc)
 {
 	complete(misc);
 }
 static int smu_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
 			u32 subaddr, u8 *data, int len)
 {
 	struct smu_i2c_cmd *cmd = bus->hostdata;
 	struct completion comp;
 	int read = addrdir & 1;
 	int rc = 0;
+	if ((read && len > SMU_I2C_READ_MAX) ||
+	    ((!read) && len > SMU_I2C_WRITE_MAX))
+		return -EINVAL;
 	memset(cmd, 0, sizeof(struct smu_i2c_cmd));
 	cmd->info.bus = bus->channel;
 	cmd->info.devaddr = addrdir;
 	cmd->info.datalen = len;
 	switch(bus->mode) {
 	case pmac_i2c_mode_std:
 		if (subsize != 0)
 			return -EINVAL;
 		cmd->info.type = SMU_I2C_TRANSFER_SIMPLE;
 		break;
 	case pmac_i2c_mode_stdsub:
 	case pmac_i2c_mode_combined:
 		if (subsize > 3 || subsize < 1)
 			return -EINVAL;
 		cmd->info.sublen = subsize;
 		/* that's big-endian only but heh ! */
 		memcpy(&cmd->info.subaddr, ((char *)&subaddr) + (4 - subsize),
 		       subsize);
 		if (bus->mode == pmac_i2c_mode_stdsub)
 			cmd->info.type = SMU_I2C_TRANSFER_STDSUB;
 		else
 			cmd->info.type = SMU_I2C_TRANSFER_COMBINED;
 		break;
 	default:
 		return -EINVAL;
 	}
-	if (!read)
+	if (!read && len)
 		memcpy(cmd->info.data, data, len);
 	init_completion(&comp);
 	cmd->done = smu_i2c_complete;
 	cmd->misc = &comp;
 	rc = smu_queue_i2c(cmd);
 	if (rc < 0)
 		return rc;
 	wait_for_completion(&comp);
 	rc = cmd->status;
-	if (read)
+	if (read && len)
 		memcpy(data, cmd->info.data, len);
 	return rc < 0 ? rc : 0;
 }
 static void __init smu_i2c_probe(void)
 {
 	struct device_node *controller, *busnode;
 	struct pmac_i2c_bus *bus;
 	u32 *reg;
 	int sz;
 	if (!smu_present())
 		return;
-	controller = of_find_node_by_name(NULL, "smu_i2c_control");
+	controller = of_find_node_by_name(NULL, "smu-i2c-control");
 	if (controller == NULL)
 		controller = of_find_node_by_name(NULL, "smu");
 	if (controller == NULL)
 		return;
 	printk(KERN_INFO "SMU i2c %s\n", controller->full_name);
 	/* Look for childs, note that they might not be of the right
 	 * type as older device trees mix i2c busses and other thigns
 	 * at the same level
 	 */
 	for (busnode = NULL;
 	     (busnode = of_get_next_child(controller, busnode)) != NULL;) {
 		if (strcmp(busnode->type, "i2c") &&
 		    strcmp(busnode->type, "i2c-bus"))
 			continue;
 		reg = (u32 *)get_property(busnode, "reg", NULL);
 		if (reg == NULL)
 			continue;
 		sz = sizeof(struct pmac_i2c_bus) + sizeof(struct smu_i2c_cmd);
 		bus = kzalloc(sz, GFP_KERNEL);
 		if (bus == NULL)
 			return;
 		bus->controller = controller;
 		bus->busnode = of_node_get(busnode);
 		bus->type = pmac_i2c_bus_smu;
 		bus->channel = *reg;
 		bus->mode = pmac_i2c_mode_std;
 		bus->hostdata = bus + 1;
 		bus->xfer = smu_i2c_xfer;
 		init_MUTEX(&bus->sem);
 		bus->flags = 0;
 		list_add(&bus->link, &pmac_i2c_busses);
 		printk(KERN_INFO " channel %x bus %s\n",
 		       bus->channel, busnode->full_name);
 	}
 }
 #endif /* CONFIG_PMAC_SMU */
 /*
  *
  * Core code
  *
  */
 struct pmac_i2c_bus *pmac_i2c_find_bus(struct device_node *node)
 {
 	struct device_node *p = of_node_get(node);
 	struct device_node *prev = NULL;
 	struct pmac_i2c_bus *bus;
 	while(p) {
 		list_for_each_entry(bus, &pmac_i2c_busses, link) {
 			if (p == bus->busnode) {
 				if (prev && bus->flags & pmac_i2c_multibus) {
 					u32 *reg;
 					reg = (u32 *)get_property(prev, "reg",
 								  NULL);
 					if (!reg)
 						continue;
 					if (((*reg) >> 8) != bus->channel)
 						continue;
 				}
 				of_node_put(p);
 				of_node_put(prev);
 				return bus;
 			}
 		}
 		of_node_put(prev);
 		prev = p;
 		p = of_get_parent(p);
 	}
 	return NULL;
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_find_bus);
 u8 pmac_i2c_get_dev_addr(struct device_node *device)
 {
 	u32 *reg = (u32 *)get_property(device, "reg", NULL);
 	if (reg == NULL)
 		return 0;
 	return (*reg) & 0xff;
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_get_dev_addr);
 struct device_node *pmac_i2c_get_controller(struct pmac_i2c_bus *bus)
 {
 	return bus->controller;
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_get_controller);
 struct device_node *pmac_i2c_get_bus_node(struct pmac_i2c_bus *bus)
 {
 	return bus->busnode;
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_get_bus_node);
 int pmac_i2c_get_type(struct pmac_i2c_bus *bus)
 {
 	return bus->type;
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_get_type);
 int pmac_i2c_get_flags(struct pmac_i2c_bus *bus)
 {
 	return bus->flags;
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_get_flags);
+int pmac_i2c_get_channel(struct pmac_i2c_bus *bus)
+{
+	return bus->channel;
+}
+EXPORT_SYMBOL_GPL(pmac_i2c_get_channel);
 void pmac_i2c_attach_adapter(struct pmac_i2c_bus *bus,
 			     struct i2c_adapter *adapter)
 {
 	WARN_ON(bus->adapter != NULL);
 	bus->adapter = adapter;
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_attach_adapter);
 void pmac_i2c_detach_adapter(struct pmac_i2c_bus *bus,
 			     struct i2c_adapter *adapter)
 {
 	WARN_ON(bus->adapter != adapter);
 	bus->adapter = NULL;
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_detach_adapter);
 struct i2c_adapter *pmac_i2c_get_adapter(struct pmac_i2c_bus *bus)
 {
 	return bus->adapter;
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_get_adapter);
+struct pmac_i2c_bus *pmac_i2c_adapter_to_bus(struct i2c_adapter *adapter)
+{
+	struct pmac_i2c_bus *bus;
+	list_for_each_entry(bus, &pmac_i2c_busses, link)
+		if (bus->adapter == adapter)
+			return bus;
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(pmac_i2c_adapter_to_bus);
 extern int pmac_i2c_match_adapter(struct device_node *dev,
 				  struct i2c_adapter *adapter)
 {
 	struct pmac_i2c_bus *bus = pmac_i2c_find_bus(dev);
 	if (bus == NULL)
 		return 0;
 	return (bus->adapter == adapter);
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_match_adapter);
 int pmac_low_i2c_lock(struct device_node *np)
 {
 	struct pmac_i2c_bus *bus, *found = NULL;
 	list_for_each_entry(bus, &pmac_i2c_busses, link) {
 		if (np == bus->controller) {
 			found = bus;
 			break;
 		}
 	}
 	if (!found)
 		return -ENODEV;
 	return pmac_i2c_open(bus, 0);
 }
 EXPORT_SYMBOL_GPL(pmac_low_i2c_lock);
 int pmac_low_i2c_unlock(struct device_node *np)
 {
 	struct pmac_i2c_bus *bus, *found = NULL;
 	list_for_each_entry(bus, &pmac_i2c_busses, link) {
 		if (np == bus->controller) {
 			found = bus;
 			break;
 		}
 	}
 	if (!found)
 		return -ENODEV;
 	pmac_i2c_close(bus);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(pmac_low_i2c_unlock);
 int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled)
 {
 	int rc;
 	down(&bus->sem);
-	bus->polled = polled;
+	bus->polled = polled || pmac_i2c_force_poll;
 	bus->opened = 1;
 	bus->mode = pmac_i2c_mode_std;
 	if (bus->open && (rc = bus->open(bus)) != 0) {
 		bus->opened = 0;
 		up(&bus->sem);
 		return rc;
 	}
 	return 0;
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_open);
 void pmac_i2c_close(struct pmac_i2c_bus *bus)
 {
 	WARN_ON(!bus->opened);
 	if (bus->close)
 		bus->close(bus);
 	bus->opened = 0;
 	up(&bus->sem);
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_close);
 int pmac_i2c_setmode(struct pmac_i2c_bus *bus, int mode)
 {
 	WARN_ON(!bus->opened);
 	/* Report me if you see the error below as there might be a new
 	 * "combined4" mode that I need to implement for the SMU bus
 	 */
 	if (mode < pmac_i2c_mode_dumb || mode > pmac_i2c_mode_combined) {
 		printk(KERN_ERR "low_i2c: Invalid mode %d requested on"
 		       " bus %s !\n", mode, bus->busnode->full_name);
 		return -EINVAL;
 	}
 	bus->mode = mode;
 	return 0;
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_setmode);
 int pmac_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
 		  u32 subaddr, u8 *data, int len)
 {
 	int rc;
 	WARN_ON(!bus->opened);
 	DBG("xfer() chan=%d, addrdir=0x%x, mode=%d, subsize=%d, subaddr=0x%x,"
 	    " %d bytes, bus %s\n", bus->channel, addrdir, bus->mode, subsize,
 	    subaddr, len, bus->busnode->full_name);
 	rc = bus->xfer(bus, addrdir, subsize, subaddr, data, len);
 #ifdef DEBUG
 	if (rc)
 		DBG("xfer error %d\n", rc);
 #endif
 	return rc;
 }
 EXPORT_SYMBOL_GPL(pmac_i2c_xfer);
 /*
  * Initialize us: probe all i2c busses on the machine and instantiate
  * busses.
  */
 /* This is non-static as it might be called early by smp code */
 int __init pmac_i2c_init(void)
 {
 	static int i2c_inited;
 	if (i2c_inited)
 		return 0;
 	i2c_inited = 1;
 	/* Probe keywest-i2c busses */
 	kw_i2c_probe();
 #ifdef CONFIG_ADB_PMU
+	/* Probe PMU i2c busses */
 	pmu_i2c_probe();
 #endif
 #ifdef CONFIG_PMAC_SMU
+	/* Probe SMU i2c busses */
 	smu_i2c_probe();
 #endif
 	return 0;
 }
 arch_initcall(pmac_i2c_init);
+/* Since pmac_i2c_init can be called too early for the platform device
+ * registration, we need to do it at a later time. In our case, subsys
+ * happens to fit well, though I agree it's a bit of a hack...
+ */
+static int __init pmac_i2c_create_platform_devices(void)
+{
+	struct pmac_i2c_bus *bus;
+	int i = 0;
+	/* In the case where we are initialized from smp_init(), we must
+	 * not use the timer (and thus the irq). It's safe from now on
+	 * though
+	 */
+	pmac_i2c_force_poll = 0;
+	/* Create platform devices */
+	list_for_each_entry(bus, &pmac_i2c_busses, link) {
+		bus->platform_dev =
+			platform_device_alloc("i2c-powermac", i++);
+		if (bus->platform_dev == NULL)
+			return -ENOMEM;
+		bus->platform_dev->dev.platform_data = bus;

arch/powerpc/platforms/powermac/setup.c

Diff comments View file @ a28d3af

 /*
  *  Powermac setup and early boot code plus other random bits.
  *
  *  PowerPC version
  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  *
  *  Adapted for Power Macintosh by Paul Mackerras
  *    Copyright (C) 1996 Paul Mackerras (paulus@samba.org)
  *
  *  Derived from "arch/alpha/kernel/setup.c"
  *    Copyright (C) 1995 Linus Torvalds
  *
  *  Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
  *
  *  This program is free software; you can redistribute it and/or
  *  modify it under the terms of the GNU General Public License
  *  as published by the Free Software Foundation; either version
  *  2 of the License, or (at your option) any later version.
  *
  */
 /*
  * bootup setup stuff..
  */
 #include <linux/config.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/sched.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/stddef.h>
 #include <linux/unistd.h>
 #include <linux/ptrace.h>
 #include <linux/slab.h>
 #include <linux/user.h>
 #include <linux/a.out.h>
 #include <linux/tty.h>
 #include <linux/string.h>
 #include <linux/delay.h>
 #include <linux/ioport.h>
 #include <linux/major.h>
 #include <linux/initrd.h>
 #include <linux/vt_kern.h>
 #include <linux/console.h>
 #include <linux/ide.h>
 #include <linux/pci.h>
 #include <linux/adb.h>
 #include <linux/cuda.h>
 #include <linux/pmu.h>
 #include <linux/irq.h>
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
 #include <linux/bitops.h>
 #include <linux/suspend.h>
 #include <asm/reg.h>
 #include <asm/sections.h>
 #include <asm/prom.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/io.h>
 #include <asm/kexec.h>
 #include <asm/pci-bridge.h>
 #include <asm/ohare.h>
 #include <asm/mediabay.h>
 #include <asm/machdep.h>
 #include <asm/dma.h>
 #include <asm/cputable.h>
 #include <asm/btext.h>
 #include <asm/pmac_feature.h>
 #include <asm/time.h>
 #include <asm/of_device.h>
 #include <asm/mmu_context.h>
 #include <asm/iommu.h>
 #include <asm/smu.h>
 #include <asm/pmc.h>
 #include <asm/lmb.h>
 #include <asm/udbg.h>
 #include "pmac.h"
 #undef SHOW_GATWICK_IRQS
 unsigned char drive_info;
 int ppc_override_l2cr = 0;
 int ppc_override_l2cr_value;
 int has_l2cache = 0;
 int pmac_newworld = 1;
 static int current_root_goodness = -1;
 extern int pmac_newworld;
 extern struct machdep_calls pmac_md;
 #define DEFAULT_ROOT_DEVICE Root_SDA1	/* sda1 - slightly silly choice */
 #ifdef CONFIG_PPC64
 #include <asm/udbg.h>
 int sccdbg;
 #endif
 extern void zs_kgdb_hook(int tty_num);
 sys_ctrler_t sys_ctrler = SYS_CTRLER_UNKNOWN;
 EXPORT_SYMBOL(sys_ctrler);
 #ifdef CONFIG_PMAC_SMU
 unsigned long smu_cmdbuf_abs;
 EXPORT_SYMBOL(smu_cmdbuf_abs);
 #endif
 #ifdef CONFIG_SMP
 extern struct smp_ops_t psurge_smp_ops;
 extern struct smp_ops_t core99_smp_ops;
 #endif /* CONFIG_SMP */
 static void pmac_show_cpuinfo(struct seq_file *m)
 {
 	struct device_node *np;
 	char *pp;
 	int plen;
 	int mbmodel;
 	unsigned int mbflags;
 	char* mbname;
 	mbmodel = pmac_call_feature(PMAC_FTR_GET_MB_INFO, NULL,
 				    PMAC_MB_INFO_MODEL, 0);
 	mbflags = pmac_call_feature(PMAC_FTR_GET_MB_INFO, NULL,
 				    PMAC_MB_INFO_FLAGS, 0);
 	if (pmac_call_feature(PMAC_FTR_GET_MB_INFO, NULL, PMAC_MB_INFO_NAME,
 			      (long) &mbname) != 0)
 		mbname = "Unknown";
 	/* find motherboard type */
 	seq_printf(m, "machine\t\t: ");
 	np = of_find_node_by_path("/");
 	if (np != NULL) {
 		pp = (char *) get_property(np, "model", NULL);
 		if (pp != NULL)
 			seq_printf(m, "%s\n", pp);
 		else
 			seq_printf(m, "PowerMac\n");
 		pp = (char *) get_property(np, "compatible", &plen);
 		if (pp != NULL) {
 			seq_printf(m, "motherboard\t:");
 			while (plen > 0) {
 				int l = strlen(pp) + 1;
 				seq_printf(m, " %s", pp);
 				plen -= l;
 				pp += l;
 			}
 			seq_printf(m, "\n");
 		}
 		of_node_put(np);
 	} else
 		seq_printf(m, "PowerMac\n");
 	/* print parsed model */
 	seq_printf(m, "detected as\t: %d (%s)\n", mbmodel, mbname);
 	seq_printf(m, "pmac flags\t: %08x\n", mbflags);
 	/* find l2 cache info */
 	np = of_find_node_by_name(NULL, "l2-cache");
 	if (np == NULL)
 		np = of_find_node_by_type(NULL, "cache");
 	if (np != NULL) {
 		unsigned int *ic = (unsigned int *)
 			get_property(np, "i-cache-size", NULL);
 		unsigned int *dc = (unsigned int *)
 			get_property(np, "d-cache-size", NULL);
 		seq_printf(m, "L2 cache\t:");
 		has_l2cache = 1;
 		if (get_property(np, "cache-unified", NULL) != 0 && dc) {
 			seq_printf(m, " %dK unified", *dc / 1024);
 		} else {
 			if (ic)
 				seq_printf(m, " %dK instruction", *ic / 1024);
 			if (dc)
 				seq_printf(m, "%s %dK data",
 					   (ic? " +": ""), *dc / 1024);
 		}
 		pp = get_property(np, "ram-type", NULL);
 		if (pp)
 			seq_printf(m, " %s", pp);
 		seq_printf(m, "\n");
 		of_node_put(np);
 	}
 	/* Indicate newworld/oldworld */
 	seq_printf(m, "pmac-generation\t: %s\n",
 		   pmac_newworld ? "NewWorld" : "OldWorld");
 }
 #ifndef CONFIG_ADB_CUDA
 int find_via_cuda(void)
 {
 	if (!find_devices("via-cuda"))
 		return 0;
 	printk("WARNING ! Your machine is CUDA-based but your kernel\n");
 	printk("          wasn't compiled with CONFIG_ADB_CUDA option !\n");
 	return 0;
 }
 #endif
 #ifndef CONFIG_ADB_PMU
 int find_via_pmu(void)
 {
 	if (!find_devices("via-pmu"))
 		return 0;
 	printk("WARNING ! Your machine is PMU-based but your kernel\n");
 	printk("          wasn't compiled with CONFIG_ADB_PMU option !\n");
 	return 0;
 }
 #endif
 #ifndef CONFIG_PMAC_SMU
 int smu_init(void)
 {
 	/* should check and warn if SMU is present */
 	return 0;
 }
 #endif
 #ifdef CONFIG_PPC32
 static volatile u32 *sysctrl_regs;
 static void __init ohare_init(void)
 {
 	/* this area has the CPU identification register
 	   and some registers used by smp boards */
 	sysctrl_regs = (volatile u32 *) ioremap(0xf8000000, 0x1000);
 	/*
 	 * Turn on the L2 cache.
 	 * We assume that we have a PSX memory controller iff
 	 * we have an ohare I/O controller.
 	 */
 	if (find_devices("ohare") != NULL) {
 		if (((sysctrl_regs[2] >> 24) & 0xf) >= 3) {
 			if (sysctrl_regs[4] & 0x10)
 				sysctrl_regs[4] |= 0x04000020;
 			else
 				sysctrl_regs[4] |= 0x04000000;
 			if(has_l2cache)
 				printk(KERN_INFO "Level 2 cache enabled\n");
 		}
 	}
 }
 static void __init l2cr_init(void)
 {
 	/* Checks "l2cr-value" property in the registry */
 	if (cpu_has_feature(CPU_FTR_L2CR)) {
 		struct device_node *np = find_devices("cpus");
 		if (np == 0)
 			np = find_type_devices("cpu");
 		if (np != 0) {
 			unsigned int *l2cr = (unsigned int *)
 				get_property(np, "l2cr-value", NULL);
 			if (l2cr != 0) {
 				ppc_override_l2cr = 1;
 				ppc_override_l2cr_value = *l2cr;
 				_set_L2CR(0);
 				_set_L2CR(ppc_override_l2cr_value);
 			}
 		}
 	}
 	if (ppc_override_l2cr)
 		printk(KERN_INFO "L2CR overridden (0x%x), "
 		       "backside cache is %s\n",
 		       ppc_override_l2cr_value,
 		       (ppc_override_l2cr_value & 0x80000000)
 				? "enabled" : "disabled");
 }
 #endif
 void __init pmac_setup_arch(void)
 {
 	struct device_node *cpu, *ic;
 	int *fp;
 	unsigned long pvr;
 	pvr = PVR_VER(mfspr(SPRN_PVR));
 	/* Set loops_per_jiffy to a half-way reasonable value,
 	   for use until calibrate_delay gets called. */
 	loops_per_jiffy = 50000000 / HZ;
 	cpu = of_find_node_by_type(NULL, "cpu");
 	if (cpu != NULL) {
 		fp = (int *) get_property(cpu, "clock-frequency", NULL);
 		if (fp != NULL) {
 			if (pvr >= 0x30 && pvr < 0x80)
 				/* PPC970 etc. */
 				loops_per_jiffy = *fp / (3 * HZ);
 			else if (pvr == 4 || pvr >= 8)
 				/* 604, G3, G4 etc. */
 				loops_per_jiffy = *fp / HZ;
 			else
 				/* 601, 603, etc. */
 				loops_per_jiffy = *fp / (2 * HZ);
 		}
 		of_node_put(cpu);
 	}
 	/* See if newworld or oldworld */
 	for (ic = NULL; (ic = of_find_all_nodes(ic)) != NULL; )
 		if (get_property(ic, "interrupt-controller", NULL))
 			break;
 	pmac_newworld = (ic != NULL);
 	if (ic)
 		of_node_put(ic);
 	/* Lookup PCI hosts */
 	pmac_pci_init();
 #ifdef CONFIG_PPC32
 	ohare_init();
 	l2cr_init();
 #endif /* CONFIG_PPC32 */
 #ifdef CONFIG_KGDB
 	zs_kgdb_hook(0);
 #endif
 	find_via_cuda();
 	find_via_pmu();
 	smu_init();
 #if defined(CONFIG_NVRAM) || defined(CONFIG_PPC64)
 	pmac_nvram_init();
 #endif
 #ifdef CONFIG_PPC32
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (initrd_start)
 		ROOT_DEV = Root_RAM0;
 	else
 #endif
 		ROOT_DEV = DEFAULT_ROOT_DEVICE;
 #endif
 #ifdef CONFIG_SMP
 	/* Check for Core99 */
 	if (find_devices("uni-n") || find_devices("u3") || find_devices("u4"))
 		smp_ops = &core99_smp_ops;
 #ifdef CONFIG_PPC32
 	else
 		smp_ops = &psurge_smp_ops;
 #endif
 #endif /* CONFIG_SMP */
 }
 char *bootpath;
 char *bootdevice;
 void *boot_host;
 int boot_target;
 int boot_part;
 extern dev_t boot_dev;
 #ifdef CONFIG_SCSI
 void __init note_scsi_host(struct device_node *node, void *host)
 {
 	int l;
 	char *p;
 	l = strlen(node->full_name);
 	if (bootpath != NULL && bootdevice != NULL
 	    && strncmp(node->full_name, bootdevice, l) == 0
 	    && (bootdevice[l] == '/' || bootdevice[l] == 0)) {
 		boot_host = host;
 		/*
 		 * There's a bug in OF 1.0.5.  (Why am I not surprised.)
 		 * If you pass a path like scsi/sd@1:0 to canon, it returns
 		 * something like /bandit@F2000000/gc@10/53c94@10000/sd@0,0
 		 * That is, the scsi target number doesn't get preserved.
 		 * So we pick the target number out of bootpath and use that.
 		 */
 		p = strstr(bootpath, "/sd@");
 		if (p != NULL) {
 			p += 4;
 			boot_target = simple_strtoul(p, NULL, 10);
 			p = strchr(p, ':');
 			if (p != NULL)
 				boot_part = simple_strtoul(p + 1, NULL, 10);
 		}
 	}
 }
 EXPORT_SYMBOL(note_scsi_host);
 #endif
 #if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC)
 static dev_t __init find_ide_boot(void)
 {
 	char *p;
 	int n;
 	dev_t __init pmac_find_ide_boot(char *bootdevice, int n);
 	if (bootdevice == NULL)
 		return 0;
 	p = strrchr(bootdevice, '/');
 	if (p == NULL)
 		return 0;
 	n = p - bootdevice;
 	return pmac_find_ide_boot(bootdevice, n);
 }
 #endif /* CONFIG_BLK_DEV_IDE && CONFIG_BLK_DEV_IDE_PMAC */
 static void __init find_boot_device(void)
 {
 #if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC)
 	boot_dev = find_ide_boot();
 #endif
 }
 /* TODO: Merge the suspend-to-ram with the common code !!!
  * currently, this is a stub implementation for suspend-to-disk
  * only
  */
 #ifdef CONFIG_SOFTWARE_SUSPEND
 static int pmac_pm_prepare(suspend_state_t state)
 {
 	printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state);
 	return 0;
 }
 static int pmac_pm_enter(suspend_state_t state)
 {
 	printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state);
 	/* Giveup the lazy FPU & vec so we don't have to back them
 	 * up from the low level code
 	 */
 	enable_kernel_fp();
 #ifdef CONFIG_ALTIVEC
 	if (cur_cpu_spec->cpu_features & CPU_FTR_ALTIVEC)
 		enable_kernel_altivec();
 #endif /* CONFIG_ALTIVEC */
 	return 0;
 }
 static int pmac_pm_finish(suspend_state_t state)
 {
 	printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state);
 	/* Restore userland MMU context */
 	set_context(current->active_mm->context, current->active_mm->pgd);
 	return 0;
 }
 static struct pm_ops pmac_pm_ops = {
 	.pm_disk_mode	= PM_DISK_SHUTDOWN,
 	.prepare	= pmac_pm_prepare,
 	.enter		= pmac_pm_enter,
 	.finish		= pmac_pm_finish,
 };
 #endif /* CONFIG_SOFTWARE_SUSPEND */
 static int initializing = 1;
 static int pmac_late_init(void)
 {
 	initializing = 0;
 #ifdef CONFIG_SOFTWARE_SUSPEND
 	pm_set_ops(&pmac_pm_ops);
 #endif /* CONFIG_SOFTWARE_SUSPEND */
 	return 0;
 }
 late_initcall(pmac_late_init);
 /* can't be __init - can be called whenever a disk is first accessed */
 void note_bootable_part(dev_t dev, int part, int goodness)
 {
 	static int found_boot = 0;
 	char *p;
 	if (!initializing)
 		return;
 	if ((goodness <= current_root_goodness) &&
 	    ROOT_DEV != DEFAULT_ROOT_DEVICE)
 		return;
 	p = strstr(saved_command_line, "root=");
 	if (p != NULL && (p == saved_command_line || p[-1] == ' '))
 		return;
 	if (!found_boot) {
 		find_boot_device();
 		found_boot = 1;
 	}
 	if (!boot_dev || dev == boot_dev) {
 		ROOT_DEV = dev + part;
 		boot_dev = 0;
 		current_root_goodness = goodness;
 	}
 }
 #ifdef CONFIG_ADB_CUDA
 static void cuda_restart(void)
 {
 	struct adb_request req;
 	cuda_request(&req, NULL, 2, CUDA_PACKET, CUDA_RESET_SYSTEM);
 	for (;;)
 		cuda_poll();
 }
 static void cuda_shutdown(void)
 {
 	struct adb_request req;
 	cuda_request(&req, NULL, 2, CUDA_PACKET, CUDA_POWERDOWN);
 	for (;;)
 		cuda_poll();
 }
 #else
 #define cuda_restart()
 #define cuda_shutdown()
 #endif
 #ifndef CONFIG_ADB_PMU
 #define pmu_restart()
 #define pmu_shutdown()
 #endif
 #ifndef CONFIG_PMAC_SMU
 #define smu_restart()
 #define smu_shutdown()
 #endif
 static void pmac_restart(char *cmd)
 {
 	switch (sys_ctrler) {
 	case SYS_CTRLER_CUDA:
 		cuda_restart();
 		break;
 	case SYS_CTRLER_PMU:
 		pmu_restart();
 		break;
 	case SYS_CTRLER_SMU:
 		smu_restart();
 		break;
 	default: ;
 	}
 }
 static void pmac_power_off(void)
 {
 	switch (sys_ctrler) {
 	case SYS_CTRLER_CUDA:
 		cuda_shutdown();
 		break;
 	case SYS_CTRLER_PMU:
 		pmu_shutdown();
 		break;
 	case SYS_CTRLER_SMU:
 		smu_shutdown();
 		break;
 	default: ;
 	}
 }
 static void
 pmac_halt(void)
 {
 	pmac_power_off();
 }
 #ifdef CONFIG_PPC32
 void __init pmac_init(void)
 {
 	/* isa_io_base gets set in pmac_pci_init */
 	isa_mem_base = PMAC_ISA_MEM_BASE;
 	pci_dram_offset = PMAC_PCI_DRAM_OFFSET;
 	ISA_DMA_THRESHOLD = ~0L;
 	DMA_MODE_READ = 1;
 	DMA_MODE_WRITE = 2;
 	ppc_md = pmac_md;
 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 #ifdef CONFIG_BLK_DEV_IDE_PMAC
         ppc_ide_md.ide_init_hwif	= pmac_ide_init_hwif_ports;
         ppc_ide_md.default_io_base	= pmac_ide_get_base;
 #endif /* CONFIG_BLK_DEV_IDE_PMAC */
 #endif /* defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) */
 	if (ppc_md.progress) ppc_md.progress("pmac_init(): exit", 0);
 }
 #endif
 /*
  * Early initialization.
  */
 static void __init pmac_init_early(void)
 {
 #ifdef CONFIG_PPC64
 	/* Initialize hash table, from now on, we can take hash faults
 	 * and call ioremap
 	 */
 	hpte_init_native();
 #endif
 	/* Enable early btext debug if requested */
 	if (strstr(cmd_line, "btextdbg")) {
 		udbg_adb_init_early();
 		register_early_udbg_console();
 	}
 	/* Probe motherboard chipset */
 	pmac_feature_init();
 	/* We can NAP */
 	powersave_nap = 1;
 	printk(KERN_INFO "Using native/NAP idle loop\n");
 	/* Initialize debug stuff */
 	udbg_scc_init(!!strstr(cmd_line, "sccdbg"));
 	udbg_adb_init(!!strstr(cmd_line, "btextdbg"));
 #ifdef CONFIG_PPC64
 	/* Setup interrupt mapping options */
 	ppc64_interrupt_controller = IC_OPEN_PIC;
 	iommu_init_early_dart();
 #endif
 }
 /*
  * pmac has no legacy IO, anything calling this function has to
  * fail or bad things will happen
  */
 static int pmac_check_legacy_ioport(unsigned int baseport)
 {
 	return -ENODEV;
 }
 static int __init pmac_declare_of_platform_devices(void)
 {
-	struct device_node *np, *npp;
+	struct device_node *np;
 	np = of_find_node_by_name(NULL, "valkyrie");
 	if (np)
 		of_platform_device_create(np, "valkyrie", NULL);
 	np = of_find_node_by_name(NULL, "platinum");
 	if (np)
 		of_platform_device_create(np, "platinum", NULL);
-	npp = of_find_node_by_name(NULL, "uni-n");
-	if (npp == NULL)
-		npp = of_find_node_by_name(NULL, "u3");
-	if (npp == NULL)
-		npp = of_find_node_by_name(NULL, "u4");
-	if (npp) {
-		for (np = NULL; (np = of_get_next_child(npp, np)) != NULL;) {
-			if (strncmp(np->name, "i2c", 3) == 0) {
-				of_platform_device_create(np, "uni-n-i2c",
-							  NULL);
-				of_node_put(np);
-				break;
-			}
-		}
-		of_node_put(npp);
-	}
         np = of_find_node_by_type(NULL, "smu");
         if (np) {
 		of_platform_device_create(np, "smu", NULL);
 		of_node_put(np);
 	}
 	return 0;
 }
 device_initcall(pmac_declare_of_platform_devices);
 /*
  * Called very early, MMU is off, device-tree isn't unflattened
  */
 static int __init pmac_probe(int platform)
 {
 #ifdef CONFIG_PPC64
 	if (platform != PLATFORM_POWERMAC)
 		return 0;
 	/*
 	 * On U3, the DART (iommu) must be allocated now since it
 	 * has an impact on htab_initialize (due to the large page it
 	 * occupies having to be broken up so the DART itself is not
 	 * part of the cacheable linar mapping
 	 */
 	alloc_dart_table();
 #endif
 #ifdef CONFIG_PMAC_SMU
 	/*
 	 * SMU based G5s need some memory below 2Gb, at least the current
 	 * driver needs that. We have to allocate it now. We allocate 4k
 	 * (1 small page) for now.
 	 */
 	smu_cmdbuf_abs = lmb_alloc_base(4096, 4096, 0x80000000UL);
 #endif /* CONFIG_PMAC_SMU */
 	return 1;
 }
 #ifdef CONFIG_PPC64
 /* Move that to pci.c */
 static int pmac_pci_probe_mode(struct pci_bus *bus)
 {
 	struct device_node *node = bus->sysdata;
 	/* We need to use normal PCI probing for the AGP bus,
 	 * since the device for the AGP bridge isn't in the tree.
 	 */
 	if (bus->self == NULL && (device_is_compatible(node, "u3-agp") ||
 				  device_is_compatible(node, "u4-pcie")))
 		return PCI_PROBE_NORMAL;
 	return PCI_PROBE_DEVTREE;
 }
 #endif
 struct machdep_calls __initdata pmac_md = {
 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC64)
 	.cpu_die		= generic_mach_cpu_die,
 #endif
 	.probe			= pmac_probe,
 	.setup_arch		= pmac_setup_arch,
 	.init_early		= pmac_init_early,
 	.show_cpuinfo		= pmac_show_cpuinfo,
 	.init_IRQ		= pmac_pic_init,
 	.get_irq		= NULL,	/* changed later */
 	.pcibios_fixup		= pmac_pcibios_fixup,
 	.restart		= pmac_restart,
 	.power_off		= pmac_power_off,
 	.halt			= pmac_halt,
 	.time_init		= pmac_time_init,
 	.get_boot_time		= pmac_get_boot_time,
 	.set_rtc_time		= pmac_set_rtc_time,
 	.get_rtc_time		= pmac_get_rtc_time,
 	.calibrate_decr		= pmac_calibrate_decr,
 	.feature_call		= pmac_do_feature_call,
 	.check_legacy_ioport	= pmac_check_legacy_ioport,
 	.progress		= udbg_progress,
 #ifdef CONFIG_PPC64
 	.pci_probe_mode		= pmac_pci_probe_mode,
 	.idle_loop		= native_idle,
 	.enable_pmcs		= power4_enable_pmcs,
 #ifdef CONFIG_KEXEC
 	.machine_kexec		= default_machine_kexec,
 	.machine_kexec_prepare	= default_machine_kexec_prepare,
 	.machine_crash_shutdown	= default_machine_crash_shutdown,
 #endif
 #endif /* CONFIG_PPC64 */
 #ifdef CONFIG_PPC32
 	.pcibios_enable_device_hook = pmac_pci_enable_device_hook,
 	.pcibios_after_init	= pmac_pcibios_after_init,
 	.phys_mem_access_prot	= pci_phys_mem_access_prot,
 #endif
 };

drivers/i2c/busses/Kconfig

Diff comments View file @ a28d3af

 #
 # Sensor device configuration
 #
 menu "I2C Hardware Bus support"
 	depends on I2C
 config I2C_ALI1535
 	tristate "ALI 1535"
 	depends on I2C && PCI
 	help
 	  If you say yes to this option, support will be included for the SMB
 	  Host controller on Acer Labs Inc. (ALI) M1535 South Bridges.  The SMB
 	  controller is part of the 7101 device, which is an ACPI-compliant
 	  Power Management Unit (PMU).
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-ali1535.
 config I2C_ALI1563
 	tristate "ALI 1563"
 	depends on I2C && PCI && EXPERIMENTAL
 	help
 	  If you say yes to this option, support will be included for the SMB
 	  Host controller on Acer Labs Inc. (ALI) M1563 South Bridges.  The SMB
 	  controller is part of the 7101 device, which is an ACPI-compliant
 	  Power Management Unit (PMU).
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-ali1563.
 config I2C_ALI15X3
 	tristate "ALI 15x3"
 	depends on I2C && PCI
 	help
 	  If you say yes to this option, support will be included for the
 	  Acer Labs Inc. (ALI) M1514 and M1543 motherboard I2C interfaces.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-ali15x3.
 config I2C_AMD756
 	tristate "AMD 756/766/768/8111 and nVidia nForce"
 	depends on I2C && PCI
 	help
 	  If you say yes to this option, support will be included for the AMD
 	  756/766/768 mainboard I2C interfaces.  The driver also includes
 	  support for the first (SMBus 1.0) I2C interface of the AMD 8111 and
 	  the nVidia nForce I2C interface.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-amd756.
 config I2C_AMD756_S4882
 	tristate "SMBus multiplexing on the Tyan S4882"
 	depends on I2C_AMD756 && EXPERIMENTAL
 	help
 	  Enabling this option will add specific SMBus support for the Tyan
 	  S4882 motherboard.  On this 4-CPU board, the SMBus is multiplexed
 	  over 8 different channels, where the various memory module EEPROMs
 	  and temperature sensors live.  Saying yes here will give you access
 	  to these in addition to the trunk.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-amd756-s4882.
 config I2C_AMD8111
 	tristate "AMD 8111"
 	depends on I2C && PCI
 	help
 	  If you say yes to this option, support will be included for the
 	  second (SMBus 2.0) AMD 8111 mainboard I2C interface.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-amd8111.
 config I2C_AU1550
 	tristate "Au1550 SMBus interface"
 	depends on I2C && SOC_AU1550
 	help
 	  If you say yes to this option, support will be included for the
 	  Au1550 SMBus interface.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-au1550.
 config I2C_ELEKTOR
 	tristate "Elektor ISA card"
 	depends on I2C && ISA && BROKEN_ON_SMP
 	select I2C_ALGOPCF
 	help
 	  This supports the PCF8584 ISA bus I2C adapter.  Say Y if you own
 	  such an adapter.
 	  This support is also available as a module.  If so, the module
 	  will be called i2c-elektor.
 config I2C_HYDRA
 	tristate "CHRP Apple Hydra Mac I/O I2C interface"
 	depends on I2C && PCI && PPC_CHRP && EXPERIMENTAL
 	select I2C_ALGOBIT
 	help
 	  This supports the use of the I2C interface in the Apple Hydra Mac
 	  I/O chip on some CHRP machines (e.g. the LongTrail).  Say Y if you
 	  have such a machine.
 	  This support is also available as a module.  If so, the module
 	  will be called i2c-hydra.
 config I2C_I801
 	tristate "Intel 82801 (ICH)"
 	depends on I2C && PCI
 	help
 	  If you say yes to this option, support will be included for the Intel
 	  801 family of mainboard I2C interfaces.  Specifically, the following
 	  versions of the chipset are supported:
 	    82801AA
 	    82801AB
 	    82801BA
 	    82801CA/CAM
 	    82801DB
 	    82801EB/ER (ICH5/ICH5R)
 	    6300ESB
 	    ICH6
 	    ICH7
 	    ESB2
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-i801.
 config I2C_I810
 	tristate "Intel 810/815"
 	depends on I2C && PCI
 	select I2C_ALGOBIT
 	help
 	  If you say yes to this option, support will be included for the Intel
 	  810/815 family of mainboard I2C interfaces.  Specifically, the
 	  following versions of the chipset are supported:
 	    i810AA
 	    i810AB
 	    i810E
 	    i815
 	    i845G
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-i810.
 config I2C_PXA
 	tristate "Intel PXA2XX I2C adapter (EXPERIMENTAL)"
 	depends on I2C && EXPERIMENTAL && ARCH_PXA
 	help
 	  If you have devices in the PXA I2C bus, say yes to this option.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-pxa.
 config I2C_PXA_SLAVE
 	bool "Intel PXA2XX I2C Slave comms support"
 	depends on I2C_PXA
 	help
 	  Support I2C slave mode communications on the PXA I2C bus.  This
 	  is necessary for systems where the PXA may be a target on the
 	  I2C bus.
 config I2C_PIIX4
 	tristate "Intel PIIX4"
 	depends on I2C && PCI
 	help
 	  If you say yes to this option, support will be included for the Intel
 	  PIIX4 family of mainboard I2C interfaces.  Specifically, the following
 	  versions of the chipset are supported:
 	    Intel PIIX4
 	    Intel 440MX
 	    Serverworks OSB4
 	    Serverworks CSB5
 	    Serverworks CSB6
 	    SMSC Victory66
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-piix4.
 config I2C_IBM_IIC
 	tristate "IBM PPC 4xx on-chip I2C interface"
 	depends on IBM_OCP && I2C
 	help
 	  Say Y here if you want to use IIC peripheral found on
 	  embedded IBM PPC 4xx based systems.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-ibm_iic.
 config I2C_IOP3XX
 	tristate "Intel IOP3xx and IXP4xx on-chip I2C interface"
 	depends on (ARCH_IOP3XX || ARCH_IXP4XX) && I2C
 	help
 	  Say Y here if you want to use the IIC bus controller on
 	  the Intel IOP3xx I/O Processors or IXP4xx Network Processors.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-iop3xx.
 config I2C_ISA
 	tristate
 	depends on I2C
 config I2C_ITE
 	tristate "ITE I2C Adapter"
 	depends on I2C && MIPS_ITE8172
 	select I2C_ALGOITE
 	help
 	  This supports the ITE8172 I2C peripheral found on some MIPS
 	  systems. Say Y if you have one of these. You should also say Y for
 	  the ITE I2C driver algorithm support above.
 	  This support is also available as a module.  If so, the module
 	  will be called i2c-ite.
 config I2C_IXP4XX
 	tristate "IXP4xx GPIO-Based I2C Interface"
 	depends on I2C && ARCH_IXP4XX
 	select I2C_ALGOBIT
 	help
 	  Say Y here if you have an Intel IXP4xx(420,421,422,425) based
 	  system and are using GPIO lines for an I2C bus.
 	  This support is also available as a module. If so, the module
 	  will be called i2c-ixp4xx.
 config I2C_IXP2000
 	tristate "IXP2000 GPIO-Based I2C Interface"
 	depends on I2C && ARCH_IXP2000
 	select I2C_ALGOBIT
 	help
 	  Say Y here if you have an Intel IXP2000(2400, 2800, 2850) based
 	  system and are using GPIO lines for an I2C bus.
 	  This support is also available as a module. If so, the module
 	  will be called i2c-ixp2000.
-config I2C_KEYWEST
+config I2C_POWERMAC
-	tristate "Powermac Keywest I2C interface"
+	tristate "Powermac I2C interface"
 	depends on I2C && PPC_PMAC
+	default y
 	help
-	  This supports the use of the I2C interface in the combo-I/O
+	  This exposes the various PowerMac i2c interfaces to the linux i2c
-	  chip on recent Apple machines.  Say Y if you have such a machine.
+	  layer and to userland. It is used by various drivers on the powemac
+	  platform, thus should generally be enabled.
-	  This support is also available as a module.  If so, the module
-	  will be called i2c-keywest.
-config I2C_PMAC_SMU
-	tristate "Powermac SMU I2C interface"
-	depends on I2C && PMAC_SMU
-	help
-	  This supports the use of the I2C interface in the SMU
-	  chip on recent Apple machines like the iMac G5.  It is used
-	  among others by the thermal control driver for those machines.
-	  Say Y if you have such a machine.
 	  This support is also available as a module.  If so, the module
-	  will be called i2c-pmac-smu.
+	  will be called i2c-powermac.
 config I2C_MPC
 	tristate "MPC107/824x/85xx/52xx"
 	depends on I2C && PPC32
 	help
 	  If you say yes to this option, support will be included for the
 	  built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC8245 and
 	  MPC85xx family processors. The driver may also work on 52xx
 	  family processors, though interrupts are known not to work.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-mpc.
 config I2C_NFORCE2
 	tristate "Nvidia nForce2, nForce3 and nForce4"
 	depends on I2C && PCI
 	help
 	  If you say yes to this option, support will be included for the Nvidia
 	  nForce2, nForce3 and nForce4 families of mainboard I2C interfaces.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-nforce2.
 config I2C_PARPORT
 	tristate "Parallel port adapter"
 	depends on I2C && PARPORT
 	select I2C_ALGOBIT
 	help
 	  This supports parallel port I2C adapters such as the ones made by
 	  Philips or Velleman, Analog Devices evaluation boards, and more.
 	  Basically any adapter using the parallel port as an I2C bus with
 	  no extra chipset is supported by this driver, or could be.
 	  This driver is a replacement for (and was inspired by) an older
 	  driver named i2c-philips-par.  The new driver supports more devices,
 	  and makes it easier to add support for new devices.
 	  Another driver exists, named i2c-parport-light, which doesn't depend
 	  on the parport driver.  This is meant for embedded systems. Don't say
 	  Y here if you intend to say Y or M there.
 	  This support is also available as a module.  If so, the module
 	  will be called i2c-parport.
 config I2C_PARPORT_LIGHT
 	tristate "Parallel port adapter (light)"
 	depends on I2C
 	select I2C_ALGOBIT
 	help
 	  This supports parallel port I2C adapters such as the ones made by
 	  Philips or Velleman, Analog Devices evaluation boards, and more.
 	  Basically any adapter using the parallel port as an I2C bus with
 	  no extra chipset is supported by this driver, or could be.
 	  This driver is a light version of i2c-parport.  It doesn't depend
 	  on the parport driver, and uses direct I/O access instead.  This
 	  might be prefered on embedded systems where wasting memory for
 	  the clean but heavy parport handling is not an option.  The
 	  drawback is a reduced portability and the impossibility to
 	  dasiy-chain other parallel port devices.
 	  Don't say Y here if you said Y or M to i2c-parport.  Saying M to
 	  both is possible but both modules should not be loaded at the same
 	  time.
 	  This support is also available as a module.  If so, the module
 	  will be called i2c-parport-light.
 config I2C_PROSAVAGE
 	tristate "S3/VIA (Pro)Savage"
 	depends on I2C && PCI
 	select I2C_ALGOBIT
 	help
 	  If you say yes to this option, support will be included for the
 	  I2C bus and DDC bus of the S3VIA embedded Savage4 and ProSavage8
 	  graphics processors.
 	  chipsets supported:
 	    S3/VIA KM266/VT8375 aka ProSavage8
 	    S3/VIA KM133/VT8365 aka Savage4
 	  This support is also available as a module.  If so, the module
 	  will be called i2c-prosavage.
 config I2C_RPXLITE
 	tristate "Embedded Planet RPX Lite/Classic support"
 	depends on (RPXLITE || RPXCLASSIC) && I2C
 	select I2C_ALGO8XX
 config I2C_S3C2410
 	tristate "S3C2410 I2C Driver"
 	depends on I2C && ARCH_S3C2410
 	help
 	  Say Y here to include support for I2C controller in the
 	  Samsung S3C2410 based System-on-Chip devices.
 config I2C_SAVAGE4
 	tristate "S3 Savage 4"
 	depends on I2C && PCI && EXPERIMENTAL
 	select I2C_ALGOBIT
 	help
 	  If you say yes to this option, support will be included for the
 	  S3 Savage 4 I2C interface.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-savage4.
 config I2C_SIBYTE
 	tristate "SiByte SMBus interface"
 	depends on SIBYTE_SB1xxx_SOC && I2C
 	help
 	  Supports the SiByte SOC on-chip I2C interfaces (2 channels).
 config SCx200_I2C
 	tristate "NatSemi SCx200 I2C using GPIO pins"
 	depends on SCx200_GPIO && I2C
 	select I2C_ALGOBIT
 	help
 	  Enable the use of two GPIO pins of a SCx200 processor as an I2C bus.
 	  If you don't know what to do here, say N.
 	  This support is also available as a module.  If so, the module
 	  will be called scx200_i2c.
 config SCx200_I2C_SCL
 	int "GPIO pin used for SCL"
 	depends on SCx200_I2C
 	default "12"
 	help
 	  Enter the GPIO pin number used for the SCL signal.  This value can
 	  also be specified with a module parameter.
 config SCx200_I2C_SDA
 	int "GPIO pin used for SDA"
 	depends on SCx200_I2C
 	default "13"
 	help
 	  Enter the GPIO pin number used for the SSA signal.  This value can
 	  also be specified with a module parameter.
 config SCx200_ACB
 	tristate "NatSemi SCx200 ACCESS.bus"
 	depends on I2C && PCI
 	help
 	  Enable the use of the ACCESS.bus controllers of a SCx200 processor.
 	  If you don't know what to do here, say N.
 	  This support is also available as a module.  If so, the module
 	  will be called scx200_acb.
 config I2C_SIS5595
 	tristate "SiS 5595"
 	depends on I2C && PCI
 	help
 	  If you say yes to this option, support will be included for the
 	  SiS5595 SMBus (a subset of I2C) interface.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-sis5595.
 config I2C_SIS630
 	tristate "SiS 630/730"
 	depends on I2C && PCI
 	help
 	  If you say yes to this option, support will be included for the
 	  SiS630 and SiS730 SMBus (a subset of I2C) interface.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-sis630.
 config I2C_SIS96X
 	tristate "SiS 96x"
 	depends on I2C && PCI
 	help
 	  If you say yes to this option, support will be included for the SiS
 	  96x SMBus (a subset of I2C) interfaces.  Specifically, the following
 	  chipsets are supported:
 	    645/961
 	    645DX/961
 	    645DX/962
 	    648/961
 	    650/961
 	    735
 	    745
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-sis96x.
 config I2C_STUB
 	tristate "I2C/SMBus Test Stub"
 	depends on I2C && EXPERIMENTAL && 'm'
 	default 'n'
 	help
 	  This module may be useful to developers of SMBus client drivers,
 	  especially for certain kinds of sensor chips.
 	  If you do build this module, be sure to read the notes and warnings
 	  in <file:Documentation/i2c/i2c-stub>.
 	  If you don't know what to do here, definitely say N.
 config I2C_VIA
 	tristate "VIA 82C586B"
 	depends on I2C && PCI && EXPERIMENTAL
 	select I2C_ALGOBIT
 	help
 	  If you say yes to this option, support will be included for the VIA
           82C586B I2C interface
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-via.
 config I2C_VIAPRO
 	tristate "VIA 82C596/82C686/823x"
 	depends on I2C && PCI
 	help
 	  If you say yes to this option, support will be included for the VIA
 	  82C596/82C686/823x I2C interfaces.  Specifically, the following
 	  chipsets are supported:
 	  82C596A/B
 	  82C686A/B
 	  8231
 	  8233
 	  8233A
 	  8235
 	  8237
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-viapro.
 config I2C_VOODOO3
 	tristate "Voodoo 3"
 	depends on I2C && PCI
 	select I2C_ALGOBIT
 	help
 	  If you say yes to this option, support will be included for the
 	  Voodoo 3 I2C interface.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-voodoo3.
 config I2C_PCA_ISA
 	tristate "PCA9564 on an ISA bus"
 	depends on I2C
 	select I2C_ALGOPCA
 	help
 	  This driver supports ISA boards using the Philips PCA 9564
 	  Parallel bus to I2C bus controller
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-pca-isa.
 config I2C_MV64XXX
 	tristate "Marvell mv64xxx I2C Controller"
 	depends on I2C && MV64X60 && EXPERIMENTAL
 	help
 	  If you say yes to this option, support will be included for the
 	  built-in I2C interface on the Marvell 64xxx line of host bridges.
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-mv64xxx.

drivers/i2c/busses/Makefile

Diff comments View file @ a28d3af

 #
 # Makefile for the i2c bus drivers.
 #
 obj-$(CONFIG_I2C_ALI1535)	+= i2c-ali1535.o
 obj-$(CONFIG_I2C_ALI1563)	+= i2c-ali1563.o
 obj-$(CONFIG_I2C_ALI15X3)	+= i2c-ali15x3.o
 obj-$(CONFIG_I2C_AMD756)	+= i2c-amd756.o
 obj-$(CONFIG_I2C_AMD756_S4882)	+= i2c-amd756-s4882.o
 obj-$(CONFIG_I2C_AMD8111)	+= i2c-amd8111.o
 obj-$(CONFIG_I2C_AU1550)	+= i2c-au1550.o
 obj-$(CONFIG_I2C_ELEKTOR)	+= i2c-elektor.o
 obj-$(CONFIG_I2C_HYDRA)		+= i2c-hydra.o
 obj-$(CONFIG_I2C_I801)		+= i2c-i801.o
 obj-$(CONFIG_I2C_I810)		+= i2c-i810.o
 obj-$(CONFIG_I2C_IBM_IIC)	+= i2c-ibm_iic.o
 obj-$(CONFIG_I2C_IOP3XX)	+= i2c-iop3xx.o
 obj-$(CONFIG_I2C_ISA)		+= i2c-isa.o
 obj-$(CONFIG_I2C_ITE)		+= i2c-ite.o
 obj-$(CONFIG_I2C_IXP2000)	+= i2c-ixp2000.o
 obj-$(CONFIG_I2C_IXP4XX)	+= i2c-ixp4xx.o
-obj-$(CONFIG_I2C_KEYWEST)	+= i2c-keywest.o
+obj-$(CONFIG_I2C_POWERMAC)	+= i2c-powermac.o
-obj-$(CONFIG_I2C_PMAC_SMU)	+= i2c-pmac-smu.o
 obj-$(CONFIG_I2C_MPC)		+= i2c-mpc.o
 obj-$(CONFIG_I2C_MV64XXX)	+= i2c-mv64xxx.o
 obj-$(CONFIG_I2C_NFORCE2)	+= i2c-nforce2.o
 obj-$(CONFIG_I2C_PARPORT)	+= i2c-parport.o
 obj-$(CONFIG_I2C_PARPORT_LIGHT)	+= i2c-parport-light.o
 obj-$(CONFIG_I2C_PCA_ISA)	+= i2c-pca-isa.o
 obj-$(CONFIG_I2C_PIIX4)		+= i2c-piix4.o
 obj-$(CONFIG_I2C_PROSAVAGE)	+= i2c-prosavage.o
 obj-$(CONFIG_I2C_PXA)		+= i2c-pxa.o
 obj-$(CONFIG_I2C_RPXLITE)	+= i2c-rpx.o
 obj-$(CONFIG_I2C_S3C2410)	+= i2c-s3c2410.o
 obj-$(CONFIG_I2C_SAVAGE4)	+= i2c-savage4.o
 obj-$(CONFIG_I2C_SIBYTE)	+= i2c-sibyte.o
 obj-$(CONFIG_I2C_SIS5595)	+= i2c-sis5595.o
 obj-$(CONFIG_I2C_SIS630)	+= i2c-sis630.o
 obj-$(CONFIG_I2C_SIS96X)	+= i2c-sis96x.o
 obj-$(CONFIG_I2C_STUB)		+= i2c-stub.o
 obj-$(CONFIG_I2C_VIA)		+= i2c-via.o
 obj-$(CONFIG_I2C_VIAPRO)	+= i2c-viapro.o
 obj-$(CONFIG_I2C_VOODOO3)	+= i2c-voodoo3.o
 obj-$(CONFIG_SCx200_ACB)	+= scx200_acb.o
 obj-$(CONFIG_SCx200_I2C)	+= scx200_i2c.o
 ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
 EXTRA_CFLAGS += -DDEBUG
 endif

drivers/i2c/busses/i2c-keywest.c

View file @ a28d3af

1	/*		File was deleted
2	i2c Support for Apple Keywest I2C Bus Controller
3
4	Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
5
6	Original work by
7
8	Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
9
10	This program is free software; you can redistribute it and/or modify
11	it under the terms of the GNU General Public License as published by
12	the Free Software Foundation; either version 2 of the License, or
13	(at your option) any later version.
14
15	This program is distributed in the hope that it will be useful,
16	but WITHOUT ANY WARRANTY; without even the implied warranty of
17	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18	GNU General Public License for more details.
19
20	You should have received a copy of the GNU General Public License
21	along with this program; if not, write to the Free Software
22	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23
24	Changes:
25
26	2001/12/13 BenH New implementation
27	2001/12/15 BenH Add support for "byte" and "quick"
28	transfers. Add i2c_xfer routine.
29	2003/09/21 BenH Rework state machine with Paulus help
30	2004/01/21 BenH Merge in Greg KH changes, polled mode is back
31	2004/02/05 BenH Merge 64 bits fixes from the g5 ppc64 tree
32
33	My understanding of the various modes supported by keywest are:
34
35	- Dumb mode : not implemented, probably direct tweaking of lines
36	- Standard mode : simple i2c transaction of type
37	S Addr R/W A Data A Data ... T
38	- Standard sub mode : combined 8 bit subaddr write with data read
39	S Addr R/W A SubAddr A Data A Data ... T
40	- Combined mode : Subaddress and Data sequences appended with no stop
41	S Addr R/W A SubAddr S Addr R/W A Data A Data ... T
42
43	Currently, this driver uses only Standard mode for i2c xfer, and
44	smbus byte & quick transfers ; and uses StandardSub mode for
45	other smbus transfers instead of combined as we need that for the
46	sound driver to be happy
47	*/
48
49	#include <linux/module.h>
50	#include <linux/kernel.h>
51	#include <linux/ioport.h>
52	#include <linux/pci.h>
53	#include <linux/types.h>
54	#include <linux/delay.h>
55	#include <linux/i2c.h>
56	#include <linux/init.h>
57	#include <linux/mm.h>
58	#include <linux/timer.h>
59	#include <linux/spinlock.h>
60	#include <linux/completion.h>
61	#include <linux/interrupt.h>
62
63	#include <asm/io.h>
64	#include <asm/prom.h>
65	#include <asm/machdep.h>
66	#include <asm/pmac_feature.h>
67	#include <asm/pmac_low_i2c.h>
68
69	#include "i2c-keywest.h"
70
71	#undef POLLED_MODE
72
73	/* Some debug macros */
74	#define WRONG_STATE(name) do {\
75	pr_debug("KW: wrong state. Got %s, state: %s (isr: %02x)\n", \
76	name, __kw_state_names[iface->state], isr); \
77	} while(0)
78
79	#ifdef DEBUG
80	static const char *__kw_state_names[] = {
81	"state_idle",
82	"state_addr",
83	"state_read",
84	"state_write",
85	"state_stop",
86	"state_dead"
87	};
88	#endif /* DEBUG */
89
90	MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
91	MODULE_DESCRIPTION("I2C driver for Apple's Keywest");
92	MODULE_LICENSE("GPL");
93
94	#ifdef POLLED_MODE
95	/* Don't schedule, the g5 fan controller is too
96	* timing sensitive
97	*/
98	static u8
99	wait_interrupt(struct keywest_iface* iface)
100	{
101	int i;
102	u8 isr;
103
104	for (i = 0; i < 200000; i++) {
105	isr = read_reg(reg_isr) & KW_I2C_IRQ_MASK;
106	if (isr != 0)
107	return isr;
108	udelay(10);
109	}
110	return isr;
111	}
112	#endif /* POLLED_MODE */
113
114	static void
115	do_stop(struct keywest_iface* iface, int result)
116	{
117	write_reg(reg_control, KW_I2C_CTL_STOP);
118	iface->state = state_stop;
119	iface->result = result;
120	}
121
122	/* Main state machine for standard & standard sub mode */
123	static void
124	handle_interrupt(struct keywest_iface *iface, u8 isr)
125	{
126	int ack;
127
128	if (isr == 0) {
129	if (iface->state != state_stop) {
130	pr_debug("KW: Timeout !\n");
131	do_stop(iface, -EIO);
132	}
133	if (iface->state == state_stop) {
134	ack = read_reg(reg_status);
135	if (!(ack & KW_I2C_STAT_BUSY)) {
136	iface->state = state_idle;
137	write_reg(reg_ier, 0x00);
138	#ifndef POLLED_MODE
139	complete(&iface->complete);
140	#endif /* POLLED_MODE */
141	}
142	}
143	return;
144	}
145
146	if (isr & KW_I2C_IRQ_ADDR) {
147	ack = read_reg(reg_status);
148	if (iface->state != state_addr) {
149	write_reg(reg_isr, KW_I2C_IRQ_ADDR);
150	WRONG_STATE("KW_I2C_IRQ_ADDR");
151	do_stop(iface, -EIO);
152	return;
153	}
154	if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
155	iface->state = state_stop;
156	iface->result = -ENODEV;
157	pr_debug("KW: NAK on address\n");
158	} else {
159	/* Handle rw "quick" mode */
160	if (iface->datalen == 0) {
161	do_stop(iface, 0);
162	} else if (iface->read_write == I2C_SMBUS_READ) {
163	iface->state = state_read;
164	if (iface->datalen > 1)
165	write_reg(reg_control, KW_I2C_CTL_AAK);
166	} else {
167	iface->state = state_write;
168	write_reg(reg_data, *(iface->data++));
169	iface->datalen--;
170	}
171	}
172	write_reg(reg_isr, KW_I2C_IRQ_ADDR);
173	}
174
175	if (isr & KW_I2C_IRQ_DATA) {
176	if (iface->state == state_read) {
177	*(iface->data++) = read_reg(reg_data);
178	write_reg(reg_isr, KW_I2C_IRQ_DATA);
179	iface->datalen--;
180	if (iface->datalen == 0)
181	iface->state = state_stop;
182	else if (iface->datalen == 1)
183	write_reg(reg_control, 0);
184	} else if (iface->state == state_write) {
185	/* Check ack status */
186	ack = read_reg(reg_status);
187	if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
188	pr_debug("KW: nack on data write (%x): %x\n",
189	iface->data[-1], ack);
190	do_stop(iface, -EIO);
191	} else if (iface->datalen) {
192	write_reg(reg_data, *(iface->data++));
193	iface->datalen--;
194	} else {
195	write_reg(reg_control, KW_I2C_CTL_STOP);
196	iface->state = state_stop;
197	iface->result = 0;
198	}
199	write_reg(reg_isr, KW_I2C_IRQ_DATA);
200	} else {
201	write_reg(reg_isr, KW_I2C_IRQ_DATA);
202	WRONG_STATE("KW_I2C_IRQ_DATA");
203	if (iface->state != state_stop)
204	do_stop(iface, -EIO);
205	}
206	}
207
208	if (isr & KW_I2C_IRQ_STOP) {
209	write_reg(reg_isr, KW_I2C_IRQ_STOP);
210	if (iface->state != state_stop) {
211	WRONG_STATE("KW_I2C_IRQ_STOP");
212	iface->result = -EIO;
213	}
214	iface->state = state_idle;
215	write_reg(reg_ier, 0x00);
216	#ifndef POLLED_MODE
217	complete(&iface->complete);
218	#endif /* POLLED_MODE */
219	}
220
221	if (isr & KW_I2C_IRQ_START)
222	write_reg(reg_isr, KW_I2C_IRQ_START);
223	}
224
225	#ifndef POLLED_MODE
226
227	/* Interrupt handler */
228	static irqreturn_t
229	keywest_irq(int irq, void dev_id, struct pt_regs regs)
230	{
231	struct keywest_iface iface = (struct keywest_iface )dev_id;
232	unsigned long flags;
233
234	spin_lock_irqsave(&iface->lock, flags);
235	del_timer(&iface->timeout_timer);
236	handle_interrupt(iface, read_reg(reg_isr));
237	if (iface->state != state_idle) {
238	iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
239	add_timer(&iface->timeout_timer);
240	}
241	spin_unlock_irqrestore(&iface->lock, flags);
242	return IRQ_HANDLED;
243	}
244
245	static void
246	keywest_timeout(unsigned long data)
247	{
248	struct keywest_iface iface = (struct keywest_iface )data;
249	unsigned long flags;
250
251	pr_debug("timeout !\n");
252	spin_lock_irqsave(&iface->lock, flags);
253	handle_interrupt(iface, read_reg(reg_isr));
254	if (iface->state != state_idle) {
255	iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
256	add_timer(&iface->timeout_timer);
257	}
258	spin_unlock_irqrestore(&iface->lock, flags);
259	}
260
261	#endif /* POLLED_MODE */
262
263	/*
264	* SMBUS-type transfer entrypoint
265	*/
266	static s32
267	keywest_smbus_xfer( struct i2c_adapter* adap,
268	u16 addr,
269	unsigned short flags,
270	char read_write,
271	u8 command,
272	int size,
273	union i2c_smbus_data* data)
274	{
275	struct keywest_chan* chan = i2c_get_adapdata(adap);
276	struct keywest_iface* iface = chan->iface;
277	int len;
278	u8* buffer;
279	u16 cur_word;
280	int rc = 0;
281
282	if (iface->state == state_dead)
283	return -ENXIO;
284
285	/* Prepare datas & select mode */
286	iface->cur_mode &= ~KW_I2C_MODE_MODE_MASK;
287	switch (size) {
288	case I2C_SMBUS_QUICK:
289	len = 0;
290	buffer = NULL;
291	iface->cur_mode \|= KW_I2C_MODE_STANDARD;
292	break;
293	case I2C_SMBUS_BYTE:
294	len = 1;
295	buffer = &data->byte;
296	iface->cur_mode \|= KW_I2C_MODE_STANDARD;
297	break;
298	case I2C_SMBUS_BYTE_DATA:
299	len = 1;
300	buffer = &data->byte;
301	iface->cur_mode \|= KW_I2C_MODE_STANDARDSUB;
302	break;
303	case I2C_SMBUS_WORD_DATA:
304	len = 2;
305	cur_word = cpu_to_le16(data->word);
306	buffer = (u8 *)&cur_word;
307	iface->cur_mode \|= KW_I2C_MODE_STANDARDSUB;
308	break;
309	case I2C_SMBUS_BLOCK_DATA:
310	len = data->block[0];
311	buffer = &data->block[1];
312	iface->cur_mode \|= KW_I2C_MODE_STANDARDSUB;
313	break;
314	default:
315	return -1;
316	}
317
318	/* Turn a standardsub read into a combined mode access */
319	if (read_write == I2C_SMBUS_READ
320	&& (iface->cur_mode & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB) {
321	iface->cur_mode &= ~KW_I2C_MODE_MODE_MASK;
322	iface->cur_mode \|= KW_I2C_MODE_COMBINED;
323	}
324
325	/* Original driver had this limitation */
326	if (len > 32)
327	len = 32;
328
329	if (pmac_low_i2c_lock(iface->node))
330	return -ENXIO;
331
332	pr_debug("chan: %d, addr: 0x%x, transfer len: %d, read: %d\n",
333	chan->chan_no, addr, len, read_write == I2C_SMBUS_READ);
334
335	iface->data = buffer;
336	iface->datalen = len;
337	iface->state = state_addr;
338	iface->result = 0;
339	iface->read_write = read_write;
340
341	/* Setup channel & clear pending irqs */
342	write_reg(reg_isr, read_reg(reg_isr));
343	write_reg(reg_mode, iface->cur_mode \| (chan->chan_no << 4));
344	write_reg(reg_status, 0);
345
346	/* Set up address and r/w bit */
347	write_reg(reg_addr,
348	(addr << 1) \| ((read_write == I2C_SMBUS_READ) ? 0x01 : 0x00));
349
350	/* Set up the sub address */
351	if ((iface->cur_mode & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB
352	\|\| (iface->cur_mode & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_COMBINED)
353	write_reg(reg_subaddr, command);
354
355	#ifndef POLLED_MODE
356	/* Arm timeout */
357	iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
358	add_timer(&iface->timeout_timer);
359	#endif
360
361	/* Start sending address & enable interrupt*/
362	write_reg(reg_control, KW_I2C_CTL_XADDR);
363	write_reg(reg_ier, KW_I2C_IRQ_MASK);
364
365	#ifdef POLLED_MODE
366	pr_debug("using polled mode...\n");
367	/* State machine, to turn into an interrupt handler */
368	while(iface->state != state_idle) {
369	unsigned long flags;
370
371	u8 isr = wait_interrupt(iface);
372	spin_lock_irqsave(&iface->lock, flags);
373	handle_interrupt(iface, isr);
374	spin_unlock_irqrestore(&iface->lock, flags);
375	}
376	#else /* POLLED_MODE */
377	pr_debug("using interrupt mode...\n");
378	wait_for_completion(&iface->complete);
379	#endif /* POLLED_MODE */
380
381	rc = iface->result;
382	pr_debug("transfer done, result: %d\n", rc);
383
384	if (rc == 0 && size == I2C_SMBUS_WORD_DATA && read_write == I2C_SMBUS_READ)
385	data->word = le16_to_cpu(cur_word);
386
387	/* Release sem */
388	pmac_low_i2c_unlock(iface->node);
389
390	return rc;
391	}
392
393	/*
394	* Generic i2c master transfer entrypoint
395	*/
396	static int
397	keywest_xfer( struct i2c_adapter *adap,
398	struct i2c_msg *msgs,
399	int num)
400	{
401	struct keywest_chan* chan = i2c_get_adapdata(adap);
402	struct keywest_iface* iface = chan->iface;
403	struct i2c_msg *pmsg;
404	int i, completed;
405	int rc = 0;
406
407	if (iface->state == state_dead)
408	return -ENXIO;
409
410	if (pmac_low_i2c_lock(iface->node))
411	return -ENXIO;
412
413	/* Set adapter to standard mode */
414	iface->cur_mode &= ~KW_I2C_MODE_MODE_MASK;
415	iface->cur_mode \|= KW_I2C_MODE_STANDARD;
416
417	completed = 0;
418	for (i = 0; rc >= 0 && i < num;) {
419	u8 addr;
420
421	pmsg = &msgs[i++];
422	addr = pmsg->addr;
423	if (pmsg->flags & I2C_M_TEN) {
424	printk(KERN_ERR "i2c-keywest: 10 bits addr not supported !\n");
425	rc = -EINVAL;
426	break;
427	}
428	pr_debug("xfer: chan: %d, doing %s %d bytes to 0x%02x - %d of %d messages\n",
429	chan->chan_no,
430	pmsg->flags & I2C_M_RD ? "read" : "write",
431	pmsg->len, addr, i, num);
432
433	/* Setup channel & clear pending irqs */
434	write_reg(reg_mode, iface->cur_mode \| (chan->chan_no << 4));
435	write_reg(reg_isr, read_reg(reg_isr));
436	write_reg(reg_status, 0);
437
438	iface->data = pmsg->buf;
439	iface->datalen = pmsg->len;
440	iface->state = state_addr;
441	iface->result = 0;
442	if (pmsg->flags & I2C_M_RD)
443	iface->read_write = I2C_SMBUS_READ;
444	else
445	iface->read_write = I2C_SMBUS_WRITE;
446
447	/* Set up address and r/w bit */
448	if (pmsg->flags & I2C_M_REV_DIR_ADDR)
449	addr ^= 1;
450	write_reg(reg_addr,
451	(addr << 1) \|
452	((iface->read_write == I2C_SMBUS_READ) ? 0x01 : 0x00));
453
454	#ifndef POLLED_MODE
455	/* Arm timeout */
456	iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
457	add_timer(&iface->timeout_timer);
458	#endif
459
460	/* Start sending address & enable interrupt*/
461	write_reg(reg_ier, KW_I2C_IRQ_MASK);
462	write_reg(reg_control, KW_I2C_CTL_XADDR);
463
464	#ifdef POLLED_MODE
465	pr_debug("using polled mode...\n");
466	/* State machine, to turn into an interrupt handler */
467	while(iface->state != state_idle) {
468	u8 isr = wait_interrupt(iface);
469	handle_interrupt(iface, isr);
470	}
471	#else /* POLLED_MODE */
472	pr_debug("using interrupt mode...\n");
473	wait_for_completion(&iface->complete);
474	#endif /* POLLED_MODE */
475
476	rc = iface->result;
477	if (rc == 0)
478	completed++;
479	pr_debug("transfer done, result: %d\n", rc);
480	}
481
482	/* Release sem */
483	pmac_low_i2c_unlock(iface->node);
484
485	return completed;
486	}
487
488	static u32
489	keywest_func(struct i2c_adapter * adapter)
490	{
491	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
492	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
493	I2C_FUNC_SMBUS_BLOCK_DATA;
494	}
495
496	/* For now, we only handle combined mode (smbus) */
497	static struct i2c_algorithm keywest_algorithm = {
498	.smbus_xfer = keywest_smbus_xfer,
499	.master_xfer = keywest_xfer,
500	.functionality = keywest_func,
501	};
502
503
504	static int
505	create_iface(struct device_node np, struct device dev)
506	{
507	unsigned long steps;
508	unsigned bsteps, tsize, i, nchan;
509	struct keywest_iface* iface;
510	u32 psteps, prate, *addrp;
511	int rc;
512
513	if (np->n_intrs < 1) {
514	printk(KERN_ERR "%s: Missing interrupt !\n",
515	np->full_name);
516	return -ENODEV;
517	}
518	addrp = (u32 *)get_property(np, "AAPL,address", NULL);
519	if (addrp == NULL) {
520	printk(KERN_ERR "%s: Can't find address !\n",
521	np->full_name);
522	return -ENODEV;
523	}
524
525	if (pmac_low_i2c_lock(np))
526	return -ENODEV;
527
528	psteps = (u32 *)get_property(np, "AAPL,address-step", NULL);
529	steps = psteps ? (*psteps) : 0x10;
530
531	/* Hrm... maybe we can be smarter here */
532	for (bsteps = 0; (steps & 0x01) == 0; bsteps++)
533	steps >>= 1;
534
535	if (np->parent->name[0] == 'u')
536	nchan = 2;
537	else
538	nchan = 1;
539
540	tsize = sizeof(struct keywest_iface) +
541	(sizeof(struct keywest_chan) + 4) * nchan;
542	iface = kzalloc(tsize, GFP_KERNEL);
543	if (iface == NULL) {
544	printk(KERN_ERR "i2c-keywest: can't allocate inteface !\n");
545	pmac_low_i2c_unlock(np);
546	return -ENOMEM;
547	}
548	spin_lock_init(&iface->lock);
549	init_completion(&iface->complete);
550	iface->node = of_node_get(np);
551	iface->bsteps = bsteps;
552	iface->chan_count = nchan;
553	iface->state = state_idle;
554	iface->irq = np->intrs[0].line;
555	iface->channels = (struct keywest_chan *)
556	(((unsigned long)(iface + 1) + 3UL) & ~3UL);
557	iface->base = ioremap(*addrp, 0x1000);
558	if (!iface->base) {
559	printk(KERN_ERR "i2c-keywest: can't map inteface !\n");
560	kfree(iface);
561	pmac_low_i2c_unlock(np);
562	return -ENOMEM;
563	}
564
565	#ifndef POLLED_MODE
566	init_timer(&iface->timeout_timer);
567	iface->timeout_timer.function = keywest_timeout;
568	iface->timeout_timer.data = (unsigned long)iface;
569	#endif
570
571	/* Select interface rate */
572	iface->cur_mode = KW_I2C_MODE_100KHZ;
573	prate = (u32 *)get_property(np, "AAPL,i2c-rate", NULL);
574	if (prate) switch(*prate) {
575	case 100:
576	iface->cur_mode = KW_I2C_MODE_100KHZ;
577	break;
578	case 50:
579	iface->cur_mode = KW_I2C_MODE_50KHZ;
580	break;
581	case 25:
582	iface->cur_mode = KW_I2C_MODE_25KHZ;
583	break;
584	default:
585	printk(KERN_WARNING "i2c-keywest: unknown rate %ldKhz, using 100KHz\n",
586	(long)*prate);
587	}
588
589	/* Select standard mode by default */
590	iface->cur_mode \|= KW_I2C_MODE_STANDARD;
591
592	/* Write mode */
593	write_reg(reg_mode, iface->cur_mode);
594
595	/* Switch interrupts off & clear them*/
596	write_reg(reg_ier, 0x00);
597	write_reg(reg_isr, KW_I2C_IRQ_MASK);
598
599	#ifndef POLLED_MODE
600	/* Request chip interrupt */
601	rc = request_irq(iface->irq, keywest_irq, SA_INTERRUPT, "keywest i2c", iface);
602	if (rc) {
603	printk(KERN_ERR "i2c-keywest: can't get IRQ %d !\n", iface->irq);
604	iounmap(iface->base);
605	kfree(iface);
606	pmac_low_i2c_unlock(np);
607	return -ENODEV;
608	}
609	#endif /* POLLED_MODE */
610
611	pmac_low_i2c_unlock(np);
612	dev_set_drvdata(dev, iface);
613
614	for (i=0; i<nchan; i++) {
615	struct keywest_chan* chan = &iface->channels[i];
616
617	sprintf(chan->adapter.name, "%s %d", np->parent->name, i);
618	chan->iface = iface;
619	chan->chan_no = i;
620	chan->adapter.algo = &keywest_algorithm;
621	chan->adapter.algo_data = NULL;
622	chan->adapter.client_register = NULL;
623	chan->adapter.client_unregister = NULL;
624	i2c_set_adapdata(&chan->adapter, chan);
625	chan->adapter.dev.parent = dev;
626
627	rc = i2c_add_adapter(&chan->adapter);
628	if (rc) {
629	printk("i2c-keywest.c: Adapter %s registration failed\n",
630	chan->adapter.name);
631	i2c_set_adapdata(&chan->adapter, NULL);
632	}
633	}
634
635	printk(KERN_INFO "Found KeyWest i2c on \"%s\", %d channel%s, stepping: %d bits\n",
636	np->parent->name, nchan, nchan > 1 ? "s" : "", bsteps);
637
638	return 0;
639	}
640
641	static int
642	dispose_iface(struct device *dev)
643	{
644	struct keywest_iface *iface = dev_get_drvdata(dev);
645	int i, rc;
646
647	/* Make sure we stop all activity */
648	if (pmac_low_i2c_lock(iface->node))
649	return -ENODEV;
650
651	#ifndef POLLED_MODE
652	spin_lock_irq(&iface->lock);
653	while (iface->state != state_idle) {
654	spin_unlock_irq(&iface->lock);
655	msleep(100);
656	spin_lock_irq(&iface->lock);
657	}
658	#endif /* POLLED_MODE */
659	iface->state = state_dead;
660	#ifndef POLLED_MODE
661	spin_unlock_irq(&iface->lock);
662	free_irq(iface->irq, iface);
663	#endif /* POLLED_MODE */
664
665	pmac_low_i2c_unlock(iface->node);
666
667	/* Release all channels */
668	for (i=0; i<iface->chan_count; i++) {
669	struct keywest_chan* chan = &iface->channels[i];
670	if (i2c_get_adapdata(&chan->adapter) == NULL)
671	continue;
672	rc = i2c_del_adapter(&chan->adapter);
673	i2c_set_adapdata(&chan->adapter, NULL);
674	/* We aren't that prepared to deal with this... */
675	if (rc)
676	printk("i2c-keywest.c: i2c_del_adapter failed, that's bad !\n");
677	}
678	iounmap(iface->base);
679	dev_set_drvdata(dev, NULL);
680	of_node_put(iface->node);
681	kfree(iface);
682
683	return 0;
684	}
685
686	static int
687	create_iface_macio(struct macio_dev* dev, const struct of_device_id *match)
688	{
689	return create_iface(dev->ofdev.node, &dev->ofdev.dev);
690	}
691
692	static int
693	dispose_iface_macio(struct macio_dev* dev)
694	{
695	return dispose_iface(&dev->ofdev.dev);
696	}
697
698	static int
699	create_iface_of_platform(struct of_device* dev, const struct of_device_id *match)
700	{
701	return create_iface(dev->node, &dev->dev);
702	}
703
704	static int
705	dispose_iface_of_platform(struct of_device* dev)
706	{
707	return dispose_iface(&dev->dev);
708	}
709
710	static struct of_device_id i2c_keywest_match[] =
711	{
712	{
713	.type = "i2c",
714	.compatible = "keywest"
715	},
716	{},
717	};
718
719	static struct macio_driver i2c_keywest_macio_driver =
720	{
721	.owner = THIS_MODULE,
722	.name = "i2c-keywest",
723	.match_table = i2c_keywest_match,
724	.probe = create_iface_macio,
725	.remove = dispose_iface_macio
726	};
727
728	static struct of_platform_driver i2c_keywest_of_platform_driver =
729	{
730	.owner = THIS_MODULE,
731	.name = "i2c-keywest",
732	.match_table = i2c_keywest_match,
733	.probe = create_iface_of_platform,
734	.remove = dispose_iface_of_platform
735	};
736
737	static int __init
738	i2c_keywest_init(void)
739	{
740	of_register_driver(&i2c_keywest_of_platform_driver);
741	macio_register_driver(&i2c_keywest_macio_driver);
742
743	return 0;
744	}
745
746	static void __exit
747	i2c_keywest_cleanup(void)
748	{
749	of_unregister_driver(&i2c_keywest_of_platform_driver);
750	macio_unregister_driver(&i2c_keywest_macio_driver);
751	}
752
753	module_init(i2c_keywest_init);
754	module_exit(i2c_keywest_cleanup);
755		1	/*

drivers/i2c/busses/i2c-keywest.h

View file @ a28d3af

1	#ifndef __I2C_KEYWEST_H__		File was deleted
2	#define __I2C_KEYWEST_H__
3
4	/* The Tumbler audio equalizer can be really slow sometimes */
5	#define POLL_TIMEOUT (2*HZ)
6
7	/* Register indices */
8	typedef enum {
9	reg_mode = 0,
10	reg_control,
11	reg_status,
12	reg_isr,
13	reg_ier,
14	reg_addr,
15	reg_subaddr,
16	reg_data
17	} reg_t;
18
19
20	/* Mode register */
21	#define KW_I2C_MODE_100KHZ 0x00
22	#define KW_I2C_MODE_50KHZ 0x01
23	#define KW_I2C_MODE_25KHZ 0x02
24	#define KW_I2C_MODE_DUMB 0x00
25	#define KW_I2C_MODE_STANDARD 0x04
26	#define KW_I2C_MODE_STANDARDSUB 0x08
27	#define KW_I2C_MODE_COMBINED 0x0C
28	#define KW_I2C_MODE_MODE_MASK 0x0C
29	#define KW_I2C_MODE_CHAN_MASK 0xF0
30
31	/* Control register */
32	#define KW_I2C_CTL_AAK 0x01
33	#define KW_I2C_CTL_XADDR 0x02
34	#define KW_I2C_CTL_STOP 0x04
35	#define KW_I2C_CTL_START 0x08
36
37	/* Status register */
38	#define KW_I2C_STAT_BUSY 0x01
39	#define KW_I2C_STAT_LAST_AAK 0x02
40	#define KW_I2C_STAT_LAST_RW 0x04
41	#define KW_I2C_STAT_SDA 0x08
42	#define KW_I2C_STAT_SCL 0x10
43
44	/* IER & ISR registers */
45	#define KW_I2C_IRQ_DATA 0x01
46	#define KW_I2C_IRQ_ADDR 0x02
47	#define KW_I2C_IRQ_STOP 0x04
48	#define KW_I2C_IRQ_START 0x08
49	#define KW_I2C_IRQ_MASK 0x0F
50
51	/* Physical interface */
52	struct keywest_iface
53	{
54	struct device_node *node;
55	void __iomem * base;
56	unsigned bsteps;
57	int irq;
58	spinlock_t lock;
59	struct keywest_chan *channels;
60	unsigned chan_count;
61	u8 cur_mode;
62	char read_write;
63	u8 *data;
64	unsigned datalen;
65	int state;
66	int result;
67	struct timer_list timeout_timer;
68	struct completion complete;
69	};
70
71	enum {
72	state_idle,
73	state_addr,
74	state_read,
75	state_write,
76	state_stop,
77	state_dead
78	};
79
80	/* Channel on an interface */
81	struct keywest_chan
82	{
83	struct i2c_adapter adapter;
84	struct keywest_iface* iface;
85	unsigned chan_no;
86	};
87
88	/* Register access */
89
90	static inline u8 __read_reg(struct keywest_iface *iface, reg_t reg)
91	{
92	return in_8(iface->base
93	+ (((unsigned)reg) << iface->bsteps));
94	}
95
96	static inline void __write_reg(struct keywest_iface *iface, reg_t reg, u8 val)
97	{
98	out_8(iface->base
99	+ (((unsigned)reg) << iface->bsteps), val);
100	(void)__read_reg(iface, reg_subaddr);
101	}
102
103	#define write_reg(reg, val) __write_reg(iface, reg, val)
104	#define read_reg(reg) __read_reg(iface, reg)
105
106
107
108	#endif /* __I2C_KEYWEST_H__ */
109		1	#ifndef __I2C_KEYWEST_H__

drivers/i2c/busses/i2c-pmac-smu.c

View file @ a28d3af

1	/*		File was deleted
2	i2c Support for Apple SMU Controller
3
4	Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp.
5	<benh@kernel.crashing.org>
6
7	This program is free software; you can redistribute it and/or modify
8	it under the terms of the GNU General Public License as published by
9	the Free Software Foundation; either version 2 of the License, or
10	(at your option) any later version.
11
12	This program is distributed in the hope that it will be useful,
13	but WITHOUT ANY WARRANTY; without even the implied warranty of
14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	GNU General Public License for more details.
16
17	You should have received a copy of the GNU General Public License
18	along with this program; if not, write to the Free Software
19	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21	*/
22
23	#include <linux/config.h>
24	#include <linux/module.h>
25	#include <linux/kernel.h>
26	#include <linux/types.h>
27	#include <linux/i2c.h>
28	#include <linux/init.h>
29	#include <linux/completion.h>
30	#include <linux/device.h>
31	#include <asm/prom.h>
32	#include <asm/of_device.h>
33	#include <asm/smu.h>
34
35	static int probe;
36
37	MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
38	MODULE_DESCRIPTION("I2C driver for Apple's SMU");
39	MODULE_LICENSE("GPL");
40	module_param(probe, bool, 0);
41
42
43	/* Physical interface */
44	struct smu_iface
45	{
46	struct i2c_adapter adapter;
47	struct completion complete;
48	u32 busid;
49	};
50
51	static void smu_i2c_done(struct smu_i2c_cmd cmd, void misc)
52	{
53	struct smu_iface *iface = misc;
54	complete(&iface->complete);
55	}
56
57	/*
58	* SMBUS-type transfer entrypoint
59	*/
60	static s32 smu_smbus_xfer( struct i2c_adapter* adap,
61	u16 addr,
62	unsigned short flags,
63	char read_write,
64	u8 command,
65	int size,
66	union i2c_smbus_data* data)
67	{
68	struct smu_iface *iface = i2c_get_adapdata(adap);
69	struct smu_i2c_cmd cmd;
70	int rc = 0;
71	int read = (read_write == I2C_SMBUS_READ);
72
73	cmd.info.bus = iface->busid;
74	cmd.info.devaddr = (addr << 1) \| (read ? 0x01 : 0x00);
75
76	/* Prepare datas & select mode */
77	switch (size) {
78	case I2C_SMBUS_QUICK:
79	cmd.info.type = SMU_I2C_TRANSFER_SIMPLE;
80	cmd.info.datalen = 0;
81	break;
82	case I2C_SMBUS_BYTE:
83	cmd.info.type = SMU_I2C_TRANSFER_SIMPLE;
84	cmd.info.datalen = 1;
85	if (!read)
86	cmd.info.data[0] = data->byte;
87	break;
88	case I2C_SMBUS_BYTE_DATA:
89	cmd.info.type = SMU_I2C_TRANSFER_STDSUB;
90	cmd.info.datalen = 1;
91	cmd.info.sublen = 1;
92	cmd.info.subaddr[0] = command;
93	cmd.info.subaddr[1] = 0;
94	cmd.info.subaddr[2] = 0;
95	if (!read)
96	cmd.info.data[0] = data->byte;
97	break;
98	case I2C_SMBUS_WORD_DATA:
99	cmd.info.type = SMU_I2C_TRANSFER_STDSUB;
100	cmd.info.datalen = 2;
101	cmd.info.sublen = 1;
102	cmd.info.subaddr[0] = command;
103	cmd.info.subaddr[1] = 0;
104	cmd.info.subaddr[2] = 0;
105	if (!read) {
106	cmd.info.data[0] = data->word & 0xff;
107	cmd.info.data[1] = (data->word >> 8) & 0xff;
108	}
109	break;
110	/* Note that these are broken vs. the expected smbus API where
111	* on reads, the lenght is actually returned from the function,
112	* but I think the current API makes no sense and I don't want
113	* any driver that I haven't verified for correctness to go
114	* anywhere near a pmac i2c bus anyway ...
115	*/
116	case I2C_SMBUS_BLOCK_DATA:
117	cmd.info.type = SMU_I2C_TRANSFER_STDSUB;
118	cmd.info.datalen = data->block[0] + 1;
119	if (cmd.info.datalen > (SMU_I2C_WRITE_MAX + 1))
120	return -EINVAL;
121	if (!read)
122	memcpy(cmd.info.data, data->block, cmd.info.datalen);
123	cmd.info.sublen = 1;
124	cmd.info.subaddr[0] = command;
125	cmd.info.subaddr[1] = 0;
126	cmd.info.subaddr[2] = 0;
127	break;
128	case I2C_SMBUS_I2C_BLOCK_DATA:
129	cmd.info.type = SMU_I2C_TRANSFER_STDSUB;
130	cmd.info.datalen = data->block[0];
131	if (cmd.info.datalen > 7)
132	return -EINVAL;
133	if (!read)
134	memcpy(cmd.info.data, &data->block[1],
135	cmd.info.datalen);
136	cmd.info.sublen = 1;
137	cmd.info.subaddr[0] = command;
138	cmd.info.subaddr[1] = 0;
139	cmd.info.subaddr[2] = 0;
140	break;
141
142	default:
143	return -EINVAL;
144	}
145
146	/* Turn a standardsub read into a combined mode access */
147	if (read_write == I2C_SMBUS_READ &&
148	cmd.info.type == SMU_I2C_TRANSFER_STDSUB)
149	cmd.info.type = SMU_I2C_TRANSFER_COMBINED;
150
151	/* Finish filling command and submit it */
152	cmd.done = smu_i2c_done;
153	cmd.misc = iface;
154	rc = smu_queue_i2c(&cmd);
155	if (rc < 0)
156	return rc;
157	wait_for_completion(&iface->complete);
158	rc = cmd.status;
159
160	if (!read \|\| rc < 0)
161	return rc;
162
163	switch (size) {
164	case I2C_SMBUS_BYTE:
165	case I2C_SMBUS_BYTE_DATA:
166	data->byte = cmd.info.data[0];
167	break;
168	case I2C_SMBUS_WORD_DATA:
169	data->word = ((u16)cmd.info.data[1]) << 8;
170	data->word \|= cmd.info.data[0];
171	break;
172	/* Note that these are broken vs. the expected smbus API where
173	* on reads, the lenght is actually returned from the function,
174	* but I think the current API makes no sense and I don't want
175	* any driver that I haven't verified for correctness to go
176	* anywhere near a pmac i2c bus anyway ...
177	*/
178	case I2C_SMBUS_BLOCK_DATA:
179	case I2C_SMBUS_I2C_BLOCK_DATA:
180	memcpy(&data->block[0], cmd.info.data, cmd.info.datalen);
181	break;
182	}
183
184	return rc;
185	}
186
187	static u32
188	smu_smbus_func(struct i2c_adapter * adapter)
189	{
190	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
191	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
192	I2C_FUNC_SMBUS_BLOCK_DATA;
193	}
194
195	/* For now, we only handle combined mode (smbus) */
196	static struct i2c_algorithm smu_algorithm = {
197	.smbus_xfer = smu_smbus_xfer,
198	.functionality = smu_smbus_func,
199	};
200
201	static int create_iface(struct device_node np, struct device dev)
202	{
203	struct smu_iface* iface;
204	u32 *reg, busid;
205	int rc;
206
207	reg = (u32 *)get_property(np, "reg", NULL);
208	if (reg == NULL) {
209	printk(KERN_ERR "i2c-pmac-smu: can't find bus number !\n");
210	return -ENXIO;
211	}
212	busid = *reg;
213
214	iface = kzalloc(sizeof(struct smu_iface), GFP_KERNEL);
215	if (iface == NULL) {
216	printk(KERN_ERR "i2c-pmac-smu: can't allocate inteface !\n");
217	return -ENOMEM;
218	}
219	init_completion(&iface->complete);
220	iface->busid = busid;
221
222	dev_set_drvdata(dev, iface);
223
224	sprintf(iface->adapter.name, "smu-i2c-%02x", busid);
225	iface->adapter.algo = &smu_algorithm;
226	iface->adapter.algo_data = NULL;
227	iface->adapter.client_register = NULL;
228	iface->adapter.client_unregister = NULL;
229	i2c_set_adapdata(&iface->adapter, iface);
230	iface->adapter.dev.parent = dev;
231
232	rc = i2c_add_adapter(&iface->adapter);
233	if (rc) {
234	printk(KERN_ERR "i2c-pamc-smu.c: Adapter %s registration "
235	"failed\n", iface->adapter.name);
236	i2c_set_adapdata(&iface->adapter, NULL);
237	}
238
239	if (probe) {
240	unsigned char addr;
241	printk("Probe: ");
242	for (addr = 0x00; addr <= 0x7f; addr++) {
243	if (i2c_smbus_xfer(&iface->adapter,addr,
244	0,0,0,I2C_SMBUS_QUICK,NULL) >= 0)
245	printk("%02x ", addr);
246	}
247	printk("\n");
248	}
249
250	printk(KERN_INFO "SMU i2c bus %x registered\n", busid);
251
252	return 0;
253	}
254
255	static int dispose_iface(struct device *dev)
256	{
257	struct smu_iface *iface = dev_get_drvdata(dev);
258	int rc;
259
260	rc = i2c_del_adapter(&iface->adapter);
261	i2c_set_adapdata(&iface->adapter, NULL);
262	/* We aren't that prepared to deal with this... */
263	if (rc)
264	printk("i2c-pmac-smu.c: Failed to remove bus %s !\n",
265	iface->adapter.name);
266	dev_set_drvdata(dev, NULL);
267	kfree(iface);
268
269	return 0;
270	}
271
272
273	static int create_iface_of_platform(struct of_device* dev,
274	const struct of_device_id *match)
275	{
276	struct device_node *node = dev->node;
277
278	if (device_is_compatible(node, "smu-i2c") \|\|
279	(node->parent != NULL &&
280	device_is_compatible(node->parent, "smu-i2c-control")))
281	return create_iface(node, &dev->dev);
282	return -ENODEV;
283	}
284
285
286	static int dispose_iface_of_platform(struct of_device* dev)
287	{
288	return dispose_iface(&dev->dev);
289	}
290
291
292	static struct of_device_id i2c_smu_match[] =
293	{
294	{
295	.compatible = "smu-i2c",
296	},
297	{
298	.compatible = "i2c-bus",
299	},
300	{},
301	};
302	static struct of_platform_driver i2c_smu_of_platform_driver =
303	{
304	.name = "i2c-smu",
305	.match_table = i2c_smu_match,
306	.probe = create_iface_of_platform,
307	.remove = dispose_iface_of_platform
308	};
309
310
311	static int __init i2c_pmac_smu_init(void)
312	{
313	of_register_driver(&i2c_smu_of_platform_driver);
314	return 0;
315	}
316
317
318	static void __exit i2c_pmac_smu_cleanup(void)
319	{
320	of_unregister_driver(&i2c_smu_of_platform_driver);
321	}
322
323	module_init(i2c_pmac_smu_init);
324	module_exit(i2c_pmac_smu_cleanup);
325		1	/*

drivers/i2c/busses/i2c-powermac.c

Diff comments View file @ a28d3af

File was created	1	/*
	2	i2c Support for Apple SMU Controller
	3
	4	Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp.
	5	<benh@kernel.crashing.org>
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; if not, write to the Free Software
	19	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	20
	21	*/
	22
	23	#include <linux/config.h>
	24	#include <linux/module.h>
	25	#include <linux/kernel.h>
	26	#include <linux/types.h>
	27	#include <linux/i2c.h>
	28	#include <linux/init.h>
	29	#include <linux/completion.h>
	30	#include <linux/device.h>
	31	#include <linux/platform_device.h>
	32	#include <asm/prom.h>
	33	#include <asm/pmac_low_i2c.h>
	34
	35	MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
	36	MODULE_DESCRIPTION("I2C driver for Apple PowerMac");
	37	MODULE_LICENSE("GPL");
	38
	39	/*
	40	* SMBUS-type transfer entrypoint
	41	*/
	42	static s32 i2c_powermac_smbus_xfer( struct i2c_adapter* adap,
	43	u16 addr,
	44	unsigned short flags,
	45	char read_write,
	46	u8 command,
	47	int size,
	48	union i2c_smbus_data* data)
	49	{
	50	struct pmac_i2c_bus *bus = i2c_get_adapdata(adap);
	51	int rc = 0;
	52	int read = (read_write == I2C_SMBUS_READ);
	53	int addrdir = (addr << 1) \| read;
	54	u8 local[2];
	55
	56	rc = pmac_i2c_open(bus, 0);
	57	if (rc)
	58	return rc;
	59
	60	switch (size) {
	61	case I2C_SMBUS_QUICK:
	62	rc = pmac_i2c_setmode(bus, pmac_i2c_mode_std);
	63	if (rc)
	64	goto bail;
	65	rc = pmac_i2c_xfer(bus, addrdir, 0, 0, NULL, 0);
	66	break;
	67	case I2C_SMBUS_BYTE:
	68	rc = pmac_i2c_setmode(bus, pmac_i2c_mode_std);
	69	if (rc)
	70	goto bail;
	71	rc = pmac_i2c_xfer(bus, addrdir, 0, 0, &data->byte, 1);
	72	break;
	73	case I2C_SMBUS_BYTE_DATA:
	74	rc = pmac_i2c_setmode(bus, read ?
	75	pmac_i2c_mode_combined :
	76	pmac_i2c_mode_stdsub);
	77	if (rc)
	78	goto bail;
	79	rc = pmac_i2c_xfer(bus, addrdir, 1, command, &data->byte, 1);
	80	break;
	81	case I2C_SMBUS_WORD_DATA:
	82	rc = pmac_i2c_setmode(bus, read ?
	83	pmac_i2c_mode_combined :
	84	pmac_i2c_mode_stdsub);
	85	if (rc)
	86	goto bail;
	87	if (!read) {
	88	local[0] = data->word & 0xff;
	89	local[1] = (data->word >> 8) & 0xff;
	90	}
	91	rc = pmac_i2c_xfer(bus, addrdir, 1, command, local, 2);
	92	if (rc == 0 && read) {
	93	data->word = ((u16)local[1]) << 8;
	94	data->word \|= local[0];
	95	}
	96	break;
	97
	98	/* Note that these are broken vs. the expected smbus API where
	99	* on reads, the lenght is actually returned from the function,
	100	* but I think the current API makes no sense and I don't want
	101	* any driver that I haven't verified for correctness to go
	102	* anywhere near a pmac i2c bus anyway ...
	103	*
	104	* I'm also not completely sure what kind of phases to do between
	105	* the actual command and the data (what I am _supposed_ to do that
	106	* is). For now, I assume writes are a single stream and reads have
	107	* a repeat start/addr phase (but not stop in between)
	108	*/
	109	case I2C_SMBUS_BLOCK_DATA:
	110	rc = pmac_i2c_setmode(bus, read ?
	111	pmac_i2c_mode_combined :
	112	pmac_i2c_mode_stdsub);
	113	if (rc)
	114	goto bail;
	115	rc = pmac_i2c_xfer(bus, addrdir, 1, command, data->block,
	116	data->block[0] + 1);
	117
	118	break;
	119	case I2C_SMBUS_I2C_BLOCK_DATA:
	120	rc = pmac_i2c_setmode(bus, read ?
	121	pmac_i2c_mode_combined :
	122	pmac_i2c_mode_stdsub);
	123	if (rc)
	124	goto bail;
	125	rc = pmac_i2c_xfer(bus, addrdir, 1, command,
	126	read ? data->block : &data->block[1],
	127	data->block[0]);
	128	break;
	129
	130	default:
	131	rc = -EINVAL;
	132	}
	133	bail:
	134	pmac_i2c_close(bus);
	135	return rc;
	136	}
	137
	138	/*
	139	* Generic i2c master transfer entrypoint. This driver only support single
	140	* messages (for "lame i2c" transfers). Anything else should use the smbus
	141	* entry point
	142	*/
	143	static int i2c_powermac_master_xfer( struct i2c_adapter *adap,
	144	struct i2c_msg *msgs,
	145	int num)
	146	{
	147	struct pmac_i2c_bus *bus = i2c_get_adapdata(adap);
	148	int rc = 0;
	149	int read;
	150	int addrdir;
	151
	152	if (num != 1)
	153	return -EINVAL;
	154	if (msgs->flags & I2C_M_TEN)
	155	return -EINVAL;
	156	read = (msgs->flags & I2C_M_RD) != 0;
	157	addrdir = (msgs->addr << 1) \| read;
	158	if (msgs->flags & I2C_M_REV_DIR_ADDR)
	159	addrdir ^= 1;
	160
	161	rc = pmac_i2c_open(bus, 0);
	162	if (rc)
	163	return rc;
	164	rc = pmac_i2c_setmode(bus, pmac_i2c_mode_std);
	165	if (rc)
	166	goto bail;
	167	rc = pmac_i2c_xfer(bus, addrdir, 0, 0, msgs->buf, msgs->len);
	168	bail:
	169	pmac_i2c_close(bus);
	170	return rc < 0 ? rc : msgs->len;
	171	}
	172
	173	static u32 i2c_powermac_func(struct i2c_adapter * adapter)
	174	{
	175	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
	176	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
	177	I2C_FUNC_SMBUS_BLOCK_DATA \| I2C_FUNC_I2C;
	178	}
	179
	180	/* For now, we only handle smbus */
	181	static struct i2c_algorithm i2c_powermac_algorithm = {
	182	.smbus_xfer = i2c_powermac_smbus_xfer,
	183	.master_xfer = i2c_powermac_master_xfer,
	184	.functionality = i2c_powermac_func,
	185	};
	186
	187
	188	static int i2c_powermac_remove(struct device *dev)
	189	{
	190	struct i2c_adapter *adapter = dev_get_drvdata(dev);
	191	struct pmac_i2c_bus *bus = i2c_get_adapdata(adapter);
	192	int rc;
	193
	194	rc = i2c_del_adapter(adapter);
	195	pmac_i2c_detach_adapter(bus, adapter);
	196	i2c_set_adapdata(adapter, NULL);
	197	/* We aren't that prepared to deal with this... */
	198	if (rc)
	199	printk("i2c-powermac.c: Failed to remove bus %s !\n",
	200	adapter->name);
	201	dev_set_drvdata(dev, NULL);
	202	kfree(adapter);
	203
	204	return 0;
	205	}
	206
	207
	208	static int i2c_powermac_probe(struct device *dev)
	209	{
	210	struct pmac_i2c_bus *bus = dev->platform_data;
	211	struct device_node *parent = NULL;
	212	struct i2c_adapter *adapter;
	213	char name[32], *basename;
	214	int rc;
	215
	216	if (bus == NULL)
	217	return -EINVAL;
	218
	219	/* Ok, now we need to make up a name for the interface that will
	220	* match what we used to do in the past, that is basically the
	221	* controller's parent device node for keywest. PMU didn't have a
	222	* naming convention and SMU has a different one
	223	*/
	224	switch(pmac_i2c_get_type(bus)) {
	225	case pmac_i2c_bus_keywest:
	226	parent = of_get_parent(pmac_i2c_get_controller(bus));
	227	if (parent == NULL)
	228	return -EINVAL;
	229	basename = parent->name;
	230	break;
	231	case pmac_i2c_bus_pmu:
	232	basename = "pmu";
	233	break;
	234	case pmac_i2c_bus_smu:
	235	/* This is not what we used to do but I'm fixing drivers at
	236	* the same time as this change
	237	*/
	238	basename = "smu";
	239	break;
	240	default:
	241	return -EINVAL;
	242	}
	243	snprintf(name, 32, "%s %d", basename, pmac_i2c_get_channel(bus));
	244	of_node_put(parent);
	245
	246	adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
	247	if (adapter == NULL) {
	248	printk(KERN_ERR "i2c-powermac: can't allocate inteface !\n");
	249	return -ENOMEM;
	250	}
	251	dev_set_drvdata(dev, adapter);
	252	strcpy(adapter->name, name);
	253	adapter->algo = &i2c_powermac_algorithm;
	254	i2c_set_adapdata(adapter, bus);
	255	adapter->dev.parent = dev;
	256	pmac_i2c_attach_adapter(bus, adapter);
	257	rc = i2c_add_adapter(adapter);
	258	if (rc) {
	259	printk(KERN_ERR "i2c-powermac: Adapter %s registration "
	260	"failed\n", name);
	261	i2c_set_adapdata(adapter, NULL);
	262	pmac_i2c_detach_adapter(bus, adapter);
	263	}
	264
	265	printk(KERN_INFO "PowerMac i2c bus %s registered\n", name);
	266	return rc;
	267	}
	268
	269
	270	static struct device_driver i2c_powermac_driver = {
	271	.name = "i2c-powermac",
	272	.bus = &platform_bus_type,
	273	.probe = i2c_powermac_probe,
	274	.remove = i2c_powermac_remove,
	275	};
	276
	277	static int __init i2c_powermac_init(void)
	278	{
	279	driver_register(&i2c_powermac_driver);
	280	return 0;
	281	}
	282
	283
	284	static void __exit i2c_powermac_cleanup(void)
	285	{
	286	driver_unregister(&i2c_powermac_driver);
	287	}
	288
	289	module_init(i2c_powermac_init);
	290	module_exit(i2c_powermac_cleanup);
	291

drivers/macintosh/Kconfig

Diff comments View file @ a28d3af

drivers/macintosh/smu.c

Diff comments View file @ a28d3af

 /*
  * PowerMac G5 SMU driver
  *
  * Copyright 2004 J. Mayer <l_indien@magic.fr>
  * Copyright 2005 Benjamin Herrenschmidt, IBM Corp.
  *
  * Released under the term of the GNU GPL v2.
  */
 /*
  * TODO:
  *  - maybe add timeout to commands ?
  *  - blocking version of time functions
  *  - polling version of i2c commands (including timer that works with
  *    interrutps off)
  *  - maybe avoid some data copies with i2c by directly using the smu cmd
  *    buffer and a lower level internal interface
  *  - understand SMU -> CPU events and implement reception of them via
  *    the userland interface
  */
 #include <linux/config.h>
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/device.h>
 #include <linux/dmapool.h>
 #include <linux/bootmem.h>
 #include <linux/vmalloc.h>
 #include <linux/highmem.h>
 #include <linux/jiffies.h>
 #include <linux/interrupt.h>
 #include <linux/rtc.h>
 #include <linux/completion.h>
 #include <linux/miscdevice.h>
 #include <linux/delay.h>
 #include <linux/sysdev.h>
 #include <linux/poll.h>
 #include <asm/byteorder.h>
 #include <asm/io.h>
 #include <asm/prom.h>
 #include <asm/machdep.h>
 #include <asm/pmac_feature.h>
 #include <asm/smu.h>
 #include <asm/sections.h>
 #include <asm/abs_addr.h>
 #include <asm/uaccess.h>
 #include <asm/of_device.h>
 #define VERSION "0.7"
 #define AUTHOR  "(c) 2005 Benjamin Herrenschmidt, IBM Corp."
 #undef DEBUG_SMU
 #ifdef DEBUG_SMU
 #define DPRINTK(fmt, args...) do { printk(KERN_DEBUG fmt , ##args); } while (0)
 #else
 #define DPRINTK(fmt, args...) do { } while (0)
 #endif
 /*
  * This is the command buffer passed to the SMU hardware
  */
 #define SMU_MAX_DATA	254
 struct smu_cmd_buf {
 	u8 cmd;
 	u8 length;
 	u8 data[SMU_MAX_DATA];
 };
 struct smu_device {
 	spinlock_t		lock;
 	struct device_node	*of_node;
 	struct of_device	*of_dev;
 	int			doorbell;	/* doorbell gpio */
 	u32 __iomem		*db_buf;	/* doorbell buffer */
 	int			db_irq;
 	int			msg;
 	int			msg_irq;
 	struct smu_cmd_buf	*cmd_buf;	/* command buffer virtual */
 	u32			cmd_buf_abs;	/* command buffer absolute */
 	struct list_head	cmd_list;
 	struct smu_cmd		*cmd_cur;	/* pending command */
 	struct list_head	cmd_i2c_list;
 	struct smu_i2c_cmd	*cmd_i2c_cur;	/* pending i2c command */
 	struct timer_list	i2c_timer;
 };
 /*
  * I don't think there will ever be more than one SMU, so
  * for now, just hard code that
  */
 static struct smu_device	*smu;
 static DECLARE_MUTEX(smu_part_access);
 static void smu_i2c_retry(unsigned long data);
 /*
  * SMU driver low level stuff
  */
 static void smu_start_cmd(void)
 {
 	unsigned long faddr, fend;
 	struct smu_cmd *cmd;
 	if (list_empty(&smu->cmd_list))
 		return;
 	/* Fetch first command in queue */
 	cmd = list_entry(smu->cmd_list.next, struct smu_cmd, link);
 	smu->cmd_cur = cmd;
 	list_del(&cmd->link);
 	DPRINTK("SMU: starting cmd %x, %d bytes data\n", cmd->cmd,
 		cmd->data_len);
 	DPRINTK("SMU: data buffer: %02x %02x %02x %02x %02x %02x %02x %02x\n",
 		((u8 *)cmd->data_buf)[0], ((u8 *)cmd->data_buf)[1],
 		((u8 *)cmd->data_buf)[2], ((u8 *)cmd->data_buf)[3],
 		((u8 *)cmd->data_buf)[4], ((u8 *)cmd->data_buf)[5],
 		((u8 *)cmd->data_buf)[6], ((u8 *)cmd->data_buf)[7]);
 	/* Fill the SMU command buffer */
 	smu->cmd_buf->cmd = cmd->cmd;
 	smu->cmd_buf->length = cmd->data_len;
 	memcpy(smu->cmd_buf->data, cmd->data_buf, cmd->data_len);
 	/* Flush command and data to RAM */
 	faddr = (unsigned long)smu->cmd_buf;
 	fend = faddr + smu->cmd_buf->length + 2;
 	flush_inval_dcache_range(faddr, fend);
 	/* This isn't exactly a DMA mapping here, I suspect
 	 * the SMU is actually communicating with us via i2c to the
 	 * northbridge or the CPU to access RAM.
 	 */
 	writel(smu->cmd_buf_abs, smu->db_buf);
 	/* Ring the SMU doorbell */
 	pmac_do_feature_call(PMAC_FTR_WRITE_GPIO, NULL, smu->doorbell, 4);
 }
 static irqreturn_t smu_db_intr(int irq, void *arg, struct pt_regs *regs)
 {
 	unsigned long flags;
 	struct smu_cmd *cmd;
 	void (*done)(struct smu_cmd *cmd, void *misc) = NULL;
 	void *misc = NULL;
 	u8 gpio;
 	int rc = 0;
 	/* SMU completed the command, well, we hope, let's make sure
 	 * of it
 	 */
 	spin_lock_irqsave(&smu->lock, flags);
 	gpio = pmac_do_feature_call(PMAC_FTR_READ_GPIO, NULL, smu->doorbell);
 	if ((gpio & 7) != 7) {
 		spin_unlock_irqrestore(&smu->lock, flags);
 		return IRQ_HANDLED;
 	}
 	cmd = smu->cmd_cur;
 	smu->cmd_cur = NULL;
 	if (cmd == NULL)
 		goto bail;
 	if (rc == 0) {
 		unsigned long faddr;
 		int reply_len;
 		u8 ack;
 		/* CPU might have brought back the cache line, so we need
 		 * to flush again before peeking at the SMU response. We
 		 * flush the entire buffer for now as we haven't read the
 		 * reply lenght (it's only 2 cache lines anyway)
 		 */
 		faddr = (unsigned long)smu->cmd_buf;
 		flush_inval_dcache_range(faddr, faddr + 256);
 		/* Now check ack */
 		ack = (~cmd->cmd) & 0xff;
 		if (ack != smu->cmd_buf->cmd) {
 			DPRINTK("SMU: incorrect ack, want %x got %x\n",
 				ack, smu->cmd_buf->cmd);
 			rc = -EIO;
 		}
 		reply_len = rc == 0 ? smu->cmd_buf->length : 0;
 		DPRINTK("SMU: reply len: %d\n", reply_len);
 		if (reply_len > cmd->reply_len) {
 			printk(KERN_WARNING "SMU: reply buffer too small,"
 			       "got %d bytes for a %d bytes buffer\n",
 			       reply_len, cmd->reply_len);
 			reply_len = cmd->reply_len;
 		}
 		cmd->reply_len = reply_len;
 		if (cmd->reply_buf && reply_len)
 			memcpy(cmd->reply_buf, smu->cmd_buf->data, reply_len);
 	}
 	/* Now complete the command. Write status last in order as we lost
 	 * ownership of the command structure as soon as it's no longer -1
 	 */
 	done = cmd->done;
 	misc = cmd->misc;
 	mb();
 	cmd->status = rc;
  bail:
 	/* Start next command if any */
 	smu_start_cmd();
 	spin_unlock_irqrestore(&smu->lock, flags);
 	/* Call command completion handler if any */
 	if (done)
 		done(cmd, misc);
 	/* It's an edge interrupt, nothing to do */
 	return IRQ_HANDLED;
 }
 static irqreturn_t smu_msg_intr(int irq, void *arg, struct pt_regs *regs)
 {
 	/* I don't quite know what to do with this one, we seem to never
 	 * receive it, so I suspect we have to arm it someway in the SMU
 	 * to start getting events that way.
 	 */
 	printk(KERN_INFO "SMU: message interrupt !\n");
 	/* It's an edge interrupt, nothing to do */
 	return IRQ_HANDLED;
 }
 /*
  * Queued command management.
  *
  */
 int smu_queue_cmd(struct smu_cmd *cmd)
 {
 	unsigned long flags;
 	if (smu == NULL)
 		return -ENODEV;
 	if (cmd->data_len > SMU_MAX_DATA ||
 	    cmd->reply_len > SMU_MAX_DATA)
 		return -EINVAL;
 	cmd->status = 1;
 	spin_lock_irqsave(&smu->lock, flags);
 	list_add_tail(&cmd->link, &smu->cmd_list);
 	if (smu->cmd_cur == NULL)
 		smu_start_cmd();
 	spin_unlock_irqrestore(&smu->lock, flags);
 	return 0;
 }
 EXPORT_SYMBOL(smu_queue_cmd);
 int smu_queue_simple(struct smu_simple_cmd *scmd, u8 command,
 		     unsigned int data_len,
 		     void (*done)(struct smu_cmd *cmd, void *misc),
 		     void *misc, ...)
 {
 	struct smu_cmd *cmd = &scmd->cmd;
 	va_list list;
 	int i;
 	if (data_len > sizeof(scmd->buffer))
 		return -EINVAL;
 	memset(scmd, 0, sizeof(*scmd));
 	cmd->cmd = command;
 	cmd->data_len = data_len;
 	cmd->data_buf = scmd->buffer;
 	cmd->reply_len = sizeof(scmd->buffer);
 	cmd->reply_buf = scmd->buffer;
 	cmd->done = done;
 	cmd->misc = misc;
 	va_start(list, misc);
 	for (i = 0; i < data_len; ++i)
 		scmd->buffer[i] = (u8)va_arg(list, int);
 	va_end(list);
 	return smu_queue_cmd(cmd);
 }
 EXPORT_SYMBOL(smu_queue_simple);
 void smu_poll(void)
 {
 	u8 gpio;
 	if (smu == NULL)
 		return;
 	gpio = pmac_do_feature_call(PMAC_FTR_READ_GPIO, NULL, smu->doorbell);
 	if ((gpio & 7) == 7)
 		smu_db_intr(smu->db_irq, smu, NULL);
 }
 EXPORT_SYMBOL(smu_poll);
 void smu_done_complete(struct smu_cmd *cmd, void *misc)
 {
 	struct completion *comp = misc;
 	complete(comp);
 }
 EXPORT_SYMBOL(smu_done_complete);
 void smu_spinwait_cmd(struct smu_cmd *cmd)
 {
 	while(cmd->status == 1)
 		smu_poll();
 }
 EXPORT_SYMBOL(smu_spinwait_cmd);
 /* RTC low level commands */
 static inline int bcd2hex (int n)
 {
 	return (((n & 0xf0) >> 4) * 10) + (n & 0xf);
 }
 static inline int hex2bcd (int n)
 {
 	return ((n / 10) << 4) + (n % 10);
 }
 static inline void smu_fill_set_rtc_cmd(struct smu_cmd_buf *cmd_buf,
 					struct rtc_time *time)
 {
 	cmd_buf->cmd = 0x8e;
 	cmd_buf->length = 8;
 	cmd_buf->data[0] = 0x80;
 	cmd_buf->data[1] = hex2bcd(time->tm_sec);
 	cmd_buf->data[2] = hex2bcd(time->tm_min);
 	cmd_buf->data[3] = hex2bcd(time->tm_hour);
 	cmd_buf->data[4] = time->tm_wday;
 	cmd_buf->data[5] = hex2bcd(time->tm_mday);
 	cmd_buf->data[6] = hex2bcd(time->tm_mon) + 1;
 	cmd_buf->data[7] = hex2bcd(time->tm_year - 100);
 }
 int smu_get_rtc_time(struct rtc_time *time, int spinwait)
 {
 	struct smu_simple_cmd cmd;
 	int rc;
 	if (smu == NULL)
 		return -ENODEV;
 	memset(time, 0, sizeof(struct rtc_time));
 	rc = smu_queue_simple(&cmd, SMU_CMD_RTC_COMMAND, 1, NULL, NULL,
 			      SMU_CMD_RTC_GET_DATETIME);
 	if (rc)
 		return rc;
 	smu_spinwait_simple(&cmd);
 	time->tm_sec = bcd2hex(cmd.buffer[0]);
 	time->tm_min = bcd2hex(cmd.buffer[1]);
 	time->tm_hour = bcd2hex(cmd.buffer[2]);
 	time->tm_wday = bcd2hex(cmd.buffer[3]);
 	time->tm_mday = bcd2hex(cmd.buffer[4]);
 	time->tm_mon = bcd2hex(cmd.buffer[5]) - 1;
 	time->tm_year = bcd2hex(cmd.buffer[6]) + 100;
 	return 0;
 }
 int smu_set_rtc_time(struct rtc_time *time, int spinwait)
 {
 	struct smu_simple_cmd cmd;
 	int rc;
 	if (smu == NULL)
 		return -ENODEV;
 	rc = smu_queue_simple(&cmd, SMU_CMD_RTC_COMMAND, 8, NULL, NULL,
 			      SMU_CMD_RTC_SET_DATETIME,
 			      hex2bcd(time->tm_sec),
 			      hex2bcd(time->tm_min),
 			      hex2bcd(time->tm_hour),
 			      time->tm_wday,
 			      hex2bcd(time->tm_mday),
 			      hex2bcd(time->tm_mon) + 1,
 			      hex2bcd(time->tm_year - 100));
 	if (rc)
 		return rc;
 	smu_spinwait_simple(&cmd);
 	return 0;
 }
 void smu_shutdown(void)
 {
 	struct smu_simple_cmd cmd;
 	if (smu == NULL)
 		return;
 	if (smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 9, NULL, NULL,
 			     'S', 'H', 'U', 'T', 'D', 'O', 'W', 'N', 0))
 		return;
 	smu_spinwait_simple(&cmd);
 	for (;;)
 		;
 }
 void smu_restart(void)
 {
 	struct smu_simple_cmd cmd;
 	if (smu == NULL)
 		return;
 	if (smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, NULL, NULL,
 			     'R', 'E', 'S', 'T', 'A', 'R', 'T', 0))
 		return;
 	smu_spinwait_simple(&cmd);
 	for (;;)
 		;
 }
 int smu_present(void)
 {
 	return smu != NULL;
 }
 EXPORT_SYMBOL(smu_present);
 int __init smu_init (void)
 {
 	struct device_node *np;
 	u32 *data;
         np = of_find_node_by_type(NULL, "smu");
         if (np == NULL)
 		return -ENODEV;
 	printk(KERN_INFO "SMU driver %s %s\n", VERSION, AUTHOR);
 	if (smu_cmdbuf_abs == 0) {
 		printk(KERN_ERR "SMU: Command buffer not allocated !\n");
 		return -EINVAL;
 	}
 	smu = alloc_bootmem(sizeof(struct smu_device));
 	if (smu == NULL)
 		return -ENOMEM;
 	memset(smu, 0, sizeof(*smu));
 	spin_lock_init(&smu->lock);
 	INIT_LIST_HEAD(&smu->cmd_list);
 	INIT_LIST_HEAD(&smu->cmd_i2c_list);
 	smu->of_node = np;
 	smu->db_irq = NO_IRQ;
 	smu->msg_irq = NO_IRQ;
 	/* smu_cmdbuf_abs is in the low 2G of RAM, can be converted to a
 	 * 32 bits value safely
 	 */
 	smu->cmd_buf_abs = (u32)smu_cmdbuf_abs;
 	smu->cmd_buf = (struct smu_cmd_buf *)abs_to_virt(smu_cmdbuf_abs);
 	np = of_find_node_by_name(NULL, "smu-doorbell");
 	if (np == NULL) {
 		printk(KERN_ERR "SMU: Can't find doorbell GPIO !\n");
 		goto fail;
 	}
 	data = (u32 *)get_property(np, "reg", NULL);
 	if (data == NULL) {
 		of_node_put(np);
 		printk(KERN_ERR "SMU: Can't find doorbell GPIO address !\n");
 		goto fail;
 	}
 	/* Current setup has one doorbell GPIO that does both doorbell
 	 * and ack. GPIOs are at 0x50, best would be to find that out
 	 * in the device-tree though.
 	 */
 	smu->doorbell = *data;
 	if (smu->doorbell < 0x50)
 		smu->doorbell += 0x50;
 	if (np->n_intrs > 0)
 		smu->db_irq = np->intrs[0].line;
 	of_node_put(np);
 	/* Now look for the smu-interrupt GPIO */
 	do {
 		np = of_find_node_by_name(NULL, "smu-interrupt");
 		if (np == NULL)
 			break;
 		data = (u32 *)get_property(np, "reg", NULL);
 		if (data == NULL) {
 			of_node_put(np);
 			break;
 		}
 		smu->msg = *data;
 		if (smu->msg < 0x50)
 			smu->msg += 0x50;
 		if (np->n_intrs > 0)
 			smu->msg_irq = np->intrs[0].line;
 		of_node_put(np);
 	} while(0);
 	/* Doorbell buffer is currently hard-coded, I didn't find a proper
 	 * device-tree entry giving the address. Best would probably to use
 	 * an offset for K2 base though, but let's do it that way for now.
 	 */
 	smu->db_buf = ioremap(0x8000860c, 0x1000);
 	if (smu->db_buf == NULL) {
 		printk(KERN_ERR "SMU: Can't map doorbell buffer pointer !\n");
 		goto fail;
 	}
 	sys_ctrler = SYS_CTRLER_SMU;
 	return 0;
  fail:
 	smu = NULL;
 	return -ENXIO;
 }
 static int smu_late_init(void)
 {
 	if (!smu)
 		return 0;
 	init_timer(&smu->i2c_timer);
 	smu->i2c_timer.function = smu_i2c_retry;
 	smu->i2c_timer.data = (unsigned long)smu;
 	/*
 	 * Try to request the interrupts
 	 */
 	if (smu->db_irq != NO_IRQ) {
 		if (request_irq(smu->db_irq, smu_db_intr,
 				SA_SHIRQ, "SMU doorbell", smu) < 0) {
 			printk(KERN_WARNING "SMU: can't "
 			       "request interrupt %d\n",
 			       smu->db_irq);
 			smu->db_irq = NO_IRQ;
 		}
 	}
 	if (smu->msg_irq != NO_IRQ) {
 		if (request_irq(smu->msg_irq, smu_msg_intr,
 				SA_SHIRQ, "SMU message", smu) < 0) {
 			printk(KERN_WARNING "SMU: can't "
 			       "request interrupt %d\n",
 			       smu->msg_irq);
 			smu->msg_irq = NO_IRQ;
 		}
 	}
 	return 0;
 }
 /* This has to be before arch_initcall as the low i2c stuff relies on the
  * above having been done before we reach arch_initcalls
  */
 core_initcall(smu_late_init);
 /*
  * sysfs visibility
  */
-static void smu_create_i2c(struct device_node *np)
-{
-	char name[32];
-	u32 *reg = (u32 *)get_property(np, "reg", NULL);
-	if (reg != NULL) {
-		sprintf(name, "smu-i2c-%02x", *reg);
-		of_platform_device_create(np, name, &smu->of_dev->dev);
-	}
-}
 static void smu_expose_childs(void *unused)
 {
-	struct device_node *np, *gp;
+	struct device_node *np;
-	for (np = NULL; (np = of_get_next_child(smu->of_node, np)) != NULL;) {
+	for (np = NULL; (np = of_get_next_child(smu->of_node, np)) != NULL;)
-		if (device_is_compatible(np, "smu-i2c-control")) {
-			gp = NULL;
-			while ((gp = of_get_next_child(np, gp)) != NULL)
-				if (device_is_compatible(gp, "i2c-bus"))
-					smu_create_i2c(gp);
-		} else if (device_is_compatible(np, "smu-i2c"))
-			smu_create_i2c(np);
 		if (device_is_compatible(np, "smu-sensors"))
 			of_platform_device_create(np, "smu-sensors",
 						  &smu->of_dev->dev);
-	}
 }
 static DECLARE_WORK(smu_expose_childs_work, smu_expose_childs, NULL);
 static int smu_platform_probe(struct of_device* dev,
 			      const struct of_device_id *match)
 {
 	if (!smu)
 		return -ENODEV;
 	smu->of_dev = dev;
 	/*
 	 * Ok, we are matched, now expose all i2c busses. We have to defer
 	 * that unfortunately or it would deadlock inside the device model
 	 */
 	schedule_work(&smu_expose_childs_work);
 	return 0;
 }
 static struct of_device_id smu_platform_match[] =
 {
 	{
 		.type		= "smu",
 	},
 	{},
 };
 static struct of_platform_driver smu_of_platform_driver =
 {
 	.name 		= "smu",
 	.match_table	= smu_platform_match,
 	.probe		= smu_platform_probe,
 };
 static int __init smu_init_sysfs(void)
 {
 	int rc;
 	/*
 	 * Due to sysfs bogosity, a sysdev is not a real device, so
 	 * we should in fact create both if we want sysdev semantics
 	 * for power management.
 	 * For now, we don't power manage machines with an SMU chip,
 	 * I'm a bit too far from figuring out how that works with those
 	 * new chipsets, but that will come back and bite us
 	 */
 	rc = of_register_driver(&smu_of_platform_driver);
 	return 0;
 }
 device_initcall(smu_init_sysfs);
 struct of_device *smu_get_ofdev(void)
 {
 	if (!smu)
 		return NULL;
 	return smu->of_dev;
 }
 EXPORT_SYMBOL_GPL(smu_get_ofdev);
 /*
  * i2c interface
  */
 static void smu_i2c_complete_command(struct smu_i2c_cmd *cmd, int fail)
 {
 	void (*done)(struct smu_i2c_cmd *cmd, void *misc) = cmd->done;
 	void *misc = cmd->misc;
 	unsigned long flags;
 	/* Check for read case */
 	if (!fail && cmd->read) {
 		if (cmd->pdata[0] < 1)
 			fail = 1;
 		else
 			memcpy(cmd->info.data, &cmd->pdata[1],
 			       cmd->info.datalen);
 	}
 	DPRINTK("SMU: completing, success: %d\n", !fail);
 	/* Update status and mark no pending i2c command with lock
 	 * held so nobody comes in while we dequeue an eventual
 	 * pending next i2c command
 	 */
 	spin_lock_irqsave(&smu->lock, flags);
 	smu->cmd_i2c_cur = NULL;
 	wmb();
 	cmd->status = fail ? -EIO : 0;
 	/* Is there another i2c command waiting ? */
 	if (!list_empty(&smu->cmd_i2c_list)) {
 		struct smu_i2c_cmd *newcmd;
 		/* Fetch it, new current, remove from list */
 		newcmd = list_entry(smu->cmd_i2c_list.next,
 				    struct smu_i2c_cmd, link);
 		smu->cmd_i2c_cur = newcmd;
 		list_del(&cmd->link);
 		/* Queue with low level smu */
 		list_add_tail(&cmd->scmd.link, &smu->cmd_list);
 		if (smu->cmd_cur == NULL)
 			smu_start_cmd();
 	}
 	spin_unlock_irqrestore(&smu->lock, flags);
 	/* Call command completion handler if any */
 	if (done)
 		done(cmd, misc);
 }
 static void smu_i2c_retry(unsigned long data)
 {
 	struct smu_i2c_cmd	*cmd = smu->cmd_i2c_cur;
 	DPRINTK("SMU: i2c failure, requeuing...\n");
 	/* requeue command simply by resetting reply_len */
 	cmd->pdata[0] = 0xff;
 	cmd->scmd.reply_len = sizeof(cmd->pdata);
 	smu_queue_cmd(&cmd->scmd);
 }
 static void smu_i2c_low_completion(struct smu_cmd *scmd, void *misc)
 {
 	struct smu_i2c_cmd	*cmd = misc;
 	int			fail = 0;
 	DPRINTK("SMU: i2c compl. stage=%d status=%x pdata[0]=%x rlen: %x\n",
 		cmd->stage, scmd->status, cmd->pdata[0], scmd->reply_len);
 	/* Check for possible status */
 	if (scmd->status < 0)
 		fail = 1;
 	else if (cmd->read) {
 		if (cmd->stage == 0)
 			fail = cmd->pdata[0] != 0;
 		else
 			fail = cmd->pdata[0] >= 0x80;
 	} else {
 		fail = cmd->pdata[0] != 0;
 	}
 	/* Handle failures by requeuing command, after 5ms interval
 	 */
 	if (fail && --cmd->retries > 0) {
 		DPRINTK("SMU: i2c failure, starting timer...\n");
 		BUG_ON(cmd != smu->cmd_i2c_cur);
 		mod_timer(&smu->i2c_timer, jiffies + msecs_to_jiffies(5));
 		return;
 	}
 	/* If failure or stage 1, command is complete */
 	if (fail || cmd->stage != 0) {
 		smu_i2c_complete_command(cmd, fail);
 		return;
 	}
 	DPRINTK("SMU: going to stage 1\n");
 	/* Ok, initial command complete, now poll status */
 	scmd->reply_buf = cmd->pdata;
 	scmd->reply_len = sizeof(cmd->pdata);
 	scmd->data_buf = cmd->pdata;
 	scmd->data_len = 1;
 	cmd->pdata[0] = 0;
 	cmd->stage = 1;
 	cmd->retries = 20;
 	smu_queue_cmd(scmd);
 }
 int smu_queue_i2c(struct smu_i2c_cmd *cmd)
 {
 	unsigned long flags;
 	if (smu == NULL)
 		return -ENODEV;
 	/* Fill most fields of scmd */
 	cmd->scmd.cmd = SMU_CMD_I2C_COMMAND;
 	cmd->scmd.done = smu_i2c_low_completion;
 	cmd->scmd.misc = cmd;
 	cmd->scmd.reply_buf = cmd->pdata;
 	cmd->scmd.reply_len = sizeof(cmd->pdata);
 	cmd->scmd.data_buf = (u8 *)(char *)&cmd->info;
 	cmd->scmd.status = 1;
 	cmd->stage = 0;
 	cmd->pdata[0] = 0xff;
 	cmd->retries = 20;
 	cmd->status = 1;
 	/* Check transfer type, sanitize some "info" fields
 	 * based on transfer type and do more checking
 	 */
 	cmd->info.caddr = cmd->info.devaddr;
 	cmd->read = cmd->info.devaddr & 0x01;
 	switch(cmd->info.type) {
 	case SMU_I2C_TRANSFER_SIMPLE:
 		memset(&cmd->info.sublen, 0, 4);
 		break;
 	case SMU_I2C_TRANSFER_COMBINED:
 		cmd->info.devaddr &= 0xfe;
 	case SMU_I2C_TRANSFER_STDSUB:
 		if (cmd->info.sublen > 3)
 			return -EINVAL;
 		break;
 	default:
 		return -EINVAL;
 	}
 	/* Finish setting up command based on transfer direction
 	 */
 	if (cmd->read) {
 		if (cmd->info.datalen > SMU_I2C_READ_MAX)
 			return -EINVAL;
 		memset(cmd->info.data, 0xff, cmd->info.datalen);
 		cmd->scmd.data_len = 9;
 	} else {
 		if (cmd->info.datalen > SMU_I2C_WRITE_MAX)
 			return -EINVAL;
 		cmd->scmd.data_len = 9 + cmd->info.datalen;
 	}
 	DPRINTK("SMU: i2c enqueuing command\n");
 	DPRINTK("SMU:   %s, len=%d bus=%x addr=%x sub0=%x type=%x\n",
 		cmd->read ? "read" : "write", cmd->info.datalen,
 		cmd->info.bus, cmd->info.caddr,
 		cmd->info.subaddr[0], cmd->info.type);
 	/* Enqueue command in i2c list, and if empty, enqueue also in
 	 * main command list
 	 */
 	spin_lock_irqsave(&smu->lock, flags);
 	if (smu->cmd_i2c_cur == NULL) {
 		smu->cmd_i2c_cur = cmd;
 		list_add_tail(&cmd->scmd.link, &smu->cmd_list);
 		if (smu->cmd_cur == NULL)
 			smu_start_cmd();
 	} else
 		list_add_tail(&cmd->link, &smu->cmd_i2c_list);
 	spin_unlock_irqrestore(&smu->lock, flags);
 	return 0;
 }
 /*
  * Handling of "partitions"
  */
 static int smu_read_datablock(u8 *dest, unsigned int addr, unsigned int len)
 {
 	DECLARE_COMPLETION(comp);
 	unsigned int chunk;
 	struct smu_cmd cmd;
 	int rc;
 	u8 params[8];
 	/* We currently use a chunk size of 0xe. We could check the
 	 * SMU firmware version and use bigger sizes though
 	 */
 	chunk = 0xe;
 	while (len) {
 		unsigned int clen = min(len, chunk);
 		cmd.cmd = SMU_CMD_MISC_ee_COMMAND;
 		cmd.data_len = 7;
 		cmd.data_buf = params;
 		cmd.reply_len = chunk;
 		cmd.reply_buf = dest;
 		cmd.done = smu_done_complete;
 		cmd.misc = &comp;
 		params[0] = SMU_CMD_MISC_ee_GET_DATABLOCK_REC;
 		params[1] = 0x4;
 		*((u32 *)&params[2]) = addr;
 		params[6] = clen;
 		rc = smu_queue_cmd(&cmd);
 		if (rc)
 			return rc;
 		wait_for_completion(&comp);
 		if (cmd.status != 0)
 			return rc;
 		if (cmd.reply_len != clen) {
 			printk(KERN_DEBUG "SMU: short read in "
 			       "smu_read_datablock, got: %d, want: %d\n",
 			       cmd.reply_len, clen);
 			return -EIO;
 		}
 		len -= clen;
 		addr += clen;
 		dest += clen;
 	}
 	return 0;
 }
 static struct smu_sdbp_header *smu_create_sdb_partition(int id)
 {
 	DECLARE_COMPLETION(comp);
 	struct smu_simple_cmd cmd;
 	unsigned int addr, len, tlen;
 	struct smu_sdbp_header *hdr;
 	struct property *prop;
 	/* First query the partition info */
 	DPRINTK("SMU: Query partition infos ... (irq=%d)\n", smu->db_irq);
 	smu_queue_simple(&cmd, SMU_CMD_PARTITION_COMMAND, 2,
 			 smu_done_complete, &comp,
 			 SMU_CMD_PARTITION_LATEST, id);
 	wait_for_completion(&comp);
 	DPRINTK("SMU: done, status: %d, reply_len: %d\n",
 		cmd.cmd.status, cmd.cmd.reply_len);
 	/* Partition doesn't exist (or other error) */
 	if (cmd.cmd.status != 0 || cmd.cmd.reply_len != 6)
 		return NULL;
 	/* Fetch address and length from reply */
 	addr = *((u16 *)cmd.buffer);
 	len = cmd.buffer[3] << 2;
 	/* Calucluate total length to allocate, including the 17 bytes
 	 * for "sdb-partition-XX" that we append at the end of the buffer
 	 */
 	tlen = sizeof(struct property) + len + 18;
 	prop = kcalloc(tlen, 1, GFP_KERNEL);
 	if (prop == NULL)
 		return NULL;
 	hdr = (struct smu_sdbp_header *)(prop + 1);
 	prop->name = ((char *)prop) + tlen - 18;
 	sprintf(prop->name, "sdb-partition-%02x", id);
 	prop->length = len;
 	prop->value = (unsigned char *)hdr;
 	prop->next = NULL;
 	/* Read the datablock */
 	if (smu_read_datablock((u8 *)hdr, addr, len)) {
 		printk(KERN_DEBUG "SMU: datablock read failed while reading "
 		       "partition %02x !\n", id);
 		goto failure;
 	}
 	/* Got it, check a few things and create the property */
 	if (hdr->id != id) {
 		printk(KERN_DEBUG "SMU: Reading partition %02x and got "
 		       "%02x !\n", id, hdr->id);
 		goto failure;
 	}
 	if (prom_add_property(smu->of_node, prop)) {
 		printk(KERN_DEBUG "SMU: Failed creating sdb-partition-%02x "
 		       "property !\n", id);
 		goto failure;
 	}
 	return hdr;
  failure:
 	kfree(prop);
 	return NULL;
 }
 /* Note: Only allowed to return error code in pointers (using ERR_PTR)
  * when interruptible is 1
  */
 struct smu_sdbp_header *__smu_get_sdb_partition(int id, unsigned int *size,
 						int interruptible)
 {
 	char pname[32];
 	struct smu_sdbp_header *part;
 	if (!smu)
 		return NULL;
 	sprintf(pname, "sdb-partition-%02x", id);
 	DPRINTK("smu_get_sdb_partition(%02x)\n", id);
 	if (interruptible) {
 		int rc;
 		rc = down_interruptible(&smu_part_access);
 		if (rc)
 			return ERR_PTR(rc);
 	} else
 		down(&smu_part_access);
 	part = (struct smu_sdbp_header *)get_property(smu->of_node,
 						      pname, size);
 	if (part == NULL) {
 		DPRINTK("trying to extract from SMU ...\n");
 		part = smu_create_sdb_partition(id);
 		if (part != NULL && size)
 			*size = part->len << 2;
 	}
 	up(&smu_part_access);
 	return part;
 }
 struct smu_sdbp_header *smu_get_sdb_partition(int id, unsigned int *size)
 {
 	return __smu_get_sdb_partition(id, size, 0);
 }
 EXPORT_SYMBOL(smu_get_sdb_partition);
 /*
  * Userland driver interface
  */
 static LIST_HEAD(smu_clist);
 static DEFINE_SPINLOCK(smu_clist_lock);
 enum smu_file_mode {
 	smu_file_commands,
 	smu_file_events,
 	smu_file_closing
 };
 struct smu_private
 {
 	struct list_head	list;
 	enum smu_file_mode	mode;
 	int			busy;
 	struct smu_cmd		cmd;
 	spinlock_t		lock;
 	wait_queue_head_t	wait;
 	u8			buffer[SMU_MAX_DATA];
 };
 static int smu_open(struct inode *inode, struct file *file)
 {
 	struct smu_private *pp;
 	unsigned long flags;
 	pp = kmalloc(sizeof(struct smu_private), GFP_KERNEL);
 	if (pp == 0)
 		return -ENOMEM;
 	memset(pp, 0, sizeof(struct smu_private));
 	spin_lock_init(&pp->lock);
 	pp->mode = smu_file_commands;
 	init_waitqueue_head(&pp->wait);
 	spin_lock_irqsave(&smu_clist_lock, flags);
 	list_add(&pp->list, &smu_clist);
 	spin_unlock_irqrestore(&smu_clist_lock, flags);
 	file->private_data = pp;
 	return 0;
 }
 static void smu_user_cmd_done(struct smu_cmd *cmd, void *misc)
 {
 	struct smu_private *pp = misc;
 	wake_up_all(&pp->wait);
 }
 static ssize_t smu_write(struct file *file, const char __user *buf,
 			 size_t count, loff_t *ppos)
 {
 	struct smu_private *pp = file->private_data;
 	unsigned long flags;
 	struct smu_user_cmd_hdr hdr;
 	int rc = 0;
 	if (pp->busy)
 		return -EBUSY;
 	else if (copy_from_user(&hdr, buf, sizeof(hdr)))
 		return -EFAULT;
 	else if (hdr.cmdtype == SMU_CMDTYPE_WANTS_EVENTS) {
 		pp->mode = smu_file_events;
 		return 0;
 	} else if (hdr.cmdtype == SMU_CMDTYPE_GET_PARTITION) {
 		struct smu_sdbp_header *part;
 		part = __smu_get_sdb_partition(hdr.cmd, NULL, 1);
 		if (part == NULL)
 			return -EINVAL;
 		else if (IS_ERR(part))
 			return PTR_ERR(part);
 		return 0;
 	} else if (hdr.cmdtype != SMU_CMDTYPE_SMU)
 		return -EINVAL;
 	else if (pp->mode != smu_file_commands)
 		return -EBADFD;
 	else if (hdr.data_len > SMU_MAX_DATA)
 		return -EINVAL;
 	spin_lock_irqsave(&pp->lock, flags);
 	if (pp->busy) {
 		spin_unlock_irqrestore(&pp->lock, flags);
 		return -EBUSY;
 	}
 	pp->busy = 1;
 	pp->cmd.status = 1;
 	spin_unlock_irqrestore(&pp->lock, flags);
 	if (copy_from_user(pp->buffer, buf + sizeof(hdr), hdr.data_len)) {
 		pp->busy = 0;
 		return -EFAULT;
 	}
 	pp->cmd.cmd = hdr.cmd;
 	pp->cmd.data_len = hdr.data_len;
 	pp->cmd.reply_len = SMU_MAX_DATA;
 	pp->cmd.data_buf = pp->buffer;
 	pp->cmd.reply_buf = pp->buffer;
 	pp->cmd.done = smu_user_cmd_done;
 	pp->cmd.misc = pp;
 	rc = smu_queue_cmd(&pp->cmd);
 	if (rc < 0)
 		return rc;
 	return count;
 }
 static ssize_t smu_read_command(struct file *file, struct smu_private *pp,
 				char __user *buf, size_t count)
 {
 	DECLARE_WAITQUEUE(wait, current);
 	struct smu_user_reply_hdr hdr;
 	unsigned long flags;
 	int size, rc = 0;
 	if (!pp->busy)
 		return 0;
 	if (count < sizeof(struct smu_user_reply_hdr))
 		return -EOVERFLOW;
 	spin_lock_irqsave(&pp->lock, flags);
 	if (pp->cmd.status == 1) {
 		if (file->f_flags & O_NONBLOCK)
 			return -EAGAIN;
 		add_wait_queue(&pp->wait, &wait);
 		for (;;) {
 			set_current_state(TASK_INTERRUPTIBLE);
 			rc = 0;
 			if (pp->cmd.status != 1)
 				break;
 			rc = -ERESTARTSYS;
 			if (signal_pending(current))
 				break;
 			spin_unlock_irqrestore(&pp->lock, flags);
 			schedule();
 			spin_lock_irqsave(&pp->lock, flags);
 		}
 		set_current_state(TASK_RUNNING);
 		remove_wait_queue(&pp->wait, &wait);
 	}
 	spin_unlock_irqrestore(&pp->lock, flags);
 	if (rc)
 		return rc;
 	if (pp->cmd.status != 0)
 		pp->cmd.reply_len = 0;
 	size = sizeof(hdr) + pp->cmd.reply_len;
 	if (count < size)
 		size = count;
 	rc = size;
 	hdr.status = pp->cmd.status;
 	hdr.reply_len = pp->cmd.reply_len;
 	if (copy_to_user(buf, &hdr, sizeof(hdr)))
 		return -EFAULT;
 	size -= sizeof(hdr);
 	if (size && copy_to_user(buf + sizeof(hdr), pp->buffer, size))
 		return -EFAULT;
 	pp->busy = 0;
 	return rc;
 }
 static ssize_t smu_read_events(struct file *file, struct smu_private *pp,
 			       char __user *buf, size_t count)
 {
 	/* Not implemented */
 	msleep_interruptible(1000);
 	return 0;
 }
 static ssize_t smu_read(struct file *file, char __user *buf,
 			size_t count, loff_t *ppos)
 {
 	struct smu_private *pp = file->private_data;
 	if (pp->mode == smu_file_commands)
 		return smu_read_command(file, pp, buf, count);
 	if (pp->mode == smu_file_events)
 		return smu_read_events(file, pp, buf, count);
 	return -EBADFD;
 }
 static unsigned int smu_fpoll(struct file *file, poll_table *wait)
 {
 	struct smu_private *pp = file->private_data;
 	unsigned int mask = 0;
 	unsigned long flags;
 	if (pp == 0)
 		return 0;
 	if (pp->mode == smu_file_commands) {
 		poll_wait(file, &pp->wait, wait);
 		spin_lock_irqsave(&pp->lock, flags);
 		if (pp->busy && pp->cmd.status != 1)
 			mask |= POLLIN;
 		spin_unlock_irqrestore(&pp->lock, flags);
 	} if (pp->mode == smu_file_events) {
 		/* Not yet implemented */
 	}
 	return mask;
 }
 static int smu_release(struct inode *inode, struct file *file)
 {
 	struct smu_private *pp = file->private_data;
 	unsigned long flags;
 	unsigned int busy;
 	if (pp == 0)
 		return 0;
 	file->private_data = NULL;
 	/* Mark file as closing to avoid races with new request */
 	spin_lock_irqsave(&pp->lock, flags);
 	pp->mode = smu_file_closing;
 	busy = pp->busy;
 	/* Wait for any pending request to complete */
 	if (busy && pp->cmd.status == 1) {
 		DECLARE_WAITQUEUE(wait, current);
 		add_wait_queue(&pp->wait, &wait);
 		for (;;) {
 			set_current_state(TASK_UNINTERRUPTIBLE);
 			if (pp->cmd.status != 1)
 				break;
 			spin_lock_irqsave(&pp->lock, flags);
 			schedule();
 			spin_unlock_irqrestore(&pp->lock, flags);
 		}
 		set_current_state(TASK_RUNNING);
 		remove_wait_queue(&pp->wait, &wait);
 	}
 	spin_unlock_irqrestore(&pp->lock, flags);
 	spin_lock_irqsave(&smu_clist_lock, flags);
 	list_del(&pp->list);
 	spin_unlock_irqrestore(&smu_clist_lock, flags);
 	kfree(pp);
 	return 0;
 }
 static struct file_operations smu_device_fops = {
 	.llseek		= no_llseek,
 	.read		= smu_read,
 	.write		= smu_write,
 	.poll		= smu_fpoll,
 	.open		= smu_open,
 	.release	= smu_release,
 };
 static struct miscdevice pmu_device = {
 	MISC_DYNAMIC_MINOR, "smu", &smu_device_fops
 };
 static int smu_device_init(void)
 {
 	if (!smu)
 		return -ENODEV;
 	if (misc_register(&pmu_device) < 0)
 		printk(KERN_ERR "via-pmu: cannot register misc device.\n");
 	return 0;
 }
 device_initcall(smu_device_init);

drivers/macintosh/windfarm_lm75_sensor.c

Diff comments View file @ a28d3af

 /*
  * Windfarm PowerMac thermal control. LM75 sensor
  *
  * (c) Copyright 2005 Benjamin Herrenschmidt, IBM Corp.
  *                    <benh@kernel.crashing.org>
  *
  * Released under the term of the GNU GPL v2.
  */
 #include <linux/types.h>
 #include <linux/errno.h>
 #include <linux/kernel.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/init.h>
 #include <linux/wait.h>
 #include <linux/i2c.h>
 #include <linux/i2c-dev.h>
 #include <asm/prom.h>
 #include <asm/machdep.h>
 #include <asm/io.h>
 #include <asm/system.h>
 #include <asm/sections.h>
+#include <asm/pmac_low_i2c.h>
 #include "windfarm.h"
 #define VERSION "0.1"
 #undef DEBUG
 #ifdef DEBUG
 #define DBG(args...)	printk(args)
 #else
 #define DBG(args...)	do { } while(0)
 #endif
 struct wf_lm75_sensor {
 	int			ds1775 : 1;
 	int			inited : 1;
 	struct 	i2c_client	i2c;
 	struct 	wf_sensor	sens;
 };
 #define wf_to_lm75(c) container_of(c, struct wf_lm75_sensor, sens)
 #define i2c_to_lm75(c) container_of(c, struct wf_lm75_sensor, i2c)
 static int wf_lm75_attach(struct i2c_adapter *adapter);
 static int wf_lm75_detach(struct i2c_client *client);
 static struct i2c_driver wf_lm75_driver = {
 	.driver = {
 		.name	= "wf_lm75",
 	},
 	.attach_adapter	= wf_lm75_attach,
 	.detach_client	= wf_lm75_detach,
 };
 static int wf_lm75_get(struct wf_sensor *sr, s32 *value)
 {
 	struct wf_lm75_sensor *lm = wf_to_lm75(sr);
 	s32 data;
 	if (lm->i2c.adapter == NULL)
 		return -ENODEV;
 	/* Init chip if necessary */
 	if (!lm->inited) {
 		u8 cfg_new, cfg = (u8)i2c_smbus_read_byte_data(&lm->i2c, 1);
 		DBG("wf_lm75: Initializing %s, cfg was: %02x\n",
 		    sr->name, cfg);
 		/* clear shutdown bit, keep other settings as left by
 		 * the firmware for now
 		 */
 		cfg_new = cfg & ~0x01;
 		i2c_smbus_write_byte_data(&lm->i2c, 1, cfg_new);
 		lm->inited = 1;
 		/* If we just powered it up, let's wait 200 ms */
 		msleep(200);
 	}
 	/* Read temperature register */
 	data = (s32)le16_to_cpu(i2c_smbus_read_word_data(&lm->i2c, 0));
 	data <<= 8;
 	*value = data;
 	return 0;
 }
 static void wf_lm75_release(struct wf_sensor *sr)
 {
 	struct wf_lm75_sensor *lm = wf_to_lm75(sr);
 	/* check if client is registered and detach from i2c */
 	if (lm->i2c.adapter) {
 		i2c_detach_client(&lm->i2c);
 		lm->i2c.adapter = NULL;
 	}
 	kfree(lm);
 }
 static struct wf_sensor_ops wf_lm75_ops = {
 	.get_value	= wf_lm75_get,
 	.release	= wf_lm75_release,
 	.owner		= THIS_MODULE,
 };
 static struct wf_lm75_sensor *wf_lm75_create(struct i2c_adapter *adapter,
 					     u8 addr, int ds1775,
 					     const char *loc)
 {
 	struct wf_lm75_sensor *lm;
 	DBG("wf_lm75: creating  %s device at address 0x%02x\n",
 	    ds1775 ? "ds1775" : "lm75", addr);
 	lm = kmalloc(sizeof(struct wf_lm75_sensor), GFP_KERNEL);
 	if (lm == NULL)
 		return NULL;
 	memset(lm, 0, sizeof(struct wf_lm75_sensor));
 	/* Usual rant about sensor names not beeing very consistent in
 	 * the device-tree, oh well ...
 	 * Add more entries below as you deal with more setups
 	 */
 	if (!strcmp(loc, "Hard drive") || !strcmp(loc, "DRIVE BAY"))
 		lm->sens.name = "hd-temp";
 	else
 		goto fail;
 	lm->inited = 0;
 	lm->sens.ops = &wf_lm75_ops;
 	lm->ds1775 = ds1775;
 	lm->i2c.addr = (addr >> 1) & 0x7f;
 	lm->i2c.adapter = adapter;
 	lm->i2c.driver = &wf_lm75_driver;
 	strncpy(lm->i2c.name, lm->sens.name, I2C_NAME_SIZE-1);
 	if (i2c_attach_client(&lm->i2c)) {
 		printk(KERN_ERR "windfarm: failed to attach %s %s to i2c\n",
 		       ds1775 ? "ds1775" : "lm75", lm->i2c.name);
 		goto fail;
 	}
 	if (wf_register_sensor(&lm->sens)) {
 		i2c_detach_client(&lm->i2c);
 		goto fail;
 	}
 	return lm;
  fail:
 	kfree(lm);
 	return NULL;
 }
 static int wf_lm75_attach(struct i2c_adapter *adapter)
 {
-	u8 bus_id;
+	struct device_node *busnode, *dev;
-	struct device_node *smu, *bus, *dev;
+	struct pmac_i2c_bus *bus;
-	/* We currently only deal with LM75's hanging off the SMU
-	 * i2c busses. If we extend that driver to other/older
-	 * machines, we should split this function into SMU-i2c,
-	 * keywest-i2c, PMU-i2c, ...
-	 */
 	DBG("wf_lm75: adapter %s detected\n", adapter->name);
-	if (strncmp(adapter->name, "smu-i2c-", 8) != 0)
+	bus = pmac_i2c_adapter_to_bus(adapter);
-		return 0;
+	if (bus == NULL)
-	smu = of_find_node_by_type(NULL, "smu");
+		return -ENODEV;
-	if (smu == NULL)
+	busnode = pmac_i2c_get_bus_node(bus);
-		return 0;
-	/* Look for the bus in the device-tree */
-	bus_id = (u8)simple_strtoul(adapter->name + 8, NULL, 16);
-	DBG("wf_lm75: bus ID is %x\n", bus_id);
-	/* Look for sensors subdir */
-	for (bus = NULL;
-	     (bus = of_get_next_child(smu, bus)) != NULL;) {
-		u32 *reg;
-		if (strcmp(bus->name, "i2c"))
-			continue;
-		reg = (u32 *)get_property(bus, "reg", NULL);
-		if (reg == NULL)
-			continue;
-		if (bus_id == *reg)
-			break;
-	}
-	of_node_put(smu);
-	if (bus == NULL) {
-		printk(KERN_WARNING "windfarm: SMU i2c bus 0x%x not found"
-		       " in device-tree !\n", bus_id);
-		return 0;
-	}
 	DBG("wf_lm75: bus found, looking for device...\n");
 	/* Now look for lm75(s) in there */
 	for (dev = NULL;
-	     (dev = of_get_next_child(bus, dev)) != NULL;) {
+	     (dev = of_get_next_child(busnode, dev)) != NULL;) {
 		const char *loc =
 			get_property(dev, "hwsensor-location", NULL);
 		u32 *reg = (u32 *)get_property(dev, "reg", NULL);
 		DBG(" dev: %s... (loc: %p, reg: %p)\n", dev->name, loc, reg);
 		if (loc == NULL || reg == NULL)
 			continue;
 		/* real lm75 */
 		if (device_is_compatible(dev, "lm75"))
 			wf_lm75_create(adapter, *reg, 0, loc);
 		/* ds1775 (compatible, better resolution */
 		else if (device_is_compatible(dev, "ds1775"))
 			wf_lm75_create(adapter, *reg, 1, loc);
 	}
-	of_node_put(bus);
 	return 0;
 }
 static int wf_lm75_detach(struct i2c_client *client)
 {
 	struct wf_lm75_sensor *lm = i2c_to_lm75(client);
 	DBG("wf_lm75: i2c detatch called for %s\n", lm->sens.name);
 	/* Mark client detached */
 	lm->i2c.adapter = NULL;
 	/* release sensor */
 	wf_unregister_sensor(&lm->sens);
 	return 0;
 }
 static int __init wf_lm75_sensor_init(void)
 {
 	return i2c_add_driver(&wf_lm75_driver);
 }
 static void __exit wf_lm75_sensor_exit(void)
 {
 	i2c_del_driver(&wf_lm75_driver);
 }
 module_init(wf_lm75_sensor_init);
 module_exit(wf_lm75_sensor_exit);
 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
 MODULE_DESCRIPTION("LM75 sensor objects for PowerMacs thermal control");
 MODULE_LICENSE("GPL");

include/asm-powerpc/pmac_low_i2c.h

Diff comments View file @ a28d3af

 /*
  *  include/asm-ppc/pmac_low_i2c.h
  *
  *  Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
  *
  *  This program is free software; you can redistribute it and/or
  *  modify it under the terms of the GNU General Public License
  *  as published by the Free Software Foundation; either version
  *  2 of the License, or (at your option) any later version.
  *
  */
 #ifndef __PMAC_LOW_I2C_H__
 #define __PMAC_LOW_I2C_H__
 #ifdef __KERNEL__
 /* i2c mode (based on the platform functions format) */
 enum {
 	pmac_i2c_mode_dumb	= 1,
 	pmac_i2c_mode_std	= 2,
 	pmac_i2c_mode_stdsub	= 3,
 	pmac_i2c_mode_combined	= 4,
 };
 /* RW bit in address */
 enum {
 	pmac_i2c_read		= 0x01,
 	pmac_i2c_write		= 0x00
 };
 /* i2c bus type */
 enum {
 	pmac_i2c_bus_keywest	= 0,
 	pmac_i2c_bus_pmu	= 1,
 	pmac_i2c_bus_smu	= 2,
 };
 /* i2c bus features */
 enum {
 	/* can_largesub : supports >1 byte subaddresses (SMU only) */
 	pmac_i2c_can_largesub	= 0x00000001u,
 	/* multibus : device node holds multiple busses, bus number is
 	 * encoded in bits 0xff00 of "reg" of a given device
 	 */
 	pmac_i2c_multibus	= 0x00000002u,
 };
 /* i2c busses in the system */
 struct pmac_i2c_bus;
 struct i2c_adapter;
 /* Init, called early during boot */
 extern int pmac_i2c_init(void);
 /* Lookup an i2c bus for a device-node. The node can be either the bus
  * node itself or a device below it. In the case of a multibus, the bus
  * node itself is the controller node, else, it's a child of the controller
  * node
  */
 extern struct pmac_i2c_bus *pmac_i2c_find_bus(struct device_node *node);
 /* Get the address for an i2c device. This strips the bus number if
  * necessary. The 7 bits address is returned 1 bit right shifted so that the
  * direction can be directly ored in
  */
 extern u8 pmac_i2c_get_dev_addr(struct device_node *device);
 /* Get infos about a bus */
 extern struct device_node *pmac_i2c_get_controller(struct pmac_i2c_bus *bus);
 extern struct device_node *pmac_i2c_get_bus_node(struct pmac_i2c_bus *bus);
 extern int pmac_i2c_get_type(struct pmac_i2c_bus *bus);
 extern int pmac_i2c_get_flags(struct pmac_i2c_bus *bus);
+extern int pmac_i2c_get_channel(struct pmac_i2c_bus *bus);
 /* i2c layer adapter attach/detach */
 extern void pmac_i2c_attach_adapter(struct pmac_i2c_bus *bus,
 				    struct i2c_adapter *adapter);
 extern void pmac_i2c_detach_adapter(struct pmac_i2c_bus *bus,
 				    struct i2c_adapter *adapter);
 extern struct i2c_adapter *pmac_i2c_get_adapter(struct pmac_i2c_bus *bus);
+extern struct pmac_i2c_bus *pmac_i2c_adapter_to_bus(struct i2c_adapter *adapter);
 /* March a device or bus with an i2c adapter structure, to be used by drivers
  * to match device-tree nodes with i2c adapters during adapter discovery
  * callbacks
  */
 extern int pmac_i2c_match_adapter(struct device_node *dev,
 				  struct i2c_adapter *adapter);
 /* (legacy) Locking functions exposed to i2c-keywest */
 extern int pmac_low_i2c_lock(struct device_node *np);
 extern int pmac_low_i2c_unlock(struct device_node *np);
 /* Access functions for platform code */
 extern int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled);
 extern void pmac_i2c_close(struct pmac_i2c_bus *bus);
 extern int pmac_i2c_setmode(struct pmac_i2c_bus *bus, int mode);
 extern int pmac_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
 			 u32 subaddr, u8 *data,  int len);
 #endif /* __KERNEL__ */
 #endif /* __PMAC_LOW_I2C_H__ */

1		1
2	menu "Macintosh device drivers"	2	menu "Macintosh device drivers"
3	depends on PPC \|\| MAC	3	depends on PPC \|\| MAC
4		4
5	config ADB	5	config ADB
6	bool "Apple Desktop Bus (ADB) support"	6	bool "Apple Desktop Bus (ADB) support"
7	depends on MAC \|\| (PPC_PMAC && PPC32)	7	depends on MAC \|\| (PPC_PMAC && PPC32)
8	help	8	help
9	Apple Desktop Bus (ADB) support is for support of devices which	9	Apple Desktop Bus (ADB) support is for support of devices which
10	are connected to an ADB port. ADB devices tend to have 4 pins.	10	are connected to an ADB port. ADB devices tend to have 4 pins.
11	If you have an Apple Macintosh prior to the iMac, an iBook or	11	If you have an Apple Macintosh prior to the iMac, an iBook or
12	PowerBook, or a "Blue and White G3", you probably want to say Y	12	PowerBook, or a "Blue and White G3", you probably want to say Y
13	here. Otherwise say N.	13	here. Otherwise say N.
14		14
15	config ADB_MACII	15	config ADB_MACII
16	bool "Include Mac II ADB driver"	16	bool "Include Mac II ADB driver"
17	depends on ADB && MAC	17	depends on ADB && MAC
18	help	18	help
19	Say Y here if want your kernel to support Macintosh systems that use	19	Say Y here if want your kernel to support Macintosh systems that use
20	the Mac II style ADB. This includes the II, IIx, IIcx, SE/30, IIci,	20	the Mac II style ADB. This includes the II, IIx, IIcx, SE/30, IIci,
21	Quadra 610, Quadra 650, Quadra 700, Quadra 800, Centris 610 and	21	Quadra 610, Quadra 650, Quadra 700, Quadra 800, Centris 610 and
22	Centris 650.	22	Centris 650.
23		23
24	config ADB_MACIISI	24	config ADB_MACIISI
25	bool "Include Mac IIsi ADB driver"	25	bool "Include Mac IIsi ADB driver"
26	depends on ADB && MAC	26	depends on ADB && MAC
27	help	27	help
28	Say Y here if want your kernel to support Macintosh systems that use	28	Say Y here if want your kernel to support Macintosh systems that use
29	the Mac IIsi style ADB. This includes the IIsi, IIvi, IIvx, Classic	29	the Mac IIsi style ADB. This includes the IIsi, IIvi, IIvx, Classic
30	II, LC, LC II, LC III, Performa 460, and the Performa 600.	30	II, LC, LC II, LC III, Performa 460, and the Performa 600.
31		31
32	config ADB_IOP	32	config ADB_IOP
33	bool "Include IOP (IIfx/Quadra 9x0) ADB driver"	33	bool "Include IOP (IIfx/Quadra 9x0) ADB driver"
34	depends on ADB && MAC	34	depends on ADB && MAC
35	help	35	help
36	The I/O Processor (IOP) is an Apple custom IC designed to provide	36	The I/O Processor (IOP) is an Apple custom IC designed to provide
37	intelligent support for I/O controllers. It is described at	37	intelligent support for I/O controllers. It is described at
38	<http://www.angelfire.com/ca2/dev68k/iopdesc.html> to enable direct	38	<http://www.angelfire.com/ca2/dev68k/iopdesc.html> to enable direct
39	support for it, say 'Y' here.	39	support for it, say 'Y' here.
40		40
41	config ADB_PMU68K	41	config ADB_PMU68K
42	bool "Include PMU (Powerbook) ADB driver"	42	bool "Include PMU (Powerbook) ADB driver"
43	depends on ADB && MAC	43	depends on ADB && MAC
44	help	44	help
45	Say Y here if want your kernel to support the m68k based Powerbooks.	45	Say Y here if want your kernel to support the m68k based Powerbooks.
46	This includes the PowerBook 140, PowerBook 145, PowerBook 150,	46	This includes the PowerBook 140, PowerBook 145, PowerBook 150,
47	PowerBook 160, PowerBook 165, PowerBook 165c, PowerBook 170,	47	PowerBook 160, PowerBook 165, PowerBook 165c, PowerBook 170,
48	PowerBook 180, PowerBook, 180c, PowerBook 190cs, PowerBook 520,	48	PowerBook 180, PowerBook, 180c, PowerBook 190cs, PowerBook 520,
49	PowerBook Duo 210, PowerBook Duo 230, PowerBook Duo 250,	49	PowerBook Duo 210, PowerBook Duo 230, PowerBook Duo 250,
50	PowerBook Duo 270c, PowerBook Duo 280 and PowerBook Duo 280c.	50	PowerBook Duo 270c, PowerBook Duo 280 and PowerBook Duo 280c.
51		51
52	# we want to change this to something like CONFIG_SYSCTRL_CUDA/PMU	52	# we want to change this to something like CONFIG_SYSCTRL_CUDA/PMU
53	config ADB_CUDA	53	config ADB_CUDA
54	bool "Support for CUDA based Macs and PowerMacs"	54	bool "Support for CUDA based Macs and PowerMacs"
55	depends on (ADB \|\| PPC_PMAC) && !PPC_PMAC64	55	depends on (ADB \|\| PPC_PMAC) && !PPC_PMAC64
56	help	56	help
57	This provides support for CUDA based Macintosh and Power Macintosh	57	This provides support for CUDA based Macintosh and Power Macintosh
58	systems. This includes many m68k based Macs (Color Classic, Mac TV,	58	systems. This includes many m68k based Macs (Color Classic, Mac TV,
59	Performa 475, Performa 520, Performa 550, Performa 575,	59	Performa 475, Performa 520, Performa 550, Performa 575,
60	Performa 588, Quadra 605, Quadra 630, Quadra/Centris 660AV, and	60	Performa 588, Quadra 605, Quadra 630, Quadra/Centris 660AV, and
61	Quadra 840AV), most OldWorld PowerMacs, the first generation iMacs,	61	Quadra 840AV), most OldWorld PowerMacs, the first generation iMacs,
62	the Blue&White G3 and the "Yikes" G4 (PCI Graphics). All later	62	the Blue&White G3 and the "Yikes" G4 (PCI Graphics). All later
63	models should use CONFIG_ADB_PMU instead. It is safe to say Y here	63	models should use CONFIG_ADB_PMU instead. It is safe to say Y here
64	even if your machine doesn't have a CUDA.	64	even if your machine doesn't have a CUDA.
65		65
66	If unsure say Y.	66	If unsure say Y.
67		67
68	config ADB_PMU	68	config ADB_PMU
69	bool "Support for PMU based PowerMacs"	69	bool "Support for PMU based PowerMacs"
70	depends on PPC_PMAC	70	depends on PPC_PMAC
71	help	71	help
72	On PowerBooks, iBooks, and recent iMacs and Power Macintoshes, the	72	On PowerBooks, iBooks, and recent iMacs and Power Macintoshes, the
73	PMU is an embedded microprocessor whose primary function is to	73	PMU is an embedded microprocessor whose primary function is to
74	control system power, and battery charging on the portable models.	74	control system power, and battery charging on the portable models.
75	The PMU also controls the ADB (Apple Desktop Bus) which connects to	75	The PMU also controls the ADB (Apple Desktop Bus) which connects to
76	the keyboard and mouse on some machines, as well as the non-volatile	76	the keyboard and mouse on some machines, as well as the non-volatile
77	RAM and the RTC (real time clock) chip. Say Y to enable support for	77	RAM and the RTC (real time clock) chip. Say Y to enable support for
78	this device; you should do so if your machine is one of those	78	this device; you should do so if your machine is one of those
79	mentioned above.	79	mentioned above.
80		80
81	config PMAC_SMU	81	config PMAC_SMU
82	bool "Support for SMU based PowerMacs"	82	bool "Support for SMU based PowerMacs"
83	depends on PPC_PMAC64	83	depends on PPC_PMAC64
84	help	84	help
85	This option adds support for the newer G5 iMacs and PowerMacs based	85	This option adds support for the newer G5 iMacs and PowerMacs based
86	on the "SMU" system control chip which replaces the old PMU.	86	on the "SMU" system control chip which replaces the old PMU.
87	If you don't know, say Y.	87	If you don't know, say Y.
88		88
89	config PMAC_APM_EMU	89	config PMAC_APM_EMU
90	tristate "APM emulation"	90	tristate "APM emulation"
91	depends on PPC_PMAC && PPC32 && PM	91	depends on PPC_PMAC && PPC32 && PM
92		92
93	config PMAC_MEDIABAY	93	config PMAC_MEDIABAY
94	bool "Support PowerBook hotswap media bay"	94	bool "Support PowerBook hotswap media bay"
95	depends on PPC_PMAC && PPC32	95	depends on PPC_PMAC && PPC32
96	help	96	help
97	This option adds support for older PowerBook's hotswap media bay	97	This option adds support for older PowerBook's hotswap media bay
98	that can contains batteries, floppy drives, or IDE devices. PCI	98	that can contains batteries, floppy drives, or IDE devices. PCI
99	devices are not fully supported in the bay as I never had one to	99	devices are not fully supported in the bay as I never had one to
100	try with	100	try with
101		101
102	# made a separate option since backlight may end up beeing used	102	# made a separate option since backlight may end up beeing used
103	# on non-powerbook machines (but only on PMU based ones AFAIK)	103	# on non-powerbook machines (but only on PMU based ones AFAIK)
104	config PMAC_BACKLIGHT	104	config PMAC_BACKLIGHT
105	bool "Backlight control for LCD screens"	105	bool "Backlight control for LCD screens"
106	depends on ADB_PMU && (BROKEN \|\| !PPC64)	106	depends on ADB_PMU && (BROKEN \|\| !PPC64)
107	help	107	help
108	Say Y here to build in code to manage the LCD backlight on a	108	Say Y here to build in code to manage the LCD backlight on a
109	Macintosh PowerBook. With this code, the backlight will be turned	109	Macintosh PowerBook. With this code, the backlight will be turned
110	on and off appropriately on power-management and lid-open/lid-closed	110	on and off appropriately on power-management and lid-open/lid-closed
111	events; also, the PowerBook button device will be enabled so you can	111	events; also, the PowerBook button device will be enabled so you can
112	change the screen brightness.	112	change the screen brightness.
113		113
114	config ADB_MACIO	114	config ADB_MACIO
115	bool "Include MacIO (CHRP) ADB driver"	115	bool "Include MacIO (CHRP) ADB driver"
116	depends on ADB && PPC_CHRP && !PPC_PMAC64	116	depends on ADB && PPC_CHRP && !PPC_PMAC64
117	help	117	help
118	Say Y here to include direct support for the ADB controller in the	118	Say Y here to include direct support for the ADB controller in the
119	Hydra chip used on PowerPC Macintoshes of the CHRP type. (The Hydra	119	Hydra chip used on PowerPC Macintoshes of the CHRP type. (The Hydra
120	also includes a MESH II SCSI controller, DBDMA controller, VIA chip,	120	also includes a MESH II SCSI controller, DBDMA controller, VIA chip,
121	OpenPIC controller and two RS422/Geoports.)	121	OpenPIC controller and two RS422/Geoports.)
122		122
123	config INPUT_ADBHID	123	config INPUT_ADBHID
124	bool "Support for ADB input devices (keyboard, mice, ...)"	124	bool "Support for ADB input devices (keyboard, mice, ...)"
125	depends on ADB && INPUT=y	125	depends on ADB && INPUT=y
126	help	126	help
127	Say Y here if you want to have ADB (Apple Desktop Bus) HID devices	127	Say Y here if you want to have ADB (Apple Desktop Bus) HID devices
128	such as keyboards, mice, joysticks, trackpads or graphic tablets	128	such as keyboards, mice, joysticks, trackpads or graphic tablets
129	handled by the input layer. If you say Y here, make sure to say Y to	129	handled by the input layer. If you say Y here, make sure to say Y to
130	the corresponding drivers "Keyboard support" (CONFIG_INPUT_KEYBDEV),	130	the corresponding drivers "Keyboard support" (CONFIG_INPUT_KEYBDEV),
131	"Mouse Support" (CONFIG_INPUT_MOUSEDEV) and "Event interface	131	"Mouse Support" (CONFIG_INPUT_MOUSEDEV) and "Event interface
132	support" (CONFIG_INPUT_EVDEV) as well.	132	support" (CONFIG_INPUT_EVDEV) as well.
133		133
134	If unsure, say Y.	134	If unsure, say Y.
135		135
136	config MAC_EMUMOUSEBTN	136	config MAC_EMUMOUSEBTN
137	bool "Support for mouse button 2+3 emulation"	137	bool "Support for mouse button 2+3 emulation"
138	depends on INPUT_ADBHID	138	depends on INPUT_ADBHID
139	help	139	help
140	This provides generic support for emulating the 2nd and 3rd mouse	140	This provides generic support for emulating the 2nd and 3rd mouse
141	button with keypresses. If you say Y here, the emulation is still	141	button with keypresses. If you say Y here, the emulation is still
142	disabled by default. The emulation is controlled by these sysctl	142	disabled by default. The emulation is controlled by these sysctl
143	entries:	143	entries:
144	/proc/sys/dev/mac_hid/mouse_button_emulation	144	/proc/sys/dev/mac_hid/mouse_button_emulation
145	/proc/sys/dev/mac_hid/mouse_button2_keycode	145	/proc/sys/dev/mac_hid/mouse_button2_keycode
146	/proc/sys/dev/mac_hid/mouse_button3_keycode	146	/proc/sys/dev/mac_hid/mouse_button3_keycode
147		147
148	If you have an Apple machine with a 1-button mouse, say Y here.	148	If you have an Apple machine with a 1-button mouse, say Y here.
149		149
150	config THERM_WINDTUNNEL	150	config THERM_WINDTUNNEL
151	tristate "Support for thermal management on Windtunnel G4s"	151	tristate "Support for thermal management on Windtunnel G4s"
152	depends on I2C && I2C_KEYWEST && PPC_PMAC && !PPC_PMAC64	152	depends on I2C && I2C_POWERMAC && PPC_PMAC && !PPC_PMAC64
153	help	153	help
154	This driver provides some thermostat and fan control for the desktop	154	This driver provides some thermostat and fan control for the desktop
155	G4 "Windtunnel"	155	G4 "Windtunnel"
156		156
157	config THERM_ADT746X	157	config THERM_ADT746X
158	tristate "Support for thermal mgmnt on laptops with ADT 746x chipset"	158	tristate "Support for thermal mgmnt on laptops with ADT 746x chipset"
159	depends on I2C && I2C_KEYWEST && PPC_PMAC && !PPC_PMAC64	159	depends on I2C && I2C_POWERMAC && PPC_PMAC && !PPC_PMAC64
160	help	160	help
161	This driver provides some thermostat and fan control for the	161	This driver provides some thermostat and fan control for the
162	iBook G4, and the ATI based aluminium PowerBooks, allowing slighlty	162	iBook G4, and the ATI based aluminium PowerBooks, allowing slighlty
163	better fan behaviour by default, and some manual control.	163	better fan behaviour by default, and some manual control.
164		164
165	config THERM_PM72	165	config THERM_PM72
166	tristate "Support for thermal management on PowerMac G5"	166	tristate "Support for thermal management on PowerMac G5"
167	depends on I2C && I2C_KEYWEST && PPC_PMAC64	167	depends on I2C && I2C_POWERMAC && PPC_PMAC64
168	help	168	help
169	This driver provides thermostat and fan control for the desktop	169	This driver provides thermostat and fan control for the desktop
170	G5 machines.	170	G5 machines.
171		171
172	config WINDFARM	172	config WINDFARM
173	tristate "New PowerMac thermal control infrastructure"	173	tristate "New PowerMac thermal control infrastructure"
174		174
175	config WINDFARM_PM81	175	config WINDFARM_PM81
176	tristate "Support for thermal management on iMac G5"	176	tristate "Support for thermal management on iMac G5"
177	depends on WINDFARM && I2C && CPU_FREQ_PMAC64 && PMAC_SMU	177	depends on WINDFARM && I2C && CPU_FREQ_PMAC64 && PMAC_SMU
178	select I2C_PMAC_SMU	178	select I2C_POWERMAC
179	help	179	help
180	This driver provides thermal control for the iMacG5	180	This driver provides thermal control for the iMacG5
181		181
182	config WINDFARM_PM91	182	config WINDFARM_PM91
183	tristate "Support for thermal management on PowerMac9,1"	183	tristate "Support for thermal management on PowerMac9,1"
184	depends on WINDFARM && I2C && CPU_FREQ_PMAC64 && PMAC_SMU	184	depends on WINDFARM && I2C && CPU_FREQ_PMAC64 && PMAC_SMU
185	select I2C_PMAC_SMU	185	select I2C_POWERMAC
186	help	186	help
187	This driver provides thermal control for the PowerMac9,1	187	This driver provides thermal control for the PowerMac9,1
188	which is the recent (SMU based) single CPU desktop G5	188	which is the recent (SMU based) single CPU desktop G5
189		189
190		190
191	config ANSLCD	191	config ANSLCD
192	tristate "Support for ANS LCD display"	192	tristate "Support for ANS LCD display"
193	depends on ADB_CUDA && PPC_PMAC	193	depends on ADB_CUDA && PPC_PMAC
194		194
195	endmenu	195	endmenu
196		196