Doug / smarc-fsl-linux-kernel

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/*

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/*

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* drivers/net/gianfar.c

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* drivers/net/gianfar.c

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*

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*

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* Gianfar Ethernet Driver

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* Gianfar Ethernet Driver

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* This driver is designed for the non-CPM ethernet controllers

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* This driver is designed for the non-CPM ethernet controllers

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* on the 85xx and 83xx family of integrated processors

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* on the 85xx and 83xx family of integrated processors

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* Based on 8260_io/fcc_enet.c

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* Based on 8260_io/fcc_enet.c

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*

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*

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* Author: Andy Fleming

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* Author: Andy Fleming

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* Maintainer: Kumar Gala

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* Maintainer: Kumar Gala

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* Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>

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* Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>

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*

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*

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*

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*

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* This program is free software; you can redistribute it and/or modify it

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* This program is free software; you can redistribute it and/or modify it

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* under the terms of the GNU General Public License as published by the

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* under the terms of the GNU General Public License as published by the

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* Free Software Foundation; either version 2 of the License, or (at your

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* Free Software Foundation; either version 2 of the License, or (at your

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* option) any later version.

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* option) any later version.

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*

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*

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* Gianfar: AKA Lambda Draconis, "Dragon"

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* Gianfar: AKA Lambda Draconis, "Dragon"

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* RA 11 31 24.2

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* RA 11 31 24.2

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* Dec +69 19 52

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* Dec +69 19 52

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* V 3.84

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* V 3.84

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* B-V +1.62

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* B-V +1.62

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*

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*

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* Theory of operation

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* Theory of operation

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*

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*

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* The driver is initialized through of_device. Configuration information

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* The driver is initialized through of_device. Configuration information

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* is therefore conveyed through an OF-style device tree.

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* is therefore conveyed through an OF-style device tree.

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*

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*

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* The Gianfar Ethernet Controller uses a ring of buffer

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* The Gianfar Ethernet Controller uses a ring of buffer

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* descriptors. The beginning is indicated by a register

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* descriptors. The beginning is indicated by a register

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* pointing to the physical address of the start of the ring.

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* pointing to the physical address of the start of the ring.

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* The end is determined by a "wrap" bit being set in the

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* The end is determined by a "wrap" bit being set in the

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* last descriptor of the ring.

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* last descriptor of the ring.

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*

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*

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* When a packet is received, the RXF bit in the

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* When a packet is received, the RXF bit in the

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* IEVENT register is set, triggering an interrupt when the

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* IEVENT register is set, triggering an interrupt when the

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* corresponding bit in the IMASK register is also set (if

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* corresponding bit in the IMASK register is also set (if

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* interrupt coalescing is active, then the interrupt may not

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* interrupt coalescing is active, then the interrupt may not

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* happen immediately, but will wait until either a set number

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* happen immediately, but will wait until either a set number

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* of frames or amount of time have passed). In NAPI, the

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* of frames or amount of time have passed). In NAPI, the

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* interrupt handler will signal there is work to be done, and

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* interrupt handler will signal there is work to be done, and

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* exit. This method will start at the last known empty

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* exit. This method will start at the last known empty

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* descriptor, and process every subsequent descriptor until there

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* descriptor, and process every subsequent descriptor until there

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* are none left with data (NAPI will stop after a set number of

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* are none left with data (NAPI will stop after a set number of

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* packets to give time to other tasks, but will eventually

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* packets to give time to other tasks, but will eventually

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* process all the packets). The data arrives inside a

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* process all the packets). The data arrives inside a

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* pre-allocated skb, and so after the skb is passed up to the

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* pre-allocated skb, and so after the skb is passed up to the

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* stack, a new skb must be allocated, and the address field in

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* stack, a new skb must be allocated, and the address field in

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* the buffer descriptor must be updated to indicate this new

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* the buffer descriptor must be updated to indicate this new

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* skb.

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* skb.

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*

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*

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* When the kernel requests that a packet be transmitted, the

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* When the kernel requests that a packet be transmitted, the

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* driver starts where it left off last time, and points the

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* driver starts where it left off last time, and points the

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* descriptor at the buffer which was passed in. The driver

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* descriptor at the buffer which was passed in. The driver

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* then informs the DMA engine that there are packets ready to

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* then informs the DMA engine that there are packets ready to

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* be transmitted. Once the controller is finished transmitting

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* be transmitted. Once the controller is finished transmitting

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* the packet, an interrupt may be triggered (under the same

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* the packet, an interrupt may be triggered (under the same

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* conditions as for reception, but depending on the TXF bit).

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* conditions as for reception, but depending on the TXF bit).

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* The driver then cleans up the buffer.

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* The driver then cleans up the buffer.

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*/

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*/

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/string.h>

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#include <linux/string.h>

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#include <linux/errno.h>

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#include <linux/errno.h>

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#include <linux/unistd.h>

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#include <linux/unistd.h>

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#include <linux/slab.h>

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#include <linux/slab.h>

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#include <linux/interrupt.h>

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#include <linux/interrupt.h>

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#include <linux/init.h>

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#include <linux/init.h>

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#include <linux/delay.h>

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#include <linux/delay.h>

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#include <linux/netdevice.h>

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#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/skbuff.h>

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#include <linux/skbuff.h>

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#include <linux/if_vlan.h>

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#include <linux/if_vlan.h>

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#include <linux/spinlock.h>

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#include <linux/spinlock.h>

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#include <linux/mm.h>

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#include <linux/mm.h>

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#include <linux/of_mdio.h>

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#include <linux/of_mdio.h>

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#include <linux/of_platform.h>

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#include <linux/of_platform.h>

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#include <linux/ip.h>

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#include <linux/ip.h>

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#include <linux/tcp.h>

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#include <linux/tcp.h>

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#include <linux/udp.h>

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#include <linux/udp.h>

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#include <linux/in.h>

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#include <linux/in.h>

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#include <asm/io.h>

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#include <asm/io.h>

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#include <asm/irq.h>

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#include <asm/irq.h>

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#include <asm/uaccess.h>

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#include <asm/uaccess.h>

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/dma-mapping.h>

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#include <linux/dma-mapping.h>

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#include <linux/crc32.h>

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#include <linux/crc32.h>

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#include <linux/mii.h>

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#include <linux/mii.h>

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#include <linux/phy.h>

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#include <linux/phy.h>

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#include <linux/phy_fixed.h>

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#include <linux/phy_fixed.h>

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#include <linux/of.h>

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#include <linux/of.h>

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#include "gianfar.h"

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#include "gianfar.h"

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#include "fsl_pq_mdio.h"

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#include "fsl_pq_mdio.h"

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#define TX_TIMEOUT (1*HZ)

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#define TX_TIMEOUT (1*HZ)

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#undef BRIEF_GFAR_ERRORS

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#undef BRIEF_GFAR_ERRORS

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#undef VERBOSE_GFAR_ERRORS

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#undef VERBOSE_GFAR_ERRORS

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const char gfar_driver_name[] = "Gianfar Ethernet";

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const char gfar_driver_name[] = "Gianfar Ethernet";

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const char gfar_driver_version[] = "1.3";

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const char gfar_driver_version[] = "1.3";

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static int gfar_enet_open(struct net_device *dev);

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static int gfar_enet_open(struct net_device *dev);

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static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);

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static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);

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static void gfar_reset_task(struct work_struct *work);

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static void gfar_reset_task(struct work_struct *work);

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static void gfar_timeout(struct net_device *dev);

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static void gfar_timeout(struct net_device *dev);

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static int gfar_close(struct net_device *dev);

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static int gfar_close(struct net_device *dev);

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struct sk_buff *gfar_new_skb(struct net_device *dev);

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struct sk_buff *gfar_new_skb(struct net_device *dev);

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static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,

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static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,

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struct sk_buff *skb);

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struct sk_buff *skb);

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static int gfar_set_mac_address(struct net_device *dev);

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static int gfar_set_mac_address(struct net_device *dev);

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static int gfar_change_mtu(struct net_device *dev, int new_mtu);

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static int gfar_change_mtu(struct net_device *dev, int new_mtu);

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static irqreturn_t gfar_error(int irq, void *dev_id);

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static irqreturn_t gfar_error(int irq, void *dev_id);

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static irqreturn_t gfar_transmit(int irq, void *dev_id);

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static irqreturn_t gfar_transmit(int irq, void *dev_id);

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static irqreturn_t gfar_interrupt(int irq, void *dev_id);

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static irqreturn_t gfar_interrupt(int irq, void *dev_id);

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static void adjust_link(struct net_device *dev);

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static void adjust_link(struct net_device *dev);

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static void init_registers(struct net_device *dev);

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static void init_registers(struct net_device *dev);

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static int init_phy(struct net_device *dev);

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static int init_phy(struct net_device *dev);

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static int gfar_probe(struct of_device *ofdev,

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static int gfar_probe(struct of_device *ofdev,

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const struct of_device_id *match);

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const struct of_device_id *match);

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static int gfar_remove(struct of_device *ofdev);

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static int gfar_remove(struct of_device *ofdev);

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static void free_skb_resources(struct gfar_private *priv);

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static void free_skb_resources(struct gfar_private *priv);

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static void gfar_set_multi(struct net_device *dev);

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static void gfar_set_multi(struct net_device *dev);

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static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);

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static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);

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static void gfar_configure_serdes(struct net_device *dev);

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static void gfar_configure_serdes(struct net_device *dev);

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static int gfar_poll(struct napi_struct *napi, int budget);

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static int gfar_poll(struct napi_struct *napi, int budget);

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#ifdef CONFIG_NET_POLL_CONTROLLER

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#ifdef CONFIG_NET_POLL_CONTROLLER

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static void gfar_netpoll(struct net_device *dev);

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static void gfar_netpoll(struct net_device *dev);

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#endif

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#endif

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int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);

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int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);

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static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);

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static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);

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static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,

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static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,

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int amount_pull);

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int amount_pull);

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static void gfar_vlan_rx_register(struct net_device *netdev,

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static void gfar_vlan_rx_register(struct net_device *netdev,

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struct vlan_group *grp);

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struct vlan_group *grp);

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void gfar_halt(struct net_device *dev);

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void gfar_halt(struct net_device *dev);

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static void gfar_halt_nodisable(struct net_device *dev);

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static void gfar_halt_nodisable(struct net_device *dev);

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void gfar_start(struct net_device *dev);

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void gfar_start(struct net_device *dev);

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static void gfar_clear_exact_match(struct net_device *dev);

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static void gfar_clear_exact_match(struct net_device *dev);

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static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);

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static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);

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static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);

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static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);

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u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb);

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u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb);

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MODULE_AUTHOR("Freescale Semiconductor, Inc");

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MODULE_AUTHOR("Freescale Semiconductor, Inc");

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MODULE_DESCRIPTION("Gianfar Ethernet Driver");

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MODULE_DESCRIPTION("Gianfar Ethernet Driver");

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MODULE_LICENSE("GPL");

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MODULE_LICENSE("GPL");

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static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,

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static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,

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dma_addr_t buf)

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dma_addr_t buf)

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{

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{

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u32 lstatus;

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u32 lstatus;

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157

bdp->bufPtr = buf;

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bdp->bufPtr = buf;

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159

lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);

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lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);

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if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)

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if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)

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lstatus |= BD_LFLAG(RXBD_WRAP);

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lstatus |= BD_LFLAG(RXBD_WRAP);

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163

eieio();

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eieio();

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bdp->lstatus = lstatus;

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bdp->lstatus = lstatus;

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}

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}

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168

static int gfar_init_bds(struct net_device *ndev)

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static int gfar_init_bds(struct net_device *ndev)

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{

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{

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struct gfar_private *priv = netdev_priv(ndev);

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struct gfar_private *priv = netdev_priv(ndev);

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struct gfar_priv_tx_q *tx_queue = NULL;

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struct gfar_priv_tx_q *tx_queue = NULL;

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struct gfar_priv_rx_q *rx_queue = NULL;

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struct gfar_priv_rx_q *rx_queue = NULL;

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struct txbd8 *txbdp;

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struct txbd8 *txbdp;

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struct rxbd8 *rxbdp;

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struct rxbd8 *rxbdp;

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int i, j;

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int i, j;

176

177

for (i = 0; i < priv->num_tx_queues; i++) {

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for (i = 0; i < priv->num_tx_queues; i++) {

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tx_queue = priv->tx_queue[i];

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tx_queue = priv->tx_queue[i];

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/* Initialize some variables in our dev structure */

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/* Initialize some variables in our dev structure */

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tx_queue->num_txbdfree = tx_queue->tx_ring_size;

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tx_queue->num_txbdfree = tx_queue->tx_ring_size;

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tx_queue->dirty_tx = tx_queue->tx_bd_base;

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tx_queue->dirty_tx = tx_queue->tx_bd_base;

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tx_queue->cur_tx = tx_queue->tx_bd_base;

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tx_queue->cur_tx = tx_queue->tx_bd_base;

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tx_queue->skb_curtx = 0;

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tx_queue->skb_curtx = 0;

184

tx_queue->skb_dirtytx = 0;

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tx_queue->skb_dirtytx = 0;

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186

/* Initialize Transmit Descriptor Ring */

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/* Initialize Transmit Descriptor Ring */

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txbdp = tx_queue->tx_bd_base;

187

txbdp = tx_queue->tx_bd_base;

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for (j = 0; j < tx_queue->tx_ring_size; j++) {

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for (j = 0; j < tx_queue->tx_ring_size; j++) {

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txbdp->lstatus = 0;

189

txbdp->lstatus = 0;

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txbdp->bufPtr = 0;

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txbdp->bufPtr = 0;

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txbdp++;

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txbdp++;

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}

192

}

193

194

/* Set the last descriptor in the ring to indicate wrap */

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/* Set the last descriptor in the ring to indicate wrap */

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txbdp--;

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txbdp--;

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txbdp->status |= TXBD_WRAP;

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txbdp->status |= TXBD_WRAP;

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}

197

}

198

199

for (i = 0; i < priv->num_rx_queues; i++) {

199

for (i = 0; i < priv->num_rx_queues; i++) {

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rx_queue = priv->rx_queue[i];

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rx_queue = priv->rx_queue[i];

201

rx_queue->cur_rx = rx_queue->rx_bd_base;

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rx_queue->cur_rx = rx_queue->rx_bd_base;

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rx_queue->skb_currx = 0;

202

rx_queue->skb_currx = 0;

203

rxbdp = rx_queue->rx_bd_base;

203

rxbdp = rx_queue->rx_bd_base;

204

205

for (j = 0; j < rx_queue->rx_ring_size; j++) {

205

for (j = 0; j < rx_queue->rx_ring_size; j++) {

206

struct sk_buff *skb = rx_queue->rx_skbuff[j];

206

struct sk_buff *skb = rx_queue->rx_skbuff[j];

207

208

if (skb) {

208

if (skb) {

209

gfar_init_rxbdp(rx_queue, rxbdp,

209

gfar_init_rxbdp(rx_queue, rxbdp,

210

rxbdp->bufPtr);

210

rxbdp->bufPtr);

211

} else {

211

} else {

212

skb = gfar_new_skb(ndev);

212

skb = gfar_new_skb(ndev);

213

if (!skb) {

213

if (!skb) {

214

pr_err("%s: Can't allocate RX buffers\n",

214

pr_err("%s: Can't allocate RX buffers\n",

215

ndev->name);

215

ndev->name);

216

goto err_rxalloc_fail;

216

goto err_rxalloc_fail;

217

}

217

}

218

rx_queue->rx_skbuff[j] = skb;

218

rx_queue->rx_skbuff[j] = skb;

219

220

gfar_new_rxbdp(rx_queue, rxbdp, skb);

220

gfar_new_rxbdp(rx_queue, rxbdp, skb);

221

}

221

}

222

223

rxbdp++;

223

rxbdp++;

224

}

224

}

225

226

}

226

}

227

228

return 0;

228

return 0;

229

230

err_rxalloc_fail:

230

err_rxalloc_fail:

231

free_skb_resources(priv);

231

free_skb_resources(priv);

232

return -ENOMEM;

232

return -ENOMEM;

233

}

233

}

234

235

static int gfar_alloc_skb_resources(struct net_device *ndev)

235

static int gfar_alloc_skb_resources(struct net_device *ndev)

236

{

236

{

237

void *vaddr;

237

void *vaddr;

238

dma_addr_t addr;

238

dma_addr_t addr;

239

int i, j, k;

239

int i, j, k;

240

struct gfar_private *priv = netdev_priv(ndev);

240

struct gfar_private *priv = netdev_priv(ndev);

241

struct device *dev = &priv->ofdev->dev;

241

struct device *dev = &priv->ofdev->dev;

242

struct gfar_priv_tx_q *tx_queue = NULL;

242

struct gfar_priv_tx_q *tx_queue = NULL;

243

struct gfar_priv_rx_q *rx_queue = NULL;

243

struct gfar_priv_rx_q *rx_queue = NULL;

244

245

priv->total_tx_ring_size = 0;

245

priv->total_tx_ring_size = 0;

246

for (i = 0; i < priv->num_tx_queues; i++)

246

for (i = 0; i < priv->num_tx_queues; i++)

247

priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;

247

priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;

248

249

priv->total_rx_ring_size = 0;

249

priv->total_rx_ring_size = 0;

250

for (i = 0; i < priv->num_rx_queues; i++)

250

for (i = 0; i < priv->num_rx_queues; i++)

251

priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;

251

priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;

252

253

/* Allocate memory for the buffer descriptors */

253

/* Allocate memory for the buffer descriptors */

254

vaddr = dma_alloc_coherent(dev,

254

vaddr = dma_alloc_coherent(dev,

255

sizeof(struct txbd8) * priv->total_tx_ring_size +

255

sizeof(struct txbd8) * priv->total_tx_ring_size +

256

sizeof(struct rxbd8) * priv->total_rx_ring_size,

256

sizeof(struct rxbd8) * priv->total_rx_ring_size,

257

&addr, GFP_KERNEL);

257

&addr, GFP_KERNEL);

258

if (!vaddr) {

258

if (!vaddr) {

259

if (netif_msg_ifup(priv))

259

if (netif_msg_ifup(priv))

260

pr_err("%s: Could not allocate buffer descriptors!\n",

260

pr_err("%s: Could not allocate buffer descriptors!\n",

261

ndev->name);

261

ndev->name);

262

return -ENOMEM;

262

return -ENOMEM;

263

}

263

}

264

265

for (i = 0; i < priv->num_tx_queues; i++) {

265

for (i = 0; i < priv->num_tx_queues; i++) {

266

tx_queue = priv->tx_queue[i];

266

tx_queue = priv->tx_queue[i];

267

tx_queue->tx_bd_base = (struct txbd8 *) vaddr;

267

tx_queue->tx_bd_base = (struct txbd8 *) vaddr;

268

tx_queue->tx_bd_dma_base = addr;

268

tx_queue->tx_bd_dma_base = addr;

269

tx_queue->dev = ndev;

269

tx_queue->dev = ndev;

270

/* enet DMA only understands physical addresses */

270

/* enet DMA only understands physical addresses */

271

addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;

271

addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;

272

vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;

272

vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;

273

}

273

}

274

275

/* Start the rx descriptor ring where the tx ring leaves off */

275

/* Start the rx descriptor ring where the tx ring leaves off */

276

for (i = 0; i < priv->num_rx_queues; i++) {

276

for (i = 0; i < priv->num_rx_queues; i++) {

277

rx_queue = priv->rx_queue[i];

277

rx_queue = priv->rx_queue[i];

278

rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;

278

rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;

279

rx_queue->rx_bd_dma_base = addr;

279

rx_queue->rx_bd_dma_base = addr;

280

rx_queue->dev = ndev;

280

rx_queue->dev = ndev;

281

addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;

281

addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;

282

vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;

282

vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;

283

}

283

}

284

285

/* Setup the skbuff rings */

285

/* Setup the skbuff rings */

286

for (i = 0; i < priv->num_tx_queues; i++) {

286

for (i = 0; i < priv->num_tx_queues; i++) {

287

tx_queue = priv->tx_queue[i];

287

tx_queue = priv->tx_queue[i];

288

tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *

288

tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *

289

tx_queue->tx_ring_size, GFP_KERNEL);

289

tx_queue->tx_ring_size, GFP_KERNEL);

290

if (!tx_queue->tx_skbuff) {

290

if (!tx_queue->tx_skbuff) {

291

if (netif_msg_ifup(priv))

291

if (netif_msg_ifup(priv))

292

pr_err("%s: Could not allocate tx_skbuff\n",

292

pr_err("%s: Could not allocate tx_skbuff\n",

293

ndev->name);

293

ndev->name);

294

goto cleanup;

294

goto cleanup;

295

}

295

}

296

297

for (k = 0; k < tx_queue->tx_ring_size; k++)

297

for (k = 0; k < tx_queue->tx_ring_size; k++)

298

tx_queue->tx_skbuff[k] = NULL;

298

tx_queue->tx_skbuff[k] = NULL;

299

}

299

}

300

301

for (i = 0; i < priv->num_rx_queues; i++) {

301

for (i = 0; i < priv->num_rx_queues; i++) {

302

rx_queue = priv->rx_queue[i];

302

rx_queue = priv->rx_queue[i];

303

rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *

303

rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *

304

rx_queue->rx_ring_size, GFP_KERNEL);

304

rx_queue->rx_ring_size, GFP_KERNEL);

305

306

if (!rx_queue->rx_skbuff) {

306

if (!rx_queue->rx_skbuff) {

307

if (netif_msg_ifup(priv))

307

if (netif_msg_ifup(priv))

308

pr_err("%s: Could not allocate rx_skbuff\n",

308

pr_err("%s: Could not allocate rx_skbuff\n",

309

ndev->name);

309

ndev->name);

310

goto cleanup;

310

goto cleanup;

311

}

311

}

312

313

for (j = 0; j < rx_queue->rx_ring_size; j++)

313

for (j = 0; j < rx_queue->rx_ring_size; j++)

314

rx_queue->rx_skbuff[j] = NULL;

314

rx_queue->rx_skbuff[j] = NULL;

315

}

315

}

316

317

if (gfar_init_bds(ndev))

317

if (gfar_init_bds(ndev))

318

goto cleanup;

318

goto cleanup;

319

320

return 0;

320

return 0;

321

322

cleanup:

322

cleanup:

323

free_skb_resources(priv);

323

free_skb_resources(priv);

324

return -ENOMEM;

324

return -ENOMEM;

325

}

325

}

326

327

static void gfar_init_tx_rx_base(struct gfar_private *priv)

327

static void gfar_init_tx_rx_base(struct gfar_private *priv)

328

{

328

{

329

struct gfar __iomem *regs = priv->gfargrp[0].regs;

329

struct gfar __iomem *regs = priv->gfargrp[0].regs;

330

u32 __iomem *baddr;

330

u32 __iomem *baddr;

331

int i;

331

int i;

332

333

baddr = &regs->tbase0;

333

baddr = &regs->tbase0;

334

for(i = 0; i < priv->num_tx_queues; i++) {

334

for(i = 0; i < priv->num_tx_queues; i++) {

335

gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);

335

gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);

336

baddr += 2;

336

baddr += 2;

337

}

337

}

338

339

baddr = &regs->rbase0;

339

baddr = &regs->rbase0;

340

for(i = 0; i < priv->num_rx_queues; i++) {

340

for(i = 0; i < priv->num_rx_queues; i++) {

341

gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);

341

gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);

342

baddr += 2;

342

baddr += 2;

343

}

343

}

344

}

344

}

345

346

static void gfar_init_mac(struct net_device *ndev)

346

static void gfar_init_mac(struct net_device *ndev)

347

{

347

{

348

struct gfar_private *priv = netdev_priv(ndev);

348

struct gfar_private *priv = netdev_priv(ndev);

349

struct gfar __iomem *regs = priv->gfargrp[0].regs;

349

struct gfar __iomem *regs = priv->gfargrp[0].regs;

350

u32 rctrl = 0;

350

u32 rctrl = 0;

351

u32 tctrl = 0;

351

u32 tctrl = 0;

352

u32 attrs = 0;

352

u32 attrs = 0;

353

354

/* write the tx/rx base registers */

354

/* write the tx/rx base registers */

355

gfar_init_tx_rx_base(priv);

355

gfar_init_tx_rx_base(priv);

356

357

/* Configure the coalescing support */

357

/* Configure the coalescing support */

358

gfar_configure_coalescing(priv, 0xFF, 0xFF);

358

gfar_configure_coalescing(priv, 0xFF, 0xFF);

359

360

if (priv->rx_filer_enable)

360

if (priv->rx_filer_enable)

361

rctrl |= RCTRL_FILREN;

361

rctrl |= RCTRL_FILREN;

362

363

if (priv->rx_csum_enable)

363

if (priv->rx_csum_enable)

364

rctrl |= RCTRL_CHECKSUMMING;

364

rctrl |= RCTRL_CHECKSUMMING;

365

366

if (priv->extended_hash) {

366

if (priv->extended_hash) {

367

rctrl |= RCTRL_EXTHASH;

367

rctrl |= RCTRL_EXTHASH;

368

369

gfar_clear_exact_match(ndev);

369

gfar_clear_exact_match(ndev);

370

rctrl |= RCTRL_EMEN;

370

rctrl |= RCTRL_EMEN;

371

}

371

}

372

373

if (priv->padding) {

373

if (priv->padding) {

374

rctrl &= ~RCTRL_PAL_MASK;

374

rctrl &= ~RCTRL_PAL_MASK;

375

rctrl |= RCTRL_PADDING(priv->padding);

375

rctrl |= RCTRL_PADDING(priv->padding);

376

}

376

}

377

378

/* keep vlan related bits if it's enabled */

378

/* keep vlan related bits if it's enabled */

379

if (priv->vlgrp) {

379

if (priv->vlgrp) {

380

rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;

380

rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;

381

tctrl |= TCTRL_VLINS;

381

tctrl |= TCTRL_VLINS;

382

}

382

}

383

384

/* Init rctrl based on our settings */

384

/* Init rctrl based on our settings */

385

gfar_write(&regs->rctrl, rctrl);

385

gfar_write(&regs->rctrl, rctrl);

386

387

if (ndev->features & NETIF_F_IP_CSUM)

387

if (ndev->features & NETIF_F_IP_CSUM)

388

tctrl |= TCTRL_INIT_CSUM;

388

tctrl |= TCTRL_INIT_CSUM;

389

390

tctrl |= TCTRL_TXSCHED_PRIO;

390

tctrl |= TCTRL_TXSCHED_PRIO;

391

392

gfar_write(&regs->tctrl, tctrl);

392

gfar_write(&regs->tctrl, tctrl);

393

394

/* Set the extraction length and index */

394

/* Set the extraction length and index */

395

attrs = ATTRELI_EL(priv->rx_stash_size) |

395

attrs = ATTRELI_EL(priv->rx_stash_size) |

396

ATTRELI_EI(priv->rx_stash_index);

396

ATTRELI_EI(priv->rx_stash_index);

397

398

gfar_write(&regs->attreli, attrs);

398

gfar_write(&regs->attreli, attrs);

399

400

/* Start with defaults, and add stashing or locking

400

/* Start with defaults, and add stashing or locking

401

* depending on the approprate variables */

401

* depending on the approprate variables */

402

attrs = ATTR_INIT_SETTINGS;

402

attrs = ATTR_INIT_SETTINGS;

403

404

if (priv->bd_stash_en)

404

if (priv->bd_stash_en)

405

attrs |= ATTR_BDSTASH;

405

attrs |= ATTR_BDSTASH;

406

407

if (priv->rx_stash_size != 0)

407

if (priv->rx_stash_size != 0)

408

attrs |= ATTR_BUFSTASH;

408

attrs |= ATTR_BUFSTASH;

409

410

gfar_write(&regs->attr, attrs);

410

gfar_write(&regs->attr, attrs);

411

412

gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);

412

gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);

413

gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);

413

gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);

414

gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);

414

gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);

415

}

415

}

416

417

static const struct net_device_ops gfar_netdev_ops = {

417

static const struct net_device_ops gfar_netdev_ops = {

418

.ndo_open = gfar_enet_open,

418

.ndo_open = gfar_enet_open,

419

.ndo_start_xmit = gfar_start_xmit,

419

.ndo_start_xmit = gfar_start_xmit,

420

.ndo_stop = gfar_close,

420

.ndo_stop = gfar_close,

421

.ndo_change_mtu = gfar_change_mtu,

421

.ndo_change_mtu = gfar_change_mtu,

422

.ndo_set_multicast_list = gfar_set_multi,

422

.ndo_set_multicast_list = gfar_set_multi,

423

.ndo_tx_timeout = gfar_timeout,

423

.ndo_tx_timeout = gfar_timeout,

424

.ndo_do_ioctl = gfar_ioctl,

424

.ndo_do_ioctl = gfar_ioctl,

425

.ndo_select_queue = gfar_select_queue,

425

.ndo_select_queue = gfar_select_queue,

426

.ndo_vlan_rx_register = gfar_vlan_rx_register,

426

.ndo_vlan_rx_register = gfar_vlan_rx_register,

427

.ndo_set_mac_address = eth_mac_addr,

427

.ndo_set_mac_address = eth_mac_addr,

428

.ndo_validate_addr = eth_validate_addr,

428

.ndo_validate_addr = eth_validate_addr,

429

#ifdef CONFIG_NET_POLL_CONTROLLER

429

#ifdef CONFIG_NET_POLL_CONTROLLER

430

.ndo_poll_controller = gfar_netpoll,

430

.ndo_poll_controller = gfar_netpoll,

431

#endif

431

#endif

432

};

432

};

433

434

unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];

434

unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];

435

unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];

435

unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];

436

437

void lock_rx_qs(struct gfar_private *priv)

437

void lock_rx_qs(struct gfar_private *priv)

438

{

438

{

439

int i = 0x0;

439

int i = 0x0;

440

441

for (i = 0; i < priv->num_rx_queues; i++)

441

for (i = 0; i < priv->num_rx_queues; i++)

442

spin_lock(&priv->rx_queue[i]->rxlock);

442

spin_lock(&priv->rx_queue[i]->rxlock);

443

}

443

}

444

445

void lock_tx_qs(struct gfar_private *priv)

445

void lock_tx_qs(struct gfar_private *priv)

446

{

446

{

447

int i = 0x0;

447

int i = 0x0;

448

449

for (i = 0; i < priv->num_tx_queues; i++)

449

for (i = 0; i < priv->num_tx_queues; i++)

450

spin_lock(&priv->tx_queue[i]->txlock);

450

spin_lock(&priv->tx_queue[i]->txlock);

451

}

451

}

452

453

void unlock_rx_qs(struct gfar_private *priv)

453

void unlock_rx_qs(struct gfar_private *priv)

454

{

454

{

455

int i = 0x0;

455

int i = 0x0;

456

457

for (i = 0; i < priv->num_rx_queues; i++)

457

for (i = 0; i < priv->num_rx_queues; i++)

458

spin_unlock(&priv->rx_queue[i]->rxlock);

458

spin_unlock(&priv->rx_queue[i]->rxlock);

459

}

459

}

460

461

void unlock_tx_qs(struct gfar_private *priv)

461

void unlock_tx_qs(struct gfar_private *priv)

462

{

462

{

463

int i = 0x0;

463

int i = 0x0;

464

465

for (i = 0; i < priv->num_tx_queues; i++)

465

for (i = 0; i < priv->num_tx_queues; i++)

466

spin_unlock(&priv->tx_queue[i]->txlock);

466

spin_unlock(&priv->tx_queue[i]->txlock);

467

}

467

}

468

469

/* Returns 1 if incoming frames use an FCB */

469

/* Returns 1 if incoming frames use an FCB */

470

static inline int gfar_uses_fcb(struct gfar_private *priv)

470

static inline int gfar_uses_fcb(struct gfar_private *priv)

471

{

471

{

472

return priv->vlgrp || priv->rx_csum_enable;

472

return priv->vlgrp || priv->rx_csum_enable;

473

}

473

}

474

475

u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb)

475

u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb)

476

{

476

{

477

return skb_get_queue_mapping(skb);

477

return skb_get_queue_mapping(skb);

478

}

478

}

479

static void free_tx_pointers(struct gfar_private *priv)

479

static void free_tx_pointers(struct gfar_private *priv)

480

{

480

{

481

int i = 0;

481

int i = 0;

482

483

for (i = 0; i < priv->num_tx_queues; i++)

483

for (i = 0; i < priv->num_tx_queues; i++)

484

kfree(priv->tx_queue[i]);

484

kfree(priv->tx_queue[i]);

485

}

485

}

486

487

static void free_rx_pointers(struct gfar_private *priv)

487

static void free_rx_pointers(struct gfar_private *priv)

488

{

488

{

489

int i = 0;

489

int i = 0;

490

491

for (i = 0; i < priv->num_rx_queues; i++)

491

for (i = 0; i < priv->num_rx_queues; i++)

492

kfree(priv->rx_queue[i]);

492

kfree(priv->rx_queue[i]);

493

}

493

}

494

495

static void unmap_group_regs(struct gfar_private *priv)

495

static void unmap_group_regs(struct gfar_private *priv)

496

{

496

{

497

int i = 0;

497

int i = 0;

498

499

for (i = 0; i < MAXGROUPS; i++)

499

for (i = 0; i < MAXGROUPS; i++)

500

if (priv->gfargrp[i].regs)

500

if (priv->gfargrp[i].regs)

501

iounmap(priv->gfargrp[i].regs);

501

iounmap(priv->gfargrp[i].regs);

502

}

502

}

503

504

static void disable_napi(struct gfar_private *priv)

504

static void disable_napi(struct gfar_private *priv)

505

{

505

{

506

int i = 0;

506

int i = 0;

507

508

for (i = 0; i < priv->num_grps; i++)

508

for (i = 0; i < priv->num_grps; i++)

509

napi_disable(&priv->gfargrp[i].napi);

509

napi_disable(&priv->gfargrp[i].napi);

510

}

510

}

511

512

static void enable_napi(struct gfar_private *priv)

512

static void enable_napi(struct gfar_private *priv)

513

{

513

{

514

int i = 0;

514

int i = 0;

515

516

for (i = 0; i < priv->num_grps; i++)

516

for (i = 0; i < priv->num_grps; i++)

517

napi_enable(&priv->gfargrp[i].napi);

517

napi_enable(&priv->gfargrp[i].napi);

518

}

518

}

519

520

static int gfar_parse_group(struct device_node *np,

520

static int gfar_parse_group(struct device_node *np,

521

struct gfar_private *priv, const char *model)

521

struct gfar_private *priv, const char *model)

522

{

522

{

523

u32 *queue_mask;

523

u32 *queue_mask;

524

u64 addr, size;

524

u64 addr, size;

525

526

addr = of_translate_address(np,

526

addr = of_translate_address(np,

527

of_get_address(np, 0, &size, NULL));

527

of_get_address(np, 0, &size, NULL));

528

priv->gfargrp[priv->num_grps].regs = ioremap(addr, size);

528

priv->gfargrp[priv->num_grps].regs = ioremap(addr, size);

529

530

if (!priv->gfargrp[priv->num_grps].regs)

530

if (!priv->gfargrp[priv->num_grps].regs)

531

return -ENOMEM;

531

return -ENOMEM;

532

533

priv->gfargrp[priv->num_grps].interruptTransmit =

533

priv->gfargrp[priv->num_grps].interruptTransmit =

534

irq_of_parse_and_map(np, 0);

534

irq_of_parse_and_map(np, 0);

535

536

/* If we aren't the FEC we have multiple interrupts */

536

/* If we aren't the FEC we have multiple interrupts */

537

if (model && strcasecmp(model, "FEC")) {

537

if (model && strcasecmp(model, "FEC")) {

538

priv->gfargrp[priv->num_grps].interruptReceive =

538

priv->gfargrp[priv->num_grps].interruptReceive =

539

irq_of_parse_and_map(np, 1);

539

irq_of_parse_and_map(np, 1);

540

priv->gfargrp[priv->num_grps].interruptError =

540

priv->gfargrp[priv->num_grps].interruptError =

541

irq_of_parse_and_map(np,2);

541

irq_of_parse_and_map(np,2);

542

if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||

542

if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||

543

priv->gfargrp[priv->num_grps].interruptReceive < 0 ||

543

priv->gfargrp[priv->num_grps].interruptReceive < 0 ||

544

priv->gfargrp[priv->num_grps].interruptError < 0) {

544

priv->gfargrp[priv->num_grps].interruptError < 0) {

545

return -EINVAL;

545

return -EINVAL;

546

}

546

}

547

}

547

}

548

549

priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;

549

priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;

550

priv->gfargrp[priv->num_grps].priv = priv;

550

priv->gfargrp[priv->num_grps].priv = priv;

551

spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);

551

spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);

552

if(priv->mode == MQ_MG_MODE) {

552

if(priv->mode == MQ_MG_MODE) {

553

queue_mask = (u32 *)of_get_property(np,

553

queue_mask = (u32 *)of_get_property(np,

554

"fsl,rx-bit-map", NULL);

554

"fsl,rx-bit-map", NULL);

555

priv->gfargrp[priv->num_grps].rx_bit_map =

555

priv->gfargrp[priv->num_grps].rx_bit_map =

556

queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);

556

queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);

557

queue_mask = (u32 *)of_get_property(np,

557

queue_mask = (u32 *)of_get_property(np,

558

"fsl,tx-bit-map", NULL);

558

"fsl,tx-bit-map", NULL);

559

priv->gfargrp[priv->num_grps].tx_bit_map =

559

priv->gfargrp[priv->num_grps].tx_bit_map =

560

queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);

560

queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);

561

} else {

561

} else {

562

priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;

562

priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;

563

priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;

563

priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;

564

}

564

}

565

priv->num_grps++;

565

priv->num_grps++;

566

567

return 0;

567

return 0;

568

}

568

}

569

570

static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)

570

static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)

571

{

571

{

572

const char *model;

572

const char *model;

573

const char *ctype;

573

const char *ctype;

574

const void *mac_addr;

574

const void *mac_addr;

575

int err = 0, i;

575

int err = 0, i;

576

struct net_device *dev = NULL;

576

struct net_device *dev = NULL;

577

struct gfar_private *priv = NULL;

577

struct gfar_private *priv = NULL;

578

struct device_node *np = ofdev->node;

578

struct device_node *np = ofdev->node;

579

struct device_node *child = NULL;

579

struct device_node *child = NULL;

580

const u32 *stash;

580

const u32 *stash;

581

const u32 *stash_len;

581

const u32 *stash_len;

582

const u32 *stash_idx;

582

const u32 *stash_idx;

583

unsigned int num_tx_qs, num_rx_qs;

583

unsigned int num_tx_qs, num_rx_qs;

584

u32 *tx_queues, *rx_queues;

584

u32 *tx_queues, *rx_queues;

585

586

if (!np || !of_device_is_available(np))

586

if (!np || !of_device_is_available(np))

587

return -ENODEV;

587

return -ENODEV;

588

589

/* parse the num of tx and rx queues */

589

/* parse the num of tx and rx queues */

590

tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);

590

tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);

591

num_tx_qs = tx_queues ? *tx_queues : 1;

591

num_tx_qs = tx_queues ? *tx_queues : 1;

592

593

if (num_tx_qs > MAX_TX_QS) {

593

if (num_tx_qs > MAX_TX_QS) {

594

printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",

594

printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",

595

num_tx_qs, MAX_TX_QS);

595

num_tx_qs, MAX_TX_QS);

596

printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");

596

printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");

597

return -EINVAL;

597

return -EINVAL;

598

}

598

}

599

600

rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);

600

rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);

601

num_rx_qs = rx_queues ? *rx_queues : 1;

601

num_rx_qs = rx_queues ? *rx_queues : 1;

602

603

if (num_rx_qs > MAX_RX_QS) {

603

if (num_rx_qs > MAX_RX_QS) {

604

printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",

604

printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",

605

num_tx_qs, MAX_TX_QS);

605

num_tx_qs, MAX_TX_QS);

606

printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");

606

printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");

607

return -EINVAL;

607

return -EINVAL;

608

}

608

}

609

610

*pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);

610

*pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);

611

dev = *pdev;

611

dev = *pdev;

612

if (NULL == dev)

612

if (NULL == dev)

613

return -ENOMEM;

613

return -ENOMEM;

614

615

priv = netdev_priv(dev);

615

priv = netdev_priv(dev);

616

priv->node = ofdev->node;

616

priv->node = ofdev->node;

617

priv->ndev = dev;

617

priv->ndev = dev;

618

619

dev->num_tx_queues = num_tx_qs;

619

dev->num_tx_queues = num_tx_qs;

620

dev->real_num_tx_queues = num_tx_qs;

620

dev->real_num_tx_queues = num_tx_qs;

621

priv->num_tx_queues = num_tx_qs;

621

priv->num_tx_queues = num_tx_qs;

622

priv->num_rx_queues = num_rx_qs;

622

priv->num_rx_queues = num_rx_qs;

623

priv->num_grps = 0x0;

623

priv->num_grps = 0x0;

624

625

model = of_get_property(np, "model", NULL);

625

model = of_get_property(np, "model", NULL);

626

627

for (i = 0; i < MAXGROUPS; i++)

627

for (i = 0; i < MAXGROUPS; i++)

628

priv->gfargrp[i].regs = NULL;

628

priv->gfargrp[i].regs = NULL;

629

630

/* Parse and initialize group specific information */

630

/* Parse and initialize group specific information */

631

if (of_device_is_compatible(np, "fsl,etsec2")) {

631

if (of_device_is_compatible(np, "fsl,etsec2")) {

632

priv->mode = MQ_MG_MODE;

632

priv->mode = MQ_MG_MODE;

633

for_each_child_of_node(np, child) {

633

for_each_child_of_node(np, child) {

634

err = gfar_parse_group(child, priv, model);

634

err = gfar_parse_group(child, priv, model);

635

if (err)

635

if (err)

636

goto err_grp_init;

636

goto err_grp_init;

637

}

637

}

638

} else {

638

} else {

639

priv->mode = SQ_SG_MODE;

639

priv->mode = SQ_SG_MODE;

640

err = gfar_parse_group(np, priv, model);

640

err = gfar_parse_group(np, priv, model);

641

if(err)

641

if(err)

642

goto err_grp_init;

642

goto err_grp_init;

643

}

643

}

644

645

for (i = 0; i < priv->num_tx_queues; i++)

645

for (i = 0; i < priv->num_tx_queues; i++)

646

priv->tx_queue[i] = NULL;

646

priv->tx_queue[i] = NULL;

647

for (i = 0; i < priv->num_rx_queues; i++)

647

for (i = 0; i < priv->num_rx_queues; i++)

648

priv->rx_queue[i] = NULL;

648

priv->rx_queue[i] = NULL;

649

650

for (i = 0; i < priv->num_tx_queues; i++) {

650

for (i = 0; i < priv->num_tx_queues; i++) {

651

priv->tx_queue[i] = (struct gfar_priv_tx_q *)kmalloc(

651

priv->tx_queue[i] = (struct gfar_priv_tx_q *)kmalloc(

652

sizeof (struct gfar_priv_tx_q), GFP_KERNEL);

652

sizeof (struct gfar_priv_tx_q), GFP_KERNEL);

653

if (!priv->tx_queue[i]) {

653

if (!priv->tx_queue[i]) {

654

err = -ENOMEM;

654

err = -ENOMEM;

655

goto tx_alloc_failed;

655

goto tx_alloc_failed;

656

}

656

}

657

priv->tx_queue[i]->tx_skbuff = NULL;

657

priv->tx_queue[i]->tx_skbuff = NULL;

658

priv->tx_queue[i]->qindex = i;

658

priv->tx_queue[i]->qindex = i;

659

priv->tx_queue[i]->dev = dev;

659

priv->tx_queue[i]->dev = dev;

660

spin_lock_init(&(priv->tx_queue[i]->txlock));

660

spin_lock_init(&(priv->tx_queue[i]->txlock));

661

}

661

}

662

663

for (i = 0; i < priv->num_rx_queues; i++) {

663

for (i = 0; i < priv->num_rx_queues; i++) {

664

priv->rx_queue[i] = (struct gfar_priv_rx_q *)kmalloc(

664

priv->rx_queue[i] = (struct gfar_priv_rx_q *)kmalloc(

665

sizeof (struct gfar_priv_rx_q), GFP_KERNEL);

665

sizeof (struct gfar_priv_rx_q), GFP_KERNEL);

666

if (!priv->rx_queue[i]) {

666

if (!priv->rx_queue[i]) {

667

err = -ENOMEM;

667

err = -ENOMEM;

668

goto rx_alloc_failed;

668

goto rx_alloc_failed;

669

}

669

}

670

priv->rx_queue[i]->rx_skbuff = NULL;

670

priv->rx_queue[i]->rx_skbuff = NULL;

671

priv->rx_queue[i]->qindex = i;

671

priv->rx_queue[i]->qindex = i;

672

priv->rx_queue[i]->dev = dev;

672

priv->rx_queue[i]->dev = dev;

673

spin_lock_init(&(priv->rx_queue[i]->rxlock));

673

spin_lock_init(&(priv->rx_queue[i]->rxlock));

674

}

674

}

675

676

677

stash = of_get_property(np, "bd-stash", NULL);

677

stash = of_get_property(np, "bd-stash", NULL);

678

679

if (stash) {

679

if (stash) {

680

priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;

680

priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;

681

priv->bd_stash_en = 1;

681

priv->bd_stash_en = 1;

682

}

682

}

683

684

stash_len = of_get_property(np, "rx-stash-len", NULL);

684

stash_len = of_get_property(np, "rx-stash-len", NULL);

685

686

if (stash_len)

686

if (stash_len)

687

priv->rx_stash_size = *stash_len;

687

priv->rx_stash_size = *stash_len;

688

689

stash_idx = of_get_property(np, "rx-stash-idx", NULL);

689

stash_idx = of_get_property(np, "rx-stash-idx", NULL);

690

691

if (stash_idx)

691

if (stash_idx)

692

priv->rx_stash_index = *stash_idx;

692

priv->rx_stash_index = *stash_idx;

693

694

if (stash_len || stash_idx)

694

if (stash_len || stash_idx)

695

priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;

695

priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;

696

697

mac_addr = of_get_mac_address(np);

697

mac_addr = of_get_mac_address(np);

698

if (mac_addr)

698

if (mac_addr)

699

memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);

699

memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);

700

701

if (model && !strcasecmp(model, "TSEC"))

701

if (model && !strcasecmp(model, "TSEC"))

702

priv->device_flags =

702

priv->device_flags =

703

FSL_GIANFAR_DEV_HAS_GIGABIT |

703

FSL_GIANFAR_DEV_HAS_GIGABIT |

704

FSL_GIANFAR_DEV_HAS_COALESCE |

704

FSL_GIANFAR_DEV_HAS_COALESCE |

705

FSL_GIANFAR_DEV_HAS_RMON |

705

FSL_GIANFAR_DEV_HAS_RMON |

706

FSL_GIANFAR_DEV_HAS_MULTI_INTR;

706

FSL_GIANFAR_DEV_HAS_MULTI_INTR;

707

if (model && !strcasecmp(model, "eTSEC"))

707

if (model && !strcasecmp(model, "eTSEC"))

708

priv->device_flags =

708

priv->device_flags =

709

FSL_GIANFAR_DEV_HAS_GIGABIT |

709

FSL_GIANFAR_DEV_HAS_GIGABIT |

710

FSL_GIANFAR_DEV_HAS_COALESCE |

710

FSL_GIANFAR_DEV_HAS_COALESCE |

711

FSL_GIANFAR_DEV_HAS_RMON |

711

FSL_GIANFAR_DEV_HAS_RMON |

712

FSL_GIANFAR_DEV_HAS_MULTI_INTR |

712

FSL_GIANFAR_DEV_HAS_MULTI_INTR |

713

FSL_GIANFAR_DEV_HAS_PADDING |

713

FSL_GIANFAR_DEV_HAS_PADDING |

714

FSL_GIANFAR_DEV_HAS_CSUM |

714

FSL_GIANFAR_DEV_HAS_CSUM |

715

FSL_GIANFAR_DEV_HAS_VLAN |

715

FSL_GIANFAR_DEV_HAS_VLAN |

716

FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |

716

FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |

717

FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;

717

FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;

718

719

ctype = of_get_property(np, "phy-connection-type", NULL);

719

ctype = of_get_property(np, "phy-connection-type", NULL);

720

721

/* We only care about rgmii-id. The rest are autodetected */

721

/* We only care about rgmii-id. The rest are autodetected */

722

if (ctype && !strcmp(ctype, "rgmii-id"))

722

if (ctype && !strcmp(ctype, "rgmii-id"))

723

priv->interface = PHY_INTERFACE_MODE_RGMII_ID;

723

priv->interface = PHY_INTERFACE_MODE_RGMII_ID;

724

else

724

else

725

priv->interface = PHY_INTERFACE_MODE_MII;

725

priv->interface = PHY_INTERFACE_MODE_MII;

726

727

if (of_get_property(np, "fsl,magic-packet", NULL))

727

if (of_get_property(np, "fsl,magic-packet", NULL))

728

priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;

728

priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;

729

730

priv->phy_node = of_parse_phandle(np, "phy-handle", 0);

730

priv->phy_node = of_parse_phandle(np, "phy-handle", 0);

731

732

/* Find the TBI PHY. If it's not there, we don't support SGMII */

732

/* Find the TBI PHY. If it's not there, we don't support SGMII */

733

priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);

733

priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);

734

735

return 0;

735

return 0;

736

737

rx_alloc_failed:

737

rx_alloc_failed:

738

free_rx_pointers(priv);

738

free_rx_pointers(priv);

739

tx_alloc_failed:

739

tx_alloc_failed:

740

free_tx_pointers(priv);

740

free_tx_pointers(priv);

741

err_grp_init:

741

err_grp_init:

742

unmap_group_regs(priv);

742

unmap_group_regs(priv);

743

free_netdev(dev);

743

free_netdev(dev);

744

return err;

744

return err;

745

}

745

}

746

747

/* Ioctl MII Interface */

747

/* Ioctl MII Interface */

748

static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)

748

static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)

749

{

749

{

750

struct gfar_private *priv = netdev_priv(dev);

750

struct gfar_private *priv = netdev_priv(dev);

751

752

if (!netif_running(dev))

752

if (!netif_running(dev))

753

return -EINVAL;

753

return -EINVAL;

754

755

if (!priv->phydev)

755

if (!priv->phydev)

756

return -ENODEV;

756

return -ENODEV;

757

758

return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);

758

return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);

759

}

759

}

760

761

static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)

761

static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)

762

{

762

{

763

unsigned int new_bit_map = 0x0;

763

unsigned int new_bit_map = 0x0;

764

int mask = 0x1 << (max_qs - 1), i;

764

int mask = 0x1 << (max_qs - 1), i;

765

for (i = 0; i < max_qs; i++) {

765

for (i = 0; i < max_qs; i++) {

766

if (bit_map & mask)

766

if (bit_map & mask)

767

new_bit_map = new_bit_map + (1 << i);

767

new_bit_map = new_bit_map + (1 << i);

768

mask = mask >> 0x1;

768

mask = mask >> 0x1;

769

}

769

}

770

return new_bit_map;

770

return new_bit_map;

771

}

771

}

772

773

static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,

773

static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,

774

u32 class)

774

u32 class)

775

{

775

{

776

u32 rqfpr = FPR_FILER_MASK;

776

u32 rqfpr = FPR_FILER_MASK;

777

u32 rqfcr = 0x0;

777

u32 rqfcr = 0x0;

778

779

rqfar--;

779

rqfar--;

780

rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;

780

rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;

781

ftp_rqfpr[rqfar] = rqfpr;

781

ftp_rqfpr[rqfar] = rqfpr;

782

ftp_rqfcr[rqfar] = rqfcr;

782

ftp_rqfcr[rqfar] = rqfcr;

783

gfar_write_filer(priv, rqfar, rqfcr, rqfpr);

783

gfar_write_filer(priv, rqfar, rqfcr, rqfpr);

784

785

rqfar--;

785

rqfar--;

786

rqfcr = RQFCR_CMP_NOMATCH;

786

rqfcr = RQFCR_CMP_NOMATCH;

787

ftp_rqfpr[rqfar] = rqfpr;

787

ftp_rqfpr[rqfar] = rqfpr;

788

ftp_rqfcr[rqfar] = rqfcr;

788

ftp_rqfcr[rqfar] = rqfcr;

789

gfar_write_filer(priv, rqfar, rqfcr, rqfpr);

789

gfar_write_filer(priv, rqfar, rqfcr, rqfpr);

790

791

rqfar--;

791

rqfar--;

792

rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;

792

rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;

793

rqfpr = class;

793

rqfpr = class;

794

ftp_rqfcr[rqfar] = rqfcr;

794

ftp_rqfcr[rqfar] = rqfcr;

795

ftp_rqfpr[rqfar] = rqfpr;

795

ftp_rqfpr[rqfar] = rqfpr;

796

gfar_write_filer(priv, rqfar, rqfcr, rqfpr);

796

gfar_write_filer(priv, rqfar, rqfcr, rqfpr);

797

798

rqfar--;

798

rqfar--;

799

rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;

799

rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;

800

rqfpr = class;

800

rqfpr = class;

801

ftp_rqfcr[rqfar] = rqfcr;

801

ftp_rqfcr[rqfar] = rqfcr;

802

ftp_rqfpr[rqfar] = rqfpr;

802

ftp_rqfpr[rqfar] = rqfpr;

803

gfar_write_filer(priv, rqfar, rqfcr, rqfpr);

803

gfar_write_filer(priv, rqfar, rqfcr, rqfpr);

804

805

return rqfar;

805

return rqfar;

806

}

806

}

807

808

static void gfar_init_filer_table(struct gfar_private *priv)

808

static void gfar_init_filer_table(struct gfar_private *priv)

809

{

809

{

810

int i = 0x0;

810

int i = 0x0;

811

u32 rqfar = MAX_FILER_IDX;

811

u32 rqfar = MAX_FILER_IDX;

812

u32 rqfcr = 0x0;

812

u32 rqfcr = 0x0;

813

u32 rqfpr = FPR_FILER_MASK;

813

u32 rqfpr = FPR_FILER_MASK;

814

815

/* Default rule */

815

/* Default rule */

816

rqfcr = RQFCR_CMP_MATCH;

816

rqfcr = RQFCR_CMP_MATCH;

817

ftp_rqfcr[rqfar] = rqfcr;

817

ftp_rqfcr[rqfar] = rqfcr;

818

ftp_rqfpr[rqfar] = rqfpr;

818

ftp_rqfpr[rqfar] = rqfpr;

819

gfar_write_filer(priv, rqfar, rqfcr, rqfpr);

819

gfar_write_filer(priv, rqfar, rqfcr, rqfpr);

820

821

rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);

821

rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);

822

rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);

822

rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);

823

rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);

823

rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);

824

rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);

824

rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);

825

rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);

825

rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);

826

rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);

826

rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);

827

828

/* cur_filer_idx indicated the fisrt non-masked rule */

828

/* cur_filer_idx indicated the fisrt non-masked rule */

829

priv->cur_filer_idx = rqfar;

829

priv->cur_filer_idx = rqfar;

830

831

/* Rest are masked rules */

831

/* Rest are masked rules */

832

rqfcr = RQFCR_CMP_NOMATCH;

832

rqfcr = RQFCR_CMP_NOMATCH;

833

for (i = 0; i < rqfar; i++) {

833

for (i = 0; i < rqfar; i++) {

834

ftp_rqfcr[i] = rqfcr;

834

ftp_rqfcr[i] = rqfcr;

835

ftp_rqfpr[i] = rqfpr;

835

ftp_rqfpr[i] = rqfpr;

836

gfar_write_filer(priv, i, rqfcr, rqfpr);

836

gfar_write_filer(priv, i, rqfcr, rqfpr);

837

}

837

}

838

}

838

}

839

840

/* Set up the ethernet device structure, private data,

840

/* Set up the ethernet device structure, private data,

841

* and anything else we need before we start */

841

* and anything else we need before we start */

842

static int gfar_probe(struct of_device *ofdev,

842

static int gfar_probe(struct of_device *ofdev,

843

const struct of_device_id *match)

843

const struct of_device_id *match)

844

{

844

{

845

u32 tempval;

845

u32 tempval;

846

struct net_device *dev = NULL;

846

struct net_device *dev = NULL;

847

struct gfar_private *priv = NULL;

847

struct gfar_private *priv = NULL;

848

struct gfar __iomem *regs = NULL;

848

struct gfar __iomem *regs = NULL;

849

int err = 0, i, grp_idx = 0;

849

int err = 0, i, grp_idx = 0;

850

int len_devname;

850

int len_devname;

851

u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;

851

u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;

852

u32 isrg = 0;

852

u32 isrg = 0;

853

u32 __iomem *baddr;

853

u32 __iomem *baddr;

854

855

err = gfar_of_init(ofdev, &dev);

855

err = gfar_of_init(ofdev, &dev);

856

857

if (err)

857

if (err)

858

return err;

858

return err;

859

860

priv = netdev_priv(dev);

860

priv = netdev_priv(dev);

861

priv->ndev = dev;

861

priv->ndev = dev;

862

priv->ofdev = ofdev;

862

priv->ofdev = ofdev;

863

priv->node = ofdev->node;

863

priv->node = ofdev->node;

864

SET_NETDEV_DEV(dev, &ofdev->dev);

864

SET_NETDEV_DEV(dev, &ofdev->dev);

865

866

spin_lock_init(&priv->bflock);

866

spin_lock_init(&priv->bflock);

867

INIT_WORK(&priv->reset_task, gfar_reset_task);

867

INIT_WORK(&priv->reset_task, gfar_reset_task);

868

869

dev_set_drvdata(&ofdev->dev, priv);

869

dev_set_drvdata(&ofdev->dev, priv);

870

regs = priv->gfargrp[0].regs;

870

regs = priv->gfargrp[0].regs;

871

872

/* Stop the DMA engine now, in case it was running before */

872

/* Stop the DMA engine now, in case it was running before */

873

/* (The firmware could have used it, and left it running). */

873

/* (The firmware could have used it, and left it running). */

874

gfar_halt(dev);

874

gfar_halt(dev);

875

876

/* Reset MAC layer */

876

/* Reset MAC layer */

877

gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);

877

gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);

878

879

/* We need to delay at least 3 TX clocks */

879

/* We need to delay at least 3 TX clocks */

880

udelay(2);

880

udelay(2);

881

882

tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);

882

tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);

883

gfar_write(&regs->maccfg1, tempval);

883

gfar_write(&regs->maccfg1, tempval);

884

885

/* Initialize MACCFG2. */

885

/* Initialize MACCFG2. */

886

gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);

886

gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);

887

888

/* Initialize ECNTRL */

888

/* Initialize ECNTRL */

889

gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);

889

gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);

890

891

/* Set the dev->base_addr to the gfar reg region */

891

/* Set the dev->base_addr to the gfar reg region */

892

dev->base_addr = (unsigned long) regs;

892

dev->base_addr = (unsigned long) regs;

893

894

SET_NETDEV_DEV(dev, &ofdev->dev);

894

SET_NETDEV_DEV(dev, &ofdev->dev);

895

896

/* Fill in the dev structure */

896

/* Fill in the dev structure */

897

dev->watchdog_timeo = TX_TIMEOUT;

897

dev->watchdog_timeo = TX_TIMEOUT;

898

dev->mtu = 1500;

898

dev->mtu = 1500;

899

dev->netdev_ops = &gfar_netdev_ops;

899

dev->netdev_ops = &gfar_netdev_ops;

900

dev->ethtool_ops = &gfar_ethtool_ops;

900

dev->ethtool_ops = &gfar_ethtool_ops;

901

902

/* Register for napi ...We are registering NAPI for each grp */

902

/* Register for napi ...We are registering NAPI for each grp */

903

for (i = 0; i < priv->num_grps; i++)

903

for (i = 0; i < priv->num_grps; i++)

904

netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);

904

netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);

905

906

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {

906

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {

907

priv->rx_csum_enable = 1;

907

priv->rx_csum_enable = 1;

908

dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;

908

dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;

909

} else

909

} else

910

priv->rx_csum_enable = 0;

910

priv->rx_csum_enable = 0;

911

912

priv->vlgrp = NULL;

912

priv->vlgrp = NULL;

913

914

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)

914

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)

915

dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;

915

dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;

916

917

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {

917

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {

918

priv->extended_hash = 1;

918

priv->extended_hash = 1;

919

priv->hash_width = 9;

919

priv->hash_width = 9;

920

921

priv->hash_regs[0] = &regs->igaddr0;

921

priv->hash_regs[0] = &regs->igaddr0;

922

priv->hash_regs[1] = &regs->igaddr1;

922

priv->hash_regs[1] = &regs->igaddr1;

923

priv->hash_regs[2] = &regs->igaddr2;

923

priv->hash_regs[2] = &regs->igaddr2;

924

priv->hash_regs[3] = &regs->igaddr3;

924

priv->hash_regs[3] = &regs->igaddr3;

925

priv->hash_regs[4] = &regs->igaddr4;

925

priv->hash_regs[4] = &regs->igaddr4;

926

priv->hash_regs[5] = &regs->igaddr5;

926

priv->hash_regs[5] = &regs->igaddr5;

927

priv->hash_regs[6] = &regs->igaddr6;

927

priv->hash_regs[6] = &regs->igaddr6;

928

priv->hash_regs[7] = &regs->igaddr7;

928

priv->hash_regs[7] = &regs->igaddr7;

929

priv->hash_regs[8] = &regs->gaddr0;

929

priv->hash_regs[8] = &regs->gaddr0;

930

priv->hash_regs[9] = &regs->gaddr1;

930

priv->hash_regs[9] = &regs->gaddr1;

931

priv->hash_regs[10] = &regs->gaddr2;

931

priv->hash_regs[10] = &regs->gaddr2;

932

priv->hash_regs[11] = &regs->gaddr3;

932

priv->hash_regs[11] = &regs->gaddr3;

933

priv->hash_regs[12] = &regs->gaddr4;

933

priv->hash_regs[12] = &regs->gaddr4;

934

priv->hash_regs[13] = &regs->gaddr5;

934

priv->hash_regs[13] = &regs->gaddr5;

935

priv->hash_regs[14] = &regs->gaddr6;

935

priv->hash_regs[14] = &regs->gaddr6;

936

priv->hash_regs[15] = &regs->gaddr7;

936

priv->hash_regs[15] = &regs->gaddr7;

937

938

} else {

938

} else {

939

priv->extended_hash = 0;

939

priv->extended_hash = 0;

940

priv->hash_width = 8;

940

priv->hash_width = 8;

941

942

priv->hash_regs[0] = &regs->gaddr0;

942

priv->hash_regs[0] = &regs->gaddr0;

943

priv->hash_regs[1] = &regs->gaddr1;

943

priv->hash_regs[1] = &regs->gaddr1;

944

priv->hash_regs[2] = &regs->gaddr2;

944

priv->hash_regs[2] = &regs->gaddr2;

945

priv->hash_regs[3] = &regs->gaddr3;

945

priv->hash_regs[3] = &regs->gaddr3;

946

priv->hash_regs[4] = &regs->gaddr4;

946

priv->hash_regs[4] = &regs->gaddr4;

947

priv->hash_regs[5] = &regs->gaddr5;

947

priv->hash_regs[5] = &regs->gaddr5;

948

priv->hash_regs[6] = &regs->gaddr6;

948

priv->hash_regs[6] = &regs->gaddr6;

949

priv->hash_regs[7] = &regs->gaddr7;

949

priv->hash_regs[7] = &regs->gaddr7;

950

}

950

}

951

952

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)

952

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)

953

priv->padding = DEFAULT_PADDING;

953

priv->padding = DEFAULT_PADDING;

954

else

954

else

955

priv->padding = 0;

955

priv->padding = 0;

956

957

if (dev->features & NETIF_F_IP_CSUM)

957

if (dev->features & NETIF_F_IP_CSUM)

958

dev->hard_header_len += GMAC_FCB_LEN;

958

dev->hard_header_len += GMAC_FCB_LEN;

959

960

/* Program the isrg regs only if number of grps > 1 */

960

/* Program the isrg regs only if number of grps > 1 */

961

if (priv->num_grps > 1) {

961

if (priv->num_grps > 1) {

962

baddr = &regs->isrg0;

962

baddr = &regs->isrg0;

963

for (i = 0; i < priv->num_grps; i++) {

963

for (i = 0; i < priv->num_grps; i++) {

964

isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);

964

isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);

965

isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);

965

isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);

966

gfar_write(baddr, isrg);

966

gfar_write(baddr, isrg);

967

baddr++;

967

baddr++;

968

isrg = 0x0;

968

isrg = 0x0;

969

}

969

}

970

}

970

}

971

972

/* Need to reverse the bit maps as bit_map's MSB is q0

972

/* Need to reverse the bit maps as bit_map's MSB is q0

973

* but, for_each_bit parses from right to left, which

973

* but, for_each_bit parses from right to left, which

974

* basically reverses the queue numbers */

974

* basically reverses the queue numbers */

975

for (i = 0; i< priv->num_grps; i++) {

975

for (i = 0; i< priv->num_grps; i++) {

976

priv->gfargrp[i].tx_bit_map = reverse_bitmap(

976

priv->gfargrp[i].tx_bit_map = reverse_bitmap(

977

priv->gfargrp[i].tx_bit_map, MAX_TX_QS);

977

priv->gfargrp[i].tx_bit_map, MAX_TX_QS);

978

priv->gfargrp[i].rx_bit_map = reverse_bitmap(

978

priv->gfargrp[i].rx_bit_map = reverse_bitmap(

979

priv->gfargrp[i].rx_bit_map, MAX_RX_QS);

979

priv->gfargrp[i].rx_bit_map, MAX_RX_QS);

980

}

980

}

981

982

/* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,

982

/* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,

983

* also assign queues to groups */

983

* also assign queues to groups */

984

for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {

984

for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {

985

priv->gfargrp[grp_idx].num_rx_queues = 0x0;

985

priv->gfargrp[grp_idx].num_rx_queues = 0x0;

986

for_each_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,

986

for_each_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,

987

priv->num_rx_queues) {

987

priv->num_rx_queues) {

988

priv->gfargrp[grp_idx].num_rx_queues++;

988

priv->gfargrp[grp_idx].num_rx_queues++;

989

priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];

989

priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];

990

rstat = rstat | (RSTAT_CLEAR_RHALT >> i);

990

rstat = rstat | (RSTAT_CLEAR_RHALT >> i);

991

rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);

991

rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);

992

}

992

}

993

priv->gfargrp[grp_idx].num_tx_queues = 0x0;

993

priv->gfargrp[grp_idx].num_tx_queues = 0x0;

994

for_each_bit (i, &priv->gfargrp[grp_idx].tx_bit_map,

994

for_each_bit (i, &priv->gfargrp[grp_idx].tx_bit_map,

995

priv->num_tx_queues) {

995

priv->num_tx_queues) {

996

priv->gfargrp[grp_idx].num_tx_queues++;

996

priv->gfargrp[grp_idx].num_tx_queues++;

997

priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];

997

priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];

998

tstat = tstat | (TSTAT_CLEAR_THALT >> i);

998

tstat = tstat | (TSTAT_CLEAR_THALT >> i);

999

tqueue = tqueue | (TQUEUE_EN0 >> i);

999

tqueue = tqueue | (TQUEUE_EN0 >> i);

1000

}

1000

}

1001

priv->gfargrp[grp_idx].rstat = rstat;

1001

priv->gfargrp[grp_idx].rstat = rstat;

1002

priv->gfargrp[grp_idx].tstat = tstat;

1002

priv->gfargrp[grp_idx].tstat = tstat;

1003

rstat = tstat =0;

1003

rstat = tstat =0;

1004

}

1004

}

1005

1006

gfar_write(&regs->rqueue, rqueue);

1006

gfar_write(&regs->rqueue, rqueue);

1007

gfar_write(&regs->tqueue, tqueue);

1007

gfar_write(&regs->tqueue, tqueue);

1008

1009

priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;

1009

priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;

1010

1011

/* Initializing some of the rx/tx queue level parameters */

1011

/* Initializing some of the rx/tx queue level parameters */

1012

for (i = 0; i < priv->num_tx_queues; i++) {

1012

for (i = 0; i < priv->num_tx_queues; i++) {

1013

priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;

1013

priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;

1014

priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;

1014

priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;

1015

priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;

1015

priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;

1016

priv->tx_queue[i]->txic = DEFAULT_TXIC;

1016

priv->tx_queue[i]->txic = DEFAULT_TXIC;

1017

}

1017

}

1018

1019

for (i = 0; i < priv->num_rx_queues; i++) {

1019

for (i = 0; i < priv->num_rx_queues; i++) {

1020

priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;

1020

priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;

1021

priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;

1021

priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;

1022

priv->rx_queue[i]->rxic = DEFAULT_RXIC;

1022

priv->rx_queue[i]->rxic = DEFAULT_RXIC;

1023

}

1023

}

1024

1025

/* Enable most messages by default */

1025

/* Enable most messages by default */

1026

priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;

1026

priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;

1027

1028

/* Carrier starts down, phylib will bring it up */

1028

/* Carrier starts down, phylib will bring it up */

1029

netif_carrier_off(dev);

1029

netif_carrier_off(dev);

1030

1031

err = register_netdev(dev);

1031

err = register_netdev(dev);

1032

1033

if (err) {

1033

if (err) {

1034

printk(KERN_ERR "%s: Cannot register net device, aborting.\n",

1034

printk(KERN_ERR "%s: Cannot register net device, aborting.\n",

1035

dev->name);

1035

dev->name);

1036

goto register_fail;

1036

goto register_fail;

1037

}

1037

}

1038

1039

device_init_wakeup(&dev->dev,

1039

device_init_wakeup(&dev->dev,

1040

priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);

1040

priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);

1041

1042

/* fill out IRQ number and name fields */

1042

/* fill out IRQ number and name fields */

1043

len_devname = strlen(dev->name);

1043

len_devname = strlen(dev->name);

1044

for (i = 0; i < priv->num_grps; i++) {

1044

for (i = 0; i < priv->num_grps; i++) {

1045

strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,

1045

strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,

1046

len_devname);

1046

len_devname);

1047

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {

1047

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {

1048

strncpy(&priv->gfargrp[i].int_name_tx[len_devname],

1048

strncpy(&priv->gfargrp[i].int_name_tx[len_devname],

1049

"_g", sizeof("_g"));

1049

"_g", sizeof("_g"));

1050

priv->gfargrp[i].int_name_tx[

1050

priv->gfargrp[i].int_name_tx[

1051

strlen(priv->gfargrp[i].int_name_tx)] = i+48;

1051

strlen(priv->gfargrp[i].int_name_tx)] = i+48;

1052

strncpy(&priv->gfargrp[i].int_name_tx[strlen(

1052

strncpy(&priv->gfargrp[i].int_name_tx[strlen(

1053

priv->gfargrp[i].int_name_tx)],

1053

priv->gfargrp[i].int_name_tx)],

1054

"_tx", sizeof("_tx") + 1);

1054

"_tx", sizeof("_tx") + 1);

1055

1056

strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,

1056

strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,

1057

len_devname);

1057

len_devname);

1058

strncpy(&priv->gfargrp[i].int_name_rx[len_devname],

1058

strncpy(&priv->gfargrp[i].int_name_rx[len_devname],

1059

"_g", sizeof("_g"));

1059

"_g", sizeof("_g"));

1060

priv->gfargrp[i].int_name_rx[

1060

priv->gfargrp[i].int_name_rx[

1061

strlen(priv->gfargrp[i].int_name_rx)] = i+48;

1061

strlen(priv->gfargrp[i].int_name_rx)] = i+48;

1062

strncpy(&priv->gfargrp[i].int_name_rx[strlen(

1062

strncpy(&priv->gfargrp[i].int_name_rx[strlen(

1063

priv->gfargrp[i].int_name_rx)],

1063

priv->gfargrp[i].int_name_rx)],

1064

"_rx", sizeof("_rx") + 1);

1064

"_rx", sizeof("_rx") + 1);

1065

1066

strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,

1066

strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,

1067

len_devname);

1067

len_devname);

1068

strncpy(&priv->gfargrp[i].int_name_er[len_devname],

1068

strncpy(&priv->gfargrp[i].int_name_er[len_devname],

1069

"_g", sizeof("_g"));

1069

"_g", sizeof("_g"));

1070

priv->gfargrp[i].int_name_er[strlen(

1070

priv->gfargrp[i].int_name_er[strlen(

1071

priv->gfargrp[i].int_name_er)] = i+48;

1071

priv->gfargrp[i].int_name_er)] = i+48;

1072

strncpy(&priv->gfargrp[i].int_name_er[strlen(\

1072

strncpy(&priv->gfargrp[i].int_name_er[strlen(\

1073

priv->gfargrp[i].int_name_er)],

1073

priv->gfargrp[i].int_name_er)],

1074

"_er", sizeof("_er") + 1);

1074

"_er", sizeof("_er") + 1);

1075

} else

1075

} else

1076

priv->gfargrp[i].int_name_tx[len_devname] = '\0';

1076

priv->gfargrp[i].int_name_tx[len_devname] = '\0';

1077

}

1077

}

1078

1079

/* Initialize the filer table */

1079

/* Initialize the filer table */

1080

gfar_init_filer_table(priv);

1080

gfar_init_filer_table(priv);

1081

1082

/* Create all the sysfs files */

1082

/* Create all the sysfs files */

1083

gfar_init_sysfs(dev);

1083

gfar_init_sysfs(dev);

1084

1085

/* Print out the device info */

1085

/* Print out the device info */

1086

printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);

1086

printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);

1087

1088

/* Even more device info helps when determining which kernel */

1088

/* Even more device info helps when determining which kernel */

1089

/* provided which set of benchmarks. */

1089

/* provided which set of benchmarks. */

1090

printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);

1090

printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);

1091

for (i = 0; i < priv->num_rx_queues; i++)

1091

for (i = 0; i < priv->num_rx_queues; i++)

1092

printk(KERN_INFO "%s: :RX BD ring size for Q[%d]: %d\n",

1092

printk(KERN_INFO "%s: :RX BD ring size for Q[%d]: %d\n",

1093

dev->name, i, priv->rx_queue[i]->rx_ring_size);

1093

dev->name, i, priv->rx_queue[i]->rx_ring_size);

1094

for(i = 0; i < priv->num_tx_queues; i++)

1094

for(i = 0; i < priv->num_tx_queues; i++)

1095

printk(KERN_INFO "%s:TX BD ring size for Q[%d]: %d\n",

1095

printk(KERN_INFO "%s:TX BD ring size for Q[%d]: %d\n",

1096

dev->name, i, priv->tx_queue[i]->tx_ring_size);

1096

dev->name, i, priv->tx_queue[i]->tx_ring_size);

1097

1098

return 0;

1098

return 0;

1099

1100

register_fail:

1100

register_fail:

1101

unmap_group_regs(priv);

1101

unmap_group_regs(priv);

1102

free_tx_pointers(priv);

1102

free_tx_pointers(priv);

1103

free_rx_pointers(priv);

1103

free_rx_pointers(priv);

1104

if (priv->phy_node)

1104

if (priv->phy_node)

1105

of_node_put(priv->phy_node);

1105

of_node_put(priv->phy_node);

1106

if (priv->tbi_node)

1106

if (priv->tbi_node)

1107

of_node_put(priv->tbi_node);

1107

of_node_put(priv->tbi_node);

1108

free_netdev(dev);

1108

free_netdev(dev);

1109

return err;

1109

return err;

1110

}

1110

}

1111

1112

static int gfar_remove(struct of_device *ofdev)

1112

static int gfar_remove(struct of_device *ofdev)

1113

{

1113

{

1114

struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);

1114

struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);

1115

1116

if (priv->phy_node)

1116

if (priv->phy_node)

1117

of_node_put(priv->phy_node);

1117

of_node_put(priv->phy_node);

1118

if (priv->tbi_node)

1118

if (priv->tbi_node)

1119

of_node_put(priv->tbi_node);

1119

of_node_put(priv->tbi_node);

1120

1121

dev_set_drvdata(&ofdev->dev, NULL);

1121

dev_set_drvdata(&ofdev->dev, NULL);

1122

1123

unregister_netdev(priv->ndev);

1123

unregister_netdev(priv->ndev);

1124

unmap_group_regs(priv);

1124

unmap_group_regs(priv);

1125

free_netdev(priv->ndev);

1125

free_netdev(priv->ndev);

1126

1127

return 0;

1127

return 0;

1128

}

1128

}

1129

1130

#ifdef CONFIG_PM

1130

#ifdef CONFIG_PM

1131

1132

static int gfar_suspend(struct device *dev)

1132

static int gfar_suspend(struct device *dev)

1133

{

1133

{

1134

struct gfar_private *priv = dev_get_drvdata(dev);

1134

struct gfar_private *priv = dev_get_drvdata(dev);

1135

struct net_device *ndev = priv->ndev;

1135

struct net_device *ndev = priv->ndev;

1136

struct gfar __iomem *regs = priv->gfargrp[0].regs;

1136

struct gfar __iomem *regs = priv->gfargrp[0].regs;

1137

unsigned long flags;

1137

unsigned long flags;

1138

u32 tempval;

1138

u32 tempval;

1139

1140

int magic_packet = priv->wol_en &&

1140

int magic_packet = priv->wol_en &&

1141

(priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);

1141

(priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);

1142

1143

netif_device_detach(ndev);

1143

netif_device_detach(ndev);

1144

1145

if (netif_running(ndev)) {

1145

if (netif_running(ndev)) {

1146

1147

local_irq_save(flags);

1147

local_irq_save(flags);

1148

lock_tx_qs(priv);

1148

lock_tx_qs(priv);

1149

lock_rx_qs(priv);

1149

lock_rx_qs(priv);

1150

1151

gfar_halt_nodisable(ndev);

1151

gfar_halt_nodisable(ndev);

1152

1153

/* Disable Tx, and Rx if wake-on-LAN is disabled. */

1153

/* Disable Tx, and Rx if wake-on-LAN is disabled. */

1154

tempval = gfar_read(&regs->maccfg1);

1154

tempval = gfar_read(&regs->maccfg1);

1155

1156

tempval &= ~MACCFG1_TX_EN;

1156

tempval &= ~MACCFG1_TX_EN;

1157

1158

if (!magic_packet)

1158

if (!magic_packet)

1159

tempval &= ~MACCFG1_RX_EN;

1159

tempval &= ~MACCFG1_RX_EN;

1160

1161

gfar_write(&regs->maccfg1, tempval);

1161

gfar_write(&regs->maccfg1, tempval);

1162

1163

unlock_rx_qs(priv);

1163

unlock_rx_qs(priv);

1164

unlock_tx_qs(priv);

1164

unlock_tx_qs(priv);

1165

local_irq_restore(flags);

1165

local_irq_restore(flags);

1166

1167

disable_napi(priv);

1167

disable_napi(priv);

1168

1169

if (magic_packet) {

1169

if (magic_packet) {

1170

/* Enable interrupt on Magic Packet */

1170

/* Enable interrupt on Magic Packet */

1171

gfar_write(&regs->imask, IMASK_MAG);

1171

gfar_write(&regs->imask, IMASK_MAG);

1172

1173

/* Enable Magic Packet mode */

1173

/* Enable Magic Packet mode */

1174

tempval = gfar_read(&regs->maccfg2);

1174

tempval = gfar_read(&regs->maccfg2);

1175

tempval |= MACCFG2_MPEN;

1175

tempval |= MACCFG2_MPEN;

1176

gfar_write(&regs->maccfg2, tempval);

1176

gfar_write(&regs->maccfg2, tempval);

1177

} else {

1177

} else {

1178

phy_stop(priv->phydev);

1178

phy_stop(priv->phydev);

1179

}

1179

}

1180

}

1180

}

1181

1182

return 0;

1182

return 0;

1183

}

1183

}

1184

1185

static int gfar_resume(struct device *dev)

1185

static int gfar_resume(struct device *dev)

1186

{

1186

{

1187

struct gfar_private *priv = dev_get_drvdata(dev);

1187

struct gfar_private *priv = dev_get_drvdata(dev);

1188

struct net_device *ndev = priv->ndev;

1188

struct net_device *ndev = priv->ndev;

1189

struct gfar __iomem *regs = priv->gfargrp[0].regs;

1189

struct gfar __iomem *regs = priv->gfargrp[0].regs;

1190

unsigned long flags;

1190

unsigned long flags;

1191

u32 tempval;

1191

u32 tempval;

1192

int magic_packet = priv->wol_en &&

1192

int magic_packet = priv->wol_en &&

1193

(priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);

1193

(priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);

1194

1195

if (!netif_running(ndev)) {

1195

if (!netif_running(ndev)) {

1196

netif_device_attach(ndev);

1196

netif_device_attach(ndev);

1197

return 0;

1197

return 0;

1198

}

1198

}

1199

1200

if (!magic_packet && priv->phydev)

1200

if (!magic_packet && priv->phydev)

1201

phy_start(priv->phydev);

1201

phy_start(priv->phydev);

1202

1203

/* Disable Magic Packet mode, in case something

1203

/* Disable Magic Packet mode, in case something

1204

* else woke us up.

1204

* else woke us up.

1205

*/

1205

*/

1206

local_irq_save(flags);

1206

local_irq_save(flags);

1207

lock_tx_qs(priv);

1207

lock_tx_qs(priv);

1208

lock_rx_qs(priv);

1208

lock_rx_qs(priv);

1209

1210

tempval = gfar_read(&regs->maccfg2);

1210

tempval = gfar_read(&regs->maccfg2);

1211

tempval &= ~MACCFG2_MPEN;

1211

tempval &= ~MACCFG2_MPEN;

1212

gfar_write(&regs->maccfg2, tempval);

1212

gfar_write(&regs->maccfg2, tempval);

1213

1214

gfar_start(ndev);

1214

gfar_start(ndev);

1215

1216

unlock_rx_qs(priv);

1216

unlock_rx_qs(priv);

1217

unlock_tx_qs(priv);

1217

unlock_tx_qs(priv);

1218

local_irq_restore(flags);

1218

local_irq_restore(flags);

1219

1220

netif_device_attach(ndev);

1220

netif_device_attach(ndev);

1221

1222

enable_napi(priv);

1222

enable_napi(priv);

1223

1224

return 0;

1224

return 0;

1225

}

1225

}

1226

1227

static int gfar_restore(struct device *dev)

1227

static int gfar_restore(struct device *dev)

1228

{

1228

{

1229

struct gfar_private *priv = dev_get_drvdata(dev);

1229

struct gfar_private *priv = dev_get_drvdata(dev);

1230

struct net_device *ndev = priv->ndev;

1230

struct net_device *ndev = priv->ndev;

1231

1232

if (!netif_running(ndev))

1232

if (!netif_running(ndev))

1233

return 0;

1233

return 0;

1234

1235

gfar_init_bds(ndev);

1235

gfar_init_bds(ndev);

1236

init_registers(ndev);

1236

init_registers(ndev);

1237

gfar_set_mac_address(ndev);

1237

gfar_set_mac_address(ndev);

1238

gfar_init_mac(ndev);

1238

gfar_init_mac(ndev);

1239

gfar_start(ndev);

1239

gfar_start(ndev);

1240

1241

priv->oldlink = 0;

1241

priv->oldlink = 0;

1242

priv->oldspeed = 0;

1242

priv->oldspeed = 0;

1243

priv->oldduplex = -1;

1243

priv->oldduplex = -1;

1244

1245

if (priv->phydev)

1245

if (priv->phydev)

1246

phy_start(priv->phydev);

1246

phy_start(priv->phydev);

1247

1248

netif_device_attach(ndev);

1248

netif_device_attach(ndev);

1249

enable_napi(priv);

1249

enable_napi(priv);

1250

1251

return 0;

1251

return 0;

1252

}

1252

}

1253

1254

static struct dev_pm_ops gfar_pm_ops = {

1254

static struct dev_pm_ops gfar_pm_ops = {

1255

.suspend = gfar_suspend,

1255

.suspend = gfar_suspend,

1256

.resume = gfar_resume,

1256

.resume = gfar_resume,

1257

.freeze = gfar_suspend,

1257

.freeze = gfar_suspend,

1258

.thaw = gfar_resume,

1258

.thaw = gfar_resume,

1259

.restore = gfar_restore,

1259

.restore = gfar_restore,

1260

};

1260

};

1261

1262

#define GFAR_PM_OPS (&gfar_pm_ops)

1262

#define GFAR_PM_OPS (&gfar_pm_ops)

1263

1264

static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)

1264

static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)

1265

{

1265

{

1266

return gfar_suspend(&ofdev->dev);

1266

return gfar_suspend(&ofdev->dev);

1267

}

1267

}

1268

1269

static int gfar_legacy_resume(struct of_device *ofdev)

1269

static int gfar_legacy_resume(struct of_device *ofdev)

1270

{

1270

{

1271

return gfar_resume(&ofdev->dev);

1271

return gfar_resume(&ofdev->dev);

1272

}

1272

}

1273

1274

#else

1274

#else

1275

1276

#define GFAR_PM_OPS NULL

1276

#define GFAR_PM_OPS NULL

1277

#define gfar_legacy_suspend NULL

1277

#define gfar_legacy_suspend NULL

1278

#define gfar_legacy_resume NULL

1278

#define gfar_legacy_resume NULL

1279

1280

#endif

1280

#endif

1281

1282

/* Reads the controller's registers to determine what interface

1282

/* Reads the controller's registers to determine what interface

1283

* connects it to the PHY.

1283

* connects it to the PHY.

1284

*/

1284

*/

1285

static phy_interface_t gfar_get_interface(struct net_device *dev)

1285

static phy_interface_t gfar_get_interface(struct net_device *dev)

1286

{

1286

{

1287

struct gfar_private *priv = netdev_priv(dev);

1287

struct gfar_private *priv = netdev_priv(dev);

1288

struct gfar __iomem *regs = priv->gfargrp[0].regs;

1288

struct gfar __iomem *regs = priv->gfargrp[0].regs;

1289

u32 ecntrl;

1289

u32 ecntrl;

1290

1291

ecntrl = gfar_read(&regs->ecntrl);

1291

ecntrl = gfar_read(&regs->ecntrl);

1292

1293

if (ecntrl & ECNTRL_SGMII_MODE)

1293

if (ecntrl & ECNTRL_SGMII_MODE)

1294

return PHY_INTERFACE_MODE_SGMII;

1294

return PHY_INTERFACE_MODE_SGMII;

1295

1296

if (ecntrl & ECNTRL_TBI_MODE) {

1296

if (ecntrl & ECNTRL_TBI_MODE) {

1297

if (ecntrl & ECNTRL_REDUCED_MODE)

1297

if (ecntrl & ECNTRL_REDUCED_MODE)

1298

return PHY_INTERFACE_MODE_RTBI;

1298

return PHY_INTERFACE_MODE_RTBI;

1299

else

1299

else

1300

return PHY_INTERFACE_MODE_TBI;

1300

return PHY_INTERFACE_MODE_TBI;

1301

}

1301

}

1302

1303

if (ecntrl & ECNTRL_REDUCED_MODE) {

1303

if (ecntrl & ECNTRL_REDUCED_MODE) {

1304

if (ecntrl & ECNTRL_REDUCED_MII_MODE)

1304

if (ecntrl & ECNTRL_REDUCED_MII_MODE)

1305

return PHY_INTERFACE_MODE_RMII;

1305

return PHY_INTERFACE_MODE_RMII;

1306

else {

1306

else {

1307

phy_interface_t interface = priv->interface;

1307

phy_interface_t interface = priv->interface;

1308

1309

/*

1309

/*

1310

* This isn't autodetected right now, so it must

1310

* This isn't autodetected right now, so it must

1311

* be set by the device tree or platform code.

1311

* be set by the device tree or platform code.

1312

*/

1312

*/

1313

if (interface == PHY_INTERFACE_MODE_RGMII_ID)

1313

if (interface == PHY_INTERFACE_MODE_RGMII_ID)

1314

return PHY_INTERFACE_MODE_RGMII_ID;

1314

return PHY_INTERFACE_MODE_RGMII_ID;

1315

1316

return PHY_INTERFACE_MODE_RGMII;

1316

return PHY_INTERFACE_MODE_RGMII;

1317

}

1317

}

1318

}

1318

}

1319

1320

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)

1320

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)

1321

return PHY_INTERFACE_MODE_GMII;

1321

return PHY_INTERFACE_MODE_GMII;

1322

1323

return PHY_INTERFACE_MODE_MII;

1323

return PHY_INTERFACE_MODE_MII;

1324

}

1324

}

1325

1326

1327

/* Initializes driver's PHY state, and attaches to the PHY.

1327

/* Initializes driver's PHY state, and attaches to the PHY.

1328

* Returns 0 on success.

1328

* Returns 0 on success.

1329

*/

1329

*/

1330

static int init_phy(struct net_device *dev)

1330

static int init_phy(struct net_device *dev)

1331

{

1331

{

1332

struct gfar_private *priv = netdev_priv(dev);

1332

struct gfar_private *priv = netdev_priv(dev);

1333

uint gigabit_support =

1333

uint gigabit_support =

1334

priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?

1334

priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?

1335

SUPPORTED_1000baseT_Full : 0;

1335

SUPPORTED_1000baseT_Full : 0;

1336

phy_interface_t interface;

1336

phy_interface_t interface;

1337

1338

priv->oldlink = 0;

1338

priv->oldlink = 0;

1339

priv->oldspeed = 0;

1339

priv->oldspeed = 0;

1340

priv->oldduplex = -1;

1340

priv->oldduplex = -1;

1341

1342

interface = gfar_get_interface(dev);

1342

interface = gfar_get_interface(dev);

1343

1344

priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,

1344

priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,

1345

interface);

1345

interface);

1346

if (!priv->phydev)

1346

if (!priv->phydev)

1347

priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,

1347

priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,

1348

interface);

1348

interface);

1349

if (!priv->phydev) {

1349

if (!priv->phydev) {

1350

dev_err(&dev->dev, "could not attach to PHY\n");

1350

dev_err(&dev->dev, "could not attach to PHY\n");

1351

return -ENODEV;

1351

return -ENODEV;

1352

}

1352

}

1353

1354

if (interface == PHY_INTERFACE_MODE_SGMII)

1354

if (interface == PHY_INTERFACE_MODE_SGMII)

1355

gfar_configure_serdes(dev);

1355

gfar_configure_serdes(dev);

1356

1357

/* Remove any features not supported by the controller */

1357

/* Remove any features not supported by the controller */

1358

priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);

1358

priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);

1359

priv->phydev->advertising = priv->phydev->supported;

1359

priv->phydev->advertising = priv->phydev->supported;

1360

1361

return 0;

1361

return 0;

1362

}

1362

}

1363

1364

/*

1364

/*

1365

* Initialize TBI PHY interface for communicating with the

1365

* Initialize TBI PHY interface for communicating with the

1366

* SERDES lynx PHY on the chip. We communicate with this PHY

1366

* SERDES lynx PHY on the chip. We communicate with this PHY

1367

* through the MDIO bus on each controller, treating it as a

1367

* through the MDIO bus on each controller, treating it as a

1368

* "normal" PHY at the address found in the TBIPA register. We assume

1368

* "normal" PHY at the address found in the TBIPA register. We assume

1369

* that the TBIPA register is valid. Either the MDIO bus code will set

1369

* that the TBIPA register is valid. Either the MDIO bus code will set

1370

* it to a value that doesn't conflict with other PHYs on the bus, or the

1370

* it to a value that doesn't conflict with other PHYs on the bus, or the

1371

* value doesn't matter, as there are no other PHYs on the bus.

1371

* value doesn't matter, as there are no other PHYs on the bus.

1372

*/

1372

*/

1373

static void gfar_configure_serdes(struct net_device *dev)

1373

static void gfar_configure_serdes(struct net_device *dev)

1374

{

1374

{

1375

struct gfar_private *priv = netdev_priv(dev);

1375

struct gfar_private *priv = netdev_priv(dev);

1376

struct phy_device *tbiphy;

1376

struct phy_device *tbiphy;

1377

1378

if (!priv->tbi_node) {

1378

if (!priv->tbi_node) {

1379

dev_warn(&dev->dev, "error: SGMII mode requires that the "

1379

dev_warn(&dev->dev, "error: SGMII mode requires that the "

1380

"device tree specify a tbi-handle\n");

1380

"device tree specify a tbi-handle\n");

1381

return;

1381

return;

1382

}

1382

}

1383

1384

tbiphy = of_phy_find_device(priv->tbi_node);

1384

tbiphy = of_phy_find_device(priv->tbi_node);

1385

if (!tbiphy) {

1385

if (!tbiphy) {

1386

dev_err(&dev->dev, "error: Could not get TBI device\n");

1386

dev_err(&dev->dev, "error: Could not get TBI device\n");

1387

return;

1387

return;

1388

}

1388

}

1389

1390

/*

1390

/*

1391

* If the link is already up, we must already be ok, and don't need to

1391

* If the link is already up, we must already be ok, and don't need to

1392

* configure and reset the TBI<->SerDes link. Maybe U-Boot configured

1392

* configure and reset the TBI<->SerDes link. Maybe U-Boot configured

1393

* everything for us? Resetting it takes the link down and requires

1393

* everything for us? Resetting it takes the link down and requires

1394

* several seconds for it to come back.

1394

* several seconds for it to come back.

1395

*/

1395

*/

1396

if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)

1396

if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)

1397

return;

1397

return;

1398

1399

/* Single clk mode, mii mode off(for serdes communication) */

1399

/* Single clk mode, mii mode off(for serdes communication) */

1400

phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);

1400

phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);

1401

1402

phy_write(tbiphy, MII_ADVERTISE,

1402

phy_write(tbiphy, MII_ADVERTISE,

1403

ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |

1403

ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |

1404

ADVERTISE_1000XPSE_ASYM);

1404

ADVERTISE_1000XPSE_ASYM);

1405

1406

phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |

1406

phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |

1407

BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);

1407

BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);

1408

}

1408

}

1409

1410

static void init_registers(struct net_device *dev)

1410

static void init_registers(struct net_device *dev)

1411

{

1411

{

1412

struct gfar_private *priv = netdev_priv(dev);

1412

struct gfar_private *priv = netdev_priv(dev);

1413

struct gfar __iomem *regs = NULL;

1413

struct gfar __iomem *regs = NULL;

1414

int i = 0;

1414

int i = 0;

1415

1416

for (i = 0; i < priv->num_grps; i++) {

1416

for (i = 0; i < priv->num_grps; i++) {

1417

regs = priv->gfargrp[i].regs;

1417

regs = priv->gfargrp[i].regs;

1418

/* Clear IEVENT */

1418

/* Clear IEVENT */

1419

gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);

1419

gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);

1420

1421

/* Initialize IMASK */

1421

/* Initialize IMASK */

1422

gfar_write(&regs->imask, IMASK_INIT_CLEAR);

1422

gfar_write(&regs->imask, IMASK_INIT_CLEAR);

1423

}

1423

}

1424

1425

regs = priv->gfargrp[0].regs;

1425

regs = priv->gfargrp[0].regs;

1426

/* Init hash registers to zero */

1426

/* Init hash registers to zero */

1427

gfar_write(&regs->igaddr0, 0);

1427

gfar_write(&regs->igaddr0, 0);

1428

gfar_write(&regs->igaddr1, 0);

1428

gfar_write(&regs->igaddr1, 0);

1429

gfar_write(&regs->igaddr2, 0);

1429

gfar_write(&regs->igaddr2, 0);

1430

gfar_write(&regs->igaddr3, 0);

1430

gfar_write(&regs->igaddr3, 0);

1431

gfar_write(&regs->igaddr4, 0);

1431

gfar_write(&regs->igaddr4, 0);

1432

gfar_write(&regs->igaddr5, 0);

1432

gfar_write(&regs->igaddr5, 0);

1433

gfar_write(&regs->igaddr6, 0);

1433

gfar_write(&regs->igaddr6, 0);

1434

gfar_write(&regs->igaddr7, 0);

1434

gfar_write(&regs->igaddr7, 0);

1435

1436

gfar_write(&regs->gaddr0, 0);

1436

gfar_write(&regs->gaddr0, 0);

1437

gfar_write(&regs->gaddr1, 0);

1437

gfar_write(&regs->gaddr1, 0);

1438

gfar_write(&regs->gaddr2, 0);

1438

gfar_write(&regs->gaddr2, 0);

1439

gfar_write(&regs->gaddr3, 0);

1439

gfar_write(&regs->gaddr3, 0);

1440

gfar_write(&regs->gaddr4, 0);

1440

gfar_write(&regs->gaddr4, 0);

1441

gfar_write(&regs->gaddr5, 0);

1441

gfar_write(&regs->gaddr5, 0);

1442

gfar_write(&regs->gaddr6, 0);

1442

gfar_write(&regs->gaddr6, 0);

1443

gfar_write(&regs->gaddr7, 0);

1443

gfar_write(&regs->gaddr7, 0);

1444

1445

/* Zero out the rmon mib registers if it has them */

1445

/* Zero out the rmon mib registers if it has them */

1446

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {

1446

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {

1447

memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));

1447

memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));

1448

1449

/* Mask off the CAM interrupts */

1449

/* Mask off the CAM interrupts */

1450

gfar_write(&regs->rmon.cam1, 0xffffffff);

1450

gfar_write(&regs->rmon.cam1, 0xffffffff);

1451

gfar_write(&regs->rmon.cam2, 0xffffffff);

1451

gfar_write(&regs->rmon.cam2, 0xffffffff);

1452

}

1452

}

1453

1454

/* Initialize the max receive buffer length */

1454

/* Initialize the max receive buffer length */

1455

gfar_write(&regs->mrblr, priv->rx_buffer_size);

1455

gfar_write(&regs->mrblr, priv->rx_buffer_size);

1456

1457

/* Initialize the Minimum Frame Length Register */

1457

/* Initialize the Minimum Frame Length Register */

1458

gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);

1458

gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);

1459

}

1459

}

1460

1461

1462

/* Halt the receive and transmit queues */

1462

/* Halt the receive and transmit queues */

1463

static void gfar_halt_nodisable(struct net_device *dev)

1463

static void gfar_halt_nodisable(struct net_device *dev)

1464

{

1464

{

1465

struct gfar_private *priv = netdev_priv(dev);

1465

struct gfar_private *priv = netdev_priv(dev);

1466

struct gfar __iomem *regs = NULL;

1466

struct gfar __iomem *regs = NULL;

1467

u32 tempval;

1467

u32 tempval;

1468

int i = 0;

1468

int i = 0;

1469

1470

for (i = 0; i < priv->num_grps; i++) {

1470

for (i = 0; i < priv->num_grps; i++) {

1471

regs = priv->gfargrp[i].regs;

1471

regs = priv->gfargrp[i].regs;

1472

/* Mask all interrupts */

1472

/* Mask all interrupts */

1473

gfar_write(&regs->imask, IMASK_INIT_CLEAR);

1473

gfar_write(&regs->imask, IMASK_INIT_CLEAR);

1474

1475

/* Clear all interrupts */

1475

/* Clear all interrupts */

1476

gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);

1476

gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);

1477

}

1477

}

1478

1479

regs = priv->gfargrp[0].regs;

1479

regs = priv->gfargrp[0].regs;

1480

/* Stop the DMA, and wait for it to stop */

1480

/* Stop the DMA, and wait for it to stop */

1481

tempval = gfar_read(&regs->dmactrl);

1481

tempval = gfar_read(&regs->dmactrl);

1482

if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))

1482

if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))

1483

!= (DMACTRL_GRS | DMACTRL_GTS)) {

1483

!= (DMACTRL_GRS | DMACTRL_GTS)) {

1484

tempval |= (DMACTRL_GRS | DMACTRL_GTS);

1484

tempval |= (DMACTRL_GRS | DMACTRL_GTS);

1485

gfar_write(&regs->dmactrl, tempval);

1485

gfar_write(&regs->dmactrl, tempval);

1486

1487

while (!(gfar_read(&regs->ievent) &

1487

while (!(gfar_read(&regs->ievent) &

1488

(IEVENT_GRSC | IEVENT_GTSC)))

1488

(IEVENT_GRSC | IEVENT_GTSC)))

1489

cpu_relax();

1489

cpu_relax();

1490

}

1490

}

1491

}

1491

}

1492

1493

/* Halt the receive and transmit queues */

1493

/* Halt the receive and transmit queues */

1494

void gfar_halt(struct net_device *dev)

1494

void gfar_halt(struct net_device *dev)

1495

{

1495

{

1496

struct gfar_private *priv = netdev_priv(dev);

1496

struct gfar_private *priv = netdev_priv(dev);

1497

struct gfar __iomem *regs = priv->gfargrp[0].regs;

1497

struct gfar __iomem *regs = priv->gfargrp[0].regs;

1498

u32 tempval;

1498

u32 tempval;

1499

1500

gfar_halt_nodisable(dev);

1500

gfar_halt_nodisable(dev);

1501

1502

/* Disable Rx and Tx */

1502

/* Disable Rx and Tx */

1503

tempval = gfar_read(&regs->maccfg1);

1503

tempval = gfar_read(&regs->maccfg1);

1504

tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);

1504

tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);

1505

gfar_write(&regs->maccfg1, tempval);

1505

gfar_write(&regs->maccfg1, tempval);

1506

}

1506

}

1507

1508

static void free_grp_irqs(struct gfar_priv_grp *grp)

1508

static void free_grp_irqs(struct gfar_priv_grp *grp)

1509

{

1509

{

1510

free_irq(grp->interruptError, grp);

1510

free_irq(grp->interruptError, grp);

1511

free_irq(grp->interruptTransmit, grp);

1511

free_irq(grp->interruptTransmit, grp);

1512

free_irq(grp->interruptReceive, grp);

1512

free_irq(grp->interruptReceive, grp);

1513

}

1513

}

1514

1515

void stop_gfar(struct net_device *dev)

1515

void stop_gfar(struct net_device *dev)

1516

{

1516

{

1517

struct gfar_private *priv = netdev_priv(dev);

1517

struct gfar_private *priv = netdev_priv(dev);

1518

unsigned long flags;

1518

unsigned long flags;

1519

int i;

1519

int i;

1520

1521

phy_stop(priv->phydev);

1521

phy_stop(priv->phydev);

1522

1523

1524

/* Lock it down */

1524

/* Lock it down */

1525

local_irq_save(flags);

1525

local_irq_save(flags);

1526

lock_tx_qs(priv);

1526

lock_tx_qs(priv);

1527

lock_rx_qs(priv);

1527

lock_rx_qs(priv);

1528

1529

gfar_halt(dev);

1529

gfar_halt(dev);

1530

1531

unlock_rx_qs(priv);

1531

unlock_rx_qs(priv);

1532

unlock_tx_qs(priv);

1532

unlock_tx_qs(priv);

1533

local_irq_restore(flags);

1533

local_irq_restore(flags);

1534

1535

/* Free the IRQs */

1535

/* Free the IRQs */

1536

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {

1536

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {

1537

for (i = 0; i < priv->num_grps; i++)

1537

for (i = 0; i < priv->num_grps; i++)

1538

free_grp_irqs(&priv->gfargrp[i]);

1538

free_grp_irqs(&priv->gfargrp[i]);

1539

} else {

1539

} else {

1540

for (i = 0; i < priv->num_grps; i++)

1540

for (i = 0; i < priv->num_grps; i++)

1541

free_irq(priv->gfargrp[i].interruptTransmit,

1541

free_irq(priv->gfargrp[i].interruptTransmit,

1542

&priv->gfargrp[i]);

1542

&priv->gfargrp[i]);

1543

}

1543

}

1544

1545

free_skb_resources(priv);

1545

free_skb_resources(priv);

1546

}

1546

}

1547

1548

static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)

1548

static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)

1549

{

1549

{

1550

struct txbd8 *txbdp;

1550

struct txbd8 *txbdp;

1551

struct gfar_private *priv = netdev_priv(tx_queue->dev);

1551

struct gfar_private *priv = netdev_priv(tx_queue->dev);

1552

int i, j;

1552

int i, j;

1553

1554

txbdp = tx_queue->tx_bd_base;

1554

txbdp = tx_queue->tx_bd_base;

1555

1556

for (i = 0; i < tx_queue->tx_ring_size; i++) {

1556

for (i = 0; i < tx_queue->tx_ring_size; i++) {

1557

if (!tx_queue->tx_skbuff[i])

1557

if (!tx_queue->tx_skbuff[i])

1558

continue;

1558

continue;

1559

1560

dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,

1560

dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,

1561

txbdp->length, DMA_TO_DEVICE);

1561

txbdp->length, DMA_TO_DEVICE);

1562

txbdp->lstatus = 0;

1562

txbdp->lstatus = 0;

1563

for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;

1563

for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;

1564

j++) {

1564

j++) {

1565

txbdp++;

1565

txbdp++;

1566

dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,

1566

dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,

1567

txbdp->length, DMA_TO_DEVICE);

1567

txbdp->length, DMA_TO_DEVICE);

1568

}

1568

}

1569

txbdp++;

1569

txbdp++;

1570

dev_kfree_skb_any(tx_queue->tx_skbuff[i]);

1570

dev_kfree_skb_any(tx_queue->tx_skbuff[i]);

1571

tx_queue->tx_skbuff[i] = NULL;

1571

tx_queue->tx_skbuff[i] = NULL;

1572

}

1572

}

1573

kfree(tx_queue->tx_skbuff);

1573

kfree(tx_queue->tx_skbuff);

1574

}

1574

}

1575

1576

static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)

1576

static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)

1577

{

1577

{

1578

struct rxbd8 *rxbdp;

1578

struct rxbd8 *rxbdp;

1579

struct gfar_private *priv = netdev_priv(rx_queue->dev);

1579

struct gfar_private *priv = netdev_priv(rx_queue->dev);

1580

int i;

1580

int i;

1581

1582

rxbdp = rx_queue->rx_bd_base;

1582

rxbdp = rx_queue->rx_bd_base;

1583

1584

for (i = 0; i < rx_queue->rx_ring_size; i++) {

1584

for (i = 0; i < rx_queue->rx_ring_size; i++) {

1585

if (rx_queue->rx_skbuff[i]) {

1585

if (rx_queue->rx_skbuff[i]) {

1586

dma_unmap_single(&priv->ofdev->dev,

1586

dma_unmap_single(&priv->ofdev->dev,

1587

rxbdp->bufPtr, priv->rx_buffer_size,

1587

rxbdp->bufPtr, priv->rx_buffer_size,

1588

DMA_FROM_DEVICE);

1588

DMA_FROM_DEVICE);

1589

dev_kfree_skb_any(rx_queue->rx_skbuff[i]);

1589

dev_kfree_skb_any(rx_queue->rx_skbuff[i]);

1590

rx_queue->rx_skbuff[i] = NULL;

1590

rx_queue->rx_skbuff[i] = NULL;

1591

}

1591

}

1592

rxbdp->lstatus = 0;

1592

rxbdp->lstatus = 0;

1593

rxbdp->bufPtr = 0;

1593

rxbdp->bufPtr = 0;

1594

rxbdp++;

1594

rxbdp++;

1595

}

1595

}

1596

kfree(rx_queue->rx_skbuff);

1596

kfree(rx_queue->rx_skbuff);

1597

}

1597

}

1598

1599

/* If there are any tx skbs or rx skbs still around, free them.

1599

/* If there are any tx skbs or rx skbs still around, free them.

1600

* Then free tx_skbuff and rx_skbuff */

1600

* Then free tx_skbuff and rx_skbuff */

1601

static void free_skb_resources(struct gfar_private *priv)

1601

static void free_skb_resources(struct gfar_private *priv)

1602

{

1602

{

1603

struct gfar_priv_tx_q *tx_queue = NULL;

1603

struct gfar_priv_tx_q *tx_queue = NULL;

1604

struct gfar_priv_rx_q *rx_queue = NULL;

1604

struct gfar_priv_rx_q *rx_queue = NULL;

1605

int i;

1605

int i;

1606

1607

/* Go through all the buffer descriptors and free their data buffers */

1607

/* Go through all the buffer descriptors and free their data buffers */

1608

for (i = 0; i < priv->num_tx_queues; i++) {

1608

for (i = 0; i < priv->num_tx_queues; i++) {

1609

tx_queue = priv->tx_queue[i];

1609

tx_queue = priv->tx_queue[i];

1610

if(!tx_queue->tx_skbuff)

1610

if(!tx_queue->tx_skbuff)

1611

free_skb_tx_queue(tx_queue);

1611

free_skb_tx_queue(tx_queue);

1612

}

1612

}

1613

1614

for (i = 0; i < priv->num_rx_queues; i++) {

1614

for (i = 0; i < priv->num_rx_queues; i++) {

1615

rx_queue = priv->rx_queue[i];

1615

rx_queue = priv->rx_queue[i];

1616

if(!rx_queue->rx_skbuff)

1616

if(!rx_queue->rx_skbuff)

1617

free_skb_rx_queue(rx_queue);

1617

free_skb_rx_queue(rx_queue);

1618

}

1618

}

1619

1620

dma_free_coherent(&priv->ofdev->dev,

1620

dma_free_coherent(&priv->ofdev->dev,

1621

sizeof(struct txbd8) * priv->total_tx_ring_size +

1621

sizeof(struct txbd8) * priv->total_tx_ring_size +

1622

sizeof(struct rxbd8) * priv->total_rx_ring_size,

1622

sizeof(struct rxbd8) * priv->total_rx_ring_size,

1623

priv->tx_queue[0]->tx_bd_base,

1623

priv->tx_queue[0]->tx_bd_base,

1624

priv->tx_queue[0]->tx_bd_dma_base);

1624

priv->tx_queue[0]->tx_bd_dma_base);

1625

}

1625

}

1626

1627

void gfar_start(struct net_device *dev)

1627

void gfar_start(struct net_device *dev)

1628

{

1628

{

1629

struct gfar_private *priv = netdev_priv(dev);

1629

struct gfar_private *priv = netdev_priv(dev);

1630

struct gfar __iomem *regs = priv->gfargrp[0].regs;

1630

struct gfar __iomem *regs = priv->gfargrp[0].regs;

1631

u32 tempval;

1631

u32 tempval;

1632

int i = 0;

1632

int i = 0;

1633

1634

/* Enable Rx and Tx in MACCFG1 */

1634

/* Enable Rx and Tx in MACCFG1 */

1635

tempval = gfar_read(&regs->maccfg1);

1635

tempval = gfar_read(&regs->maccfg1);

1636

tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);

1636

tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);

1637

gfar_write(&regs->maccfg1, tempval);

1637

gfar_write(&regs->maccfg1, tempval);

1638

1639

/* Initialize DMACTRL to have WWR and WOP */

1639

/* Initialize DMACTRL to have WWR and WOP */

1640

tempval = gfar_read(&regs->dmactrl);

1640

tempval = gfar_read(&regs->dmactrl);

1641

tempval |= DMACTRL_INIT_SETTINGS;

1641

tempval |= DMACTRL_INIT_SETTINGS;

1642

gfar_write(&regs->dmactrl, tempval);

1642

gfar_write(&regs->dmactrl, tempval);

1643

1644

/* Make sure we aren't stopped */

1644

/* Make sure we aren't stopped */

1645

tempval = gfar_read(&regs->dmactrl);

1645

tempval = gfar_read(&regs->dmactrl);

1646

tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);

1646

tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);

1647

gfar_write(&regs->dmactrl, tempval);

1647

gfar_write(&regs->dmactrl, tempval);

1648

1649

for (i = 0; i < priv->num_grps; i++) {

1649

for (i = 0; i < priv->num_grps; i++) {

1650

regs = priv->gfargrp[i].regs;

1650

regs = priv->gfargrp[i].regs;

1651

/* Clear THLT/RHLT, so that the DMA starts polling now */

1651

/* Clear THLT/RHLT, so that the DMA starts polling now */

1652

gfar_write(&regs->tstat, priv->gfargrp[i].tstat);

1652

gfar_write(&regs->tstat, priv->gfargrp[i].tstat);

1653

gfar_write(&regs->rstat, priv->gfargrp[i].rstat);

1653

gfar_write(&regs->rstat, priv->gfargrp[i].rstat);

1654

/* Unmask the interrupts we look for */

1654

/* Unmask the interrupts we look for */

1655

gfar_write(&regs->imask, IMASK_DEFAULT);

1655

gfar_write(&regs->imask, IMASK_DEFAULT);

1656

}

1656

}

1657

1658

dev->trans_start = jiffies;

1658

dev->trans_start = jiffies;

1659

}

1659

}

1660

1661

void gfar_configure_coalescing(struct gfar_private *priv,

1661

void gfar_configure_coalescing(struct gfar_private *priv,

1662

unsigned long tx_mask, unsigned long rx_mask)

1662

unsigned long tx_mask, unsigned long rx_mask)

1663

{

1663

{

1664

struct gfar __iomem *regs = priv->gfargrp[0].regs;

1664

struct gfar __iomem *regs = priv->gfargrp[0].regs;

1665

u32 __iomem *baddr;

1665

u32 __iomem *baddr;

1666

int i = 0;

1666

int i = 0;

1667

1668

/* Backward compatible case ---- even if we enable

1668

/* Backward compatible case ---- even if we enable

1669

* multiple queues, there's only single reg to program

1669

* multiple queues, there's only single reg to program

1670

*/

1670

*/

1671

gfar_write(&regs->txic, 0);

1671

gfar_write(&regs->txic, 0);

1672

if(likely(priv->tx_queue[0]->txcoalescing))

1672

if(likely(priv->tx_queue[0]->txcoalescing))

1673

gfar_write(&regs->txic, priv->tx_queue[0]->txic);

1673

gfar_write(&regs->txic, priv->tx_queue[0]->txic);

1674

1675

gfar_write(&regs->rxic, 0);

1675

gfar_write(&regs->rxic, 0);

1676

if(unlikely(priv->rx_queue[0]->rxcoalescing))

1676

if(unlikely(priv->rx_queue[0]->rxcoalescing))

1677

gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);

1677

gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);

1678

1679

if (priv->mode == MQ_MG_MODE) {

1679

if (priv->mode == MQ_MG_MODE) {

1680

baddr = &regs->txic0;

1680

baddr = &regs->txic0;

1681

for_each_bit (i, &tx_mask, priv->num_tx_queues) {

1681

for_each_bit (i, &tx_mask, priv->num_tx_queues) {

1682

if (likely(priv->tx_queue[i]->txcoalescing)) {

1682

if (likely(priv->tx_queue[i]->txcoalescing)) {

1683

gfar_write(baddr + i, 0);

1683

gfar_write(baddr + i, 0);

1684

gfar_write(baddr + i, priv->tx_queue[i]->txic);

1684

gfar_write(baddr + i, priv->tx_queue[i]->txic);

1685

}

1685

}

1686

}

1686

}

1687

1688

baddr = &regs->rxic0;

1688

baddr = &regs->rxic0;

1689

for_each_bit (i, &rx_mask, priv->num_rx_queues) {

1689

for_each_bit (i, &rx_mask, priv->num_rx_queues) {

1690

if (likely(priv->rx_queue[i]->rxcoalescing)) {

1690

if (likely(priv->rx_queue[i]->rxcoalescing)) {

1691

gfar_write(baddr + i, 0);

1691

gfar_write(baddr + i, 0);

1692

gfar_write(baddr + i, priv->rx_queue[i]->rxic);

1692

gfar_write(baddr + i, priv->rx_queue[i]->rxic);

1693

}

1693

}

1694

}

1694

}

1695

}

1695

}

1696

}

1696

}

1697

1698

static int register_grp_irqs(struct gfar_priv_grp *grp)

1698

static int register_grp_irqs(struct gfar_priv_grp *grp)

1699

{

1699

{

1700

struct gfar_private *priv = grp->priv;

1700

struct gfar_private *priv = grp->priv;

1701

struct net_device *dev = priv->ndev;

1701

struct net_device *dev = priv->ndev;

1702

int err;

1702

int err;

1703

1704

/* If the device has multiple interrupts, register for

1704

/* If the device has multiple interrupts, register for

1705

* them. Otherwise, only register for the one */

1705

* them. Otherwise, only register for the one */

1706

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {

1706

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {

1707

/* Install our interrupt handlers for Error,

1707

/* Install our interrupt handlers for Error,

1708

* Transmit, and Receive */

1708

* Transmit, and Receive */

1709

if ((err = request_irq(grp->interruptError, gfar_error, 0,

1709

if ((err = request_irq(grp->interruptError, gfar_error, 0,

1710

grp->int_name_er,grp)) < 0) {

1710

grp->int_name_er,grp)) < 0) {

1711

if (netif_msg_intr(priv))

1711

if (netif_msg_intr(priv))

1712

printk(KERN_ERR "%s: Can't get IRQ %d\n",

1712

printk(KERN_ERR "%s: Can't get IRQ %d\n",

1713

dev->name, grp->interruptError);

1713

dev->name, grp->interruptError);

1714

1715

goto err_irq_fail;

1715

goto err_irq_fail;

1716

}

1716

}

1717

1718

if ((err = request_irq(grp->interruptTransmit, gfar_transmit,

1718

if ((err = request_irq(grp->interruptTransmit, gfar_transmit,

1719

0, grp->int_name_tx, grp)) < 0) {

1719

0, grp->int_name_tx, grp)) < 0) {

1720

if (netif_msg_intr(priv))

1720

if (netif_msg_intr(priv))

1721

printk(KERN_ERR "%s: Can't get IRQ %d\n",

1721

printk(KERN_ERR "%s: Can't get IRQ %d\n",

1722

dev->name, grp->interruptTransmit);

1722

dev->name, grp->interruptTransmit);

1723

goto tx_irq_fail;

1723

goto tx_irq_fail;

1724

}

1724

}

1725

1726

if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,

1726

if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,

1727

grp->int_name_rx, grp)) < 0) {

1727

grp->int_name_rx, grp)) < 0) {

1728

if (netif_msg_intr(priv))

1728

if (netif_msg_intr(priv))

1729

printk(KERN_ERR "%s: Can't get IRQ %d\n",

1729

printk(KERN_ERR "%s: Can't get IRQ %d\n",

1730

dev->name, grp->interruptReceive);

1730

dev->name, grp->interruptReceive);

1731

goto rx_irq_fail;

1731

goto rx_irq_fail;

1732

}

1732

}

1733

} else {

1733

} else {

1734

if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,

1734

if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,

1735

grp->int_name_tx, grp)) < 0) {

1735

grp->int_name_tx, grp)) < 0) {

1736

if (netif_msg_intr(priv))

1736

if (netif_msg_intr(priv))

1737

printk(KERN_ERR "%s: Can't get IRQ %d\n",

1737

printk(KERN_ERR "%s: Can't get IRQ %d\n",

1738

dev->name, grp->interruptTransmit);

1738

dev->name, grp->interruptTransmit);

1739

goto err_irq_fail;

1739

goto err_irq_fail;

1740

}

1740

}

1741

}

1741

}

1742

1743

return 0;

1743

return 0;

1744

1745

rx_irq_fail:

1745

rx_irq_fail:

1746

free_irq(grp->interruptTransmit, grp);

1746

free_irq(grp->interruptTransmit, grp);

1747

tx_irq_fail:

1747

tx_irq_fail:

1748

free_irq(grp->interruptError, grp);

1748

free_irq(grp->interruptError, grp);

1749

err_irq_fail:

1749

err_irq_fail:

1750

return err;

1750

return err;

1751

1752

}

1752

}

1753

1754

/* Bring the controller up and running */

1754

/* Bring the controller up and running */

1755

int startup_gfar(struct net_device *ndev)

1755

int startup_gfar(struct net_device *ndev)

1756

{

1756

{

1757

struct gfar_private *priv = netdev_priv(ndev);

1757

struct gfar_private *priv = netdev_priv(ndev);

1758

struct gfar __iomem *regs = NULL;

1758

struct gfar __iomem *regs = NULL;

1759

int err, i, j;

1759

int err, i, j;

1760

1761

for (i = 0; i < priv->num_grps; i++) {

1761

for (i = 0; i < priv->num_grps; i++) {

1762

regs= priv->gfargrp[i].regs;

1762

regs= priv->gfargrp[i].regs;

1763

gfar_write(&regs->imask, IMASK_INIT_CLEAR);

1763

gfar_write(&regs->imask, IMASK_INIT_CLEAR);

1764

}

1764

}

1765

1766

regs= priv->gfargrp[0].regs;

1766

regs= priv->gfargrp[0].regs;

1767

err = gfar_alloc_skb_resources(ndev);

1767

err = gfar_alloc_skb_resources(ndev);

1768

if (err)

1768

if (err)

1769

return err;

1769

return err;

1770

1771

gfar_init_mac(ndev);

1771

gfar_init_mac(ndev);

1772

1773

for (i = 0; i < priv->num_grps; i++) {

1773

for (i = 0; i < priv->num_grps; i++) {

1774

err = register_grp_irqs(&priv->gfargrp[i]);

1774

err = register_grp_irqs(&priv->gfargrp[i]);

1775

if (err) {

1775

if (err) {

1776

for (j = 0; j < i; j++)

1776

for (j = 0; j < i; j++)

1777

free_grp_irqs(&priv->gfargrp[j]);

1777

free_grp_irqs(&priv->gfargrp[j]);

1778

goto irq_fail;

1778

goto irq_fail;

1779

}

1779

}

1780

}

1780

}

1781

1782

/* Start the controller */

1782

/* Start the controller */

1783

gfar_start(ndev);

1783

gfar_start(ndev);

1784

1785

phy_start(priv->phydev);

1785

phy_start(priv->phydev);

1786

1787

gfar_configure_coalescing(priv, 0xFF, 0xFF);

1787

gfar_configure_coalescing(priv, 0xFF, 0xFF);

1788

1789

return 0;

1789

return 0;

1790

1791

irq_fail:

1791

irq_fail:

1792

free_skb_resources(priv);

1792

free_skb_resources(priv);

1793

return err;

1793

return err;

1794

}

1794

}

1795

1796

/* Called when something needs to use the ethernet device */

1796

/* Called when something needs to use the ethernet device */

1797

/* Returns 0 for success. */

1797

/* Returns 0 for success. */

1798

static int gfar_enet_open(struct net_device *dev)

1798

static int gfar_enet_open(struct net_device *dev)

1799

{

1799

{

1800

struct gfar_private *priv = netdev_priv(dev);

1800

struct gfar_private *priv = netdev_priv(dev);

1801

int err;

1801

int err;

1802

1803

enable_napi(priv);

1803

enable_napi(priv);

1804

1805

skb_queue_head_init(&priv->rx_recycle);

1805

skb_queue_head_init(&priv->rx_recycle);

1806

1807

/* Initialize a bunch of registers */

1807

/* Initialize a bunch of registers */

1808

init_registers(dev);

1808

init_registers(dev);

1809

1810

gfar_set_mac_address(dev);

1810

gfar_set_mac_address(dev);

1811

1812

err = init_phy(dev);

1812

err = init_phy(dev);

1813

1814

if (err) {

1814

if (err) {

1815

disable_napi(priv);

1815

disable_napi(priv);

1816

return err;

1816

return err;

1817

}

1817

}

1818

1819

err = startup_gfar(dev);

1819

err = startup_gfar(dev);

1820

if (err) {

1820

if (err) {

1821

disable_napi(priv);

1821

disable_napi(priv);

1822

return err;

1822

return err;

1823

}

1823

}

1824

1825

netif_tx_start_all_queues(dev);

1825

netif_tx_start_all_queues(dev);

1826

1827

device_set_wakeup_enable(&dev->dev, priv->wol_en);

1827

device_set_wakeup_enable(&dev->dev, priv->wol_en);

1828

1829

return err;

1829

return err;

1830

}

1830

}

1831

1832

static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)

1832

static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)

1833

{

1833

{

1834

struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);

1834

struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);

1835

1836

memset(fcb, 0, GMAC_FCB_LEN);

1836

memset(fcb, 0, GMAC_FCB_LEN);

1837

1838

return fcb;

1838

return fcb;

1839

}

1839

}

1840

1841

static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)

1841

static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)

1842

{

1842

{

1843

u8 flags = 0;

1843

u8 flags = 0;

1844

1845

/* If we're here, it's a IP packet with a TCP or UDP

1845

/* If we're here, it's a IP packet with a TCP or UDP

1846

* payload. We set it to checksum, using a pseudo-header

1846

* payload. We set it to checksum, using a pseudo-header

1847

* we provide

1847

* we provide

1848

*/

1848

*/

1849

flags = TXFCB_DEFAULT;

1849

flags = TXFCB_DEFAULT;

1850

1851

/* Tell the controller what the protocol is */

1851

/* Tell the controller what the protocol is */

1852

/* And provide the already calculated phcs */

1852

/* And provide the already calculated phcs */

1853

if (ip_hdr(skb)->protocol == IPPROTO_UDP) {

1853

if (ip_hdr(skb)->protocol == IPPROTO_UDP) {

1854

flags |= TXFCB_UDP;

1854

flags |= TXFCB_UDP;

1855

fcb->phcs = udp_hdr(skb)->check;

1855

fcb->phcs = udp_hdr(skb)->check;

1856

} else

1856

} else

1857

fcb->phcs = tcp_hdr(skb)->check;

1857

fcb->phcs = tcp_hdr(skb)->check;

1858

1859

/* l3os is the distance between the start of the

1859

/* l3os is the distance between the start of the

1860

* frame (skb->data) and the start of the IP hdr.

1860

* frame (skb->data) and the start of the IP hdr.

1861

* l4os is the distance between the start of the

1861

* l4os is the distance between the start of the

1862

* l3 hdr and the l4 hdr */

1862

* l3 hdr and the l4 hdr */

1863

fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);

1863

fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);

1864

fcb->l4os = skb_network_header_len(skb);

1864

fcb->l4os = skb_network_header_len(skb);

1865

1866

fcb->flags = flags;

1866

fcb->flags = flags;

1867

}

1867

}

1868

1869

void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)

1869

void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)

1870

{

1870

{

1871

fcb->flags |= TXFCB_VLN;

1871

fcb->flags |= TXFCB_VLN;

1872

fcb->vlctl = vlan_tx_tag_get(skb);

1872

fcb->vlctl = vlan_tx_tag_get(skb);

1873

}

1873

}

1874

1875

static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,

1875

static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,

1876

struct txbd8 *base, int ring_size)

1876

struct txbd8 *base, int ring_size)

1877

{

1877

{

1878

struct txbd8 *new_bd = bdp + stride;

1878

struct txbd8 *new_bd = bdp + stride;

1879

1880

return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;

1880

return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;

1881

}

1881

}

1882

1883

static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,

1883

static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,

1884

int ring_size)

1884

int ring_size)

1885

{

1885

{

1886

return skip_txbd(bdp, 1, base, ring_size);

1886

return skip_txbd(bdp, 1, base, ring_size);

1887

}

1887

}

1888

1889

/* This is called by the kernel when a frame is ready for transmission. */

1889

/* This is called by the kernel when a frame is ready for transmission. */

1890

/* It is pointed to by the dev->hard_start_xmit function pointer */

1890

/* It is pointed to by the dev->hard_start_xmit function pointer */

1891

static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)

1891

static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)

1892

{

1892

{

1893

struct gfar_private *priv = netdev_priv(dev);

1893

struct gfar_private *priv = netdev_priv(dev);

1894

struct gfar_priv_tx_q *tx_queue = NULL;

1894

struct gfar_priv_tx_q *tx_queue = NULL;

1895

struct netdev_queue *txq;

1895

struct netdev_queue *txq;

1896

struct gfar __iomem *regs = NULL;

1896

struct gfar __iomem *regs = NULL;

1897

struct txfcb *fcb = NULL;

1897

struct txfcb *fcb = NULL;

1898

struct txbd8 *txbdp, *txbdp_start, *base;

1898

struct txbd8 *txbdp, *txbdp_start, *base;

1899

u32 lstatus;

1899

u32 lstatus;

1900

int i, rq = 0;

1900

int i, rq = 0;

1901

u32 bufaddr;

1901

u32 bufaddr;

1902

unsigned long flags;

1902

unsigned long flags;

1903

unsigned int nr_frags, length;

1903

unsigned int nr_frags, length;

1904

1905

1906

rq = skb->queue_mapping;

1906

rq = skb->queue_mapping;

1907

tx_queue = priv->tx_queue[rq];

1907

tx_queue = priv->tx_queue[rq];

1908

txq = netdev_get_tx_queue(dev, rq);

1908

txq = netdev_get_tx_queue(dev, rq);

1909

base = tx_queue->tx_bd_base;

1909

base = tx_queue->tx_bd_base;

1910

regs = tx_queue->grp->regs;

1910

regs = tx_queue->grp->regs;

1911

1912

/* make space for additional header when fcb is needed */

1912

/* make space for additional header when fcb is needed */

1913

if (((skb->ip_summed == CHECKSUM_PARTIAL) ||

1913

if (((skb->ip_summed == CHECKSUM_PARTIAL) ||

1914

(priv->vlgrp && vlan_tx_tag_present(skb))) &&

1914

(priv->vlgrp && vlan_tx_tag_present(skb))) &&

1915

(skb_headroom(skb) < GMAC_FCB_LEN)) {

1915

(skb_headroom(skb) < GMAC_FCB_LEN)) {

1916

struct sk_buff *skb_new;

1916

struct sk_buff *skb_new;

1917

1918

skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);

1918

skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);

1919

if (!skb_new) {

1919

if (!skb_new) {

1920

dev->stats.tx_errors++;

1920

dev->stats.tx_errors++;

1921

kfree_skb(skb);

1921

kfree_skb(skb);

1922

return NETDEV_TX_OK;

1922

return NETDEV_TX_OK;

1923

}

1923

}

1924

kfree_skb(skb);

1924

kfree_skb(skb);

1925

skb = skb_new;

1925

skb = skb_new;

1926

}

1926

}

1927

1928

/* total number of fragments in the SKB */

1928

/* total number of fragments in the SKB */

1929

nr_frags = skb_shinfo(skb)->nr_frags;

1929

nr_frags = skb_shinfo(skb)->nr_frags;

1930

1931

spin_lock_irqsave(&tx_queue->txlock, flags);

1932

1933

/* check if there is space to queue this packet */

1931

/* check if there is space to queue this packet */

1934

if ((nr_frags+1) > tx_queue->num_txbdfree) {

1932

if ((nr_frags+1) > tx_queue->num_txbdfree) {

1935

/* no space, stop the queue */

1933

/* no space, stop the queue */

1936

netif_tx_stop_queue(txq);

1934

netif_tx_stop_queue(txq);

1937

dev->stats.tx_fifo_errors++;

1935

dev->stats.tx_fifo_errors++;

1938

spin_unlock_irqrestore(&tx_queue->txlock, flags);

1939

return NETDEV_TX_BUSY;

1936

return NETDEV_TX_BUSY;

1940

}

1937

}

1941

1938

1942

/* Update transmit stats */

1939

/* Update transmit stats */

1943

dev->stats.tx_bytes += skb->len;

1940

dev->stats.tx_bytes += skb->len;

1944

1941

1945

txbdp = txbdp_start = tx_queue->cur_tx;

1942

txbdp = txbdp_start = tx_queue->cur_tx;

1946

1943

1947

if (nr_frags == 0) {

1944

if (nr_frags == 0) {

1948

lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);

1945

lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);

1949

} else {

1946

} else {

1950

/* Place the fragment addresses and lengths into the TxBDs */

1947

/* Place the fragment addresses and lengths into the TxBDs */

1951

for (i = 0; i < nr_frags; i++) {

1948

for (i = 0; i < nr_frags; i++) {

1952

/* Point at the next BD, wrapping as needed */

1949

/* Point at the next BD, wrapping as needed */

1953

txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);

1950

txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);

1954

1951

1955

length = skb_shinfo(skb)->frags[i].size;

1952

length = skb_shinfo(skb)->frags[i].size;

1956

1953

1957

lstatus = txbdp->lstatus | length |

1954

lstatus = txbdp->lstatus | length |

1958

BD_LFLAG(TXBD_READY);

1955

BD_LFLAG(TXBD_READY);

1959

1956

1960

/* Handle the last BD specially */

1957

/* Handle the last BD specially */

1961

if (i == nr_frags - 1)

1958

if (i == nr_frags - 1)

1962

lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);

1959

lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);

1963

1960

1964

bufaddr = dma_map_page(&priv->ofdev->dev,

1961

bufaddr = dma_map_page(&priv->ofdev->dev,

1965

skb_shinfo(skb)->frags[i].page,

1962

skb_shinfo(skb)->frags[i].page,

1966

skb_shinfo(skb)->frags[i].page_offset,

1963

skb_shinfo(skb)->frags[i].page_offset,

1967

length,

1964

length,

1968

DMA_TO_DEVICE);

1965

DMA_TO_DEVICE);

1969

1966

1970

/* set the TxBD length and buffer pointer */

1967

/* set the TxBD length and buffer pointer */

1971

txbdp->bufPtr = bufaddr;

1968

txbdp->bufPtr = bufaddr;

1972

txbdp->lstatus = lstatus;

1969

txbdp->lstatus = lstatus;

1973

}

1970

}

1974

1971

1975

lstatus = txbdp_start->lstatus;

1972

lstatus = txbdp_start->lstatus;

1976

}

1973

}

1977

1974

1978

/* Set up checksumming */

1975

/* Set up checksumming */

1979

if (CHECKSUM_PARTIAL == skb->ip_summed) {

1976

if (CHECKSUM_PARTIAL == skb->ip_summed) {

1980

fcb = gfar_add_fcb(skb);

1977

fcb = gfar_add_fcb(skb);

1981

lstatus |= BD_LFLAG(TXBD_TOE);

1978

lstatus |= BD_LFLAG(TXBD_TOE);

1982

gfar_tx_checksum(skb, fcb);

1979

gfar_tx_checksum(skb, fcb);

1983

}

1980

}

1984

1981

1985

if (priv->vlgrp && vlan_tx_tag_present(skb)) {

1982

if (priv->vlgrp && vlan_tx_tag_present(skb)) {

1986

if (unlikely(NULL == fcb)) {

1983

if (unlikely(NULL == fcb)) {

1987

fcb = gfar_add_fcb(skb);

1984

fcb = gfar_add_fcb(skb);

1988

lstatus |= BD_LFLAG(TXBD_TOE);

1985

lstatus |= BD_LFLAG(TXBD_TOE);

1989

}

1986

}

1990

1987

1991

gfar_tx_vlan(skb, fcb);

1988

gfar_tx_vlan(skb, fcb);

1992

}

1989

}

1993

1990

1994

/* setup the TxBD length and buffer pointer for the first BD */

1991

/* setup the TxBD length and buffer pointer for the first BD */

1995

tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;

1992

tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;

1996

txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,

1993

txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,

1997

skb_headlen(skb), DMA_TO_DEVICE);

1994

skb_headlen(skb), DMA_TO_DEVICE);

1998

1995

1999

lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);

1996

lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);

2000

1997

2001

/*

1998

/*

1999

* We can work in parallel with gfar_clean_tx_ring(), except

2000

* when modifying num_txbdfree. Note that we didn't grab the lock

2001

* when we were reading the num_txbdfree and checking for available

2002

* space, that's because outside of this function it can only grow,

2003

* and once we've got needed space, it cannot suddenly disappear.

2004

*

2005

* The lock also protects us from gfar_error(), which can modify

2006

* regs->tstat and thus retrigger the transfers, which is why we

2007

* also must grab the lock before setting ready bit for the first

2008

* to be transmitted BD.

2009

*/

2010

spin_lock_irqsave(&tx_queue->txlock, flags);

2011

2012

/*

2002

* The powerpc-specific eieio() is used, as wmb() has too strong

2013

* The powerpc-specific eieio() is used, as wmb() has too strong

2003

* semantics (it requires synchronization between cacheable and

2014

* semantics (it requires synchronization between cacheable and

2004

* uncacheable mappings, which eieio doesn't provide and which we

2015

* uncacheable mappings, which eieio doesn't provide and which we

2005

* don't need), thus requiring a more expensive sync instruction. At

2016

* don't need), thus requiring a more expensive sync instruction. At

2006

* some point, the set of architecture-independent barrier functions

2017

* some point, the set of architecture-independent barrier functions

2007

* should be expanded to include weaker barriers.

2018

* should be expanded to include weaker barriers.

2008

*/

2019

*/

2009

eieio();

2020

eieio();

2010

2021

2011

txbdp_start->lstatus = lstatus;

2022

txbdp_start->lstatus = lstatus;

2012

2023

2013

/* Update the current skb pointer to the next entry we will use

2024

/* Update the current skb pointer to the next entry we will use

2014

* (wrapping if necessary) */

2025

* (wrapping if necessary) */

2015

tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &

2026

tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &

2016

TX_RING_MOD_MASK(tx_queue->tx_ring_size);

2027

TX_RING_MOD_MASK(tx_queue->tx_ring_size);

2017

2028

2018

tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);

2029

tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);

2019

2030

2020

/* reduce TxBD free count */

2031

/* reduce TxBD free count */

2021

tx_queue->num_txbdfree -= (nr_frags + 1);

2032

tx_queue->num_txbdfree -= (nr_frags + 1);

2022

2033

2023

dev->trans_start = jiffies;

2034

dev->trans_start = jiffies;

2024

2035

2025

/* If the next BD still needs to be cleaned up, then the bds

2036

/* If the next BD still needs to be cleaned up, then the bds

2026

are full. We need to tell the kernel to stop sending us stuff. */

2037

are full. We need to tell the kernel to stop sending us stuff. */

2027

if (!tx_queue->num_txbdfree) {

2038

if (!tx_queue->num_txbdfree) {

2028

netif_tx_stop_queue(txq);

2039

netif_tx_stop_queue(txq);

2029

2040

2030

dev->stats.tx_fifo_errors++;

2041

dev->stats.tx_fifo_errors++;

2031

}

2042

}

2032

2043

2033

/* Tell the DMA to go go go */

2044

/* Tell the DMA to go go go */

2034

gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);

2045

gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);

2035

2046

2036

/* Unlock priv */

2047

/* Unlock priv */

2037

spin_unlock_irqrestore(&tx_queue->txlock, flags);

2048

spin_unlock_irqrestore(&tx_queue->txlock, flags);

2038

2049

2039

return NETDEV_TX_OK;

2050

return NETDEV_TX_OK;

2040

}

2051

}

2041

2052

2042

/* Stops the kernel queue, and halts the controller */

2053

/* Stops the kernel queue, and halts the controller */

2043

static int gfar_close(struct net_device *dev)

2054

static int gfar_close(struct net_device *dev)

2044

{

2055

{

2045

struct gfar_private *priv = netdev_priv(dev);

2056

struct gfar_private *priv = netdev_priv(dev);

2046

2057

2047

disable_napi(priv);

2058

disable_napi(priv);

2048

2059

2049

skb_queue_purge(&priv->rx_recycle);

2060

skb_queue_purge(&priv->rx_recycle);

2050

cancel_work_sync(&priv->reset_task);

2061

cancel_work_sync(&priv->reset_task);

2051

stop_gfar(dev);

2062

stop_gfar(dev);

2052

2063

2053

/* Disconnect from the PHY */

2064

/* Disconnect from the PHY */

2054

phy_disconnect(priv->phydev);

2065

phy_disconnect(priv->phydev);

2055

priv->phydev = NULL;

2066

priv->phydev = NULL;

2056

2067

2057

netif_tx_stop_all_queues(dev);

2068

netif_tx_stop_all_queues(dev);

2058

2069

2059

return 0;

2070

return 0;

2060

}

2071

}

2061

2072

2062

/* Changes the mac address if the controller is not running. */

2073

/* Changes the mac address if the controller is not running. */

2063

static int gfar_set_mac_address(struct net_device *dev)

2074

static int gfar_set_mac_address(struct net_device *dev)

2064

{

2075

{

2065

gfar_set_mac_for_addr(dev, 0, dev->dev_addr);

2076

gfar_set_mac_for_addr(dev, 0, dev->dev_addr);

2066

2077

2067

return 0;

2078

return 0;

2068

}

2079

}

2069

2080

2070

2081

2071

/* Enables and disables VLAN insertion/extraction */

2082

/* Enables and disables VLAN insertion/extraction */

2072

static void gfar_vlan_rx_register(struct net_device *dev,

2083

static void gfar_vlan_rx_register(struct net_device *dev,

2073

struct vlan_group *grp)

2084

struct vlan_group *grp)

2074

{

2085

{

2075

struct gfar_private *priv = netdev_priv(dev);

2086

struct gfar_private *priv = netdev_priv(dev);

2076

struct gfar __iomem *regs = NULL;

2087

struct gfar __iomem *regs = NULL;

2077

unsigned long flags;

2088

unsigned long flags;

2078

u32 tempval;

2089

u32 tempval;

2079

2090

2080

regs = priv->gfargrp[0].regs;

2091

regs = priv->gfargrp[0].regs;

2081

local_irq_save(flags);

2092

local_irq_save(flags);

2082

lock_rx_qs(priv);

2093

lock_rx_qs(priv);

2083

2094

2084

priv->vlgrp = grp;

2095

priv->vlgrp = grp;

2085

2096

2086

if (grp) {

2097

if (grp) {

2087

/* Enable VLAN tag insertion */

2098

/* Enable VLAN tag insertion */

2088

tempval = gfar_read(&regs->tctrl);

2099

tempval = gfar_read(&regs->tctrl);

2089

tempval |= TCTRL_VLINS;

2100

tempval |= TCTRL_VLINS;

2090

2101

2091

gfar_write(&regs->tctrl, tempval);

2102

gfar_write(&regs->tctrl, tempval);

2092

2103

2093

/* Enable VLAN tag extraction */

2104

/* Enable VLAN tag extraction */

2094

tempval = gfar_read(&regs->rctrl);

2105

tempval = gfar_read(&regs->rctrl);

2095

tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);

2106

tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);

2096

gfar_write(&regs->rctrl, tempval);

2107

gfar_write(&regs->rctrl, tempval);

2097

} else {

2108

} else {

2098

/* Disable VLAN tag insertion */

2109

/* Disable VLAN tag insertion */

2099

tempval = gfar_read(&regs->tctrl);

2110

tempval = gfar_read(&regs->tctrl);

2100

tempval &= ~TCTRL_VLINS;

2111

tempval &= ~TCTRL_VLINS;

2101

gfar_write(&regs->tctrl, tempval);

2112

gfar_write(&regs->tctrl, tempval);

2102

2113

2103

/* Disable VLAN tag extraction */

2114

/* Disable VLAN tag extraction */

2104

tempval = gfar_read(&regs->rctrl);

2115

tempval = gfar_read(&regs->rctrl);

2105

tempval &= ~RCTRL_VLEX;

2116

tempval &= ~RCTRL_VLEX;

2106

/* If parse is no longer required, then disable parser */

2117

/* If parse is no longer required, then disable parser */

2107

if (tempval & RCTRL_REQ_PARSER)

2118

if (tempval & RCTRL_REQ_PARSER)

2108

tempval |= RCTRL_PRSDEP_INIT;

2119

tempval |= RCTRL_PRSDEP_INIT;

2109

else

2120

else

2110

tempval &= ~RCTRL_PRSDEP_INIT;

2121

tempval &= ~RCTRL_PRSDEP_INIT;

2111

gfar_write(&regs->rctrl, tempval);

2122

gfar_write(&regs->rctrl, tempval);

2112

}

2123

}

2113

2124

2114

gfar_change_mtu(dev, dev->mtu);

2125

gfar_change_mtu(dev, dev->mtu);

2115

2126

2116

unlock_rx_qs(priv);

2127

unlock_rx_qs(priv);

2117

local_irq_restore(flags);

2128

local_irq_restore(flags);

2118

}

2129

}

2119

2130

2120

static int gfar_change_mtu(struct net_device *dev, int new_mtu)

2131

static int gfar_change_mtu(struct net_device *dev, int new_mtu)

2121

{

2132

{

2122

int tempsize, tempval;

2133

int tempsize, tempval;

2123

struct gfar_private *priv = netdev_priv(dev);

2134

struct gfar_private *priv = netdev_priv(dev);

2124

struct gfar __iomem *regs = priv->gfargrp[0].regs;

2135

struct gfar __iomem *regs = priv->gfargrp[0].regs;

2125

int oldsize = priv->rx_buffer_size;

2136

int oldsize = priv->rx_buffer_size;

2126

int frame_size = new_mtu + ETH_HLEN;

2137

int frame_size = new_mtu + ETH_HLEN;

2127

2138

2128

if (priv->vlgrp)

2139

if (priv->vlgrp)

2129

frame_size += VLAN_HLEN;

2140

frame_size += VLAN_HLEN;

2130

2141

2131

if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {

2142

if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {

2132

if (netif_msg_drv(priv))

2143

if (netif_msg_drv(priv))

2133

printk(KERN_ERR "%s: Invalid MTU setting\n",

2144

printk(KERN_ERR "%s: Invalid MTU setting\n",

2134

dev->name);

2145

dev->name);

2135

return -EINVAL;

2146

return -EINVAL;

2136

}

2147

}

2137

2148

2138

if (gfar_uses_fcb(priv))

2149

if (gfar_uses_fcb(priv))

2139

frame_size += GMAC_FCB_LEN;

2150

frame_size += GMAC_FCB_LEN;

2140

2151

2141

frame_size += priv->padding;

2152

frame_size += priv->padding;

2142

2153

2143

tempsize =

2154

tempsize =

2144

(frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +

2155

(frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +

2145

INCREMENTAL_BUFFER_SIZE;

2156

INCREMENTAL_BUFFER_SIZE;

2146

2157

2147

/* Only stop and start the controller if it isn't already

2158

/* Only stop and start the controller if it isn't already

2148

* stopped, and we changed something */

2159

* stopped, and we changed something */

2149

if ((oldsize != tempsize) && (dev->flags & IFF_UP))

2160

if ((oldsize != tempsize) && (dev->flags & IFF_UP))

2150

stop_gfar(dev);

2161

stop_gfar(dev);

2151

2162

2152

priv->rx_buffer_size = tempsize;

2163

priv->rx_buffer_size = tempsize;

2153

2164

2154

dev->mtu = new_mtu;

2165

dev->mtu = new_mtu;

2155

2166

2156

gfar_write(&regs->mrblr, priv->rx_buffer_size);

2167

gfar_write(&regs->mrblr, priv->rx_buffer_size);

2157

gfar_write(&regs->maxfrm, priv->rx_buffer_size);

2168

gfar_write(&regs->maxfrm, priv->rx_buffer_size);

2158

2169

2159

/* If the mtu is larger than the max size for standard

2170

/* If the mtu is larger than the max size for standard

2160

* ethernet frames (ie, a jumbo frame), then set maccfg2

2171

* ethernet frames (ie, a jumbo frame), then set maccfg2

2161

* to allow huge frames, and to check the length */

2172

* to allow huge frames, and to check the length */

2162

tempval = gfar_read(&regs->maccfg2);

2173

tempval = gfar_read(&regs->maccfg2);

2163

2174

2164

if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)

2175

if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)

2165

tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);

2176

tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);

2166

else

2177

else

2167

tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);

2178

tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);

2168

2179

2169

gfar_write(&regs->maccfg2, tempval);

2180

gfar_write(&regs->maccfg2, tempval);

2170

2181

2171

if ((oldsize != tempsize) && (dev->flags & IFF_UP))

2182

if ((oldsize != tempsize) && (dev->flags & IFF_UP))

2172

startup_gfar(dev);

2183

startup_gfar(dev);

2173

2184

2174

return 0;

2185

return 0;

2175

}

2186

}

2176

2187

2177

/* gfar_reset_task gets scheduled when a packet has not been

2188

/* gfar_reset_task gets scheduled when a packet has not been

2178

* transmitted after a set amount of time.

2189

* transmitted after a set amount of time.

2179

* For now, assume that clearing out all the structures, and

2190

* For now, assume that clearing out all the structures, and

2180

* starting over will fix the problem.

2191

* starting over will fix the problem.

2181

*/

2192

*/

2182

static void gfar_reset_task(struct work_struct *work)

2193

static void gfar_reset_task(struct work_struct *work)

2183

{

2194

{

2184

struct gfar_private *priv = container_of(work, struct gfar_private,

2195

struct gfar_private *priv = container_of(work, struct gfar_private,

2185

reset_task);

2196

reset_task);

2186

struct net_device *dev = priv->ndev;

2197

struct net_device *dev = priv->ndev;

2187

2198

2188

if (dev->flags & IFF_UP) {

2199

if (dev->flags & IFF_UP) {

2189

netif_tx_stop_all_queues(dev);

2200

netif_tx_stop_all_queues(dev);

2190

stop_gfar(dev);

2201

stop_gfar(dev);

2191

startup_gfar(dev);

2202

startup_gfar(dev);

2192

netif_tx_start_all_queues(dev);

2203

netif_tx_start_all_queues(dev);

2193

}

2204

}

2194

2205

2195

netif_tx_schedule_all(dev);

2206

netif_tx_schedule_all(dev);

2196

}

2207

}

2197

2208

2198

static void gfar_timeout(struct net_device *dev)

2209

static void gfar_timeout(struct net_device *dev)

2199

{

2210

{

2200

struct gfar_private *priv = netdev_priv(dev);

2211

struct gfar_private *priv = netdev_priv(dev);

2201

2212

2202

dev->stats.tx_errors++;

2213

dev->stats.tx_errors++;

2203

schedule_work(&priv->reset_task);

2214

schedule_work(&priv->reset_task);

2204

}

2215

}

2205

2216

2206

/* Interrupt Handler for Transmit complete */

2217

/* Interrupt Handler for Transmit complete */

2207

static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)

2218

static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)

2208

{

2219

{

2209

struct net_device *dev = tx_queue->dev;

2220

struct net_device *dev = tx_queue->dev;

2210

struct gfar_private *priv = netdev_priv(dev);

2221

struct gfar_private *priv = netdev_priv(dev);

2211

struct gfar_priv_rx_q *rx_queue = NULL;

2222

struct gfar_priv_rx_q *rx_queue = NULL;

2212

struct txbd8 *bdp;

2223

struct txbd8 *bdp;

2213

struct txbd8 *lbdp = NULL;

2224

struct txbd8 *lbdp = NULL;

2214

struct txbd8 *base = tx_queue->tx_bd_base;

2225

struct txbd8 *base = tx_queue->tx_bd_base;

2215

struct sk_buff *skb;

2226

struct sk_buff *skb;

2216

int skb_dirtytx;

2227

int skb_dirtytx;

2217

int tx_ring_size = tx_queue->tx_ring_size;

2228

int tx_ring_size = tx_queue->tx_ring_size;

2218

int frags = 0;

2229

int frags = 0;

2219

int i;

2230

int i;

2220

int howmany = 0;

2231

int howmany = 0;

2221

u32 lstatus;

2232

u32 lstatus;

2222

2233

2223

rx_queue = priv->rx_queue[tx_queue->qindex];

2234

rx_queue = priv->rx_queue[tx_queue->qindex];

2224

bdp = tx_queue->dirty_tx;

2235

bdp = tx_queue->dirty_tx;

2225

skb_dirtytx = tx_queue->skb_dirtytx;

2236

skb_dirtytx = tx_queue->skb_dirtytx;

2226

2237

2227

while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {

2238

while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {

2239

unsigned long flags;

2240

2228

frags = skb_shinfo(skb)->nr_frags;

2241

frags = skb_shinfo(skb)->nr_frags;

2229

lbdp = skip_txbd(bdp, frags, base, tx_ring_size);

2242

lbdp = skip_txbd(bdp, frags, base, tx_ring_size);

2230

2243

2231

lstatus = lbdp->lstatus;

2244

lstatus = lbdp->lstatus;

2232

2245

2233

/* Only clean completed frames */

2246

/* Only clean completed frames */

2234

if ((lstatus & BD_LFLAG(TXBD_READY)) &&

2247

if ((lstatus & BD_LFLAG(TXBD_READY)) &&

2235

(lstatus & BD_LENGTH_MASK))

2248

(lstatus & BD_LENGTH_MASK))

2236

break;

2249

break;

2237

2250

2238

dma_unmap_single(&priv->ofdev->dev,

2251

dma_unmap_single(&priv->ofdev->dev,

2239

bdp->bufPtr,

2252

bdp->bufPtr,

2240

bdp->length,

2253

bdp->length,

2241

DMA_TO_DEVICE);

2254

DMA_TO_DEVICE);

2242

2255

2243

bdp->lstatus &= BD_LFLAG(TXBD_WRAP);

2256

bdp->lstatus &= BD_LFLAG(TXBD_WRAP);

2244

bdp = next_txbd(bdp, base, tx_ring_size);

2257

bdp = next_txbd(bdp, base, tx_ring_size);

2245

2258

2246

for (i = 0; i < frags; i++) {

2259

for (i = 0; i < frags; i++) {

2247

dma_unmap_page(&priv->ofdev->dev,

2260

dma_unmap_page(&priv->ofdev->dev,

2248

bdp->bufPtr,

2261

bdp->bufPtr,

2249

bdp->length,

2262

bdp->length,

2250

DMA_TO_DEVICE);

2263

DMA_TO_DEVICE);

2251

bdp->lstatus &= BD_LFLAG(TXBD_WRAP);

2264

bdp->lstatus &= BD_LFLAG(TXBD_WRAP);

2252

bdp = next_txbd(bdp, base, tx_ring_size);

2265

bdp = next_txbd(bdp, base, tx_ring_size);

2253

}

2266

}

2254

2267

2255

/*

2268

/*

2256

* If there's room in the queue (limit it to rx_buffer_size)

2269

* If there's room in the queue (limit it to rx_buffer_size)

2257

* we add this skb back into the pool, if it's the right size

2270

* we add this skb back into the pool, if it's the right size

2258

*/

2271

*/

2259

if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&

2272

if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&

2260

skb_recycle_check(skb, priv->rx_buffer_size +

2273

skb_recycle_check(skb, priv->rx_buffer_size +

2261

RXBUF_ALIGNMENT))

2274

RXBUF_ALIGNMENT))

2262

__skb_queue_head(&priv->rx_recycle, skb);

2275

__skb_queue_head(&priv->rx_recycle, skb);

2263

else

2276

else

2264

dev_kfree_skb_any(skb);

2277

dev_kfree_skb_any(skb);

2265

2278

2266

tx_queue->tx_skbuff[skb_dirtytx] = NULL;

2279

tx_queue->tx_skbuff[skb_dirtytx] = NULL;

2267

2280

2268

skb_dirtytx = (skb_dirtytx + 1) &

2281

skb_dirtytx = (skb_dirtytx + 1) &

2269

TX_RING_MOD_MASK(tx_ring_size);

2282

TX_RING_MOD_MASK(tx_ring_size);

2270

2283

2271

howmany++;

2284

howmany++;

2285

spin_lock_irqsave(&tx_queue->txlock, flags);

2272

tx_queue->num_txbdfree += frags + 1;

2286

tx_queue->num_txbdfree += frags + 1;

2287

spin_unlock_irqrestore(&tx_queue->txlock, flags);

2273

}

2288

}

2274

2289

2275

/* If we freed a buffer, we can restart transmission, if necessary */

2290

/* If we freed a buffer, we can restart transmission, if necessary */

2276

if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)

2291

if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)

2277

netif_wake_subqueue(dev, tx_queue->qindex);

2292

netif_wake_subqueue(dev, tx_queue->qindex);

2278

2293

2279

/* Update dirty indicators */

2294

/* Update dirty indicators */

2280

tx_queue->skb_dirtytx = skb_dirtytx;

2295

tx_queue->skb_dirtytx = skb_dirtytx;

2281

tx_queue->dirty_tx = bdp;

2296

tx_queue->dirty_tx = bdp;

2282

2297

2283

dev->stats.tx_packets += howmany;

2298

dev->stats.tx_packets += howmany;

2284

2299

2285

return howmany;

2300

return howmany;

2286

}

2301

}

2287

2302

2288

static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)

2303

static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)

2289

{

2304

{

2290

unsigned long flags;

2305

unsigned long flags;

2291

2306

2292

spin_lock_irqsave(&gfargrp->grplock, flags);

2307

spin_lock_irqsave(&gfargrp->grplock, flags);

2293

if (napi_schedule_prep(&gfargrp->napi)) {

2308

if (napi_schedule_prep(&gfargrp->napi)) {

2294

gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);

2309

gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);

2295

__napi_schedule(&gfargrp->napi);

2310

__napi_schedule(&gfargrp->napi);

2296

} else {

2311

} else {

2297

/*

2312

/*

2298

* Clear IEVENT, so interrupts aren't called again

2313

* Clear IEVENT, so interrupts aren't called again

2299

* because of the packets that have already arrived.

2314

* because of the packets that have already arrived.

2300

*/

2315

*/

2301

gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);

2316

gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);

2302

}

2317

}

2303

spin_unlock_irqrestore(&gfargrp->grplock, flags);

2318

spin_unlock_irqrestore(&gfargrp->grplock, flags);

2304

2319

2305

}

2320

}

2306

2321

2307

/* Interrupt Handler for Transmit complete */

2322

/* Interrupt Handler for Transmit complete */

2308

static irqreturn_t gfar_transmit(int irq, void *grp_id)

2323

static irqreturn_t gfar_transmit(int irq, void *grp_id)

2309

{

2324

{

2310

gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);

2325

gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);

2311

return IRQ_HANDLED;

2326

return IRQ_HANDLED;

2312

}

2327

}

2313

2328

2314

static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,

2329

static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,

2315

struct sk_buff *skb)

2330

struct sk_buff *skb)

2316

{

2331

{

2317

struct net_device *dev = rx_queue->dev;

2332

struct net_device *dev = rx_queue->dev;

2318

struct gfar_private *priv = netdev_priv(dev);

2333

struct gfar_private *priv = netdev_priv(dev);

2319

dma_addr_t buf;

2334

dma_addr_t buf;

2320

2335

2321

buf = dma_map_single(&priv->ofdev->dev, skb->data,

2336

buf = dma_map_single(&priv->ofdev->dev, skb->data,

2322

priv->rx_buffer_size, DMA_FROM_DEVICE);

2337

priv->rx_buffer_size, DMA_FROM_DEVICE);

2323

gfar_init_rxbdp(rx_queue, bdp, buf);

2338

gfar_init_rxbdp(rx_queue, bdp, buf);

2324

}

2339

}

2325

2340

2326

2341

2327

struct sk_buff * gfar_new_skb(struct net_device *dev)

2342

struct sk_buff * gfar_new_skb(struct net_device *dev)

2328

{

2343

{

2329

unsigned int alignamount;

2344

unsigned int alignamount;

2330

struct gfar_private *priv = netdev_priv(dev);

2345

struct gfar_private *priv = netdev_priv(dev);

2331

struct sk_buff *skb = NULL;

2346

struct sk_buff *skb = NULL;

2332

2347

2333

skb = __skb_dequeue(&priv->rx_recycle);

2348

skb = __skb_dequeue(&priv->rx_recycle);

2334

if (!skb)

2349

if (!skb)

2335

skb = netdev_alloc_skb(dev,

2350

skb = netdev_alloc_skb(dev,

2336

priv->rx_buffer_size + RXBUF_ALIGNMENT);

2351

priv->rx_buffer_size + RXBUF_ALIGNMENT);

2337

2352

2338

if (!skb)

2353

if (!skb)

2339

return NULL;

2354

return NULL;

2340

2355

2341

alignamount = RXBUF_ALIGNMENT -

2356

alignamount = RXBUF_ALIGNMENT -

2342

(((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));

2357

(((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));

2343

2358

2344

/* We need the data buffer to be aligned properly. We will reserve

2359

/* We need the data buffer to be aligned properly. We will reserve

2345

* as many bytes as needed to align the data properly

2360

* as many bytes as needed to align the data properly

2346

*/

2361

*/

2347

skb_reserve(skb, alignamount);

2362

skb_reserve(skb, alignamount);

2348

2363

2349

return skb;

2364

return skb;

2350

}

2365

}

2351

2366

2352

static inline void count_errors(unsigned short status, struct net_device *dev)

2367

static inline void count_errors(unsigned short status, struct net_device *dev)

2353

{

2368

{

2354

struct gfar_private *priv = netdev_priv(dev);

2369

struct gfar_private *priv = netdev_priv(dev);

2355

struct net_device_stats *stats = &dev->stats;

2370

struct net_device_stats *stats = &dev->stats;

2356

struct gfar_extra_stats *estats = &priv->extra_stats;

2371

struct gfar_extra_stats *estats = &priv->extra_stats;

2357

2372

2358

/* If the packet was truncated, none of the other errors

2373

/* If the packet was truncated, none of the other errors

2359

* matter */

2374

* matter */

2360

if (status & RXBD_TRUNCATED) {

2375

if (status & RXBD_TRUNCATED) {

2361

stats->rx_length_errors++;

2376

stats->rx_length_errors++;

2362

2377

2363

estats->rx_trunc++;

2378

estats->rx_trunc++;

2364

2379

2365

return;

2380

return;

2366

}

2381

}

2367

/* Count the errors, if there were any */

2382

/* Count the errors, if there were any */

2368

if (status & (RXBD_LARGE | RXBD_SHORT)) {

2383

if (status & (RXBD_LARGE | RXBD_SHORT)) {

2369

stats->rx_length_errors++;

2384

stats->rx_length_errors++;

2370

2385

2371

if (status & RXBD_LARGE)

2386

if (status & RXBD_LARGE)

2372

estats->rx_large++;

2387

estats->rx_large++;

2373

else

2388

else

2374

estats->rx_short++;

2389

estats->rx_short++;

2375

}

2390

}

2376

if (status & RXBD_NONOCTET) {

2391

if (status & RXBD_NONOCTET) {

2377

stats->rx_frame_errors++;

2392

stats->rx_frame_errors++;

2378

estats->rx_nonoctet++;

2393

estats->rx_nonoctet++;

2379

}

2394

}

2380

if (status & RXBD_CRCERR) {

2395

if (status & RXBD_CRCERR) {

2381

estats->rx_crcerr++;

2396

estats->rx_crcerr++;

2382

stats->rx_crc_errors++;

2397

stats->rx_crc_errors++;

2383

}

2398

}

2384

if (status & RXBD_OVERRUN) {

2399

if (status & RXBD_OVERRUN) {

2385

estats->rx_overrun++;

2400

estats->rx_overrun++;

2386

stats->rx_crc_errors++;

2401

stats->rx_crc_errors++;

2387

}

2402

}

2388

}

2403

}

2389

2404

2390

irqreturn_t gfar_receive(int irq, void *grp_id)

2405

irqreturn_t gfar_receive(int irq, void *grp_id)

2391

{

2406

{

2392

gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);

2407

gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);

2393

return IRQ_HANDLED;

2408

return IRQ_HANDLED;

2394

}

2409

}

2395

2410

2396

static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)

2411

static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)

2397

{

2412

{

2398

/* If valid headers were found, and valid sums

2413

/* If valid headers were found, and valid sums

2399

* were verified, then we tell the kernel that no

2414

* were verified, then we tell the kernel that no

2400

* checksumming is necessary. Otherwise, it is */

2415

* checksumming is necessary. Otherwise, it is */

2401

if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))

2416

if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))

2402

skb->ip_summed = CHECKSUM_UNNECESSARY;

2417

skb->ip_summed = CHECKSUM_UNNECESSARY;

2403

else

2418

else

2404

skb->ip_summed = CHECKSUM_NONE;

2419

skb->ip_summed = CHECKSUM_NONE;

2405

}

2420

}

2406

2421

2407

2422

2408

/* gfar_process_frame() -- handle one incoming packet if skb

2423

/* gfar_process_frame() -- handle one incoming packet if skb

2409

* isn't NULL. */

2424

* isn't NULL. */

2410

static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,

2425

static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,

2411

int amount_pull)

2426

int amount_pull)

2412

{

2427

{

2413

struct gfar_private *priv = netdev_priv(dev);

2428

struct gfar_private *priv = netdev_priv(dev);

2414

struct rxfcb *fcb = NULL;

2429

struct rxfcb *fcb = NULL;

2415

2430

2416

int ret;

2431

int ret;

2417

2432

2418

/* fcb is at the beginning if exists */

2433

/* fcb is at the beginning if exists */

2419

fcb = (struct rxfcb *)skb->data;

2434

fcb = (struct rxfcb *)skb->data;

2420

2435

2421

/* Remove the FCB from the skb */

2436

/* Remove the FCB from the skb */

2422

skb_set_queue_mapping(skb, fcb->rq);

2437

skb_set_queue_mapping(skb, fcb->rq);

2423

/* Remove the padded bytes, if there are any */

2438

/* Remove the padded bytes, if there are any */

2424

if (amount_pull)

2439

if (amount_pull)

2425

skb_pull(skb, amount_pull);

2440

skb_pull(skb, amount_pull);

2426

2441

2427

if (priv->rx_csum_enable)

2442

if (priv->rx_csum_enable)

2428

gfar_rx_checksum(skb, fcb);

2443

gfar_rx_checksum(skb, fcb);

2429

2444

2430

/* Tell the skb what kind of packet this is */

2445

/* Tell the skb what kind of packet this is */

2431

skb->protocol = eth_type_trans(skb, dev);

2446

skb->protocol = eth_type_trans(skb, dev);

2432

2447

2433

/* Send the packet up the stack */

2448

/* Send the packet up the stack */

2434

if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))

2449

if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))

2435

ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);

2450

ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);

2436

else

2451

else

2437

ret = netif_receive_skb(skb);

2452

ret = netif_receive_skb(skb);

2438

2453

2439

if (NET_RX_DROP == ret)

2454

if (NET_RX_DROP == ret)

2440

priv->extra_stats.kernel_dropped++;

2455

priv->extra_stats.kernel_dropped++;

2441

2456

2442

return 0;

2457

return 0;

2443

}

2458

}

2444

2459

2445

/* gfar_clean_rx_ring() -- Processes each frame in the rx ring

2460

/* gfar_clean_rx_ring() -- Processes each frame in the rx ring

2446

* until the budget/quota has been reached. Returns the number

2461

* until the budget/quota has been reached. Returns the number

2447

* of frames handled

2462

* of frames handled

2448

*/

2463

*/

2449

int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)

2464

int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)

2450

{

2465

{

2451

struct net_device *dev = rx_queue->dev;

2466

struct net_device *dev = rx_queue->dev;

2452

struct rxbd8 *bdp, *base;

2467

struct rxbd8 *bdp, *base;

2453

struct sk_buff *skb;

2468

struct sk_buff *skb;

2454

int pkt_len;

2469

int pkt_len;

2455

int amount_pull;

2470

int amount_pull;

2456

int howmany = 0;

2471

int howmany = 0;

2457

struct gfar_private *priv = netdev_priv(dev);

2472

struct gfar_private *priv = netdev_priv(dev);

2458

2473

2459

/* Get the first full descriptor */

2474

/* Get the first full descriptor */

2460

bdp = rx_queue->cur_rx;

2475

bdp = rx_queue->cur_rx;

2461

base = rx_queue->rx_bd_base;

2476

base = rx_queue->rx_bd_base;

2462

2477

2463

amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +

2478

amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +

2464

priv->padding;

2479

priv->padding;

2465

2480

2466

while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {

2481

while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {

2467

struct sk_buff *newskb;

2482

struct sk_buff *newskb;

2468

rmb();

2483

rmb();

2469

2484

2470

/* Add another skb for the future */

2485

/* Add another skb for the future */

2471

newskb = gfar_new_skb(dev);

2486

newskb = gfar_new_skb(dev);

2472

2487

2473

skb = rx_queue->rx_skbuff[rx_queue->skb_currx];

2488

skb = rx_queue->rx_skbuff[rx_queue->skb_currx];

2474

2489

2475

dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,

2490

dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,

2476

priv->rx_buffer_size, DMA_FROM_DEVICE);

2491

priv->rx_buffer_size, DMA_FROM_DEVICE);

2477

2492

2478

/* We drop the frame if we failed to allocate a new buffer */

2493

/* We drop the frame if we failed to allocate a new buffer */

2479

if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||

2494

if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||

2480

bdp->status & RXBD_ERR)) {

2495

bdp->status & RXBD_ERR)) {

2481

count_errors(bdp->status, dev);

2496

count_errors(bdp->status, dev);

2482

2497

2483

if (unlikely(!newskb))

2498

if (unlikely(!newskb))

2484

newskb = skb;

2499

newskb = skb;

2485

else if (skb) {

2500

else if (skb) {

2486

/*

2501

/*

2487

* We need to reset ->data to what it

2502

* We need to reset ->data to what it

2488

* was before gfar_new_skb() re-aligned

2503

* was before gfar_new_skb() re-aligned

2489

* it to an RXBUF_ALIGNMENT boundary

2504

* it to an RXBUF_ALIGNMENT boundary

2490

* before we put the skb back on the

2505

* before we put the skb back on the

2491

* recycle list.

2506

* recycle list.

2492

*/

2507

*/

2493

skb->data = skb->head + NET_SKB_PAD;

2508

skb->data = skb->head + NET_SKB_PAD;

2494

__skb_queue_head(&priv->rx_recycle, skb);

2509

__skb_queue_head(&priv->rx_recycle, skb);

2495

}

2510

}

2496

} else {

2511

} else {

2497

/* Increment the number of packets */

2512

/* Increment the number of packets */

2498

dev->stats.rx_packets++;

2513

dev->stats.rx_packets++;

2499

howmany++;

2514

howmany++;

2500

2515

2501

if (likely(skb)) {

2516

if (likely(skb)) {

2502

pkt_len = bdp->length - ETH_FCS_LEN;

2517

pkt_len = bdp->length - ETH_FCS_LEN;

2503

/* Remove the FCS from the packet length */

2518

/* Remove the FCS from the packet length */

2504

skb_put(skb, pkt_len);

2519

skb_put(skb, pkt_len);

2505

dev->stats.rx_bytes += pkt_len;

2520

dev->stats.rx_bytes += pkt_len;

2506

2521

2507

gfar_process_frame(dev, skb, amount_pull);

2522

gfar_process_frame(dev, skb, amount_pull);

2508

2523

2509

} else {

2524

} else {

2510

if (netif_msg_rx_err(priv))

2525

if (netif_msg_rx_err(priv))

2511

printk(KERN_WARNING

2526

printk(KERN_WARNING

2512

"%s: Missing skb!\n", dev->name);

2527

"%s: Missing skb!\n", dev->name);

2513

dev->stats.rx_dropped++;

2528

dev->stats.rx_dropped++;

2514

priv->extra_stats.rx_skbmissing++;

2529

priv->extra_stats.rx_skbmissing++;

2515

}

2530

}

2516

2531

2517

}

2532

}

2518

2533

2519

rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;

2534

rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;

2520

2535

2521

/* Setup the new bdp */

2536

/* Setup the new bdp */

2522

gfar_new_rxbdp(rx_queue, bdp, newskb);

2537

gfar_new_rxbdp(rx_queue, bdp, newskb);

2523

2538

2524

/* Update to the next pointer */

2539

/* Update to the next pointer */

2525

bdp = next_bd(bdp, base, rx_queue->rx_ring_size);

2540

bdp = next_bd(bdp, base, rx_queue->rx_ring_size);

2526

2541

2527

/* update to point at the next skb */

2542

/* update to point at the next skb */

2528

rx_queue->skb_currx =

2543

rx_queue->skb_currx =

2529

(rx_queue->skb_currx + 1) &

2544

(rx_queue->skb_currx + 1) &

2530

RX_RING_MOD_MASK(rx_queue->rx_ring_size);

2545

RX_RING_MOD_MASK(rx_queue->rx_ring_size);

2531

}

2546

}

2532

2547

2533

/* Update the current rxbd pointer to be the next one */

2548

/* Update the current rxbd pointer to be the next one */

2534

rx_queue->cur_rx = bdp;

2549

rx_queue->cur_rx = bdp;

2535

2550

2536

return howmany;

2551

return howmany;

2537

}

2552

}

2538

2553

2539

static int gfar_poll(struct napi_struct *napi, int budget)

2554

static int gfar_poll(struct napi_struct *napi, int budget)

2540

{

2555

{

2541

struct gfar_priv_grp *gfargrp = container_of(napi,

2556

struct gfar_priv_grp *gfargrp = container_of(napi,

2542

struct gfar_priv_grp, napi);

2557

struct gfar_priv_grp, napi);

2543

struct gfar_private *priv = gfargrp->priv;

2558

struct gfar_private *priv = gfargrp->priv;

2544

struct gfar __iomem *regs = gfargrp->regs;

2559

struct gfar __iomem *regs = gfargrp->regs;

2545

struct gfar_priv_tx_q *tx_queue = NULL;

2560

struct gfar_priv_tx_q *tx_queue = NULL;

2546

struct gfar_priv_rx_q *rx_queue = NULL;

2561

struct gfar_priv_rx_q *rx_queue = NULL;

2547

int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;

2562

int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;

2548

int tx_cleaned = 0, i, left_over_budget = budget;

2563

int tx_cleaned = 0, i, left_over_budget = budget;

2549

unsigned long serviced_queues = 0;

2564

unsigned long serviced_queues = 0;

2550

int num_queues = 0;

2565

int num_queues = 0;

2551

unsigned long flags;

2552

2566

2553

num_queues = gfargrp->num_rx_queues;

2567

num_queues = gfargrp->num_rx_queues;

2554

budget_per_queue = budget/num_queues;

2568

budget_per_queue = budget/num_queues;

2555

2569

2556

/* Clear IEVENT, so interrupts aren't called again

2570

/* Clear IEVENT, so interrupts aren't called again

2557

* because of the packets that have already arrived */

2571

* because of the packets that have already arrived */

2558

gfar_write(&regs->ievent, IEVENT_RTX_MASK);

2572

gfar_write(&regs->ievent, IEVENT_RTX_MASK);

2559

2573

2560

while (num_queues && left_over_budget) {

2574

while (num_queues && left_over_budget) {

2561

2575

2562

budget_per_queue = left_over_budget/num_queues;

2576

budget_per_queue = left_over_budget/num_queues;

2563

left_over_budget = 0;

2577

left_over_budget = 0;

2564

2578

2565

for_each_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {

2579

for_each_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {

2566

if (test_bit(i, &serviced_queues))

2580

if (test_bit(i, &serviced_queues))

2567

continue;

2581

continue;

2568

rx_queue = priv->rx_queue[i];

2582

rx_queue = priv->rx_queue[i];

2569

tx_queue = priv->tx_queue[rx_queue->qindex];

2583

tx_queue = priv->tx_queue[rx_queue->qindex];

2570

2584

2571

/* If we fail to get the lock,

2585

tx_cleaned += gfar_clean_tx_ring(tx_queue);

2572

* don't bother with the TX BDs */

2573

if (spin_trylock_irqsave(&tx_queue->txlock, flags)) {

2574

tx_cleaned += gfar_clean_tx_ring(tx_queue);

2575

spin_unlock_irqrestore(&tx_queue->txlock,

2576

flags);

2577

}

2578

2579

rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,

2586

rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,

2580

budget_per_queue);

2587

budget_per_queue);

2581

rx_cleaned += rx_cleaned_per_queue;

2588

rx_cleaned += rx_cleaned_per_queue;

2582

if(rx_cleaned_per_queue < budget_per_queue) {

2589

if(rx_cleaned_per_queue < budget_per_queue) {

2583

left_over_budget = left_over_budget +

2590

left_over_budget = left_over_budget +

2584

(budget_per_queue - rx_cleaned_per_queue);

2591

(budget_per_queue - rx_cleaned_per_queue);

2585

set_bit(i, &serviced_queues);

2592

set_bit(i, &serviced_queues);

2586

num_queues--;

2593

num_queues--;

2587

}

2594

}

2588

}

2595

}

2589

}

2596

}

2590

2597

2591

if (tx_cleaned)

2598

if (tx_cleaned)

2592

return budget;

2599

return budget;

2593

2600

2594

if (rx_cleaned < budget) {

2601

if (rx_cleaned < budget) {

2595

napi_complete(napi);

2602

napi_complete(napi);

2596

2603

2597

/* Clear the halt bit in RSTAT */

2604

/* Clear the halt bit in RSTAT */

2598

gfar_write(&regs->rstat, gfargrp->rstat);

2605

gfar_write(&regs->rstat, gfargrp->rstat);

2599

2606

2600

gfar_write(&regs->imask, IMASK_DEFAULT);

2607

gfar_write(&regs->imask, IMASK_DEFAULT);

2601

2608

2602

/* If we are coalescing interrupts, update the timer */

2609

/* If we are coalescing interrupts, update the timer */

2603

/* Otherwise, clear it */

2610

/* Otherwise, clear it */

2604

gfar_configure_coalescing(priv,

2611

gfar_configure_coalescing(priv,

2605

gfargrp->rx_bit_map, gfargrp->tx_bit_map);

2612

gfargrp->rx_bit_map, gfargrp->tx_bit_map);

2606

}

2613

}

2607

2614

2608

return rx_cleaned;

2615

return rx_cleaned;

2609

}

2616

}

2610

2617

2611

#ifdef CONFIG_NET_POLL_CONTROLLER

2618

#ifdef CONFIG_NET_POLL_CONTROLLER

2612

/*

2619

/*

2613

* Polling 'interrupt' - used by things like netconsole to send skbs

2620

* Polling 'interrupt' - used by things like netconsole to send skbs

2614

* without having to re-enable interrupts. It's not called while

2621

* without having to re-enable interrupts. It's not called while

2615

* the interrupt routine is executing.

2622

* the interrupt routine is executing.

2616

*/

2623

*/

2617

static void gfar_netpoll(struct net_device *dev)

2624

static void gfar_netpoll(struct net_device *dev)

2618

{

2625

{

2619

struct gfar_private *priv = netdev_priv(dev);

2626

struct gfar_private *priv = netdev_priv(dev);

2620

int i = 0;

2627

int i = 0;

2621

2628

2622

/* If the device has multiple interrupts, run tx/rx */

2629

/* If the device has multiple interrupts, run tx/rx */

2623

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {

2630

if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {

2624

for (i = 0; i < priv->num_grps; i++) {

2631

for (i = 0; i < priv->num_grps; i++) {

2625

disable_irq(priv->gfargrp[i].interruptTransmit);

2632

disable_irq(priv->gfargrp[i].interruptTransmit);

2626

disable_irq(priv->gfargrp[i].interruptReceive);

2633

disable_irq(priv->gfargrp[i].interruptReceive);

2627

disable_irq(priv->gfargrp[i].interruptError);

2634

disable_irq(priv->gfargrp[i].interruptError);

2628

gfar_interrupt(priv->gfargrp[i].interruptTransmit,

2635

gfar_interrupt(priv->gfargrp[i].interruptTransmit,

2629

&priv->gfargrp[i]);

2636

&priv->gfargrp[i]);

2630

enable_irq(priv->gfargrp[i].interruptError);

2637

enable_irq(priv->gfargrp[i].interruptError);

2631

enable_irq(priv->gfargrp[i].interruptReceive);

2638

enable_irq(priv->gfargrp[i].interruptReceive);

2632

enable_irq(priv->gfargrp[i].interruptTransmit);

2639

enable_irq(priv->gfargrp[i].interruptTransmit);

2633

}

2640

}

2634

} else {

2641

} else {

2635

for (i = 0; i < priv->num_grps; i++) {

2642

for (i = 0; i < priv->num_grps; i++) {

2636

disable_irq(priv->gfargrp[i].interruptTransmit);

2643

disable_irq(priv->gfargrp[i].interruptTransmit);

2637

gfar_interrupt(priv->gfargrp[i].interruptTransmit,

2644

gfar_interrupt(priv->gfargrp[i].interruptTransmit,

2638

&priv->gfargrp[i]);

2645

&priv->gfargrp[i]);

2639

enable_irq(priv->gfargrp[i].interruptTransmit);

2646

enable_irq(priv->gfargrp[i].interruptTransmit);

2640

}

2647

}

2641

}

2648

}

2642

#endif

2649

#endif

2643

2650

2644

/* The interrupt handler for devices with one interrupt */

2651

/* The interrupt handler for devices with one interrupt */

2645

static irqreturn_t gfar_interrupt(int irq, void *grp_id)

2652

static irqreturn_t gfar_interrupt(int irq, void *grp_id)

2646

{

2653

{

2647

struct gfar_priv_grp *gfargrp = grp_id;

2654

struct gfar_priv_grp *gfargrp = grp_id;

2648

2655

2649

/* Save ievent for future reference */

2656

/* Save ievent for future reference */

2650

u32 events = gfar_read(&gfargrp->regs->ievent);

2657

u32 events = gfar_read(&gfargrp->regs->ievent);

2651

2658

2652

/* Check for reception */

2659

/* Check for reception */

2653

if (events & IEVENT_RX_MASK)

2660

if (events & IEVENT_RX_MASK)

2654

gfar_receive(irq, grp_id);

2661

gfar_receive(irq, grp_id);

2655

2662

2656

/* Check for transmit completion */

2663

/* Check for transmit completion */

2657

if (events & IEVENT_TX_MASK)

2664

if (events & IEVENT_TX_MASK)

2658

gfar_transmit(irq, grp_id);

2665

gfar_transmit(irq, grp_id);

2659

2666

2660

/* Check for errors */

2667

/* Check for errors */

2661

if (events & IEVENT_ERR_MASK)

2668

if (events & IEVENT_ERR_MASK)

2662

gfar_error(irq, grp_id);

2669

gfar_error(irq, grp_id);

2663

2670

2664

return IRQ_HANDLED;

2671

return IRQ_HANDLED;

2665

}

2672

}

2666

2673

2667

/* Called every time the controller might need to be made

2674

/* Called every time the controller might need to be made

2668

* aware of new link state. The PHY code conveys this

2675

* aware of new link state. The PHY code conveys this

2669

* information through variables in the phydev structure, and this

2676

* information through variables in the phydev structure, and this

2670

* function converts those variables into the appropriate

2677

* function converts those variables into the appropriate

2671

* register values, and can bring down the device if needed.

2678

* register values, and can bring down the device if needed.

2672

*/

2679

*/

2673

static void adjust_link(struct net_device *dev)

2680

static void adjust_link(struct net_device *dev)

2674

{

2681

{

2675

struct gfar_private *priv = netdev_priv(dev);

2682

struct gfar_private *priv = netdev_priv(dev);

2676

struct gfar __iomem *regs = priv->gfargrp[0].regs;

2683

struct gfar __iomem *regs = priv->gfargrp[0].regs;

2677

unsigned long flags;

2684

unsigned long flags;

2678

struct phy_device *phydev = priv->phydev;

2685

struct phy_device *phydev = priv->phydev;

2679

int new_state = 0;

2686

int new_state = 0;

2680

2687

2681

local_irq_save(flags);

2688

local_irq_save(flags);

2682

lock_tx_qs(priv);

2689

lock_tx_qs(priv);

2683

2690

2684

if (phydev->link) {

2691

if (phydev->link) {

2685

u32 tempval = gfar_read(&regs->maccfg2);

2692

u32 tempval = gfar_read(&regs->maccfg2);

2686

u32 ecntrl = gfar_read(&regs->ecntrl);

2693

u32 ecntrl = gfar_read(&regs->ecntrl);

2687

2694

2688

/* Now we make sure that we can be in full duplex mode.

2695

/* Now we make sure that we can be in full duplex mode.

2689

* If not, we operate in half-duplex mode. */

2696

* If not, we operate in half-duplex mode. */

2690

if (phydev->duplex != priv->oldduplex) {

2697

if (phydev->duplex != priv->oldduplex) {

2691

new_state = 1;

2698

new_state = 1;

2692

if (!(phydev->duplex))

2699

if (!(phydev->duplex))

2693

tempval &= ~(MACCFG2_FULL_DUPLEX);

2700

tempval &= ~(MACCFG2_FULL_DUPLEX);

2694

else

2701

else

2695

tempval |= MACCFG2_FULL_DUPLEX;

2702

tempval |= MACCFG2_FULL_DUPLEX;

2696

2703

2697

priv->oldduplex = phydev->duplex;

2704

priv->oldduplex = phydev->duplex;

2698

}

2705

}

2699

2706

2700

if (phydev->speed != priv->oldspeed) {

2707

if (phydev->speed != priv->oldspeed) {

2701

new_state = 1;

2708

new_state = 1;

2702

switch (phydev->speed) {

2709

switch (phydev->speed) {

2703

case 1000:

2710

case 1000:

2704

tempval =

2711

tempval =

2705

((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);

2712

((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);

2706

2713

2707

ecntrl &= ~(ECNTRL_R100);

2714

ecntrl &= ~(ECNTRL_R100);

2708

break;

2715

break;

2709

case 100:

2716

case 100:

2710

case 10:

2717

case 10:

2711

tempval =

2718

tempval =

2712

((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);

2719

((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);

2713

2720

2714

/* Reduced mode distinguishes

2721

/* Reduced mode distinguishes

2715

* between 10 and 100 */

2722

* between 10 and 100 */

2716

if (phydev->speed == SPEED_100)

2723

if (phydev->speed == SPEED_100)

2717

ecntrl |= ECNTRL_R100;

2724

ecntrl |= ECNTRL_R100;

2718

else

2725

else

2719

ecntrl &= ~(ECNTRL_R100);

2726

ecntrl &= ~(ECNTRL_R100);

2720

break;

2727

break;

2721

default:

2728

default:

2722

if (netif_msg_link(priv))

2729

if (netif_msg_link(priv))

2723

printk(KERN_WARNING

2730

printk(KERN_WARNING

2724

"%s: Ack! Speed (%d) is not 10/100/1000!\n",

2731

"%s: Ack! Speed (%d) is not 10/100/1000!\n",

2725

dev->name, phydev->speed);

2732

dev->name, phydev->speed);

2726

break;

2733

break;

2727

}

2734

}

2728

2735

2729

priv->oldspeed = phydev->speed;

2736

priv->oldspeed = phydev->speed;

2730

}

2737

}

2731

2738

2732

gfar_write(&regs->maccfg2, tempval);

2739

gfar_write(&regs->maccfg2, tempval);

2733

gfar_write(&regs->ecntrl, ecntrl);

2740

gfar_write(&regs->ecntrl, ecntrl);

2734

2741

2735

if (!priv->oldlink) {

2742

if (!priv->oldlink) {

2736

new_state = 1;

2743

new_state = 1;

2737

priv->oldlink = 1;

2744

priv->oldlink = 1;

2738

}

2745

}

2739

} else if (priv->oldlink) {

2746

} else if (priv->oldlink) {

2740

new_state = 1;

2747

new_state = 1;

2741

priv->oldlink = 0;

2748

priv->oldlink = 0;

2742

priv->oldspeed = 0;

2749

priv->oldspeed = 0;

2743

priv->oldduplex = -1;

2750

priv->oldduplex = -1;

2744

}

2751

}

2745

2752

2746

if (new_state && netif_msg_link(priv))

2753

if (new_state && netif_msg_link(priv))

2747

phy_print_status(phydev);

2754

phy_print_status(phydev);

2748

unlock_tx_qs(priv);

2755

unlock_tx_qs(priv);

2749

local_irq_restore(flags);

2756

local_irq_restore(flags);

2750

}

2757

}

2751

2758

2752

/* Update the hash table based on the current list of multicast

2759

/* Update the hash table based on the current list of multicast

2753

* addresses we subscribe to. Also, change the promiscuity of

2760

* addresses we subscribe to. Also, change the promiscuity of

2754

* the device based on the flags (this function is called

2761

* the device based on the flags (this function is called

2755

* whenever dev->flags is changed */

2762

* whenever dev->flags is changed */

2756

static void gfar_set_multi(struct net_device *dev)

2763

static void gfar_set_multi(struct net_device *dev)

2757

{

2764

{

2758

struct dev_mc_list *mc_ptr;

2765

struct dev_mc_list *mc_ptr;

2759

struct gfar_private *priv = netdev_priv(dev);

2766

struct gfar_private *priv = netdev_priv(dev);

2760

struct gfar __iomem *regs = priv->gfargrp[0].regs;

2767

struct gfar __iomem *regs = priv->gfargrp[0].regs;

2761

u32 tempval;

2768

u32 tempval;

2762

2769

2763

if (dev->flags & IFF_PROMISC) {

2770

if (dev->flags & IFF_PROMISC) {

2764

/* Set RCTRL to PROM */

2771

/* Set RCTRL to PROM */

2765

tempval = gfar_read(&regs->rctrl);

2772

tempval = gfar_read(&regs->rctrl);

2766

tempval |= RCTRL_PROM;

2773

tempval |= RCTRL_PROM;

2767

gfar_write(&regs->rctrl, tempval);

2774

gfar_write(&regs->rctrl, tempval);

2768

} else {

2775

} else {

2769

/* Set RCTRL to not PROM */

2776

/* Set RCTRL to not PROM */

2770

tempval = gfar_read(&regs->rctrl);

2777

tempval = gfar_read(&regs->rctrl);

2771

tempval &= ~(RCTRL_PROM);

2778

tempval &= ~(RCTRL_PROM);

2772

gfar_write(&regs->rctrl, tempval);

2779

gfar_write(&regs->rctrl, tempval);

2773

}

2780

}

2774

2781

2775

if (dev->flags & IFF_ALLMULTI) {

2782

if (dev->flags & IFF_ALLMULTI) {

2776

/* Set the hash to rx all multicast frames */

2783

/* Set the hash to rx all multicast frames */

2777

gfar_write(&regs->igaddr0, 0xffffffff);

2784

gfar_write(&regs->igaddr0, 0xffffffff);

2778

gfar_write(&regs->igaddr1, 0xffffffff);

2785

gfar_write(&regs->igaddr1, 0xffffffff);

2779

gfar_write(&regs->igaddr2, 0xffffffff);

2786

gfar_write(&regs->igaddr2, 0xffffffff);

2780

gfar_write(&regs->igaddr3, 0xffffffff);

2787

gfar_write(&regs->igaddr3, 0xffffffff);

2781

gfar_write(&regs->igaddr4, 0xffffffff);

2788

gfar_write(&regs->igaddr4, 0xffffffff);

2782

gfar_write(&regs->igaddr5, 0xffffffff);

2789

gfar_write(&regs->igaddr5, 0xffffffff);

2783

gfar_write(&regs->igaddr6, 0xffffffff);

2790

gfar_write(&regs->igaddr6, 0xffffffff);

2784

gfar_write(&regs->igaddr7, 0xffffffff);

2791

gfar_write(&regs->igaddr7, 0xffffffff);

2785

gfar_write(&regs->gaddr0, 0xffffffff);

2792

gfar_write(&regs->gaddr0, 0xffffffff);

2786

gfar_write(&regs->gaddr1, 0xffffffff);

2793

gfar_write(&regs->gaddr1, 0xffffffff);

2787

gfar_write(&regs->gaddr2, 0xffffffff);

2794

gfar_write(&regs->gaddr2, 0xffffffff);

2788

gfar_write(&regs->gaddr3, 0xffffffff);

2795

gfar_write(&regs->gaddr3, 0xffffffff);

2789

gfar_write(&regs->gaddr4, 0xffffffff);

2796

gfar_write(&regs->gaddr4, 0xffffffff);

2790

gfar_write(&regs->gaddr5, 0xffffffff);

2797

gfar_write(&regs->gaddr5, 0xffffffff);

2791

gfar_write(&regs->gaddr6, 0xffffffff);

2798

gfar_write(&regs->gaddr6, 0xffffffff);

2792

gfar_write(&regs->gaddr7, 0xffffffff);

2799

gfar_write(&regs->gaddr7, 0xffffffff);

2793

} else {

2800

} else {

2794

int em_num;

2801

int em_num;

2795

int idx;

2802

int idx;

2796

2803

2797

/* zero out the hash */

2804

/* zero out the hash */

2798

gfar_write(&regs->igaddr0, 0x0);

2805

gfar_write(&regs->igaddr0, 0x0);

2799

gfar_write(&regs->igaddr1, 0x0);

2806

gfar_write(&regs->igaddr1, 0x0);

2800

gfar_write(&regs->igaddr2, 0x0);

2807

gfar_write(&regs->igaddr2, 0x0);

2801

gfar_write(&regs->igaddr3, 0x0);

2808

gfar_write(&regs->igaddr3, 0x0);

2802

gfar_write(&regs->igaddr4, 0x0);

2809

gfar_write(&regs->igaddr4, 0x0);

2803

gfar_write(&regs->igaddr5, 0x0);

2810

gfar_write(&regs->igaddr5, 0x0);

2804

gfar_write(&regs->igaddr6, 0x0);

2811

gfar_write(&regs->igaddr6, 0x0);

2805

gfar_write(&regs->igaddr7, 0x0);

2812

gfar_write(&regs->igaddr7, 0x0);

2806

gfar_write(&regs->gaddr0, 0x0);

2813

gfar_write(&regs->gaddr0, 0x0);

2807

gfar_write(&regs->gaddr1, 0x0);

2814

gfar_write(&regs->gaddr1, 0x0);

2808

gfar_write(&regs->gaddr2, 0x0);

2815

gfar_write(&regs->gaddr2, 0x0);

2809

gfar_write(&regs->gaddr3, 0x0);

2816

gfar_write(&regs->gaddr3, 0x0);

2810

gfar_write(&regs->gaddr4, 0x0);

2817

gfar_write(&regs->gaddr4, 0x0);

2811

gfar_write(&regs->gaddr5, 0x0);

2818

gfar_write(&regs->gaddr5, 0x0);

2812

gfar_write(&regs->gaddr6, 0x0);

2819

gfar_write(&regs->gaddr6, 0x0);

2813

gfar_write(&regs->gaddr7, 0x0);

2820

gfar_write(&regs->gaddr7, 0x0);

2814

2821

2815

/* If we have extended hash tables, we need to

2822

/* If we have extended hash tables, we need to

2816

* clear the exact match registers to prepare for

2823

* clear the exact match registers to prepare for

2817

* setting them */

2824

* setting them */

2818

if (priv->extended_hash) {

2825

if (priv->extended_hash) {

2819

em_num = GFAR_EM_NUM + 1;

2826

em_num = GFAR_EM_NUM + 1;

2820

gfar_clear_exact_match(dev);

2827

gfar_clear_exact_match(dev);

2821

idx = 1;

2828

idx = 1;

2822

} else {

2829

} else {

2823

idx = 0;

2830

idx = 0;

2824

em_num = 0;

2831

em_num = 0;

2825

}

2832

}

2826

2833

2827

if (dev->mc_count == 0)

2834

if (dev->mc_count == 0)

2828

return;

2835

return;

2829

2836

2830

/* Parse the list, and set the appropriate bits */

2837

/* Parse the list, and set the appropriate bits */

2831

for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {

2838

for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {

2832

if (idx < em_num) {

2839

if (idx < em_num) {

2833

gfar_set_mac_for_addr(dev, idx,

2840

gfar_set_mac_for_addr(dev, idx,

2834

mc_ptr->dmi_addr);

2841

mc_ptr->dmi_addr);

2835

idx++;

2842

idx++;

2836

} else

2843

} else

2837

gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);

2844

gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);

2838

}

2845

}

2839

}

2846

}

2840

2847

2841

return;

2848

return;

2842

}

2849

}

2843

2850

2844

2851

2845

/* Clears each of the exact match registers to zero, so they

2852

/* Clears each of the exact match registers to zero, so they

2846

* don't interfere with normal reception */

2853

* don't interfere with normal reception */

2847

static void gfar_clear_exact_match(struct net_device *dev)

2854

static void gfar_clear_exact_match(struct net_device *dev)

2848

{

2855

{

2849

int idx;

2856

int idx;

2850

u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};

2857

u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};

2851

2858

2852

for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)

2859

for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)

2853

gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);

2860

gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);

2854

}

2861

}

2855

2862

2856

/* Set the appropriate hash bit for the given addr */

2863

/* Set the appropriate hash bit for the given addr */

2857

/* The algorithm works like so:

2864

/* The algorithm works like so:

2858

* 1) Take the Destination Address (ie the multicast address), and

2865

* 1) Take the Destination Address (ie the multicast address), and

2859

* do a CRC on it (little endian), and reverse the bits of the

2866

* do a CRC on it (little endian), and reverse the bits of the

2860

* result.

2867

* result.

2861

* 2) Use the 8 most significant bits as a hash into a 256-entry

2868

* 2) Use the 8 most significant bits as a hash into a 256-entry

2862

* table. The table is controlled through 8 32-bit registers:

2869

* table. The table is controlled through 8 32-bit registers:

2863

* gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is

2870

* gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is

2864

* gaddr7. This means that the 3 most significant bits in the

2871

* gaddr7. This means that the 3 most significant bits in the

2865

* hash index which gaddr register to use, and the 5 other bits

2872

* hash index which gaddr register to use, and the 5 other bits

2866

* indicate which bit (assuming an IBM numbering scheme, which

2873

* indicate which bit (assuming an IBM numbering scheme, which

2867

* for PowerPC (tm) is usually the case) in the register holds

2874

* for PowerPC (tm) is usually the case) in the register holds

2868

* the entry. */

2875

* the entry. */

2869

static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)

2876

static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)

2870

{

2877

{

2871

u32 tempval;

2878

u32 tempval;

2872

struct gfar_private *priv = netdev_priv(dev);

2879

struct gfar_private *priv = netdev_priv(dev);

2873

u32 result = ether_crc(MAC_ADDR_LEN, addr);

2880

u32 result = ether_crc(MAC_ADDR_LEN, addr);

2874

int width = priv->hash_width;

2881

int width = priv->hash_width;

2875

u8 whichbit = (result >> (32 - width)) & 0x1f;

2882

u8 whichbit = (result >> (32 - width)) & 0x1f;

2876

u8 whichreg = result >> (32 - width + 5);

2883

u8 whichreg = result >> (32 - width + 5);

2877

u32 value = (1 << (31-whichbit));

2884

u32 value = (1 << (31-whichbit));

2878

2885

2879

tempval = gfar_read(priv->hash_regs[whichreg]);

2886

tempval = gfar_read(priv->hash_regs[whichreg]);

2880

tempval |= value;

2887

tempval |= value;

2881

gfar_write(priv->hash_regs[whichreg], tempval);

2888

gfar_write(priv->hash_regs[whichreg], tempval);

2882

2889

2883

return;

2890

return;

2884

}

2891

}

2885

2892

2886

2893

2887

/* There are multiple MAC Address register pairs on some controllers

2894

/* There are multiple MAC Address register pairs on some controllers

2888

* This function sets the numth pair to a given address

2895

* This function sets the numth pair to a given address

2889

*/

2896

*/

2890

static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)

2897

static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)

2891

{

2898

{

2892

struct gfar_private *priv = netdev_priv(dev);

2899

struct gfar_private *priv = netdev_priv(dev);

2893

struct gfar __iomem *regs = priv->gfargrp[0].regs;

2900

struct gfar __iomem *regs = priv->gfargrp[0].regs;

2894

int idx;

2901

int idx;

2895

char tmpbuf[MAC_ADDR_LEN];

2902

char tmpbuf[MAC_ADDR_LEN];

2896

u32 tempval;

2903

u32 tempval;

2897

u32 __iomem *macptr = &regs->macstnaddr1;

2904

u32 __iomem *macptr = &regs->macstnaddr1;

2898

2905

2899

macptr += num*2;

2906

macptr += num*2;

2900

2907

2901

/* Now copy it into the mac registers backwards, cuz */

2908

/* Now copy it into the mac registers backwards, cuz */

2902

/* little endian is silly */

2909

/* little endian is silly */

2903

for (idx = 0; idx < MAC_ADDR_LEN; idx++)

2910

for (idx = 0; idx < MAC_ADDR_LEN; idx++)

2904

tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];

2911

tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];

2905

2912

2906

gfar_write(macptr, *((u32 *) (tmpbuf)));

2913

gfar_write(macptr, *((u32 *) (tmpbuf)));

2907

2914

2908

tempval = *((u32 *) (tmpbuf + 4));

2915

tempval = *((u32 *) (tmpbuf + 4));

2909

2916

2910

gfar_write(macptr+1, tempval);

2917

gfar_write(macptr+1, tempval);

2911

}

2918

}

2912

2919

2913

/* GFAR error interrupt handler */

2920

/* GFAR error interrupt handler */

2914

static irqreturn_t gfar_error(int irq, void *grp_id)

2921

static irqreturn_t gfar_error(int irq, void *grp_id)

2915

{

2922

{

2916

struct gfar_priv_grp *gfargrp = grp_id;

2923

struct gfar_priv_grp *gfargrp = grp_id;

2917

struct gfar __iomem *regs = gfargrp->regs;

2924

struct gfar __iomem *regs = gfargrp->regs;

2918

struct gfar_private *priv= gfargrp->priv;

2925

struct gfar_private *priv= gfargrp->priv;

2919

struct net_device *dev = priv->ndev;

2926

struct net_device *dev = priv->ndev;

2920

2927

2921

/* Save ievent for future reference */

2928

/* Save ievent for future reference */

2922

u32 events = gfar_read(&regs->ievent);

2929

u32 events = gfar_read(&regs->ievent);

2923

2930

2924

/* Clear IEVENT */

2931

/* Clear IEVENT */

2925

gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);

2932

gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);

2926

2933

2927

/* Magic Packet is not an error. */

2934

/* Magic Packet is not an error. */

2928

if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&

2935

if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&

2929

(events & IEVENT_MAG))

2936

(events & IEVENT_MAG))

2930

events &= ~IEVENT_MAG;

2937

events &= ~IEVENT_MAG;

2931

2938

2932

/* Hmm... */

2939

/* Hmm... */

2933

if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))

2940

if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))

2934

printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",

2941

printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",

2935

dev->name, events, gfar_read(&regs->imask));

2942

dev->name, events, gfar_read(&regs->imask));

2936

2943

2937

/* Update the error counters */

2944

/* Update the error counters */

2938

if (events & IEVENT_TXE) {

2945

if (events & IEVENT_TXE) {

2939

dev->stats.tx_errors++;

2946

dev->stats.tx_errors++;

2940

2947

2941

if (events & IEVENT_LC)

2948

if (events & IEVENT_LC)

2942

dev->stats.tx_window_errors++;

2949

dev->stats.tx_window_errors++;

2943

if (events & IEVENT_CRL)

2950

if (events & IEVENT_CRL)

2944

dev->stats.tx_aborted_errors++;

2951

dev->stats.tx_aborted_errors++;

2945

if (events & IEVENT_XFUN) {

2952

if (events & IEVENT_XFUN) {

2946

unsigned long flags;

2953

unsigned long flags;

2947

2954

2948

if (netif_msg_tx_err(priv))

2955

if (netif_msg_tx_err(priv))

2949

printk(KERN_DEBUG "%s: TX FIFO underrun, "

2956

printk(KERN_DEBUG "%s: TX FIFO underrun, "

2950

"packet dropped.\n", dev->name);

2957

"packet dropped.\n", dev->name);

2951

dev->stats.tx_dropped++;

2958

dev->stats.tx_dropped++;

2952

priv->extra_stats.tx_underrun++;

2959

priv->extra_stats.tx_underrun++;

2953

2960

2954

local_irq_save(flags);

2961

local_irq_save(flags);

2955

lock_tx_qs(priv);

2962

lock_tx_qs(priv);

2956

2963

2957

/* Reactivate the Tx Queues */

2964

/* Reactivate the Tx Queues */

2958

gfar_write(&regs->tstat, gfargrp->tstat);

2965

gfar_write(&regs->tstat, gfargrp->tstat);

2959

2966

2960

unlock_tx_qs(priv);

2967

unlock_tx_qs(priv);

2961

local_irq_restore(flags);

2968

local_irq_restore(flags);

2962

}

2969

}

2963

if (netif_msg_tx_err(priv))

2970

if (netif_msg_tx_err(priv))

2964

printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);

2971

printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);

2965

}

2972

}

2966

if (events & IEVENT_BSY) {

2973

if (events & IEVENT_BSY) {

2967

dev->stats.rx_errors++;

2974

dev->stats.rx_errors++;

2968

priv->extra_stats.rx_bsy++;

2975

priv->extra_stats.rx_bsy++;

2969

2976

2970

gfar_receive(irq, grp_id);

2977

gfar_receive(irq, grp_id);

2971

2978

2972

if (netif_msg_rx_err(priv))

2979

if (netif_msg_rx_err(priv))

2973

printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",

2980

printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",

2974

dev->name, gfar_read(&regs->rstat));

2981

dev->name, gfar_read(&regs->rstat));

2975

}

2982

}

2976

if (events & IEVENT_BABR) {

2983

if (events & IEVENT_BABR) {

2977

dev->stats.rx_errors++;

2984

dev->stats.rx_errors++;

2978

priv->extra_stats.rx_babr++;

2985

priv->extra_stats.rx_babr++;

2979

2986

2980

if (netif_msg_rx_err(priv))

2987

if (netif_msg_rx_err(priv))

2981

printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);

2988

printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);

2982

}

2989

}

2983

if (events & IEVENT_EBERR) {

2990

if (events & IEVENT_EBERR) {

2984

priv->extra_stats.eberr++;

2991

priv->extra_stats.eberr++;

2985

if (netif_msg_rx_err(priv))

2992

if (netif_msg_rx_err(priv))

2986

printk(KERN_DEBUG "%s: bus error\n", dev->name);

2993

printk(KERN_DEBUG "%s: bus error\n", dev->name);

2987

}

2994

}

2988

if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))

2995

if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))

2989

printk(KERN_DEBUG "%s: control frame\n", dev->name);

2996

printk(KERN_DEBUG "%s: control frame\n", dev->name);

2990

2997

2991

if (events & IEVENT_BABT) {

2998

if (events & IEVENT_BABT) {

2992

priv->extra_stats.tx_babt++;

2999

priv->extra_stats.tx_babt++;

2993

if (netif_msg_tx_err(priv))

3000

if (netif_msg_tx_err(priv))

2994

printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);

3001

printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);

2995

}

3002

}

2996

return IRQ_HANDLED;

3003

return IRQ_HANDLED;

2997

}

3004

}

2998

3005

2999

static struct of_device_id gfar_match[] =

3006

static struct of_device_id gfar_match[] =

3000

{

3007

{

3001

{

3008

{

3002

.type = "network",

3009

.type = "network",

3003

.compatible = "gianfar",

3010

.compatible = "gianfar",

3004

},

3011

},

3005

{

3012

{

3006

.compatible = "fsl,etsec2",

3013

.compatible = "fsl,etsec2",

3007

},

3014

},

3008

{},

3015

{},

3009

};

3016

};

3010

MODULE_DEVICE_TABLE(of, gfar_match);

3017

MODULE_DEVICE_TABLE(of, gfar_match);

3011

3018

3012

/* Structure for a device driver */

3019

/* Structure for a device driver */

3013

static struct of_platform_driver gfar_driver = {

3020

static struct of_platform_driver gfar_driver = {

3014

.name = "fsl-gianfar",

3021

.name = "fsl-gianfar",

3015

.match_table = gfar_match,

3022

.match_table = gfar_match,

3016

3023

3017

.probe = gfar_probe,

3024

.probe = gfar_probe,

3018

.remove = gfar_remove,

3025

.remove = gfar_remove,

3019

.suspend = gfar_legacy_suspend,

3026

.suspend = gfar_legacy_suspend,

3020

.resume = gfar_legacy_resume,

3027

.resume = gfar_legacy_resume,

3021

.driver.pm = GFAR_PM_OPS,

3028

.driver.pm = GFAR_PM_OPS,

3022

};

3029

};

3023

3030

3024

static int __init gfar_init(void)

3031

static int __init gfar_init(void)

3025

{

3032

{

3026

return of_register_platform_driver(&gfar_driver);

3033

return of_register_platform_driver(&gfar_driver);

GITLAB

gianfar: Revive SKB recycling

 /*
  * drivers/net/gianfar.c
  *
  * Gianfar Ethernet Driver
  * This driver is designed for the non-CPM ethernet controllers
  * on the 85xx and 83xx family of integrated processors
  * Based on 8260_io/fcc_enet.c
  *
  * Author: Andy Fleming
  * Maintainer: Kumar Gala
  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  *
  * Copyright 2002-2009 Freescale Semiconductor, Inc.
  * Copyright 2007 MontaVista Software, Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *
  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  *  RA 11 31 24.2
  *  Dec +69 19 52
  *  V 3.84
  *  B-V +1.62
  *
  *  Theory of operation
  *
  *  The driver is initialized through of_device. Configuration information
  *  is therefore conveyed through an OF-style device tree.
  *
  *  The Gianfar Ethernet Controller uses a ring of buffer
  *  descriptors.  The beginning is indicated by a register
  *  pointing to the physical address of the start of the ring.
  *  The end is determined by a "wrap" bit being set in the
  *  last descriptor of the ring.
  *
  *  When a packet is received, the RXF bit in the
  *  IEVENT register is set, triggering an interrupt when the
  *  corresponding bit in the IMASK register is also set (if
  *  interrupt coalescing is active, then the interrupt may not
  *  happen immediately, but will wait until either a set number
  *  of frames or amount of time have passed).  In NAPI, the
  *  interrupt handler will signal there is work to be done, and
  *  exit. This method will start at the last known empty
  *  descriptor, and process every subsequent descriptor until there
  *  are none left with data (NAPI will stop after a set number of
  *  packets to give time to other tasks, but will eventually
  *  process all the packets).  The data arrives inside a
  *  pre-allocated skb, and so after the skb is passed up to the
  *  stack, a new skb must be allocated, and the address field in
  *  the buffer descriptor must be updated to indicate this new
  *  skb.
  *
  *  When the kernel requests that a packet be transmitted, the
  *  driver starts where it left off last time, and points the
  *  descriptor at the buffer which was passed in.  The driver
  *  then informs the DMA engine that there are packets ready to
  *  be transmitted.  Once the controller is finished transmitting
  *  the packet, an interrupt may be triggered (under the same
  *  conditions as for reception, but depending on the TXF bit).
  *  The driver then cleans up the buffer.
  */
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/errno.h>
 #include <linux/unistd.h>
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
 #include <linux/if_vlan.h>
 #include <linux/spinlock.h>
 #include <linux/mm.h>
 #include <linux/of_mdio.h>
 #include <linux/of_platform.h>
 #include <linux/ip.h>
 #include <linux/tcp.h>
 #include <linux/udp.h>
 #include <linux/in.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/uaccess.h>
 #include <linux/module.h>
 #include <linux/dma-mapping.h>
 #include <linux/crc32.h>
 #include <linux/mii.h>
 #include <linux/phy.h>
 #include <linux/phy_fixed.h>
 #include <linux/of.h>
 #include "gianfar.h"
 #include "fsl_pq_mdio.h"
 #define TX_TIMEOUT      (1*HZ)
 #undef BRIEF_GFAR_ERRORS
 #undef VERBOSE_GFAR_ERRORS
 const char gfar_driver_name[] = "Gianfar Ethernet";
 const char gfar_driver_version[] = "1.3";
 static int gfar_enet_open(struct net_device *dev);
 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 static void gfar_reset_task(struct work_struct *work);
 static void gfar_timeout(struct net_device *dev);
 static int gfar_close(struct net_device *dev);
 struct sk_buff *gfar_new_skb(struct net_device *dev);
 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 		struct sk_buff *skb);
 static int gfar_set_mac_address(struct net_device *dev);
 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 static irqreturn_t gfar_error(int irq, void *dev_id);
 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 static void adjust_link(struct net_device *dev);
 static void init_registers(struct net_device *dev);
 static int init_phy(struct net_device *dev);
 static int gfar_probe(struct of_device *ofdev,
 		const struct of_device_id *match);
 static int gfar_remove(struct of_device *ofdev);
 static void free_skb_resources(struct gfar_private *priv);
 static void gfar_set_multi(struct net_device *dev);
 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 static void gfar_configure_serdes(struct net_device *dev);
 static int gfar_poll(struct napi_struct *napi, int budget);
 #ifdef CONFIG_NET_POLL_CONTROLLER
 static void gfar_netpoll(struct net_device *dev);
 #endif
 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 			      int amount_pull);
 static void gfar_vlan_rx_register(struct net_device *netdev,
 		                struct vlan_group *grp);
 void gfar_halt(struct net_device *dev);
 static void gfar_halt_nodisable(struct net_device *dev);
 void gfar_start(struct net_device *dev);
 static void gfar_clear_exact_match(struct net_device *dev);
 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb);
 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 MODULE_LICENSE("GPL");
 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 			    dma_addr_t buf)
 {
 	u32 lstatus;
 	bdp->bufPtr = buf;
 	lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 	if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 		lstatus |= BD_LFLAG(RXBD_WRAP);
 	eieio();
 	bdp->lstatus = lstatus;
 }
 static int gfar_init_bds(struct net_device *ndev)
 {
 	struct gfar_private *priv = netdev_priv(ndev);
 	struct gfar_priv_tx_q *tx_queue = NULL;
 	struct gfar_priv_rx_q *rx_queue = NULL;
 	struct txbd8 *txbdp;
 	struct rxbd8 *rxbdp;
 	int i, j;
 	for (i = 0; i < priv->num_tx_queues; i++) {
 		tx_queue = priv->tx_queue[i];
 		/* Initialize some variables in our dev structure */
 		tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 		tx_queue->dirty_tx = tx_queue->tx_bd_base;
 		tx_queue->cur_tx = tx_queue->tx_bd_base;
 		tx_queue->skb_curtx = 0;
 		tx_queue->skb_dirtytx = 0;
 		/* Initialize Transmit Descriptor Ring */
 		txbdp = tx_queue->tx_bd_base;
 		for (j = 0; j < tx_queue->tx_ring_size; j++) {
 			txbdp->lstatus = 0;
 			txbdp->bufPtr = 0;
 			txbdp++;
 		}
 		/* Set the last descriptor in the ring to indicate wrap */
 		txbdp--;
 		txbdp->status |= TXBD_WRAP;
 	}
 	for (i = 0; i < priv->num_rx_queues; i++) {
 		rx_queue = priv->rx_queue[i];
 		rx_queue->cur_rx = rx_queue->rx_bd_base;
 		rx_queue->skb_currx = 0;
 		rxbdp = rx_queue->rx_bd_base;
 		for (j = 0; j < rx_queue->rx_ring_size; j++) {
 			struct sk_buff *skb = rx_queue->rx_skbuff[j];
 			if (skb) {
 				gfar_init_rxbdp(rx_queue, rxbdp,
 						rxbdp->bufPtr);
 			} else {
 				skb = gfar_new_skb(ndev);
 				if (!skb) {
 					pr_err("%s: Can't allocate RX buffers\n",
 							ndev->name);
 					goto err_rxalloc_fail;
 				}
 				rx_queue->rx_skbuff[j] = skb;
 				gfar_new_rxbdp(rx_queue, rxbdp, skb);
 			}
 			rxbdp++;
 		}
 	}
 	return 0;
 err_rxalloc_fail:
 	free_skb_resources(priv);
 	return -ENOMEM;
 }
 static int gfar_alloc_skb_resources(struct net_device *ndev)
 {
 	void *vaddr;
 	dma_addr_t addr;
 	int i, j, k;
 	struct gfar_private *priv = netdev_priv(ndev);
 	struct device *dev = &priv->ofdev->dev;
 	struct gfar_priv_tx_q *tx_queue = NULL;
 	struct gfar_priv_rx_q *rx_queue = NULL;
 	priv->total_tx_ring_size = 0;
 	for (i = 0; i < priv->num_tx_queues; i++)
 		priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 	priv->total_rx_ring_size = 0;
 	for (i = 0; i < priv->num_rx_queues; i++)
 		priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 	/* Allocate memory for the buffer descriptors */
 	vaddr = dma_alloc_coherent(dev,
 			sizeof(struct txbd8) * priv->total_tx_ring_size +
 			sizeof(struct rxbd8) * priv->total_rx_ring_size,
 			&addr, GFP_KERNEL);
 	if (!vaddr) {
 		if (netif_msg_ifup(priv))
 			pr_err("%s: Could not allocate buffer descriptors!\n",
 			       ndev->name);
 		return -ENOMEM;
 	}
 	for (i = 0; i < priv->num_tx_queues; i++) {
 		tx_queue = priv->tx_queue[i];
 		tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
 		tx_queue->tx_bd_dma_base = addr;
 		tx_queue->dev = ndev;
 		/* enet DMA only understands physical addresses */
 		addr    += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 		vaddr   += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 	}
 	/* Start the rx descriptor ring where the tx ring leaves off */
 	for (i = 0; i < priv->num_rx_queues; i++) {
 		rx_queue = priv->rx_queue[i];
 		rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
 		rx_queue->rx_bd_dma_base = addr;
 		rx_queue->dev = ndev;
 		addr    += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 		vaddr   += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 	}
 	/* Setup the skbuff rings */
 	for (i = 0; i < priv->num_tx_queues; i++) {
 		tx_queue = priv->tx_queue[i];
 		tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 				  tx_queue->tx_ring_size, GFP_KERNEL);
 		if (!tx_queue->tx_skbuff) {
 			if (netif_msg_ifup(priv))
 				pr_err("%s: Could not allocate tx_skbuff\n",
 						ndev->name);
 			goto cleanup;
 		}
 		for (k = 0; k < tx_queue->tx_ring_size; k++)
 			tx_queue->tx_skbuff[k] = NULL;
 	}
 	for (i = 0; i < priv->num_rx_queues; i++) {
 		rx_queue = priv->rx_queue[i];
 		rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 				  rx_queue->rx_ring_size, GFP_KERNEL);
 		if (!rx_queue->rx_skbuff) {
 			if (netif_msg_ifup(priv))
 				pr_err("%s: Could not allocate rx_skbuff\n",
 				       ndev->name);
 			goto cleanup;
 		}
 		for (j = 0; j < rx_queue->rx_ring_size; j++)
 			rx_queue->rx_skbuff[j] = NULL;
 	}
 	if (gfar_init_bds(ndev))
 		goto cleanup;
 	return 0;
 cleanup:
 	free_skb_resources(priv);
 	return -ENOMEM;
 }
 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 {
 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
 	u32 __iomem *baddr;
 	int i;
 	baddr = &regs->tbase0;
 	for(i = 0; i < priv->num_tx_queues; i++) {
 		gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 		baddr	+= 2;
 	}
 	baddr = &regs->rbase0;
 	for(i = 0; i < priv->num_rx_queues; i++) {
 		gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 		baddr   += 2;
 	}
 }
 static void gfar_init_mac(struct net_device *ndev)
 {
 	struct gfar_private *priv = netdev_priv(ndev);
 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
 	u32 rctrl = 0;
 	u32 tctrl = 0;
 	u32 attrs = 0;
 	/* write the tx/rx base registers */
 	gfar_init_tx_rx_base(priv);
 	/* Configure the coalescing support */
 	gfar_configure_coalescing(priv, 0xFF, 0xFF);
 	if (priv->rx_filer_enable)
 		rctrl |= RCTRL_FILREN;
 	if (priv->rx_csum_enable)
 		rctrl |= RCTRL_CHECKSUMMING;
 	if (priv->extended_hash) {
 		rctrl |= RCTRL_EXTHASH;
 		gfar_clear_exact_match(ndev);
 		rctrl |= RCTRL_EMEN;
 	}
 	if (priv->padding) {
 		rctrl &= ~RCTRL_PAL_MASK;
 		rctrl |= RCTRL_PADDING(priv->padding);
 	}
 	/* keep vlan related bits if it's enabled */
 	if (priv->vlgrp) {
 		rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 		tctrl |= TCTRL_VLINS;
 	}
 	/* Init rctrl based on our settings */
 	gfar_write(&regs->rctrl, rctrl);
 	if (ndev->features & NETIF_F_IP_CSUM)
 		tctrl |= TCTRL_INIT_CSUM;
 	tctrl |= TCTRL_TXSCHED_PRIO;
 	gfar_write(&regs->tctrl, tctrl);
 	/* Set the extraction length and index */
 	attrs = ATTRELI_EL(priv->rx_stash_size) |
 		ATTRELI_EI(priv->rx_stash_index);
 	gfar_write(&regs->attreli, attrs);
 	/* Start with defaults, and add stashing or locking
 	 * depending on the approprate variables */
 	attrs = ATTR_INIT_SETTINGS;
 	if (priv->bd_stash_en)
 		attrs |= ATTR_BDSTASH;
 	if (priv->rx_stash_size != 0)
 		attrs |= ATTR_BUFSTASH;
 	gfar_write(&regs->attr, attrs);
 	gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 	gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 	gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 }
 static const struct net_device_ops gfar_netdev_ops = {
 	.ndo_open = gfar_enet_open,
 	.ndo_start_xmit = gfar_start_xmit,
 	.ndo_stop = gfar_close,
 	.ndo_change_mtu = gfar_change_mtu,
 	.ndo_set_multicast_list = gfar_set_multi,
 	.ndo_tx_timeout = gfar_timeout,
 	.ndo_do_ioctl = gfar_ioctl,
 	.ndo_select_queue = gfar_select_queue,
 	.ndo_vlan_rx_register = gfar_vlan_rx_register,
 	.ndo_set_mac_address = eth_mac_addr,
 	.ndo_validate_addr = eth_validate_addr,
 #ifdef CONFIG_NET_POLL_CONTROLLER
 	.ndo_poll_controller = gfar_netpoll,
 #endif
 };
 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
 void lock_rx_qs(struct gfar_private *priv)
 {
 	int i = 0x0;
 	for (i = 0; i < priv->num_rx_queues; i++)
 		spin_lock(&priv->rx_queue[i]->rxlock);
 }
 void lock_tx_qs(struct gfar_private *priv)
 {
 	int i = 0x0;
 	for (i = 0; i < priv->num_tx_queues; i++)
 		spin_lock(&priv->tx_queue[i]->txlock);
 }
 void unlock_rx_qs(struct gfar_private *priv)
 {
 	int i = 0x0;
 	for (i = 0; i < priv->num_rx_queues; i++)
 		spin_unlock(&priv->rx_queue[i]->rxlock);
 }
 void unlock_tx_qs(struct gfar_private *priv)
 {
 	int i = 0x0;
 	for (i = 0; i < priv->num_tx_queues; i++)
 		spin_unlock(&priv->tx_queue[i]->txlock);
 }
 /* Returns 1 if incoming frames use an FCB */
 static inline int gfar_uses_fcb(struct gfar_private *priv)
 {
 	return priv->vlgrp || priv->rx_csum_enable;
 }
 u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb)
 {
 	return skb_get_queue_mapping(skb);
 }
 static void free_tx_pointers(struct gfar_private *priv)
 {
 	int i = 0;
 	for (i = 0; i < priv->num_tx_queues; i++)
 		kfree(priv->tx_queue[i]);
 }
 static void free_rx_pointers(struct gfar_private *priv)
 {
 	int i = 0;
 	for (i = 0; i < priv->num_rx_queues; i++)
 		kfree(priv->rx_queue[i]);
 }
 static void unmap_group_regs(struct gfar_private *priv)
 {
 	int i = 0;
 	for (i = 0; i < MAXGROUPS; i++)
 		if (priv->gfargrp[i].regs)
 			iounmap(priv->gfargrp[i].regs);
 }
 static void disable_napi(struct gfar_private *priv)
 {
 	int i = 0;
 	for (i = 0; i < priv->num_grps; i++)
 		napi_disable(&priv->gfargrp[i].napi);
 }
 static void enable_napi(struct gfar_private *priv)
 {
 	int i = 0;
 	for (i = 0; i < priv->num_grps; i++)
 		napi_enable(&priv->gfargrp[i].napi);
 }
 static int gfar_parse_group(struct device_node *np,
 		struct gfar_private *priv, const char *model)
 {
 	u32 *queue_mask;
 	u64 addr, size;
 	addr = of_translate_address(np,
 			of_get_address(np, 0, &size, NULL));
 	priv->gfargrp[priv->num_grps].regs = ioremap(addr, size);
 	if (!priv->gfargrp[priv->num_grps].regs)
 		return -ENOMEM;
 	priv->gfargrp[priv->num_grps].interruptTransmit =
 			irq_of_parse_and_map(np, 0);
 	/* If we aren't the FEC we have multiple interrupts */
 	if (model && strcasecmp(model, "FEC")) {
 		priv->gfargrp[priv->num_grps].interruptReceive =
 			irq_of_parse_and_map(np, 1);
 		priv->gfargrp[priv->num_grps].interruptError =
 			irq_of_parse_and_map(np,2);
 		if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
 			priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
 			priv->gfargrp[priv->num_grps].interruptError < 0) {
 			return -EINVAL;
 		}
 	}
 	priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
 	priv->gfargrp[priv->num_grps].priv = priv;
 	spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
 	if(priv->mode == MQ_MG_MODE) {
 		queue_mask = (u32 *)of_get_property(np,
 					"fsl,rx-bit-map", NULL);
 		priv->gfargrp[priv->num_grps].rx_bit_map =
 			queue_mask ?  *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
 		queue_mask = (u32 *)of_get_property(np,
 					"fsl,tx-bit-map", NULL);
 		priv->gfargrp[priv->num_grps].tx_bit_map =
 			queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 	} else {
 		priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
 		priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
 	}
 	priv->num_grps++;
 	return 0;
 }
 static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)
 {
 	const char *model;
 	const char *ctype;
 	const void *mac_addr;
 	int err = 0, i;
 	struct net_device *dev = NULL;
 	struct gfar_private *priv = NULL;
 	struct device_node *np = ofdev->node;
 	struct device_node *child = NULL;
 	const u32 *stash;
 	const u32 *stash_len;
 	const u32 *stash_idx;
 	unsigned int num_tx_qs, num_rx_qs;
 	u32 *tx_queues, *rx_queues;
 	if (!np || !of_device_is_available(np))
 		return -ENODEV;
 	/* parse the num of tx and rx queues */
 	tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 	num_tx_qs = tx_queues ? *tx_queues : 1;
 	if (num_tx_qs > MAX_TX_QS) {
 		printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 				num_tx_qs, MAX_TX_QS);
 		printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
 		return -EINVAL;
 	}
 	rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 	num_rx_qs = rx_queues ? *rx_queues : 1;
 	if (num_rx_qs > MAX_RX_QS) {
 		printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 				num_tx_qs, MAX_TX_QS);
 		printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
 		return -EINVAL;
 	}
 	*pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 	dev = *pdev;
 	if (NULL == dev)
 		return -ENOMEM;
 	priv = netdev_priv(dev);
 	priv->node = ofdev->node;
 	priv->ndev = dev;
 	dev->num_tx_queues = num_tx_qs;
 	dev->real_num_tx_queues = num_tx_qs;
 	priv->num_tx_queues = num_tx_qs;
 	priv->num_rx_queues = num_rx_qs;
 	priv->num_grps = 0x0;
 	model = of_get_property(np, "model", NULL);
 	for (i = 0; i < MAXGROUPS; i++)
 		priv->gfargrp[i].regs = NULL;
 	/* Parse and initialize group specific information */
 	if (of_device_is_compatible(np, "fsl,etsec2")) {
 		priv->mode = MQ_MG_MODE;
 		for_each_child_of_node(np, child) {
 			err = gfar_parse_group(child, priv, model);
 			if (err)
 				goto err_grp_init;
 		}
 	} else {
 		priv->mode = SQ_SG_MODE;
 		err = gfar_parse_group(np, priv, model);
 		if(err)
 			goto err_grp_init;
 	}
 	for (i = 0; i < priv->num_tx_queues; i++)
 	       priv->tx_queue[i] = NULL;
 	for (i = 0; i < priv->num_rx_queues; i++)
 		priv->rx_queue[i] = NULL;
 	for (i = 0; i < priv->num_tx_queues; i++) {
 		priv->tx_queue[i] =  (struct gfar_priv_tx_q *)kmalloc(
 				sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
 		if (!priv->tx_queue[i]) {
 			err = -ENOMEM;
 			goto tx_alloc_failed;
 		}
 		priv->tx_queue[i]->tx_skbuff = NULL;
 		priv->tx_queue[i]->qindex = i;
 		priv->tx_queue[i]->dev = dev;
 		spin_lock_init(&(priv->tx_queue[i]->txlock));
 	}
 	for (i = 0; i < priv->num_rx_queues; i++) {
 		priv->rx_queue[i] = (struct gfar_priv_rx_q *)kmalloc(
 					sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
 		if (!priv->rx_queue[i]) {
 			err = -ENOMEM;
 			goto rx_alloc_failed;
 		}
 		priv->rx_queue[i]->rx_skbuff = NULL;
 		priv->rx_queue[i]->qindex = i;
 		priv->rx_queue[i]->dev = dev;
 		spin_lock_init(&(priv->rx_queue[i]->rxlock));
 	}
 	stash = of_get_property(np, "bd-stash", NULL);
 	if (stash) {
 		priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 		priv->bd_stash_en = 1;
 	}
 	stash_len = of_get_property(np, "rx-stash-len", NULL);
 	if (stash_len)
 		priv->rx_stash_size = *stash_len;
 	stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 	if (stash_idx)
 		priv->rx_stash_index = *stash_idx;
 	if (stash_len || stash_idx)
 		priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 	mac_addr = of_get_mac_address(np);
 	if (mac_addr)
 		memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 	if (model && !strcasecmp(model, "TSEC"))
 		priv->device_flags =
 			FSL_GIANFAR_DEV_HAS_GIGABIT |
 			FSL_GIANFAR_DEV_HAS_COALESCE |
 			FSL_GIANFAR_DEV_HAS_RMON |
 			FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 	if (model && !strcasecmp(model, "eTSEC"))
 		priv->device_flags =
 			FSL_GIANFAR_DEV_HAS_GIGABIT |
 			FSL_GIANFAR_DEV_HAS_COALESCE |
 			FSL_GIANFAR_DEV_HAS_RMON |
 			FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 			FSL_GIANFAR_DEV_HAS_PADDING |
 			FSL_GIANFAR_DEV_HAS_CSUM |
 			FSL_GIANFAR_DEV_HAS_VLAN |
 			FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 			FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
 	ctype = of_get_property(np, "phy-connection-type", NULL);
 	/* We only care about rgmii-id.  The rest are autodetected */
 	if (ctype && !strcmp(ctype, "rgmii-id"))
 		priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 	else
 		priv->interface = PHY_INTERFACE_MODE_MII;
 	if (of_get_property(np, "fsl,magic-packet", NULL))
 		priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 	priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 	/* Find the TBI PHY.  If it's not there, we don't support SGMII */
 	priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 	return 0;
 rx_alloc_failed:
 	free_rx_pointers(priv);
 tx_alloc_failed:
 	free_tx_pointers(priv);
 err_grp_init:
 	unmap_group_regs(priv);
 	free_netdev(dev);
 	return err;
 }
 /* Ioctl MII Interface */
 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	if (!netif_running(dev))
 		return -EINVAL;
 	if (!priv->phydev)
 		return -ENODEV;
 	return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
 }
 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 {
 	unsigned int new_bit_map = 0x0;
 	int mask = 0x1 << (max_qs - 1), i;
 	for (i = 0; i < max_qs; i++) {
 		if (bit_map & mask)
 			new_bit_map = new_bit_map + (1 << i);
 		mask = mask >> 0x1;
 	}
 	return new_bit_map;
 }
 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 				   u32 class)
 {
 	u32 rqfpr = FPR_FILER_MASK;
 	u32 rqfcr = 0x0;
 	rqfar--;
 	rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 	ftp_rqfpr[rqfar] = rqfpr;
 	ftp_rqfcr[rqfar] = rqfcr;
 	gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 	rqfar--;
 	rqfcr = RQFCR_CMP_NOMATCH;
 	ftp_rqfpr[rqfar] = rqfpr;
 	ftp_rqfcr[rqfar] = rqfcr;
 	gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 	rqfar--;
 	rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 	rqfpr = class;
 	ftp_rqfcr[rqfar] = rqfcr;
 	ftp_rqfpr[rqfar] = rqfpr;
 	gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 	rqfar--;
 	rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 	rqfpr = class;
 	ftp_rqfcr[rqfar] = rqfcr;
 	ftp_rqfpr[rqfar] = rqfpr;
 	gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 	return rqfar;
 }
 static void gfar_init_filer_table(struct gfar_private *priv)
 {
 	int i = 0x0;
 	u32 rqfar = MAX_FILER_IDX;
 	u32 rqfcr = 0x0;
 	u32 rqfpr = FPR_FILER_MASK;
 	/* Default rule */
 	rqfcr = RQFCR_CMP_MATCH;
 	ftp_rqfcr[rqfar] = rqfcr;
 	ftp_rqfpr[rqfar] = rqfpr;
 	gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 	rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 	rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 	rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 	rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 	rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 	rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 	/* cur_filer_idx indicated the fisrt non-masked rule */
 	priv->cur_filer_idx = rqfar;
 	/* Rest are masked rules */
 	rqfcr = RQFCR_CMP_NOMATCH;
 	for (i = 0; i < rqfar; i++) {
 		ftp_rqfcr[i] = rqfcr;
 		ftp_rqfpr[i] = rqfpr;
 		gfar_write_filer(priv, i, rqfcr, rqfpr);
 	}
 }
 /* Set up the ethernet device structure, private data,
  * and anything else we need before we start */
 static int gfar_probe(struct of_device *ofdev,
 		const struct of_device_id *match)
 {
 	u32 tempval;
 	struct net_device *dev = NULL;
 	struct gfar_private *priv = NULL;
 	struct gfar __iomem *regs = NULL;
 	int err = 0, i, grp_idx = 0;
 	int len_devname;
 	u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 	u32 isrg = 0;
 	u32 __iomem *baddr;
 	err = gfar_of_init(ofdev, &dev);
 	if (err)
 		return err;
 	priv = netdev_priv(dev);
 	priv->ndev = dev;
 	priv->ofdev = ofdev;
 	priv->node = ofdev->node;
 	SET_NETDEV_DEV(dev, &ofdev->dev);
 	spin_lock_init(&priv->bflock);
 	INIT_WORK(&priv->reset_task, gfar_reset_task);
 	dev_set_drvdata(&ofdev->dev, priv);
 	regs = priv->gfargrp[0].regs;
 	/* Stop the DMA engine now, in case it was running before */
 	/* (The firmware could have used it, and left it running). */
 	gfar_halt(dev);
 	/* Reset MAC layer */
 	gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
 	/* We need to delay at least 3 TX clocks */
 	udelay(2);
 	tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 	gfar_write(&regs->maccfg1, tempval);
 	/* Initialize MACCFG2. */
 	gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
 	/* Initialize ECNTRL */
 	gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
 	/* Set the dev->base_addr to the gfar reg region */
 	dev->base_addr = (unsigned long) regs;
 	SET_NETDEV_DEV(dev, &ofdev->dev);
 	/* Fill in the dev structure */
 	dev->watchdog_timeo = TX_TIMEOUT;
 	dev->mtu = 1500;
 	dev->netdev_ops = &gfar_netdev_ops;
 	dev->ethtool_ops = &gfar_ethtool_ops;
 	/* Register for napi ...We are registering NAPI for each grp */
 	for (i = 0; i < priv->num_grps; i++)
 		netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 		priv->rx_csum_enable = 1;
 		dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
 	} else
 		priv->rx_csum_enable = 0;
 	priv->vlgrp = NULL;
 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
 		dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 		priv->extended_hash = 1;
 		priv->hash_width = 9;
 		priv->hash_regs[0] = &regs->igaddr0;
 		priv->hash_regs[1] = &regs->igaddr1;
 		priv->hash_regs[2] = &regs->igaddr2;
 		priv->hash_regs[3] = &regs->igaddr3;
 		priv->hash_regs[4] = &regs->igaddr4;
 		priv->hash_regs[5] = &regs->igaddr5;
 		priv->hash_regs[6] = &regs->igaddr6;
 		priv->hash_regs[7] = &regs->igaddr7;
 		priv->hash_regs[8] = &regs->gaddr0;
 		priv->hash_regs[9] = &regs->gaddr1;
 		priv->hash_regs[10] = &regs->gaddr2;
 		priv->hash_regs[11] = &regs->gaddr3;
 		priv->hash_regs[12] = &regs->gaddr4;
 		priv->hash_regs[13] = &regs->gaddr5;
 		priv->hash_regs[14] = &regs->gaddr6;
 		priv->hash_regs[15] = &regs->gaddr7;
 	} else {
 		priv->extended_hash = 0;
 		priv->hash_width = 8;
 		priv->hash_regs[0] = &regs->gaddr0;
 		priv->hash_regs[1] = &regs->gaddr1;
 		priv->hash_regs[2] = &regs->gaddr2;
 		priv->hash_regs[3] = &regs->gaddr3;
 		priv->hash_regs[4] = &regs->gaddr4;
 		priv->hash_regs[5] = &regs->gaddr5;
 		priv->hash_regs[6] = &regs->gaddr6;
 		priv->hash_regs[7] = &regs->gaddr7;
 	}
 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 		priv->padding = DEFAULT_PADDING;
 	else
 		priv->padding = 0;
 	if (dev->features & NETIF_F_IP_CSUM)
 		dev->hard_header_len += GMAC_FCB_LEN;
 	/* Program the isrg regs only if number of grps > 1 */
 	if (priv->num_grps > 1) {
 		baddr = &regs->isrg0;
 		for (i = 0; i < priv->num_grps; i++) {
 			isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
 			isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
 			gfar_write(baddr, isrg);
 			baddr++;
 			isrg = 0x0;
 		}
 	}
 	/* Need to reverse the bit maps as  bit_map's MSB is q0
 	 * but, for_each_bit parses from right to left, which
 	 * basically reverses the queue numbers */
 	for (i = 0; i< priv->num_grps; i++) {
 		priv->gfargrp[i].tx_bit_map = reverse_bitmap(
 				priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
 		priv->gfargrp[i].rx_bit_map = reverse_bitmap(
 				priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
 	}
 	/* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 	 * also assign queues to groups */
 	for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
 		priv->gfargrp[grp_idx].num_rx_queues = 0x0;
 		for_each_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
 				priv->num_rx_queues) {
 			priv->gfargrp[grp_idx].num_rx_queues++;
 			priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
 			rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
 			rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 		}
 		priv->gfargrp[grp_idx].num_tx_queues = 0x0;
 		for_each_bit (i, &priv->gfargrp[grp_idx].tx_bit_map,
 				priv->num_tx_queues) {
 			priv->gfargrp[grp_idx].num_tx_queues++;
 			priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
 			tstat = tstat | (TSTAT_CLEAR_THALT >> i);
 			tqueue = tqueue | (TQUEUE_EN0 >> i);
 		}
 		priv->gfargrp[grp_idx].rstat = rstat;
 		priv->gfargrp[grp_idx].tstat = tstat;
 		rstat = tstat =0;
 	}
 	gfar_write(&regs->rqueue, rqueue);
 	gfar_write(&regs->tqueue, tqueue);
 	priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 	/* Initializing some of the rx/tx queue level parameters */
 	for (i = 0; i < priv->num_tx_queues; i++) {
 		priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
 		priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
 		priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
 		priv->tx_queue[i]->txic = DEFAULT_TXIC;
 	}
 	for (i = 0; i < priv->num_rx_queues; i++) {
 		priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
 		priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
 		priv->rx_queue[i]->rxic = DEFAULT_RXIC;
 	}
 	/* Enable most messages by default */
 	priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 	/* Carrier starts down, phylib will bring it up */
 	netif_carrier_off(dev);
 	err = register_netdev(dev);
 	if (err) {
 		printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 				dev->name);
 		goto register_fail;
 	}
 	device_init_wakeup(&dev->dev,
 		priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 	/* fill out IRQ number and name fields */
 	len_devname = strlen(dev->name);
 	for (i = 0; i < priv->num_grps; i++) {
 		strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
 				len_devname);
 		if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 			strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
 				"_g", sizeof("_g"));
 			priv->gfargrp[i].int_name_tx[
 				strlen(priv->gfargrp[i].int_name_tx)] = i+48;
 			strncpy(&priv->gfargrp[i].int_name_tx[strlen(
 				priv->gfargrp[i].int_name_tx)],
 				"_tx", sizeof("_tx") + 1);
 			strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
 					len_devname);
 			strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
 					"_g", sizeof("_g"));
 			priv->gfargrp[i].int_name_rx[
 				strlen(priv->gfargrp[i].int_name_rx)] = i+48;
 			strncpy(&priv->gfargrp[i].int_name_rx[strlen(
 				priv->gfargrp[i].int_name_rx)],
 				"_rx", sizeof("_rx") + 1);
 			strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
 					len_devname);
 			strncpy(&priv->gfargrp[i].int_name_er[len_devname],
 				"_g", sizeof("_g"));
 			priv->gfargrp[i].int_name_er[strlen(
 					priv->gfargrp[i].int_name_er)] = i+48;
 			strncpy(&priv->gfargrp[i].int_name_er[strlen(\
 				priv->gfargrp[i].int_name_er)],
 				"_er", sizeof("_er") + 1);
 		} else
 			priv->gfargrp[i].int_name_tx[len_devname] = '\0';
 	}
 	/* Initialize the filer table */
 	gfar_init_filer_table(priv);
 	/* Create all the sysfs files */
 	gfar_init_sysfs(dev);
 	/* Print out the device info */
 	printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
 	/* Even more device info helps when determining which kernel */
 	/* provided which set of benchmarks. */
 	printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 	for (i = 0; i < priv->num_rx_queues; i++)
 		printk(KERN_INFO "%s: :RX BD ring size for Q[%d]: %d\n",
 			dev->name, i, priv->rx_queue[i]->rx_ring_size);
 	for(i = 0; i < priv->num_tx_queues; i++)
 		 printk(KERN_INFO "%s:TX BD ring size for Q[%d]: %d\n",
 			dev->name, i, priv->tx_queue[i]->tx_ring_size);
 	return 0;
 register_fail:
 	unmap_group_regs(priv);
 	free_tx_pointers(priv);
 	free_rx_pointers(priv);
 	if (priv->phy_node)
 		of_node_put(priv->phy_node);
 	if (priv->tbi_node)
 		of_node_put(priv->tbi_node);
 	free_netdev(dev);
 	return err;
 }
 static int gfar_remove(struct of_device *ofdev)
 {
 	struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 	if (priv->phy_node)
 		of_node_put(priv->phy_node);
 	if (priv->tbi_node)
 		of_node_put(priv->tbi_node);
 	dev_set_drvdata(&ofdev->dev, NULL);
 	unregister_netdev(priv->ndev);
 	unmap_group_regs(priv);
 	free_netdev(priv->ndev);
 	return 0;
 }
 #ifdef CONFIG_PM
 static int gfar_suspend(struct device *dev)
 {
 	struct gfar_private *priv = dev_get_drvdata(dev);
 	struct net_device *ndev = priv->ndev;
 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
 	unsigned long flags;
 	u32 tempval;
 	int magic_packet = priv->wol_en &&
 		(priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 	netif_device_detach(ndev);
 	if (netif_running(ndev)) {
 		local_irq_save(flags);
 		lock_tx_qs(priv);
 		lock_rx_qs(priv);
 		gfar_halt_nodisable(ndev);
 		/* Disable Tx, and Rx if wake-on-LAN is disabled. */
 		tempval = gfar_read(&regs->maccfg1);
 		tempval &= ~MACCFG1_TX_EN;
 		if (!magic_packet)
 			tempval &= ~MACCFG1_RX_EN;
 		gfar_write(&regs->maccfg1, tempval);
 		unlock_rx_qs(priv);
 		unlock_tx_qs(priv);
 		local_irq_restore(flags);
 		disable_napi(priv);
 		if (magic_packet) {
 			/* Enable interrupt on Magic Packet */
 			gfar_write(&regs->imask, IMASK_MAG);
 			/* Enable Magic Packet mode */
 			tempval = gfar_read(&regs->maccfg2);
 			tempval |= MACCFG2_MPEN;
 			gfar_write(&regs->maccfg2, tempval);
 		} else {
 			phy_stop(priv->phydev);
 		}
 	}
 	return 0;
 }
 static int gfar_resume(struct device *dev)
 {
 	struct gfar_private *priv = dev_get_drvdata(dev);
 	struct net_device *ndev = priv->ndev;
 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
 	unsigned long flags;
 	u32 tempval;
 	int magic_packet = priv->wol_en &&
 		(priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 	if (!netif_running(ndev)) {
 		netif_device_attach(ndev);
 		return 0;
 	}
 	if (!magic_packet && priv->phydev)
 		phy_start(priv->phydev);
 	/* Disable Magic Packet mode, in case something
 	 * else woke us up.
 	 */
 	local_irq_save(flags);
 	lock_tx_qs(priv);
 	lock_rx_qs(priv);
 	tempval = gfar_read(&regs->maccfg2);
 	tempval &= ~MACCFG2_MPEN;
 	gfar_write(&regs->maccfg2, tempval);
 	gfar_start(ndev);
 	unlock_rx_qs(priv);
 	unlock_tx_qs(priv);
 	local_irq_restore(flags);
 	netif_device_attach(ndev);
 	enable_napi(priv);
 	return 0;
 }
 static int gfar_restore(struct device *dev)
 {
 	struct gfar_private *priv = dev_get_drvdata(dev);
 	struct net_device *ndev = priv->ndev;
 	if (!netif_running(ndev))
 		return 0;
 	gfar_init_bds(ndev);
 	init_registers(ndev);
 	gfar_set_mac_address(ndev);
 	gfar_init_mac(ndev);
 	gfar_start(ndev);
 	priv->oldlink = 0;
 	priv->oldspeed = 0;
 	priv->oldduplex = -1;
 	if (priv->phydev)
 		phy_start(priv->phydev);
 	netif_device_attach(ndev);
 	enable_napi(priv);
 	return 0;
 }
 static struct dev_pm_ops gfar_pm_ops = {
 	.suspend = gfar_suspend,
 	.resume = gfar_resume,
 	.freeze = gfar_suspend,
 	.thaw = gfar_resume,
 	.restore = gfar_restore,
 };
 #define GFAR_PM_OPS (&gfar_pm_ops)
 static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)
 {
 	return gfar_suspend(&ofdev->dev);
 }
 static int gfar_legacy_resume(struct of_device *ofdev)
 {
 	return gfar_resume(&ofdev->dev);
 }
 #else
 #define GFAR_PM_OPS NULL
 #define gfar_legacy_suspend NULL
 #define gfar_legacy_resume NULL
 #endif
 /* Reads the controller's registers to determine what interface
  * connects it to the PHY.
  */
 static phy_interface_t gfar_get_interface(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
 	u32 ecntrl;
 	ecntrl = gfar_read(&regs->ecntrl);
 	if (ecntrl & ECNTRL_SGMII_MODE)
 		return PHY_INTERFACE_MODE_SGMII;
 	if (ecntrl & ECNTRL_TBI_MODE) {
 		if (ecntrl & ECNTRL_REDUCED_MODE)
 			return PHY_INTERFACE_MODE_RTBI;
 		else
 			return PHY_INTERFACE_MODE_TBI;
 	}
 	if (ecntrl & ECNTRL_REDUCED_MODE) {
 		if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 			return PHY_INTERFACE_MODE_RMII;
 		else {
 			phy_interface_t interface = priv->interface;
 			/*
 			 * This isn't autodetected right now, so it must
 			 * be set by the device tree or platform code.
 			 */
 			if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 				return PHY_INTERFACE_MODE_RGMII_ID;
 			return PHY_INTERFACE_MODE_RGMII;
 		}
 	}
 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 		return PHY_INTERFACE_MODE_GMII;
 	return PHY_INTERFACE_MODE_MII;
 }
 /* Initializes driver's PHY state, and attaches to the PHY.
  * Returns 0 on success.
  */
 static int init_phy(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	uint gigabit_support =
 		priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 		SUPPORTED_1000baseT_Full : 0;
 	phy_interface_t interface;
 	priv->oldlink = 0;
 	priv->oldspeed = 0;
 	priv->oldduplex = -1;
 	interface = gfar_get_interface(dev);
 	priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
 				      interface);
 	if (!priv->phydev)
 		priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
 							 interface);
 	if (!priv->phydev) {
 		dev_err(&dev->dev, "could not attach to PHY\n");
 		return -ENODEV;
 	}
 	if (interface == PHY_INTERFACE_MODE_SGMII)
 		gfar_configure_serdes(dev);
 	/* Remove any features not supported by the controller */
 	priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 	priv->phydev->advertising = priv->phydev->supported;
 	return 0;
 }
 /*
  * Initialize TBI PHY interface for communicating with the
  * SERDES lynx PHY on the chip.  We communicate with this PHY
  * through the MDIO bus on each controller, treating it as a
  * "normal" PHY at the address found in the TBIPA register.  We assume
  * that the TBIPA register is valid.  Either the MDIO bus code will set
  * it to a value that doesn't conflict with other PHYs on the bus, or the
  * value doesn't matter, as there are no other PHYs on the bus.
  */
 static void gfar_configure_serdes(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct phy_device *tbiphy;
 	if (!priv->tbi_node) {
 		dev_warn(&dev->dev, "error: SGMII mode requires that the "
 				    "device tree specify a tbi-handle\n");
 		return;
 	}
 	tbiphy = of_phy_find_device(priv->tbi_node);
 	if (!tbiphy) {
 		dev_err(&dev->dev, "error: Could not get TBI device\n");
 		return;
 	}
 	/*
 	 * If the link is already up, we must already be ok, and don't need to
 	 * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
 	 * everything for us?  Resetting it takes the link down and requires
 	 * several seconds for it to come back.
 	 */
 	if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
 		return;
 	/* Single clk mode, mii mode off(for serdes communication) */
 	phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
 	phy_write(tbiphy, MII_ADVERTISE,
 			ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 			ADVERTISE_1000XPSE_ASYM);
 	phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
 			BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 }
 static void init_registers(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar __iomem *regs = NULL;
 	int i = 0;
 	for (i = 0; i < priv->num_grps; i++) {
 		regs = priv->gfargrp[i].regs;
 		/* Clear IEVENT */
 		gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 		/* Initialize IMASK */
 		gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 	}
 	regs = priv->gfargrp[0].regs;
 	/* Init hash registers to zero */
 	gfar_write(&regs->igaddr0, 0);
 	gfar_write(&regs->igaddr1, 0);
 	gfar_write(&regs->igaddr2, 0);
 	gfar_write(&regs->igaddr3, 0);
 	gfar_write(&regs->igaddr4, 0);
 	gfar_write(&regs->igaddr5, 0);
 	gfar_write(&regs->igaddr6, 0);
 	gfar_write(&regs->igaddr7, 0);
 	gfar_write(&regs->gaddr0, 0);
 	gfar_write(&regs->gaddr1, 0);
 	gfar_write(&regs->gaddr2, 0);
 	gfar_write(&regs->gaddr3, 0);
 	gfar_write(&regs->gaddr4, 0);
 	gfar_write(&regs->gaddr5, 0);
 	gfar_write(&regs->gaddr6, 0);
 	gfar_write(&regs->gaddr7, 0);
 	/* Zero out the rmon mib registers if it has them */
 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 		memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
 		/* Mask off the CAM interrupts */
 		gfar_write(&regs->rmon.cam1, 0xffffffff);
 		gfar_write(&regs->rmon.cam2, 0xffffffff);
 	}
 	/* Initialize the max receive buffer length */
 	gfar_write(&regs->mrblr, priv->rx_buffer_size);
 	/* Initialize the Minimum Frame Length Register */
 	gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
 }
 /* Halt the receive and transmit queues */
 static void gfar_halt_nodisable(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar __iomem *regs = NULL;
 	u32 tempval;
 	int i = 0;
 	for (i = 0; i < priv->num_grps; i++) {
 		regs = priv->gfargrp[i].regs;
 		/* Mask all interrupts */
 		gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 		/* Clear all interrupts */
 		gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 	}
 	regs = priv->gfargrp[0].regs;
 	/* Stop the DMA, and wait for it to stop */
 	tempval = gfar_read(&regs->dmactrl);
 	if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 	    != (DMACTRL_GRS | DMACTRL_GTS)) {
 		tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 		gfar_write(&regs->dmactrl, tempval);
 		while (!(gfar_read(&regs->ievent) &
 			 (IEVENT_GRSC | IEVENT_GTSC)))
 			cpu_relax();
 	}
 }
 /* Halt the receive and transmit queues */
 void gfar_halt(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
 	u32 tempval;
 	gfar_halt_nodisable(dev);
 	/* Disable Rx and Tx */
 	tempval = gfar_read(&regs->maccfg1);
 	tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 	gfar_write(&regs->maccfg1, tempval);
 }
 static void free_grp_irqs(struct gfar_priv_grp *grp)
 {
 	free_irq(grp->interruptError, grp);
 	free_irq(grp->interruptTransmit, grp);
 	free_irq(grp->interruptReceive, grp);
 }
 void stop_gfar(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	unsigned long flags;
 	int i;
 	phy_stop(priv->phydev);
 	/* Lock it down */
 	local_irq_save(flags);
 	lock_tx_qs(priv);
 	lock_rx_qs(priv);
 	gfar_halt(dev);
 	unlock_rx_qs(priv);
 	unlock_tx_qs(priv);
 	local_irq_restore(flags);
 	/* Free the IRQs */
 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 		for (i = 0; i < priv->num_grps; i++)
 			free_grp_irqs(&priv->gfargrp[i]);
 	} else {
 		for (i = 0; i < priv->num_grps; i++)
 			free_irq(priv->gfargrp[i].interruptTransmit,
 					&priv->gfargrp[i]);
 	}
 	free_skb_resources(priv);
 }
 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
 {
 	struct txbd8 *txbdp;
 	struct gfar_private *priv = netdev_priv(tx_queue->dev);
 	int i, j;
 	txbdp = tx_queue->tx_bd_base;
 	for (i = 0; i < tx_queue->tx_ring_size; i++) {
 		if (!tx_queue->tx_skbuff[i])
 			continue;
 		dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
 				txbdp->length, DMA_TO_DEVICE);
 		txbdp->lstatus = 0;
 		for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
 				j++) {
 			txbdp++;
 			dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
 					txbdp->length, DMA_TO_DEVICE);
 		}
 		txbdp++;
 		dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
 		tx_queue->tx_skbuff[i] = NULL;
 	}
 	kfree(tx_queue->tx_skbuff);
 }
 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
 {
 	struct rxbd8 *rxbdp;
 	struct gfar_private *priv = netdev_priv(rx_queue->dev);
 	int i;
 	rxbdp = rx_queue->rx_bd_base;
 	for (i = 0; i < rx_queue->rx_ring_size; i++) {
 		if (rx_queue->rx_skbuff[i]) {
 			dma_unmap_single(&priv->ofdev->dev,
 					rxbdp->bufPtr, priv->rx_buffer_size,
 					DMA_FROM_DEVICE);
 			dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
 			rx_queue->rx_skbuff[i] = NULL;
 		}
 		rxbdp->lstatus = 0;
 		rxbdp->bufPtr = 0;
 		rxbdp++;
 	}
 	kfree(rx_queue->rx_skbuff);
 }
 /* If there are any tx skbs or rx skbs still around, free them.
  * Then free tx_skbuff and rx_skbuff */
 static void free_skb_resources(struct gfar_private *priv)
 {
 	struct gfar_priv_tx_q *tx_queue = NULL;
 	struct gfar_priv_rx_q *rx_queue = NULL;
 	int i;
 	/* Go through all the buffer descriptors and free their data buffers */
 	for (i = 0; i < priv->num_tx_queues; i++) {
 		tx_queue = priv->tx_queue[i];
 		if(!tx_queue->tx_skbuff)
 			free_skb_tx_queue(tx_queue);
 	}
 	for (i = 0; i < priv->num_rx_queues; i++) {
 		rx_queue = priv->rx_queue[i];
 		if(!rx_queue->rx_skbuff)
 			free_skb_rx_queue(rx_queue);
 	}
 	dma_free_coherent(&priv->ofdev->dev,
 			sizeof(struct txbd8) * priv->total_tx_ring_size +
 			sizeof(struct rxbd8) * priv->total_rx_ring_size,
 			priv->tx_queue[0]->tx_bd_base,
 			priv->tx_queue[0]->tx_bd_dma_base);
 }
 void gfar_start(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
 	u32 tempval;
 	int i = 0;
 	/* Enable Rx and Tx in MACCFG1 */
 	tempval = gfar_read(&regs->maccfg1);
 	tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 	gfar_write(&regs->maccfg1, tempval);
 	/* Initialize DMACTRL to have WWR and WOP */
 	tempval = gfar_read(&regs->dmactrl);
 	tempval |= DMACTRL_INIT_SETTINGS;
 	gfar_write(&regs->dmactrl, tempval);
 	/* Make sure we aren't stopped */
 	tempval = gfar_read(&regs->dmactrl);
 	tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 	gfar_write(&regs->dmactrl, tempval);
 	for (i = 0; i < priv->num_grps; i++) {
 		regs = priv->gfargrp[i].regs;
 		/* Clear THLT/RHLT, so that the DMA starts polling now */
 		gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
 		gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
 		/* Unmask the interrupts we look for */
 		gfar_write(&regs->imask, IMASK_DEFAULT);
 	}
 	dev->trans_start = jiffies;
 }
 void gfar_configure_coalescing(struct gfar_private *priv,
 	unsigned long tx_mask, unsigned long rx_mask)
 {
 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
 	u32 __iomem *baddr;
 	int i = 0;
 	/* Backward compatible case ---- even if we enable
 	 * multiple queues, there's only single reg to program
 	 */
 	gfar_write(&regs->txic, 0);
 	if(likely(priv->tx_queue[0]->txcoalescing))
 		gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 	gfar_write(&regs->rxic, 0);
 	if(unlikely(priv->rx_queue[0]->rxcoalescing))
 		gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 	if (priv->mode == MQ_MG_MODE) {
 		baddr = &regs->txic0;
 		for_each_bit (i, &tx_mask, priv->num_tx_queues) {
 			if (likely(priv->tx_queue[i]->txcoalescing)) {
 				gfar_write(baddr + i, 0);
 				gfar_write(baddr + i, priv->tx_queue[i]->txic);
 			}
 		}
 		baddr = &regs->rxic0;
 		for_each_bit (i, &rx_mask, priv->num_rx_queues) {
 			if (likely(priv->rx_queue[i]->rxcoalescing)) {
 				gfar_write(baddr + i, 0);
 				gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 			}
 		}
 	}
 }
 static int register_grp_irqs(struct gfar_priv_grp *grp)
 {
 	struct gfar_private *priv = grp->priv;
 	struct net_device *dev = priv->ndev;
 	int err;
 	/* If the device has multiple interrupts, register for
 	 * them.  Otherwise, only register for the one */
 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 		/* Install our interrupt handlers for Error,
 		 * Transmit, and Receive */
 		if ((err = request_irq(grp->interruptError, gfar_error, 0,
 				grp->int_name_er,grp)) < 0) {
 			if (netif_msg_intr(priv))
 				printk(KERN_ERR "%s: Can't get IRQ %d\n",
 					dev->name, grp->interruptError);
 				goto err_irq_fail;
 		}
 		if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
 				0, grp->int_name_tx, grp)) < 0) {
 			if (netif_msg_intr(priv))
 				printk(KERN_ERR "%s: Can't get IRQ %d\n",
 					dev->name, grp->interruptTransmit);
 			goto tx_irq_fail;
 		}
 		if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
 				grp->int_name_rx, grp)) < 0) {
 			if (netif_msg_intr(priv))
 				printk(KERN_ERR "%s: Can't get IRQ %d\n",
 					dev->name, grp->interruptReceive);
 			goto rx_irq_fail;
 		}
 	} else {
 		if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
 				grp->int_name_tx, grp)) < 0) {
 			if (netif_msg_intr(priv))
 				printk(KERN_ERR "%s: Can't get IRQ %d\n",
 					dev->name, grp->interruptTransmit);
 			goto err_irq_fail;
 		}
 	}
 	return 0;
 rx_irq_fail:
 	free_irq(grp->interruptTransmit, grp);
 tx_irq_fail:
 	free_irq(grp->interruptError, grp);
 err_irq_fail:
 	return err;
 }
 /* Bring the controller up and running */
 int startup_gfar(struct net_device *ndev)
 {
 	struct gfar_private *priv = netdev_priv(ndev);
 	struct gfar __iomem *regs = NULL;
 	int err, i, j;
 	for (i = 0; i < priv->num_grps; i++) {
 		regs= priv->gfargrp[i].regs;
 		gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 	}
 	regs= priv->gfargrp[0].regs;
 	err = gfar_alloc_skb_resources(ndev);
 	if (err)
 		return err;
 	gfar_init_mac(ndev);
 	for (i = 0; i < priv->num_grps; i++) {
 		err = register_grp_irqs(&priv->gfargrp[i]);
 		if (err) {
 			for (j = 0; j < i; j++)
 				free_grp_irqs(&priv->gfargrp[j]);
 				goto irq_fail;
 		}
 	}
 	/* Start the controller */
 	gfar_start(ndev);
 	phy_start(priv->phydev);
 	gfar_configure_coalescing(priv, 0xFF, 0xFF);
 	return 0;
 irq_fail:
 	free_skb_resources(priv);
 	return err;
 }
 /* Called when something needs to use the ethernet device */
 /* Returns 0 for success. */
 static int gfar_enet_open(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	int err;
 	enable_napi(priv);
 	skb_queue_head_init(&priv->rx_recycle);
 	/* Initialize a bunch of registers */
 	init_registers(dev);
 	gfar_set_mac_address(dev);
 	err = init_phy(dev);
 	if (err) {
 		disable_napi(priv);
 		return err;
 	}
 	err = startup_gfar(dev);
 	if (err) {
 		disable_napi(priv);
 		return err;
 	}
 	netif_tx_start_all_queues(dev);
 	device_set_wakeup_enable(&dev->dev, priv->wol_en);
 	return err;
 }
 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
 {
 	struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
 	memset(fcb, 0, GMAC_FCB_LEN);
 	return fcb;
 }
 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
 {
 	u8 flags = 0;
 	/* If we're here, it's a IP packet with a TCP or UDP
 	 * payload.  We set it to checksum, using a pseudo-header
 	 * we provide
 	 */
 	flags = TXFCB_DEFAULT;
 	/* Tell the controller what the protocol is */
 	/* And provide the already calculated phcs */
 	if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
 		flags |= TXFCB_UDP;
 		fcb->phcs = udp_hdr(skb)->check;
 	} else
 		fcb->phcs = tcp_hdr(skb)->check;
 	/* l3os is the distance between the start of the
 	 * frame (skb->data) and the start of the IP hdr.
 	 * l4os is the distance between the start of the
 	 * l3 hdr and the l4 hdr */
 	fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
 	fcb->l4os = skb_network_header_len(skb);
 	fcb->flags = flags;
 }
 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
 {
 	fcb->flags |= TXFCB_VLN;
 	fcb->vlctl = vlan_tx_tag_get(skb);
 }
 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
 			       struct txbd8 *base, int ring_size)
 {
 	struct txbd8 *new_bd = bdp + stride;
 	return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
 }
 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
 		int ring_size)
 {
 	return skip_txbd(bdp, 1, base, ring_size);
 }
 /* This is called by the kernel when a frame is ready for transmission. */
 /* It is pointed to by the dev->hard_start_xmit function pointer */
 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar_priv_tx_q *tx_queue = NULL;
 	struct netdev_queue *txq;
 	struct gfar __iomem *regs = NULL;
 	struct txfcb *fcb = NULL;
 	struct txbd8 *txbdp, *txbdp_start, *base;
 	u32 lstatus;
 	int i, rq = 0;
 	u32 bufaddr;
 	unsigned long flags;
 	unsigned int nr_frags, length;
 	rq = skb->queue_mapping;
 	tx_queue = priv->tx_queue[rq];
 	txq = netdev_get_tx_queue(dev, rq);
 	base = tx_queue->tx_bd_base;
 	regs = tx_queue->grp->regs;
 	/* make space for additional header when fcb is needed */
 	if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
 			(priv->vlgrp && vlan_tx_tag_present(skb))) &&
 			(skb_headroom(skb) < GMAC_FCB_LEN)) {
 		struct sk_buff *skb_new;
 		skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
 		if (!skb_new) {
 			dev->stats.tx_errors++;
 			kfree_skb(skb);
 			return NETDEV_TX_OK;
 		}
 		kfree_skb(skb);
 		skb = skb_new;
 	}
 	/* total number of fragments in the SKB */
 	nr_frags = skb_shinfo(skb)->nr_frags;
-	spin_lock_irqsave(&tx_queue->txlock, flags);
 	/* check if there is space to queue this packet */
 	if ((nr_frags+1) > tx_queue->num_txbdfree) {
 		/* no space, stop the queue */
 		netif_tx_stop_queue(txq);
 		dev->stats.tx_fifo_errors++;
-		spin_unlock_irqrestore(&tx_queue->txlock, flags);
 		return NETDEV_TX_BUSY;
 	}
 	/* Update transmit stats */
 	dev->stats.tx_bytes += skb->len;
 	txbdp = txbdp_start = tx_queue->cur_tx;
 	if (nr_frags == 0) {
 		lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
 	} else {
 		/* Place the fragment addresses and lengths into the TxBDs */
 		for (i = 0; i < nr_frags; i++) {
 			/* Point at the next BD, wrapping as needed */
 			txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
 			length = skb_shinfo(skb)->frags[i].size;
 			lstatus = txbdp->lstatus | length |
 				BD_LFLAG(TXBD_READY);
 			/* Handle the last BD specially */
 			if (i == nr_frags - 1)
 				lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
 			bufaddr = dma_map_page(&priv->ofdev->dev,
 					skb_shinfo(skb)->frags[i].page,
 					skb_shinfo(skb)->frags[i].page_offset,
 					length,
 					DMA_TO_DEVICE);
 			/* set the TxBD length and buffer pointer */
 			txbdp->bufPtr = bufaddr;
 			txbdp->lstatus = lstatus;
 		}
 		lstatus = txbdp_start->lstatus;
 	}
 	/* Set up checksumming */
 	if (CHECKSUM_PARTIAL == skb->ip_summed) {
 		fcb = gfar_add_fcb(skb);
 		lstatus |= BD_LFLAG(TXBD_TOE);
 		gfar_tx_checksum(skb, fcb);
 	}
 	if (priv->vlgrp && vlan_tx_tag_present(skb)) {
 		if (unlikely(NULL == fcb)) {
 			fcb = gfar_add_fcb(skb);
 			lstatus |= BD_LFLAG(TXBD_TOE);
 		}
 		gfar_tx_vlan(skb, fcb);
 	}
 	/* setup the TxBD length and buffer pointer for the first BD */
 	tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
 	txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
 			skb_headlen(skb), DMA_TO_DEVICE);
 	lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
 	/*
+	 * We can work in parallel with gfar_clean_tx_ring(), except
+	 * when modifying num_txbdfree. Note that we didn't grab the lock
+	 * when we were reading the num_txbdfree and checking for available
+	 * space, that's because outside of this function it can only grow,
+	 * and once we've got needed space, it cannot suddenly disappear.
+	 *
+	 * The lock also protects us from gfar_error(), which can modify
+	 * regs->tstat and thus retrigger the transfers, which is why we
+	 * also must grab the lock before setting ready bit for the first
+	 * to be transmitted BD.
+	 */
+	spin_lock_irqsave(&tx_queue->txlock, flags);
+	/*
 	 * The powerpc-specific eieio() is used, as wmb() has too strong
 	 * semantics (it requires synchronization between cacheable and
 	 * uncacheable mappings, which eieio doesn't provide and which we
 	 * don't need), thus requiring a more expensive sync instruction.  At
 	 * some point, the set of architecture-independent barrier functions
 	 * should be expanded to include weaker barriers.
 	 */
 	eieio();
 	txbdp_start->lstatus = lstatus;
 	/* Update the current skb pointer to the next entry we will use
 	 * (wrapping if necessary) */
 	tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
 		TX_RING_MOD_MASK(tx_queue->tx_ring_size);
 	tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
 	/* reduce TxBD free count */
 	tx_queue->num_txbdfree -= (nr_frags + 1);
 	dev->trans_start = jiffies;
 	/* If the next BD still needs to be cleaned up, then the bds
 	   are full.  We need to tell the kernel to stop sending us stuff. */
 	if (!tx_queue->num_txbdfree) {
 		netif_tx_stop_queue(txq);
 		dev->stats.tx_fifo_errors++;
 	}
 	/* Tell the DMA to go go go */
 	gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
 	/* Unlock priv */
 	spin_unlock_irqrestore(&tx_queue->txlock, flags);
 	return NETDEV_TX_OK;
 }
 /* Stops the kernel queue, and halts the controller */
 static int gfar_close(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	disable_napi(priv);
 	skb_queue_purge(&priv->rx_recycle);
 	cancel_work_sync(&priv->reset_task);
 	stop_gfar(dev);
 	/* Disconnect from the PHY */
 	phy_disconnect(priv->phydev);
 	priv->phydev = NULL;
 	netif_tx_stop_all_queues(dev);
 	return 0;
 }
 /* Changes the mac address if the controller is not running. */
 static int gfar_set_mac_address(struct net_device *dev)
 {
 	gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 	return 0;
 }
 /* Enables and disables VLAN insertion/extraction */
 static void gfar_vlan_rx_register(struct net_device *dev,
 		struct vlan_group *grp)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar __iomem *regs = NULL;
 	unsigned long flags;
 	u32 tempval;
 	regs = priv->gfargrp[0].regs;
 	local_irq_save(flags);
 	lock_rx_qs(priv);
 	priv->vlgrp = grp;
 	if (grp) {
 		/* Enable VLAN tag insertion */
 		tempval = gfar_read(&regs->tctrl);
 		tempval |= TCTRL_VLINS;
 		gfar_write(&regs->tctrl, tempval);
 		/* Enable VLAN tag extraction */
 		tempval = gfar_read(&regs->rctrl);
 		tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
 		gfar_write(&regs->rctrl, tempval);
 	} else {
 		/* Disable VLAN tag insertion */
 		tempval = gfar_read(&regs->tctrl);
 		tempval &= ~TCTRL_VLINS;
 		gfar_write(&regs->tctrl, tempval);
 		/* Disable VLAN tag extraction */
 		tempval = gfar_read(&regs->rctrl);
 		tempval &= ~RCTRL_VLEX;
 		/* If parse is no longer required, then disable parser */
 		if (tempval & RCTRL_REQ_PARSER)
 			tempval |= RCTRL_PRSDEP_INIT;
 		else
 			tempval &= ~RCTRL_PRSDEP_INIT;
 		gfar_write(&regs->rctrl, tempval);
 	}
 	gfar_change_mtu(dev, dev->mtu);
 	unlock_rx_qs(priv);
 	local_irq_restore(flags);
 }
 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
 {
 	int tempsize, tempval;
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
 	int oldsize = priv->rx_buffer_size;
 	int frame_size = new_mtu + ETH_HLEN;
 	if (priv->vlgrp)
 		frame_size += VLAN_HLEN;
 	if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
 		if (netif_msg_drv(priv))
 			printk(KERN_ERR "%s: Invalid MTU setting\n",
 					dev->name);
 		return -EINVAL;
 	}
 	if (gfar_uses_fcb(priv))
 		frame_size += GMAC_FCB_LEN;
 	frame_size += priv->padding;
 	tempsize =
 	    (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
 	    INCREMENTAL_BUFFER_SIZE;
 	/* Only stop and start the controller if it isn't already
 	 * stopped, and we changed something */
 	if ((oldsize != tempsize) && (dev->flags & IFF_UP))
 		stop_gfar(dev);
 	priv->rx_buffer_size = tempsize;
 	dev->mtu = new_mtu;
 	gfar_write(&regs->mrblr, priv->rx_buffer_size);
 	gfar_write(&regs->maxfrm, priv->rx_buffer_size);
 	/* If the mtu is larger than the max size for standard
 	 * ethernet frames (ie, a jumbo frame), then set maccfg2
 	 * to allow huge frames, and to check the length */
 	tempval = gfar_read(&regs->maccfg2);
 	if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
 		tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
 	else
 		tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
 	gfar_write(&regs->maccfg2, tempval);
 	if ((oldsize != tempsize) && (dev->flags & IFF_UP))
 		startup_gfar(dev);
 	return 0;
 }
 /* gfar_reset_task gets scheduled when a packet has not been
  * transmitted after a set amount of time.
  * For now, assume that clearing out all the structures, and
  * starting over will fix the problem.
  */
 static void gfar_reset_task(struct work_struct *work)
 {
 	struct gfar_private *priv = container_of(work, struct gfar_private,
 			reset_task);
 	struct net_device *dev = priv->ndev;
 	if (dev->flags & IFF_UP) {
 		netif_tx_stop_all_queues(dev);
 		stop_gfar(dev);
 		startup_gfar(dev);
 		netif_tx_start_all_queues(dev);
 	}
 	netif_tx_schedule_all(dev);
 }
 static void gfar_timeout(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	dev->stats.tx_errors++;
 	schedule_work(&priv->reset_task);
 }
 /* Interrupt Handler for Transmit complete */
 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
 {
 	struct net_device *dev = tx_queue->dev;
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar_priv_rx_q *rx_queue = NULL;
 	struct txbd8 *bdp;
 	struct txbd8 *lbdp = NULL;
 	struct txbd8 *base = tx_queue->tx_bd_base;
 	struct sk_buff *skb;
 	int skb_dirtytx;
 	int tx_ring_size = tx_queue->tx_ring_size;
 	int frags = 0;
 	int i;
 	int howmany = 0;
 	u32 lstatus;
 	rx_queue = priv->rx_queue[tx_queue->qindex];
 	bdp = tx_queue->dirty_tx;
 	skb_dirtytx = tx_queue->skb_dirtytx;
 	while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
+		unsigned long flags;
 		frags = skb_shinfo(skb)->nr_frags;
 		lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
 		lstatus = lbdp->lstatus;
 		/* Only clean completed frames */
 		if ((lstatus & BD_LFLAG(TXBD_READY)) &&
 				(lstatus & BD_LENGTH_MASK))
 			break;
 		dma_unmap_single(&priv->ofdev->dev,
 				bdp->bufPtr,
 				bdp->length,
 				DMA_TO_DEVICE);
 		bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
 		bdp = next_txbd(bdp, base, tx_ring_size);
 		for (i = 0; i < frags; i++) {
 			dma_unmap_page(&priv->ofdev->dev,
 					bdp->bufPtr,
 					bdp->length,
 					DMA_TO_DEVICE);
 			bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
 			bdp = next_txbd(bdp, base, tx_ring_size);
 		}
 		/*
 		 * If there's room in the queue (limit it to rx_buffer_size)
 		 * we add this skb back into the pool, if it's the right size
 		 */
 		if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
 				skb_recycle_check(skb, priv->rx_buffer_size +
 					RXBUF_ALIGNMENT))
 			__skb_queue_head(&priv->rx_recycle, skb);
 		else
 			dev_kfree_skb_any(skb);
 		tx_queue->tx_skbuff[skb_dirtytx] = NULL;
 		skb_dirtytx = (skb_dirtytx + 1) &
 			TX_RING_MOD_MASK(tx_ring_size);
 		howmany++;
+		spin_lock_irqsave(&tx_queue->txlock, flags);
 		tx_queue->num_txbdfree += frags + 1;
+		spin_unlock_irqrestore(&tx_queue->txlock, flags);
 	}
 	/* If we freed a buffer, we can restart transmission, if necessary */
 	if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
 		netif_wake_subqueue(dev, tx_queue->qindex);
 	/* Update dirty indicators */
 	tx_queue->skb_dirtytx = skb_dirtytx;
 	tx_queue->dirty_tx = bdp;
 	dev->stats.tx_packets += howmany;
 	return howmany;
 }
 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
 {
 	unsigned long flags;
 	spin_lock_irqsave(&gfargrp->grplock, flags);
 	if (napi_schedule_prep(&gfargrp->napi)) {
 		gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
 		__napi_schedule(&gfargrp->napi);
 	} else {
 		/*
 		 * Clear IEVENT, so interrupts aren't called again
 		 * because of the packets that have already arrived.
 		 */
 		gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
 	}
 	spin_unlock_irqrestore(&gfargrp->grplock, flags);
 }
 /* Interrupt Handler for Transmit complete */
 static irqreturn_t gfar_transmit(int irq, void *grp_id)
 {
 	gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
 	return IRQ_HANDLED;
 }
 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 		struct sk_buff *skb)
 {
 	struct net_device *dev = rx_queue->dev;
 	struct gfar_private *priv = netdev_priv(dev);
 	dma_addr_t buf;
 	buf = dma_map_single(&priv->ofdev->dev, skb->data,
 			     priv->rx_buffer_size, DMA_FROM_DEVICE);
 	gfar_init_rxbdp(rx_queue, bdp, buf);
 }
 struct sk_buff * gfar_new_skb(struct net_device *dev)
 {
 	unsigned int alignamount;
 	struct gfar_private *priv = netdev_priv(dev);
 	struct sk_buff *skb = NULL;
 	skb = __skb_dequeue(&priv->rx_recycle);
 	if (!skb)
 		skb = netdev_alloc_skb(dev,
 				priv->rx_buffer_size + RXBUF_ALIGNMENT);
 	if (!skb)
 		return NULL;
 	alignamount = RXBUF_ALIGNMENT -
 		(((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
 	/* We need the data buffer to be aligned properly.  We will reserve
 	 * as many bytes as needed to align the data properly
 	 */
 	skb_reserve(skb, alignamount);
 	return skb;
 }
 static inline void count_errors(unsigned short status, struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct net_device_stats *stats = &dev->stats;
 	struct gfar_extra_stats *estats = &priv->extra_stats;
 	/* If the packet was truncated, none of the other errors
 	 * matter */
 	if (status & RXBD_TRUNCATED) {
 		stats->rx_length_errors++;
 		estats->rx_trunc++;
 		return;
 	}
 	/* Count the errors, if there were any */
 	if (status & (RXBD_LARGE | RXBD_SHORT)) {
 		stats->rx_length_errors++;
 		if (status & RXBD_LARGE)
 			estats->rx_large++;
 		else
 			estats->rx_short++;
 	}
 	if (status & RXBD_NONOCTET) {
 		stats->rx_frame_errors++;
 		estats->rx_nonoctet++;
 	}
 	if (status & RXBD_CRCERR) {
 		estats->rx_crcerr++;
 		stats->rx_crc_errors++;
 	}
 	if (status & RXBD_OVERRUN) {
 		estats->rx_overrun++;
 		stats->rx_crc_errors++;
 	}
 }
 irqreturn_t gfar_receive(int irq, void *grp_id)
 {
 	gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
 	return IRQ_HANDLED;
 }
 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
 {
 	/* If valid headers were found, and valid sums
 	 * were verified, then we tell the kernel that no
 	 * checksumming is necessary.  Otherwise, it is */
 	if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
 		skb->ip_summed = CHECKSUM_UNNECESSARY;
 	else
 		skb->ip_summed = CHECKSUM_NONE;
 }
 /* gfar_process_frame() -- handle one incoming packet if skb
  * isn't NULL.  */
 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 			      int amount_pull)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct rxfcb *fcb = NULL;
 	int ret;
 	/* fcb is at the beginning if exists */
 	fcb = (struct rxfcb *)skb->data;
 	/* Remove the FCB from the skb */
 	skb_set_queue_mapping(skb, fcb->rq);
 	/* Remove the padded bytes, if there are any */
 	if (amount_pull)
 		skb_pull(skb, amount_pull);
 	if (priv->rx_csum_enable)
 		gfar_rx_checksum(skb, fcb);
 	/* Tell the skb what kind of packet this is */
 	skb->protocol = eth_type_trans(skb, dev);
 	/* Send the packet up the stack */
 	if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
 		ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
 	else
 		ret = netif_receive_skb(skb);
 	if (NET_RX_DROP == ret)
 		priv->extra_stats.kernel_dropped++;
 	return 0;
 }
 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
  *   until the budget/quota has been reached. Returns the number
  *   of frames handled
  */
 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
 {
 	struct net_device *dev = rx_queue->dev;
 	struct rxbd8 *bdp, *base;
 	struct sk_buff *skb;
 	int pkt_len;
 	int amount_pull;
 	int howmany = 0;
 	struct gfar_private *priv = netdev_priv(dev);
 	/* Get the first full descriptor */
 	bdp = rx_queue->cur_rx;
 	base = rx_queue->rx_bd_base;
 	amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
 		priv->padding;
 	while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
 		struct sk_buff *newskb;
 		rmb();
 		/* Add another skb for the future */
 		newskb = gfar_new_skb(dev);
 		skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
 		dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
 				priv->rx_buffer_size, DMA_FROM_DEVICE);
 		/* We drop the frame if we failed to allocate a new buffer */
 		if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
 				 bdp->status & RXBD_ERR)) {
 			count_errors(bdp->status, dev);
 			if (unlikely(!newskb))
 				newskb = skb;
 			else if (skb) {
 				/*
 				 * We need to reset ->data to what it
 				 * was before gfar_new_skb() re-aligned
 				 * it to an RXBUF_ALIGNMENT boundary
 				 * before we put the skb back on the
 				 * recycle list.
 				 */
 				skb->data = skb->head + NET_SKB_PAD;
 				__skb_queue_head(&priv->rx_recycle, skb);
 			}
 		} else {
 			/* Increment the number of packets */
 			dev->stats.rx_packets++;
 			howmany++;
 			if (likely(skb)) {
 				pkt_len = bdp->length - ETH_FCS_LEN;
 				/* Remove the FCS from the packet length */
 				skb_put(skb, pkt_len);
 				dev->stats.rx_bytes += pkt_len;
 				gfar_process_frame(dev, skb, amount_pull);
 			} else {
 				if (netif_msg_rx_err(priv))
 					printk(KERN_WARNING
 					       "%s: Missing skb!\n", dev->name);
 				dev->stats.rx_dropped++;
 				priv->extra_stats.rx_skbmissing++;
 			}
 		}
 		rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
 		/* Setup the new bdp */
 		gfar_new_rxbdp(rx_queue, bdp, newskb);
 		/* Update to the next pointer */
 		bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
 		/* update to point at the next skb */
 		rx_queue->skb_currx =
 		    (rx_queue->skb_currx + 1) &
 		    RX_RING_MOD_MASK(rx_queue->rx_ring_size);
 	}
 	/* Update the current rxbd pointer to be the next one */
 	rx_queue->cur_rx = bdp;
 	return howmany;
 }
 static int gfar_poll(struct napi_struct *napi, int budget)
 {
 	struct gfar_priv_grp *gfargrp = container_of(napi,
 			struct gfar_priv_grp, napi);
 	struct gfar_private *priv = gfargrp->priv;
 	struct gfar __iomem *regs = gfargrp->regs;
 	struct gfar_priv_tx_q *tx_queue = NULL;
 	struct gfar_priv_rx_q *rx_queue = NULL;
 	int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
 	int tx_cleaned = 0, i, left_over_budget = budget;
 	unsigned long serviced_queues = 0;
 	int num_queues = 0;
-	unsigned long flags;
 	num_queues = gfargrp->num_rx_queues;
 	budget_per_queue = budget/num_queues;
 	/* Clear IEVENT, so interrupts aren't called again
 	 * because of the packets that have already arrived */
 	gfar_write(&regs->ievent, IEVENT_RTX_MASK);
 	while (num_queues && left_over_budget) {
 		budget_per_queue = left_over_budget/num_queues;
 		left_over_budget = 0;
 		for_each_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
 			if (test_bit(i, &serviced_queues))
 				continue;
 			rx_queue = priv->rx_queue[i];
 			tx_queue = priv->tx_queue[rx_queue->qindex];
-			/* If we fail to get the lock,
+			tx_cleaned += gfar_clean_tx_ring(tx_queue);
-			 * don't bother with the TX BDs */
-			if (spin_trylock_irqsave(&tx_queue->txlock, flags)) {
-				tx_cleaned += gfar_clean_tx_ring(tx_queue);
-				spin_unlock_irqrestore(&tx_queue->txlock,
-							flags);
-			}
 			rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
 							budget_per_queue);
 			rx_cleaned += rx_cleaned_per_queue;
 			if(rx_cleaned_per_queue < budget_per_queue) {
 				left_over_budget = left_over_budget +
 					(budget_per_queue - rx_cleaned_per_queue);
 				set_bit(i, &serviced_queues);
 				num_queues--;
 			}
 		}
 	}
 	if (tx_cleaned)
 		return budget;
 	if (rx_cleaned < budget) {
 		napi_complete(napi);
 		/* Clear the halt bit in RSTAT */
 		gfar_write(&regs->rstat, gfargrp->rstat);
 		gfar_write(&regs->imask, IMASK_DEFAULT);
 		/* If we are coalescing interrupts, update the timer */
 		/* Otherwise, clear it */
 		gfar_configure_coalescing(priv,
 				gfargrp->rx_bit_map, gfargrp->tx_bit_map);
 	}
 	return rx_cleaned;
 }
 #ifdef CONFIG_NET_POLL_CONTROLLER
 /*
  * Polling 'interrupt' - used by things like netconsole to send skbs
  * without having to re-enable interrupts. It's not called while
  * the interrupt routine is executing.
  */
 static void gfar_netpoll(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	int i = 0;
 	/* If the device has multiple interrupts, run tx/rx */
 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 		for (i = 0; i < priv->num_grps; i++) {
 			disable_irq(priv->gfargrp[i].interruptTransmit);
 			disable_irq(priv->gfargrp[i].interruptReceive);
 			disable_irq(priv->gfargrp[i].interruptError);
 			gfar_interrupt(priv->gfargrp[i].interruptTransmit,
 						&priv->gfargrp[i]);
 			enable_irq(priv->gfargrp[i].interruptError);
 			enable_irq(priv->gfargrp[i].interruptReceive);
 			enable_irq(priv->gfargrp[i].interruptTransmit);
 		}
 	} else {
 		for (i = 0; i < priv->num_grps; i++) {
 			disable_irq(priv->gfargrp[i].interruptTransmit);
 			gfar_interrupt(priv->gfargrp[i].interruptTransmit,
 						&priv->gfargrp[i]);
 			enable_irq(priv->gfargrp[i].interruptTransmit);
 	}
 }
 #endif
 /* The interrupt handler for devices with one interrupt */
 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
 {
 	struct gfar_priv_grp *gfargrp = grp_id;
 	/* Save ievent for future reference */
 	u32 events = gfar_read(&gfargrp->regs->ievent);
 	/* Check for reception */
 	if (events & IEVENT_RX_MASK)
 		gfar_receive(irq, grp_id);
 	/* Check for transmit completion */
 	if (events & IEVENT_TX_MASK)
 		gfar_transmit(irq, grp_id);
 	/* Check for errors */
 	if (events & IEVENT_ERR_MASK)
 		gfar_error(irq, grp_id);
 	return IRQ_HANDLED;
 }
 /* Called every time the controller might need to be made
  * aware of new link state.  The PHY code conveys this
  * information through variables in the phydev structure, and this
  * function converts those variables into the appropriate
  * register values, and can bring down the device if needed.
  */
 static void adjust_link(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
 	unsigned long flags;
 	struct phy_device *phydev = priv->phydev;
 	int new_state = 0;
 	local_irq_save(flags);
 	lock_tx_qs(priv);
 	if (phydev->link) {
 		u32 tempval = gfar_read(&regs->maccfg2);
 		u32 ecntrl = gfar_read(&regs->ecntrl);
 		/* Now we make sure that we can be in full duplex mode.
 		 * If not, we operate in half-duplex mode. */
 		if (phydev->duplex != priv->oldduplex) {
 			new_state = 1;
 			if (!(phydev->duplex))
 				tempval &= ~(MACCFG2_FULL_DUPLEX);
 			else
 				tempval |= MACCFG2_FULL_DUPLEX;
 			priv->oldduplex = phydev->duplex;
 		}
 		if (phydev->speed != priv->oldspeed) {
 			new_state = 1;
 			switch (phydev->speed) {
 			case 1000:
 				tempval =
 				    ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
 				ecntrl &= ~(ECNTRL_R100);
 				break;
 			case 100:
 			case 10:
 				tempval =
 				    ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
 				/* Reduced mode distinguishes
 				 * between 10 and 100 */
 				if (phydev->speed == SPEED_100)
 					ecntrl |= ECNTRL_R100;
 				else
 					ecntrl &= ~(ECNTRL_R100);
 				break;
 			default:
 				if (netif_msg_link(priv))
 					printk(KERN_WARNING
 						"%s: Ack!  Speed (%d) is not 10/100/1000!\n",
 						dev->name, phydev->speed);
 				break;
 			}
 			priv->oldspeed = phydev->speed;
 		}
 		gfar_write(&regs->maccfg2, tempval);
 		gfar_write(&regs->ecntrl, ecntrl);
 		if (!priv->oldlink) {
 			new_state = 1;
 			priv->oldlink = 1;
 		}
 	} else if (priv->oldlink) {
 		new_state = 1;
 		priv->oldlink = 0;
 		priv->oldspeed = 0;
 		priv->oldduplex = -1;
 	}
 	if (new_state && netif_msg_link(priv))
 		phy_print_status(phydev);
 	unlock_tx_qs(priv);
 	local_irq_restore(flags);
 }
 /* Update the hash table based on the current list of multicast
  * addresses we subscribe to.  Also, change the promiscuity of
  * the device based on the flags (this function is called
  * whenever dev->flags is changed */
 static void gfar_set_multi(struct net_device *dev)
 {
 	struct dev_mc_list *mc_ptr;
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
 	u32 tempval;
 	if (dev->flags & IFF_PROMISC) {
 		/* Set RCTRL to PROM */
 		tempval = gfar_read(&regs->rctrl);
 		tempval |= RCTRL_PROM;
 		gfar_write(&regs->rctrl, tempval);
 	} else {
 		/* Set RCTRL to not PROM */
 		tempval = gfar_read(&regs->rctrl);
 		tempval &= ~(RCTRL_PROM);
 		gfar_write(&regs->rctrl, tempval);
 	}
 	if (dev->flags & IFF_ALLMULTI) {
 		/* Set the hash to rx all multicast frames */
 		gfar_write(&regs->igaddr0, 0xffffffff);
 		gfar_write(&regs->igaddr1, 0xffffffff);
 		gfar_write(&regs->igaddr2, 0xffffffff);
 		gfar_write(&regs->igaddr3, 0xffffffff);
 		gfar_write(&regs->igaddr4, 0xffffffff);
 		gfar_write(&regs->igaddr5, 0xffffffff);
 		gfar_write(&regs->igaddr6, 0xffffffff);
 		gfar_write(&regs->igaddr7, 0xffffffff);
 		gfar_write(&regs->gaddr0, 0xffffffff);
 		gfar_write(&regs->gaddr1, 0xffffffff);
 		gfar_write(&regs->gaddr2, 0xffffffff);
 		gfar_write(&regs->gaddr3, 0xffffffff);
 		gfar_write(&regs->gaddr4, 0xffffffff);
 		gfar_write(&regs->gaddr5, 0xffffffff);
 		gfar_write(&regs->gaddr6, 0xffffffff);
 		gfar_write(&regs->gaddr7, 0xffffffff);
 	} else {
 		int em_num;
 		int idx;
 		/* zero out the hash */
 		gfar_write(&regs->igaddr0, 0x0);
 		gfar_write(&regs->igaddr1, 0x0);
 		gfar_write(&regs->igaddr2, 0x0);
 		gfar_write(&regs->igaddr3, 0x0);
 		gfar_write(&regs->igaddr4, 0x0);
 		gfar_write(&regs->igaddr5, 0x0);
 		gfar_write(&regs->igaddr6, 0x0);
 		gfar_write(&regs->igaddr7, 0x0);
 		gfar_write(&regs->gaddr0, 0x0);
 		gfar_write(&regs->gaddr1, 0x0);
 		gfar_write(&regs->gaddr2, 0x0);
 		gfar_write(&regs->gaddr3, 0x0);
 		gfar_write(&regs->gaddr4, 0x0);
 		gfar_write(&regs->gaddr5, 0x0);
 		gfar_write(&regs->gaddr6, 0x0);
 		gfar_write(&regs->gaddr7, 0x0);
 		/* If we have extended hash tables, we need to
 		 * clear the exact match registers to prepare for
 		 * setting them */
 		if (priv->extended_hash) {
 			em_num = GFAR_EM_NUM + 1;
 			gfar_clear_exact_match(dev);
 			idx = 1;
 		} else {
 			idx = 0;
 			em_num = 0;
 		}
 		if (dev->mc_count == 0)
 			return;
 		/* Parse the list, and set the appropriate bits */
 		for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
 			if (idx < em_num) {
 				gfar_set_mac_for_addr(dev, idx,
 						mc_ptr->dmi_addr);
 				idx++;
 			} else
 				gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
 		}
 	}
 	return;
 }
 /* Clears each of the exact match registers to zero, so they
  * don't interfere with normal reception */
 static void gfar_clear_exact_match(struct net_device *dev)
 {
 	int idx;
 	u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
 	for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
 		gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
 }
 /* Set the appropriate hash bit for the given addr */
 /* The algorithm works like so:
  * 1) Take the Destination Address (ie the multicast address), and
  * do a CRC on it (little endian), and reverse the bits of the
  * result.
  * 2) Use the 8 most significant bits as a hash into a 256-entry
  * table.  The table is controlled through 8 32-bit registers:
  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
  * gaddr7.  This means that the 3 most significant bits in the
  * hash index which gaddr register to use, and the 5 other bits
  * indicate which bit (assuming an IBM numbering scheme, which
  * for PowerPC (tm) is usually the case) in the register holds
  * the entry. */
 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
 {
 	u32 tempval;
 	struct gfar_private *priv = netdev_priv(dev);
 	u32 result = ether_crc(MAC_ADDR_LEN, addr);
 	int width = priv->hash_width;
 	u8 whichbit = (result >> (32 - width)) & 0x1f;
 	u8 whichreg = result >> (32 - width + 5);
 	u32 value = (1 << (31-whichbit));
 	tempval = gfar_read(priv->hash_regs[whichreg]);
 	tempval |= value;
 	gfar_write(priv->hash_regs[whichreg], tempval);
 	return;
 }
 /* There are multiple MAC Address register pairs on some controllers
  * This function sets the numth pair to a given address
  */
 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
 	int idx;
 	char tmpbuf[MAC_ADDR_LEN];
 	u32 tempval;
 	u32 __iomem *macptr = &regs->macstnaddr1;
 	macptr += num*2;
 	/* Now copy it into the mac registers backwards, cuz */
 	/* little endian is silly */
 	for (idx = 0; idx < MAC_ADDR_LEN; idx++)
 		tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
 	gfar_write(macptr, *((u32 *) (tmpbuf)));
 	tempval = *((u32 *) (tmpbuf + 4));
 	gfar_write(macptr+1, tempval);
 }
 /* GFAR error interrupt handler */
 static irqreturn_t gfar_error(int irq, void *grp_id)
 {
 	struct gfar_priv_grp *gfargrp = grp_id;
 	struct gfar __iomem *regs = gfargrp->regs;
 	struct gfar_private *priv= gfargrp->priv;
 	struct net_device *dev = priv->ndev;
 	/* Save ievent for future reference */
 	u32 events = gfar_read(&regs->ievent);
 	/* Clear IEVENT */
 	gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
 	/* Magic Packet is not an error. */
 	if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
 	    (events & IEVENT_MAG))
 		events &= ~IEVENT_MAG;
 	/* Hmm... */
 	if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
 		printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
 		       dev->name, events, gfar_read(&regs->imask));
 	/* Update the error counters */
 	if (events & IEVENT_TXE) {
 		dev->stats.tx_errors++;
 		if (events & IEVENT_LC)
 			dev->stats.tx_window_errors++;
 		if (events & IEVENT_CRL)
 			dev->stats.tx_aborted_errors++;
 		if (events & IEVENT_XFUN) {
 			unsigned long flags;
 			if (netif_msg_tx_err(priv))
 				printk(KERN_DEBUG "%s: TX FIFO underrun, "
 				       "packet dropped.\n", dev->name);
 			dev->stats.tx_dropped++;
 			priv->extra_stats.tx_underrun++;
 			local_irq_save(flags);
 			lock_tx_qs(priv);
 			/* Reactivate the Tx Queues */
 			gfar_write(&regs->tstat, gfargrp->tstat);
 			unlock_tx_qs(priv);
 			local_irq_restore(flags);
 		}
 		if (netif_msg_tx_err(priv))
 			printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
 	}
 	if (events & IEVENT_BSY) {
 		dev->stats.rx_errors++;
 		priv->extra_stats.rx_bsy++;
 		gfar_receive(irq, grp_id);
 		if (netif_msg_rx_err(priv))
 			printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
 			       dev->name, gfar_read(&regs->rstat));
 	}
 	if (events & IEVENT_BABR) {
 		dev->stats.rx_errors++;
 		priv->extra_stats.rx_babr++;
 		if (netif_msg_rx_err(priv))
 			printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
 	}
 	if (events & IEVENT_EBERR) {
 		priv->extra_stats.eberr++;
 		if (netif_msg_rx_err(priv))
 			printk(KERN_DEBUG "%s: bus error\n", dev->name);
 	}
 	if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
 		printk(KERN_DEBUG "%s: control frame\n", dev->name);
 	if (events & IEVENT_BABT) {
 		priv->extra_stats.tx_babt++;
 		if (netif_msg_tx_err(priv))
 			printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
 	}
 	return IRQ_HANDLED;
 }
 static struct of_device_id gfar_match[] =
 {
 	{
 		.type = "network",
 		.compatible = "gianfar",
 	},
 	{
 		.compatible = "fsl,etsec2",
 	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, gfar_match);
 /* Structure for a device driver */
 static struct of_platform_driver gfar_driver = {
 	.name = "fsl-gianfar",
 	.match_table = gfar_match,
 	.probe = gfar_probe,
 	.remove = gfar_remove,
 	.suspend = gfar_legacy_suspend,
 	.resume = gfar_legacy_resume,
 	.driver.pm = GFAR_PM_OPS,
 };
 static int __init gfar_init(void)
 {
 	return of_register_platform_driver(&gfar_driver);