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Commit a6a434124457fe64bb3980ceb2170505207db6e5

Authored by Mark Brown
Committed by Dave Jones
1 parent b191c54029
Exists in master and in 6 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[CPUFREQ] s3c64xx: Use pr_fmt() for consistent log messages 

They're already consistent but it saves remembering to do so.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Dave Jones <davej@redhat.com>

Showing 1 changed file with 22 additions and 13 deletions Inline Diff

drivers/cpufreq/s3c64xx-cpufreq.c
Diff comments   View file @ a6a4341
1 /* 1 /*
2 * Copyright 2009 Wolfson Microelectronics plc 2 * Copyright 2009 Wolfson Microelectronics plc
3 * 3 *
4 * S3C64xx CPUfreq Support 4 * S3C64xx CPUfreq Support
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11 #define pr_fmt(fmt) "cpufreq: " fmt
12
11 #include <linux/kernel.h> 13 #include <linux/kernel.h>
12 #include <linux/types.h> 14 #include <linux/types.h>
13 #include <linux/init.h> 15 #include <linux/init.h>
14 #include <linux/cpufreq.h> 16 #include <linux/cpufreq.h>
15 #include <linux/clk.h> 17 #include <linux/clk.h>
16 #include <linux/err.h> 18 #include <linux/err.h>
17 #include <linux/regulator/consumer.h> 19 #include <linux/regulator/consumer.h>
18 #include <linux/module.h> 20 #include <linux/module.h>
19 21
20 static struct clk *armclk; 22 static struct clk *armclk;
21 static struct regulator *vddarm; 23 static struct regulator *vddarm;
22 static unsigned long regulator_latency; 24 static unsigned long regulator_latency;
23 25
24 #ifdef CONFIG_CPU_S3C6410 26 #ifdef CONFIG_CPU_S3C6410
25 struct s3c64xx_dvfs { 27 struct s3c64xx_dvfs {
26 unsigned int vddarm_min; 28 unsigned int vddarm_min;
27 unsigned int vddarm_max; 29 unsigned int vddarm_max;
28 }; 30 };
29 31
30 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { 32 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
31 [0] = { 1000000, 1150000 }, 33 [0] = { 1000000, 1150000 },
32 [1] = { 1050000, 1150000 }, 34 [1] = { 1050000, 1150000 },
33 [2] = { 1100000, 1150000 }, 35 [2] = { 1100000, 1150000 },
34 [3] = { 1200000, 1350000 }, 36 [3] = { 1200000, 1350000 },
35 [4] = { 1300000, 1350000 }, 37 [4] = { 1300000, 1350000 },
36 }; 38 };
37 39
38 static struct cpufreq_frequency_table s3c64xx_freq_table[] = { 40 static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
39 { 0, 66000 }, 41 { 0, 66000 },
40 { 0, 100000 }, 42 { 0, 100000 },
41 { 0, 133000 }, 43 { 0, 133000 },
42 { 1, 200000 }, 44 { 1, 200000 },
43 { 1, 222000 }, 45 { 1, 222000 },
44 { 1, 266000 }, 46 { 1, 266000 },
45 { 2, 333000 }, 47 { 2, 333000 },
46 { 2, 400000 }, 48 { 2, 400000 },
47 { 2, 532000 }, 49 { 2, 532000 },
48 { 2, 533000 }, 50 { 2, 533000 },
49 { 3, 667000 }, 51 { 3, 667000 },
50 { 4, 800000 }, 52 { 4, 800000 },
51 { 0, CPUFREQ_TABLE_END }, 53 { 0, CPUFREQ_TABLE_END },
52 }; 54 };
53 #endif 55 #endif
54 56
55 static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy) 57 static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
56 { 58 {
57 if (policy->cpu != 0) 59 if (policy->cpu != 0)
58 return -EINVAL; 60 return -EINVAL;
59 61
60 return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table); 62 return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
61 } 63 }
62 64
63 static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu) 65 static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
64 { 66 {
65 if (cpu != 0) 67 if (cpu != 0)
66 return 0; 68 return 0;
67 69
68 return clk_get_rate(armclk) / 1000; 70 return clk_get_rate(armclk) / 1000;
69 } 71 }
70 72
71 static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, 73 static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
72 unsigned int target_freq, 74 unsigned int target_freq,
73 unsigned int relation) 75 unsigned int relation)
74 { 76 {
75 int ret; 77 int ret;
76 unsigned int i; 78 unsigned int i;
77 struct cpufreq_freqs freqs; 79 struct cpufreq_freqs freqs;
78 struct s3c64xx_dvfs *dvfs; 80 struct s3c64xx_dvfs *dvfs;
79 81
80 ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table, 82 ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
81 target_freq, relation, &i); 83 target_freq, relation, &i);
82 if (ret != 0) 84 if (ret != 0)
83 return ret; 85 return ret;
84 86
85 freqs.cpu = 0; 87 freqs.cpu = 0;
86 freqs.old = clk_get_rate(armclk) / 1000; 88 freqs.old = clk_get_rate(armclk) / 1000;
87 freqs.new = s3c64xx_freq_table[i].frequency; 89 freqs.new = s3c64xx_freq_table[i].frequency;
88 freqs.flags = 0; 90 freqs.flags = 0;
89 dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index]; 91 dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
90 92
91 if (freqs.old == freqs.new) 93 if (freqs.old == freqs.new)
92 return 0; 94 return 0;
93 95
94 pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new); 96 pr_debug("Transition %d-%dkHz\n", freqs.old, freqs.new);
95 97
96 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 98 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
97 99
98 #ifdef CONFIG_REGULATOR 100 #ifdef CONFIG_REGULATOR
99 if (vddarm && freqs.new > freqs.old) { 101 if (vddarm && freqs.new > freqs.old) {
100 ret = regulator_set_voltage(vddarm, 102 ret = regulator_set_voltage(vddarm,
101 dvfs->vddarm_min, 103 dvfs->vddarm_min,
102 dvfs->vddarm_max); 104 dvfs->vddarm_max);
103 if (ret != 0) { 105 if (ret != 0) {
104 pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n", 106 pr_err("Failed to set VDDARM for %dkHz: %d\n",
105 freqs.new, ret); 107 freqs.new, ret);
106 goto err; 108 goto err;
107 } 109 }
108 } 110 }
109 #endif 111 #endif
110 112
111 ret = clk_set_rate(armclk, freqs.new * 1000); 113 ret = clk_set_rate(armclk, freqs.new * 1000);
112 if (ret < 0) { 114 if (ret < 0) {
113 pr_err("cpufreq: Failed to set rate %dkHz: %d\n", 115 pr_err("Failed to set rate %dkHz: %d\n",
114 freqs.new, ret); 116 freqs.new, ret);
115 goto err; 117 goto err;
116 } 118 }
117 119
118 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 120 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
119 121
120 #ifdef CONFIG_REGULATOR 122 #ifdef CONFIG_REGULATOR
121 if (vddarm && freqs.new < freqs.old) { 123 if (vddarm && freqs.new < freqs.old) {
122 ret = regulator_set_voltage(vddarm, 124 ret = regulator_set_voltage(vddarm,
123 dvfs->vddarm_min, 125 dvfs->vddarm_min,
124 dvfs->vddarm_max); 126 dvfs->vddarm_max);
125 if (ret != 0) { 127 if (ret != 0) {
126 pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n", 128 pr_err("Failed to set VDDARM for %dkHz: %d\n",
127 freqs.new, ret); 129 freqs.new, ret);
128 goto err_clk; 130 goto err_clk;
129 } 131 }
130 } 132 }
131 #endif 133 #endif
132 134
133 pr_debug("cpufreq: Set actual frequency %lukHz\n", 135 pr_debug("Set actual frequency %lukHz\n",
134 clk_get_rate(armclk) / 1000); 136 clk_get_rate(armclk) / 1000);
135 137
136 return 0; 138 return 0;
137 139
138 err_clk: 140 err_clk:
139 if (clk_set_rate(armclk, freqs.old * 1000) < 0) 141 if (clk_set_rate(armclk, freqs.old * 1000) < 0)
140 pr_err("Failed to restore original clock rate\n"); 142 pr_err("Failed to restore original clock rate\n");
141 err: 143 err:
142 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 144 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
143 145
144 return ret; 146 return ret;
145 } 147 }
146 148
147 #ifdef CONFIG_REGULATOR 149 #ifdef CONFIG_REGULATOR
148 static void __init s3c64xx_cpufreq_config_regulator(void) 150 static void __init s3c64xx_cpufreq_config_regulator(void)
149 { 151 {
150 int count, v, i, found; 152 int count, v, i, found;
151 struct cpufreq_frequency_table *freq; 153 struct cpufreq_frequency_table *freq;
152 struct s3c64xx_dvfs *dvfs; 154 struct s3c64xx_dvfs *dvfs;
153 155
154 count = regulator_count_voltages(vddarm); 156 count = regulator_count_voltages(vddarm);
155 if (count < 0) { 157 if (count < 0) {
156 pr_err("cpufreq: Unable to check supported voltages\n"); 158 pr_err("Unable to check supported voltages\n");
157 } 159 }
158 160
159 freq = s3c64xx_freq_table; 161 freq = s3c64xx_freq_table;
160 while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) { 162 while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
161 if (freq->frequency == CPUFREQ_ENTRY_INVALID) 163 if (freq->frequency == CPUFREQ_ENTRY_INVALID)
162 continue; 164 continue;
163 165
164 dvfs = &s3c64xx_dvfs_table[freq->index]; 166 dvfs = &s3c64xx_dvfs_table[freq->index];
165 found = 0; 167 found = 0;
166 168
167 for (i = 0; i < count; i++) { 169 for (i = 0; i < count; i++) {
168 v = regulator_list_voltage(vddarm, i); 170 v = regulator_list_voltage(vddarm, i);
169 if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) 171 if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
170 found = 1; 172 found = 1;
171 } 173 }
172 174
173 if (!found) { 175 if (!found) {
174 pr_debug("cpufreq: %dkHz unsupported by regulator\n", 176 pr_debug("%dkHz unsupported by regulator\n",
175 freq->frequency); 177 freq->frequency);
176 freq->frequency = CPUFREQ_ENTRY_INVALID; 178 freq->frequency = CPUFREQ_ENTRY_INVALID;
177 } 179 }
178 180
179 freq++; 181 freq++;
180 } 182 }
181 183
182 /* Guess based on having to do an I2C/SPI write; in future we 184 /* Guess based on having to do an I2C/SPI write; in future we
183 * will be able to query the regulator performance here. */ 185 * will be able to query the regulator performance here. */
184 regulator_latency = 1 * 1000 * 1000; 186 regulator_latency = 1 * 1000 * 1000;
185 } 187 }
186 #endif 188 #endif
187 189
188 static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) 190 static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
189 { 191 {
190 int ret; 192 int ret;
191 struct cpufreq_frequency_table *freq; 193 struct cpufreq_frequency_table *freq;
192 194
193 if (policy->cpu != 0) 195 if (policy->cpu != 0)
194 return -EINVAL; 196 return -EINVAL;
195 197
196 if (s3c64xx_freq_table == NULL) { 198 if (s3c64xx_freq_table == NULL) {
197 pr_err("cpufreq: No frequency information for this CPU\n"); 199 pr_err("No frequency information for this CPU\n");
198 return -ENODEV; 200 return -ENODEV;
199 } 201 }
200 202
201 armclk = clk_get(NULL, "armclk"); 203 armclk = clk_get(NULL, "armclk");
202 if (IS_ERR(armclk)) { 204 if (IS_ERR(armclk)) {
203 pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n", 205 pr_err("Unable to obtain ARMCLK: %ld\n",
204 PTR_ERR(armclk)); 206 PTR_ERR(armclk));
205 return PTR_ERR(armclk); 207 return PTR_ERR(armclk);
206 } 208 }
207 209
208 #ifdef CONFIG_REGULATOR 210 #ifdef CONFIG_REGULATOR
209 vddarm = regulator_get(NULL, "vddarm"); 211 vddarm = regulator_get(NULL, "vddarm");
210 if (IS_ERR(vddarm)) { 212 if (IS_ERR(vddarm)) {
211 ret = PTR_ERR(vddarm); 213 ret = PTR_ERR(vddarm);
212 pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret); 214 pr_err("Failed to obtain VDDARM: %d\n", ret);
213 pr_err("cpufreq: Only frequency scaling available\n"); 215 pr_err("Only frequency scaling available\n");
214 vddarm = NULL; 216 vddarm = NULL;
215 } else { 217 } else {
216 s3c64xx_cpufreq_config_regulator(); 218 s3c64xx_cpufreq_config_regulator();
217 } 219 }
220
221 vddint = regulator_get(NULL, "vddint");
222 if (IS_ERR(vddint)) {
223 ret = PTR_ERR(vddint);
224 pr_err("Failed to obtain VDDINT: %d\n", ret);
225 vddint = NULL;
226 }
218 #endif 227 #endif
219 228
220 freq = s3c64xx_freq_table; 229 freq = s3c64xx_freq_table;
221 while (freq->frequency != CPUFREQ_TABLE_END) { 230 while (freq->frequency != CPUFREQ_TABLE_END) {
222 unsigned long r; 231 unsigned long r;
223 232
224 /* Check for frequencies we can generate */ 233 /* Check for frequencies we can generate */
225 r = clk_round_rate(armclk, freq->frequency * 1000); 234 r = clk_round_rate(armclk, freq->frequency * 1000);
226 r /= 1000; 235 r /= 1000;
227 if (r != freq->frequency) { 236 if (r != freq->frequency) {
228 pr_debug("cpufreq: %dkHz unsupported by clock\n", 237 pr_debug("%dkHz unsupported by clock\n",
229 freq->frequency); 238 freq->frequency);
230 freq->frequency = CPUFREQ_ENTRY_INVALID; 239 freq->frequency = CPUFREQ_ENTRY_INVALID;
231 } 240 }
232 241
233 /* If we have no regulator then assume startup 242 /* If we have no regulator then assume startup
234 * frequency is the maximum we can support. */ 243 * frequency is the maximum we can support. */
235 if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0)) 244 if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
236 freq->frequency = CPUFREQ_ENTRY_INVALID; 245 freq->frequency = CPUFREQ_ENTRY_INVALID;
237 246
238 freq++; 247 freq++;
239 } 248 }
240 249
241 policy->cur = clk_get_rate(armclk) / 1000; 250 policy->cur = clk_get_rate(armclk) / 1000;
242 251
243 /* Datasheet says PLL stabalisation time (if we were to use 252 /* Datasheet says PLL stabalisation time (if we were to use
244 * the PLLs, which we don't currently) is ~300us worst case, 253 * the PLLs, which we don't currently) is ~300us worst case,
245 * but add some fudge. 254 * but add some fudge.
246 */ 255 */
247 policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency; 256 policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
248 257
249 ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table); 258 ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
250 if (ret != 0) { 259 if (ret != 0) {
251 pr_err("cpufreq: Failed to configure frequency table: %d\n", 260 pr_err("Failed to configure frequency table: %d\n",
252 ret); 261 ret);
253 regulator_put(vddarm); 262 regulator_put(vddarm);
254 clk_put(armclk); 263 clk_put(armclk);
255 } 264 }
256 265
257 return ret; 266 return ret;
258 } 267 }
259 268
260 static struct cpufreq_driver s3c64xx_cpufreq_driver = { 269 static struct cpufreq_driver s3c64xx_cpufreq_driver = {
261 .owner = THIS_MODULE, 270 .owner = THIS_MODULE,
262 .flags = 0, 271 .flags = 0,
263 .verify = s3c64xx_cpufreq_verify_speed, 272 .verify = s3c64xx_cpufreq_verify_speed,
264 .target = s3c64xx_cpufreq_set_target, 273 .target = s3c64xx_cpufreq_set_target,
265 .get = s3c64xx_cpufreq_get_speed, 274 .get = s3c64xx_cpufreq_get_speed,
266 .init = s3c64xx_cpufreq_driver_init, 275 .init = s3c64xx_cpufreq_driver_init,
267 .name = "s3c", 276 .name = "s3c",
268 }; 277 };
269 278
270 static int __init s3c64xx_cpufreq_init(void) 279 static int __init s3c64xx_cpufreq_init(void)
271 { 280 {
272 return cpufreq_register_driver(&s3c64xx_cpufreq_driver); 281 return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
273 } 282 }
274 module_init(s3c64xx_cpufreq_init); 283 module_init(s3c64xx_cpufreq_init);
275 284