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Commit a9381b3f9b68027902f5da356064ba186c7a4f59

Authored by Sachin Kamat
Committed by Mike Turquette
1 parent ae2329f790
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

clk: exynos5420: Make exynos5420_plls static 

'exynos5420_plls' is used only in this file. Make is static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

drivers/clk/samsung/clk-exynos5420.c
Diff comments   View file @ a9381b3
1 /* 1 /*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Authors: Thomas Abraham <thomas.ab@samsung.com> 3 * Authors: Thomas Abraham <thomas.ab@samsung.com>
4 * Chander Kashyap <k.chander@samsung.com> 4 * Chander Kashyap <k.chander@samsung.com>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 * 9 *
10 * Common Clock Framework support for Exynos5420 SoC. 10 * Common Clock Framework support for Exynos5420 SoC.
11 */ 11 */
12 12
13 #include <linux/clk.h> 13 #include <linux/clk.h>
14 #include <linux/clkdev.h> 14 #include <linux/clkdev.h>
15 #include <linux/clk-provider.h> 15 #include <linux/clk-provider.h>
16 #include <linux/of.h> 16 #include <linux/of.h>
17 #include <linux/of_address.h> 17 #include <linux/of_address.h>
18 18
19 #include "clk.h" 19 #include "clk.h"
20 20
21 #define APLL_LOCK 0x0 21 #define APLL_LOCK 0x0
22 #define APLL_CON0 0x100 22 #define APLL_CON0 0x100
23 #define SRC_CPU 0x200 23 #define SRC_CPU 0x200
24 #define DIV_CPU0 0x500 24 #define DIV_CPU0 0x500
25 #define DIV_CPU1 0x504 25 #define DIV_CPU1 0x504
26 #define GATE_BUS_CPU 0x700 26 #define GATE_BUS_CPU 0x700
27 #define GATE_SCLK_CPU 0x800 27 #define GATE_SCLK_CPU 0x800
28 #define CPLL_LOCK 0x10020 28 #define CPLL_LOCK 0x10020
29 #define DPLL_LOCK 0x10030 29 #define DPLL_LOCK 0x10030
30 #define EPLL_LOCK 0x10040 30 #define EPLL_LOCK 0x10040
31 #define RPLL_LOCK 0x10050 31 #define RPLL_LOCK 0x10050
32 #define IPLL_LOCK 0x10060 32 #define IPLL_LOCK 0x10060
33 #define SPLL_LOCK 0x10070 33 #define SPLL_LOCK 0x10070
34 #define VPLL_LOCK 0x10070 34 #define VPLL_LOCK 0x10070
35 #define MPLL_LOCK 0x10090 35 #define MPLL_LOCK 0x10090
36 #define CPLL_CON0 0x10120 36 #define CPLL_CON0 0x10120
37 #define DPLL_CON0 0x10128 37 #define DPLL_CON0 0x10128
38 #define EPLL_CON0 0x10130 38 #define EPLL_CON0 0x10130
39 #define RPLL_CON0 0x10140 39 #define RPLL_CON0 0x10140
40 #define IPLL_CON0 0x10150 40 #define IPLL_CON0 0x10150
41 #define SPLL_CON0 0x10160 41 #define SPLL_CON0 0x10160
42 #define VPLL_CON0 0x10170 42 #define VPLL_CON0 0x10170
43 #define MPLL_CON0 0x10180 43 #define MPLL_CON0 0x10180
44 #define SRC_TOP0 0x10200 44 #define SRC_TOP0 0x10200
45 #define SRC_TOP1 0x10204 45 #define SRC_TOP1 0x10204
46 #define SRC_TOP2 0x10208 46 #define SRC_TOP2 0x10208
47 #define SRC_TOP3 0x1020c 47 #define SRC_TOP3 0x1020c
48 #define SRC_TOP4 0x10210 48 #define SRC_TOP4 0x10210
49 #define SRC_TOP5 0x10214 49 #define SRC_TOP5 0x10214
50 #define SRC_TOP6 0x10218 50 #define SRC_TOP6 0x10218
51 #define SRC_TOP7 0x1021c 51 #define SRC_TOP7 0x1021c
52 #define SRC_DISP10 0x1022c 52 #define SRC_DISP10 0x1022c
53 #define SRC_MAU 0x10240 53 #define SRC_MAU 0x10240
54 #define SRC_FSYS 0x10244 54 #define SRC_FSYS 0x10244
55 #define SRC_PERIC0 0x10250 55 #define SRC_PERIC0 0x10250
56 #define SRC_PERIC1 0x10254 56 #define SRC_PERIC1 0x10254
57 #define SRC_TOP10 0x10280 57 #define SRC_TOP10 0x10280
58 #define SRC_TOP11 0x10284 58 #define SRC_TOP11 0x10284
59 #define SRC_TOP12 0x10288 59 #define SRC_TOP12 0x10288
60 #define SRC_MASK_DISP10 0x1032c 60 #define SRC_MASK_DISP10 0x1032c
61 #define SRC_MASK_FSYS 0x10340 61 #define SRC_MASK_FSYS 0x10340
62 #define SRC_MASK_PERIC0 0x10350 62 #define SRC_MASK_PERIC0 0x10350
63 #define SRC_MASK_PERIC1 0x10354 63 #define SRC_MASK_PERIC1 0x10354
64 #define DIV_TOP0 0x10500 64 #define DIV_TOP0 0x10500
65 #define DIV_TOP1 0x10504 65 #define DIV_TOP1 0x10504
66 #define DIV_TOP2 0x10508 66 #define DIV_TOP2 0x10508
67 #define DIV_DISP10 0x1052c 67 #define DIV_DISP10 0x1052c
68 #define DIV_MAU 0x10544 68 #define DIV_MAU 0x10544
69 #define DIV_FSYS0 0x10548 69 #define DIV_FSYS0 0x10548
70 #define DIV_FSYS1 0x1054c 70 #define DIV_FSYS1 0x1054c
71 #define DIV_FSYS2 0x10550 71 #define DIV_FSYS2 0x10550
72 #define DIV_PERIC0 0x10558 72 #define DIV_PERIC0 0x10558
73 #define DIV_PERIC1 0x1055c 73 #define DIV_PERIC1 0x1055c
74 #define DIV_PERIC2 0x10560 74 #define DIV_PERIC2 0x10560
75 #define DIV_PERIC3 0x10564 75 #define DIV_PERIC3 0x10564
76 #define DIV_PERIC4 0x10568 76 #define DIV_PERIC4 0x10568
77 #define GATE_BUS_TOP 0x10700 77 #define GATE_BUS_TOP 0x10700
78 #define GATE_BUS_FSYS0 0x10740 78 #define GATE_BUS_FSYS0 0x10740
79 #define GATE_BUS_PERIC 0x10750 79 #define GATE_BUS_PERIC 0x10750
80 #define GATE_BUS_PERIC1 0x10754 80 #define GATE_BUS_PERIC1 0x10754
81 #define GATE_BUS_PERIS0 0x10760 81 #define GATE_BUS_PERIS0 0x10760
82 #define GATE_BUS_PERIS1 0x10764 82 #define GATE_BUS_PERIS1 0x10764
83 #define GATE_IP_GSCL0 0x10910 83 #define GATE_IP_GSCL0 0x10910
84 #define GATE_IP_GSCL1 0x10920 84 #define GATE_IP_GSCL1 0x10920
85 #define GATE_IP_MFC 0x1092c 85 #define GATE_IP_MFC 0x1092c
86 #define GATE_IP_DISP1 0x10928 86 #define GATE_IP_DISP1 0x10928
87 #define GATE_IP_G3D 0x10930 87 #define GATE_IP_G3D 0x10930
88 #define GATE_IP_GEN 0x10934 88 #define GATE_IP_GEN 0x10934
89 #define GATE_IP_MSCL 0x10970 89 #define GATE_IP_MSCL 0x10970
90 #define GATE_TOP_SCLK_GSCL 0x10820 90 #define GATE_TOP_SCLK_GSCL 0x10820
91 #define GATE_TOP_SCLK_DISP1 0x10828 91 #define GATE_TOP_SCLK_DISP1 0x10828
92 #define GATE_TOP_SCLK_MAU 0x1083c 92 #define GATE_TOP_SCLK_MAU 0x1083c
93 #define GATE_TOP_SCLK_FSYS 0x10840 93 #define GATE_TOP_SCLK_FSYS 0x10840
94 #define GATE_TOP_SCLK_PERIC 0x10850 94 #define GATE_TOP_SCLK_PERIC 0x10850
95 #define BPLL_LOCK 0x20010 95 #define BPLL_LOCK 0x20010
96 #define BPLL_CON0 0x20110 96 #define BPLL_CON0 0x20110
97 #define SRC_CDREX 0x20200 97 #define SRC_CDREX 0x20200
98 #define KPLL_LOCK 0x28000 98 #define KPLL_LOCK 0x28000
99 #define KPLL_CON0 0x28100 99 #define KPLL_CON0 0x28100
100 #define SRC_KFC 0x28200 100 #define SRC_KFC 0x28200
101 #define DIV_KFC0 0x28500 101 #define DIV_KFC0 0x28500
102 102
103 /* list of PLLs */ 103 /* list of PLLs */
104 enum exynos5420_plls { 104 enum exynos5420_plls {
105 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 105 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
106 bpll, kpll, 106 bpll, kpll,
107 nr_plls /* number of PLLs */ 107 nr_plls /* number of PLLs */
108 }; 108 };
109 109
110 enum exynos5420_clks { 110 enum exynos5420_clks {
111 none, 111 none,
112 112
113 /* core clocks */ 113 /* core clocks */
114 fin_pll, fout_apll, fout_cpll, fout_dpll, fout_epll, fout_rpll, 114 fin_pll, fout_apll, fout_cpll, fout_dpll, fout_epll, fout_rpll,
115 fout_ipll, fout_spll, fout_vpll, fout_mpll, fout_bpll, fout_kpll, 115 fout_ipll, fout_spll, fout_vpll, fout_mpll, fout_bpll, fout_kpll,
116 116
117 /* gate for special clocks (sclk) */ 117 /* gate for special clocks (sclk) */
118 sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0, 118 sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
119 sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1, 119 sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1,
120 sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel, 120 sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
121 sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0, 121 sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
122 sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro, 122 sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
123 sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, 123 sclk_pwm, sclk_gscl_wa, sclk_gscl_wb,
124 124
125 /* gate clocks */ 125 /* gate clocks */
126 aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3, 126 aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
127 i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1, 127 i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1,
128 i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen = 300, 128 i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen = 300,
129 chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, 129 chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7,
130 tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu, 130 tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu,
131 pclk66_gpio = 330, aclk200_fsys2 = 350, mmc0, mmc1, mmc2, sromc, ufs, 131 pclk66_gpio = 330, aclk200_fsys2 = 350, mmc0, mmc1, mmc2, sromc, ufs,
132 aclk200_fsys = 360, tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301, 132 aclk200_fsys = 360, tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301,
133 aclk400_mscl = 380, mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1, 133 aclk400_mscl = 380, mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1,
134 smmu_mscl2, aclk333 = 400, mfc, smmu_mfcl, smmu_mfcr, 134 smmu_mscl2, aclk333 = 400, mfc, smmu_mfcl, smmu_mfcr,
135 aclk200_disp1 = 410, dsim1, dp1, hdmi, aclk300_disp1 = 420, fimd1, 135 aclk200_disp1 = 410, dsim1, dp1, hdmi, aclk300_disp1 = 420, fimd1,
136 smmu_fimd1, aclk166 = 430, mixer, aclk266 = 440, rotator, mdma1, 136 smmu_fimd1, aclk166 = 430, mixer, aclk266 = 440, rotator, mdma1,
137 smmu_rotator, smmu_mdma1, aclk300_jpeg = 450, jpeg, jpeg2, smmu_jpeg, 137 smmu_rotator, smmu_mdma1, aclk300_jpeg = 450, jpeg, jpeg2, smmu_jpeg,
138 aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0, 138 aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
139 gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0, 139 gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
140 aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0, 140 aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
141 smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, 141 smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d,
142 142
143 nr_clks, 143 nr_clks,
144 }; 144 };
145 145
146 /* 146 /*
147 * list of controller registers to be saved and restored during a 147 * list of controller registers to be saved and restored during a
148 * suspend/resume cycle. 148 * suspend/resume cycle.
149 */ 149 */
150 static __initdata unsigned long exynos5420_clk_regs[] = { 150 static __initdata unsigned long exynos5420_clk_regs[] = {
151 SRC_CPU, 151 SRC_CPU,
152 DIV_CPU0, 152 DIV_CPU0,
153 DIV_CPU1, 153 DIV_CPU1,
154 GATE_BUS_CPU, 154 GATE_BUS_CPU,
155 GATE_SCLK_CPU, 155 GATE_SCLK_CPU,
156 SRC_TOP0, 156 SRC_TOP0,
157 SRC_TOP1, 157 SRC_TOP1,
158 SRC_TOP2, 158 SRC_TOP2,
159 SRC_TOP3, 159 SRC_TOP3,
160 SRC_TOP4, 160 SRC_TOP4,
161 SRC_TOP5, 161 SRC_TOP5,
162 SRC_TOP6, 162 SRC_TOP6,
163 SRC_TOP7, 163 SRC_TOP7,
164 SRC_DISP10, 164 SRC_DISP10,
165 SRC_MAU, 165 SRC_MAU,
166 SRC_FSYS, 166 SRC_FSYS,
167 SRC_PERIC0, 167 SRC_PERIC0,
168 SRC_PERIC1, 168 SRC_PERIC1,
169 SRC_TOP10, 169 SRC_TOP10,
170 SRC_TOP11, 170 SRC_TOP11,
171 SRC_TOP12, 171 SRC_TOP12,
172 SRC_MASK_DISP10, 172 SRC_MASK_DISP10,
173 SRC_MASK_FSYS, 173 SRC_MASK_FSYS,
174 SRC_MASK_PERIC0, 174 SRC_MASK_PERIC0,
175 SRC_MASK_PERIC1, 175 SRC_MASK_PERIC1,
176 DIV_TOP0, 176 DIV_TOP0,
177 DIV_TOP1, 177 DIV_TOP1,
178 DIV_TOP2, 178 DIV_TOP2,
179 DIV_DISP10, 179 DIV_DISP10,
180 DIV_MAU, 180 DIV_MAU,
181 DIV_FSYS0, 181 DIV_FSYS0,
182 DIV_FSYS1, 182 DIV_FSYS1,
183 DIV_FSYS2, 183 DIV_FSYS2,
184 DIV_PERIC0, 184 DIV_PERIC0,
185 DIV_PERIC1, 185 DIV_PERIC1,
186 DIV_PERIC2, 186 DIV_PERIC2,
187 DIV_PERIC3, 187 DIV_PERIC3,
188 DIV_PERIC4, 188 DIV_PERIC4,
189 GATE_BUS_TOP, 189 GATE_BUS_TOP,
190 GATE_BUS_FSYS0, 190 GATE_BUS_FSYS0,
191 GATE_BUS_PERIC, 191 GATE_BUS_PERIC,
192 GATE_BUS_PERIC1, 192 GATE_BUS_PERIC1,
193 GATE_BUS_PERIS0, 193 GATE_BUS_PERIS0,
194 GATE_BUS_PERIS1, 194 GATE_BUS_PERIS1,
195 GATE_IP_GSCL0, 195 GATE_IP_GSCL0,
196 GATE_IP_GSCL1, 196 GATE_IP_GSCL1,
197 GATE_IP_MFC, 197 GATE_IP_MFC,
198 GATE_IP_DISP1, 198 GATE_IP_DISP1,
199 GATE_IP_G3D, 199 GATE_IP_G3D,
200 GATE_IP_GEN, 200 GATE_IP_GEN,
201 GATE_IP_MSCL, 201 GATE_IP_MSCL,
202 GATE_TOP_SCLK_GSCL, 202 GATE_TOP_SCLK_GSCL,
203 GATE_TOP_SCLK_DISP1, 203 GATE_TOP_SCLK_DISP1,
204 GATE_TOP_SCLK_MAU, 204 GATE_TOP_SCLK_MAU,
205 GATE_TOP_SCLK_FSYS, 205 GATE_TOP_SCLK_FSYS,
206 GATE_TOP_SCLK_PERIC, 206 GATE_TOP_SCLK_PERIC,
207 SRC_CDREX, 207 SRC_CDREX,
208 SRC_KFC, 208 SRC_KFC,
209 DIV_KFC0, 209 DIV_KFC0,
210 }; 210 };
211 211
212 /* list of all parent clocks */ 212 /* list of all parent clocks */
213 PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll", 213 PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll",
214 "sclk_mpll", "sclk_spll" }; 214 "sclk_mpll", "sclk_spll" };
215 PNAME(cpu_p) = { "mout_apll" , "mout_mspll_cpu" }; 215 PNAME(cpu_p) = { "mout_apll" , "mout_mspll_cpu" };
216 PNAME(kfc_p) = { "mout_kpll" , "mout_mspll_kfc" }; 216 PNAME(kfc_p) = { "mout_kpll" , "mout_mspll_kfc" };
217 PNAME(apll_p) = { "fin_pll", "fout_apll", }; 217 PNAME(apll_p) = { "fin_pll", "fout_apll", };
218 PNAME(bpll_p) = { "fin_pll", "fout_bpll", }; 218 PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
219 PNAME(cpll_p) = { "fin_pll", "fout_cpll", }; 219 PNAME(cpll_p) = { "fin_pll", "fout_cpll", };
220 PNAME(dpll_p) = { "fin_pll", "fout_dpll", }; 220 PNAME(dpll_p) = { "fin_pll", "fout_dpll", };
221 PNAME(epll_p) = { "fin_pll", "fout_epll", }; 221 PNAME(epll_p) = { "fin_pll", "fout_epll", };
222 PNAME(ipll_p) = { "fin_pll", "fout_ipll", }; 222 PNAME(ipll_p) = { "fin_pll", "fout_ipll", };
223 PNAME(kpll_p) = { "fin_pll", "fout_kpll", }; 223 PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
224 PNAME(mpll_p) = { "fin_pll", "fout_mpll", }; 224 PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
225 PNAME(rpll_p) = { "fin_pll", "fout_rpll", }; 225 PNAME(rpll_p) = { "fin_pll", "fout_rpll", };
226 PNAME(spll_p) = { "fin_pll", "fout_spll", }; 226 PNAME(spll_p) = { "fin_pll", "fout_spll", };
227 PNAME(vpll_p) = { "fin_pll", "fout_vpll", }; 227 PNAME(vpll_p) = { "fin_pll", "fout_vpll", };
228 228
229 PNAME(group1_p) = { "sclk_cpll", "sclk_dpll", "sclk_mpll" }; 229 PNAME(group1_p) = { "sclk_cpll", "sclk_dpll", "sclk_mpll" };
230 PNAME(group2_p) = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll", 230 PNAME(group2_p) = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll",
231 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 231 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
232 PNAME(group3_p) = { "sclk_rpll", "sclk_spll" }; 232 PNAME(group3_p) = { "sclk_rpll", "sclk_spll" };
233 PNAME(group4_p) = { "sclk_ipll", "sclk_dpll", "sclk_mpll" }; 233 PNAME(group4_p) = { "sclk_ipll", "sclk_dpll", "sclk_mpll" };
234 PNAME(group5_p) = { "sclk_vpll", "sclk_dpll" }; 234 PNAME(group5_p) = { "sclk_vpll", "sclk_dpll" };
235 235
236 PNAME(sw_aclk66_p) = { "dout_aclk66", "sclk_spll" }; 236 PNAME(sw_aclk66_p) = { "dout_aclk66", "sclk_spll" };
237 PNAME(aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" }; 237 PNAME(aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" };
238 238
239 PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"}; 239 PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"};
240 PNAME(user_aclk200_fsys_p) = { "fin_pll", "mout_sw_aclk200_fsys" }; 240 PNAME(user_aclk200_fsys_p) = { "fin_pll", "mout_sw_aclk200_fsys" };
241 241
242 PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"}; 242 PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"};
243 PNAME(user_aclk200_fsys2_p) = { "fin_pll", "mout_sw_aclk200_fsys2" }; 243 PNAME(user_aclk200_fsys2_p) = { "fin_pll", "mout_sw_aclk200_fsys2" };
244 244
245 PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"}; 245 PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"};
246 PNAME(aclk200_disp1_p) = { "fin_pll", "mout_sw_aclk200" }; 246 PNAME(aclk200_disp1_p) = { "fin_pll", "mout_sw_aclk200" };
247 247
248 PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"}; 248 PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"};
249 PNAME(user_aclk400_mscl_p) = { "fin_pll", "mout_sw_aclk400_mscl" }; 249 PNAME(user_aclk400_mscl_p) = { "fin_pll", "mout_sw_aclk400_mscl" };
250 250
251 PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"}; 251 PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"};
252 PNAME(user_aclk333_p) = { "fin_pll", "mout_sw_aclk333" }; 252 PNAME(user_aclk333_p) = { "fin_pll", "mout_sw_aclk333" };
253 253
254 PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"}; 254 PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"};
255 PNAME(user_aclk166_p) = { "fin_pll", "mout_sw_aclk166" }; 255 PNAME(user_aclk166_p) = { "fin_pll", "mout_sw_aclk166" };
256 256
257 PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"}; 257 PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"};
258 PNAME(user_aclk266_p) = { "fin_pll", "mout_sw_aclk266" }; 258 PNAME(user_aclk266_p) = { "fin_pll", "mout_sw_aclk266" };
259 259
260 PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"}; 260 PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"};
261 PNAME(user_aclk333_432_gscl_p) = { "fin_pll", "mout_sw_aclk333_432_gscl" }; 261 PNAME(user_aclk333_432_gscl_p) = { "fin_pll", "mout_sw_aclk333_432_gscl" };
262 262
263 PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"}; 263 PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"};
264 PNAME(user_aclk300_gscl_p) = { "fin_pll", "mout_sw_aclk300_gscl" }; 264 PNAME(user_aclk300_gscl_p) = { "fin_pll", "mout_sw_aclk300_gscl" };
265 265
266 PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"}; 266 PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"};
267 PNAME(user_aclk300_disp1_p) = { "fin_pll", "mout_sw_aclk300_disp1" }; 267 PNAME(user_aclk300_disp1_p) = { "fin_pll", "mout_sw_aclk300_disp1" };
268 268
269 PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"}; 269 PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"};
270 PNAME(user_aclk300_jpeg_p) = { "fin_pll", "mout_sw_aclk300_jpeg" }; 270 PNAME(user_aclk300_jpeg_p) = { "fin_pll", "mout_sw_aclk300_jpeg" };
271 271
272 PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"}; 272 PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"};
273 PNAME(user_aclk_g3d_p) = { "fin_pll", "mout_sw_aclk_g3d" }; 273 PNAME(user_aclk_g3d_p) = { "fin_pll", "mout_sw_aclk_g3d" };
274 274
275 PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"}; 275 PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"};
276 PNAME(user_aclk266_g2d_p) = { "fin_pll", "mout_sw_aclk266_g2d" }; 276 PNAME(user_aclk266_g2d_p) = { "fin_pll", "mout_sw_aclk266_g2d" };
277 277
278 PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"}; 278 PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"};
279 PNAME(user_aclk333_g2d_p) = { "fin_pll", "mout_sw_aclk333_g2d" }; 279 PNAME(user_aclk333_g2d_p) = { "fin_pll", "mout_sw_aclk333_g2d" };
280 280
281 PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll", 281 PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll",
282 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 282 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
283 PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll", 283 PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll",
284 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 284 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
285 PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll", 285 PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
286 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 286 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
287 PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2", 287 PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
288 "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 288 "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
289 PNAME(hdmi_p) = { "sclk_hdmiphy", "dout_hdmi_pixel" }; 289 PNAME(hdmi_p) = { "sclk_hdmiphy", "dout_hdmi_pixel" };
290 PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll", 290 PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
291 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 291 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
292 292
293 /* fixed rate clocks generated outside the soc */ 293 /* fixed rate clocks generated outside the soc */
294 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 294 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
295 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), 295 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
296 }; 296 };
297 297
298 /* fixed rate clocks generated inside the soc */ 298 /* fixed rate clocks generated inside the soc */
299 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { 299 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
300 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 300 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
301 FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 301 FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
302 FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 302 FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
303 FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), 303 FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
304 FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 304 FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
305 }; 305 };
306 306
307 static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 307 static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
308 FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0), 308 FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
309 }; 309 };
310 310
311 static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 311 static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
312 MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2), 312 MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
313 MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2), 313 MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
314 MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1), 314 MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1),
315 MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1), 315 MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
316 MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1), 316 MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
317 MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), 317 MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
318 318
319 MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), 319 MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
320 320
321 MUX_A(none, "mout_aclk400_mscl", group1_p, 321 MUX_A(none, "mout_aclk400_mscl", group1_p,
322 SRC_TOP0, 4, 2, "aclk400_mscl"), 322 SRC_TOP0, 4, 2, "aclk400_mscl"),
323 MUX(none, "mout_aclk200", group1_p, SRC_TOP0, 8, 2), 323 MUX(none, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
324 MUX(none, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2), 324 MUX(none, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
325 MUX(none, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2), 325 MUX(none, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
326 326
327 MUX(none, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2), 327 MUX(none, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
328 MUX(none, "mout_aclk66", group1_p, SRC_TOP1, 8, 2), 328 MUX(none, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
329 MUX(none, "mout_aclk266", group1_p, SRC_TOP1, 20, 2), 329 MUX(none, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
330 MUX(none, "mout_aclk166", group1_p, SRC_TOP1, 24, 2), 330 MUX(none, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
331 MUX(none, "mout_aclk333", group1_p, SRC_TOP1, 28, 2), 331 MUX(none, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
332 332
333 MUX(none, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2), 333 MUX(none, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
334 MUX(none, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2), 334 MUX(none, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
335 MUX(none, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1), 335 MUX(none, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
336 MUX(none, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2), 336 MUX(none, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
337 MUX(none, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2), 337 MUX(none, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
338 MUX(none, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2), 338 MUX(none, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
339 339
340 MUX(none, "mout_user_aclk400_mscl", user_aclk400_mscl_p, 340 MUX(none, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
341 SRC_TOP3, 4, 1), 341 SRC_TOP3, 4, 1),
342 MUX_A(none, "mout_aclk200_disp1", aclk200_disp1_p, 342 MUX_A(none, "mout_aclk200_disp1", aclk200_disp1_p,
343 SRC_TOP3, 8, 1, "aclk200_disp1"), 343 SRC_TOP3, 8, 1, "aclk200_disp1"),
344 MUX(none, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p, 344 MUX(none, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
345 SRC_TOP3, 12, 1), 345 SRC_TOP3, 12, 1),
346 MUX(none, "mout_user_aclk200_fsys", user_aclk200_fsys_p, 346 MUX(none, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
347 SRC_TOP3, 28, 1), 347 SRC_TOP3, 28, 1),
348 348
349 MUX(none, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p, 349 MUX(none, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
350 SRC_TOP4, 0, 1), 350 SRC_TOP4, 0, 1),
351 MUX(none, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1), 351 MUX(none, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
352 MUX(none, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1), 352 MUX(none, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
353 MUX(none, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1), 353 MUX(none, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
354 MUX(none, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1), 354 MUX(none, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
355 355
356 MUX(none, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1), 356 MUX(none, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
357 MUX(none, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1), 357 MUX(none, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
358 MUX(none, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1), 358 MUX(none, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
359 MUX_A(none, "mout_user_aclk_g3d", user_aclk_g3d_p, 359 MUX_A(none, "mout_user_aclk_g3d", user_aclk_g3d_p,
360 SRC_TOP5, 16, 1, "aclkg3d"), 360 SRC_TOP5, 16, 1, "aclkg3d"),
361 MUX(none, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p, 361 MUX(none, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
362 SRC_TOP5, 20, 1), 362 SRC_TOP5, 20, 1),
363 MUX(none, "mout_user_aclk300_disp1", user_aclk300_disp1_p, 363 MUX(none, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
364 SRC_TOP5, 24, 1), 364 SRC_TOP5, 24, 1),
365 MUX(none, "mout_user_aclk300_gscl", user_aclk300_gscl_p, 365 MUX(none, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
366 SRC_TOP5, 28, 1), 366 SRC_TOP5, 28, 1),
367 367
368 MUX(none, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1), 368 MUX(none, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
369 MUX(none, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1), 369 MUX(none, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
370 MUX(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1), 370 MUX(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
371 MUX(none, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1), 371 MUX(none, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
372 MUX(none, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1), 372 MUX(none, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
373 MUX(none, "sclk_epll", epll_p, SRC_TOP6, 20, 1), 373 MUX(none, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
374 MUX(none, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1), 374 MUX(none, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
375 MUX(none, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1), 375 MUX(none, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
376 376
377 MUX(none, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1), 377 MUX(none, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
378 MUX(none, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1), 378 MUX(none, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
379 MUX(none, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p, 379 MUX(none, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
380 SRC_TOP10, 12, 1), 380 SRC_TOP10, 12, 1),
381 MUX(none, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1), 381 MUX(none, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
382 382
383 MUX(none, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p, 383 MUX(none, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
384 SRC_TOP11, 0, 1), 384 SRC_TOP11, 0, 1),
385 MUX(none, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1), 385 MUX(none, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
386 MUX(none, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1), 386 MUX(none, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
387 MUX(none, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1), 387 MUX(none, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
388 MUX(none, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1), 388 MUX(none, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
389 389
390 MUX(none, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1), 390 MUX(none, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
391 MUX(none, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1), 391 MUX(none, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
392 MUX(none, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1), 392 MUX(none, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
393 MUX(none, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), 393 MUX(none, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
394 MUX(none, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p, 394 MUX(none, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
395 SRC_TOP12, 24, 1), 395 SRC_TOP12, 24, 1),
396 MUX(none, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 396 MUX(none, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
397 397
398 /* DISP1 Block */ 398 /* DISP1 Block */
399 MUX(none, "mout_fimd1", group3_p, SRC_DISP10, 4, 1), 399 MUX(none, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
400 MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3), 400 MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
401 MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3), 401 MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
402 MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3), 402 MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
403 MUX(none, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), 403 MUX(none, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
404 404
405 /* MAU Block */ 405 /* MAU Block */
406 MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3), 406 MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
407 407
408 /* FSYS Block */ 408 /* FSYS Block */
409 MUX(none, "mout_usbd301", group2_p, SRC_FSYS, 4, 3), 409 MUX(none, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
410 MUX(none, "mout_mmc0", group2_p, SRC_FSYS, 8, 3), 410 MUX(none, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
411 MUX(none, "mout_mmc1", group2_p, SRC_FSYS, 12, 3), 411 MUX(none, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
412 MUX(none, "mout_mmc2", group2_p, SRC_FSYS, 16, 3), 412 MUX(none, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
413 MUX(none, "mout_usbd300", group2_p, SRC_FSYS, 20, 3), 413 MUX(none, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
414 MUX(none, "mout_unipro", group2_p, SRC_FSYS, 24, 3), 414 MUX(none, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
415 415
416 /* PERIC Block */ 416 /* PERIC Block */
417 MUX(none, "mout_uart0", group2_p, SRC_PERIC0, 4, 3), 417 MUX(none, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
418 MUX(none, "mout_uart1", group2_p, SRC_PERIC0, 8, 3), 418 MUX(none, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
419 MUX(none, "mout_uart2", group2_p, SRC_PERIC0, 12, 3), 419 MUX(none, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
420 MUX(none, "mout_uart3", group2_p, SRC_PERIC0, 16, 3), 420 MUX(none, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
421 MUX(none, "mout_pwm", group2_p, SRC_PERIC0, 24, 3), 421 MUX(none, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
422 MUX(none, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3), 422 MUX(none, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
423 MUX(none, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3), 423 MUX(none, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
424 MUX(none, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3), 424 MUX(none, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
425 MUX(none, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3), 425 MUX(none, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
426 MUX(none, "mout_spi0", group2_p, SRC_PERIC1, 20, 3), 426 MUX(none, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
427 MUX(none, "mout_spi1", group2_p, SRC_PERIC1, 24, 3), 427 MUX(none, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
428 MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3), 428 MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
429 }; 429 };
430 430
431 static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 431 static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
432 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 432 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
433 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 433 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
434 DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3), 434 DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3),
435 DIV(none, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3), 435 DIV(none, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
436 DIV(none, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 436 DIV(none, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
437 437
438 DIV(none, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 438 DIV(none, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
439 DIV(none, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 439 DIV(none, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
440 DIV(none, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 440 DIV(none, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
441 DIV(none, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 441 DIV(none, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
442 DIV(none, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 442 DIV(none, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
443 443
444 DIV(none, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 444 DIV(none, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
445 DIV_TOP1, 0, 3), 445 DIV_TOP1, 0, 3),
446 DIV(none, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 446 DIV(none, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
447 DIV(none, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 447 DIV(none, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
448 DIV(none, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 448 DIV(none, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
449 DIV(none, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 449 DIV(none, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
450 450
451 DIV(none, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), 451 DIV(none, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
452 DIV(none, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 452 DIV(none, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
453 DIV(none, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 453 DIV(none, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
454 DIV(none, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 454 DIV(none, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
455 DIV_A(none, "dout_aclk300_disp1", "mout_aclk300_disp1", 455 DIV_A(none, "dout_aclk300_disp1", "mout_aclk300_disp1",
456 DIV_TOP2, 24, 3, "aclk300_disp1"), 456 DIV_TOP2, 24, 3, "aclk300_disp1"),
457 DIV(none, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 457 DIV(none, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
458 458
459 /* DISP1 Block */ 459 /* DISP1 Block */
460 DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), 460 DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
461 DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 461 DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
462 DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 462 DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
463 DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 463 DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
464 464
465 /* Audio Block */ 465 /* Audio Block */
466 DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 466 DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
467 DIV(none, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 467 DIV(none, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
468 468
469 /* USB3.0 */ 469 /* USB3.0 */
470 DIV(none, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 470 DIV(none, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
471 DIV(none, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 471 DIV(none, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
472 DIV(none, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 472 DIV(none, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
473 DIV(none, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 473 DIV(none, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
474 474
475 /* MMC */ 475 /* MMC */
476 DIV(none, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 476 DIV(none, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
477 DIV(none, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 477 DIV(none, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
478 DIV(none, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 478 DIV(none, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
479 479
480 DIV(none, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 480 DIV(none, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
481 481
482 /* UART and PWM */ 482 /* UART and PWM */
483 DIV(none, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 483 DIV(none, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
484 DIV(none, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 484 DIV(none, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
485 DIV(none, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 485 DIV(none, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
486 DIV(none, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 486 DIV(none, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
487 DIV(none, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 487 DIV(none, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
488 488
489 /* SPI */ 489 /* SPI */
490 DIV(none, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 490 DIV(none, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
491 DIV(none, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 491 DIV(none, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
492 DIV(none, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 492 DIV(none, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
493 493
494 /* PCM */ 494 /* PCM */
495 DIV(none, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 495 DIV(none, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
496 DIV(none, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 496 DIV(none, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
497 497
498 /* Audio - I2S */ 498 /* Audio - I2S */
499 DIV(none, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 499 DIV(none, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
500 DIV(none, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 500 DIV(none, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
501 DIV(none, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 501 DIV(none, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
502 DIV(none, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 502 DIV(none, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
503 DIV(none, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 503 DIV(none, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
504 504
505 /* SPI Pre-Ratio */ 505 /* SPI Pre-Ratio */
506 DIV(none, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), 506 DIV(none, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
507 DIV(none, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), 507 DIV(none, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
508 DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), 508 DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
509 }; 509 };
510 510
511 static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 511 static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
512 /* TODO: Re-verify the CG bits for all the gate clocks */ 512 /* TODO: Re-verify the CG bits for all the gate clocks */
513 GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"), 513 GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"),
514 514
515 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 515 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
516 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 516 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
517 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 517 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
518 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 518 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
519 519
520 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 520 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
521 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 521 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
522 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 522 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
523 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), 523 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
524 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 524 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
525 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 525 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
526 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 526 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
527 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), 527 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
528 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 528 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
529 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 529 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
530 GATE(0, "pclk66_gpio", "mout_sw_aclk66", 530 GATE(0, "pclk66_gpio", "mout_sw_aclk66",
531 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 531 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
532 GATE(0, "aclk66_psgen", "mout_aclk66_psgen", 532 GATE(0, "aclk66_psgen", "mout_aclk66_psgen",
533 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 533 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
534 GATE(0, "aclk66_peric", "mout_aclk66_peric", 534 GATE(0, "aclk66_peric", "mout_aclk66_peric",
535 GATE_BUS_TOP, 11, 0, 0), 535 GATE_BUS_TOP, 11, 0, 0),
536 GATE(0, "aclk166", "mout_user_aclk166", 536 GATE(0, "aclk166", "mout_user_aclk166",
537 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 537 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
538 GATE(0, "aclk333", "mout_aclk333", 538 GATE(0, "aclk333", "mout_aclk333",
539 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 539 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
540 540
541 /* sclk */ 541 /* sclk */
542 GATE(sclk_uart0, "sclk_uart0", "dout_uart0", 542 GATE(sclk_uart0, "sclk_uart0", "dout_uart0",
543 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 543 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
544 GATE(sclk_uart1, "sclk_uart1", "dout_uart1", 544 GATE(sclk_uart1, "sclk_uart1", "dout_uart1",
545 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 545 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
546 GATE(sclk_uart2, "sclk_uart2", "dout_uart2", 546 GATE(sclk_uart2, "sclk_uart2", "dout_uart2",
547 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 547 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
548 GATE(sclk_uart3, "sclk_uart3", "dout_uart3", 548 GATE(sclk_uart3, "sclk_uart3", "dout_uart3",
549 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 549 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
550 GATE(sclk_spi0, "sclk_spi0", "dout_pre_spi0", 550 GATE(sclk_spi0, "sclk_spi0", "dout_pre_spi0",
551 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 551 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
552 GATE(sclk_spi1, "sclk_spi1", "dout_pre_spi1", 552 GATE(sclk_spi1, "sclk_spi1", "dout_pre_spi1",
553 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 553 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
554 GATE(sclk_spi2, "sclk_spi2", "dout_pre_spi2", 554 GATE(sclk_spi2, "sclk_spi2", "dout_pre_spi2",
555 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 555 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
556 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 556 GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
557 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 557 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
558 GATE(sclk_pwm, "sclk_pwm", "dout_pwm", 558 GATE(sclk_pwm, "sclk_pwm", "dout_pwm",
559 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 559 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
560 GATE(sclk_pcm1, "sclk_pcm1", "dout_pcm1", 560 GATE(sclk_pcm1, "sclk_pcm1", "dout_pcm1",
561 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 561 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
562 GATE(sclk_pcm2, "sclk_pcm2", "dout_pcm2", 562 GATE(sclk_pcm2, "sclk_pcm2", "dout_pcm2",
563 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 563 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
564 GATE(sclk_i2s1, "sclk_i2s1", "dout_i2s1", 564 GATE(sclk_i2s1, "sclk_i2s1", "dout_i2s1",
565 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 565 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
566 GATE(sclk_i2s2, "sclk_i2s2", "dout_i2s2", 566 GATE(sclk_i2s2, "sclk_i2s2", "dout_i2s2",
567 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 567 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
568 568
569 GATE(sclk_mmc0, "sclk_mmc0", "dout_mmc0", 569 GATE(sclk_mmc0, "sclk_mmc0", "dout_mmc0",
570 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 570 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
571 GATE(sclk_mmc1, "sclk_mmc1", "dout_mmc1", 571 GATE(sclk_mmc1, "sclk_mmc1", "dout_mmc1",
572 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 572 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
573 GATE(sclk_mmc2, "sclk_mmc2", "dout_mmc2", 573 GATE(sclk_mmc2, "sclk_mmc2", "dout_mmc2",
574 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 574 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
575 GATE(sclk_usbphy301, "sclk_usbphy301", "dout_usbphy301", 575 GATE(sclk_usbphy301, "sclk_usbphy301", "dout_usbphy301",
576 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 576 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
577 GATE(sclk_usbphy300, "sclk_usbphy300", "dout_usbphy300", 577 GATE(sclk_usbphy300, "sclk_usbphy300", "dout_usbphy300",
578 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 578 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
579 GATE(sclk_usbd300, "sclk_usbd300", "dout_usbd300", 579 GATE(sclk_usbd300, "sclk_usbd300", "dout_usbd300",
580 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 580 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
581 GATE(sclk_usbd301, "sclk_usbd301", "dout_usbd301", 581 GATE(sclk_usbd301, "sclk_usbd301", "dout_usbd301",
582 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 582 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
583 583
584 GATE(sclk_usbd301, "sclk_unipro", "dout_unipro", 584 GATE(sclk_usbd301, "sclk_unipro", "dout_unipro",
585 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 585 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
586 586
587 GATE(sclk_gscl_wa, "sclk_gscl_wa", "aclK333_432_gscl", 587 GATE(sclk_gscl_wa, "sclk_gscl_wa", "aclK333_432_gscl",
588 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0), 588 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
589 GATE(sclk_gscl_wb, "sclk_gscl_wb", "aclk333_432_gscl", 589 GATE(sclk_gscl_wb, "sclk_gscl_wb", "aclk333_432_gscl",
590 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0), 590 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
591 591
592 /* Display */ 592 /* Display */
593 GATE(sclk_fimd1, "sclk_fimd1", "dout_fimd1", 593 GATE(sclk_fimd1, "sclk_fimd1", "dout_fimd1",
594 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 594 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
595 GATE(sclk_mipi1, "sclk_mipi1", "dout_mipi1", 595 GATE(sclk_mipi1, "sclk_mipi1", "dout_mipi1",
596 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 596 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
597 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", 597 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
598 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), 598 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
599 GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel", 599 GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel",
600 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 600 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
601 GATE(sclk_dp1, "sclk_dp1", "dout_dp1", 601 GATE(sclk_dp1, "sclk_dp1", "dout_dp1",
602 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 602 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
603 603
604 /* Maudio Block */ 604 /* Maudio Block */
605 GATE(sclk_maudio0, "sclk_maudio0", "dout_maudio0", 605 GATE(sclk_maudio0, "sclk_maudio0", "dout_maudio0",
606 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 606 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
607 GATE(sclk_maupcm0, "sclk_maupcm0", "dout_maupcm0", 607 GATE(sclk_maupcm0, "sclk_maupcm0", "dout_maupcm0",
608 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 608 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
609 /* FSYS */ 609 /* FSYS */
610 GATE(tsi, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 610 GATE(tsi, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
611 GATE(pdma0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 611 GATE(pdma0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
612 GATE(pdma1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 612 GATE(pdma1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
613 GATE(ufs, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 613 GATE(ufs, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
614 GATE(rtic, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), 614 GATE(rtic, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
615 GATE(mmc0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), 615 GATE(mmc0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
616 GATE(mmc1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), 616 GATE(mmc1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
617 GATE(mmc2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), 617 GATE(mmc2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
618 GATE(sromc, "sromc", "aclk200_fsys2", 618 GATE(sromc, "sromc", "aclk200_fsys2",
619 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), 619 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
620 GATE(usbh20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), 620 GATE(usbh20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
621 GATE(usbd300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), 621 GATE(usbd300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
622 GATE(usbd301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), 622 GATE(usbd301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
623 623
624 /* UART */ 624 /* UART */
625 GATE(uart0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0), 625 GATE(uart0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
626 GATE(uart1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0), 626 GATE(uart1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
627 GATE_A(uart2, "uart2", "aclk66_peric", 627 GATE_A(uart2, "uart2", "aclk66_peric",
628 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"), 628 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
629 GATE(uart3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0), 629 GATE(uart3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
630 /* I2C */ 630 /* I2C */
631 GATE(i2c0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0), 631 GATE(i2c0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
632 GATE(i2c1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0), 632 GATE(i2c1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
633 GATE(i2c2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0), 633 GATE(i2c2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
634 GATE(i2c3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0), 634 GATE(i2c3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
635 GATE(i2c4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0), 635 GATE(i2c4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
636 GATE(i2c5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0), 636 GATE(i2c5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
637 GATE(i2c6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0), 637 GATE(i2c6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
638 GATE(i2c7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0), 638 GATE(i2c7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
639 GATE(i2c_hdmi, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 0), 639 GATE(i2c_hdmi, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 0),
640 GATE(tsadc, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0), 640 GATE(tsadc, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
641 /* SPI */ 641 /* SPI */
642 GATE(spi0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0), 642 GATE(spi0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
643 GATE(spi1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0), 643 GATE(spi1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
644 GATE(spi2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0), 644 GATE(spi2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
645 GATE(keyif, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0), 645 GATE(keyif, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
646 /* I2S */ 646 /* I2S */
647 GATE(i2s1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0), 647 GATE(i2s1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
648 GATE(i2s2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0), 648 GATE(i2s2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
649 /* PCM */ 649 /* PCM */
650 GATE(pcm1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0), 650 GATE(pcm1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
651 GATE(pcm2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0), 651 GATE(pcm2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
652 /* PWM */ 652 /* PWM */
653 GATE(pwm, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0), 653 GATE(pwm, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
654 /* SPDIF */ 654 /* SPDIF */
655 GATE(spdif, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0), 655 GATE(spdif, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
656 656
657 GATE(i2c8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0), 657 GATE(i2c8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
658 GATE(i2c9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0), 658 GATE(i2c9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
659 GATE(i2c10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0), 659 GATE(i2c10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
660 660
661 GATE(chipid, "chipid", "aclk66_psgen", 661 GATE(chipid, "chipid", "aclk66_psgen",
662 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0), 662 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
663 GATE(sysreg, "sysreg", "aclk66_psgen", 663 GATE(sysreg, "sysreg", "aclk66_psgen",
664 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0), 664 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
665 GATE(tzpc0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0), 665 GATE(tzpc0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
666 GATE(tzpc1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0), 666 GATE(tzpc1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
667 GATE(tzpc2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0), 667 GATE(tzpc2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
668 GATE(tzpc3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0), 668 GATE(tzpc3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
669 GATE(tzpc4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0), 669 GATE(tzpc4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
670 GATE(tzpc5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0), 670 GATE(tzpc5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
671 GATE(tzpc6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0), 671 GATE(tzpc6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
672 GATE(tzpc7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0), 672 GATE(tzpc7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
673 GATE(tzpc8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0), 673 GATE(tzpc8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
674 GATE(tzpc9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0), 674 GATE(tzpc9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
675 675
676 GATE(hdmi_cec, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 0), 676 GATE(hdmi_cec, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 0),
677 GATE(seckey, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 677 GATE(seckey, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
678 GATE(wdt, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0), 678 GATE(wdt, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
679 GATE(rtc, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0), 679 GATE(rtc, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
680 GATE(tmu, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0), 680 GATE(tmu, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
681 GATE(tmu_gpu, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0), 681 GATE(tmu_gpu, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
682 682
683 GATE(gscl0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 683 GATE(gscl0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
684 GATE(gscl1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 684 GATE(gscl1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
685 GATE(clk_3aa, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0), 685 GATE(clk_3aa, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
686 686
687 GATE(smmu_3aa, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 0), 687 GATE(smmu_3aa, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 0),
688 GATE(smmu_fimcl0, "smmu_fimcl0", "aclk333_432_gscl", 688 GATE(smmu_fimcl0, "smmu_fimcl0", "aclk333_432_gscl",
689 GATE_IP_GSCL1, 3, 0, 0), 689 GATE_IP_GSCL1, 3, 0, 0),
690 GATE(smmu_fimcl1, "smmu_fimcl1", "aclk333_432_gscl", 690 GATE(smmu_fimcl1, "smmu_fimcl1", "aclk333_432_gscl",
691 GATE_IP_GSCL1, 4, 0, 0), 691 GATE_IP_GSCL1, 4, 0, 0),
692 GATE(smmu_gscl0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 0), 692 GATE(smmu_gscl0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 0),
693 GATE(smmu_gscl1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 0), 693 GATE(smmu_gscl1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 0),
694 GATE(gscl_wa, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0), 694 GATE(gscl_wa, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
695 GATE(gscl_wb, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0), 695 GATE(gscl_wb, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
696 GATE(smmu_fimcl3, "smmu_fimcl3,", "aclk333_432_gscl", 696 GATE(smmu_fimcl3, "smmu_fimcl3,", "aclk333_432_gscl",
697 GATE_IP_GSCL1, 16, 0, 0), 697 GATE_IP_GSCL1, 16, 0, 0),
698 GATE(fimc_lite3, "fimc_lite3", "aclk333_432_gscl", 698 GATE(fimc_lite3, "fimc_lite3", "aclk333_432_gscl",
699 GATE_IP_GSCL1, 17, 0, 0), 699 GATE_IP_GSCL1, 17, 0, 0),
700 700
701 GATE(fimd1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 701 GATE(fimd1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
702 GATE(dsim1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 702 GATE(dsim1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
703 GATE(dp1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 703 GATE(dp1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
704 GATE(mixer, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0), 704 GATE(mixer, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
705 GATE(hdmi, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 705 GATE(hdmi, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
706 GATE(smmu_fimd1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 0), 706 GATE(smmu_fimd1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 0),
707 707
708 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 708 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
709 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 709 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
710 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 710 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
711 711
712 GATE(g3d, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0), 712 GATE(g3d, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
713 713
714 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 714 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
715 GATE(jpeg, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 715 GATE(jpeg, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
716 GATE(jpeg2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 716 GATE(jpeg2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
717 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), 717 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
718 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), 718 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
719 GATE(smmu_jpeg, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0), 719 GATE(smmu_jpeg, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
720 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0), 720 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
721 721
722 GATE(mscl0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 722 GATE(mscl0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
723 GATE(mscl1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 723 GATE(mscl1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
724 GATE(mscl2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 724 GATE(mscl2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
725 GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0), 725 GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0),
726 GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0), 726 GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0),
727 GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0), 727 GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
728 }; 728 };
729 729
730 struct __initdata samsung_pll_clock exynos5420_plls[nr_plls] = { 730 static struct __initdata samsung_pll_clock exynos5420_plls[nr_plls] = {
731 [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, 731 [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
732 APLL_CON0, NULL), 732 APLL_CON0, NULL),
733 [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, 733 [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
734 MPLL_CON0, NULL), 734 MPLL_CON0, NULL),
735 [dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK, 735 [dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK,
736 DPLL_CON0, NULL), 736 DPLL_CON0, NULL),
737 [epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, 737 [epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
738 EPLL_CON0, NULL), 738 EPLL_CON0, NULL),
739 [rpll] = PLL(pll_2650, fout_rpll, "fout_rpll", "fin_pll", RPLL_LOCK, 739 [rpll] = PLL(pll_2650, fout_rpll, "fout_rpll", "fin_pll", RPLL_LOCK,
740 RPLL_CON0, NULL), 740 RPLL_CON0, NULL),
741 [ipll] = PLL(pll_2550, fout_ipll, "fout_ipll", "fin_pll", IPLL_LOCK, 741 [ipll] = PLL(pll_2550, fout_ipll, "fout_ipll", "fin_pll", IPLL_LOCK,
742 IPLL_CON0, NULL), 742 IPLL_CON0, NULL),
743 [spll] = PLL(pll_2550, fout_spll, "fout_spll", "fin_pll", SPLL_LOCK, 743 [spll] = PLL(pll_2550, fout_spll, "fout_spll", "fin_pll", SPLL_LOCK,
744 SPLL_CON0, NULL), 744 SPLL_CON0, NULL),
745 [vpll] = PLL(pll_2550, fout_vpll, "fout_vpll", "fin_pll", VPLL_LOCK, 745 [vpll] = PLL(pll_2550, fout_vpll, "fout_vpll", "fin_pll", VPLL_LOCK,
746 VPLL_CON0, NULL), 746 VPLL_CON0, NULL),
747 [mpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, 747 [mpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
748 MPLL_CON0, NULL), 748 MPLL_CON0, NULL),
749 [bpll] = PLL(pll_2550, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK, 749 [bpll] = PLL(pll_2550, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK,
750 BPLL_CON0, NULL), 750 BPLL_CON0, NULL),
751 [kpll] = PLL(pll_2550, fout_kpll, "fout_kpll", "fin_pll", KPLL_LOCK, 751 [kpll] = PLL(pll_2550, fout_kpll, "fout_kpll", "fin_pll", KPLL_LOCK,
752 KPLL_CON0, NULL), 752 KPLL_CON0, NULL),
753 }; 753 };
754 754
755 static __initdata struct of_device_id ext_clk_match[] = { 755 static __initdata struct of_device_id ext_clk_match[] = {
756 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 756 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
757 { }, 757 { },
758 }; 758 };
759 759
760 /* register exynos5420 clocks */ 760 /* register exynos5420 clocks */
761 static void __init exynos5420_clk_init(struct device_node *np) 761 static void __init exynos5420_clk_init(struct device_node *np)
762 { 762 {
763 void __iomem *reg_base; 763 void __iomem *reg_base;
764 764
765 if (np) { 765 if (np) {
766 reg_base = of_iomap(np, 0); 766 reg_base = of_iomap(np, 0);
767 if (!reg_base) 767 if (!reg_base)
768 panic("%s: failed to map registers\n", __func__); 768 panic("%s: failed to map registers\n", __func__);
769 } else { 769 } else {
770 panic("%s: unable to determine soc\n", __func__); 770 panic("%s: unable to determine soc\n", __func__);
771 } 771 }
772 772
773 samsung_clk_init(np, reg_base, nr_clks, 773 samsung_clk_init(np, reg_base, nr_clks,
774 exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs), 774 exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs),
775 NULL, 0); 775 NULL, 0);
776 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, 776 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
777 ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), 777 ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
778 ext_clk_match); 778 ext_clk_match);
779 samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), 779 samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls),
780 reg_base); 780 reg_base);
781 samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks, 781 samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
782 ARRAY_SIZE(exynos5420_fixed_rate_clks)); 782 ARRAY_SIZE(exynos5420_fixed_rate_clks));
783 samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks, 783 samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks,
784 ARRAY_SIZE(exynos5420_fixed_factor_clks)); 784 ARRAY_SIZE(exynos5420_fixed_factor_clks));
785 samsung_clk_register_mux(exynos5420_mux_clks, 785 samsung_clk_register_mux(exynos5420_mux_clks,
786 ARRAY_SIZE(exynos5420_mux_clks)); 786 ARRAY_SIZE(exynos5420_mux_clks));
787 samsung_clk_register_div(exynos5420_div_clks, 787 samsung_clk_register_div(exynos5420_div_clks,
788 ARRAY_SIZE(exynos5420_div_clks)); 788 ARRAY_SIZE(exynos5420_div_clks));
789 samsung_clk_register_gate(exynos5420_gate_clks, 789 samsung_clk_register_gate(exynos5420_gate_clks,
790 ARRAY_SIZE(exynos5420_gate_clks)); 790 ARRAY_SIZE(exynos5420_gate_clks));
791 } 791 }
792 CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 792 CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
793 793