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Commit ab137d04db5a4b32250ce5ef1b288ce6cf06adf6

Authored by Venu Byravarasu 2013-01-24 18:27:03 +0800

Committed by Stephen Warren 2013-01-29 02:42:11 +0800

Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches

usb: host: tegra: make use of PHY pointer of HCD

As pointer to PHY structure can be stored in struct usb_hcd
making use of it, to call Tegra PHY APIs.

Call to usb_phy_shutdown() is moved up in tegra_ehci_remove(),
so that to avoid dereferencing of hcd after its freed up.

Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Felipe Balbi <balbi@ti.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

Showing 3 changed files with 29 additions and 22 deletions Inline Diff

drivers/usb/host/ehci-tegra.c
drivers/usb/phy/tegra_usb_phy.c
include/linux/usb/tegra_usb_phy.h

drivers/usb/host/ehci-tegra.c

Diff comments View file @ ab137d0

 /*
  * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
  *
  * Copyright (C) 2010 Google, Inc.
  * Copyright (C) 2009 - 2013 NVIDIA Corporation
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
  * Free Software Foundation; either version 2 of the License, or (at your
  * option) any later version.
  *
  * This program is distributed in the hope that it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  *
  */
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
 #include <linux/platform_data/tegra_usb.h>
 #include <linux/irq.h>
 #include <linux/usb/otg.h>
 #include <linux/gpio.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
 #include <linux/pm_runtime.h>
 #include <linux/usb/ehci_def.h>
 #include <linux/usb/tegra_usb_phy.h>
 #define TEGRA_USB_BASE			0xC5000000
 #define TEGRA_USB2_BASE			0xC5004000
 #define TEGRA_USB3_BASE			0xC5008000
 /* PORTSC registers */
 #define TEGRA_USB_PORTSC1			0x184
 #define TEGRA_USB_PORTSC1_PTS(x)	(((x) & 0x3) << 30)
 #define TEGRA_USB_PORTSC1_PHCD	(1 << 23)
 #define TEGRA_USB_DMA_ALIGN 32
 struct tegra_ehci_hcd {
 	struct ehci_hcd *ehci;
 	struct tegra_usb_phy *phy;
 	struct clk *clk;
 	struct usb_phy *transceiver;
 	int host_resumed;
 	int port_resuming;
 	bool needs_double_reset;
 	enum tegra_usb_phy_port_speed port_speed;
 };
 static void tegra_ehci_power_up(struct usb_hcd *hcd)
 {
 	struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 	clk_prepare_enable(tegra->clk);
-	usb_phy_set_suspend(&tegra->phy->u_phy, 0);
+	usb_phy_set_suspend(hcd->phy, 0);
 	tegra->host_resumed = 1;
 }
 static void tegra_ehci_power_down(struct usb_hcd *hcd)
 {
 	struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 	tegra->host_resumed = 0;
-	usb_phy_set_suspend(&tegra->phy->u_phy, 1);
+	usb_phy_set_suspend(hcd->phy, 1);
 	clk_disable_unprepare(tegra->clk);
 }
 static int tegra_ehci_internal_port_reset(
 	struct ehci_hcd	*ehci,
 	u32 __iomem	*portsc_reg
 )
 {
 	u32		temp;
 	unsigned long	flags;
 	int		retval = 0;
 	int		i, tries;
 	u32		saved_usbintr;
 	spin_lock_irqsave(&ehci->lock, flags);
 	saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
 	/* disable USB interrupt */
 	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 	spin_unlock_irqrestore(&ehci->lock, flags);
 	/*
 	 * Here we have to do Port Reset at most twice for
 	 * Port Enable bit to be set.
 	 */
 	for (i = 0; i < 2; i++) {
 		temp = ehci_readl(ehci, portsc_reg);
 		temp |= PORT_RESET;
 		ehci_writel(ehci, temp, portsc_reg);
 		mdelay(10);
 		temp &= ~PORT_RESET;
 		ehci_writel(ehci, temp, portsc_reg);
 		mdelay(1);
 		tries = 100;
 		do {
 			mdelay(1);
 			/*
 			 * Up to this point, Port Enable bit is
 			 * expected to be set after 2 ms waiting.
 			 * USB1 usually takes extra 45 ms, for safety,
 			 * we take 100 ms as timeout.
 			 */
 			temp = ehci_readl(ehci, portsc_reg);
 		} while (!(temp & PORT_PE) && tries--);
 		if (temp & PORT_PE)
 			break;
 	}
 	if (i == 2)
 		retval = -ETIMEDOUT;
 	/*
 	 * Clear Connect Status Change bit if it's set.
 	 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
 	 */
 	if (temp & PORT_CSC)
 		ehci_writel(ehci, PORT_CSC, portsc_reg);
 	/*
 	 * Write to clear any interrupt status bits that might be set
 	 * during port reset.
 	 */
 	temp = ehci_readl(ehci, &ehci->regs->status);
 	ehci_writel(ehci, temp, &ehci->regs->status);
 	/* restore original interrupt enable bits */
 	ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
 	return retval;
 }
 static int tegra_ehci_hub_control(
 	struct usb_hcd	*hcd,
 	u16		typeReq,
 	u16		wValue,
 	u16		wIndex,
 	char		*buf,
 	u16		wLength
 )
 {
 	struct ehci_hcd	*ehci = hcd_to_ehci(hcd);
 	struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 	u32 __iomem	*status_reg;
 	u32		temp;
 	unsigned long	flags;
 	int		retval = 0;
 	status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
 	spin_lock_irqsave(&ehci->lock, flags);
 	if (typeReq == GetPortStatus) {
 		temp = ehci_readl(ehci, status_reg);
 		if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
 			/* Resume completed, re-enable disconnect detection */
 			tegra->port_resuming = 0;
-			tegra_usb_phy_postresume(tegra->phy);
+			tegra_usb_phy_postresume(hcd->phy);
 		}
 	}
 	else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
 		temp = ehci_readl(ehci, status_reg);
 		if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
 			retval = -EPIPE;
 			goto done;
 		}
 		temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
 		temp |= PORT_WKDISC_E | PORT_WKOC_E;
 		ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
 		/*
 		 * If a transaction is in progress, there may be a delay in
 		 * suspending the port. Poll until the port is suspended.
 		 */
 		if (handshake(ehci, status_reg, PORT_SUSPEND,
 						PORT_SUSPEND, 5000))
 			pr_err("%s: timeout waiting for SUSPEND\n", __func__);
 		set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
 		goto done;
 	}
 	/* For USB1 port we need to issue Port Reset twice internally */
 	if (tegra->needs_double_reset &&
 	   (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
 		spin_unlock_irqrestore(&ehci->lock, flags);
 		return tegra_ehci_internal_port_reset(ehci, status_reg);
 	}
 	/*
 	 * Tegra host controller will time the resume operation to clear the bit
 	 * when the port control state switches to HS or FS Idle. This behavior
 	 * is different from EHCI where the host controller driver is required
 	 * to set this bit to a zero after the resume duration is timed in the
 	 * driver.
 	 */
 	else if (typeReq == ClearPortFeature &&
 					wValue == USB_PORT_FEAT_SUSPEND) {
 		temp = ehci_readl(ehci, status_reg);
 		if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
 			retval = -EPIPE;
 			goto done;
 		}
 		if (!(temp & PORT_SUSPEND))
 			goto done;
 		/* Disable disconnect detection during port resume */
-		tegra_usb_phy_preresume(tegra->phy);
+		tegra_usb_phy_preresume(hcd->phy);
 		ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
 		temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
 		/* start resume signalling */
 		ehci_writel(ehci, temp | PORT_RESUME, status_reg);
 		set_bit(wIndex-1, &ehci->resuming_ports);
 		spin_unlock_irqrestore(&ehci->lock, flags);
 		msleep(20);
 		spin_lock_irqsave(&ehci->lock, flags);
 		/* Poll until the controller clears RESUME and SUSPEND */
 		if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
 			pr_err("%s: timeout waiting for RESUME\n", __func__);
 		if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
 			pr_err("%s: timeout waiting for SUSPEND\n", __func__);
 		ehci->reset_done[wIndex-1] = 0;
 		clear_bit(wIndex-1, &ehci->resuming_ports);
 		tegra->port_resuming = 1;
 		goto done;
 	}
 	spin_unlock_irqrestore(&ehci->lock, flags);
 	/* Handle the hub control events here */
 	return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
 done:
 	spin_unlock_irqrestore(&ehci->lock, flags);
 	return retval;
 }
 static void tegra_ehci_restart(struct usb_hcd *hcd)
 {
 	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 	ehci_reset(ehci);
 	/* setup the frame list and Async q heads */
 	ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
 	ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
 	/* setup the command register and set the controller in RUN mode */
 	ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
 	ehci->command |= CMD_RUN;
 	ehci_writel(ehci, ehci->command, &ehci->regs->command);
 	down_write(&ehci_cf_port_reset_rwsem);
 	ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 	/* flush posted writes */
 	ehci_readl(ehci, &ehci->regs->command);
 	up_write(&ehci_cf_port_reset_rwsem);
 }
 static void tegra_ehci_shutdown(struct usb_hcd *hcd)
 {
 	struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 	/* ehci_shutdown touches the USB controller registers, make sure
 	 * controller has clocks to it */
 	if (!tegra->host_resumed)
 		tegra_ehci_power_up(hcd);
 	ehci_shutdown(hcd);
 }
 static int tegra_ehci_setup(struct usb_hcd *hcd)
 {
 	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 	/* EHCI registers start at offset 0x100 */
 	ehci->caps = hcd->regs + 0x100;
 	/* switch to host mode */
 	hcd->has_tt = 1;
 	return ehci_setup(hcd);
 }
 struct dma_aligned_buffer {
 	void *kmalloc_ptr;
 	void *old_xfer_buffer;
 	u8 data[0];
 };
 static void free_dma_aligned_buffer(struct urb *urb)
 {
 	struct dma_aligned_buffer *temp;
 	if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
 		return;
 	temp = container_of(urb->transfer_buffer,
 		struct dma_aligned_buffer, data);
 	if (usb_urb_dir_in(urb))
 		memcpy(temp->old_xfer_buffer, temp->data,
 		       urb->transfer_buffer_length);
 	urb->transfer_buffer = temp->old_xfer_buffer;
 	kfree(temp->kmalloc_ptr);
 	urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
 }
 static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
 {
 	struct dma_aligned_buffer *temp, *kmalloc_ptr;
 	size_t kmalloc_size;
 	if (urb->num_sgs || urb->sg ||
 	    urb->transfer_buffer_length == 0 ||
 	    !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
 		return 0;
 	/* Allocate a buffer with enough padding for alignment */
 	kmalloc_size = urb->transfer_buffer_length +
 		sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
 	kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
 	if (!kmalloc_ptr)
 		return -ENOMEM;
 	/* Position our struct dma_aligned_buffer such that data is aligned */
 	temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
 	temp->kmalloc_ptr = kmalloc_ptr;
 	temp->old_xfer_buffer = urb->transfer_buffer;
 	if (usb_urb_dir_out(urb))
 		memcpy(temp->data, urb->transfer_buffer,
 		       urb->transfer_buffer_length);
 	urb->transfer_buffer = temp->data;
 	urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
 	return 0;
 }
 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
 				      gfp_t mem_flags)
 {
 	int ret;
 	ret = alloc_dma_aligned_buffer(urb, mem_flags);
 	if (ret)
 		return ret;
 	ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
 	if (ret)
 		free_dma_aligned_buffer(urb);
 	return ret;
 }
 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
 {
 	usb_hcd_unmap_urb_for_dma(hcd, urb);
 	free_dma_aligned_buffer(urb);
 }
 static const struct hc_driver tegra_ehci_hc_driver = {
 	.description		= hcd_name,
 	.product_desc		= "Tegra EHCI Host Controller",
 	.hcd_priv_size		= sizeof(struct ehci_hcd),
 	.flags			= HCD_USB2 | HCD_MEMORY,
 	/* standard ehci functions */
 	.irq			= ehci_irq,
 	.start			= ehci_run,
 	.stop			= ehci_stop,
 	.urb_enqueue		= ehci_urb_enqueue,
 	.urb_dequeue		= ehci_urb_dequeue,
 	.endpoint_disable	= ehci_endpoint_disable,
 	.endpoint_reset		= ehci_endpoint_reset,
 	.get_frame_number	= ehci_get_frame,
 	.hub_status_data	= ehci_hub_status_data,
 	.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
 	.relinquish_port	= ehci_relinquish_port,
 	.port_handed_over	= ehci_port_handed_over,
 	/* modified ehci functions for tegra */
 	.reset			= tegra_ehci_setup,
 	.shutdown		= tegra_ehci_shutdown,
 	.map_urb_for_dma	= tegra_ehci_map_urb_for_dma,
 	.unmap_urb_for_dma	= tegra_ehci_unmap_urb_for_dma,
 	.hub_control		= tegra_ehci_hub_control,
 #ifdef CONFIG_PM
 	.bus_suspend		= ehci_bus_suspend,
 	.bus_resume		= ehci_bus_resume,
 #endif
 };
 static int setup_vbus_gpio(struct platform_device *pdev,
 			   struct tegra_ehci_platform_data *pdata)
 {
 	int err = 0;
 	int gpio;
 	gpio = pdata->vbus_gpio;
 	if (!gpio_is_valid(gpio))
 		gpio = of_get_named_gpio(pdev->dev.of_node,
 					 "nvidia,vbus-gpio", 0);
 	if (!gpio_is_valid(gpio))
 		return 0;
 	err = gpio_request(gpio, "vbus_gpio");
 	if (err) {
 		dev_err(&pdev->dev, "can't request vbus gpio %d", gpio);
 		return err;
 	}
 	err = gpio_direction_output(gpio, 1);
 	if (err) {
 		dev_err(&pdev->dev, "can't enable vbus\n");
 		return err;
 	}
 	return err;
 }
 #ifdef CONFIG_PM
 static int controller_suspend(struct device *dev)
 {
 	struct tegra_ehci_hcd *tegra =
 			platform_get_drvdata(to_platform_device(dev));
 	struct ehci_hcd	*ehci = tegra->ehci;
 	struct usb_hcd *hcd = ehci_to_hcd(ehci);
 	struct ehci_regs __iomem *hw = ehci->regs;
 	unsigned long flags;
 	if (time_before(jiffies, ehci->next_statechange))
 		msleep(10);
 	ehci_halt(ehci);
 	spin_lock_irqsave(&ehci->lock, flags);
 	tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
 	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 	spin_unlock_irqrestore(&ehci->lock, flags);
 	tegra_ehci_power_down(hcd);
 	return 0;
 }
 static int controller_resume(struct device *dev)
 {
 	struct tegra_ehci_hcd *tegra =
 			platform_get_drvdata(to_platform_device(dev));
 	struct ehci_hcd	*ehci = tegra->ehci;
 	struct usb_hcd *hcd = ehci_to_hcd(ehci);
 	struct ehci_regs __iomem *hw = ehci->regs;
 	unsigned long val;
 	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 	tegra_ehci_power_up(hcd);
 	if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
 		/* Wait for the phy to detect new devices
 		 * before we restart the controller */
 		msleep(10);
 		goto restart;
 	}
 	/* Force the phy to keep data lines in suspend state */
-	tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
+	tegra_ehci_phy_restore_start(hcd->phy, tegra->port_speed);
 	/* Enable host mode */
 	tdi_reset(ehci);
 	/* Enable Port Power */
 	val = readl(&hw->port_status[0]);
 	val |= PORT_POWER;
 	writel(val, &hw->port_status[0]);
 	udelay(10);
 	/* Check if the phy resume from LP0. When the phy resume from LP0
 	 * USB register will be reset. */
 	if (!readl(&hw->async_next)) {
 		/* Program the field PTC based on the saved speed mode */
 		val = readl(&hw->port_status[0]);
 		val &= ~PORT_TEST(~0);
 		if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
 			val |= PORT_TEST_FORCE;
 		else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
 			val |= PORT_TEST(6);
 		else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 			val |= PORT_TEST(7);
 		writel(val, &hw->port_status[0]);
 		udelay(10);
 		/* Disable test mode by setting PTC field to NORMAL_OP */
 		val = readl(&hw->port_status[0]);
 		val &= ~PORT_TEST(~0);
 		writel(val, &hw->port_status[0]);
 		udelay(10);
 	}
 	/* Poll until CCS is enabled */
 	if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
 						 PORT_CONNECT, 2000)) {
 		pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
 		goto restart;
 	}
 	/* Poll until PE is enabled */
 	if (handshake(ehci, &hw->port_status[0], PORT_PE,
 						 PORT_PE, 2000)) {
 		pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
 		goto restart;
 	}
 	/* Clear the PCI status, to avoid an interrupt taken upon resume */
 	val = readl(&hw->status);
 	val |= STS_PCD;
 	writel(val, &hw->status);
 	/* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
 	val = readl(&hw->port_status[0]);
 	if ((val & PORT_POWER) && (val & PORT_PE)) {
 		val |= PORT_SUSPEND;
 		writel(val, &hw->port_status[0]);
 		/* Wait until port suspend completes */
 		if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
 							 PORT_SUSPEND, 1000)) {
 			pr_err("%s: timeout waiting for PORT_SUSPEND\n",
 								__func__);
 			goto restart;
 		}
 	}
-	tegra_ehci_phy_restore_end(tegra->phy);
+	tegra_ehci_phy_restore_end(hcd->phy);
 	goto done;
  restart:
 	if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
-		tegra_ehci_phy_restore_end(tegra->phy);
+		tegra_ehci_phy_restore_end(hcd->phy);
 	tegra_ehci_restart(hcd);
  done:
-	tegra_usb_phy_preresume(tegra->phy);
+	tegra_usb_phy_preresume(hcd->phy);
 	tegra->port_resuming = 1;
 	return 0;
 }
 static int tegra_ehci_suspend(struct device *dev)
 {
 	struct tegra_ehci_hcd *tegra =
 			platform_get_drvdata(to_platform_device(dev));
 	struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 	int rc = 0;
 	/*
 	 * When system sleep is supported and USB controller wakeup is
 	 * implemented: If the controller is runtime-suspended and the
 	 * wakeup setting needs to be changed, call pm_runtime_resume().
 	 */
 	if (HCD_HW_ACCESSIBLE(hcd))
 		rc = controller_suspend(dev);
 	return rc;
 }
 static int tegra_ehci_resume(struct device *dev)
 {
 	int rc;
 	rc = controller_resume(dev);
 	if (rc == 0) {
 		pm_runtime_disable(dev);
 		pm_runtime_set_active(dev);
 		pm_runtime_enable(dev);
 	}
 	return rc;
 }
 static int tegra_ehci_runtime_suspend(struct device *dev)
 {
 	return controller_suspend(dev);
 }
 static int tegra_ehci_runtime_resume(struct device *dev)
 {
 	return controller_resume(dev);
 }
 static const struct dev_pm_ops tegra_ehci_pm_ops = {
 	.suspend	= tegra_ehci_suspend,
 	.resume		= tegra_ehci_resume,
 	.runtime_suspend = tegra_ehci_runtime_suspend,
 	.runtime_resume	= tegra_ehci_runtime_resume,
 };
 #endif
 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
 #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
 void tegra_ehci_set_pts(struct usb_phy *x, u8 pts_val)
 {
 	unsigned long val;
 	struct usb_hcd *hcd = bus_to_hcd(x->otg->host);
 	void __iomem *base = hcd->regs;
 	val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
 	val &= ~TEGRA_USB_PORTSC1_PTS(3);
 	val |= TEGRA_USB_PORTSC1_PTS(pts_val & 3);
 	writel(val, base + TEGRA_USB_PORTSC1);
 }
 EXPORT_SYMBOL_GPL(tegra_ehci_set_pts);
 void tegra_ehci_set_phcd(struct usb_phy *x, bool enable)
 {
 	unsigned long val;
 	struct usb_hcd *hcd = bus_to_hcd(x->otg->host);
 	void __iomem *base = hcd->regs;
 	val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
 	if (enable)
 		val |= TEGRA_USB_PORTSC1_PHCD;
 	else
 		val &= ~TEGRA_USB_PORTSC1_PHCD;
 	writel(val, base + TEGRA_USB_PORTSC1);
 }
 EXPORT_SYMBOL_GPL(tegra_ehci_set_phcd);
 static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
 static int tegra_ehci_probe(struct platform_device *pdev)
 {
 	struct resource *res;
 	struct usb_hcd *hcd;
 	struct tegra_ehci_hcd *tegra;
 	struct tegra_ehci_platform_data *pdata;
 	int err = 0;
 	int irq;
 	int instance = pdev->id;
 	struct usb_phy *u_phy;
 	pdata = pdev->dev.platform_data;
 	if (!pdata) {
 		dev_err(&pdev->dev, "Platform data missing\n");
 		return -EINVAL;
 	}
 	/* Right now device-tree probed devices don't get dma_mask set.
 	 * Since shared usb code relies on it, set it here for now.
 	 * Once we have dma capability bindings this can go away.
 	 */
 	if (!pdev->dev.dma_mask)
 		pdev->dev.dma_mask = &tegra_ehci_dma_mask;
 	setup_vbus_gpio(pdev, pdata);
 	tegra = devm_kzalloc(&pdev->dev, sizeof(struct tegra_ehci_hcd),
 			     GFP_KERNEL);
 	if (!tegra)
 		return -ENOMEM;
 	hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
 					dev_name(&pdev->dev));
 	if (!hcd) {
 		dev_err(&pdev->dev, "Unable to create HCD\n");
 		return -ENOMEM;
 	}
 	platform_set_drvdata(pdev, tegra);
 	tegra->clk = devm_clk_get(&pdev->dev, NULL);
 	if (IS_ERR(tegra->clk)) {
 		dev_err(&pdev->dev, "Can't get ehci clock\n");
 		err = PTR_ERR(tegra->clk);
 		goto fail_clk;
 	}
 	err = clk_prepare_enable(tegra->clk);
 	if (err)
 		goto fail_clk;
 	tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
 		"nvidia,needs-double-reset");
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(&pdev->dev, "Failed to get I/O memory\n");
 		err = -ENXIO;
 		goto fail_io;
 	}
 	hcd->rsrc_start = res->start;
 	hcd->rsrc_len = resource_size(res);
 	hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 	if (!hcd->regs) {
 		dev_err(&pdev->dev, "Failed to remap I/O memory\n");
 		err = -ENOMEM;
 		goto fail_io;
 	}
 	/* This is pretty ugly and needs to be fixed when we do only
 	 * device-tree probing. Old code relies on the platform_device
 	 * numbering that we lack for device-tree-instantiated devices.
 	 */
 	if (instance < 0) {
 		switch (res->start) {
 		case TEGRA_USB_BASE:
 			instance = 0;
 			break;
 		case TEGRA_USB2_BASE:
 			instance = 1;
 			break;
 		case TEGRA_USB3_BASE:
 			instance = 2;
 			break;
 		default:
 			err = -ENODEV;
 			dev_err(&pdev->dev, "unknown usb instance\n");
 			goto fail_io;
 		}
 	}
 	tegra->phy = tegra_usb_phy_open(&pdev->dev, instance, hcd->regs,
 					pdata->phy_config,
 					TEGRA_USB_PHY_MODE_HOST);
 	if (IS_ERR(tegra->phy)) {
 		dev_err(&pdev->dev, "Failed to open USB phy\n");
 		err = -ENXIO;
 		goto fail_io;
 	}
-	usb_phy_init(&tegra->phy->u_phy);
 	hcd->phy = u_phy = &tegra->phy->u_phy;
+	usb_phy_init(hcd->phy);
 	u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
 			     GFP_KERNEL);
 	if (!u_phy->otg) {
 		dev_err(&pdev->dev, "Failed to alloc memory for otg\n");
 		err = -ENOMEM;
 		goto fail_io;
 	}
 	u_phy->otg->host = hcd_to_bus(hcd);
-	err = usb_phy_set_suspend(&tegra->phy->u_phy, 0);
+	err = usb_phy_set_suspend(hcd->phy, 0);
 	if (err) {
 		dev_err(&pdev->dev, "Failed to power on the phy\n");
 		goto fail;
 	}
 	tegra->host_resumed = 1;
 	tegra->ehci = hcd_to_ehci(hcd);
 	irq = platform_get_irq(pdev, 0);
 	if (!irq) {
 		dev_err(&pdev->dev, "Failed to get IRQ\n");
 		err = -ENODEV;
 		goto fail;
 	}
 #ifdef CONFIG_USB_OTG_UTILS
 	if (pdata->operating_mode == TEGRA_USB_OTG) {
 		tegra->transceiver =
 			devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
 		if (!IS_ERR_OR_NULL(tegra->transceiver))
 			otg_set_host(tegra->transceiver->otg, &hcd->self);
 	}
 #endif
 	err = usb_add_hcd(hcd, irq, IRQF_SHARED);
 	if (err) {
 		dev_err(&pdev->dev, "Failed to add USB HCD\n");
 		goto fail;
 	}
 	pm_runtime_set_active(&pdev->dev);
 	pm_runtime_get_noresume(&pdev->dev);
 	/* Don't skip the pm_runtime_forbid call if wakeup isn't working */
 	/* if (!pdata->power_down_on_bus_suspend) */
 		pm_runtime_forbid(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
 	pm_runtime_put_sync(&pdev->dev);
 	return err;
 fail:
 #ifdef CONFIG_USB_OTG_UTILS
 	if (!IS_ERR_OR_NULL(tegra->transceiver))
 		otg_set_host(tegra->transceiver->otg, NULL);
 #endif
-	usb_phy_shutdown(&tegra->phy->u_phy);
+	usb_phy_shutdown(hcd->phy);
 fail_io:
 	clk_disable_unprepare(tegra->clk);
 fail_clk:
 	usb_put_hcd(hcd);
 	return err;
 }
 static int tegra_ehci_remove(struct platform_device *pdev)
 {
 	struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
 	struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 	pm_runtime_get_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 	pm_runtime_put_noidle(&pdev->dev);
 #ifdef CONFIG_USB_OTG_UTILS
 	if (!IS_ERR_OR_NULL(tegra->transceiver))
 		otg_set_host(tegra->transceiver->otg, NULL);
 #endif
+	usb_phy_shutdown(hcd->phy);
 	usb_remove_hcd(hcd);
 	usb_put_hcd(hcd);
-	usb_phy_shutdown(&tegra->phy->u_phy);
 	clk_disable_unprepare(tegra->clk);
 	return 0;
 }
 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
 {
 	struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
 	struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 	if (hcd->driver->shutdown)
 		hcd->driver->shutdown(hcd);
 }
 static struct of_device_id tegra_ehci_of_match[] = {
 	{ .compatible = "nvidia,tegra20-ehci", },
 	{ },
 };
 static struct platform_driver tegra_ehci_driver = {
 	.probe		= tegra_ehci_probe,
 	.remove		= tegra_ehci_remove,
 	.shutdown	= tegra_ehci_hcd_shutdown,
 	.driver		= {
 		.name	= "tegra-ehci",
 		.of_match_table = tegra_ehci_of_match,
 #ifdef CONFIG_PM
 		.pm	= &tegra_ehci_pm_ops,
 #endif

drivers/usb/phy/tegra_usb_phy.c

Diff comments View file @ ab137d0

 /*
  * Copyright (C) 2010 Google, Inc.
  *
  * Author:
  *	Erik Gilling <konkers@google.com>
  *	Benoit Goby <benoit@android.com>
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
  * may be copied, distributed, and modified under those terms.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  */
 #include <linux/resource.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 #include <asm/mach-types.h>
 #include <linux/usb/tegra_usb_phy.h>
 #define TEGRA_USB_BASE		0xC5000000
 #define TEGRA_USB_SIZE		SZ_16K
 #define ULPI_VIEWPORT		0x170
 #define USB_SUSP_CTRL		0x400
 #define   USB_WAKE_ON_CNNT_EN_DEV	(1 << 3)
 #define   USB_WAKE_ON_DISCON_EN_DEV	(1 << 4)
 #define   USB_SUSP_CLR		(1 << 5)
 #define   USB_PHY_CLK_VALID	(1 << 7)
 #define   UTMIP_RESET			(1 << 11)
 #define   UHSIC_RESET			(1 << 11)
 #define   UTMIP_PHY_ENABLE		(1 << 12)
 #define   ULPI_PHY_ENABLE	(1 << 13)
 #define   USB_SUSP_SET		(1 << 14)
 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)	(((x) & 0x7) << 16)
 #define USB1_LEGACY_CTRL	0x410
 #define   USB1_NO_LEGACY_MODE			(1 << 0)
 #define   USB1_VBUS_SENSE_CTL_MASK		(3 << 1)
 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP	(0 << 1)
 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
 						(1 << 1)
 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD	(2 << 1)
 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD	(3 << 1)
 #define ULPI_TIMING_CTRL_0	0x424
 #define   ULPI_OUTPUT_PINMUX_BYP	(1 << 10)
 #define   ULPI_CLKOUT_PINMUX_BYP	(1 << 11)
 #define ULPI_TIMING_CTRL_1	0x428
 #define   ULPI_DATA_TRIMMER_LOAD	(1 << 0)
 #define   ULPI_DATA_TRIMMER_SEL(x)	(((x) & 0x7) << 1)
 #define   ULPI_STPDIRNXT_TRIMMER_LOAD	(1 << 16)
 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x)	(((x) & 0x7) << 17)
 #define   ULPI_DIR_TRIMMER_LOAD		(1 << 24)
 #define   ULPI_DIR_TRIMMER_SEL(x)	(((x) & 0x7) << 25)
 #define UTMIP_PLL_CFG1		0x804
 #define   UTMIP_XTAL_FREQ_COUNT(x)		(((x) & 0xfff) << 0)
 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)	(((x) & 0x1f) << 27)
 #define UTMIP_XCVR_CFG0		0x808
 #define   UTMIP_XCVR_SETUP(x)			(((x) & 0xf) << 0)
 #define   UTMIP_XCVR_LSRSLEW(x)			(((x) & 0x3) << 8)
 #define   UTMIP_XCVR_LSFSLEW(x)			(((x) & 0x3) << 10)
 #define   UTMIP_FORCE_PD_POWERDOWN		(1 << 14)
 #define   UTMIP_FORCE_PD2_POWERDOWN		(1 << 16)
 #define   UTMIP_FORCE_PDZI_POWERDOWN		(1 << 18)
 #define   UTMIP_XCVR_HSSLEW_MSB(x)		(((x) & 0x7f) << 25)
 #define UTMIP_BIAS_CFG0		0x80c
 #define   UTMIP_OTGPD			(1 << 11)
 #define   UTMIP_BIASPD			(1 << 10)
 #define UTMIP_HSRX_CFG0		0x810
 #define   UTMIP_ELASTIC_LIMIT(x)	(((x) & 0x1f) << 10)
 #define   UTMIP_IDLE_WAIT(x)		(((x) & 0x1f) << 15)
 #define UTMIP_HSRX_CFG1		0x814
 #define   UTMIP_HS_SYNC_START_DLY(x)	(((x) & 0x1f) << 1)
 #define UTMIP_TX_CFG0		0x820
 #define   UTMIP_FS_PREABMLE_J		(1 << 19)
 #define   UTMIP_HS_DISCON_DISABLE	(1 << 8)
 #define UTMIP_MISC_CFG0		0x824
 #define   UTMIP_DPDM_OBSERVE		(1 << 26)
 #define   UTMIP_DPDM_OBSERVE_SEL(x)	(((x) & 0xf) << 27)
 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J	UTMIP_DPDM_OBSERVE_SEL(0xf)
 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K	UTMIP_DPDM_OBSERVE_SEL(0xe)
 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
 #define   UTMIP_SUSPEND_EXIT_ON_EDGE	(1 << 22)
 #define UTMIP_MISC_CFG1		0x828
 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x)	(((x) & 0x1f) << 18)
 #define   UTMIP_PLLU_STABLE_COUNT(x)	(((x) & 0xfff) << 6)
 #define UTMIP_DEBOUNCE_CFG0	0x82c
 #define   UTMIP_BIAS_DEBOUNCE_A(x)	(((x) & 0xffff) << 0)
 #define UTMIP_BAT_CHRG_CFG0	0x830
 #define   UTMIP_PD_CHRG			(1 << 0)
 #define UTMIP_SPARE_CFG0	0x834
 #define   FUSE_SETUP_SEL		(1 << 3)
 #define UTMIP_XCVR_CFG1		0x838
 #define   UTMIP_FORCE_PDDISC_POWERDOWN	(1 << 0)
 #define   UTMIP_FORCE_PDCHRP_POWERDOWN	(1 << 2)
 #define   UTMIP_FORCE_PDDR_POWERDOWN	(1 << 4)
 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)	(((x) & 0xf) << 18)
 #define UTMIP_BIAS_CFG1		0x83c
 #define   UTMIP_BIAS_PDTRK_COUNT(x)	(((x) & 0x1f) << 3)
 static DEFINE_SPINLOCK(utmip_pad_lock);
 static int utmip_pad_count;
 struct tegra_xtal_freq {
 	int freq;
 	u8 enable_delay;
 	u8 stable_count;
 	u8 active_delay;
 	u8 xtal_freq_count;
 	u16 debounce;
 };
 static const struct tegra_xtal_freq tegra_freq_table[] = {
 	{
 		.freq = 12000000,
 		.enable_delay = 0x02,
 		.stable_count = 0x2F,
 		.active_delay = 0x04,
 		.xtal_freq_count = 0x76,
 		.debounce = 0x7530,
 	},
 	{
 		.freq = 13000000,
 		.enable_delay = 0x02,
 		.stable_count = 0x33,
 		.active_delay = 0x05,
 		.xtal_freq_count = 0x7F,
 		.debounce = 0x7EF4,
 	},
 	{
 		.freq = 19200000,
 		.enable_delay = 0x03,
 		.stable_count = 0x4B,
 		.active_delay = 0x06,
 		.xtal_freq_count = 0xBB,
 		.debounce = 0xBB80,
 	},
 	{
 		.freq = 26000000,
 		.enable_delay = 0x04,
 		.stable_count = 0x66,
 		.active_delay = 0x09,
 		.xtal_freq_count = 0xFE,
 		.debounce = 0xFDE8,
 	},
 };
 static struct tegra_utmip_config utmip_default[] = {
 	[0] = {
 		.hssync_start_delay = 9,
 		.idle_wait_delay = 17,
 		.elastic_limit = 16,
 		.term_range_adj = 6,
 		.xcvr_setup = 9,
 		.xcvr_lsfslew = 1,
 		.xcvr_lsrslew = 1,
 	},
 	[2] = {
 		.hssync_start_delay = 9,
 		.idle_wait_delay = 17,
 		.elastic_limit = 16,
 		.term_range_adj = 6,
 		.xcvr_setup = 9,
 		.xcvr_lsfslew = 2,
 		.xcvr_lsrslew = 2,
 	},
 };
 static int utmip_pad_open(struct tegra_usb_phy *phy)
 {
 	phy->pad_clk = clk_get_sys("utmip-pad", NULL);
 	if (IS_ERR(phy->pad_clk)) {
 		pr_err("%s: can't get utmip pad clock\n", __func__);
 		return PTR_ERR(phy->pad_clk);
 	}
 	if (phy->is_legacy_phy) {
 		phy->pad_regs = phy->regs;
 	} else {
 		phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
 		if (!phy->pad_regs) {
 			pr_err("%s: can't remap usb registers\n", __func__);
 			clk_put(phy->pad_clk);
 			return -ENOMEM;
 		}
 	}
 	return 0;
 }
 static void utmip_pad_close(struct tegra_usb_phy *phy)
 {
 	if (!phy->is_legacy_phy)
 		iounmap(phy->pad_regs);
 	clk_put(phy->pad_clk);
 }
 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
 {
 	unsigned long val, flags;
 	void __iomem *base = phy->pad_regs;
 	clk_prepare_enable(phy->pad_clk);
 	spin_lock_irqsave(&utmip_pad_lock, flags);
 	if (utmip_pad_count++ == 0) {
 		val = readl(base + UTMIP_BIAS_CFG0);
 		val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
 		writel(val, base + UTMIP_BIAS_CFG0);
 	}
 	spin_unlock_irqrestore(&utmip_pad_lock, flags);
 	clk_disable_unprepare(phy->pad_clk);
 }
 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 {
 	unsigned long val, flags;
 	void __iomem *base = phy->pad_regs;
 	if (!utmip_pad_count) {
 		pr_err("%s: utmip pad already powered off\n", __func__);
 		return -EINVAL;
 	}
 	clk_prepare_enable(phy->pad_clk);
 	spin_lock_irqsave(&utmip_pad_lock, flags);
 	if (--utmip_pad_count == 0) {
 		val = readl(base + UTMIP_BIAS_CFG0);
 		val |= UTMIP_OTGPD | UTMIP_BIASPD;
 		writel(val, base + UTMIP_BIAS_CFG0);
 	}
 	spin_unlock_irqrestore(&utmip_pad_lock, flags);
 	clk_disable_unprepare(phy->pad_clk);
 	return 0;
 }
 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
 {
 	unsigned long timeout = 2000;
 	do {
 		if ((readl(reg) & mask) == result)
 			return 0;
 		udelay(1);
 		timeout--;
 	} while (timeout);
 	return -1;
 }
 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
 {
 	unsigned long val;
 	void __iomem *base = phy->regs;
 	if (phy->is_legacy_phy) {
 		val = readl(base + USB_SUSP_CTRL);
 		val |= USB_SUSP_SET;
 		writel(val, base + USB_SUSP_CTRL);
 		udelay(10);
 		val = readl(base + USB_SUSP_CTRL);
 		val &= ~USB_SUSP_SET;
 		writel(val, base + USB_SUSP_CTRL);
 	} else
 		tegra_ehci_set_phcd(&phy->u_phy, true);
 	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
 		pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 }
 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
 {
 	unsigned long val;
 	void __iomem *base = phy->regs;
 	if (phy->is_legacy_phy) {
 		val = readl(base + USB_SUSP_CTRL);
 		val |= USB_SUSP_CLR;
 		writel(val, base + USB_SUSP_CTRL);
 		udelay(10);
 		val = readl(base + USB_SUSP_CTRL);
 		val &= ~USB_SUSP_CLR;
 		writel(val, base + USB_SUSP_CTRL);
 	} else
 		tegra_ehci_set_phcd(&phy->u_phy, false);
 	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 						     USB_PHY_CLK_VALID))
 		pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 }
 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
 {
 	unsigned long val;
 	void __iomem *base = phy->regs;
 	struct tegra_utmip_config *config = phy->config;
 	val = readl(base + USB_SUSP_CTRL);
 	val |= UTMIP_RESET;
 	writel(val, base + USB_SUSP_CTRL);
 	if (phy->is_legacy_phy) {
 		val = readl(base + USB1_LEGACY_CTRL);
 		val |= USB1_NO_LEGACY_MODE;
 		writel(val, base + USB1_LEGACY_CTRL);
 	}
 	val = readl(base + UTMIP_TX_CFG0);
 	val &= ~UTMIP_FS_PREABMLE_J;
 	writel(val, base + UTMIP_TX_CFG0);
 	val = readl(base + UTMIP_HSRX_CFG0);
 	val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
 	val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
 	val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
 	writel(val, base + UTMIP_HSRX_CFG0);
 	val = readl(base + UTMIP_HSRX_CFG1);
 	val &= ~UTMIP_HS_SYNC_START_DLY(~0);
 	val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
 	writel(val, base + UTMIP_HSRX_CFG1);
 	val = readl(base + UTMIP_DEBOUNCE_CFG0);
 	val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
 	val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
 	writel(val, base + UTMIP_DEBOUNCE_CFG0);
 	val = readl(base + UTMIP_MISC_CFG0);
 	val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
 	writel(val, base + UTMIP_MISC_CFG0);
 	val = readl(base + UTMIP_MISC_CFG1);
 	val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
 	val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
 		UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
 	writel(val, base + UTMIP_MISC_CFG1);
 	val = readl(base + UTMIP_PLL_CFG1);
 	val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
 	val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
 		UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
 	writel(val, base + UTMIP_PLL_CFG1);
 	if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
 		val = readl(base + USB_SUSP_CTRL);
 		val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
 		writel(val, base + USB_SUSP_CTRL);
 	}
 	utmip_pad_power_on(phy);
 	val = readl(base + UTMIP_XCVR_CFG0);
 	val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 		 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
 		 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
 		 UTMIP_XCVR_HSSLEW_MSB(~0));
 	val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
 	val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
 	val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
 	writel(val, base + UTMIP_XCVR_CFG0);
 	val = readl(base + UTMIP_XCVR_CFG1);
 	val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 		 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
 	val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
 	writel(val, base + UTMIP_XCVR_CFG1);
 	val = readl(base + UTMIP_BAT_CHRG_CFG0);
 	val &= ~UTMIP_PD_CHRG;
 	writel(val, base + UTMIP_BAT_CHRG_CFG0);
 	val = readl(base + UTMIP_BIAS_CFG1);
 	val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
 	val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
 	writel(val, base + UTMIP_BIAS_CFG1);
 	if (phy->is_legacy_phy) {
 		val = readl(base + UTMIP_SPARE_CFG0);
 		if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
 			val &= ~FUSE_SETUP_SEL;
 		else
 			val |= FUSE_SETUP_SEL;
 		writel(val, base + UTMIP_SPARE_CFG0);
 	} else {
 		val = readl(base + USB_SUSP_CTRL);
 		val |= UTMIP_PHY_ENABLE;
 		writel(val, base + USB_SUSP_CTRL);
 	}
 	val = readl(base + USB_SUSP_CTRL);
 	val &= ~UTMIP_RESET;
 	writel(val, base + USB_SUSP_CTRL);
 	if (phy->is_legacy_phy) {
 		val = readl(base + USB1_LEGACY_CTRL);
 		val &= ~USB1_VBUS_SENSE_CTL_MASK;
 		val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
 		writel(val, base + USB1_LEGACY_CTRL);
 		val = readl(base + USB_SUSP_CTRL);
 		val &= ~USB_SUSP_SET;
 		writel(val, base + USB_SUSP_CTRL);
 	}
 	utmi_phy_clk_enable(phy);
 	if (!phy->is_legacy_phy)
 		tegra_ehci_set_pts(&phy->u_phy, 0);
 	return 0;
 }
 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
 {
 	unsigned long val;
 	void __iomem *base = phy->regs;
 	utmi_phy_clk_disable(phy);
 	if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
 		val = readl(base + USB_SUSP_CTRL);
 		val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
 		val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
 		writel(val, base + USB_SUSP_CTRL);
 	}
 	val = readl(base + USB_SUSP_CTRL);
 	val |= UTMIP_RESET;
 	writel(val, base + USB_SUSP_CTRL);
 	val = readl(base + UTMIP_BAT_CHRG_CFG0);
 	val |= UTMIP_PD_CHRG;
 	writel(val, base + UTMIP_BAT_CHRG_CFG0);
 	val = readl(base + UTMIP_XCVR_CFG0);
 	val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 	       UTMIP_FORCE_PDZI_POWERDOWN;
 	writel(val, base + UTMIP_XCVR_CFG0);
 	val = readl(base + UTMIP_XCVR_CFG1);
 	val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 	       UTMIP_FORCE_PDDR_POWERDOWN;
 	writel(val, base + UTMIP_XCVR_CFG1);
 	return utmip_pad_power_off(phy);
 }
 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
 {
 	unsigned long val;
 	void __iomem *base = phy->regs;
 	val = readl(base + UTMIP_TX_CFG0);
 	val |= UTMIP_HS_DISCON_DISABLE;
 	writel(val, base + UTMIP_TX_CFG0);
 }
 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
 {
 	unsigned long val;
 	void __iomem *base = phy->regs;
 	val = readl(base + UTMIP_TX_CFG0);
 	val &= ~UTMIP_HS_DISCON_DISABLE;
 	writel(val, base + UTMIP_TX_CFG0);
 }
 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
 				   enum tegra_usb_phy_port_speed port_speed)
 {
 	unsigned long val;
 	void __iomem *base = phy->regs;
 	val = readl(base + UTMIP_MISC_CFG0);
 	val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
 	if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 		val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
 	else
 		val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
 	writel(val, base + UTMIP_MISC_CFG0);
 	udelay(1);
 	val = readl(base + UTMIP_MISC_CFG0);
 	val |= UTMIP_DPDM_OBSERVE;
 	writel(val, base + UTMIP_MISC_CFG0);
 	udelay(10);
 }
 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
 {
 	unsigned long val;
 	void __iomem *base = phy->regs;
 	val = readl(base + UTMIP_MISC_CFG0);
 	val &= ~UTMIP_DPDM_OBSERVE;
 	writel(val, base + UTMIP_MISC_CFG0);
 	udelay(10);
 }
 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
 {
 	int ret;
 	unsigned long val;
 	void __iomem *base = phy->regs;
 	struct tegra_ulpi_config *config = phy->config;
 	gpio_direction_output(config->reset_gpio, 0);
 	msleep(5);
 	gpio_direction_output(config->reset_gpio, 1);
 	clk_prepare_enable(phy->clk);
 	msleep(1);
 	val = readl(base + USB_SUSP_CTRL);
 	val |= UHSIC_RESET;
 	writel(val, base + USB_SUSP_CTRL);
 	val = readl(base + ULPI_TIMING_CTRL_0);
 	val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
 	writel(val, base + ULPI_TIMING_CTRL_0);
 	val = readl(base + USB_SUSP_CTRL);
 	val |= ULPI_PHY_ENABLE;
 	writel(val, base + USB_SUSP_CTRL);
 	val = 0;
 	writel(val, base + ULPI_TIMING_CTRL_1);
 	val |= ULPI_DATA_TRIMMER_SEL(4);
 	val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
 	val |= ULPI_DIR_TRIMMER_SEL(4);
 	writel(val, base + ULPI_TIMING_CTRL_1);
 	udelay(10);
 	val |= ULPI_DATA_TRIMMER_LOAD;
 	val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
 	val |= ULPI_DIR_TRIMMER_LOAD;
 	writel(val, base + ULPI_TIMING_CTRL_1);
 	/* Fix VbusInvalid due to floating VBUS */
 	ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
 	if (ret) {
 		pr_err("%s: ulpi write failed\n", __func__);
 		return ret;
 	}
 	ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
 	if (ret) {
 		pr_err("%s: ulpi write failed\n", __func__);
 		return ret;
 	}
 	val = readl(base + USB_SUSP_CTRL);
 	val |= USB_SUSP_CLR;
 	writel(val, base + USB_SUSP_CTRL);
 	udelay(100);
 	val = readl(base + USB_SUSP_CTRL);
 	val &= ~USB_SUSP_CLR;
 	writel(val, base + USB_SUSP_CTRL);
 	return 0;
 }
 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
 {
 	struct tegra_ulpi_config *config = phy->config;
 	clk_disable(phy->clk);
 	return gpio_direction_output(config->reset_gpio, 0);
 }
 static int	tegra_phy_init(struct usb_phy *x)
 {
 	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 	struct tegra_ulpi_config *ulpi_config;
 	int err;
 	if (phy->is_ulpi_phy) {
 		ulpi_config = phy->config;
 		phy->clk = clk_get_sys(NULL, ulpi_config->clk);
 		if (IS_ERR(phy->clk)) {
 			pr_err("%s: can't get ulpi clock\n", __func__);
 			err = -ENXIO;
 			goto err1;
 		}
 		if (!gpio_is_valid(ulpi_config->reset_gpio))
 			ulpi_config->reset_gpio =
 				of_get_named_gpio(phy->dev->of_node,
 						  "nvidia,phy-reset-gpio", 0);
 		if (!gpio_is_valid(ulpi_config->reset_gpio)) {
 			pr_err("%s: invalid reset gpio: %d\n", __func__,
 			       ulpi_config->reset_gpio);
 			err = -EINVAL;
 			goto err1;
 		}
 		gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
 		gpio_direction_output(ulpi_config->reset_gpio, 0);
 		phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
 		phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
 	} else {
 		err = utmip_pad_open(phy);
 		if (err < 0)
 			goto err1;
 	}
 	return 0;
 err1:
 	clk_disable_unprepare(phy->pll_u);
 	clk_put(phy->pll_u);
 	return err;
 }
 static void tegra_usb_phy_close(struct usb_phy *x)
 {
 	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 	if (phy->is_ulpi_phy)
 		clk_put(phy->clk);
 	else
 		utmip_pad_close(phy);
 	clk_disable_unprepare(phy->pll_u);
 	clk_put(phy->pll_u);
 	kfree(phy);
 }
 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 {
 	if (phy->is_ulpi_phy)
 		return ulpi_phy_power_on(phy);
 	else
 		return utmi_phy_power_on(phy);
 }
 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 {
 	if (phy->is_ulpi_phy)
 		return ulpi_phy_power_off(phy);
 	else
 		return utmi_phy_power_off(phy);
 }
 static int	tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
 {
 	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 	if (suspend)
 		return tegra_usb_phy_power_off(phy);
 	else
 		return tegra_usb_phy_power_on(phy);
 }
 struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
 	void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode)
 {
 	struct tegra_usb_phy *phy;
 	unsigned long parent_rate;
 	int i;
 	int err;
 	struct device_node *np = dev->of_node;
 	phy = kzalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
 	if (!phy)
 		return ERR_PTR(-ENOMEM);
 	phy->instance = instance;
 	phy->regs = regs;
 	phy->config = config;
 	phy->mode = phy_mode;
 	phy->dev = dev;
 	phy->is_legacy_phy =
 		of_property_read_bool(np, "nvidia,has-legacy-mode");
 	err = of_property_match_string(np, "phy_type", "ulpi");
 	if (err < 0)
 		phy->is_ulpi_phy = false;
 	else
 		phy->is_ulpi_phy = true;
 	if (!phy->config) {
 		if (phy->is_ulpi_phy) {
 			pr_err("%s: ulpi phy configuration missing", __func__);
 			err = -EINVAL;
 			goto err0;
 		} else {
 			phy->config = &utmip_default[instance];
 		}
 	}
 	phy->pll_u = clk_get_sys(NULL, "pll_u");
 	if (IS_ERR(phy->pll_u)) {
 		pr_err("Can't get pll_u clock\n");
 		err = PTR_ERR(phy->pll_u);
 		goto err0;
 	}
 	clk_prepare_enable(phy->pll_u);
 	parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
 	for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
 		if (tegra_freq_table[i].freq == parent_rate) {
 			phy->freq = &tegra_freq_table[i];
 			break;
 		}
 	}
 	if (!phy->freq) {
 		pr_err("invalid pll_u parent rate %ld\n", parent_rate);
 		err = -EINVAL;
 		goto err1;
 	}
 	phy->u_phy.init = tegra_phy_init;
 	phy->u_phy.shutdown = tegra_usb_phy_close;
 	phy->u_phy.set_suspend = tegra_usb_phy_suspend;
 	return phy;
 err1:
 	clk_disable_unprepare(phy->pll_u);
 	clk_put(phy->pll_u);
 err0:
 	kfree(phy);
 	return ERR_PTR(err);
 }
 EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
-void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
+void tegra_usb_phy_preresume(struct usb_phy *x)
 {
+	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 	if (!phy->is_ulpi_phy)
 		utmi_phy_preresume(phy);
 }
 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
-void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
+void tegra_usb_phy_postresume(struct usb_phy *x)
 {
+	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 	if (!phy->is_ulpi_phy)
 		utmi_phy_postresume(phy);
 }
 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
-void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
+void tegra_ehci_phy_restore_start(struct usb_phy *x,
 				 enum tegra_usb_phy_port_speed port_speed)
 {
+	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 	if (!phy->is_ulpi_phy)
 		utmi_phy_restore_start(phy, port_speed);
 }
 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
-void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
+void tegra_ehci_phy_restore_end(struct usb_phy *x)
 {
+	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 	if (!phy->is_ulpi_phy)
 		utmi_phy_restore_end(phy);
 }
 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);

include/linux/usb/tegra_usb_phy.h

Diff comments View file @ ab137d0

1	/*	1	/*
2	* Copyright (C) 2010 Google, Inc.	2	* Copyright (C) 2010 Google, Inc.
3	*	3	*
4	* This software is licensed under the terms of the GNU General Public	4	* This software is licensed under the terms of the GNU General Public
5	* License version 2, as published by the Free Software Foundation, and	5	* License version 2, as published by the Free Software Foundation, and
6	* may be copied, distributed, and modified under those terms.	6	* may be copied, distributed, and modified under those terms.
7	*	7	*
8	* This program is distributed in the hope that it will be useful,	8	* This program is distributed in the hope that it will be useful,
9	* but WITHOUT ANY WARRANTY; without even the implied warranty of	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11	* GNU General Public License for more details.	11	* GNU General Public License for more details.
12	*	12	*
13	*/	13	*/
14		14
15	#ifndef __TEGRA_USB_PHY_H	15	#ifndef __TEGRA_USB_PHY_H
16	#define __TEGRA_USB_PHY_H	16	#define __TEGRA_USB_PHY_H
17		17
18	#include <linux/clk.h>	18	#include <linux/clk.h>
19	#include <linux/usb/otg.h>	19	#include <linux/usb/otg.h>
20		20
21	struct tegra_utmip_config {	21	struct tegra_utmip_config {
22	u8 hssync_start_delay;	22	u8 hssync_start_delay;
23	u8 elastic_limit;	23	u8 elastic_limit;
24	u8 idle_wait_delay;	24	u8 idle_wait_delay;
25	u8 term_range_adj;	25	u8 term_range_adj;
26	u8 xcvr_setup;	26	u8 xcvr_setup;
27	u8 xcvr_lsfslew;	27	u8 xcvr_lsfslew;
28	u8 xcvr_lsrslew;	28	u8 xcvr_lsrslew;
29	};	29	};
30		30
31	struct tegra_ulpi_config {	31	struct tegra_ulpi_config {
32	int reset_gpio;	32	int reset_gpio;
33	const char *clk;	33	const char *clk;
34	};	34	};
35		35
36	enum tegra_usb_phy_port_speed {	36	enum tegra_usb_phy_port_speed {
37	TEGRA_USB_PHY_PORT_SPEED_FULL = 0,	37	TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
38	TEGRA_USB_PHY_PORT_SPEED_LOW,	38	TEGRA_USB_PHY_PORT_SPEED_LOW,
39	TEGRA_USB_PHY_PORT_SPEED_HIGH,	39	TEGRA_USB_PHY_PORT_SPEED_HIGH,
40	};	40	};
41		41
42	enum tegra_usb_phy_mode {	42	enum tegra_usb_phy_mode {
43	TEGRA_USB_PHY_MODE_DEVICE,	43	TEGRA_USB_PHY_MODE_DEVICE,
44	TEGRA_USB_PHY_MODE_HOST,	44	TEGRA_USB_PHY_MODE_HOST,
45	};	45	};
46		46
47	struct tegra_xtal_freq;	47	struct tegra_xtal_freq;
48		48
49	struct tegra_usb_phy {	49	struct tegra_usb_phy {
50	int instance;	50	int instance;
51	const struct tegra_xtal_freq *freq;	51	const struct tegra_xtal_freq *freq;
52	void __iomem *regs;	52	void __iomem *regs;
53	void __iomem *pad_regs;	53	void __iomem *pad_regs;
54	struct clk *clk;	54	struct clk *clk;
55	struct clk *pll_u;	55	struct clk *pll_u;
56	struct clk *pad_clk;	56	struct clk *pad_clk;
57	enum tegra_usb_phy_mode mode;	57	enum tegra_usb_phy_mode mode;
58	void *config;	58	void *config;
59	struct usb_phy *ulpi;	59	struct usb_phy *ulpi;
60	struct usb_phy u_phy;	60	struct usb_phy u_phy;
61	struct device *dev;	61	struct device *dev;
62	bool is_legacy_phy;	62	bool is_legacy_phy;
63	bool is_ulpi_phy;	63	bool is_ulpi_phy;
64	};	64	};
65		65
66	struct tegra_usb_phy tegra_usb_phy_open(struct device dev, int instance,	66	struct tegra_usb_phy tegra_usb_phy_open(struct device dev, int instance,
67	void __iomem regs, void config, enum tegra_usb_phy_mode phy_mode);	67	void __iomem regs, void config, enum tegra_usb_phy_mode phy_mode);
68		68
69	void tegra_usb_phy_preresume(struct tegra_usb_phy *phy);	69	void tegra_usb_phy_preresume(struct usb_phy *phy);
70		70
71	void tegra_usb_phy_postresume(struct tegra_usb_phy *phy);	71	void tegra_usb_phy_postresume(struct usb_phy *phy);
72		72
73	void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,	73	void tegra_ehci_phy_restore_start(struct usb_phy *phy,
74	enum tegra_usb_phy_port_speed port_speed);	74	enum tegra_usb_phy_port_speed port_speed);
75		75
76	void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy);	76	void tegra_ehci_phy_restore_end(struct usb_phy *phy);
77		77
78	void tegra_ehci_set_pts(struct usb_phy *x, u8 pts_val);	78	void tegra_ehci_set_pts(struct usb_phy *x, u8 pts_val);
79		79
80	void tegra_ehci_set_phcd(struct usb_phy *x, bool enable);	80	void tegra_ehci_set_phcd(struct usb_phy *x, bool enable);
81		81
82	#endif /* __TEGRA_USB_PHY_H */	82	#endif /* __TEGRA_USB_PHY_H */
83		83