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Commit abf1f5aafc1939db1f252e33914a3689e0f5830f

Authored by Krzysztof Helt
Committed by Jaroslav Kysela
1 parent a6a950a8a8
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

ALSA: opti93x: add support for Opti93x codec in cs4231-lib 

This patch adds support for WSS compatible Opti93x
codec to the cs4231-lib.

Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Tested-by: Rene Herman <rene.herman@gmail.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Jaroslav Kysela <perex@perex.cz>

Showing 3 changed files with 120 additions and 9 deletions Inline Diff

include/sound/cs4231-regs.h
Diff comments   View file @ abf1f5a
1 #ifndef __SOUND_CS4231_REGS_H 1 #ifndef __SOUND_CS4231_REGS_H
2 #define __SOUND_CS4231_REGS_H 2 #define __SOUND_CS4231_REGS_H
3 3
4 /* 4 /*
5 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 5 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
6 * Definitions for CS4231 & InterWave chips & compatible chips registers 6 * Definitions for CS4231 & InterWave chips & compatible chips registers
7 * 7 *
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * 22 *
23 */ 23 */
24 24
25 /* IO ports */ 25 /* IO ports */
26 26
27 #define CS4231P(x) (c_d_c_CS4231##x) 27 #define CS4231P(x) (c_d_c_CS4231##x)
28 28
29 #define c_d_c_CS4231REGSEL 0 29 #define c_d_c_CS4231REGSEL 0
30 #define c_d_c_CS4231REG 1 30 #define c_d_c_CS4231REG 1
31 #define c_d_c_CS4231STATUS 2 31 #define c_d_c_CS4231STATUS 2
32 #define c_d_c_CS4231PIO 3 32 #define c_d_c_CS4231PIO 3
33 33
34 /* codec registers */ 34 /* codec registers */
35 35
36 #define CS4231_LEFT_INPUT 0x00 /* left input control */ 36 #define CS4231_LEFT_INPUT 0x00 /* left input control */
37 #define CS4231_RIGHT_INPUT 0x01 /* right input control */ 37 #define CS4231_RIGHT_INPUT 0x01 /* right input control */
38 #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */ 38 #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
39 #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */ 39 #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
40 #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */ 40 #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
41 #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */ 41 #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
42 #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */ 42 #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
43 #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */ 43 #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
44 #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */ 44 #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
45 #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */ 45 #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
46 #define CS4231_PIN_CTRL 0x0a /* pin control */ 46 #define CS4231_PIN_CTRL 0x0a /* pin control */
47 #define CS4231_TEST_INIT 0x0b /* test and initialization */ 47 #define CS4231_TEST_INIT 0x0b /* test and initialization */
48 #define CS4231_MISC_INFO 0x0c /* miscellaneous information */ 48 #define CS4231_MISC_INFO 0x0c /* miscellaneous information */
49 #define CS4231_LOOPBACK 0x0d /* loopback control */ 49 #define CS4231_LOOPBACK 0x0d /* loopback control */
50 #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */ 50 #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
51 #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */ 51 #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
52 #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */ 52 #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
53 #define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */ 53 #define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */
54 #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */ 54 #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
55 #define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */ 55 #define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */
56 #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */ 56 #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
57 #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */ 57 #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
58 #define CS4231_TIMER_LOW 0x14 /* timer low byte */ 58 #define CS4231_TIMER_LOW 0x14 /* timer low byte */
59 #define CS4231_TIMER_HIGH 0x15 /* timer high byte */ 59 #define CS4231_TIMER_HIGH 0x15 /* timer high byte */
60 #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */ 60 #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
61 #define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */ 61 #define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */
62 #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */ 62 #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
63 #define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */ 63 #define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */
64 #define CS4236_EXT_REG 0x17 /* extended register access */ 64 #define CS4236_EXT_REG 0x17 /* extended register access */
65 #define CS4231_IRQ_STATUS 0x18 /* irq status register */ 65 #define CS4231_IRQ_STATUS 0x18 /* irq status register */
66 #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */ 66 #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
67 #define CS4231_VERSION 0x19 /* CS4231(A) - version values */ 67 #define CS4231_VERSION 0x19 /* CS4231(A) - version values */
68 #define CS4231_MONO_CTRL 0x1a /* mono input/output control */ 68 #define CS4231_MONO_CTRL 0x1a /* mono input/output control */
69 #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */ 69 #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
70 #define AD1845_PWR_DOWN 0x1b /* power down control */ 70 #define AD1845_PWR_DOWN 0x1b /* power down control */
71 #define CS4235_LEFT_MASTER 0x1b /* left master output control */ 71 #define CS4235_LEFT_MASTER 0x1b /* left master output control */
72 #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */ 72 #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
73 #define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */ 73 #define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
74 #define AD1845_CLOCK 0x1d /* crystal clock select and total power down */ 74 #define AD1845_CLOCK 0x1d /* crystal clock select and total power down */
75 #define CS4235_RIGHT_MASTER 0x1d /* right master output control */ 75 #define CS4235_RIGHT_MASTER 0x1d /* right master output control */
76 #define CS4231_REC_UPR_CNT 0x1e /* record upper count */ 76 #define CS4231_REC_UPR_CNT 0x1e /* record upper count */
77 #define CS4231_REC_LWR_CNT 0x1f /* record lower count */ 77 #define CS4231_REC_LWR_CNT 0x1f /* record lower count */
78 78
79 /* definitions for codec register select port - CODECP( REGSEL ) */ 79 /* definitions for codec register select port - CODECP( REGSEL ) */
80 80
81 #define CS4231_INIT 0x80 /* CODEC is initializing */ 81 #define CS4231_INIT 0x80 /* CODEC is initializing */
82 #define CS4231_MCE 0x40 /* mode change enable */ 82 #define CS4231_MCE 0x40 /* mode change enable */
83 #define CS4231_TRD 0x20 /* transfer request disable */ 83 #define CS4231_TRD 0x20 /* transfer request disable */
84 84
85 /* definitions for codec status register - CODECP( STATUS ) */ 85 /* definitions for codec status register - CODECP( STATUS ) */
86 86
87 #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */ 87 #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
88 88
89 /* definitions for codec irq status */ 89 /* definitions for codec irq status */
90 90
91 #define CS4231_PLAYBACK_IRQ 0x10 91 #define CS4231_PLAYBACK_IRQ 0x10
92 #define CS4231_RECORD_IRQ 0x20 92 #define CS4231_RECORD_IRQ 0x20
93 #define CS4231_TIMER_IRQ 0x40 93 #define CS4231_TIMER_IRQ 0x40
94 #define CS4231_ALL_IRQS 0x70 94 #define CS4231_ALL_IRQS 0x70
95 #define CS4231_REC_UNDERRUN 0x08 95 #define CS4231_REC_UNDERRUN 0x08
96 #define CS4231_REC_OVERRUN 0x04 96 #define CS4231_REC_OVERRUN 0x04
97 #define CS4231_PLY_OVERRUN 0x02 97 #define CS4231_PLY_OVERRUN 0x02
98 #define CS4231_PLY_UNDERRUN 0x01 98 #define CS4231_PLY_UNDERRUN 0x01
99 99
100 /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */ 100 /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
101 101
102 #define CS4231_ENABLE_MIC_GAIN 0x20 102 #define CS4231_ENABLE_MIC_GAIN 0x20
103 103
104 #define CS4231_MIXS_LINE 0x00 104 #define CS4231_MIXS_LINE 0x00
105 #define CS4231_MIXS_AUX1 0x40 105 #define CS4231_MIXS_AUX1 0x40
106 #define CS4231_MIXS_MIC 0x80 106 #define CS4231_MIXS_MIC 0x80
107 #define CS4231_MIXS_ALL 0xc0 107 #define CS4231_MIXS_ALL 0xc0
108 108
109 /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */ 109 /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
110 110
111 #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */ 111 #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
112 #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */ 112 #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
113 #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */ 113 #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
114 #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */ 114 #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
115 #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */ 115 #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
116 #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */ 116 #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
117 #define CS4231_STEREO 0x10 /* stereo mode */ 117 #define CS4231_STEREO 0x10 /* stereo mode */
118 /* bits 3-1 define frequency divisor */ 118 /* bits 3-1 define frequency divisor */
119 #define CS4231_XTAL1 0x00 /* 24.576 crystal */ 119 #define CS4231_XTAL1 0x00 /* 24.576 crystal */
120 #define CS4231_XTAL2 0x01 /* 16.9344 crystal */ 120 #define CS4231_XTAL2 0x01 /* 16.9344 crystal */
121 121
122 /* definitions for interface control register - CS4231_IFACE_CTRL */ 122 /* definitions for interface control register - CS4231_IFACE_CTRL */
123 123
124 #define CS4231_RECORD_PIO 0x80 /* record PIO enable */ 124 #define CS4231_RECORD_PIO 0x80 /* record PIO enable */
125 #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */ 125 #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
126 #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */ 126 #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
127 #define CS4231_AUTOCALIB 0x08 /* auto calibrate */ 127 #define CS4231_AUTOCALIB 0x08 /* auto calibrate */
128 #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */ 128 #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
129 #define CS4231_RECORD_ENABLE 0x02 /* record enable */ 129 #define CS4231_RECORD_ENABLE 0x02 /* record enable */
130 #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */ 130 #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
131 131
132 /* definitions for pin control register - CS4231_PIN_CTRL */ 132 /* definitions for pin control register - CS4231_PIN_CTRL */
133 133
134 #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */ 134 #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
135 #define CS4231_XCTL1 0x40 /* external control #1 */ 135 #define CS4231_XCTL1 0x40 /* external control #1 */
136 #define CS4231_XCTL0 0x80 /* external control #0 */ 136 #define CS4231_XCTL0 0x80 /* external control #0 */
137 137
138 /* definitions for test and init register - CS4231_TEST_INIT */ 138 /* definitions for test and init register - CS4231_TEST_INIT */
139 139
140 #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */ 140 #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
141 #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */ 141 #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
142 142
143 /* definitions for misc control register - CS4231_MISC_INFO */ 143 /* definitions for misc control register - CS4231_MISC_INFO */
144 144
145 #define CS4231_MODE2 0x40 /* MODE 2 */ 145 #define CS4231_MODE2 0x40 /* MODE 2 */
146 #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */ 146 #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
147 #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */ 147 #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
148 148
149 /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */ 149 /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
150 150
151 #define CS4231_DACZ 0x01 /* zero DAC when underrun */ 151 #define CS4231_DACZ 0x01 /* zero DAC when underrun */
152 #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */ 152 #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
153 #define CS4231_OLB 0x80 /* output level bit */ 153 #define CS4231_OLB 0x80 /* output level bit */
154 154
155 /* definitions for Extended Registers - CS4236+ */ 155 /* definitions for Extended Registers - CS4236+ */
156 156
157 #define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f)) 157 #define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f))
158 #define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8) 158 #define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8)
159 159
160 #define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */ 160 #define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */
161 #define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */ 161 #define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */
162 #define CS4236_LEFT_MIC 0x28 /* left MIC volume */ 162 #define CS4236_LEFT_MIC 0x28 /* left MIC volume */
163 #define CS4236_RIGHT_MIC 0x38 /* right MIC volume */ 163 #define CS4236_RIGHT_MIC 0x38 /* right MIC volume */
164 #define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */ 164 #define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */
165 #define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */ 165 #define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */
166 #define CS4236_LEFT_FM 0x68 /* left FM volume */ 166 #define CS4236_LEFT_FM 0x68 /* left FM volume */
167 #define CS4236_RIGHT_FM 0x78 /* right FM volume */ 167 #define CS4236_RIGHT_FM 0x78 /* right FM volume */
168 #define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */ 168 #define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */
169 #define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */ 169 #define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */
170 #define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */ 170 #define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */
171 #define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */ 171 #define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */
172 #define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */ 172 #define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */
173 #define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */ 173 #define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */
174 #define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */ 174 #define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */
175 #define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */ 175 #define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */
176 #define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */ 176 #define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */
177 #define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */ 177 #define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */
178 #define CS4236_VERSION 0x9c /* chip version and ID */ 178 #define CS4236_VERSION 0x9c /* chip version and ID */
179 179
180 /* definitions for extended registers - OPTI93X */
181 #define OPTi931_AUX_LEFT_INPUT 0x10
182 #define OPTi931_AUX_RIGHT_INPUT 0x11
183 #define OPTi93X_MIC_LEFT_INPUT 0x14
184 #define OPTi93X_MIC_RIGHT_INPUT 0x15
185 #define OPTi93X_OUT_LEFT 0x16
186 #define OPTi93X_OUT_RIGHT 0x17
187
180 #endif /* __SOUND_CS4231_REGS_H */ 188 #endif /* __SOUND_CS4231_REGS_H */
181 189
include/sound/cs4231.h
Diff comments   View file @ abf1f5a
1 #ifndef __SOUND_CS4231_H 1 #ifndef __SOUND_CS4231_H
2 #define __SOUND_CS4231_H 2 #define __SOUND_CS4231_H
3 3
4 /* 4 /*
5 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 5 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
6 * Definitions for CS4231 & InterWave chips & compatible chips 6 * Definitions for CS4231 & InterWave chips & compatible chips
7 * 7 *
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * 22 *
23 */ 23 */
24 24
25 #include "control.h" 25 #include "control.h"
26 #include "pcm.h" 26 #include "pcm.h"
27 #include "timer.h" 27 #include "timer.h"
28 28
29 #include "cs4231-regs.h" 29 #include "cs4231-regs.h"
30 30
31 /* defines for codec.mode */ 31 /* defines for codec.mode */
32 32
33 #define CS4231_MODE_NONE 0x0000 33 #define CS4231_MODE_NONE 0x0000
34 #define CS4231_MODE_PLAY 0x0001 34 #define CS4231_MODE_PLAY 0x0001
35 #define CS4231_MODE_RECORD 0x0002 35 #define CS4231_MODE_RECORD 0x0002
36 #define CS4231_MODE_TIMER 0x0004 36 #define CS4231_MODE_TIMER 0x0004
37 #define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER) 37 #define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
38 38
39 /* defines for codec.hardware */ 39 /* defines for codec.hardware */
40 40
41 #define CS4231_HW_DETECT 0x0000 /* let CS4231 driver detect chip */ 41 #define CS4231_HW_DETECT 0x0000 /* let CS4231 driver detect chip */
42 #define CS4231_HW_DETECT3 0x0001 /* allow mode 3 */ 42 #define CS4231_HW_DETECT3 0x0001 /* allow mode 3 */
43 #define CS4231_HW_TYPE_MASK 0xff00 /* type mask */ 43 #define CS4231_HW_TYPE_MASK 0xff00 /* type mask */
44 #define CS4231_HW_CS4231_MASK 0x0100 /* CS4231 serie */ 44 #define CS4231_HW_CS4231_MASK 0x0100 /* CS4231 serie */
45 #define CS4231_HW_CS4231 0x0100 /* CS4231 chip */ 45 #define CS4231_HW_CS4231 0x0100 /* CS4231 chip */
46 #define CS4231_HW_CS4231A 0x0101 /* CS4231A chip */ 46 #define CS4231_HW_CS4231A 0x0101 /* CS4231A chip */
47 #define CS4231_HW_AD1845 0x0102 /* AD1845 chip */ 47 #define CS4231_HW_AD1845 0x0102 /* AD1845 chip */
48 #define CS4231_HW_CS4232_MASK 0x0200 /* CS4232 serie (has control ports) */ 48 #define CS4231_HW_CS4232_MASK 0x0200 /* CS4232 serie (has control ports) */
49 #define CS4231_HW_CS4232 0x0200 /* CS4232 */ 49 #define CS4231_HW_CS4232 0x0200 /* CS4232 */
50 #define CS4231_HW_CS4232A 0x0201 /* CS4232A */ 50 #define CS4231_HW_CS4232A 0x0201 /* CS4232A */
51 #define CS4231_HW_CS4236 0x0202 /* CS4236 */ 51 #define CS4231_HW_CS4236 0x0202 /* CS4236 */
52 #define CS4231_HW_CS4236B_MASK 0x0400 /* CS4236B serie (has extended control regs) */ 52 #define CS4231_HW_CS4236B_MASK 0x0400 /* CS4236B serie (has extended control regs) */
53 #define CS4231_HW_CS4235 0x0400 /* CS4235 - Crystal Clear (tm) stereo enhancement */ 53 #define CS4231_HW_CS4235 0x0400 /* CS4235 - Crystal Clear (tm) stereo enhancement */
54 #define CS4231_HW_CS4236B 0x0401 /* CS4236B */ 54 #define CS4231_HW_CS4236B 0x0401 /* CS4236B */
55 #define CS4231_HW_CS4237B 0x0402 /* CS4237B - SRS 3D */ 55 #define CS4231_HW_CS4237B 0x0402 /* CS4237B - SRS 3D */
56 #define CS4231_HW_CS4238B 0x0403 /* CS4238B - QSOUND 3D */ 56 #define CS4231_HW_CS4238B 0x0403 /* CS4238B - QSOUND 3D */
57 #define CS4231_HW_CS4239 0x0404 /* CS4239 - Crystal Clear (tm) stereo enhancement */ 57 #define CS4231_HW_CS4239 0x0404 /* CS4239 - Crystal Clear (tm) stereo enhancement */
58 /* compatible, but clones */ 58 /* compatible, but clones */
59 #define CS4231_HW_INTERWAVE 0x1000 /* InterWave chip */ 59 #define CS4231_HW_INTERWAVE 0x1000 /* InterWave chip */
60 #define CS4231_HW_OPL3SA2 0x1101 /* OPL3-SA2 chip, similar to cs4231 */ 60 #define CS4231_HW_OPL3SA2 0x1101 /* OPL3-SA2 chip, similar to cs4231 */
61 #define CS4231_HW_OPTI93X 0x1102 /* Opti 930/931/933 */
61 62
62 /* defines for codec.hwshare */ 63 /* defines for codec.hwshare */
63 #define CS4231_HWSHARE_IRQ (1<<0) 64 #define CS4231_HWSHARE_IRQ (1<<0)
64 #define CS4231_HWSHARE_DMA1 (1<<1) 65 #define CS4231_HWSHARE_DMA1 (1<<1)
65 #define CS4231_HWSHARE_DMA2 (1<<2) 66 #define CS4231_HWSHARE_DMA2 (1<<2)
66 67
67 struct snd_cs4231 { 68 struct snd_cs4231 {
68 unsigned long port; /* base i/o port */ 69 unsigned long port; /* base i/o port */
69 struct resource *res_port; 70 struct resource *res_port;
70 unsigned long cport; /* control base i/o port (CS4236) */ 71 unsigned long cport; /* control base i/o port (CS4236) */
71 struct resource *res_cport; 72 struct resource *res_cport;
72 int irq; /* IRQ line */ 73 int irq; /* IRQ line */
73 int dma1; /* playback DMA */ 74 int dma1; /* playback DMA */
74 int dma2; /* record DMA */ 75 int dma2; /* record DMA */
75 unsigned short version; /* version of CODEC chip */ 76 unsigned short version; /* version of CODEC chip */
76 unsigned short mode; /* see to CS4231_MODE_XXXX */ 77 unsigned short mode; /* see to CS4231_MODE_XXXX */
77 unsigned short hardware; /* see to CS4231_HW_XXXX */ 78 unsigned short hardware; /* see to CS4231_HW_XXXX */
78 unsigned short hwshare; /* shared resources */ 79 unsigned short hwshare; /* shared resources */
79 unsigned short single_dma:1, /* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */ 80 unsigned short single_dma:1, /* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */
80 ebus_flag:1; /* SPARC: EBUS present */ 81 ebus_flag:1; /* SPARC: EBUS present */
81 82
82 struct snd_card *card; 83 struct snd_card *card;
83 struct snd_pcm *pcm; 84 struct snd_pcm *pcm;
84 struct snd_pcm_substream *playback_substream; 85 struct snd_pcm_substream *playback_substream;
85 struct snd_pcm_substream *capture_substream; 86 struct snd_pcm_substream *capture_substream;
86 struct snd_timer *timer; 87 struct snd_timer *timer;
87 88
88 unsigned char image[32]; /* registers image */ 89 unsigned char image[32]; /* registers image */
89 unsigned char eimage[32]; /* extended registers image */ 90 unsigned char eimage[32]; /* extended registers image */
90 unsigned char cimage[16]; /* control registers image */ 91 unsigned char cimage[16]; /* control registers image */
91 int mce_bit; 92 int mce_bit;
92 int calibrate_mute; 93 int calibrate_mute;
93 int sw_3d_bit; 94 int sw_3d_bit;
94 unsigned int p_dma_size; 95 unsigned int p_dma_size;
95 unsigned int c_dma_size; 96 unsigned int c_dma_size;
96 97
97 spinlock_t reg_lock; 98 spinlock_t reg_lock;
98 struct mutex mce_mutex; 99 struct mutex mce_mutex;
99 struct mutex open_mutex; 100 struct mutex open_mutex;
100 101
101 int (*rate_constraint) (struct snd_pcm_runtime *runtime); 102 int (*rate_constraint) (struct snd_pcm_runtime *runtime);
102 void (*set_playback_format) (struct snd_cs4231 *chip, struct snd_pcm_hw_params *hw_params, unsigned char pdfr); 103 void (*set_playback_format) (struct snd_cs4231 *chip, struct snd_pcm_hw_params *hw_params, unsigned char pdfr);
103 void (*set_capture_format) (struct snd_cs4231 *chip, struct snd_pcm_hw_params *hw_params, unsigned char cdfr); 104 void (*set_capture_format) (struct snd_cs4231 *chip, struct snd_pcm_hw_params *hw_params, unsigned char cdfr);
104 void (*trigger) (struct snd_cs4231 *chip, unsigned int what, int start); 105 void (*trigger) (struct snd_cs4231 *chip, unsigned int what, int start);
105 #ifdef CONFIG_PM 106 #ifdef CONFIG_PM
106 void (*suspend) (struct snd_cs4231 *chip); 107 void (*suspend) (struct snd_cs4231 *chip);
107 void (*resume) (struct snd_cs4231 *chip); 108 void (*resume) (struct snd_cs4231 *chip);
108 #endif 109 #endif
109 void *dma_private_data; 110 void *dma_private_data;
110 int (*claim_dma) (struct snd_cs4231 *chip, void *dma_private_data, int dma); 111 int (*claim_dma) (struct snd_cs4231 *chip, void *dma_private_data, int dma);
111 int (*release_dma) (struct snd_cs4231 *chip, void *dma_private_data, int dma); 112 int (*release_dma) (struct snd_cs4231 *chip, void *dma_private_data, int dma);
112 }; 113 };
113 114
114 /* exported functions */ 115 /* exported functions */
115 116
116 void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val); 117 void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val);
117 unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg); 118 unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg);
118 void snd_cs4236_ext_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val); 119 void snd_cs4236_ext_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val);
119 unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg); 120 unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg);
120 void snd_cs4231_mce_up(struct snd_cs4231 *chip); 121 void snd_cs4231_mce_up(struct snd_cs4231 *chip);
121 void snd_cs4231_mce_down(struct snd_cs4231 *chip); 122 void snd_cs4231_mce_down(struct snd_cs4231 *chip);
123
124 void snd_cs4231_overrange(struct snd_cs4231 *chip);
122 125
123 irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id); 126 irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id);
124 127
125 const char *snd_cs4231_chip_id(struct snd_cs4231 *chip); 128 const char *snd_cs4231_chip_id(struct snd_cs4231 *chip);
126 129
127 int snd_cs4231_create(struct snd_card *card, 130 int snd_cs4231_create(struct snd_card *card,
128 unsigned long port, 131 unsigned long port,
129 unsigned long cport, 132 unsigned long cport,
130 int irq, int dma1, int dma2, 133 int irq, int dma1, int dma2,
131 unsigned short hardware, 134 unsigned short hardware,
132 unsigned short hwshare, 135 unsigned short hwshare,
133 struct snd_cs4231 ** rchip); 136 struct snd_cs4231 ** rchip);
134 int snd_cs4231_pcm(struct snd_cs4231 * chip, int device, struct snd_pcm **rpcm); 137 int snd_cs4231_pcm(struct snd_cs4231 * chip, int device, struct snd_pcm **rpcm);
135 int snd_cs4231_timer(struct snd_cs4231 * chip, int device, struct snd_timer **rtimer); 138 int snd_cs4231_timer(struct snd_cs4231 * chip, int device, struct snd_timer **rtimer);
136 int snd_cs4231_mixer(struct snd_cs4231 * chip); 139 int snd_cs4231_mixer(struct snd_cs4231 * chip);
137 140
138 int snd_cs4236_create(struct snd_card *card, 141 int snd_cs4236_create(struct snd_card *card,
139 unsigned long port, 142 unsigned long port,
140 unsigned long cport, 143 unsigned long cport,
141 int irq, int dma1, int dma2, 144 int irq, int dma1, int dma2,
142 unsigned short hardware, 145 unsigned short hardware,
143 unsigned short hwshare, 146 unsigned short hwshare,
144 struct snd_cs4231 ** rchip); 147 struct snd_cs4231 ** rchip);
145 int snd_cs4236_pcm(struct snd_cs4231 * chip, int device, struct snd_pcm **rpcm); 148 int snd_cs4236_pcm(struct snd_cs4231 * chip, int device, struct snd_pcm **rpcm);
146 int snd_cs4236_mixer(struct snd_cs4231 * chip); 149 int snd_cs4236_mixer(struct snd_cs4231 * chip);
147 150
148 /* 151 /*
149 * mixer library 152 * mixer library
150 */ 153 */
151 154
152 #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \ 155 #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
153 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 156 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
154 .info = snd_cs4231_info_single, \ 157 .info = snd_cs4231_info_single, \
155 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \ 158 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
156 .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } 159 .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
157 160
158 int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo); 161 int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo);
159 int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); 162 int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
160 int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); 163 int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
161 164
162 #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ 165 #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
163 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 166 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
164 .info = snd_cs4231_info_double, \ 167 .info = snd_cs4231_info_double, \
165 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \ 168 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
166 .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } 169 .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
167 170
168 int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo); 171 int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo);
169 int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); 172 int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
170 int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); 173 int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
171 174
172 #endif /* __SOUND_CS4231_H */ 175 #endif /* __SOUND_CS4231_H */
173 176
sound/isa/cs423x/cs4231_lib.c
Diff comments   View file @ abf1f5a
1 /* 1 /*
2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
3 * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips 3 * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
4 * 4 *
5 * Bugs: 5 * Bugs:
6 * - sometimes record brokes playback with WSS portion of 6 * - sometimes record brokes playback with WSS portion of
7 * Yamaha OPL3-SA3 chip 7 * Yamaha OPL3-SA3 chip
8 * - CS4231 (GUS MAX) - still trouble with occasional noises 8 * - CS4231 (GUS MAX) - still trouble with occasional noises
9 * - broken initialization? 9 * - broken initialization?
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or 13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version. 14 * (at your option) any later version.
15 * 15 *
16 * This program is distributed in the hope that it will be useful, 16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * You should have received a copy of the GNU General Public License 21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software 22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * 24 *
25 */ 25 */
26 26
27 #include <linux/delay.h> 27 #include <linux/delay.h>
28 #include <linux/pm.h> 28 #include <linux/pm.h>
29 #include <linux/init.h> 29 #include <linux/init.h>
30 #include <linux/interrupt.h> 30 #include <linux/interrupt.h>
31 #include <linux/slab.h> 31 #include <linux/slab.h>
32 #include <linux/ioport.h> 32 #include <linux/ioport.h>
33 #include <sound/core.h> 33 #include <sound/core.h>
34 #include <sound/cs4231.h> 34 #include <sound/cs4231.h>
35 #include <sound/pcm_params.h> 35 #include <sound/pcm_params.h>
36 36
37 #include <asm/io.h> 37 #include <asm/io.h>
38 #include <asm/dma.h> 38 #include <asm/dma.h>
39 #include <asm/irq.h> 39 #include <asm/irq.h>
40 40
41 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); 41 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
42 MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips"); 42 MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
43 MODULE_LICENSE("GPL"); 43 MODULE_LICENSE("GPL");
44 44
45 #if 0 45 #if 0
46 #define SNDRV_DEBUG_MCE 46 #define SNDRV_DEBUG_MCE
47 #endif 47 #endif
48 48
49 /* 49 /*
50 * Some variables 50 * Some variables
51 */ 51 */
52 52
53 static unsigned char freq_bits[14] = { 53 static unsigned char freq_bits[14] = {
54 /* 5510 */ 0x00 | CS4231_XTAL2, 54 /* 5510 */ 0x00 | CS4231_XTAL2,
55 /* 6620 */ 0x0E | CS4231_XTAL2, 55 /* 6620 */ 0x0E | CS4231_XTAL2,
56 /* 8000 */ 0x00 | CS4231_XTAL1, 56 /* 8000 */ 0x00 | CS4231_XTAL1,
57 /* 9600 */ 0x0E | CS4231_XTAL1, 57 /* 9600 */ 0x0E | CS4231_XTAL1,
58 /* 11025 */ 0x02 | CS4231_XTAL2, 58 /* 11025 */ 0x02 | CS4231_XTAL2,
59 /* 16000 */ 0x02 | CS4231_XTAL1, 59 /* 16000 */ 0x02 | CS4231_XTAL1,
60 /* 18900 */ 0x04 | CS4231_XTAL2, 60 /* 18900 */ 0x04 | CS4231_XTAL2,
61 /* 22050 */ 0x06 | CS4231_XTAL2, 61 /* 22050 */ 0x06 | CS4231_XTAL2,
62 /* 27042 */ 0x04 | CS4231_XTAL1, 62 /* 27042 */ 0x04 | CS4231_XTAL1,
63 /* 32000 */ 0x06 | CS4231_XTAL1, 63 /* 32000 */ 0x06 | CS4231_XTAL1,
64 /* 33075 */ 0x0C | CS4231_XTAL2, 64 /* 33075 */ 0x0C | CS4231_XTAL2,
65 /* 37800 */ 0x08 | CS4231_XTAL2, 65 /* 37800 */ 0x08 | CS4231_XTAL2,
66 /* 44100 */ 0x0A | CS4231_XTAL2, 66 /* 44100 */ 0x0A | CS4231_XTAL2,
67 /* 48000 */ 0x0C | CS4231_XTAL1 67 /* 48000 */ 0x0C | CS4231_XTAL1
68 }; 68 };
69 69
70 static unsigned int rates[14] = { 70 static unsigned int rates[14] = {
71 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050, 71 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
72 27042, 32000, 33075, 37800, 44100, 48000 72 27042, 32000, 33075, 37800, 44100, 48000
73 }; 73 };
74 74
75 static struct snd_pcm_hw_constraint_list hw_constraints_rates = { 75 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
76 .count = ARRAY_SIZE(rates), 76 .count = ARRAY_SIZE(rates),
77 .list = rates, 77 .list = rates,
78 .mask = 0, 78 .mask = 0,
79 }; 79 };
80 80
81 static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime) 81 static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
82 { 82 {
83 return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); 83 return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
84 } 84 }
85 85
86 static unsigned char snd_cs4231_original_image[32] = 86 static unsigned char snd_cs4231_original_image[32] =
87 { 87 {
88 0x00, /* 00/00 - lic */ 88 0x00, /* 00/00 - lic */
89 0x00, /* 01/01 - ric */ 89 0x00, /* 01/01 - ric */
90 0x9f, /* 02/02 - la1ic */ 90 0x9f, /* 02/02 - la1ic */
91 0x9f, /* 03/03 - ra1ic */ 91 0x9f, /* 03/03 - ra1ic */
92 0x9f, /* 04/04 - la2ic */ 92 0x9f, /* 04/04 - la2ic */
93 0x9f, /* 05/05 - ra2ic */ 93 0x9f, /* 05/05 - ra2ic */
94 0xbf, /* 06/06 - loc */ 94 0xbf, /* 06/06 - loc */
95 0xbf, /* 07/07 - roc */ 95 0xbf, /* 07/07 - roc */
96 0x20, /* 08/08 - pdfr */ 96 0x20, /* 08/08 - pdfr */
97 CS4231_AUTOCALIB, /* 09/09 - ic */ 97 CS4231_AUTOCALIB, /* 09/09 - ic */
98 0x00, /* 0a/10 - pc */ 98 0x00, /* 0a/10 - pc */
99 0x00, /* 0b/11 - ti */ 99 0x00, /* 0b/11 - ti */
100 CS4231_MODE2, /* 0c/12 - mi */ 100 CS4231_MODE2, /* 0c/12 - mi */
101 0xfc, /* 0d/13 - lbc */ 101 0xfc, /* 0d/13 - lbc */
102 0x00, /* 0e/14 - pbru */ 102 0x00, /* 0e/14 - pbru */
103 0x00, /* 0f/15 - pbrl */ 103 0x00, /* 0f/15 - pbrl */
104 0x80, /* 10/16 - afei */ 104 0x80, /* 10/16 - afei */
105 0x01, /* 11/17 - afeii */ 105 0x01, /* 11/17 - afeii */
106 0x9f, /* 12/18 - llic */ 106 0x9f, /* 12/18 - llic */
107 0x9f, /* 13/19 - rlic */ 107 0x9f, /* 13/19 - rlic */
108 0x00, /* 14/20 - tlb */ 108 0x00, /* 14/20 - tlb */
109 0x00, /* 15/21 - thb */ 109 0x00, /* 15/21 - thb */
110 0x00, /* 16/22 - la3mic/reserved */ 110 0x00, /* 16/22 - la3mic/reserved */
111 0x00, /* 17/23 - ra3mic/reserved */ 111 0x00, /* 17/23 - ra3mic/reserved */
112 0x00, /* 18/24 - afs */ 112 0x00, /* 18/24 - afs */
113 0x00, /* 19/25 - lamoc/version */ 113 0x00, /* 19/25 - lamoc/version */
114 0xcf, /* 1a/26 - mioc */ 114 0xcf, /* 1a/26 - mioc */
115 0x00, /* 1b/27 - ramoc/reserved */ 115 0x00, /* 1b/27 - ramoc/reserved */
116 0x20, /* 1c/28 - cdfr */ 116 0x20, /* 1c/28 - cdfr */
117 0x00, /* 1d/29 - res4 */ 117 0x00, /* 1d/29 - res4 */
118 0x00, /* 1e/30 - cbru */ 118 0x00, /* 1e/30 - cbru */
119 0x00, /* 1f/31 - cbrl */ 119 0x00, /* 1f/31 - cbrl */
120 }; 120 };
121 121
122 static unsigned char snd_opti93x_original_image[32] =
123 {
124 0x00, /* 00/00 - l_mixout_outctrl */
125 0x00, /* 01/01 - r_mixout_outctrl */
126 0x88, /* 02/02 - l_cd_inctrl */
127 0x88, /* 03/03 - r_cd_inctrl */
128 0x88, /* 04/04 - l_a1/fm_inctrl */
129 0x88, /* 05/05 - r_a1/fm_inctrl */
130 0x80, /* 06/06 - l_dac_inctrl */
131 0x80, /* 07/07 - r_dac_inctrl */
132 0x00, /* 08/08 - ply_dataform_reg */
133 0x00, /* 09/09 - if_conf */
134 0x00, /* 0a/10 - pin_ctrl */
135 0x00, /* 0b/11 - err_init_reg */
136 0x0a, /* 0c/12 - id_reg */
137 0x00, /* 0d/13 - reserved */
138 0x00, /* 0e/14 - ply_upcount_reg */
139 0x00, /* 0f/15 - ply_lowcount_reg */
140 0x88, /* 10/16 - reserved/l_a1_inctrl */
141 0x88, /* 11/17 - reserved/r_a1_inctrl */
142 0x88, /* 12/18 - l_line_inctrl */
143 0x88, /* 13/19 - r_line_inctrl */
144 0x88, /* 14/20 - l_mic_inctrl */
145 0x88, /* 15/21 - r_mic_inctrl */
146 0x80, /* 16/22 - l_out_outctrl */
147 0x80, /* 17/23 - r_out_outctrl */
148 0x00, /* 18/24 - reserved */
149 0x00, /* 19/25 - reserved */
150 0x00, /* 1a/26 - reserved */
151 0x00, /* 1b/27 - reserved */
152 0x00, /* 1c/28 - cap_dataform_reg */
153 0x00, /* 1d/29 - reserved */
154 0x00, /* 1e/30 - cap_upcount_reg */
155 0x00 /* 1f/31 - cap_lowcount_reg */
156 };
157
122 /* 158 /*
123 * Basic I/O functions 159 * Basic I/O functions
124 */ 160 */
125 161
126 static inline void cs4231_outb(struct snd_cs4231 *chip, u8 offset, u8 val) 162 static inline void cs4231_outb(struct snd_cs4231 *chip, u8 offset, u8 val)
127 { 163 {
128 outb(val, chip->port + offset); 164 outb(val, chip->port + offset);
129 } 165 }
130 166
131 static inline u8 cs4231_inb(struct snd_cs4231 *chip, u8 offset) 167 static inline u8 cs4231_inb(struct snd_cs4231 *chip, u8 offset)
132 { 168 {
133 return inb(chip->port + offset); 169 return inb(chip->port + offset);
134 } 170 }
135 171
136 static void snd_cs4231_wait(struct snd_cs4231 *chip) 172 static void snd_cs4231_wait(struct snd_cs4231 *chip)
137 { 173 {
138 int timeout; 174 int timeout;
139 175
140 for (timeout = 250; 176 for (timeout = 250;
141 timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT); 177 timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
142 timeout--) 178 timeout--)
143 udelay(100); 179 udelay(100);
144 } 180 }
145 181
146 static void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg, 182 static void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
147 unsigned char mask, unsigned char value) 183 unsigned char mask, unsigned char value)
148 { 184 {
149 unsigned char tmp = (chip->image[reg] & mask) | value; 185 unsigned char tmp = (chip->image[reg] & mask) | value;
150 186
151 snd_cs4231_wait(chip); 187 snd_cs4231_wait(chip);
152 #ifdef CONFIG_SND_DEBUG 188 #ifdef CONFIG_SND_DEBUG
153 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) 189 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
154 snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value); 190 snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
155 #endif 191 #endif
156 chip->image[reg] = tmp; 192 chip->image[reg] = tmp;
157 if (!chip->calibrate_mute) { 193 if (!chip->calibrate_mute) {
158 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg); 194 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
159 wmb(); 195 wmb();
160 cs4231_outb(chip, CS4231P(REG), tmp); 196 cs4231_outb(chip, CS4231P(REG), tmp);
161 mb(); 197 mb();
162 } 198 }
163 } 199 }
164 200
165 static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, unsigned char value) 201 static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
166 { 202 {
167 int timeout; 203 int timeout;
168 204
169 for (timeout = 250; 205 for (timeout = 250;
170 timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT); 206 timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
171 timeout--) 207 timeout--)
172 udelay(10); 208 udelay(10);
173 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg); 209 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
174 cs4231_outb(chip, CS4231P(REG), value); 210 cs4231_outb(chip, CS4231P(REG), value);
175 mb(); 211 mb();
176 } 212 }
177 213
178 void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char value) 214 void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
179 { 215 {
180 snd_cs4231_wait(chip); 216 snd_cs4231_wait(chip);
181 #ifdef CONFIG_SND_DEBUG 217 #ifdef CONFIG_SND_DEBUG
182 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) 218 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
183 snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value); 219 snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
184 #endif 220 #endif
185 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg); 221 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
186 cs4231_outb(chip, CS4231P(REG), value); 222 cs4231_outb(chip, CS4231P(REG), value);
187 chip->image[reg] = value; 223 chip->image[reg] = value;
188 mb(); 224 mb();
189 snd_printdd("codec out - reg 0x%x = 0x%x\n", 225 snd_printdd("codec out - reg 0x%x = 0x%x\n",
190 chip->mce_bit | reg, value); 226 chip->mce_bit | reg, value);
191 } 227 }
192 228
193 unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg) 229 unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
194 { 230 {
195 snd_cs4231_wait(chip); 231 snd_cs4231_wait(chip);
196 #ifdef CONFIG_SND_DEBUG 232 #ifdef CONFIG_SND_DEBUG
197 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) 233 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
198 snd_printk("in: auto calibration time out - reg = 0x%x\n", reg); 234 snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
199 #endif 235 #endif
200 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg); 236 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
201 mb(); 237 mb();
202 return cs4231_inb(chip, CS4231P(REG)); 238 return cs4231_inb(chip, CS4231P(REG));
203 } 239 }
204 240
205 void snd_cs4236_ext_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val) 241 void snd_cs4236_ext_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val)
206 { 242 {
207 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17); 243 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
208 cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01)); 244 cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
209 cs4231_outb(chip, CS4231P(REG), val); 245 cs4231_outb(chip, CS4231P(REG), val);
210 chip->eimage[CS4236_REG(reg)] = val; 246 chip->eimage[CS4236_REG(reg)] = val;
211 #if 0 247 #if 0
212 printk("ext out : reg = 0x%x, val = 0x%x\n", reg, val); 248 printk("ext out : reg = 0x%x, val = 0x%x\n", reg, val);
213 #endif 249 #endif
214 } 250 }
215 251
216 unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg) 252 unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg)
217 { 253 {
218 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17); 254 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
219 cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01)); 255 cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
220 #if 1 256 #if 1
221 return cs4231_inb(chip, CS4231P(REG)); 257 return cs4231_inb(chip, CS4231P(REG));
222 #else 258 #else
223 { 259 {
224 unsigned char res; 260 unsigned char res;
225 res = cs4231_inb(chip, CS4231P(REG)); 261 res = cs4231_inb(chip, CS4231P(REG));
226 printk("ext in : reg = 0x%x, val = 0x%x\n", reg, res); 262 printk("ext in : reg = 0x%x, val = 0x%x\n", reg, res);
227 return res; 263 return res;
228 } 264 }
229 #endif 265 #endif
230 } 266 }
231 267
232 #if 0 268 #if 0
233 269
234 static void snd_cs4231_debug(struct snd_cs4231 *chip) 270 static void snd_cs4231_debug(struct snd_cs4231 *chip)
235 { 271 {
236 printk("CS4231 REGS: INDEX = 0x%02x ", cs4231_inb(chip, CS4231P(REGSEL))); 272 printk("CS4231 REGS: INDEX = 0x%02x ", cs4231_inb(chip, CS4231P(REGSEL)));
237 printk(" STATUS = 0x%02x\n", cs4231_inb(chip, CS4231P(STATUS))); 273 printk(" STATUS = 0x%02x\n", cs4231_inb(chip, CS4231P(STATUS)));
238 printk(" 0x00: left input = 0x%02x ", snd_cs4231_in(chip, 0x00)); 274 printk(" 0x00: left input = 0x%02x ", snd_cs4231_in(chip, 0x00));
239 printk(" 0x10: alt 1 (CFIG 2) = 0x%02x\n", snd_cs4231_in(chip, 0x10)); 275 printk(" 0x10: alt 1 (CFIG 2) = 0x%02x\n", snd_cs4231_in(chip, 0x10));
240 printk(" 0x01: right input = 0x%02x ", snd_cs4231_in(chip, 0x01)); 276 printk(" 0x01: right input = 0x%02x ", snd_cs4231_in(chip, 0x01));
241 printk(" 0x11: alt 2 (CFIG 3) = 0x%02x\n", snd_cs4231_in(chip, 0x11)); 277 printk(" 0x11: alt 2 (CFIG 3) = 0x%02x\n", snd_cs4231_in(chip, 0x11));
242 printk(" 0x02: GF1 left input = 0x%02x ", snd_cs4231_in(chip, 0x02)); 278 printk(" 0x02: GF1 left input = 0x%02x ", snd_cs4231_in(chip, 0x02));
243 printk(" 0x12: left line in = 0x%02x\n", snd_cs4231_in(chip, 0x12)); 279 printk(" 0x12: left line in = 0x%02x\n", snd_cs4231_in(chip, 0x12));
244 printk(" 0x03: GF1 right input = 0x%02x ", snd_cs4231_in(chip, 0x03)); 280 printk(" 0x03: GF1 right input = 0x%02x ", snd_cs4231_in(chip, 0x03));
245 printk(" 0x13: right line in = 0x%02x\n", snd_cs4231_in(chip, 0x13)); 281 printk(" 0x13: right line in = 0x%02x\n", snd_cs4231_in(chip, 0x13));
246 printk(" 0x04: CD left input = 0x%02x ", snd_cs4231_in(chip, 0x04)); 282 printk(" 0x04: CD left input = 0x%02x ", snd_cs4231_in(chip, 0x04));
247 printk(" 0x14: timer low = 0x%02x\n", snd_cs4231_in(chip, 0x14)); 283 printk(" 0x14: timer low = 0x%02x\n", snd_cs4231_in(chip, 0x14));
248 printk(" 0x05: CD right input = 0x%02x ", snd_cs4231_in(chip, 0x05)); 284 printk(" 0x05: CD right input = 0x%02x ", snd_cs4231_in(chip, 0x05));
249 printk(" 0x15: timer high = 0x%02x\n", snd_cs4231_in(chip, 0x15)); 285 printk(" 0x15: timer high = 0x%02x\n", snd_cs4231_in(chip, 0x15));
250 printk(" 0x06: left output = 0x%02x ", snd_cs4231_in(chip, 0x06)); 286 printk(" 0x06: left output = 0x%02x ", snd_cs4231_in(chip, 0x06));
251 printk(" 0x16: left MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x16)); 287 printk(" 0x16: left MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x16));
252 printk(" 0x07: right output = 0x%02x ", snd_cs4231_in(chip, 0x07)); 288 printk(" 0x07: right output = 0x%02x ", snd_cs4231_in(chip, 0x07));
253 printk(" 0x17: right MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x17)); 289 printk(" 0x17: right MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x17));
254 printk(" 0x08: playback format = 0x%02x ", snd_cs4231_in(chip, 0x08)); 290 printk(" 0x08: playback format = 0x%02x ", snd_cs4231_in(chip, 0x08));
255 printk(" 0x18: IRQ status = 0x%02x\n", snd_cs4231_in(chip, 0x18)); 291 printk(" 0x18: IRQ status = 0x%02x\n", snd_cs4231_in(chip, 0x18));
256 printk(" 0x09: iface (CFIG 1) = 0x%02x ", snd_cs4231_in(chip, 0x09)); 292 printk(" 0x09: iface (CFIG 1) = 0x%02x ", snd_cs4231_in(chip, 0x09));
257 printk(" 0x19: left line out = 0x%02x\n", snd_cs4231_in(chip, 0x19)); 293 printk(" 0x19: left line out = 0x%02x\n", snd_cs4231_in(chip, 0x19));
258 printk(" 0x0a: pin control = 0x%02x ", snd_cs4231_in(chip, 0x0a)); 294 printk(" 0x0a: pin control = 0x%02x ", snd_cs4231_in(chip, 0x0a));
259 printk(" 0x1a: mono control = 0x%02x\n", snd_cs4231_in(chip, 0x1a)); 295 printk(" 0x1a: mono control = 0x%02x\n", snd_cs4231_in(chip, 0x1a));
260 printk(" 0x0b: init & status = 0x%02x ", snd_cs4231_in(chip, 0x0b)); 296 printk(" 0x0b: init & status = 0x%02x ", snd_cs4231_in(chip, 0x0b));
261 printk(" 0x1b: right line out = 0x%02x\n", snd_cs4231_in(chip, 0x1b)); 297 printk(" 0x1b: right line out = 0x%02x\n", snd_cs4231_in(chip, 0x1b));
262 printk(" 0x0c: revision & mode = 0x%02x ", snd_cs4231_in(chip, 0x0c)); 298 printk(" 0x0c: revision & mode = 0x%02x ", snd_cs4231_in(chip, 0x0c));
263 printk(" 0x1c: record format = 0x%02x\n", snd_cs4231_in(chip, 0x1c)); 299 printk(" 0x1c: record format = 0x%02x\n", snd_cs4231_in(chip, 0x1c));
264 printk(" 0x0d: loopback = 0x%02x ", snd_cs4231_in(chip, 0x0d)); 300 printk(" 0x0d: loopback = 0x%02x ", snd_cs4231_in(chip, 0x0d));
265 printk(" 0x1d: var freq (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x1d)); 301 printk(" 0x1d: var freq (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x1d));
266 printk(" 0x0e: ply upr count = 0x%02x ", snd_cs4231_in(chip, 0x0e)); 302 printk(" 0x0e: ply upr count = 0x%02x ", snd_cs4231_in(chip, 0x0e));
267 printk(" 0x1e: ply lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1e)); 303 printk(" 0x1e: ply lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1e));
268 printk(" 0x0f: rec upr count = 0x%02x ", snd_cs4231_in(chip, 0x0f)); 304 printk(" 0x0f: rec upr count = 0x%02x ", snd_cs4231_in(chip, 0x0f));
269 printk(" 0x1f: rec lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1f)); 305 printk(" 0x1f: rec lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1f));
270 } 306 }
271 307
272 #endif 308 #endif
273 309
274 /* 310 /*
275 * CS4231 detection / MCE routines 311 * CS4231 detection / MCE routines
276 */ 312 */
277 313
278 static void snd_cs4231_busy_wait(struct snd_cs4231 *chip) 314 static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
279 { 315 {
280 int timeout; 316 int timeout;
281 317
282 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */ 318 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
283 for (timeout = 5; timeout > 0; timeout--) 319 for (timeout = 5; timeout > 0; timeout--)
284 cs4231_inb(chip, CS4231P(REGSEL)); 320 cs4231_inb(chip, CS4231P(REGSEL));
285 /* end of cleanup sequence */ 321 /* end of cleanup sequence */
286 for (timeout = 250; 322 for (timeout = 250;
287 timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT); 323 timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
288 timeout--) 324 timeout--)
289 udelay(10); 325 udelay(10);
290 } 326 }
291 327
292 void snd_cs4231_mce_up(struct snd_cs4231 *chip) 328 void snd_cs4231_mce_up(struct snd_cs4231 *chip)
293 { 329 {
294 unsigned long flags; 330 unsigned long flags;
295 int timeout; 331 int timeout;
296 332
297 snd_cs4231_wait(chip); 333 snd_cs4231_wait(chip);
298 #ifdef CONFIG_SND_DEBUG 334 #ifdef CONFIG_SND_DEBUG
299 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) 335 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
300 snd_printk("mce_up - auto calibration time out (0)\n"); 336 snd_printk("mce_up - auto calibration time out (0)\n");
301 #endif 337 #endif
302 spin_lock_irqsave(&chip->reg_lock, flags); 338 spin_lock_irqsave(&chip->reg_lock, flags);
303 chip->mce_bit |= CS4231_MCE; 339 chip->mce_bit |= CS4231_MCE;
304 timeout = cs4231_inb(chip, CS4231P(REGSEL)); 340 timeout = cs4231_inb(chip, CS4231P(REGSEL));
305 if (timeout == 0x80) 341 if (timeout == 0x80)
306 snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port); 342 snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
307 if (!(timeout & CS4231_MCE)) 343 if (!(timeout & CS4231_MCE))
308 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f)); 344 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
309 spin_unlock_irqrestore(&chip->reg_lock, flags); 345 spin_unlock_irqrestore(&chip->reg_lock, flags);
310 } 346 }
311 347
312 void snd_cs4231_mce_down(struct snd_cs4231 *chip) 348 void snd_cs4231_mce_down(struct snd_cs4231 *chip)
313 { 349 {
314 unsigned long flags; 350 unsigned long flags;
315 unsigned long end_time; 351 unsigned long end_time;
316 int timeout; 352 int timeout;
317 353
318 snd_cs4231_busy_wait(chip); 354 snd_cs4231_busy_wait(chip);
319 355
320 #ifdef CONFIG_SND_DEBUG 356 #ifdef CONFIG_SND_DEBUG
321 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) 357 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
322 snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", (long)CS4231P(REGSEL)); 358 snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", (long)CS4231P(REGSEL));
323 #endif 359 #endif
324 spin_lock_irqsave(&chip->reg_lock, flags); 360 spin_lock_irqsave(&chip->reg_lock, flags);
325 chip->mce_bit &= ~CS4231_MCE; 361 chip->mce_bit &= ~CS4231_MCE;
326 timeout = cs4231_inb(chip, CS4231P(REGSEL)); 362 timeout = cs4231_inb(chip, CS4231P(REGSEL));
327 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f)); 363 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
328 spin_unlock_irqrestore(&chip->reg_lock, flags); 364 spin_unlock_irqrestore(&chip->reg_lock, flags);
329 if (timeout == 0x80) 365 if (timeout == 0x80)
330 snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port); 366 snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
331 if ((timeout & CS4231_MCE) == 0 || 367 if ((timeout & CS4231_MCE) == 0 ||
332 !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) { 368 !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
333 return; 369 return;
334 } 370 }
335 371
336 /* 372 /*
337 * Wait for (possible -- during init auto-calibration may not be set) 373 * Wait for (possible -- during init auto-calibration may not be set)
338 * calibration process to start. Needs upto 5 sample periods on AD1848 374 * calibration process to start. Needs upto 5 sample periods on AD1848
339 * which at the slowest possible rate of 5.5125 kHz means 907 us. 375 * which at the slowest possible rate of 5.5125 kHz means 907 us.
340 */ 376 */
341 msleep(1); 377 msleep(1);
342 378
343 snd_printdd("(1) jiffies = %lu\n", jiffies); 379 snd_printdd("(1) jiffies = %lu\n", jiffies);
344 380
345 /* check condition up to 250 ms */ 381 /* check condition up to 250 ms */
346 end_time = jiffies + msecs_to_jiffies(250); 382 end_time = jiffies + msecs_to_jiffies(250);
347 while (snd_cs4231_in(chip, CS4231_TEST_INIT) & 383 while (snd_cs4231_in(chip, CS4231_TEST_INIT) &
348 CS4231_CALIB_IN_PROGRESS) { 384 CS4231_CALIB_IN_PROGRESS) {
349 385
350 if (time_after(jiffies, end_time)) { 386 if (time_after(jiffies, end_time)) {
351 snd_printk(KERN_ERR "mce_down - " 387 snd_printk(KERN_ERR "mce_down - "
352 "auto calibration time out (2)\n"); 388 "auto calibration time out (2)\n");
353 return; 389 return;
354 } 390 }
355 msleep(1); 391 msleep(1);
356 } 392 }
357 393
358 snd_printdd("(2) jiffies = %lu\n", jiffies); 394 snd_printdd("(2) jiffies = %lu\n", jiffies);
359 395
360 /* check condition up to 100 ms */ 396 /* check condition up to 100 ms */
361 end_time = jiffies + msecs_to_jiffies(100); 397 end_time = jiffies + msecs_to_jiffies(100);
362 while (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) { 398 while (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
363 if (time_after(jiffies, end_time)) { 399 if (time_after(jiffies, end_time)) {
364 snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n"); 400 snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
365 return; 401 return;
366 } 402 }
367 msleep(1); 403 msleep(1);
368 } 404 }
369 405
370 snd_printdd("(3) jiffies = %lu\n", jiffies); 406 snd_printdd("(3) jiffies = %lu\n", jiffies);
371 snd_printd("mce_down - exit = 0x%x\n", cs4231_inb(chip, CS4231P(REGSEL))); 407 snd_printd("mce_down - exit = 0x%x\n", cs4231_inb(chip, CS4231P(REGSEL)));
372 } 408 }
373 409
374 static unsigned int snd_cs4231_get_count(unsigned char format, unsigned int size) 410 static unsigned int snd_cs4231_get_count(unsigned char format, unsigned int size)
375 { 411 {
376 switch (format & 0xe0) { 412 switch (format & 0xe0) {
377 case CS4231_LINEAR_16: 413 case CS4231_LINEAR_16:
378 case CS4231_LINEAR_16_BIG: 414 case CS4231_LINEAR_16_BIG:
379 size >>= 1; 415 size >>= 1;
380 break; 416 break;
381 case CS4231_ADPCM_16: 417 case CS4231_ADPCM_16:
382 return size >> 2; 418 return size >> 2;
383 } 419 }
384 if (format & CS4231_STEREO) 420 if (format & CS4231_STEREO)
385 size >>= 1; 421 size >>= 1;
386 return size; 422 return size;
387 } 423 }
388 424
389 static int snd_cs4231_trigger(struct snd_pcm_substream *substream, 425 static int snd_cs4231_trigger(struct snd_pcm_substream *substream,
390 int cmd) 426 int cmd)
391 { 427 {
392 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 428 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
393 int result = 0; 429 int result = 0;
394 unsigned int what; 430 unsigned int what;
395 struct snd_pcm_substream *s; 431 struct snd_pcm_substream *s;
396 int do_start; 432 int do_start;
397 433
398 #if 0 434 #if 0
399 printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, cs4231_inb(chip, CS4231P(STATUS))); 435 printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, cs4231_inb(chip, CS4231P(STATUS)));
400 #endif 436 #endif
401 437
402 switch (cmd) { 438 switch (cmd) {
403 case SNDRV_PCM_TRIGGER_START: 439 case SNDRV_PCM_TRIGGER_START:
404 case SNDRV_PCM_TRIGGER_RESUME: 440 case SNDRV_PCM_TRIGGER_RESUME:
405 do_start = 1; break; 441 do_start = 1; break;
406 case SNDRV_PCM_TRIGGER_STOP: 442 case SNDRV_PCM_TRIGGER_STOP:
407 case SNDRV_PCM_TRIGGER_SUSPEND: 443 case SNDRV_PCM_TRIGGER_SUSPEND:
408 do_start = 0; break; 444 do_start = 0; break;
409 default: 445 default:
410 return -EINVAL; 446 return -EINVAL;
411 } 447 }
412 448
413 what = 0; 449 what = 0;
414 snd_pcm_group_for_each_entry(s, substream) { 450 snd_pcm_group_for_each_entry(s, substream) {
415 if (s == chip->playback_substream) { 451 if (s == chip->playback_substream) {
416 what |= CS4231_PLAYBACK_ENABLE; 452 what |= CS4231_PLAYBACK_ENABLE;
417 snd_pcm_trigger_done(s, substream); 453 snd_pcm_trigger_done(s, substream);
418 } else if (s == chip->capture_substream) { 454 } else if (s == chip->capture_substream) {
419 what |= CS4231_RECORD_ENABLE; 455 what |= CS4231_RECORD_ENABLE;
420 snd_pcm_trigger_done(s, substream); 456 snd_pcm_trigger_done(s, substream);
421 } 457 }
422 } 458 }
423 spin_lock(&chip->reg_lock); 459 spin_lock(&chip->reg_lock);
424 if (do_start) { 460 if (do_start) {
425 chip->image[CS4231_IFACE_CTRL] |= what; 461 chip->image[CS4231_IFACE_CTRL] |= what;
426 if (chip->trigger) 462 if (chip->trigger)
427 chip->trigger(chip, what, 1); 463 chip->trigger(chip, what, 1);
428 } else { 464 } else {
429 chip->image[CS4231_IFACE_CTRL] &= ~what; 465 chip->image[CS4231_IFACE_CTRL] &= ~what;
430 if (chip->trigger) 466 if (chip->trigger)
431 chip->trigger(chip, what, 0); 467 chip->trigger(chip, what, 0);
432 } 468 }
433 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]); 469 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
434 spin_unlock(&chip->reg_lock); 470 spin_unlock(&chip->reg_lock);
435 #if 0 471 #if 0
436 snd_cs4231_debug(chip); 472 snd_cs4231_debug(chip);
437 #endif 473 #endif
438 return result; 474 return result;
439 } 475 }
440 476
441 /* 477 /*
442 * CODEC I/O 478 * CODEC I/O
443 */ 479 */
444 480
445 static unsigned char snd_cs4231_get_rate(unsigned int rate) 481 static unsigned char snd_cs4231_get_rate(unsigned int rate)
446 { 482 {
447 int i; 483 int i;
448 484
449 for (i = 0; i < ARRAY_SIZE(rates); i++) 485 for (i = 0; i < ARRAY_SIZE(rates); i++)
450 if (rate == rates[i]) 486 if (rate == rates[i])
451 return freq_bits[i]; 487 return freq_bits[i];
452 // snd_BUG(); 488 // snd_BUG();
453 return freq_bits[ARRAY_SIZE(rates) - 1]; 489 return freq_bits[ARRAY_SIZE(rates) - 1];
454 } 490 }
455 491
456 static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, 492 static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip,
457 int format, 493 int format,
458 int channels) 494 int channels)
459 { 495 {
460 unsigned char rformat; 496 unsigned char rformat;
461 497
462 rformat = CS4231_LINEAR_8; 498 rformat = CS4231_LINEAR_8;
463 switch (format) { 499 switch (format) {
464 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break; 500 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
465 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break; 501 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
466 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break; 502 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
467 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break; 503 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
468 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break; 504 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
469 } 505 }
470 if (channels > 1) 506 if (channels > 1)
471 rformat |= CS4231_STEREO; 507 rformat |= CS4231_STEREO;
472 #if 0 508 #if 0
473 snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode); 509 snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
474 #endif 510 #endif
475 return rformat; 511 return rformat;
476 } 512 }
477 513
478 static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute) 514 static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
479 { 515 {
480 unsigned long flags; 516 unsigned long flags;
481 517
482 mute = mute ? 1 : 0; 518 mute = mute ? 1 : 0;
483 spin_lock_irqsave(&chip->reg_lock, flags); 519 spin_lock_irqsave(&chip->reg_lock, flags);
484 if (chip->calibrate_mute == mute) { 520 if (chip->calibrate_mute == mute) {
485 spin_unlock_irqrestore(&chip->reg_lock, flags); 521 spin_unlock_irqrestore(&chip->reg_lock, flags);
486 return; 522 return;
487 } 523 }
488 if (!mute) { 524 if (!mute) {
489 snd_cs4231_dout(chip, CS4231_LEFT_INPUT, chip->image[CS4231_LEFT_INPUT]); 525 snd_cs4231_dout(chip, CS4231_LEFT_INPUT, chip->image[CS4231_LEFT_INPUT]);
490 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT, chip->image[CS4231_RIGHT_INPUT]); 526 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT, chip->image[CS4231_RIGHT_INPUT]);
491 snd_cs4231_dout(chip, CS4231_LOOPBACK, chip->image[CS4231_LOOPBACK]); 527 snd_cs4231_dout(chip, CS4231_LOOPBACK, chip->image[CS4231_LOOPBACK]);
492 } 528 }
493 snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]); 529 snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
494 snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]); 530 snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
495 snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]); 531 snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
496 snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]); 532 snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
497 snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]); 533 snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
498 snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]); 534 snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
499 snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN, mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]); 535 snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN, mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
500 snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN, mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]); 536 snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN, mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
501 snd_cs4231_dout(chip, CS4231_MONO_CTRL, mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]); 537 snd_cs4231_dout(chip, CS4231_MONO_CTRL, mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
502 if (chip->hardware == CS4231_HW_INTERWAVE) { 538 if (chip->hardware == CS4231_HW_INTERWAVE) {
503 snd_cs4231_dout(chip, CS4231_LEFT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_LEFT_MIC_INPUT]); 539 snd_cs4231_dout(chip, CS4231_LEFT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_LEFT_MIC_INPUT]);
504 snd_cs4231_dout(chip, CS4231_RIGHT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_MIC_INPUT]); 540 snd_cs4231_dout(chip, CS4231_RIGHT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_MIC_INPUT]);
505 snd_cs4231_dout(chip, CS4231_LINE_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_LEFT_OUTPUT]); 541 snd_cs4231_dout(chip, CS4231_LINE_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_LEFT_OUTPUT]);
506 snd_cs4231_dout(chip, CS4231_LINE_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_RIGHT_OUTPUT]); 542 snd_cs4231_dout(chip, CS4231_LINE_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_RIGHT_OUTPUT]);
507 } 543 }
508 chip->calibrate_mute = mute; 544 chip->calibrate_mute = mute;
509 spin_unlock_irqrestore(&chip->reg_lock, flags); 545 spin_unlock_irqrestore(&chip->reg_lock, flags);
510 } 546 }
511 547
512 static void snd_cs4231_playback_format(struct snd_cs4231 *chip, 548 static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
513 struct snd_pcm_hw_params *params, 549 struct snd_pcm_hw_params *params,
514 unsigned char pdfr) 550 unsigned char pdfr)
515 { 551 {
516 unsigned long flags; 552 unsigned long flags;
517 int full_calib = 1; 553 int full_calib = 1;
518 554
519 mutex_lock(&chip->mce_mutex); 555 mutex_lock(&chip->mce_mutex);
520 snd_cs4231_calibrate_mute(chip, 1); 556 snd_cs4231_calibrate_mute(chip, 1);
521 if (chip->hardware == CS4231_HW_CS4231A || 557 if (chip->hardware == CS4231_HW_CS4231A ||
522 (chip->hardware & CS4231_HW_CS4232_MASK)) { 558 (chip->hardware & CS4231_HW_CS4232_MASK)) {
523 spin_lock_irqsave(&chip->reg_lock, flags); 559 spin_lock_irqsave(&chip->reg_lock, flags);
524 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */ 560 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
525 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x10); 561 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x10);
526 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr); 562 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
527 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x10); 563 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
528 udelay(100); /* Fixes audible clicks at least on GUS MAX */ 564 udelay(100); /* Fixes audible clicks at least on GUS MAX */
529 full_calib = 0; 565 full_calib = 0;
530 } 566 }
531 spin_unlock_irqrestore(&chip->reg_lock, flags); 567 spin_unlock_irqrestore(&chip->reg_lock, flags);
532 } 568 }
533 if (full_calib) { 569 if (full_calib) {
534 snd_cs4231_mce_up(chip); 570 snd_cs4231_mce_up(chip);
535 spin_lock_irqsave(&chip->reg_lock, flags); 571 spin_lock_irqsave(&chip->reg_lock, flags);
536 if (chip->hardware != CS4231_HW_INTERWAVE && !chip->single_dma) { 572 if (chip->hardware != CS4231_HW_INTERWAVE && !chip->single_dma) {
537 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, 573 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
538 (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ? 574 (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
539 (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) : 575 (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
540 pdfr); 576 pdfr);
541 } else { 577 } else {
542 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr); 578 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
543 } 579 }
544 spin_unlock_irqrestore(&chip->reg_lock, flags); 580 spin_unlock_irqrestore(&chip->reg_lock, flags);
545 if (chip->hardware == CS4231_HW_OPL3SA2) 581 if (chip->hardware == CS4231_HW_OPL3SA2)
546 udelay(100); /* this seems to help */ 582 udelay(100); /* this seems to help */
547 snd_cs4231_mce_down(chip); 583 snd_cs4231_mce_down(chip);
548 } 584 }
549 snd_cs4231_calibrate_mute(chip, 0); 585 snd_cs4231_calibrate_mute(chip, 0);
550 mutex_unlock(&chip->mce_mutex); 586 mutex_unlock(&chip->mce_mutex);
551 } 587 }
552 588
553 static void snd_cs4231_capture_format(struct snd_cs4231 *chip, 589 static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
554 struct snd_pcm_hw_params *params, 590 struct snd_pcm_hw_params *params,
555 unsigned char cdfr) 591 unsigned char cdfr)
556 { 592 {
557 unsigned long flags; 593 unsigned long flags;
558 int full_calib = 1; 594 int full_calib = 1;
559 595
560 mutex_lock(&chip->mce_mutex); 596 mutex_lock(&chip->mce_mutex);
561 snd_cs4231_calibrate_mute(chip, 1); 597 snd_cs4231_calibrate_mute(chip, 1);
562 if (chip->hardware == CS4231_HW_CS4231A || 598 if (chip->hardware == CS4231_HW_CS4231A ||
563 (chip->hardware & CS4231_HW_CS4232_MASK)) { 599 (chip->hardware & CS4231_HW_CS4232_MASK)) {
564 spin_lock_irqsave(&chip->reg_lock, flags); 600 spin_lock_irqsave(&chip->reg_lock, flags);
565 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */ 601 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
566 (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) { 602 (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
567 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x20); 603 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x20);
568 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT] = cdfr); 604 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT] = cdfr);
569 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x20); 605 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
570 full_calib = 0; 606 full_calib = 0;
571 } 607 }
572 spin_unlock_irqrestore(&chip->reg_lock, flags); 608 spin_unlock_irqrestore(&chip->reg_lock, flags);
573 } 609 }
574 if (full_calib) { 610 if (full_calib) {
575 snd_cs4231_mce_up(chip); 611 snd_cs4231_mce_up(chip);
576 spin_lock_irqsave(&chip->reg_lock, flags); 612 spin_lock_irqsave(&chip->reg_lock, flags);
577 if (chip->hardware != CS4231_HW_INTERWAVE) { 613 if (chip->hardware != CS4231_HW_INTERWAVE) {
578 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) { 614 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
579 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, 615 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
580 ((chip->single_dma ? cdfr : chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) | 616 ((chip->single_dma ? cdfr : chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
581 (cdfr & 0x0f)); 617 (cdfr & 0x0f));
582 spin_unlock_irqrestore(&chip->reg_lock, flags); 618 spin_unlock_irqrestore(&chip->reg_lock, flags);
583 snd_cs4231_mce_down(chip); 619 snd_cs4231_mce_down(chip);
584 snd_cs4231_mce_up(chip); 620 snd_cs4231_mce_up(chip);
585 spin_lock_irqsave(&chip->reg_lock, flags); 621 spin_lock_irqsave(&chip->reg_lock, flags);
586 } 622 }
587 } 623 }
588 snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr); 624 snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
589 spin_unlock_irqrestore(&chip->reg_lock, flags); 625 spin_unlock_irqrestore(&chip->reg_lock, flags);
590 snd_cs4231_mce_down(chip); 626 snd_cs4231_mce_down(chip);
591 } 627 }
592 snd_cs4231_calibrate_mute(chip, 0); 628 snd_cs4231_calibrate_mute(chip, 0);
593 mutex_unlock(&chip->mce_mutex); 629 mutex_unlock(&chip->mce_mutex);
594 } 630 }
595 631
596 /* 632 /*
597 * Timer interface 633 * Timer interface
598 */ 634 */
599 635
600 static unsigned long snd_cs4231_timer_resolution(struct snd_timer * timer) 636 static unsigned long snd_cs4231_timer_resolution(struct snd_timer * timer)
601 { 637 {
602 struct snd_cs4231 *chip = snd_timer_chip(timer); 638 struct snd_cs4231 *chip = snd_timer_chip(timer);
603 if (chip->hardware & CS4231_HW_CS4236B_MASK) 639 if (chip->hardware & CS4231_HW_CS4236B_MASK)
604 return 14467; 640 return 14467;
605 else 641 else
606 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920; 642 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
607 } 643 }
608 644
609 static int snd_cs4231_timer_start(struct snd_timer * timer) 645 static int snd_cs4231_timer_start(struct snd_timer * timer)
610 { 646 {
611 unsigned long flags; 647 unsigned long flags;
612 unsigned int ticks; 648 unsigned int ticks;
613 struct snd_cs4231 *chip = snd_timer_chip(timer); 649 struct snd_cs4231 *chip = snd_timer_chip(timer);
614 spin_lock_irqsave(&chip->reg_lock, flags); 650 spin_lock_irqsave(&chip->reg_lock, flags);
615 ticks = timer->sticks; 651 ticks = timer->sticks;
616 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 || 652 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
617 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] || 653 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
618 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) { 654 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
619 snd_cs4231_out(chip, CS4231_TIMER_HIGH, chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8)); 655 snd_cs4231_out(chip, CS4231_TIMER_HIGH, chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8));
620 snd_cs4231_out(chip, CS4231_TIMER_LOW, chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks); 656 snd_cs4231_out(chip, CS4231_TIMER_LOW, chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks);
621 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE); 657 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
622 } 658 }
623 spin_unlock_irqrestore(&chip->reg_lock, flags); 659 spin_unlock_irqrestore(&chip->reg_lock, flags);
624 return 0; 660 return 0;
625 } 661 }
626 662
627 static int snd_cs4231_timer_stop(struct snd_timer * timer) 663 static int snd_cs4231_timer_stop(struct snd_timer * timer)
628 { 664 {
629 unsigned long flags; 665 unsigned long flags;
630 struct snd_cs4231 *chip = snd_timer_chip(timer); 666 struct snd_cs4231 *chip = snd_timer_chip(timer);
631 spin_lock_irqsave(&chip->reg_lock, flags); 667 spin_lock_irqsave(&chip->reg_lock, flags);
632 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE); 668 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
633 spin_unlock_irqrestore(&chip->reg_lock, flags); 669 spin_unlock_irqrestore(&chip->reg_lock, flags);
634 return 0; 670 return 0;
635 } 671 }
636 672
637 static void snd_cs4231_init(struct snd_cs4231 *chip) 673 static void snd_cs4231_init(struct snd_cs4231 *chip)
638 { 674 {
639 unsigned long flags; 675 unsigned long flags;
640 676
641 snd_cs4231_mce_down(chip); 677 snd_cs4231_mce_down(chip);
642 678
643 #ifdef SNDRV_DEBUG_MCE 679 #ifdef SNDRV_DEBUG_MCE
644 snd_printk("init: (1)\n"); 680 snd_printk("init: (1)\n");
645 #endif 681 #endif
646 snd_cs4231_mce_up(chip); 682 snd_cs4231_mce_up(chip);
647 spin_lock_irqsave(&chip->reg_lock, flags); 683 spin_lock_irqsave(&chip->reg_lock, flags);
648 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | 684 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
649 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO | 685 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
650 CS4231_CALIB_MODE); 686 CS4231_CALIB_MODE);
651 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB; 687 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
652 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]); 688 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
653 spin_unlock_irqrestore(&chip->reg_lock, flags); 689 spin_unlock_irqrestore(&chip->reg_lock, flags);
654 snd_cs4231_mce_down(chip); 690 snd_cs4231_mce_down(chip);
655 691
656 #ifdef SNDRV_DEBUG_MCE 692 #ifdef SNDRV_DEBUG_MCE
657 snd_printk("init: (2)\n"); 693 snd_printk("init: (2)\n");
658 #endif 694 #endif
659 695
660 snd_cs4231_mce_up(chip); 696 snd_cs4231_mce_up(chip);
661 spin_lock_irqsave(&chip->reg_lock, flags); 697 spin_lock_irqsave(&chip->reg_lock, flags);
662 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]); 698 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
663 spin_unlock_irqrestore(&chip->reg_lock, flags); 699 spin_unlock_irqrestore(&chip->reg_lock, flags);
664 snd_cs4231_mce_down(chip); 700 snd_cs4231_mce_down(chip);
665 701
666 #ifdef SNDRV_DEBUG_MCE 702 #ifdef SNDRV_DEBUG_MCE
667 snd_printk("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]); 703 snd_printk("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
668 #endif 704 #endif
669 705
670 spin_lock_irqsave(&chip->reg_lock, flags); 706 spin_lock_irqsave(&chip->reg_lock, flags);
671 snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]); 707 snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
672 spin_unlock_irqrestore(&chip->reg_lock, flags); 708 spin_unlock_irqrestore(&chip->reg_lock, flags);
673 709
674 snd_cs4231_mce_up(chip); 710 snd_cs4231_mce_up(chip);
675 spin_lock_irqsave(&chip->reg_lock, flags); 711 spin_lock_irqsave(&chip->reg_lock, flags);
676 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]); 712 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
677 spin_unlock_irqrestore(&chip->reg_lock, flags); 713 spin_unlock_irqrestore(&chip->reg_lock, flags);
678 snd_cs4231_mce_down(chip); 714 snd_cs4231_mce_down(chip);
679 715
680 #ifdef SNDRV_DEBUG_MCE 716 #ifdef SNDRV_DEBUG_MCE
681 snd_printk("init: (4)\n"); 717 snd_printk("init: (4)\n");
682 #endif 718 #endif
683 719
684 snd_cs4231_mce_up(chip); 720 snd_cs4231_mce_up(chip);
685 spin_lock_irqsave(&chip->reg_lock, flags); 721 spin_lock_irqsave(&chip->reg_lock, flags);
686 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]); 722 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
687 spin_unlock_irqrestore(&chip->reg_lock, flags); 723 spin_unlock_irqrestore(&chip->reg_lock, flags);
688 snd_cs4231_mce_down(chip); 724 snd_cs4231_mce_down(chip);
689 725
690 #ifdef SNDRV_DEBUG_MCE 726 #ifdef SNDRV_DEBUG_MCE
691 snd_printk("init: (5)\n"); 727 snd_printk("init: (5)\n");
692 #endif 728 #endif
693 } 729 }
694 730
695 static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode) 731 static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
696 { 732 {
697 unsigned long flags; 733 unsigned long flags;
698 734
699 mutex_lock(&chip->open_mutex); 735 mutex_lock(&chip->open_mutex);
700 if ((chip->mode & mode) || 736 if ((chip->mode & mode) ||
701 ((chip->mode & CS4231_MODE_OPEN) && chip->single_dma)) { 737 ((chip->mode & CS4231_MODE_OPEN) && chip->single_dma)) {
702 mutex_unlock(&chip->open_mutex); 738 mutex_unlock(&chip->open_mutex);
703 return -EAGAIN; 739 return -EAGAIN;
704 } 740 }
705 if (chip->mode & CS4231_MODE_OPEN) { 741 if (chip->mode & CS4231_MODE_OPEN) {
706 chip->mode |= mode; 742 chip->mode |= mode;
707 mutex_unlock(&chip->open_mutex); 743 mutex_unlock(&chip->open_mutex);
708 return 0; 744 return 0;
709 } 745 }
710 /* ok. now enable and ack CODEC IRQ */ 746 /* ok. now enable and ack CODEC IRQ */
711 spin_lock_irqsave(&chip->reg_lock, flags); 747 spin_lock_irqsave(&chip->reg_lock, flags);
712 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ | 748 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
713 CS4231_RECORD_IRQ | 749 CS4231_RECORD_IRQ |
714 CS4231_TIMER_IRQ); 750 CS4231_TIMER_IRQ);
715 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 751 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
716 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */ 752 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
717 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */ 753 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
718 chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE; 754 chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
719 snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]); 755 snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
720 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ | 756 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
721 CS4231_RECORD_IRQ | 757 CS4231_RECORD_IRQ |
722 CS4231_TIMER_IRQ); 758 CS4231_TIMER_IRQ);
723 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 759 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
724 spin_unlock_irqrestore(&chip->reg_lock, flags); 760 spin_unlock_irqrestore(&chip->reg_lock, flags);
725 761
726 chip->mode = mode; 762 chip->mode = mode;
727 mutex_unlock(&chip->open_mutex); 763 mutex_unlock(&chip->open_mutex);
728 return 0; 764 return 0;
729 } 765 }
730 766
731 static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode) 767 static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
732 { 768 {
733 unsigned long flags; 769 unsigned long flags;
734 770
735 mutex_lock(&chip->open_mutex); 771 mutex_lock(&chip->open_mutex);
736 chip->mode &= ~mode; 772 chip->mode &= ~mode;
737 if (chip->mode & CS4231_MODE_OPEN) { 773 if (chip->mode & CS4231_MODE_OPEN) {
738 mutex_unlock(&chip->open_mutex); 774 mutex_unlock(&chip->open_mutex);
739 return; 775 return;
740 } 776 }
741 snd_cs4231_calibrate_mute(chip, 1); 777 snd_cs4231_calibrate_mute(chip, 1);
742 778
743 /* disable IRQ */ 779 /* disable IRQ */
744 spin_lock_irqsave(&chip->reg_lock, flags); 780 spin_lock_irqsave(&chip->reg_lock, flags);
745 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 781 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
746 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */ 782 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
747 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */ 783 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
748 chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE; 784 chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
749 snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]); 785 snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
750 786
751 /* now disable record & playback */ 787 /* now disable record & playback */
752 788
753 if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | 789 if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
754 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) { 790 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
755 spin_unlock_irqrestore(&chip->reg_lock, flags); 791 spin_unlock_irqrestore(&chip->reg_lock, flags);
756 snd_cs4231_mce_up(chip); 792 snd_cs4231_mce_up(chip);
757 spin_lock_irqsave(&chip->reg_lock, flags); 793 spin_lock_irqsave(&chip->reg_lock, flags);
758 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | 794 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
759 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO); 795 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
760 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]); 796 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
761 spin_unlock_irqrestore(&chip->reg_lock, flags); 797 spin_unlock_irqrestore(&chip->reg_lock, flags);
762 snd_cs4231_mce_down(chip); 798 snd_cs4231_mce_down(chip);
763 spin_lock_irqsave(&chip->reg_lock, flags); 799 spin_lock_irqsave(&chip->reg_lock, flags);
764 } 800 }
765 801
766 /* clear IRQ again */ 802 /* clear IRQ again */
767 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 803 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
768 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */ 804 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
769 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */ 805 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
770 spin_unlock_irqrestore(&chip->reg_lock, flags); 806 spin_unlock_irqrestore(&chip->reg_lock, flags);
771 807
772 snd_cs4231_calibrate_mute(chip, 0); 808 snd_cs4231_calibrate_mute(chip, 0);
773 809
774 chip->mode = 0; 810 chip->mode = 0;
775 mutex_unlock(&chip->open_mutex); 811 mutex_unlock(&chip->open_mutex);
776 } 812 }
777 813
778 /* 814 /*
779 * timer open/close 815 * timer open/close
780 */ 816 */
781 817
782 static int snd_cs4231_timer_open(struct snd_timer * timer) 818 static int snd_cs4231_timer_open(struct snd_timer * timer)
783 { 819 {
784 struct snd_cs4231 *chip = snd_timer_chip(timer); 820 struct snd_cs4231 *chip = snd_timer_chip(timer);
785 snd_cs4231_open(chip, CS4231_MODE_TIMER); 821 snd_cs4231_open(chip, CS4231_MODE_TIMER);
786 return 0; 822 return 0;
787 } 823 }
788 824
789 static int snd_cs4231_timer_close(struct snd_timer * timer) 825 static int snd_cs4231_timer_close(struct snd_timer * timer)
790 { 826 {
791 struct snd_cs4231 *chip = snd_timer_chip(timer); 827 struct snd_cs4231 *chip = snd_timer_chip(timer);
792 snd_cs4231_close(chip, CS4231_MODE_TIMER); 828 snd_cs4231_close(chip, CS4231_MODE_TIMER);
793 return 0; 829 return 0;
794 } 830 }
795 831
796 static struct snd_timer_hardware snd_cs4231_timer_table = 832 static struct snd_timer_hardware snd_cs4231_timer_table =
797 { 833 {
798 .flags = SNDRV_TIMER_HW_AUTO, 834 .flags = SNDRV_TIMER_HW_AUTO,
799 .resolution = 9945, 835 .resolution = 9945,
800 .ticks = 65535, 836 .ticks = 65535,
801 .open = snd_cs4231_timer_open, 837 .open = snd_cs4231_timer_open,
802 .close = snd_cs4231_timer_close, 838 .close = snd_cs4231_timer_close,
803 .c_resolution = snd_cs4231_timer_resolution, 839 .c_resolution = snd_cs4231_timer_resolution,
804 .start = snd_cs4231_timer_start, 840 .start = snd_cs4231_timer_start,
805 .stop = snd_cs4231_timer_stop, 841 .stop = snd_cs4231_timer_stop,
806 }; 842 };
807 843
808 /* 844 /*
809 * ok.. exported functions.. 845 * ok.. exported functions..
810 */ 846 */
811 847
812 static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream, 848 static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
813 struct snd_pcm_hw_params *hw_params) 849 struct snd_pcm_hw_params *hw_params)
814 { 850 {
815 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 851 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
816 unsigned char new_pdfr; 852 unsigned char new_pdfr;
817 int err; 853 int err;
818 854
819 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) 855 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
820 return err; 856 return err;
821 new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) | 857 new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
822 snd_cs4231_get_rate(params_rate(hw_params)); 858 snd_cs4231_get_rate(params_rate(hw_params));
823 chip->set_playback_format(chip, hw_params, new_pdfr); 859 chip->set_playback_format(chip, hw_params, new_pdfr);
824 return 0; 860 return 0;
825 } 861 }
826 862
827 static int snd_cs4231_playback_hw_free(struct snd_pcm_substream *substream) 863 static int snd_cs4231_playback_hw_free(struct snd_pcm_substream *substream)
828 { 864 {
829 return snd_pcm_lib_free_pages(substream); 865 return snd_pcm_lib_free_pages(substream);
830 } 866 }
831 867
832 static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream) 868 static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
833 { 869 {
834 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 870 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
835 struct snd_pcm_runtime *runtime = substream->runtime; 871 struct snd_pcm_runtime *runtime = substream->runtime;
836 unsigned long flags; 872 unsigned long flags;
837 unsigned int size = snd_pcm_lib_buffer_bytes(substream); 873 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
838 unsigned int count = snd_pcm_lib_period_bytes(substream); 874 unsigned int count = snd_pcm_lib_period_bytes(substream);
839 875
840 spin_lock_irqsave(&chip->reg_lock, flags); 876 spin_lock_irqsave(&chip->reg_lock, flags);
841 chip->p_dma_size = size; 877 chip->p_dma_size = size;
842 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO); 878 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
843 snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT); 879 snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
844 count = snd_cs4231_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1; 880 count = snd_cs4231_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
845 snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count); 881 snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
846 snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8)); 882 snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
847 spin_unlock_irqrestore(&chip->reg_lock, flags); 883 spin_unlock_irqrestore(&chip->reg_lock, flags);
848 #if 0 884 #if 0
849 snd_cs4231_debug(chip); 885 snd_cs4231_debug(chip);
850 #endif 886 #endif
851 return 0; 887 return 0;
852 } 888 }
853 889
854 static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream, 890 static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
855 struct snd_pcm_hw_params *hw_params) 891 struct snd_pcm_hw_params *hw_params)
856 { 892 {
857 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 893 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
858 unsigned char new_cdfr; 894 unsigned char new_cdfr;
859 int err; 895 int err;
860 896
861 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) 897 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
862 return err; 898 return err;
863 new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) | 899 new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
864 snd_cs4231_get_rate(params_rate(hw_params)); 900 snd_cs4231_get_rate(params_rate(hw_params));
865 chip->set_capture_format(chip, hw_params, new_cdfr); 901 chip->set_capture_format(chip, hw_params, new_cdfr);
866 return 0; 902 return 0;
867 } 903 }
868 904
869 static int snd_cs4231_capture_hw_free(struct snd_pcm_substream *substream) 905 static int snd_cs4231_capture_hw_free(struct snd_pcm_substream *substream)
870 { 906 {
871 return snd_pcm_lib_free_pages(substream); 907 return snd_pcm_lib_free_pages(substream);
872 } 908 }
873 909
874 static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream) 910 static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
875 { 911 {
876 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 912 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
877 struct snd_pcm_runtime *runtime = substream->runtime; 913 struct snd_pcm_runtime *runtime = substream->runtime;
878 unsigned long flags; 914 unsigned long flags;
879 unsigned int size = snd_pcm_lib_buffer_bytes(substream); 915 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
880 unsigned int count = snd_pcm_lib_period_bytes(substream); 916 unsigned int count = snd_pcm_lib_period_bytes(substream);
881 917
882 spin_lock_irqsave(&chip->reg_lock, flags); 918 spin_lock_irqsave(&chip->reg_lock, flags);
883 chip->c_dma_size = size; 919 chip->c_dma_size = size;
884 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO); 920 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
885 snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT); 921 snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
886 count = snd_cs4231_get_count(chip->image[CS4231_REC_FORMAT], count) - 1; 922 count = snd_cs4231_get_count(chip->image[CS4231_REC_FORMAT], count) - 1;
887 if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) { 923 if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
888 snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count); 924 snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
889 snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8)); 925 snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
890 } else { 926 } else {
891 snd_cs4231_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count); 927 snd_cs4231_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
892 snd_cs4231_out(chip, CS4231_REC_UPR_CNT, (unsigned char) (count >> 8)); 928 snd_cs4231_out(chip, CS4231_REC_UPR_CNT, (unsigned char) (count >> 8));
893 } 929 }
894 spin_unlock_irqrestore(&chip->reg_lock, flags); 930 spin_unlock_irqrestore(&chip->reg_lock, flags);
895 return 0; 931 return 0;
896 } 932 }
897 933
898 static void snd_cs4231_overrange(struct snd_cs4231 *chip) 934 void snd_cs4231_overrange(struct snd_cs4231 *chip)
899 { 935 {
900 unsigned long flags; 936 unsigned long flags;
901 unsigned char res; 937 unsigned char res;
902 938
903 spin_lock_irqsave(&chip->reg_lock, flags); 939 spin_lock_irqsave(&chip->reg_lock, flags);
904 res = snd_cs4231_in(chip, CS4231_TEST_INIT); 940 res = snd_cs4231_in(chip, CS4231_TEST_INIT);
905 spin_unlock_irqrestore(&chip->reg_lock, flags); 941 spin_unlock_irqrestore(&chip->reg_lock, flags);
906 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */ 942 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
907 chip->capture_substream->runtime->overrange++; 943 chip->capture_substream->runtime->overrange++;
908 } 944 }
909 945
910 irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id) 946 irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id)
911 { 947 {
912 struct snd_cs4231 *chip = dev_id; 948 struct snd_cs4231 *chip = dev_id;
913 unsigned char status; 949 unsigned char status;
914 950
915 status = snd_cs4231_in(chip, CS4231_IRQ_STATUS); 951 status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
916 if (status & CS4231_TIMER_IRQ) { 952 if (status & CS4231_TIMER_IRQ) {
917 if (chip->timer) 953 if (chip->timer)
918 snd_timer_interrupt(chip->timer, chip->timer->sticks); 954 snd_timer_interrupt(chip->timer, chip->timer->sticks);
919 } 955 }
920 if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) { 956 if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
921 if (status & CS4231_PLAYBACK_IRQ) { 957 if (status & CS4231_PLAYBACK_IRQ) {
922 if (chip->mode & CS4231_MODE_PLAY) { 958 if (chip->mode & CS4231_MODE_PLAY) {
923 if (chip->playback_substream) 959 if (chip->playback_substream)
924 snd_pcm_period_elapsed(chip->playback_substream); 960 snd_pcm_period_elapsed(chip->playback_substream);
925 } 961 }
926 if (chip->mode & CS4231_MODE_RECORD) { 962 if (chip->mode & CS4231_MODE_RECORD) {
927 if (chip->capture_substream) { 963 if (chip->capture_substream) {
928 snd_cs4231_overrange(chip); 964 snd_cs4231_overrange(chip);
929 snd_pcm_period_elapsed(chip->capture_substream); 965 snd_pcm_period_elapsed(chip->capture_substream);
930 } 966 }
931 } 967 }
932 } 968 }
933 } else { 969 } else {
934 if (status & CS4231_PLAYBACK_IRQ) { 970 if (status & CS4231_PLAYBACK_IRQ) {
935 if (chip->playback_substream) 971 if (chip->playback_substream)
936 snd_pcm_period_elapsed(chip->playback_substream); 972 snd_pcm_period_elapsed(chip->playback_substream);
937 } 973 }
938 if (status & CS4231_RECORD_IRQ) { 974 if (status & CS4231_RECORD_IRQ) {
939 if (chip->capture_substream) { 975 if (chip->capture_substream) {
940 snd_cs4231_overrange(chip); 976 snd_cs4231_overrange(chip);
941 snd_pcm_period_elapsed(chip->capture_substream); 977 snd_pcm_period_elapsed(chip->capture_substream);
942 } 978 }
943 } 979 }
944 } 980 }
945 981
946 spin_lock(&chip->reg_lock); 982 spin_lock(&chip->reg_lock);
947 snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0); 983 snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
948 spin_unlock(&chip->reg_lock); 984 spin_unlock(&chip->reg_lock);
949 return IRQ_HANDLED; 985 return IRQ_HANDLED;
950 } 986 }
951 987
952 static snd_pcm_uframes_t snd_cs4231_playback_pointer(struct snd_pcm_substream *substream) 988 static snd_pcm_uframes_t snd_cs4231_playback_pointer(struct snd_pcm_substream *substream)
953 { 989 {
954 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 990 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
955 size_t ptr; 991 size_t ptr;
956 992
957 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) 993 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
958 return 0; 994 return 0;
959 ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size); 995 ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
960 return bytes_to_frames(substream->runtime, ptr); 996 return bytes_to_frames(substream->runtime, ptr);
961 } 997 }
962 998
963 static snd_pcm_uframes_t snd_cs4231_capture_pointer(struct snd_pcm_substream *substream) 999 static snd_pcm_uframes_t snd_cs4231_capture_pointer(struct snd_pcm_substream *substream)
964 { 1000 {
965 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1001 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
966 size_t ptr; 1002 size_t ptr;
967 1003
968 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)) 1004 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
969 return 0; 1005 return 0;
970 ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size); 1006 ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
971 return bytes_to_frames(substream->runtime, ptr); 1007 return bytes_to_frames(substream->runtime, ptr);
972 } 1008 }
973 1009
974 /* 1010 /*
975 1011
976 */ 1012 */
977 1013
978 static int snd_cs4231_probe(struct snd_cs4231 *chip) 1014 static int snd_cs4231_probe(struct snd_cs4231 *chip)
979 { 1015 {
980 unsigned long flags; 1016 unsigned long flags;
981 int i, id, rev; 1017 int i, id, rev;
982 unsigned char *ptr; 1018 unsigned char *ptr;
983 unsigned int hw; 1019 unsigned int hw;
984 1020
985 #if 0 1021 #if 0
986 snd_cs4231_debug(chip); 1022 snd_cs4231_debug(chip);
987 #endif 1023 #endif
988 id = 0; 1024 id = 0;
989 for (i = 0; i < 50; i++) { 1025 for (i = 0; i < 50; i++) {
990 mb(); 1026 mb();
991 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) 1027 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
992 udelay(2000); 1028 udelay(2000);
993 else { 1029 else {
994 spin_lock_irqsave(&chip->reg_lock, flags); 1030 spin_lock_irqsave(&chip->reg_lock, flags);
995 snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2); 1031 snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
996 id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f; 1032 id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
997 spin_unlock_irqrestore(&chip->reg_lock, flags); 1033 spin_unlock_irqrestore(&chip->reg_lock, flags);
998 if (id == 0x0a) 1034 if (id == 0x0a)
999 break; /* this is valid value */ 1035 break; /* this is valid value */
1000 } 1036 }
1001 } 1037 }
1002 snd_printdd("cs4231: port = 0x%lx, id = 0x%x\n", chip->port, id); 1038 snd_printdd("cs4231: port = 0x%lx, id = 0x%x\n", chip->port, id);
1003 if (id != 0x0a) 1039 if (id != 0x0a)
1004 return -ENODEV; /* no valid device found */ 1040 return -ENODEV; /* no valid device found */
1005 1041
1006 if (((hw = chip->hardware) & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) { 1042 if (((hw = chip->hardware) & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
1007 rev = snd_cs4231_in(chip, CS4231_VERSION) & 0xe7; 1043 rev = snd_cs4231_in(chip, CS4231_VERSION) & 0xe7;
1008 snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev); 1044 snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
1009 if (rev == 0x80) { 1045 if (rev == 0x80) {
1010 unsigned char tmp = snd_cs4231_in(chip, 23); 1046 unsigned char tmp = snd_cs4231_in(chip, 23);
1011 snd_cs4231_out(chip, 23, ~tmp); 1047 snd_cs4231_out(chip, 23, ~tmp);
1012 if (snd_cs4231_in(chip, 23) != tmp) 1048 if (snd_cs4231_in(chip, 23) != tmp)
1013 chip->hardware = CS4231_HW_AD1845; 1049 chip->hardware = CS4231_HW_AD1845;
1014 else 1050 else
1015 chip->hardware = CS4231_HW_CS4231; 1051 chip->hardware = CS4231_HW_CS4231;
1016 } else if (rev == 0xa0) { 1052 } else if (rev == 0xa0) {
1017 chip->hardware = CS4231_HW_CS4231A; 1053 chip->hardware = CS4231_HW_CS4231A;
1018 } else if (rev == 0xa2) { 1054 } else if (rev == 0xa2) {
1019 chip->hardware = CS4231_HW_CS4232; 1055 chip->hardware = CS4231_HW_CS4232;
1020 } else if (rev == 0xb2) { 1056 } else if (rev == 0xb2) {
1021 chip->hardware = CS4231_HW_CS4232A; 1057 chip->hardware = CS4231_HW_CS4232A;
1022 } else if (rev == 0x83) { 1058 } else if (rev == 0x83) {
1023 chip->hardware = CS4231_HW_CS4236; 1059 chip->hardware = CS4231_HW_CS4236;
1024 } else if (rev == 0x03) { 1060 } else if (rev == 0x03) {
1025 chip->hardware = CS4231_HW_CS4236B; 1061 chip->hardware = CS4231_HW_CS4236B;
1026 } else { 1062 } else {
1027 snd_printk("unknown CS chip with version 0x%x\n", rev); 1063 snd_printk("unknown CS chip with version 0x%x\n", rev);
1028 return -ENODEV; /* unknown CS4231 chip? */ 1064 return -ENODEV; /* unknown CS4231 chip? */
1029 } 1065 }
1030 } 1066 }
1031 spin_lock_irqsave(&chip->reg_lock, flags); 1067 spin_lock_irqsave(&chip->reg_lock, flags);
1032 cs4231_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */ 1068 cs4231_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
1033 cs4231_outb(chip, CS4231P(STATUS), 0); 1069 cs4231_outb(chip, CS4231P(STATUS), 0);
1034 mb(); 1070 mb();
1035 spin_unlock_irqrestore(&chip->reg_lock, flags); 1071 spin_unlock_irqrestore(&chip->reg_lock, flags);
1036 1072
1037 chip->image[CS4231_MISC_INFO] = CS4231_MODE2; 1073 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1038 switch (chip->hardware) { 1074 switch (chip->hardware) {
1039 case CS4231_HW_INTERWAVE: 1075 case CS4231_HW_INTERWAVE:
1040 chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3; 1076 chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
1041 break; 1077 break;
1042 case CS4231_HW_CS4235: 1078 case CS4231_HW_CS4235:
1043 case CS4231_HW_CS4236B: 1079 case CS4231_HW_CS4236B:
1044 case CS4231_HW_CS4237B: 1080 case CS4231_HW_CS4237B:
1045 case CS4231_HW_CS4238B: 1081 case CS4231_HW_CS4238B:
1046 case CS4231_HW_CS4239: 1082 case CS4231_HW_CS4239:
1047 if (hw == CS4231_HW_DETECT3) 1083 if (hw == CS4231_HW_DETECT3)
1048 chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3; 1084 chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
1049 else 1085 else
1050 chip->hardware = CS4231_HW_CS4236; 1086 chip->hardware = CS4231_HW_CS4236;
1051 break; 1087 break;
1052 } 1088 }
1053 1089
1054 chip->image[CS4231_IFACE_CTRL] = 1090 chip->image[CS4231_IFACE_CTRL] =
1055 (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) | 1091 (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
1056 (chip->single_dma ? CS4231_SINGLE_DMA : 0); 1092 (chip->single_dma ? CS4231_SINGLE_DMA : 0);
1057 chip->image[CS4231_ALT_FEATURE_1] = 0x80; 1093 if (chip->hardware != CS4231_HW_OPTI93X) {
1058 chip->image[CS4231_ALT_FEATURE_2] = chip->hardware == CS4231_HW_INTERWAVE ? 0xc2 : 0x01; 1094 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1095 chip->image[CS4231_ALT_FEATURE_2] =
1096 chip->hardware == CS4231_HW_INTERWAVE ? 0xc2 : 0x01;
1097 }
1059 ptr = (unsigned char *) &chip->image; 1098 ptr = (unsigned char *) &chip->image;
1060 snd_cs4231_mce_down(chip); 1099 snd_cs4231_mce_down(chip);
1061 spin_lock_irqsave(&chip->reg_lock, flags); 1100 spin_lock_irqsave(&chip->reg_lock, flags);
1062 for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */ 1101 for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
1063 snd_cs4231_out(chip, i, *ptr++); 1102 snd_cs4231_out(chip, i, *ptr++);
1064 spin_unlock_irqrestore(&chip->reg_lock, flags); 1103 spin_unlock_irqrestore(&chip->reg_lock, flags);
1065 snd_cs4231_mce_up(chip); 1104 snd_cs4231_mce_up(chip);
1066 snd_cs4231_mce_down(chip); 1105 snd_cs4231_mce_down(chip);
1067 1106
1068 mdelay(2); 1107 mdelay(2);
1069 1108
1070 /* ok.. try check hardware version for CS4236+ chips */ 1109 /* ok.. try check hardware version for CS4236+ chips */
1071 if ((hw & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) { 1110 if ((hw & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
1072 if (chip->hardware == CS4231_HW_CS4236B) { 1111 if (chip->hardware == CS4231_HW_CS4236B) {
1073 rev = snd_cs4236_ext_in(chip, CS4236_VERSION); 1112 rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
1074 snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff); 1113 snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
1075 id = snd_cs4236_ext_in(chip, CS4236_VERSION); 1114 id = snd_cs4236_ext_in(chip, CS4236_VERSION);
1076 snd_cs4236_ext_out(chip, CS4236_VERSION, rev); 1115 snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
1077 snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id); 1116 snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
1078 if ((id & 0x1f) == 0x1d) { /* CS4235 */ 1117 if ((id & 0x1f) == 0x1d) { /* CS4235 */
1079 chip->hardware = CS4231_HW_CS4235; 1118 chip->hardware = CS4231_HW_CS4235;
1080 switch (id >> 5) { 1119 switch (id >> 5) {
1081 case 4: 1120 case 4:
1082 case 5: 1121 case 5:
1083 case 6: 1122 case 6:
1084 break; 1123 break;
1085 default: 1124 default:
1086 snd_printk("unknown CS4235 chip (enhanced version = 0x%x)\n", id); 1125 snd_printk("unknown CS4235 chip (enhanced version = 0x%x)\n", id);
1087 } 1126 }
1088 } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */ 1127 } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
1089 switch (id >> 5) { 1128 switch (id >> 5) {
1090 case 4: 1129 case 4:
1091 case 5: 1130 case 5:
1092 case 6: 1131 case 6:
1093 case 7: 1132 case 7:
1094 chip->hardware = CS4231_HW_CS4236B; 1133 chip->hardware = CS4231_HW_CS4236B;
1095 break; 1134 break;
1096 default: 1135 default:
1097 snd_printk("unknown CS4236 chip (enhanced version = 0x%x)\n", id); 1136 snd_printk("unknown CS4236 chip (enhanced version = 0x%x)\n", id);
1098 } 1137 }
1099 } else if ((id & 0x1f) == 0x08) { /* CS4237B */ 1138 } else if ((id & 0x1f) == 0x08) { /* CS4237B */
1100 chip->hardware = CS4231_HW_CS4237B; 1139 chip->hardware = CS4231_HW_CS4237B;
1101 switch (id >> 5) { 1140 switch (id >> 5) {
1102 case 4: 1141 case 4:
1103 case 5: 1142 case 5:
1104 case 6: 1143 case 6:
1105 case 7: 1144 case 7:
1106 break; 1145 break;
1107 default: 1146 default:
1108 snd_printk("unknown CS4237B chip (enhanced version = 0x%x)\n", id); 1147 snd_printk("unknown CS4237B chip (enhanced version = 0x%x)\n", id);
1109 } 1148 }
1110 } else if ((id & 0x1f) == 0x09) { /* CS4238B */ 1149 } else if ((id & 0x1f) == 0x09) { /* CS4238B */
1111 chip->hardware = CS4231_HW_CS4238B; 1150 chip->hardware = CS4231_HW_CS4238B;
1112 switch (id >> 5) { 1151 switch (id >> 5) {
1113 case 5: 1152 case 5:
1114 case 6: 1153 case 6:
1115 case 7: 1154 case 7:
1116 break; 1155 break;
1117 default: 1156 default:
1118 snd_printk("unknown CS4238B chip (enhanced version = 0x%x)\n", id); 1157 snd_printk("unknown CS4238B chip (enhanced version = 0x%x)\n", id);
1119 } 1158 }
1120 } else if ((id & 0x1f) == 0x1e) { /* CS4239 */ 1159 } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
1121 chip->hardware = CS4231_HW_CS4239; 1160 chip->hardware = CS4231_HW_CS4239;
1122 switch (id >> 5) { 1161 switch (id >> 5) {
1123 case 4: 1162 case 4:
1124 case 5: 1163 case 5:
1125 case 6: 1164 case 6:
1126 break; 1165 break;
1127 default: 1166 default:
1128 snd_printk("unknown CS4239 chip (enhanced version = 0x%x)\n", id); 1167 snd_printk("unknown CS4239 chip (enhanced version = 0x%x)\n", id);
1129 } 1168 }
1130 } else { 1169 } else {
1131 snd_printk("unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n", id); 1170 snd_printk("unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n", id);
1132 } 1171 }
1133 } 1172 }
1134 } 1173 }
1135 return 0; /* all things are ok.. */ 1174 return 0; /* all things are ok.. */
1136 } 1175 }
1137 1176
1138 /* 1177 /*
1139 1178
1140 */ 1179 */
1141 1180
1142 static struct snd_pcm_hardware snd_cs4231_playback = 1181 static struct snd_pcm_hardware snd_cs4231_playback =
1143 { 1182 {
1144 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1183 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1145 SNDRV_PCM_INFO_MMAP_VALID | 1184 SNDRV_PCM_INFO_MMAP_VALID |
1146 SNDRV_PCM_INFO_RESUME | 1185 SNDRV_PCM_INFO_RESUME |
1147 SNDRV_PCM_INFO_SYNC_START), 1186 SNDRV_PCM_INFO_SYNC_START),
1148 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM | 1187 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1149 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE), 1188 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1150 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000, 1189 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1151 .rate_min = 5510, 1190 .rate_min = 5510,
1152 .rate_max = 48000, 1191 .rate_max = 48000,
1153 .channels_min = 1, 1192 .channels_min = 1,
1154 .channels_max = 2, 1193 .channels_max = 2,
1155 .buffer_bytes_max = (128*1024), 1194 .buffer_bytes_max = (128*1024),
1156 .period_bytes_min = 64, 1195 .period_bytes_min = 64,
1157 .period_bytes_max = (128*1024), 1196 .period_bytes_max = (128*1024),
1158 .periods_min = 1, 1197 .periods_min = 1,
1159 .periods_max = 1024, 1198 .periods_max = 1024,
1160 .fifo_size = 0, 1199 .fifo_size = 0,
1161 }; 1200 };
1162 1201
1163 static struct snd_pcm_hardware snd_cs4231_capture = 1202 static struct snd_pcm_hardware snd_cs4231_capture =
1164 { 1203 {
1165 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1204 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1166 SNDRV_PCM_INFO_MMAP_VALID | 1205 SNDRV_PCM_INFO_MMAP_VALID |
1167 SNDRV_PCM_INFO_RESUME | 1206 SNDRV_PCM_INFO_RESUME |
1168 SNDRV_PCM_INFO_SYNC_START), 1207 SNDRV_PCM_INFO_SYNC_START),
1169 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM | 1208 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1170 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE), 1209 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1171 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000, 1210 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1172 .rate_min = 5510, 1211 .rate_min = 5510,
1173 .rate_max = 48000, 1212 .rate_max = 48000,
1174 .channels_min = 1, 1213 .channels_min = 1,
1175 .channels_max = 2, 1214 .channels_max = 2,
1176 .buffer_bytes_max = (128*1024), 1215 .buffer_bytes_max = (128*1024),
1177 .period_bytes_min = 64, 1216 .period_bytes_min = 64,
1178 .period_bytes_max = (128*1024), 1217 .period_bytes_max = (128*1024),
1179 .periods_min = 1, 1218 .periods_min = 1,
1180 .periods_max = 1024, 1219 .periods_max = 1024,
1181 .fifo_size = 0, 1220 .fifo_size = 0,
1182 }; 1221 };
1183 1222
1184 /* 1223 /*
1185 1224
1186 */ 1225 */
1187 1226
1188 static int snd_cs4231_playback_open(struct snd_pcm_substream *substream) 1227 static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
1189 { 1228 {
1190 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1229 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1191 struct snd_pcm_runtime *runtime = substream->runtime; 1230 struct snd_pcm_runtime *runtime = substream->runtime;
1192 int err; 1231 int err;
1193 1232
1194 runtime->hw = snd_cs4231_playback; 1233 runtime->hw = snd_cs4231_playback;
1195 1234
1196 /* hardware bug in InterWave chipset */ 1235 /* hardware bug in InterWave chipset */
1197 if (chip->hardware == CS4231_HW_INTERWAVE && chip->dma1 > 3) 1236 if (chip->hardware == CS4231_HW_INTERWAVE && chip->dma1 > 3)
1198 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW; 1237 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
1199 1238
1200 /* hardware limitation of cheap chips */ 1239 /* hardware limitation of cheap chips */
1201 if (chip->hardware == CS4231_HW_CS4235 || 1240 if (chip->hardware == CS4231_HW_CS4235 ||
1202 chip->hardware == CS4231_HW_CS4239) 1241 chip->hardware == CS4231_HW_CS4239)
1203 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE; 1242 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
1204 1243
1205 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max); 1244 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
1206 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max); 1245 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
1207 1246
1208 if (chip->claim_dma) { 1247 if (chip->claim_dma) {
1209 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0) 1248 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
1210 return err; 1249 return err;
1211 } 1250 }
1212 1251
1213 if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) { 1252 if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
1214 if (chip->release_dma) 1253 if (chip->release_dma)
1215 chip->release_dma(chip, chip->dma_private_data, chip->dma1); 1254 chip->release_dma(chip, chip->dma_private_data, chip->dma1);
1216 snd_free_pages(runtime->dma_area, runtime->dma_bytes); 1255 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1217 return err; 1256 return err;
1218 } 1257 }
1219 chip->playback_substream = substream; 1258 chip->playback_substream = substream;
1220 snd_pcm_set_sync(substream); 1259 snd_pcm_set_sync(substream);
1221 chip->rate_constraint(runtime); 1260 chip->rate_constraint(runtime);
1222 return 0; 1261 return 0;
1223 } 1262 }
1224 1263
1225 static int snd_cs4231_capture_open(struct snd_pcm_substream *substream) 1264 static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
1226 { 1265 {
1227 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1266 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1228 struct snd_pcm_runtime *runtime = substream->runtime; 1267 struct snd_pcm_runtime *runtime = substream->runtime;
1229 int err; 1268 int err;
1230 1269
1231 runtime->hw = snd_cs4231_capture; 1270 runtime->hw = snd_cs4231_capture;
1232 1271
1233 /* hardware limitation of cheap chips */ 1272 /* hardware limitation of cheap chips */
1234 if (chip->hardware == CS4231_HW_CS4235 || 1273 if (chip->hardware == CS4231_HW_CS4235 ||
1235 chip->hardware == CS4231_HW_CS4239) 1274 chip->hardware == CS4231_HW_CS4239)
1236 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE; 1275 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
1237 1276
1238 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max); 1277 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
1239 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max); 1278 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
1240 1279
1241 if (chip->claim_dma) { 1280 if (chip->claim_dma) {
1242 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0) 1281 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
1243 return err; 1282 return err;
1244 } 1283 }
1245 1284
1246 if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) { 1285 if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
1247 if (chip->release_dma) 1286 if (chip->release_dma)
1248 chip->release_dma(chip, chip->dma_private_data, chip->dma2); 1287 chip->release_dma(chip, chip->dma_private_data, chip->dma2);
1249 snd_free_pages(runtime->dma_area, runtime->dma_bytes); 1288 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1250 return err; 1289 return err;
1251 } 1290 }
1252 chip->capture_substream = substream; 1291 chip->capture_substream = substream;
1253 snd_pcm_set_sync(substream); 1292 snd_pcm_set_sync(substream);
1254 chip->rate_constraint(runtime); 1293 chip->rate_constraint(runtime);
1255 return 0; 1294 return 0;
1256 } 1295 }
1257 1296
1258 static int snd_cs4231_playback_close(struct snd_pcm_substream *substream) 1297 static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
1259 { 1298 {
1260 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1299 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1261 1300
1262 chip->playback_substream = NULL; 1301 chip->playback_substream = NULL;
1263 snd_cs4231_close(chip, CS4231_MODE_PLAY); 1302 snd_cs4231_close(chip, CS4231_MODE_PLAY);
1264 return 0; 1303 return 0;
1265 } 1304 }
1266 1305
1267 static int snd_cs4231_capture_close(struct snd_pcm_substream *substream) 1306 static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
1268 { 1307 {
1269 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1308 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1270 1309
1271 chip->capture_substream = NULL; 1310 chip->capture_substream = NULL;
1272 snd_cs4231_close(chip, CS4231_MODE_RECORD); 1311 snd_cs4231_close(chip, CS4231_MODE_RECORD);
1273 return 0; 1312 return 0;
1274 } 1313 }
1275 1314
1276 #ifdef CONFIG_PM 1315 #ifdef CONFIG_PM
1277 1316
1278 /* lowlevel suspend callback for CS4231 */ 1317 /* lowlevel suspend callback for CS4231 */
1279 static void snd_cs4231_suspend(struct snd_cs4231 *chip) 1318 static void snd_cs4231_suspend(struct snd_cs4231 *chip)
1280 { 1319 {
1281 int reg; 1320 int reg;
1282 unsigned long flags; 1321 unsigned long flags;
1283 1322
1284 snd_pcm_suspend_all(chip->pcm); 1323 snd_pcm_suspend_all(chip->pcm);
1285 spin_lock_irqsave(&chip->reg_lock, flags); 1324 spin_lock_irqsave(&chip->reg_lock, flags);
1286 for (reg = 0; reg < 32; reg++) 1325 for (reg = 0; reg < 32; reg++)
1287 chip->image[reg] = snd_cs4231_in(chip, reg); 1326 chip->image[reg] = snd_cs4231_in(chip, reg);
1288 spin_unlock_irqrestore(&chip->reg_lock, flags); 1327 spin_unlock_irqrestore(&chip->reg_lock, flags);
1289 } 1328 }
1290 1329
1291 /* lowlevel resume callback for CS4231 */ 1330 /* lowlevel resume callback for CS4231 */
1292 static void snd_cs4231_resume(struct snd_cs4231 *chip) 1331 static void snd_cs4231_resume(struct snd_cs4231 *chip)
1293 { 1332 {
1294 int reg; 1333 int reg;
1295 unsigned long flags; 1334 unsigned long flags;
1296 /* int timeout; */ 1335 /* int timeout; */
1297 1336
1298 snd_cs4231_mce_up(chip); 1337 snd_cs4231_mce_up(chip);
1299 spin_lock_irqsave(&chip->reg_lock, flags); 1338 spin_lock_irqsave(&chip->reg_lock, flags);
1300 for (reg = 0; reg < 32; reg++) { 1339 for (reg = 0; reg < 32; reg++) {
1301 switch (reg) { 1340 switch (reg) {
1302 case CS4231_VERSION: 1341 case CS4231_VERSION:
1303 break; 1342 break;
1304 default: 1343 default:
1305 snd_cs4231_out(chip, reg, chip->image[reg]); 1344 snd_cs4231_out(chip, reg, chip->image[reg]);
1306 break; 1345 break;
1307 } 1346 }
1308 } 1347 }
1309 spin_unlock_irqrestore(&chip->reg_lock, flags); 1348 spin_unlock_irqrestore(&chip->reg_lock, flags);
1310 #if 1 1349 #if 1
1311 snd_cs4231_mce_down(chip); 1350 snd_cs4231_mce_down(chip);
1312 #else 1351 #else
1313 /* The following is a workaround to avoid freeze after resume on TP600E. 1352 /* The following is a workaround to avoid freeze after resume on TP600E.
1314 This is the first half of copy of snd_cs4231_mce_down(), but doesn't 1353 This is the first half of copy of snd_cs4231_mce_down(), but doesn't
1315 include rescheduling. -- iwai 1354 include rescheduling. -- iwai
1316 */ 1355 */
1317 snd_cs4231_busy_wait(chip); 1356 snd_cs4231_busy_wait(chip);
1318 spin_lock_irqsave(&chip->reg_lock, flags); 1357 spin_lock_irqsave(&chip->reg_lock, flags);
1319 chip->mce_bit &= ~CS4231_MCE; 1358 chip->mce_bit &= ~CS4231_MCE;
1320 timeout = cs4231_inb(chip, CS4231P(REGSEL)); 1359 timeout = cs4231_inb(chip, CS4231P(REGSEL));
1321 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f)); 1360 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
1322 spin_unlock_irqrestore(&chip->reg_lock, flags); 1361 spin_unlock_irqrestore(&chip->reg_lock, flags);
1323 if (timeout == 0x80) 1362 if (timeout == 0x80)
1324 snd_printk("down [0x%lx]: serious init problem - codec still busy\n", chip->port); 1363 snd_printk("down [0x%lx]: serious init problem - codec still busy\n", chip->port);
1325 if ((timeout & CS4231_MCE) == 0 || 1364 if ((timeout & CS4231_MCE) == 0 ||
1326 !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) { 1365 !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
1327 return; 1366 return;
1328 } 1367 }
1329 snd_cs4231_busy_wait(chip); 1368 snd_cs4231_busy_wait(chip);
1330 #endif 1369 #endif
1331 } 1370 }
1332 #endif /* CONFIG_PM */ 1371 #endif /* CONFIG_PM */
1333 1372
1334 static int snd_cs4231_free(struct snd_cs4231 *chip) 1373 static int snd_cs4231_free(struct snd_cs4231 *chip)
1335 { 1374 {
1336 release_and_free_resource(chip->res_port); 1375 release_and_free_resource(chip->res_port);
1337 release_and_free_resource(chip->res_cport); 1376 release_and_free_resource(chip->res_cport);
1338 if (chip->irq >= 0) { 1377 if (chip->irq >= 0) {
1339 disable_irq(chip->irq); 1378 disable_irq(chip->irq);
1340 if (!(chip->hwshare & CS4231_HWSHARE_IRQ)) 1379 if (!(chip->hwshare & CS4231_HWSHARE_IRQ))
1341 free_irq(chip->irq, (void *) chip); 1380 free_irq(chip->irq, (void *) chip);
1342 } 1381 }
1343 if (!(chip->hwshare & CS4231_HWSHARE_DMA1) && chip->dma1 >= 0) { 1382 if (!(chip->hwshare & CS4231_HWSHARE_DMA1) && chip->dma1 >= 0) {
1344 snd_dma_disable(chip->dma1); 1383 snd_dma_disable(chip->dma1);
1345 free_dma(chip->dma1); 1384 free_dma(chip->dma1);
1346 } 1385 }
1347 if (!(chip->hwshare & CS4231_HWSHARE_DMA2) && chip->dma2 >= 0 && chip->dma2 != chip->dma1) { 1386 if (!(chip->hwshare & CS4231_HWSHARE_DMA2) && chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
1348 snd_dma_disable(chip->dma2); 1387 snd_dma_disable(chip->dma2);
1349 free_dma(chip->dma2); 1388 free_dma(chip->dma2);
1350 } 1389 }
1351 if (chip->timer) 1390 if (chip->timer)
1352 snd_device_free(chip->card, chip->timer); 1391 snd_device_free(chip->card, chip->timer);
1353 kfree(chip); 1392 kfree(chip);
1354 return 0; 1393 return 0;
1355 } 1394 }
1356 1395
1357 static int snd_cs4231_dev_free(struct snd_device *device) 1396 static int snd_cs4231_dev_free(struct snd_device *device)
1358 { 1397 {
1359 struct snd_cs4231 *chip = device->device_data; 1398 struct snd_cs4231 *chip = device->device_data;
1360 return snd_cs4231_free(chip); 1399 return snd_cs4231_free(chip);
1361 } 1400 }
1362 1401
1363 const char *snd_cs4231_chip_id(struct snd_cs4231 *chip) 1402 const char *snd_cs4231_chip_id(struct snd_cs4231 *chip)
1364 { 1403 {
1365 switch (chip->hardware) { 1404 switch (chip->hardware) {
1366 case CS4231_HW_CS4231: return "CS4231"; 1405 case CS4231_HW_CS4231: return "CS4231";
1367 case CS4231_HW_CS4231A: return "CS4231A"; 1406 case CS4231_HW_CS4231A: return "CS4231A";
1368 case CS4231_HW_CS4232: return "CS4232"; 1407 case CS4231_HW_CS4232: return "CS4232";
1369 case CS4231_HW_CS4232A: return "CS4232A"; 1408 case CS4231_HW_CS4232A: return "CS4232A";
1370 case CS4231_HW_CS4235: return "CS4235"; 1409 case CS4231_HW_CS4235: return "CS4235";
1371 case CS4231_HW_CS4236: return "CS4236"; 1410 case CS4231_HW_CS4236: return "CS4236";
1372 case CS4231_HW_CS4236B: return "CS4236B"; 1411 case CS4231_HW_CS4236B: return "CS4236B";
1373 case CS4231_HW_CS4237B: return "CS4237B"; 1412 case CS4231_HW_CS4237B: return "CS4237B";
1374 case CS4231_HW_CS4238B: return "CS4238B"; 1413 case CS4231_HW_CS4238B: return "CS4238B";
1375 case CS4231_HW_CS4239: return "CS4239"; 1414 case CS4231_HW_CS4239: return "CS4239";
1376 case CS4231_HW_INTERWAVE: return "AMD InterWave"; 1415 case CS4231_HW_INTERWAVE: return "AMD InterWave";
1377 case CS4231_HW_OPL3SA2: return chip->card->shortname; 1416 case CS4231_HW_OPL3SA2: return chip->card->shortname;
1378 case CS4231_HW_AD1845: return "AD1845"; 1417 case CS4231_HW_AD1845: return "AD1845";
1418 case CS4231_HW_OPTI93X: return "OPTi 93x";
1379 default: return "???"; 1419 default: return "???";
1380 } 1420 }
1381 } 1421 }
1382 1422
1383 static int snd_cs4231_new(struct snd_card *card, 1423 static int snd_cs4231_new(struct snd_card *card,
1384 unsigned short hardware, 1424 unsigned short hardware,
1385 unsigned short hwshare, 1425 unsigned short hwshare,
1386 struct snd_cs4231 ** rchip) 1426 struct snd_cs4231 ** rchip)
1387 { 1427 {
1388 struct snd_cs4231 *chip; 1428 struct snd_cs4231 *chip;
1389 1429
1390 *rchip = NULL; 1430 *rchip = NULL;
1391 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1431 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1392 if (chip == NULL) 1432 if (chip == NULL)
1393 return -ENOMEM; 1433 return -ENOMEM;
1394 chip->hardware = hardware; 1434 chip->hardware = hardware;
1395 chip->hwshare = hwshare; 1435 chip->hwshare = hwshare;
1396 1436
1397 spin_lock_init(&chip->reg_lock); 1437 spin_lock_init(&chip->reg_lock);
1398 mutex_init(&chip->mce_mutex); 1438 mutex_init(&chip->mce_mutex);
1399 mutex_init(&chip->open_mutex); 1439 mutex_init(&chip->open_mutex);
1400 chip->card = card; 1440 chip->card = card;
1401 chip->rate_constraint = snd_cs4231_xrate; 1441 chip->rate_constraint = snd_cs4231_xrate;
1402 chip->set_playback_format = snd_cs4231_playback_format; 1442 chip->set_playback_format = snd_cs4231_playback_format;
1403 chip->set_capture_format = snd_cs4231_capture_format; 1443 chip->set_capture_format = snd_cs4231_capture_format;
1404 memcpy(&chip->image, &snd_cs4231_original_image, sizeof(snd_cs4231_original_image)); 1444 if (chip->hardware == CS4231_HW_OPTI93X)
1405 1445 memcpy(&chip->image, &snd_opti93x_original_image,
1446 sizeof(snd_opti93x_original_image));
1447 else
1448 memcpy(&chip->image, &snd_cs4231_original_image,
1449 sizeof(snd_cs4231_original_image));
1450
1406 *rchip = chip; 1451 *rchip = chip;
1407 return 0; 1452 return 0;
1408 } 1453 }
1409 1454
1410 int snd_cs4231_create(struct snd_card *card, 1455 int snd_cs4231_create(struct snd_card *card,
1411 unsigned long port, 1456 unsigned long port,
1412 unsigned long cport, 1457 unsigned long cport,
1413 int irq, int dma1, int dma2, 1458 int irq, int dma1, int dma2,
1414 unsigned short hardware, 1459 unsigned short hardware,
1415 unsigned short hwshare, 1460 unsigned short hwshare,
1416 struct snd_cs4231 ** rchip) 1461 struct snd_cs4231 ** rchip)
1417 { 1462 {
1418 static struct snd_device_ops ops = { 1463 static struct snd_device_ops ops = {
1419 .dev_free = snd_cs4231_dev_free, 1464 .dev_free = snd_cs4231_dev_free,
1420 }; 1465 };
1421 struct snd_cs4231 *chip; 1466 struct snd_cs4231 *chip;
1422 int err; 1467 int err;
1423 1468
1424 err = snd_cs4231_new(card, hardware, hwshare, &chip); 1469 err = snd_cs4231_new(card, hardware, hwshare, &chip);
1425 if (err < 0) 1470 if (err < 0)
1426 return err; 1471 return err;
1427 1472
1428 chip->irq = -1; 1473 chip->irq = -1;
1429 chip->dma1 = -1; 1474 chip->dma1 = -1;
1430 chip->dma2 = -1; 1475 chip->dma2 = -1;
1431 1476
1432 if ((chip->res_port = request_region(port, 4, "CS4231")) == NULL) { 1477 if ((chip->res_port = request_region(port, 4, "CS4231")) == NULL) {
1433 snd_printk(KERN_ERR "cs4231: can't grab port 0x%lx\n", port); 1478 snd_printk(KERN_ERR "cs4231: can't grab port 0x%lx\n", port);
1434 snd_cs4231_free(chip); 1479 snd_cs4231_free(chip);
1435 return -EBUSY; 1480 return -EBUSY;
1436 } 1481 }
1437 chip->port = port; 1482 chip->port = port;
1438 if ((long)cport >= 0 && (chip->res_cport = request_region(cport, 8, "CS4232 Control")) == NULL) { 1483 if ((long)cport >= 0 && (chip->res_cport = request_region(cport, 8, "CS4232 Control")) == NULL) {
1439 snd_printk(KERN_ERR "cs4231: can't grab control port 0x%lx\n", cport); 1484 snd_printk(KERN_ERR "cs4231: can't grab control port 0x%lx\n", cport);
1440 snd_cs4231_free(chip); 1485 snd_cs4231_free(chip);
1441 return -ENODEV; 1486 return -ENODEV;
1442 } 1487 }
1443 chip->cport = cport; 1488 chip->cport = cport;
1444 if (!(hwshare & CS4231_HWSHARE_IRQ) && request_irq(irq, snd_cs4231_interrupt, IRQF_DISABLED, "CS4231", (void *) chip)) { 1489 if (!(hwshare & CS4231_HWSHARE_IRQ) && request_irq(irq, snd_cs4231_interrupt, IRQF_DISABLED, "CS4231", (void *) chip)) {
1445 snd_printk(KERN_ERR "cs4231: can't grab IRQ %d\n", irq); 1490 snd_printk(KERN_ERR "cs4231: can't grab IRQ %d\n", irq);
1446 snd_cs4231_free(chip); 1491 snd_cs4231_free(chip);
1447 return -EBUSY; 1492 return -EBUSY;
1448 } 1493 }
1449 chip->irq = irq; 1494 chip->irq = irq;
1450 if (!(hwshare & CS4231_HWSHARE_DMA1) && request_dma(dma1, "CS4231 - 1")) { 1495 if (!(hwshare & CS4231_HWSHARE_DMA1) && request_dma(dma1, "CS4231 - 1")) {
1451 snd_printk(KERN_ERR "cs4231: can't grab DMA1 %d\n", dma1); 1496 snd_printk(KERN_ERR "cs4231: can't grab DMA1 %d\n", dma1);
1452 snd_cs4231_free(chip); 1497 snd_cs4231_free(chip);
1453 return -EBUSY; 1498 return -EBUSY;
1454 } 1499 }
1455 chip->dma1 = dma1; 1500 chip->dma1 = dma1;
1456 if (!(hwshare & CS4231_HWSHARE_DMA2) && dma1 != dma2 && dma2 >= 0 && request_dma(dma2, "CS4231 - 2")) { 1501 if (!(hwshare & CS4231_HWSHARE_DMA2) && dma1 != dma2 && dma2 >= 0 && request_dma(dma2, "CS4231 - 2")) {
1457 snd_printk(KERN_ERR "cs4231: can't grab DMA2 %d\n", dma2); 1502 snd_printk(KERN_ERR "cs4231: can't grab DMA2 %d\n", dma2);
1458 snd_cs4231_free(chip); 1503 snd_cs4231_free(chip);
1459 return -EBUSY; 1504 return -EBUSY;
1460 } 1505 }
1461 if (dma1 == dma2 || dma2 < 0) { 1506 if (dma1 == dma2 || dma2 < 0) {
1462 chip->single_dma = 1; 1507 chip->single_dma = 1;
1463 chip->dma2 = chip->dma1; 1508 chip->dma2 = chip->dma1;
1464 } else 1509 } else
1465 chip->dma2 = dma2; 1510 chip->dma2 = dma2;
1466 1511
1467 /* global setup */ 1512 /* global setup */
1468 if (snd_cs4231_probe(chip) < 0) { 1513 if (snd_cs4231_probe(chip) < 0) {
1469 snd_cs4231_free(chip); 1514 snd_cs4231_free(chip);
1470 return -ENODEV; 1515 return -ENODEV;
1471 } 1516 }
1472 snd_cs4231_init(chip); 1517 snd_cs4231_init(chip);
1473 1518
1474 #if 0 1519 #if 0
1475 if (chip->hardware & CS4231_HW_CS4232_MASK) { 1520 if (chip->hardware & CS4231_HW_CS4232_MASK) {
1476 if (chip->res_cport == NULL) 1521 if (chip->res_cport == NULL)
1477 snd_printk("CS4232 control port features are not accessible\n"); 1522 snd_printk("CS4232 control port features are not accessible\n");
1478 } 1523 }
1479 #endif 1524 #endif
1480 1525
1481 /* Register device */ 1526 /* Register device */
1482 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1527 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1483 snd_cs4231_free(chip); 1528 snd_cs4231_free(chip);
1484 return err; 1529 return err;
1485 } 1530 }
1486 1531
1487 #ifdef CONFIG_PM 1532 #ifdef CONFIG_PM
1488 /* Power Management */ 1533 /* Power Management */
1489 chip->suspend = snd_cs4231_suspend; 1534 chip->suspend = snd_cs4231_suspend;
1490 chip->resume = snd_cs4231_resume; 1535 chip->resume = snd_cs4231_resume;
1491 #endif 1536 #endif
1492 1537
1493 *rchip = chip; 1538 *rchip = chip;
1494 return 0; 1539 return 0;
1495 } 1540 }
1496 1541
1497 static struct snd_pcm_ops snd_cs4231_playback_ops = { 1542 static struct snd_pcm_ops snd_cs4231_playback_ops = {
1498 .open = snd_cs4231_playback_open, 1543 .open = snd_cs4231_playback_open,
1499 .close = snd_cs4231_playback_close, 1544 .close = snd_cs4231_playback_close,
1500 .ioctl = snd_pcm_lib_ioctl, 1545 .ioctl = snd_pcm_lib_ioctl,
1501 .hw_params = snd_cs4231_playback_hw_params, 1546 .hw_params = snd_cs4231_playback_hw_params,
1502 .hw_free = snd_cs4231_playback_hw_free, 1547 .hw_free = snd_cs4231_playback_hw_free,
1503 .prepare = snd_cs4231_playback_prepare, 1548 .prepare = snd_cs4231_playback_prepare,
1504 .trigger = snd_cs4231_trigger, 1549 .trigger = snd_cs4231_trigger,
1505 .pointer = snd_cs4231_playback_pointer, 1550 .pointer = snd_cs4231_playback_pointer,
1506 }; 1551 };
1507 1552
1508 static struct snd_pcm_ops snd_cs4231_capture_ops = { 1553 static struct snd_pcm_ops snd_cs4231_capture_ops = {
1509 .open = snd_cs4231_capture_open, 1554 .open = snd_cs4231_capture_open,
1510 .close = snd_cs4231_capture_close, 1555 .close = snd_cs4231_capture_close,
1511 .ioctl = snd_pcm_lib_ioctl, 1556 .ioctl = snd_pcm_lib_ioctl,
1512 .hw_params = snd_cs4231_capture_hw_params, 1557 .hw_params = snd_cs4231_capture_hw_params,
1513 .hw_free = snd_cs4231_capture_hw_free, 1558 .hw_free = snd_cs4231_capture_hw_free,
1514 .prepare = snd_cs4231_capture_prepare, 1559 .prepare = snd_cs4231_capture_prepare,
1515 .trigger = snd_cs4231_trigger, 1560 .trigger = snd_cs4231_trigger,
1516 .pointer = snd_cs4231_capture_pointer, 1561 .pointer = snd_cs4231_capture_pointer,
1517 }; 1562 };
1518 1563
1519 int snd_cs4231_pcm(struct snd_cs4231 *chip, int device, struct snd_pcm **rpcm) 1564 int snd_cs4231_pcm(struct snd_cs4231 *chip, int device, struct snd_pcm **rpcm)
1520 { 1565 {
1521 struct snd_pcm *pcm; 1566 struct snd_pcm *pcm;
1522 int err; 1567 int err;
1523 1568
1524 if ((err = snd_pcm_new(chip->card, "CS4231", device, 1, 1, &pcm)) < 0) 1569 if ((err = snd_pcm_new(chip->card, "CS4231", device, 1, 1, &pcm)) < 0)
1525 return err; 1570 return err;
1526 1571
1527 spin_lock_init(&chip->reg_lock); 1572 spin_lock_init(&chip->reg_lock);
1528 mutex_init(&chip->mce_mutex); 1573 mutex_init(&chip->mce_mutex);
1529 mutex_init(&chip->open_mutex); 1574 mutex_init(&chip->open_mutex);
1530 1575
1531 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops); 1576 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
1532 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops); 1577 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
1533 1578
1534 /* global setup */ 1579 /* global setup */
1535 pcm->private_data = chip; 1580 pcm->private_data = chip;
1536 pcm->info_flags = 0; 1581 pcm->info_flags = 0;
1537 if (chip->single_dma) 1582 if (chip->single_dma)
1538 pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX; 1583 pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
1539 if (chip->hardware != CS4231_HW_INTERWAVE) 1584 if (chip->hardware != CS4231_HW_INTERWAVE)
1540 pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX; 1585 pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
1541 strcpy(pcm->name, snd_cs4231_chip_id(chip)); 1586 strcpy(pcm->name, snd_cs4231_chip_id(chip));
1542 1587
1543 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1588 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1544 snd_dma_isa_data(), 1589 snd_dma_isa_data(),
1545 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024); 1590 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
1546 1591
1547 chip->pcm = pcm; 1592 chip->pcm = pcm;
1548 if (rpcm) 1593 if (rpcm)
1549 *rpcm = pcm; 1594 *rpcm = pcm;
1550 return 0; 1595 return 0;
1551 } 1596 }
1552 1597
1553 static void snd_cs4231_timer_free(struct snd_timer *timer) 1598 static void snd_cs4231_timer_free(struct snd_timer *timer)
1554 { 1599 {
1555 struct snd_cs4231 *chip = timer->private_data; 1600 struct snd_cs4231 *chip = timer->private_data;
1556 chip->timer = NULL; 1601 chip->timer = NULL;
1557 } 1602 }
1558 1603
1559 int snd_cs4231_timer(struct snd_cs4231 *chip, int device, struct snd_timer **rtimer) 1604 int snd_cs4231_timer(struct snd_cs4231 *chip, int device, struct snd_timer **rtimer)
1560 { 1605 {
1561 struct snd_timer *timer; 1606 struct snd_timer *timer;
1562 struct snd_timer_id tid; 1607 struct snd_timer_id tid;
1563 int err; 1608 int err;
1564 1609
1565 /* Timer initialization */ 1610 /* Timer initialization */
1566 tid.dev_class = SNDRV_TIMER_CLASS_CARD; 1611 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1567 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE; 1612 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1568 tid.card = chip->card->number; 1613 tid.card = chip->card->number;
1569 tid.device = device; 1614 tid.device = device;
1570 tid.subdevice = 0; 1615 tid.subdevice = 0;
1571 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0) 1616 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
1572 return err; 1617 return err;
1573 strcpy(timer->name, snd_cs4231_chip_id(chip)); 1618 strcpy(timer->name, snd_cs4231_chip_id(chip));
1574 timer->private_data = chip; 1619 timer->private_data = chip;
1575 timer->private_free = snd_cs4231_timer_free; 1620 timer->private_free = snd_cs4231_timer_free;
1576 timer->hw = snd_cs4231_timer_table; 1621 timer->hw = snd_cs4231_timer_table;
1577 chip->timer = timer; 1622 chip->timer = timer;
1578 if (rtimer) 1623 if (rtimer)
1579 *rtimer = timer; 1624 *rtimer = timer;
1580 return 0; 1625 return 0;
1581 } 1626 }
1582 1627
1583 /* 1628 /*
1584 * MIXER part 1629 * MIXER part
1585 */ 1630 */
1586 1631
1587 static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1632 static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1588 { 1633 {
1589 static char *texts[4] = { 1634 static char *texts[4] = {
1590 "Line", "Aux", "Mic", "Mix" 1635 "Line", "Aux", "Mic", "Mix"
1591 }; 1636 };
1592 static char *opl3sa_texts[4] = { 1637 static char *opl3sa_texts[4] = {
1593 "Line", "CD", "Mic", "Mix" 1638 "Line", "CD", "Mic", "Mix"
1594 }; 1639 };
1595 static char *gusmax_texts[4] = { 1640 static char *gusmax_texts[4] = {
1596 "Line", "Synth", "Mic", "Mix" 1641 "Line", "Synth", "Mic", "Mix"
1597 }; 1642 };
1598 char **ptexts = texts; 1643 char **ptexts = texts;
1599 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1644 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1600 1645
1601 snd_assert(chip->card != NULL, return -EINVAL); 1646 snd_assert(chip->card != NULL, return -EINVAL);
1602 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1647 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1603 uinfo->count = 2; 1648 uinfo->count = 2;
1604 uinfo->value.enumerated.items = 4; 1649 uinfo->value.enumerated.items = 4;
1605 if (uinfo->value.enumerated.item > 3) 1650 if (uinfo->value.enumerated.item > 3)
1606 uinfo->value.enumerated.item = 3; 1651 uinfo->value.enumerated.item = 3;
1607 if (!strcmp(chip->card->driver, "GUS MAX")) 1652 if (!strcmp(chip->card->driver, "GUS MAX"))
1608 ptexts = gusmax_texts; 1653 ptexts = gusmax_texts;
1609 switch (chip->hardware) { 1654 switch (chip->hardware) {
1610 case CS4231_HW_INTERWAVE: ptexts = gusmax_texts; break; 1655 case CS4231_HW_INTERWAVE: ptexts = gusmax_texts; break;
1611 case CS4231_HW_OPL3SA2: ptexts = opl3sa_texts; break; 1656 case CS4231_HW_OPL3SA2: ptexts = opl3sa_texts; break;
1612 } 1657 }
1613 strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]); 1658 strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
1614 return 0; 1659 return 0;
1615 } 1660 }
1616 1661
1617 static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1662 static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1618 { 1663 {
1619 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1664 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1620 unsigned long flags; 1665 unsigned long flags;
1621 1666
1622 spin_lock_irqsave(&chip->reg_lock, flags); 1667 spin_lock_irqsave(&chip->reg_lock, flags);
1623 ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6; 1668 ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
1624 ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6; 1669 ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
1625 spin_unlock_irqrestore(&chip->reg_lock, flags); 1670 spin_unlock_irqrestore(&chip->reg_lock, flags);
1626 return 0; 1671 return 0;
1627 } 1672 }
1628 1673
1629 static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1674 static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1630 { 1675 {
1631 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1676 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1632 unsigned long flags; 1677 unsigned long flags;
1633 unsigned short left, right; 1678 unsigned short left, right;
1634 int change; 1679 int change;
1635 1680
1636 if (ucontrol->value.enumerated.item[0] > 3 || 1681 if (ucontrol->value.enumerated.item[0] > 3 ||
1637 ucontrol->value.enumerated.item[1] > 3) 1682 ucontrol->value.enumerated.item[1] > 3)
1638 return -EINVAL; 1683 return -EINVAL;
1639 left = ucontrol->value.enumerated.item[0] << 6; 1684 left = ucontrol->value.enumerated.item[0] << 6;
1640 right = ucontrol->value.enumerated.item[1] << 6; 1685 right = ucontrol->value.enumerated.item[1] << 6;
1641 spin_lock_irqsave(&chip->reg_lock, flags); 1686 spin_lock_irqsave(&chip->reg_lock, flags);
1642 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left; 1687 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
1643 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right; 1688 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
1644 change = left != chip->image[CS4231_LEFT_INPUT] || 1689 change = left != chip->image[CS4231_LEFT_INPUT] ||
1645 right != chip->image[CS4231_RIGHT_INPUT]; 1690 right != chip->image[CS4231_RIGHT_INPUT];
1646 snd_cs4231_out(chip, CS4231_LEFT_INPUT, left); 1691 snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
1647 snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right); 1692 snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
1648 spin_unlock_irqrestore(&chip->reg_lock, flags); 1693 spin_unlock_irqrestore(&chip->reg_lock, flags);
1649 return change; 1694 return change;
1650 } 1695 }
1651 1696
1652 int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1697 int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1653 { 1698 {
1654 int mask = (kcontrol->private_value >> 16) & 0xff; 1699 int mask = (kcontrol->private_value >> 16) & 0xff;
1655 1700
1656 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 1701 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1657 uinfo->count = 1; 1702 uinfo->count = 1;
1658 uinfo->value.integer.min = 0; 1703 uinfo->value.integer.min = 0;
1659 uinfo->value.integer.max = mask; 1704 uinfo->value.integer.max = mask;
1660 return 0; 1705 return 0;
1661 } 1706 }
1662 1707
1663 int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1708 int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1664 { 1709 {
1665 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1710 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1666 unsigned long flags; 1711 unsigned long flags;
1667 int reg = kcontrol->private_value & 0xff; 1712 int reg = kcontrol->private_value & 0xff;
1668 int shift = (kcontrol->private_value >> 8) & 0xff; 1713 int shift = (kcontrol->private_value >> 8) & 0xff;
1669 int mask = (kcontrol->private_value >> 16) & 0xff; 1714 int mask = (kcontrol->private_value >> 16) & 0xff;
1670 int invert = (kcontrol->private_value >> 24) & 0xff; 1715 int invert = (kcontrol->private_value >> 24) & 0xff;
1671 1716
1672 spin_lock_irqsave(&chip->reg_lock, flags); 1717 spin_lock_irqsave(&chip->reg_lock, flags);
1673 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask; 1718 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
1674 spin_unlock_irqrestore(&chip->reg_lock, flags); 1719 spin_unlock_irqrestore(&chip->reg_lock, flags);
1675 if (invert) 1720 if (invert)
1676 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; 1721 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
1677 return 0; 1722 return 0;
1678 } 1723 }
1679 1724
1680 int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1725 int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1681 { 1726 {
1682 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1727 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1683 unsigned long flags; 1728 unsigned long flags;
1684 int reg = kcontrol->private_value & 0xff; 1729 int reg = kcontrol->private_value & 0xff;
1685 int shift = (kcontrol->private_value >> 8) & 0xff; 1730 int shift = (kcontrol->private_value >> 8) & 0xff;
1686 int mask = (kcontrol->private_value >> 16) & 0xff; 1731 int mask = (kcontrol->private_value >> 16) & 0xff;
1687 int invert = (kcontrol->private_value >> 24) & 0xff; 1732 int invert = (kcontrol->private_value >> 24) & 0xff;
1688 int change; 1733 int change;
1689 unsigned short val; 1734 unsigned short val;
1690 1735
1691 val = (ucontrol->value.integer.value[0] & mask); 1736 val = (ucontrol->value.integer.value[0] & mask);
1692 if (invert) 1737 if (invert)
1693 val = mask - val; 1738 val = mask - val;
1694 val <<= shift; 1739 val <<= shift;
1695 spin_lock_irqsave(&chip->reg_lock, flags); 1740 spin_lock_irqsave(&chip->reg_lock, flags);
1696 val = (chip->image[reg] & ~(mask << shift)) | val; 1741 val = (chip->image[reg] & ~(mask << shift)) | val;
1697 change = val != chip->image[reg]; 1742 change = val != chip->image[reg];
1698 snd_cs4231_out(chip, reg, val); 1743 snd_cs4231_out(chip, reg, val);
1699 spin_unlock_irqrestore(&chip->reg_lock, flags); 1744 spin_unlock_irqrestore(&chip->reg_lock, flags);
1700 return change; 1745 return change;
1701 } 1746 }
1702 1747
1703 int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1748 int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1704 { 1749 {
1705 int mask = (kcontrol->private_value >> 24) & 0xff; 1750 int mask = (kcontrol->private_value >> 24) & 0xff;
1706 1751
1707 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 1752 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1708 uinfo->count = 2; 1753 uinfo->count = 2;
1709 uinfo->value.integer.min = 0; 1754 uinfo->value.integer.min = 0;
1710 uinfo->value.integer.max = mask; 1755 uinfo->value.integer.max = mask;
1711 return 0; 1756 return 0;
1712 } 1757 }
1713 1758
1714 int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1759 int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1715 { 1760 {
1716 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1761 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1717 unsigned long flags; 1762 unsigned long flags;
1718 int left_reg = kcontrol->private_value & 0xff; 1763 int left_reg = kcontrol->private_value & 0xff;
1719 int right_reg = (kcontrol->private_value >> 8) & 0xff; 1764 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1720 int shift_left = (kcontrol->private_value >> 16) & 0x07; 1765 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1721 int shift_right = (kcontrol->private_value >> 19) & 0x07; 1766 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1722 int mask = (kcontrol->private_value >> 24) & 0xff; 1767 int mask = (kcontrol->private_value >> 24) & 0xff;
1723 int invert = (kcontrol->private_value >> 22) & 1; 1768 int invert = (kcontrol->private_value >> 22) & 1;
1724 1769
1725 spin_lock_irqsave(&chip->reg_lock, flags); 1770 spin_lock_irqsave(&chip->reg_lock, flags);
1726 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask; 1771 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
1727 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask; 1772 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
1728 spin_unlock_irqrestore(&chip->reg_lock, flags); 1773 spin_unlock_irqrestore(&chip->reg_lock, flags);
1729 if (invert) { 1774 if (invert) {
1730 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; 1775 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
1731 ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; 1776 ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
1732 } 1777 }
1733 return 0; 1778 return 0;
1734 } 1779 }
1735 1780
1736 int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1781 int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1737 { 1782 {
1738 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1783 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1739 unsigned long flags; 1784 unsigned long flags;
1740 int left_reg = kcontrol->private_value & 0xff; 1785 int left_reg = kcontrol->private_value & 0xff;
1741 int right_reg = (kcontrol->private_value >> 8) & 0xff; 1786 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1742 int shift_left = (kcontrol->private_value >> 16) & 0x07; 1787 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1743 int shift_right = (kcontrol->private_value >> 19) & 0x07; 1788 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1744 int mask = (kcontrol->private_value >> 24) & 0xff; 1789 int mask = (kcontrol->private_value >> 24) & 0xff;
1745 int invert = (kcontrol->private_value >> 22) & 1; 1790 int invert = (kcontrol->private_value >> 22) & 1;
1746 int change; 1791 int change;
1747 unsigned short val1, val2; 1792 unsigned short val1, val2;
1748 1793
1749 val1 = ucontrol->value.integer.value[0] & mask; 1794 val1 = ucontrol->value.integer.value[0] & mask;
1750 val2 = ucontrol->value.integer.value[1] & mask; 1795 val2 = ucontrol->value.integer.value[1] & mask;
1751 if (invert) { 1796 if (invert) {
1752 val1 = mask - val1; 1797 val1 = mask - val1;
1753 val2 = mask - val2; 1798 val2 = mask - val2;
1754 } 1799 }
1755 val1 <<= shift_left; 1800 val1 <<= shift_left;
1756 val2 <<= shift_right; 1801 val2 <<= shift_right;
1757 spin_lock_irqsave(&chip->reg_lock, flags); 1802 spin_lock_irqsave(&chip->reg_lock, flags);
1758 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1; 1803 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
1759 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2; 1804 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
1760 change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg]; 1805 change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
1761 snd_cs4231_out(chip, left_reg, val1); 1806 snd_cs4231_out(chip, left_reg, val1);
1762 snd_cs4231_out(chip, right_reg, val2); 1807 snd_cs4231_out(chip, right_reg, val2);
1763 spin_unlock_irqrestore(&chip->reg_lock, flags); 1808 spin_unlock_irqrestore(&chip->reg_lock, flags);
1764 return change; 1809 return change;
1765 } 1810 }
1766 1811
1767 static struct snd_kcontrol_new snd_cs4231_controls[] = { 1812 static struct snd_kcontrol_new snd_cs4231_controls[] = {
1768 CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1), 1813 CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
1769 CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1), 1814 CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
1770 CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1), 1815 CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
1771 CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1), 1816 CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
1772 CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1), 1817 CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
1773 CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1), 1818 CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
1774 CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1), 1819 CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
1775 CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1), 1820 CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
1776 CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1), 1821 CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
1777 CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1), 1822 CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
1778 CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1), 1823 CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
1779 CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0), 1824 CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
1780 CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0), 1825 CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
1781 { 1826 {
1782 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1827 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1783 .name = "Capture Source", 1828 .name = "Capture Source",
1784 .info = snd_cs4231_info_mux, 1829 .info = snd_cs4231_info_mux,
1785 .get = snd_cs4231_get_mux, 1830 .get = snd_cs4231_get_mux,
1786 .put = snd_cs4231_put_mux, 1831 .put = snd_cs4231_put_mux,
1787 }, 1832 },
1788 CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0), 1833 CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
1789 CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0), 1834 CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
1790 CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1) 1835 CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1)
1791 }; 1836 };
1792 1837
1838 static struct snd_kcontrol_new snd_opti93x_controls[] = {
1839 CS4231_DOUBLE("Master Playback Switch", 0,
1840 OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 7, 7, 1, 1),
1841 CS4231_DOUBLE("Master Playback Volume", 0,
1842 OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 1, 1, 31, 1),
1843 CS4231_DOUBLE("PCM Playback Switch", 0,
1844 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
1845 CS4231_DOUBLE("PCM Playback Volume", 0,
1846 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 31, 1),
1847 CS4231_DOUBLE("FM Playback Switch", 0,
1848 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
1849 CS4231_DOUBLE("FM Playback Volume", 0,
1850 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 1, 1, 15, 1),
1851 CS4231_DOUBLE("Line Playback Switch", 0,
1852 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
1853 CS4231_DOUBLE("Line Playback Volume", 0,
1854 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 15, 1),
1855 CS4231_DOUBLE("Mic Playback Switch", 0,
1856 OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 7, 7, 1, 1),
1857 CS4231_DOUBLE("Mic Playback Volume", 0,
1858 OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 1, 1, 15, 1),
1859 CS4231_DOUBLE("Mic Boost", 0,
1860 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
1861 CS4231_DOUBLE("CD Playback Switch", 0,
1862 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
1863 CS4231_DOUBLE("CD Playback Volume", 0,
1864 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 1, 1, 15, 1),
1865 CS4231_DOUBLE("Aux Playback Switch", 0,
1866 OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 7, 7, 1, 1),
1867 CS4231_DOUBLE("Aux Playback Volume", 0,
1868 OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 1, 1, 15, 1),
1869 CS4231_DOUBLE("Capture Volume", 0,
1870 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
1871 {
1872 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1873 .name = "Capture Source",
1874 .info = snd_cs4231_info_mux,
1875 .get = snd_cs4231_get_mux,
1876 .put = snd_cs4231_put_mux,
1877 }
1878 };
1879
1793 int snd_cs4231_mixer(struct snd_cs4231 *chip) 1880 int snd_cs4231_mixer(struct snd_cs4231 *chip)
1794 { 1881 {
1795 struct snd_card *card; 1882 struct snd_card *card;
1796 unsigned int idx; 1883 unsigned int idx;
1797 int err; 1884 int err;
1798 1885
1799 snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL); 1886 snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
1800 1887
1801 card = chip->card; 1888 card = chip->card;
1802 1889
1803 strcpy(card->mixername, chip->pcm->name); 1890 strcpy(card->mixername, chip->pcm->name);
1804 1891
1805 for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) { 1892 if (chip->hardware == CS4231_HW_OPTI93X)
1806 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4231_controls[idx], chip))) < 0) 1893 for (idx = 0; idx < ARRAY_SIZE(snd_opti93x_controls); idx++) {
1807 return err; 1894 err = snd_ctl_add(card,
1808 } 1895 snd_ctl_new1(&snd_opti93x_controls[idx],
1896 chip));
1897 if (err < 0)
1898 return err;
1899 }
1900 else
1901 for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
1902 err = snd_ctl_add(card,
1903 snd_ctl_new1(&snd_cs4231_controls[idx],
1904 chip));
1905 if (err < 0)
1906 return err;
1907 }
1809 return 0; 1908 return 0;
1810 } 1909 }
1811 1910
1812 EXPORT_SYMBOL(snd_cs4231_out); 1911 EXPORT_SYMBOL(snd_cs4231_out);
1813 EXPORT_SYMBOL(snd_cs4231_in); 1912 EXPORT_SYMBOL(snd_cs4231_in);
1814 EXPORT_SYMBOL(snd_cs4236_ext_out); 1913 EXPORT_SYMBOL(snd_cs4236_ext_out);
1815 EXPORT_SYMBOL(snd_cs4236_ext_in); 1914 EXPORT_SYMBOL(snd_cs4236_ext_in);
1816 EXPORT_SYMBOL(snd_cs4231_mce_up); 1915 EXPORT_SYMBOL(snd_cs4231_mce_up);
1817 EXPORT_SYMBOL(snd_cs4231_mce_down); 1916 EXPORT_SYMBOL(snd_cs4231_mce_down);
1917 EXPORT_SYMBOL(snd_cs4231_overrange);
1818 EXPORT_SYMBOL(snd_cs4231_interrupt); 1918 EXPORT_SYMBOL(snd_cs4231_interrupt);
1819 EXPORT_SYMBOL(snd_cs4231_chip_id); 1919 EXPORT_SYMBOL(snd_cs4231_chip_id);
1820 EXPORT_SYMBOL(snd_cs4231_create); 1920 EXPORT_SYMBOL(snd_cs4231_create);
1821 EXPORT_SYMBOL(snd_cs4231_pcm); 1921 EXPORT_SYMBOL(snd_cs4231_pcm);
1822 EXPORT_SYMBOL(snd_cs4231_mixer); 1922 EXPORT_SYMBOL(snd_cs4231_mixer);
1823 EXPORT_SYMBOL(snd_cs4231_timer); 1923 EXPORT_SYMBOL(snd_cs4231_timer);
1824 EXPORT_SYMBOL(snd_cs4231_info_single); 1924 EXPORT_SYMBOL(snd_cs4231_info_single);
1825 EXPORT_SYMBOL(snd_cs4231_get_single); 1925 EXPORT_SYMBOL(snd_cs4231_get_single);
1826 EXPORT_SYMBOL(snd_cs4231_put_single); 1926 EXPORT_SYMBOL(snd_cs4231_put_single);
1827 EXPORT_SYMBOL(snd_cs4231_info_double); 1927 EXPORT_SYMBOL(snd_cs4231_info_double);
1828 EXPORT_SYMBOL(snd_cs4231_get_double); 1928 EXPORT_SYMBOL(snd_cs4231_get_double);
1829 EXPORT_SYMBOL(snd_cs4231_put_double); 1929 EXPORT_SYMBOL(snd_cs4231_put_double);
1830 1930
1831 /* 1931 /*
1832 * INIT part 1932 * INIT part
1833 */ 1933 */
1834 1934
1835 static int __init alsa_cs4231_init(void) 1935 static int __init alsa_cs4231_init(void)
1836 { 1936 {
1837 return 0; 1937 return 0;
1838 } 1938 }
1839 1939
1840 static void __exit alsa_cs4231_exit(void) 1940 static void __exit alsa_cs4231_exit(void)
1841 { 1941 {
1842 } 1942 }
1843 1943
1844 module_init(alsa_cs4231_init) 1944 module_init(alsa_cs4231_init)
1845 module_exit(alsa_cs4231_exit) 1945 module_exit(alsa_cs4231_exit)
1846 1946