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Commit b08b4f8e63e60a64f81e194269be14afee396f33

Authored by GuanXuetao
1 parent fa7499ef77
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

unicore32 machine related files: hardware registers 

This patch adds all hardware registers definitions.

Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>

Showing 20 changed files with 1615 additions and 0 deletions Inline Diff

arch/unicore32/include/mach/PKUnity.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * linux/arch/unicore32/include/mach/PKUnity.h
3 *
4 * Code specific to PKUnity SoC and UniCore ISA
5 *
6 * Copyright (C) 2001-2010 GUAN Xue-tao
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 /* Be sure that virtual mapping is defined right */
14 #ifndef __MACH_PUV3_HARDWARE_H__
15 #error You must include hardware.h not PKUnity.h
16 #endif
17
18 #include "bitfield.h"
19
20 /*
21 * Memory Definitions
22 */
23 #define PKUNITY_SDRAM_BASE 0x00000000 /* 0x00000000 - 0x7FFFFFFF 2GB */
24 #define PKUNITY_IOSPACE_BASE 0x80000000 /* 0x80000000 - 0xFFFFFFFF 2GB */
25 #define PKUNITY_PCI_BASE 0x80000000 /* 0x80000000 - 0xBFFFFFFF 1GB */
26 #include "regs-pci.h"
27 #define PKUNITY_BOOT_ROM2_BASE 0xF4000000 /* 0xF4000000 - 0xF7FFFFFF 64MB */
28 #define PKUNITY_BOOT_SRAM2_BASE 0xF8000000 /* 0xF8000000 - 0xFBFFFFFF 64MB */
29 #define PKUNITY_BOOT_FLASH_BASE 0xFC000000 /* 0xFC000000 - 0xFFFFFFFF 64MB */
30
31 /*
32 * PKUNITY Memory Map Addresses: 0x0D000000 - 0x0EFFFFFF (32MB)
33 */
34 #define PKUNITY_UVC_MMAP_BASE 0x0D000000 /* 0x0D000000 - 0x0DFFFFFF 16MB */
35 #define PKUNITY_UVC_MMAP_SIZE 0x01000000 /* 16MB */
36 #define PKUNITY_UNIGFX_MMAP_BASE 0x0E000000 /* 0x0E000000 - 0x0EFFFFFF 16MB */
37 #define PKUNITY_UNIGFX_MMAP_SIZE 0x01000000 /* 16MB */
38
39 /*
40 * PKUNITY System Bus Addresses (PCI): 0x80000000 - 0xBFFFFFFF (1GB)
41 */
42 /* PCI Configuration regs */
43 #define PKUNITY_PCICFG_BASE 0x80000000 /* 0x80000000 - 0x8000000B 12B */
44 /* PCI Bridge Base */
45 #define PKUNITY_PCIBRI_BASE 0x80010000 /* 0x80010000 - 0x80010250 592B */
46 /* PCI Legacy IO */
47 #define PKUNITY_PCILIO_BASE 0x80030000 /* 0x80030000 - 0x8003FFFF 64KB */
48 /* PCI AHB-PCI MEM-mapping */
49 #define PKUNITY_PCIMEM_BASE 0x90000000 /* 0x90000000 - 0x97FFFFFF 128MB */
50 /* PCI PCI-AHB MEM-mapping */
51 #define PKUNITY_PCIAHB_BASE 0x98000000 /* 0x98000000 - 0x9FFFFFFF 128MB */
52
53 /*
54 * PKUNITY System Bus Addresses (AHB): 0xC0000000 - 0xEDFFFFFF (640MB)
55 */
56 /* AHB-0 is DDR2 SDRAM */
57 /* AHB-1 is PCI Space */
58 #define PKUNITY_ARBITER_BASE 0xC0000000 /* AHB-2 */
59 #define PKUNITY_DDR2CTRL_BASE 0xC0100000 /* AHB-3 */
60 #define PKUNITY_DMAC_BASE 0xC0200000 /* AHB-4 */
61 #include "regs-dmac.h"
62 #define PKUNITY_UMAL_BASE 0xC0300000 /* AHB-5 */
63 #include "regs-umal.h"
64 #define PKUNITY_USB_BASE 0xC0400000 /* AHB-6 */
65 #define PKUNITY_SATA_BASE 0xC0500000 /* AHB-7 */
66 #define PKUNITY_SMC_BASE 0xC0600000 /* AHB-8 */
67 /* AHB-9 is for APB bridge */
68 #define PKUNITY_MME_BASE 0xC0700000 /* AHB-10 */
69 #define PKUNITY_UNIGFX_BASE 0xC0800000 /* AHB-11 */
70 #include "regs-unigfx.h"
71 #define PKUNITY_NAND_BASE 0xC0900000 /* AHB-12 */
72 #include "regs-nand.h"
73 #define PKUNITY_H264D_BASE 0xC0A00000 /* AHB-13 */
74 #define PKUNITY_H264E_BASE 0xC0B00000 /* AHB-14 */
75
76 /*
77 * PKUNITY Peripheral Bus Addresses (APB): 0xEE000000 - 0xEFFFFFFF (128MB)
78 */
79 #define PKUNITY_UART0_BASE 0xEE000000 /* APB-0 */
80 #define PKUNITY_UART1_BASE 0xEE100000 /* APB-1 */
81 #include "regs-uart.h"
82 #define PKUNITY_I2C_BASE 0xEE200000 /* APB-2 */
83 #include "regs-i2c.h"
84 #define PKUNITY_SPI_BASE 0xEE300000 /* APB-3 */
85 #include "regs-spi.h"
86 #define PKUNITY_AC97_BASE 0xEE400000 /* APB-4 */
87 #include "regs-ac97.h"
88 #define PKUNITY_GPIO_BASE 0xEE500000 /* APB-5 */
89 #include "regs-gpio.h"
90 #define PKUNITY_INTC_BASE 0xEE600000 /* APB-6 */
91 #include "regs-intc.h"
92 #define PKUNITY_RTC_BASE 0xEE700000 /* APB-7 */
93 #include "regs-rtc.h"
94 #define PKUNITY_OST_BASE 0xEE800000 /* APB-8 */
95 #include "regs-ost.h"
96 #define PKUNITY_RESETC_BASE 0xEE900000 /* APB-9 */
97 #include "regs-resetc.h"
98 #define PKUNITY_PM_BASE 0xEEA00000 /* APB-10 */
99 #include "regs-pm.h"
100 #define PKUNITY_PS2_BASE 0xEEB00000 /* APB-11 */
101 #include "regs-ps2.h"
102 #define PKUNITY_SDC_BASE 0xEEC00000 /* APB-12 */
103 #include "regs-sdc.h"
104
105
arch/unicore32/include/mach/bitfield.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * linux/arch/unicore32/include/mach/bitfield.h
3 *
4 * Code specific to PKUnity SoC and UniCore ISA
5 *
6 * Copyright (C) 2001-2010 GUAN Xue-tao
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12 #ifndef __MACH_PUV3_BITFIELD_H__
13 #define __MACH_PUV3_BITFIELD_H__
14
15 #ifndef __ASSEMBLY__
16 #define UData(Data) ((unsigned long) (Data))
17 #else
18 #define UData(Data) (Data)
19 #endif
20
21 #define FIELD(val, vmask, vshift) (((val) & ((UData(1) << (vmask)) - 1)) << (vshift))
22 #define FMASK(vmask, vshift) (((UData(1) << (vmask)) - 1) << (vshift))
23
24 #endif /* __MACH_PUV3_BITFIELD_H__ */
25
arch/unicore32/include/mach/hardware.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * linux/arch/unicore32/include/mach/hardware.h
3 *
4 * Code specific to PKUnity SoC and UniCore ISA
5 *
6 * Copyright (C) 2001-2010 GUAN Xue-tao
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This file contains the hardware definitions for PKUnity architecture
13 */
14
15 #ifndef __MACH_PUV3_HARDWARE_H__
16 #define __MACH_PUV3_HARDWARE_H__
17
18 #include "PKUnity.h"
19
20 #define io_p2v(x) ((x) - PKUNITY_IOSPACE_BASE)
21 #define io_v2p(x) ((x) + PKUNITY_IOSPACE_BASE)
22
23 #ifndef __ASSEMBLY__
24
25 # define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
26 # define __PREG(x) (io_v2p((unsigned long)&(x)))
27
28 #else
29
30 # define __REG(x) io_p2v(x)
31 # define __PREG(x) io_v2p(x)
32
33 #endif
34
35 #define PCIBIOS_MIN_IO 0x4000 /* should lower than 64KB */
36 #define PCIBIOS_MIN_MEM PKUNITY_PCIMEM_BASE
37
38 /*
39 * We override the standard dma-mask routines for bouncing.
40 */
41 #define HAVE_ARCH_PCI_SET_DMA_MASK
42
43 #define pcibios_assign_all_busses() 1
44
45 #endif /* __MACH_PUV3_HARDWARE_H__ */
46
arch/unicore32/include/mach/regs-ac97.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity AC97 Registers
3 */
4
5 #define PKUNITY_AC97_CONR __REG(PKUNITY_AC97_BASE + 0x0000)
6 #define PKUNITY_AC97_OCR __REG(PKUNITY_AC97_BASE + 0x0004)
7 #define PKUNITY_AC97_ICR __REG(PKUNITY_AC97_BASE + 0x0008)
8 #define PKUNITY_AC97_CRAC __REG(PKUNITY_AC97_BASE + 0x000C)
9 #define PKUNITY_AC97_INTR __REG(PKUNITY_AC97_BASE + 0x0010)
10 #define PKUNITY_AC97_INTRSTAT __REG(PKUNITY_AC97_BASE + 0x0014)
11 #define PKUNITY_AC97_INTRCLEAR __REG(PKUNITY_AC97_BASE + 0x0018)
12 #define PKUNITY_AC97_ENABLE __REG(PKUNITY_AC97_BASE + 0x001C)
13 #define PKUNITY_AC97_OUT_FIFO __REG(PKUNITY_AC97_BASE + 0x0020)
14 #define PKUNITY_AC97_IN_FIFO __REG(PKUNITY_AC97_BASE + 0x0030)
15
16 #define AC97_CODEC_REG(v) FIELD((v), 7, 16)
17 #define AC97_CODEC_VAL(v) FIELD((v), 16, 0)
18 #define AC97_CODEC_WRITECOMPLETE FIELD(1, 1, 2)
19
20 /*
21 * VAR PLAY SAMPLE RATE
22 */
23 #define AC97_CMD_VPSAMPLE (FIELD(3, 2, 16) | FIELD(3, 2, 0))
24
25 /*
26 * FIX CAPTURE SAMPLE RATE
27 */
28 #define AC97_CMD_FCSAMPLE FIELD(7, 3, 0)
29
30 #define AC97_CMD_RESET FIELD(1, 1, 0)
31 #define AC97_CMD_ENABLE FIELD(1, 1, 0)
32 #define AC97_CMD_DISABLE FIELD(0, 1, 0)
33
arch/unicore32/include/mach/regs-dmac.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity Direct Memory Access Controller (DMAC)
3 */
4
5 /*
6 * Interrupt Status Reg DMAC_ISR.
7 */
8 #define DMAC_ISR __REG(PKUNITY_DMAC_BASE + 0x0020)
9 /*
10 * Interrupt Transfer Complete Status Reg DMAC_ITCSR.
11 */
12 #define DMAC_ITCSR __REG(PKUNITY_DMAC_BASE + 0x0050)
13 /*
14 * Interrupt Transfer Complete Clear Reg DMAC_ITCCR.
15 */
16 #define DMAC_ITCCR __REG(PKUNITY_DMAC_BASE + 0x0060)
17 /*
18 * Interrupt Error Status Reg DMAC_IESR.
19 */
20 #define DMAC_IESR __REG(PKUNITY_DMAC_BASE + 0x0080)
21 /*
22 * Interrupt Error Clear Reg DMAC_IECR.
23 */
24 #define DMAC_IECR __REG(PKUNITY_DMAC_BASE + 0x0090)
25 /*
26 * Enable Channels Reg DMAC_ENCH.
27 */
28 #define DMAC_ENCH __REG(PKUNITY_DMAC_BASE + 0x00B0)
29
30 /*
31 * DMA control reg. Space [byte]
32 */
33 #define DMASp 0x00000100
34
35 /*
36 * Source Addr DMAC_SRCADDR(ch).
37 */
38 #define DMAC_SRCADDR(ch) __REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00)
39 /*
40 * Destination Addr DMAC_DESTADDR(ch).
41 */
42 #define DMAC_DESTADDR(ch) __REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04)
43 /*
44 * Control Reg DMAC_CONTROL(ch).
45 */
46 #define DMAC_CONTROL(ch) __REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C)
47 /*
48 * Configuration Reg DMAC_CONFIG(ch).
49 */
50 #define DMAC_CONFIG(ch) __REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10)
51
52 #define DMAC_IR_MASK FMASK(6, 0)
53 /*
54 * select channel (ch)
55 */
56 #define DMAC_CHANNEL(ch) FIELD(1, 1, (ch))
57
58 #define DMAC_CONTROL_SIZE_BYTE(v) (FIELD((v), 12, 14) | \
59 FIELD(0, 3, 9) | FIELD(0, 3, 6))
60 #define DMAC_CONTROL_SIZE_HWORD(v) (FIELD((v) >> 1, 12, 14) | \
61 FIELD(1, 3, 9) | FIELD(1, 3, 6))
62 #define DMAC_CONTROL_SIZE_WORD(v) (FIELD((v) >> 2, 12, 14) | \
63 FIELD(2, 3, 9) | FIELD(2, 3, 6))
64 #define DMAC_CONTROL_DI FIELD(1, 1, 13)
65 #define DMAC_CONTROL_SI FIELD(1, 1, 12)
66 #define DMAC_CONTROL_BURST_1BYTE (FIELD(0, 3, 3) | FIELD(0, 3, 0))
67 #define DMAC_CONTROL_BURST_4BYTE (FIELD(3, 3, 3) | FIELD(3, 3, 0))
68 #define DMAC_CONTROL_BURST_8BYTE (FIELD(5, 3, 3) | FIELD(5, 3, 0))
69 #define DMAC_CONTROL_BURST_16BYTE (FIELD(7, 3, 3) | FIELD(7, 3, 0))
70
71 #define DMAC_CONFIG_UART0_WR (FIELD(2, 4, 11) | FIELD(1, 2, 1))
72 #define DMAC_CONFIG_UART0_RD (FIELD(2, 4, 7) | FIELD(2, 2, 1))
73 #define DMAC_CONFIG_UART1_WR (FIELD(3, 4, 11) | FIELD(1, 2, 1))
74 #define DMAC_CONFIG_UART1RD (FIELD(3, 4, 7) | FIELD(2, 2, 1))
75 #define DMAC_CONFIG_AC97WR (FIELD(4, 4, 11) | FIELD(1, 2, 1))
76 #define DMAC_CONFIG_AC97RD (FIELD(4, 4, 7) | FIELD(2, 2, 1))
77 #define DMAC_CONFIG_MMCWR (FIELD(7, 4, 11) | FIELD(1, 2, 1))
78 #define DMAC_CONFIG_MMCRD (FIELD(7, 4, 7) | FIELD(2, 2, 1))
79 #define DMAC_CONFIG_MASKITC FIELD(1, 1, 4)
80 #define DMAC_CONFIG_MASKIE FIELD(1, 1, 3)
81 #define DMAC_CONFIG_EN FIELD(1, 1, 0)
82
arch/unicore32/include/mach/regs-gpio.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity General-Purpose Input/Output (GPIO) Registers
3 */
4
5 /*
6 * Voltage Status Reg GPIO_GPLR.
7 */
8 #define GPIO_GPLR __REG(PKUNITY_GPIO_BASE + 0x0000)
9 /*
10 * Pin Direction Reg GPIO_GPDR.
11 */
12 #define GPIO_GPDR __REG(PKUNITY_GPIO_BASE + 0x0004)
13 /*
14 * Output Pin Set Reg GPIO_GPSR.
15 */
16 #define GPIO_GPSR __REG(PKUNITY_GPIO_BASE + 0x0008)
17 /*
18 * Output Pin Clear Reg GPIO_GPCR.
19 */
20 #define GPIO_GPCR __REG(PKUNITY_GPIO_BASE + 0x000C)
21 /*
22 * Raise Edge Detect Reg GPIO_GRER.
23 */
24 #define GPIO_GRER __REG(PKUNITY_GPIO_BASE + 0x0010)
25 /*
26 * Fall Edge Detect Reg GPIO_GFER.
27 */
28 #define GPIO_GFER __REG(PKUNITY_GPIO_BASE + 0x0014)
29 /*
30 * Edge Status Reg GPIO_GEDR.
31 */
32 #define GPIO_GEDR __REG(PKUNITY_GPIO_BASE + 0x0018)
33 /*
34 * Sepcial Voltage Detect Reg GPIO_GPIR.
35 */
36 #define GPIO_GPIR __REG(PKUNITY_GPIO_BASE + 0x0020)
37
38 #define GPIO_MIN (0)
39 #define GPIO_MAX (27)
40
41 #define GPIO_GPIO(Nb) (0x00000001 << (Nb)) /* GPIO [0..27] */
42 #define GPIO_GPIO0 GPIO_GPIO(0) /* GPIO [0] */
43 #define GPIO_GPIO1 GPIO_GPIO(1) /* GPIO [1] */
44 #define GPIO_GPIO2 GPIO_GPIO(2) /* GPIO [2] */
45 #define GPIO_GPIO3 GPIO_GPIO(3) /* GPIO [3] */
46 #define GPIO_GPIO4 GPIO_GPIO(4) /* GPIO [4] */
47 #define GPIO_GPIO5 GPIO_GPIO(5) /* GPIO [5] */
48 #define GPIO_GPIO6 GPIO_GPIO(6) /* GPIO [6] */
49 #define GPIO_GPIO7 GPIO_GPIO(7) /* GPIO [7] */
50 #define GPIO_GPIO8 GPIO_GPIO(8) /* GPIO [8] */
51 #define GPIO_GPIO9 GPIO_GPIO(9) /* GPIO [9] */
52 #define GPIO_GPIO10 GPIO_GPIO(10) /* GPIO [10] */
53 #define GPIO_GPIO11 GPIO_GPIO(11) /* GPIO [11] */
54 #define GPIO_GPIO12 GPIO_GPIO(12) /* GPIO [12] */
55 #define GPIO_GPIO13 GPIO_GPIO(13) /* GPIO [13] */
56 #define GPIO_GPIO14 GPIO_GPIO(14) /* GPIO [14] */
57 #define GPIO_GPIO15 GPIO_GPIO(15) /* GPIO [15] */
58 #define GPIO_GPIO16 GPIO_GPIO(16) /* GPIO [16] */
59 #define GPIO_GPIO17 GPIO_GPIO(17) /* GPIO [17] */
60 #define GPIO_GPIO18 GPIO_GPIO(18) /* GPIO [18] */
61 #define GPIO_GPIO19 GPIO_GPIO(19) /* GPIO [19] */
62 #define GPIO_GPIO20 GPIO_GPIO(20) /* GPIO [20] */
63 #define GPIO_GPIO21 GPIO_GPIO(21) /* GPIO [21] */
64 #define GPIO_GPIO22 GPIO_GPIO(22) /* GPIO [22] */
65 #define GPIO_GPIO23 GPIO_GPIO(23) /* GPIO [23] */
66 #define GPIO_GPIO24 GPIO_GPIO(24) /* GPIO [24] */
67 #define GPIO_GPIO25 GPIO_GPIO(25) /* GPIO [25] */
68 #define GPIO_GPIO26 GPIO_GPIO(26) /* GPIO [26] */
69 #define GPIO_GPIO27 GPIO_GPIO(27) /* GPIO [27] */
70
71
arch/unicore32/include/mach/regs-i2c.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity Inter-integrated Circuit (I2C) Registers
3 */
4
5 /*
6 * Control Reg I2C_CON.
7 */
8 #define I2C_CON __REG(PKUNITY_I2C_BASE + 0x0000)
9 /*
10 * Target Address Reg I2C_TAR.
11 */
12 #define I2C_TAR __REG(PKUNITY_I2C_BASE + 0x0004)
13 /*
14 * Data buffer and command Reg I2C_DATACMD.
15 */
16 #define I2C_DATACMD __REG(PKUNITY_I2C_BASE + 0x0010)
17 /*
18 * Enable Reg I2C_ENABLE.
19 */
20 #define I2C_ENABLE __REG(PKUNITY_I2C_BASE + 0x006C)
21 /*
22 * Status Reg I2C_STATUS.
23 */
24 #define I2C_STATUS __REG(PKUNITY_I2C_BASE + 0x0070)
25 /*
26 * Tx FIFO Length Reg I2C_TXFLR.
27 */
28 #define I2C_TXFLR __REG(PKUNITY_I2C_BASE + 0x0074)
29 /*
30 * Rx FIFO Length Reg I2C_RXFLR.
31 */
32 #define I2C_RXFLR __REG(PKUNITY_I2C_BASE + 0x0078)
33 /*
34 * Enable Status Reg I2C_ENSTATUS.
35 */
36 #define I2C_ENSTATUS __REG(PKUNITY_I2C_BASE + 0x009C)
37
38 #define I2C_CON_MASTER FIELD(1, 1, 0)
39 #define I2C_CON_SPEED_STD FIELD(1, 2, 1)
40 #define I2C_CON_SPEED_FAST FIELD(2, 2, 1)
41 #define I2C_CON_RESTART FIELD(1, 1, 5)
42 #define I2C_CON_SLAVEDISABLE FIELD(1, 1, 6)
43
44 #define I2C_DATACMD_READ FIELD(1, 1, 8)
45 #define I2C_DATACMD_WRITE FIELD(0, 1, 8)
46 #define I2C_DATACMD_DAT_MASK FMASK(8, 0)
47 #define I2C_DATACMD_DAT(v) FIELD((v), 8, 0)
48
49 #define I2C_ENABLE_ENABLE FIELD(1, 1, 0)
50 #define I2C_ENABLE_DISABLE FIELD(0, 1, 0)
51
52 #define I2C_STATUS_RFF FIELD(1, 1, 4)
53 #define I2C_STATUS_RFNE FIELD(1, 1, 3)
54 #define I2C_STATUS_TFE FIELD(1, 1, 2)
55 #define I2C_STATUS_TFNF FIELD(1, 1, 1)
56 #define I2C_STATUS_ACTIVITY FIELD(1, 1, 0)
57
58 #define I2C_ENSTATUS_ENABLE FIELD(1, 1, 0)
59
60 #define I2C_TAR_THERMAL 0x4f
61 #define I2C_TAR_SPD 0x50
62 #define I2C_TAR_PWIC 0x55
63 #define I2C_TAR_EEPROM 0x57
64
arch/unicore32/include/mach/regs-intc.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUNITY Interrupt Controller (INTC) Registers
3 */
4 /*
5 * INTC Level Reg INTC_ICLR.
6 */
7 #define INTC_ICLR __REG(PKUNITY_INTC_BASE + 0x0000)
8 /*
9 * INTC Mask Reg INTC_ICMR.
10 */
11 #define INTC_ICMR __REG(PKUNITY_INTC_BASE + 0x0004)
12 /*
13 * INTC Pending Reg INTC_ICPR.
14 */
15 #define INTC_ICPR __REG(PKUNITY_INTC_BASE + 0x0008)
16 /*
17 * INTC IRQ Pending Reg INTC_ICIP.
18 */
19 #define INTC_ICIP __REG(PKUNITY_INTC_BASE + 0x000C)
20 /*
21 * INTC REAL Pending Reg INTC_ICFP.
22 */
23 #define INTC_ICFP __REG(PKUNITY_INTC_BASE + 0x0010)
24 /*
25 * INTC Control Reg INTC_ICCR.
26 */
27 #define INTC_ICCR __REG(PKUNITY_INTC_BASE + 0x0014)
28
29
arch/unicore32/include/mach/regs-nand.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity NAND Controller Registers
3 */
4 /*
5 * ID Reg. 0 NAND_IDR0
6 */
7 #define NAND_IDR0 __REG(PKUNITY_NAND_BASE + 0x0000)
8 /*
9 * ID Reg. 1 NAND_IDR1
10 */
11 #define NAND_IDR1 __REG(PKUNITY_NAND_BASE + 0x0004)
12 /*
13 * ID Reg. 2 NAND_IDR2
14 */
15 #define NAND_IDR2 __REG(PKUNITY_NAND_BASE + 0x0008)
16 /*
17 * ID Reg. 3 NAND_IDR3
18 */
19 #define NAND_IDR3 __REG(PKUNITY_NAND_BASE + 0x000C)
20 /*
21 * Page Address Reg 0 NAND_PAR0
22 */
23 #define NAND_PAR0 __REG(PKUNITY_NAND_BASE + 0x0010)
24 /*
25 * Page Address Reg 1 NAND_PAR1
26 */
27 #define NAND_PAR1 __REG(PKUNITY_NAND_BASE + 0x0014)
28 /*
29 * Page Address Reg 2 NAND_PAR2
30 */
31 #define NAND_PAR2 __REG(PKUNITY_NAND_BASE + 0x0018)
32 /*
33 * ECC Enable Reg NAND_ECCEN
34 */
35 #define NAND_ECCEN __REG(PKUNITY_NAND_BASE + 0x001C)
36 /*
37 * Buffer Reg NAND_BUF
38 */
39 #define NAND_BUF __REG(PKUNITY_NAND_BASE + 0x0020)
40 /*
41 * ECC Status Reg NAND_ECCSR
42 */
43 #define NAND_ECCSR __REG(PKUNITY_NAND_BASE + 0x0024)
44 /*
45 * Command Reg NAND_CMD
46 */
47 #define NAND_CMD __REG(PKUNITY_NAND_BASE + 0x0028)
48 /*
49 * DMA Configure Reg NAND_DMACR
50 */
51 #define NAND_DMACR __REG(PKUNITY_NAND_BASE + 0x002C)
52 /*
53 * Interrupt Reg NAND_IR
54 */
55 #define NAND_IR __REG(PKUNITY_NAND_BASE + 0x0030)
56 /*
57 * Interrupt Mask Reg NAND_IMR
58 */
59 #define NAND_IMR __REG(PKUNITY_NAND_BASE + 0x0034)
60 /*
61 * Chip Enable Reg NAND_CHIPEN
62 */
63 #define NAND_CHIPEN __REG(PKUNITY_NAND_BASE + 0x0038)
64 /*
65 * Address Reg NAND_ADDR
66 */
67 #define NAND_ADDR __REG(PKUNITY_NAND_BASE + 0x003C)
68
69 /*
70 * Command bits NAND_CMD_CMD_MASK
71 */
72 #define NAND_CMD_CMD_MASK FMASK(4, 4)
73 #define NAND_CMD_CMD_READPAGE FIELD(0x0, 4, 4)
74 #define NAND_CMD_CMD_ERASEBLOCK FIELD(0x6, 4, 4)
75 #define NAND_CMD_CMD_READSTATUS FIELD(0x7, 4, 4)
76 #define NAND_CMD_CMD_WRITEPAGE FIELD(0x8, 4, 4)
77 #define NAND_CMD_CMD_READID FIELD(0x9, 4, 4)
78 #define NAND_CMD_CMD_RESET FIELD(0xf, 4, 4)
79
80
arch/unicore32/include/mach/regs-ost.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity Operating System Timer (OST) Registers
3 */
4 /*
5 * Match Reg 0 OST_OSMR0
6 */
7 #define OST_OSMR0 __REG(PKUNITY_OST_BASE + 0x0000)
8 /*
9 * Match Reg 1 OST_OSMR1
10 */
11 #define OST_OSMR1 __REG(PKUNITY_OST_BASE + 0x0004)
12 /*
13 * Match Reg 2 OST_OSMR2
14 */
15 #define OST_OSMR2 __REG(PKUNITY_OST_BASE + 0x0008)
16 /*
17 * Match Reg 3 OST_OSMR3
18 */
19 #define OST_OSMR3 __REG(PKUNITY_OST_BASE + 0x000C)
20 /*
21 * Counter Reg OST_OSCR
22 */
23 #define OST_OSCR __REG(PKUNITY_OST_BASE + 0x0010)
24 /*
25 * Status Reg OST_OSSR
26 */
27 #define OST_OSSR __REG(PKUNITY_OST_BASE + 0x0014)
28 /*
29 * Watchdog Enable Reg OST_OWER
30 */
31 #define OST_OWER __REG(PKUNITY_OST_BASE + 0x0018)
32 /*
33 * Interrupt Enable Reg OST_OIER
34 */
35 #define OST_OIER __REG(PKUNITY_OST_BASE + 0x001C)
36 /*
37 * PWM Pulse Width Control Reg OST_PWMPWCR
38 */
39 #define OST_PWMPWCR __REG(PKUNITY_OST_BASE + 0x0080)
40 /*
41 * PWM Duty Cycle Control Reg OST_PWMDCCR
42 */
43 #define OST_PWMDCCR __REG(PKUNITY_OST_BASE + 0x0084)
44 /*
45 * PWM Period Control Reg OST_PWMPCR
46 */
47 #define OST_PWMPCR __REG(PKUNITY_OST_BASE + 0x0088)
48
49 /*
50 * Match detected 0 OST_OSSR_M0
51 */
52 #define OST_OSSR_M0 FIELD(1, 1, 0)
53 /*
54 * Match detected 1 OST_OSSR_M1
55 */
56 #define OST_OSSR_M1 FIELD(1, 1, 1)
57 /*
58 * Match detected 2 OST_OSSR_M2
59 */
60 #define OST_OSSR_M2 FIELD(1, 1, 2)
61 /*
62 * Match detected 3 OST_OSSR_M3
63 */
64 #define OST_OSSR_M3 FIELD(1, 1, 3)
65
66 /*
67 * Interrupt enable 0 OST_OIER_E0
68 */
69 #define OST_OIER_E0 FIELD(1, 1, 0)
70 /*
71 * Interrupt enable 1 OST_OIER_E1
72 */
73 #define OST_OIER_E1 FIELD(1, 1, 1)
74 /*
75 * Interrupt enable 2 OST_OIER_E2
76 */
77 #define OST_OIER_E2 FIELD(1, 1, 2)
78 /*
79 * Interrupt enable 3 OST_OIER_E3
80 */
81 #define OST_OIER_E3 FIELD(1, 1, 3)
82
83 /*
84 * Watchdog Match Enable OST_OWER_WME
85 */
86 #define OST_OWER_WME FIELD(1, 1, 0)
87
88 /*
89 * PWM Full Duty Cycle OST_PWMDCCR_FDCYCLE
90 */
91 #define OST_PWMDCCR_FDCYCLE FIELD(1, 1, 10)
92
93
arch/unicore32/include/mach/regs-pci.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity AHB-PCI Bridge Registers
3 */
4
5 /*
6 * AHB/PCI fixed physical address for pci addess configuration
7 */
8 /*
9 * PCICFG Bridge Base Reg.
10 */
11 #define PCICFG_BRIBASE __REG(PKUNITY_PCICFG_BASE + 0x0000)
12 /*
13 * PCICFG Address Reg.
14 */
15 #define PCICFG_ADDR __REG(PKUNITY_PCICFG_BASE + 0x0004)
16 /*
17 * PCICFG Address Reg.
18 */
19 #define PCICFG_DATA __REG(PKUNITY_PCICFG_BASE + 0x0008)
20
21 /*
22 * PCI Bridge configuration space
23 */
24 #define PCIBRI_ID __REG(PKUNITY_PCIBRI_BASE + 0x0000)
25 #define PCIBRI_CMD __REG(PKUNITY_PCIBRI_BASE + 0x0004)
26 #define PCIBRI_CLASS __REG(PKUNITY_PCIBRI_BASE + 0x0008)
27 #define PCIBRI_LTR __REG(PKUNITY_PCIBRI_BASE + 0x000C)
28 #define PCIBRI_BAR0 __REG(PKUNITY_PCIBRI_BASE + 0x0010)
29 #define PCIBRI_BAR1 __REG(PKUNITY_PCIBRI_BASE + 0x0014)
30 #define PCIBRI_BAR2 __REG(PKUNITY_PCIBRI_BASE + 0x0018)
31 #define PCIBRI_BAR3 __REG(PKUNITY_PCIBRI_BASE + 0x001C)
32 #define PCIBRI_BAR4 __REG(PKUNITY_PCIBRI_BASE + 0x0020)
33 #define PCIBRI_BAR5 __REG(PKUNITY_PCIBRI_BASE + 0x0024)
34
35 #define PCIBRI_PCICTL0 __REG(PKUNITY_PCIBRI_BASE + 0x0100)
36 #define PCIBRI_PCIBAR0 __REG(PKUNITY_PCIBRI_BASE + 0x0104)
37 #define PCIBRI_PCIAMR0 __REG(PKUNITY_PCIBRI_BASE + 0x0108)
38 #define PCIBRI_PCITAR0 __REG(PKUNITY_PCIBRI_BASE + 0x010C)
39 #define PCIBRI_PCICTL1 __REG(PKUNITY_PCIBRI_BASE + 0x0110)
40 #define PCIBRI_PCIBAR1 __REG(PKUNITY_PCIBRI_BASE + 0x0114)
41 #define PCIBRI_PCIAMR1 __REG(PKUNITY_PCIBRI_BASE + 0x0118)
42 #define PCIBRI_PCITAR1 __REG(PKUNITY_PCIBRI_BASE + 0x011C)
43 #define PCIBRI_PCICTL2 __REG(PKUNITY_PCIBRI_BASE + 0x0120)
44 #define PCIBRI_PCIBAR2 __REG(PKUNITY_PCIBRI_BASE + 0x0124)
45 #define PCIBRI_PCIAMR2 __REG(PKUNITY_PCIBRI_BASE + 0x0128)
46 #define PCIBRI_PCITAR2 __REG(PKUNITY_PCIBRI_BASE + 0x012C)
47 #define PCIBRI_PCICTL3 __REG(PKUNITY_PCIBRI_BASE + 0x0130)
48 #define PCIBRI_PCIBAR3 __REG(PKUNITY_PCIBRI_BASE + 0x0134)
49 #define PCIBRI_PCIAMR3 __REG(PKUNITY_PCIBRI_BASE + 0x0138)
50 #define PCIBRI_PCITAR3 __REG(PKUNITY_PCIBRI_BASE + 0x013C)
51 #define PCIBRI_PCICTL4 __REG(PKUNITY_PCIBRI_BASE + 0x0140)
52 #define PCIBRI_PCIBAR4 __REG(PKUNITY_PCIBRI_BASE + 0x0144)
53 #define PCIBRI_PCIAMR4 __REG(PKUNITY_PCIBRI_BASE + 0x0148)
54 #define PCIBRI_PCITAR4 __REG(PKUNITY_PCIBRI_BASE + 0x014C)
55 #define PCIBRI_PCICTL5 __REG(PKUNITY_PCIBRI_BASE + 0x0150)
56 #define PCIBRI_PCIBAR5 __REG(PKUNITY_PCIBRI_BASE + 0x0154)
57 #define PCIBRI_PCIAMR5 __REG(PKUNITY_PCIBRI_BASE + 0x0158)
58 #define PCIBRI_PCITAR5 __REG(PKUNITY_PCIBRI_BASE + 0x015C)
59
60 #define PCIBRI_AHBCTL0 __REG(PKUNITY_PCIBRI_BASE + 0x0180)
61 #define PCIBRI_AHBBAR0 __REG(PKUNITY_PCIBRI_BASE + 0x0184)
62 #define PCIBRI_AHBAMR0 __REG(PKUNITY_PCIBRI_BASE + 0x0188)
63 #define PCIBRI_AHBTAR0 __REG(PKUNITY_PCIBRI_BASE + 0x018C)
64 #define PCIBRI_AHBCTL1 __REG(PKUNITY_PCIBRI_BASE + 0x0190)
65 #define PCIBRI_AHBBAR1 __REG(PKUNITY_PCIBRI_BASE + 0x0194)
66 #define PCIBRI_AHBAMR1 __REG(PKUNITY_PCIBRI_BASE + 0x0198)
67 #define PCIBRI_AHBTAR1 __REG(PKUNITY_PCIBRI_BASE + 0x019C)
68 #define PCIBRI_AHBCTL2 __REG(PKUNITY_PCIBRI_BASE + 0x01A0)
69 #define PCIBRI_AHBBAR2 __REG(PKUNITY_PCIBRI_BASE + 0x01A4)
70 #define PCIBRI_AHBAMR2 __REG(PKUNITY_PCIBRI_BASE + 0x01A8)
71 #define PCIBRI_AHBTAR2 __REG(PKUNITY_PCIBRI_BASE + 0x01AC)
72 #define PCIBRI_AHBCTL3 __REG(PKUNITY_PCIBRI_BASE + 0x01B0)
73 #define PCIBRI_AHBBAR3 __REG(PKUNITY_PCIBRI_BASE + 0x01B4)
74 #define PCIBRI_AHBAMR3 __REG(PKUNITY_PCIBRI_BASE + 0x01B8)
75 #define PCIBRI_AHBTAR3 __REG(PKUNITY_PCIBRI_BASE + 0x01BC)
76 #define PCIBRI_AHBCTL4 __REG(PKUNITY_PCIBRI_BASE + 0x01C0)
77 #define PCIBRI_AHBBAR4 __REG(PKUNITY_PCIBRI_BASE + 0x01C4)
78 #define PCIBRI_AHBAMR4 __REG(PKUNITY_PCIBRI_BASE + 0x01C8)
79 #define PCIBRI_AHBTAR4 __REG(PKUNITY_PCIBRI_BASE + 0x01CC)
80 #define PCIBRI_AHBCTL5 __REG(PKUNITY_PCIBRI_BASE + 0x01D0)
81 #define PCIBRI_AHBBAR5 __REG(PKUNITY_PCIBRI_BASE + 0x01D4)
82 #define PCIBRI_AHBAMR5 __REG(PKUNITY_PCIBRI_BASE + 0x01D8)
83 #define PCIBRI_AHBTAR5 __REG(PKUNITY_PCIBRI_BASE + 0x01DC)
84
85 #define PCIBRI_CTLx_AT FIELD(1, 1, 2)
86 #define PCIBRI_CTLx_PREF FIELD(1, 1, 1)
87 #define PCIBRI_CTLx_MRL FIELD(1, 1, 0)
88
89 #define PCIBRI_BARx_ADDR FIELD(0xFFFFFFFC, 30, 2)
90 #define PCIBRI_BARx_IO FIELD(1, 1, 0)
91 #define PCIBRI_BARx_MEM FIELD(0, 1, 0)
92
93 #define PCIBRI_CMD_IO FIELD(1, 1, 0)
94 #define PCIBRI_CMD_MEM FIELD(1, 1, 1)
95
arch/unicore32/include/mach/regs-pm.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUNITY Power Manager (PM) Registers
3 */
4 /*
5 * PM Control Reg PM_PMCR
6 */
7 #define PM_PMCR __REG(PKUNITY_PM_BASE + 0x0000)
8 /*
9 * PM General Conf. Reg PM_PGCR
10 */
11 #define PM_PGCR __REG(PKUNITY_PM_BASE + 0x0004)
12 /*
13 * PM PLL Conf. Reg PM_PPCR
14 */
15 #define PM_PPCR __REG(PKUNITY_PM_BASE + 0x0008)
16 /*
17 * PM Wakeup Enable Reg PM_PWER
18 */
19 #define PM_PWER __REG(PKUNITY_PM_BASE + 0x000C)
20 /*
21 * PM GPIO Sleep Status Reg PM_PGSR
22 */
23 #define PM_PGSR __REG(PKUNITY_PM_BASE + 0x0010)
24 /*
25 * PM Clock Gate Reg PM_PCGR
26 */
27 #define PM_PCGR __REG(PKUNITY_PM_BASE + 0x0014)
28 /*
29 * PM SYS PLL Conf. Reg PM_PLLSYSCFG
30 */
31 #define PM_PLLSYSCFG __REG(PKUNITY_PM_BASE + 0x0018)
32 /*
33 * PM DDR PLL Conf. Reg PM_PLLDDRCFG
34 */
35 #define PM_PLLDDRCFG __REG(PKUNITY_PM_BASE + 0x001C)
36 /*
37 * PM VGA PLL Conf. Reg PM_PLLVGACFG
38 */
39 #define PM_PLLVGACFG __REG(PKUNITY_PM_BASE + 0x0020)
40 /*
41 * PM Div Conf. Reg PM_DIVCFG
42 */
43 #define PM_DIVCFG __REG(PKUNITY_PM_BASE + 0x0024)
44 /*
45 * PM SYS PLL Status Reg PM_PLLSYSSTATUS
46 */
47 #define PM_PLLSYSSTATUS __REG(PKUNITY_PM_BASE + 0x0028)
48 /*
49 * PM DDR PLL Status Reg PM_PLLDDRSTATUS
50 */
51 #define PM_PLLDDRSTATUS __REG(PKUNITY_PM_BASE + 0x002C)
52 /*
53 * PM VGA PLL Status Reg PM_PLLVGASTATUS
54 */
55 #define PM_PLLVGASTATUS __REG(PKUNITY_PM_BASE + 0x0030)
56 /*
57 * PM Div Status Reg PM_DIVSTATUS
58 */
59 #define PM_DIVSTATUS __REG(PKUNITY_PM_BASE + 0x0034)
60 /*
61 * PM Software Reset Reg PM_SWRESET
62 */
63 #define PM_SWRESET __REG(PKUNITY_PM_BASE + 0x0038)
64 /*
65 * PM DDR2 PAD Start Reg PM_DDR2START
66 */
67 #define PM_DDR2START __REG(PKUNITY_PM_BASE + 0x003C)
68 /*
69 * PM DDR2 PAD Status Reg PM_DDR2CAL0
70 */
71 #define PM_DDR2CAL0 __REG(PKUNITY_PM_BASE + 0x0040)
72 /*
73 * PM PLL DFC Done Reg PM_PLLDFCDONE
74 */
75 #define PM_PLLDFCDONE __REG(PKUNITY_PM_BASE + 0x0044)
76
77 #define PM_PMCR_SFB FIELD(1, 1, 0)
78 #define PM_PMCR_IFB FIELD(1, 1, 1)
79 #define PM_PMCR_CFBSYS FIELD(1, 1, 2)
80 #define PM_PMCR_CFBDDR FIELD(1, 1, 3)
81 #define PM_PMCR_CFBVGA FIELD(1, 1, 4)
82 #define PM_PMCR_CFBDIVBCLK FIELD(1, 1, 5)
83
84 /*
85 * GPIO 8~27 wake-up enable PM_PWER_GPIOHIGH
86 */
87 #define PM_PWER_GPIOHIGH FIELD(1, 1, 8)
88 /*
89 * RTC alarm wake-up enable PM_PWER_RTC
90 */
91 #define PM_PWER_RTC FIELD(1, 1, 31)
92
93 #define PM_PCGR_BCLK64DDR FIELD(1, 1, 0)
94 #define PM_PCGR_BCLK64VGA FIELD(1, 1, 1)
95 #define PM_PCGR_BCLKDDR FIELD(1, 1, 2)
96 #define PM_PCGR_BCLKPCI FIELD(1, 1, 4)
97 #define PM_PCGR_BCLKDMAC FIELD(1, 1, 5)
98 #define PM_PCGR_BCLKUMAL FIELD(1, 1, 6)
99 #define PM_PCGR_BCLKUSB FIELD(1, 1, 7)
100 #define PM_PCGR_BCLKMME FIELD(1, 1, 10)
101 #define PM_PCGR_BCLKNAND FIELD(1, 1, 11)
102 #define PM_PCGR_BCLKH264E FIELD(1, 1, 12)
103 #define PM_PCGR_BCLKVGA FIELD(1, 1, 13)
104 #define PM_PCGR_BCLKH264D FIELD(1, 1, 14)
105 #define PM_PCGR_VECLK FIELD(1, 1, 15)
106 #define PM_PCGR_HECLK FIELD(1, 1, 16)
107 #define PM_PCGR_HDCLK FIELD(1, 1, 17)
108 #define PM_PCGR_NANDCLK FIELD(1, 1, 18)
109 #define PM_PCGR_GECLK FIELD(1, 1, 19)
110 #define PM_PCGR_VGACLK FIELD(1, 1, 20)
111 #define PM_PCGR_PCICLK FIELD(1, 1, 21)
112 #define PM_PCGR_SATACLK FIELD(1, 1, 25)
113
114 /*
115 * [23:20]PM_DIVCFG_VGACLK(v)
116 */
117 #define PM_DIVCFG_VGACLK_MASK FMASK(4, 20)
118 #define PM_DIVCFG_VGACLK(v) FIELD((v), 4, 20)
119
120 #define PM_SWRESET_USB FIELD(1, 1, 6)
121 #define PM_SWRESET_VGADIV FIELD(1, 1, 26)
122 #define PM_SWRESET_GEDIV FIELD(1, 1, 27)
123
124 #define PM_PLLDFCDONE_SYSDFC FIELD(1, 1, 0)
125 #define PM_PLLDFCDONE_DDRDFC FIELD(1, 1, 1)
126 #define PM_PLLDFCDONE_VGADFC FIELD(1, 1, 2)
127
arch/unicore32/include/mach/regs-ps2.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity PS2 Controller Registers
3 */
4 /*
5 * the same as I8042_DATA_REG PS2_DATA
6 */
7 #define PS2_DATA __REG(PKUNITY_PS2_BASE + 0x0060)
8 /*
9 * the same as I8042_COMMAND_REG PS2_COMMAND
10 */
11 #define PS2_COMMAND __REG(PKUNITY_PS2_BASE + 0x0064)
12 /*
13 * the same as I8042_STATUS_REG PS2_STATUS
14 */
15 #define PS2_STATUS __REG(PKUNITY_PS2_BASE + 0x0064)
16 /*
17 * counter reg PS2_CNT
18 */
19 #define PS2_CNT __REG(PKUNITY_PS2_BASE + 0x0068)
20
21
arch/unicore32/include/mach/regs-resetc.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity Reset Controller (RC) Registers
3 */
4 /*
5 * Software Reset Register
6 */
7 #define RESETC_SWRR __REG(PKUNITY_RESETC_BASE + 0x0000)
8 /*
9 * Reset Status Register
10 */
11 #define RESETC_RSSR __REG(PKUNITY_RESETC_BASE + 0x0004)
12
13 /*
14 * Software Reset Bit
15 */
16 #define RESETC_SWRR_SRB FIELD(1, 1, 0)
17
18 /*
19 * Hardware Reset
20 */
21 #define RESETC_RSSR_HWR FIELD(1, 1, 0)
22 /*
23 * Software Reset
24 */
25 #define RESETC_RSSR_SWR FIELD(1, 1, 1)
26 /*
27 * Watchdog Reset
28 */
29 #define RESETC_RSSR_WDR FIELD(1, 1, 2)
30 /*
31 * Sleep Mode Reset
32 */
33 #define RESETC_RSSR_SMR FIELD(1, 1, 3)
34
35
arch/unicore32/include/mach/regs-rtc.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity Real-Time Clock (RTC) control registers
3 */
4 /*
5 * RTC Alarm Reg RTC_RTAR
6 */
7 #define RTC_RTAR __REG(PKUNITY_RTC_BASE + 0x0000)
8 /*
9 * RTC Count Reg RTC_RCNR
10 */
11 #define RTC_RCNR __REG(PKUNITY_RTC_BASE + 0x0004)
12 /*
13 * RTC Trim Reg RTC_RTTR
14 */
15 #define RTC_RTTR __REG(PKUNITY_RTC_BASE + 0x0008)
16 /*
17 * RTC Status Reg RTC_RTSR
18 */
19 #define RTC_RTSR __REG(PKUNITY_RTC_BASE + 0x0010)
20
21 /*
22 * ALarm detected RTC_RTSR_AL
23 */
24 #define RTC_RTSR_AL FIELD(1, 1, 0)
25 /*
26 * 1 Hz clock detected RTC_RTSR_HZ
27 */
28 #define RTC_RTSR_HZ FIELD(1, 1, 1)
29 /*
30 * ALarm interrupt Enable RTC_RTSR_ALE
31 */
32 #define RTC_RTSR_ALE FIELD(1, 1, 2)
33 /*
34 * 1 Hz clock interrupt Enable RTC_RTSR_HZE
35 */
36 #define RTC_RTSR_HZE FIELD(1, 1, 3)
37
38
arch/unicore32/include/mach/regs-sdc.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity Multi-Media Card and Security Digital Card (MMC/SD) Registers
3 */
4 /*
5 * Clock Control Reg SDC_CCR
6 */
7 #define SDC_CCR __REG(PKUNITY_SDC_BASE + 0x0000)
8 /*
9 * Software Reset Reg SDC_SRR
10 */
11 #define SDC_SRR __REG(PKUNITY_SDC_BASE + 0x0004)
12 /*
13 * Argument Reg SDC_ARGUMENT
14 */
15 #define SDC_ARGUMENT __REG(PKUNITY_SDC_BASE + 0x0008)
16 /*
17 * Command Reg SDC_COMMAND
18 */
19 #define SDC_COMMAND __REG(PKUNITY_SDC_BASE + 0x000C)
20 /*
21 * Block Size Reg SDC_BLOCKSIZE
22 */
23 #define SDC_BLOCKSIZE __REG(PKUNITY_SDC_BASE + 0x0010)
24 /*
25 * Block Cound Reg SDC_BLOCKCOUNT
26 */
27 #define SDC_BLOCKCOUNT __REG(PKUNITY_SDC_BASE + 0x0014)
28 /*
29 * Transfer Mode Reg SDC_TMR
30 */
31 #define SDC_TMR __REG(PKUNITY_SDC_BASE + 0x0018)
32 /*
33 * Response Reg. 0 SDC_RES0
34 */
35 #define SDC_RES0 __REG(PKUNITY_SDC_BASE + 0x001C)
36 /*
37 * Response Reg. 1 SDC_RES1
38 */
39 #define SDC_RES1 __REG(PKUNITY_SDC_BASE + 0x0020)
40 /*
41 * Response Reg. 2 SDC_RES2
42 */
43 #define SDC_RES2 __REG(PKUNITY_SDC_BASE + 0x0024)
44 /*
45 * Response Reg. 3 SDC_RES3
46 */
47 #define SDC_RES3 __REG(PKUNITY_SDC_BASE + 0x0028)
48 /*
49 * Read Timeout Control Reg SDC_RTCR
50 */
51 #define SDC_RTCR __REG(PKUNITY_SDC_BASE + 0x002C)
52 /*
53 * Interrupt Status Reg SDC_ISR
54 */
55 #define SDC_ISR __REG(PKUNITY_SDC_BASE + 0x0030)
56 /*
57 * Interrupt Status Mask Reg SDC_ISMR
58 */
59 #define SDC_ISMR __REG(PKUNITY_SDC_BASE + 0x0034)
60 /*
61 * RX FIFO SDC_RXFIFO
62 */
63 #define SDC_RXFIFO __REG(PKUNITY_SDC_BASE + 0x0038)
64 /*
65 * TX FIFO SDC_TXFIFO
66 */
67 #define SDC_TXFIFO __REG(PKUNITY_SDC_BASE + 0x003C)
68
69 /*
70 * SD Clock Enable SDC_CCR_CLKEN
71 */
72 #define SDC_CCR_CLKEN FIELD(1, 1, 2)
73 /*
74 * [15:8] SDC_CCR_PDIV(v)
75 */
76 #define SDC_CCR_PDIV(v) FIELD((v), 8, 8)
77
78 /*
79 * Software reset enable SDC_SRR_ENABLE
80 */
81 #define SDC_SRR_ENABLE FIELD(0, 1, 0)
82 /*
83 * Software reset disable SDC_SRR_DISABLE
84 */
85 #define SDC_SRR_DISABLE FIELD(1, 1, 0)
86
87 /*
88 * Response type SDC_COMMAND_RESTYPE_MASK
89 */
90 #define SDC_COMMAND_RESTYPE_MASK FMASK(2, 0)
91 /*
92 * No response SDC_COMMAND_RESTYPE_NONE
93 */
94 #define SDC_COMMAND_RESTYPE_NONE FIELD(0, 2, 0)
95 /*
96 * 136-bit long response SDC_COMMAND_RESTYPE_LONG
97 */
98 #define SDC_COMMAND_RESTYPE_LONG FIELD(1, 2, 0)
99 /*
100 * 48-bit short response SDC_COMMAND_RESTYPE_SHORT
101 */
102 #define SDC_COMMAND_RESTYPE_SHORT FIELD(2, 2, 0)
103 /*
104 * 48-bit short and test if busy response SDC_COMMAND_RESTYPE_SHORTBUSY
105 */
106 #define SDC_COMMAND_RESTYPE_SHORTBUSY FIELD(3, 2, 0)
107 /*
108 * data ready SDC_COMMAND_DATAREADY
109 */
110 #define SDC_COMMAND_DATAREADY FIELD(1, 1, 2)
111 #define SDC_COMMAND_CMDEN FIELD(1, 1, 3)
112 /*
113 * [10:5] SDC_COMMAND_CMDINDEX(v)
114 */
115 #define SDC_COMMAND_CMDINDEX(v) FIELD((v), 6, 5)
116
117 /*
118 * [10:0] SDC_BLOCKSIZE_BSMASK(v)
119 */
120 #define SDC_BLOCKSIZE_BSMASK(v) FIELD((v), 11, 0)
121 /*
122 * [11:0] SDC_BLOCKCOUNT_BCMASK(v)
123 */
124 #define SDC_BLOCKCOUNT_BCMASK(v) FIELD((v), 12, 0)
125
126 /*
127 * Data Width 1bit SDC_TMR_WTH_1BIT
128 */
129 #define SDC_TMR_WTH_1BIT FIELD(0, 1, 0)
130 /*
131 * Data Width 4bit SDC_TMR_WTH_4BIT
132 */
133 #define SDC_TMR_WTH_4BIT FIELD(1, 1, 0)
134 /*
135 * Read SDC_TMR_DIR_READ
136 */
137 #define SDC_TMR_DIR_READ FIELD(0, 1, 1)
138 /*
139 * Write SDC_TMR_DIR_WRITE
140 */
141 #define SDC_TMR_DIR_WRITE FIELD(1, 1, 1)
142
143 #define SDC_IR_MASK FMASK(13, 0)
144 #define SDC_IR_RESTIMEOUT FIELD(1, 1, 0)
145 #define SDC_IR_WRITECRC FIELD(1, 1, 1)
146 #define SDC_IR_READCRC FIELD(1, 1, 2)
147 #define SDC_IR_TXFIFOREAD FIELD(1, 1, 3)
148 #define SDC_IR_RXFIFOWRITE FIELD(1, 1, 4)
149 #define SDC_IR_READTIMEOUT FIELD(1, 1, 5)
150 #define SDC_IR_DATACOMPLETE FIELD(1, 1, 6)
151 #define SDC_IR_CMDCOMPLETE FIELD(1, 1, 7)
152 #define SDC_IR_RXFIFOFULL FIELD(1, 1, 8)
153 #define SDC_IR_RXFIFOEMPTY FIELD(1, 1, 9)
154 #define SDC_IR_TXFIFOFULL FIELD(1, 1, 10)
155 #define SDC_IR_TXFIFOEMPTY FIELD(1, 1, 11)
156 #define SDC_IR_ENDCMDWITHRES FIELD(1, 1, 12)
157
arch/unicore32/include/mach/regs-spi.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity Serial Peripheral Interface (SPI) Registers
3 */
4 /*
5 * Control reg. 0 SPI_CR0
6 */
7 #define SPI_CR0 __REG(PKUNITY_SPI_BASE + 0x0000)
8 /*
9 * Control reg. 1 SPI_CR1
10 */
11 #define SPI_CR1 __REG(PKUNITY_SPI_BASE + 0x0004)
12 /*
13 * Enable reg SPI_SSIENR
14 */
15 #define SPI_SSIENR __REG(PKUNITY_SPI_BASE + 0x0008)
16 /*
17 * Status reg SPI_SR
18 */
19 #define SPI_SR __REG(PKUNITY_SPI_BASE + 0x0028)
20 /*
21 * Interrupt Mask reg SPI_IMR
22 */
23 #define SPI_IMR __REG(PKUNITY_SPI_BASE + 0x002C)
24 /*
25 * Interrupt Status reg SPI_ISR
26 */
27 #define SPI_ISR __REG(PKUNITY_SPI_BASE + 0x0030)
28
29 /*
30 * Enable SPI Controller SPI_SSIENR_EN
31 */
32 #define SPI_SSIENR_EN FIELD(1, 1, 0)
33
34 /*
35 * SPI Busy SPI_SR_BUSY
36 */
37 #define SPI_SR_BUSY FIELD(1, 1, 0)
38 /*
39 * Transmit FIFO Not Full SPI_SR_TFNF
40 */
41 #define SPI_SR_TFNF FIELD(1, 1, 1)
42 /*
43 * Transmit FIFO Empty SPI_SR_TFE
44 */
45 #define SPI_SR_TFE FIELD(1, 1, 2)
46 /*
47 * Receive FIFO Not Empty SPI_SR_RFNE
48 */
49 #define SPI_SR_RFNE FIELD(1, 1, 3)
50 /*
51 * Receive FIFO Full SPI_SR_RFF
52 */
53 #define SPI_SR_RFF FIELD(1, 1, 4)
54
55 /*
56 * Trans. FIFO Empty Interrupt Status SPI_ISR_TXEIS
57 */
58 #define SPI_ISR_TXEIS FIELD(1, 1, 0)
59 /*
60 * Trans. FIFO Overflow Interrupt Status SPI_ISR_TXOIS
61 */
62 #define SPI_ISR_TXOIS FIELD(1, 1, 1)
63 /*
64 * Receiv. FIFO Underflow Interrupt Status SPI_ISR_RXUIS
65 */
66 #define SPI_ISR_RXUIS FIELD(1, 1, 2)
67 /*
68 * Receiv. FIFO Overflow Interrupt Status SPI_ISR_RXOIS
69 */
70 #define SPI_ISR_RXOIS FIELD(1, 1, 3)
71 /*
72 * Receiv. FIFO Full Interrupt Status SPI_ISR_RXFIS
73 */
74 #define SPI_ISR_RXFIS FIELD(1, 1, 4)
75 #define SPI_ISR_MSTIS FIELD(1, 1, 5)
76
77 /*
78 * Trans. FIFO Empty Interrupt Mask SPI_IMR_TXEIM
79 */
80 #define SPI_IMR_TXEIM FIELD(1, 1, 0)
81 /*
82 * Trans. FIFO Overflow Interrupt Mask SPI_IMR_TXOIM
83 */
84 #define SPI_IMR_TXOIM FIELD(1, 1, 1)
85 /*
86 * Receiv. FIFO Underflow Interrupt Mask SPI_IMR_RXUIM
87 */
88 #define SPI_IMR_RXUIM FIELD(1, 1, 2)
89 /*
90 * Receiv. FIFO Overflow Interrupt Mask SPI_IMR_RXOIM
91 */
92 #define SPI_IMR_RXOIM FIELD(1, 1, 3)
93 /*
94 * Receiv. FIFO Full Interrupt Mask SPI_IMR_RXFIM
95 */
96 #define SPI_IMR_RXFIM FIELD(1, 1, 4)
97 #define SPI_IMR_MSTIM FIELD(1, 1, 5)
98
99
arch/unicore32/include/mach/regs-uart.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity Universal Asynchronous Receiver/Transmitter (UART) Registers
3 */
4
arch/unicore32/include/mach/regs-umal.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity Ultra Media Access Layer (UMAL) Ethernet MAC Registers
3 */
4
5 /* MAC module of UMAL */
6 /* UMAL's MAC module includes G/MII interface, several additional PHY
7 * interfaces, and MAC control sub-layer, which provides support for control
8 * frames (e.g. PAUSE frames).
9 */
10 /*
11 * TX/RX reset and control UMAL_CFG1
12 */
13 #define UMAL_CFG1 __REG(PKUNITY_UMAL_BASE + 0x0000)
14 /*
15 * MAC interface mode control UMAL_CFG2
16 */
17 #define UMAL_CFG2 __REG(PKUNITY_UMAL_BASE + 0x0004)
18 /*
19 * Inter Packet/Frame Gap UMAL_IPGIFG
20 */
21 #define UMAL_IPGIFG __REG(PKUNITY_UMAL_BASE + 0x0008)
22 /*
23 * Collision retry or backoff UMAL_HALFDUPLEX
24 */
25 #define UMAL_HALFDUPLEX __REG(PKUNITY_UMAL_BASE + 0x000c)
26 /*
27 * Maximum Frame Length UMAL_MAXFRAME
28 */
29 #define UMAL_MAXFRAME __REG(PKUNITY_UMAL_BASE + 0x0010)
30 /*
31 * Test Regsiter UMAL_TESTREG
32 */
33 #define UMAL_TESTREG __REG(PKUNITY_UMAL_BASE + 0x001c)
34 /*
35 * MII Management Configure UMAL_MIICFG
36 */
37 #define UMAL_MIICFG __REG(PKUNITY_UMAL_BASE + 0x0020)
38 /*
39 * MII Management Command UMAL_MIICMD
40 */
41 #define UMAL_MIICMD __REG(PKUNITY_UMAL_BASE + 0x0024)
42 /*
43 * MII Management Address UMAL_MIIADDR
44 */
45 #define UMAL_MIIADDR __REG(PKUNITY_UMAL_BASE + 0x0028)
46 /*
47 * MII Management Control UMAL_MIICTRL
48 */
49 #define UMAL_MIICTRL __REG(PKUNITY_UMAL_BASE + 0x002c)
50 /*
51 * MII Management Status UMAL_MIISTATUS
52 */
53 #define UMAL_MIISTATUS __REG(PKUNITY_UMAL_BASE + 0x0030)
54 /*
55 * MII Managment Indicator UMAL_MIIIDCT
56 */
57 #define UMAL_MIIIDCT __REG(PKUNITY_UMAL_BASE + 0x0034)
58 /*
59 * Interface Control UMAL_IFCTRL
60 */
61 #define UMAL_IFCTRL __REG(PKUNITY_UMAL_BASE + 0x0038)
62 /*
63 * Interface Status UMAL_IFSTATUS
64 */
65 #define UMAL_IFSTATUS __REG(PKUNITY_UMAL_BASE + 0x003c)
66 /*
67 * MAC address (high 4 bytes) UMAL_STADDR1
68 */
69 #define UMAL_STADDR1 __REG(PKUNITY_UMAL_BASE + 0x0040)
70 /*
71 * MAC address (low 2 bytes) UMAL_STADDR2
72 */
73 #define UMAL_STADDR2 __REG(PKUNITY_UMAL_BASE + 0x0044)
74
75 /* FIFO MODULE OF UMAL */
76 /* UMAL's FIFO module provides data queuing for increased system level
77 * throughput
78 */
79 #define UMAL_FIFOCFG0 __REG(PKUNITY_UMAL_BASE + 0x0048)
80 #define UMAL_FIFOCFG1 __REG(PKUNITY_UMAL_BASE + 0x004c)
81 #define UMAL_FIFOCFG2 __REG(PKUNITY_UMAL_BASE + 0x0050)
82 #define UMAL_FIFOCFG3 __REG(PKUNITY_UMAL_BASE + 0x0054)
83 #define UMAL_FIFOCFG4 __REG(PKUNITY_UMAL_BASE + 0x0058)
84 #define UMAL_FIFOCFG5 __REG(PKUNITY_UMAL_BASE + 0x005c)
85 #define UMAL_FIFORAM0 __REG(PKUNITY_UMAL_BASE + 0x0060)
86 #define UMAL_FIFORAM1 __REG(PKUNITY_UMAL_BASE + 0x0064)
87 #define UMAL_FIFORAM2 __REG(PKUNITY_UMAL_BASE + 0x0068)
88 #define UMAL_FIFORAM3 __REG(PKUNITY_UMAL_BASE + 0x006c)
89 #define UMAL_FIFORAM4 __REG(PKUNITY_UMAL_BASE + 0x0070)
90 #define UMAL_FIFORAM5 __REG(PKUNITY_UMAL_BASE + 0x0074)
91 #define UMAL_FIFORAM6 __REG(PKUNITY_UMAL_BASE + 0x0078)
92 #define UMAL_FIFORAM7 __REG(PKUNITY_UMAL_BASE + 0x007c)
93
94 /* MAHBE MODUEL OF UMAL */
95 /* UMAL's MAHBE module interfaces to the host system through 32-bit AHB Master
96 * and Slave ports.Registers within the M-AHBE provide Control and Status
97 * information concerning these transfers.
98 */
99 /*
100 * Transmit Control UMAL_DMATxCtrl
101 */
102 #define UMAL_DMATxCtrl __REG(PKUNITY_UMAL_BASE + 0x0180)
103 /*
104 * Pointer to TX Descripter UMAL_DMATxDescriptor
105 */
106 #define UMAL_DMATxDescriptor __REG(PKUNITY_UMAL_BASE + 0x0184)
107 /*
108 * Status of Tx Packet Transfers UMAL_DMATxStatus
109 */
110 #define UMAL_DMATxStatus __REG(PKUNITY_UMAL_BASE + 0x0188)
111 /*
112 * Receive Control UMAL_DMARxCtrl
113 */
114 #define UMAL_DMARxCtrl __REG(PKUNITY_UMAL_BASE + 0x018c)
115 /*
116 * Pointer to Rx Descriptor UMAL_DMARxDescriptor
117 */
118 #define UMAL_DMARxDescriptor __REG(PKUNITY_UMAL_BASE + 0x0190)
119 /*
120 * Status of Rx Packet Transfers UMAL_DMARxStatus
121 */
122 #define UMAL_DMARxStatus __REG(PKUNITY_UMAL_BASE + 0x0194)
123 /*
124 * Interrupt Mask UMAL_DMAIntrMask
125 */
126 #define UMAL_DMAIntrMask __REG(PKUNITY_UMAL_BASE + 0x0198)
127 /*
128 * Interrupts, read only UMAL_DMAInterrupt
129 */
130 #define UMAL_DMAInterrupt __REG(PKUNITY_UMAL_BASE + 0x019c)
131
132 /*
133 * Commands for UMAL_CFG1 register
134 */
135 #define UMAL_CFG1_TXENABLE FIELD(1, 1, 0)
136 #define UMAL_CFG1_RXENABLE FIELD(1, 1, 2)
137 #define UMAL_CFG1_TXFLOWCTL FIELD(1, 1, 4)
138 #define UMAL_CFG1_RXFLOWCTL FIELD(1, 1, 5)
139 #define UMAL_CFG1_CONFLPBK FIELD(1, 1, 8)
140 #define UMAL_CFG1_RESET FIELD(1, 1, 31)
141 #define UMAL_CFG1_CONFFLCTL (MAC_TX_FLOW_CTL | MAC_RX_FLOW_CTL)
142
143 /*
144 * Commands for UMAL_CFG2 register
145 */
146 #define UMAL_CFG2_FULLDUPLEX FIELD(1, 1, 0)
147 #define UMAL_CFG2_CRCENABLE FIELD(1, 1, 1)
148 #define UMAL_CFG2_PADCRC FIELD(1, 1, 2)
149 #define UMAL_CFG2_LENGTHCHECK FIELD(1, 1, 4)
150 #define UMAL_CFG2_MODEMASK FMASK(2, 8)
151 #define UMAL_CFG2_NIBBLEMODE FIELD(1, 2, 8)
152 #define UMAL_CFG2_BYTEMODE FIELD(2, 2, 8)
153 #define UMAL_CFG2_PREAMBLENMASK FMASK(4, 12)
154 #define UMAL_CFG2_DEFPREAMBLEN FIELD(7, 4, 12)
155 #define UMAL_CFG2_FD100 (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_NIBBLEMODE \
156 | UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \
157 | UMAL_CFG2_CRCENABLE | UMAL_CFG2_FULLDUPLEX)
158 #define UMAL_CFG2_FD1000 (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_BYTEMODE \
159 | UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \
160 | UMAL_CFG2_CRCENABLE | UMAL_CFG2_FULLDUPLEX)
161 #define UMAL_CFG2_HD100 (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_NIBBLEMODE \
162 | UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \
163 | UMAL_CFG2_CRCENABLE)
164
165 /*
166 * Command for UMAL_IFCTRL register
167 */
168 #define UMAL_IFCTRL_RESET FIELD(1, 1, 31)
169
170 /*
171 * Command for UMAL_MIICFG register
172 */
173 #define UMAL_MIICFG_RESET FIELD(1, 1, 31)
174
175 /*
176 * Command for UMAL_MIICMD register
177 */
178 #define UMAL_MIICMD_READ FIELD(1, 1, 0)
179
180 /*
181 * Command for UMAL_MIIIDCT register
182 */
183 #define UMAL_MIIIDCT_BUSY FIELD(1, 1, 0)
184 #define UMAL_MIIIDCT_NOTVALID FIELD(1, 1, 2)
185
186 /*
187 * Commands for DMATxCtrl regesters
188 */
189 #define UMAL_DMA_Enable FIELD(1, 1, 0)
190
191 /*
192 * Commands for DMARxCtrl regesters
193 */
194 #define UMAL_DMAIntrMask_ENABLEHALFWORD FIELD(1, 1, 16)
195
196 /*
197 * Command for DMARxStatus
198 */
199 #define CLR_RX_BUS_ERR FIELD(1, 1, 3)
200 #define CLR_RX_OVERFLOW FIELD(1, 1, 2)
201 #define CLR_RX_PKT FIELD(1, 1, 0)
202
203 /*
204 * Command for DMATxStatus
205 */
206 #define CLR_TX_BUS_ERR FIELD(1, 1, 3)
207 #define CLR_TX_UNDERRUN FIELD(1, 1, 1)
208 #define CLR_TX_PKT FIELD(1, 1, 0)
209
210 /*
211 * Commands for DMAIntrMask and DMAInterrupt register
212 */
213 #define INT_RX_MASK FIELD(0xd, 4, 4)
214 #define INT_TX_MASK FIELD(0xb, 4, 0)
215
216 #define INT_RX_BUS_ERR FIELD(1, 1, 7)
217 #define INT_RX_OVERFLOW FIELD(1, 1, 6)
218 #define INT_RX_PKT FIELD(1, 1, 4)
219 #define INT_TX_BUS_ERR FIELD(1, 1, 3)
220 #define INT_TX_UNDERRUN FIELD(1, 1, 1)
221 #define INT_TX_PKT FIELD(1, 1, 0)
222
223 /*
224 * MARCOS of UMAL's descriptors
225 */
226 #define UMAL_DESC_PACKETSIZE_EMPTY FIELD(1, 1, 31)
227 #define UMAL_DESC_PACKETSIZE_NONEMPTY FIELD(0, 1, 31)
228 #define UMAL_DESC_PACKETSIZE_SIZEMASK FMASK(12, 0)
229
230
arch/unicore32/include/mach/regs-unigfx.h
Diff comments   View file @ b08b4f8
File was created 1 /*
2 * PKUnity UNIGFX Registers
3 */
4
5 #define UDE_BASE (PKUNITY_UNIGFX_BASE + 0x1400)
6 #define UGE_BASE (PKUNITY_UNIGFX_BASE + 0x0000)
7
8 /*
9 * command reg for UNIGFX DE
10 */
11 /*
12 * control reg UDE_CFG
13 */
14 #define UDE_CFG __REG(UDE_BASE + 0x0000)
15 /*
16 * framebuffer start address reg UDE_FSA
17 */
18 #define UDE_FSA __REG(UDE_BASE + 0x0004)
19 /*
20 * line size reg UDE_LS
21 */
22 #define UDE_LS __REG(UDE_BASE + 0x0008)
23 /*
24 * pitch size reg UDE_PS
25 */
26 #define UDE_PS __REG(UDE_BASE + 0x000C)
27 /*
28 * horizontal active time reg UDE_HAT
29 */
30 #define UDE_HAT __REG(UDE_BASE + 0x0010)
31 /*
32 * horizontal blank time reg UDE_HBT
33 */
34 #define UDE_HBT __REG(UDE_BASE + 0x0014)
35 /*
36 * horizontal sync time reg UDE_HST
37 */
38 #define UDE_HST __REG(UDE_BASE + 0x0018)
39 /*
40 * vertival active time reg UDE_VAT
41 */
42 #define UDE_VAT __REG(UDE_BASE + 0x001C)
43 /*
44 * vertival blank time reg UDE_VBT
45 */
46 #define UDE_VBT __REG(UDE_BASE + 0x0020)
47 /*
48 * vertival sync time reg UDE_VST
49 */
50 #define UDE_VST __REG(UDE_BASE + 0x0024)
51 /*
52 * cursor position UDE_CXY
53 */
54 #define UDE_CXY __REG(UDE_BASE + 0x0028)
55 /*
56 * cursor front color UDE_CC0
57 */
58 #define UDE_CC0 __REG(UDE_BASE + 0x002C)
59 /*
60 * cursor background color UDE_CC1
61 */
62 #define UDE_CC1 __REG(UDE_BASE + 0x0030)
63 /*
64 * video position UDE_VXY
65 */
66 #define UDE_VXY __REG(UDE_BASE + 0x0034)
67 /*
68 * video start address reg UDE_VSA
69 */
70 #define UDE_VSA __REG(UDE_BASE + 0x0040)
71 /*
72 * video size reg UDE_VS
73 */
74 #define UDE_VS __REG(UDE_BASE + 0x004C)
75
76 /*
77 * command reg for UNIGFX GE
78 */
79 /*
80 * src xy reg UGE_SRCXY
81 */
82 #define UGE_SRCXY __REG(UGE_BASE + 0x0000)
83 /*
84 * dst xy reg UGE_DSTXY
85 */
86 #define UGE_DSTXY __REG(UGE_BASE + 0x0004)
87 /*
88 * pitch reg UGE_PITCH
89 */
90 #define UGE_PITCH __REG(UGE_BASE + 0x0008)
91 /*
92 * src start reg UGE_SRCSTART
93 */
94 #define UGE_SRCSTART __REG(UGE_BASE + 0x000C)
95 /*
96 * dst start reg UGE_DSTSTART
97 */
98 #define UGE_DSTSTART __REG(UGE_BASE + 0x0010)
99 /*
100 * width height reg UGE_WIDHEIGHT
101 */
102 #define UGE_WIDHEIGHT __REG(UGE_BASE + 0x0014)
103 /*
104 * rop alpah reg UGE_ROPALPHA
105 */
106 #define UGE_ROPALPHA __REG(UGE_BASE + 0x0018)
107 /*
108 * front color UGE_FCOLOR
109 */
110 #define UGE_FCOLOR __REG(UGE_BASE + 0x001C)
111 /*
112 * background color UGE_BCOLOR
113 */
114 #define UGE_BCOLOR __REG(UGE_BASE + 0x0020)
115 /*
116 * src color key for high value UGE_SCH
117 */
118 #define UGE_SCH __REG(UGE_BASE + 0x0024)
119 /*
120 * dst color key for high value UGE_DCH
121 */
122 #define UGE_DCH __REG(UGE_BASE + 0x0028)
123 /*
124 * src color key for low value UGE_SCL
125 */
126 #define UGE_SCL __REG(UGE_BASE + 0x002C)
127 /*
128 * dst color key for low value UGE_DCL
129 */
130 #define UGE_DCL __REG(UGE_BASE + 0x0030)
131 /*
132 * clip 0 reg UGE_CLIP0
133 */
134 #define UGE_CLIP0 __REG(UGE_BASE + 0x0034)
135 /*
136 * clip 1 reg UGE_CLIP1
137 */
138 #define UGE_CLIP1 __REG(UGE_BASE + 0x0038)
139 /*
140 * command reg UGE_COMMAND
141 */
142 #define UGE_COMMAND __REG(UGE_BASE + 0x003C)
143 /*
144 * pattern 0 UGE_P0
145 */
146 #define UGE_P0 __REG(UGE_BASE + 0x0040)
147 #define UGE_P1 __REG(UGE_BASE + 0x0044)
148 #define UGE_P2 __REG(UGE_BASE + 0x0048)
149 #define UGE_P3 __REG(UGE_BASE + 0x004C)
150 #define UGE_P4 __REG(UGE_BASE + 0x0050)
151 #define UGE_P5 __REG(UGE_BASE + 0x0054)
152 #define UGE_P6 __REG(UGE_BASE + 0x0058)
153 #define UGE_P7 __REG(UGE_BASE + 0x005C)
154 #define UGE_P8 __REG(UGE_BASE + 0x0060)
155 #define UGE_P9 __REG(UGE_BASE + 0x0064)
156 #define UGE_P10 __REG(UGE_BASE + 0x0068)
157 #define UGE_P11 __REG(UGE_BASE + 0x006C)
158 #define UGE_P12 __REG(UGE_BASE + 0x0070)
159 #define UGE_P13 __REG(UGE_BASE + 0x0074)
160 #define UGE_P14 __REG(UGE_BASE + 0x0078)
161 #define UGE_P15 __REG(UGE_BASE + 0x007C)
162 #define UGE_P16 __REG(UGE_BASE + 0x0080)
163 #define UGE_P17 __REG(UGE_BASE + 0x0084)
164 #define UGE_P18 __REG(UGE_BASE + 0x0088)
165 #define UGE_P19 __REG(UGE_BASE + 0x008C)
166 #define UGE_P20 __REG(UGE_BASE + 0x0090)
167 #define UGE_P21 __REG(UGE_BASE + 0x0094)
168 #define UGE_P22 __REG(UGE_BASE + 0x0098)
169 #define UGE_P23 __REG(UGE_BASE + 0x009C)
170 #define UGE_P24 __REG(UGE_BASE + 0x00A0)
171 #define UGE_P25 __REG(UGE_BASE + 0x00A4)
172 #define UGE_P26 __REG(UGE_BASE + 0x00A8)
173 #define UGE_P27 __REG(UGE_BASE + 0x00AC)
174 #define UGE_P28 __REG(UGE_BASE + 0x00B0)
175 #define UGE_P29 __REG(UGE_BASE + 0x00B4)
176 #define UGE_P30 __REG(UGE_BASE + 0x00B8)
177 #define UGE_P31 __REG(UGE_BASE + 0x00BC)
178
179 #define UDE_CFG_DST_MASK FMASK(2, 8)
180 #define UDE_CFG_DST8 FIELD(0x0, 2, 8)
181 #define UDE_CFG_DST16 FIELD(0x1, 2, 8)
182 #define UDE_CFG_DST24 FIELD(0x2, 2, 8)
183 #define UDE_CFG_DST32 FIELD(0x3, 2, 8)
184
185 /*
186 * GDEN enable UDE_CFG_GDEN_ENABLE
187 */
188 #define UDE_CFG_GDEN_ENABLE FIELD(1, 1, 3)
189 /*
190 * VDEN enable UDE_CFG_VDEN_ENABLE
191 */
192 #define UDE_CFG_VDEN_ENABLE FIELD(1, 1, 4)
193 /*
194 * CDEN enable UDE_CFG_CDEN_ENABLE
195 */
196 #define UDE_CFG_CDEN_ENABLE FIELD(1, 1, 5)
197 /*
198 * TIMEUP enable UDE_CFG_TIMEUP_ENABLE
199 */
200 #define UDE_CFG_TIMEUP_ENABLE FIELD(1, 1, 6)
201