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Commit b2f104bba39e16f48b7e0ac6447cc167c54505b8

Authored by Bartlomiej Zolnierkiewicz
Committed by Jeff Garzik
1 parent 8c7e8f947f
Exists in master and in 6 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

pata_legacy: use PIO mask defines 

Acked-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>

Showing 1 changed file with 11 additions and 11 deletions Inline Diff

drivers/ata/pata_legacy.c
Diff comments   View file @ b2f104b
1 /* 1 /*
2 * pata-legacy.c - Legacy port PATA/SATA controller driver. 2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat, all rights reserved. 3 * Copyright 2005/2006 Red Hat, all rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option) 7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version. 8 * any later version.
9 * 9 *
10 * This program is distributed in the hope that it will be useful, 10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 * 14 *
15 * You should have received a copy of the GNU General Public License 15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to 16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18 * 18 *
19 * An ATA driver for the legacy ATA ports. 19 * An ATA driver for the legacy ATA ports.
20 * 20 *
21 * Data Sources: 21 * Data Sources:
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com 22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
23 * HT6560 series: 23 * HT6560 series:
24 * Promise 20230/20620: 24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html 25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html 26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html 27 * http://www.ryston.cz/petr/vlb/pdc20630.html
28 * QDI65x0: 28 * QDI65x0:
29 * http://www.ryston.cz/petr/vlb/qd6500.html 29 * http://www.ryston.cz/petr/vlb/qd6500.html
30 * http://www.ryston.cz/petr/vlb/qd6580.html 30 * http://www.ryston.cz/petr/vlb/qd6580.html
31 * 31 *
32 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c 32 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
33 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by 33 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
34 * Samuel Thibault <samuel.thibault@ens-lyon.org> 34 * Samuel Thibault <samuel.thibault@ens-lyon.org>
35 * 35 *
36 * Unsupported but docs exist: 36 * Unsupported but docs exist:
37 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 37 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
38 * 38 *
39 * This driver handles legacy (that is "ISA/VLB side") IDE ports found 39 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
40 * on PC class systems. There are three hybrid devices that are exceptions 40 * on PC class systems. There are three hybrid devices that are exceptions
41 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and 41 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
42 * the MPIIX where the tuning is PCI side but the IDE is "ISA side". 42 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
43 * 43 *
44 * Specific support is included for the ht6560a/ht6560b/opti82c611a/ 44 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
45 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A 45 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
46 * 46 *
47 * Support for the Winbond 83759A when operating in advanced mode. 47 * Support for the Winbond 83759A when operating in advanced mode.
48 * Multichip mode is not currently supported. 48 * Multichip mode is not currently supported.
49 * 49 *
50 * Use the autospeed and pio_mask options with: 50 * Use the autospeed and pio_mask options with:
51 * Appian ADI/2 aka CLPD7220 or AIC25VL01. 51 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
52 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with 52 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
53 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, 53 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
54 * Winbond W83759A, Promise PDC20230-B 54 * Winbond W83759A, Promise PDC20230-B
55 * 55 *
56 * For now use autospeed and pio_mask as above with the W83759A. This may 56 * For now use autospeed and pio_mask as above with the W83759A. This may
57 * change. 57 * change.
58 * 58 *
59 */ 59 */
60 60
61 #include <linux/async.h> 61 #include <linux/async.h>
62 #include <linux/kernel.h> 62 #include <linux/kernel.h>
63 #include <linux/module.h> 63 #include <linux/module.h>
64 #include <linux/pci.h> 64 #include <linux/pci.h>
65 #include <linux/init.h> 65 #include <linux/init.h>
66 #include <linux/blkdev.h> 66 #include <linux/blkdev.h>
67 #include <linux/delay.h> 67 #include <linux/delay.h>
68 #include <scsi/scsi_host.h> 68 #include <scsi/scsi_host.h>
69 #include <linux/ata.h> 69 #include <linux/ata.h>
70 #include <linux/libata.h> 70 #include <linux/libata.h>
71 #include <linux/platform_device.h> 71 #include <linux/platform_device.h>
72 72
73 #define DRV_NAME "pata_legacy" 73 #define DRV_NAME "pata_legacy"
74 #define DRV_VERSION "0.6.5" 74 #define DRV_VERSION "0.6.5"
75 75
76 #define NR_HOST 6 76 #define NR_HOST 6
77 77
78 static int all; 78 static int all;
79 module_param(all, int, 0444); 79 module_param(all, int, 0444);
80 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)"); 80 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
81 81
82 enum controller { 82 enum controller {
83 BIOS = 0, 83 BIOS = 0,
84 SNOOP = 1, 84 SNOOP = 1,
85 PDC20230 = 2, 85 PDC20230 = 2,
86 HT6560A = 3, 86 HT6560A = 3,
87 HT6560B = 4, 87 HT6560B = 4,
88 OPTI611A = 5, 88 OPTI611A = 5,
89 OPTI46X = 6, 89 OPTI46X = 6,
90 QDI6500 = 7, 90 QDI6500 = 7,
91 QDI6580 = 8, 91 QDI6580 = 8,
92 QDI6580DP = 9, /* Dual channel mode is different */ 92 QDI6580DP = 9, /* Dual channel mode is different */
93 W83759A = 10, 93 W83759A = 10,
94 94
95 UNKNOWN = -1 95 UNKNOWN = -1
96 }; 96 };
97 97
98 struct legacy_data { 98 struct legacy_data {
99 unsigned long timing; 99 unsigned long timing;
100 u8 clock[2]; 100 u8 clock[2];
101 u8 last; 101 u8 last;
102 int fast; 102 int fast;
103 enum controller type; 103 enum controller type;
104 struct platform_device *platform_dev; 104 struct platform_device *platform_dev;
105 }; 105 };
106 106
107 struct legacy_probe { 107 struct legacy_probe {
108 unsigned char *name; 108 unsigned char *name;
109 unsigned long port; 109 unsigned long port;
110 unsigned int irq; 110 unsigned int irq;
111 unsigned int slot; 111 unsigned int slot;
112 enum controller type; 112 enum controller type;
113 unsigned long private; 113 unsigned long private;
114 }; 114 };
115 115
116 struct legacy_controller { 116 struct legacy_controller {
117 const char *name; 117 const char *name;
118 struct ata_port_operations *ops; 118 struct ata_port_operations *ops;
119 unsigned int pio_mask; 119 unsigned int pio_mask;
120 unsigned int flags; 120 unsigned int flags;
121 unsigned int pflags; 121 unsigned int pflags;
122 int (*setup)(struct platform_device *, struct legacy_probe *probe, 122 int (*setup)(struct platform_device *, struct legacy_probe *probe,
123 struct legacy_data *data); 123 struct legacy_data *data);
124 }; 124 };
125 125
126 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; 126 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
127 127
128 static struct legacy_probe probe_list[NR_HOST]; 128 static struct legacy_probe probe_list[NR_HOST];
129 static struct legacy_data legacy_data[NR_HOST]; 129 static struct legacy_data legacy_data[NR_HOST];
130 static struct ata_host *legacy_host[NR_HOST]; 130 static struct ata_host *legacy_host[NR_HOST];
131 static int nr_legacy_host; 131 static int nr_legacy_host;
132 132
133 133
134 static int probe_all; /* Set to check all ISA port ranges */ 134 static int probe_all; /* Set to check all ISA port ranges */
135 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */ 135 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
136 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */ 136 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
137 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */ 137 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
138 static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */ 138 static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
139 static int autospeed; /* Chip present which snoops speed changes */ 139 static int autospeed; /* Chip present which snoops speed changes */
140 static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */ 140 static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
141 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ 141 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
142 142
143 /* Set to probe QDI controllers */ 143 /* Set to probe QDI controllers */
144 #ifdef CONFIG_PATA_QDI_MODULE 144 #ifdef CONFIG_PATA_QDI_MODULE
145 static int qdi = 1; 145 static int qdi = 1;
146 #else 146 #else
147 static int qdi; 147 static int qdi;
148 #endif 148 #endif
149 149
150 #ifdef CONFIG_PATA_WINBOND_VLB_MODULE 150 #ifdef CONFIG_PATA_WINBOND_VLB_MODULE
151 static int winbond = 1; /* Set to probe Winbond controllers, 151 static int winbond = 1; /* Set to probe Winbond controllers,
152 give I/O port if non standard */ 152 give I/O port if non standard */
153 #else 153 #else
154 static int winbond; /* Set to probe Winbond controllers, 154 static int winbond; /* Set to probe Winbond controllers,
155 give I/O port if non standard */ 155 give I/O port if non standard */
156 #endif 156 #endif
157 157
158 /** 158 /**
159 * legacy_probe_add - Add interface to probe list 159 * legacy_probe_add - Add interface to probe list
160 * @port: Controller port 160 * @port: Controller port
161 * @irq: IRQ number 161 * @irq: IRQ number
162 * @type: Controller type 162 * @type: Controller type
163 * @private: Controller specific info 163 * @private: Controller specific info
164 * 164 *
165 * Add an entry into the probe list for ATA controllers. This is used 165 * Add an entry into the probe list for ATA controllers. This is used
166 * to add the default ISA slots and then to build up the table 166 * to add the default ISA slots and then to build up the table
167 * further according to other ISA/VLB/Weird device scans 167 * further according to other ISA/VLB/Weird device scans
168 * 168 *
169 * An I/O port list is used to keep ordering stable and sane, as we 169 * An I/O port list is used to keep ordering stable and sane, as we
170 * don't have any good way to talk about ordering otherwise 170 * don't have any good way to talk about ordering otherwise
171 */ 171 */
172 172
173 static int legacy_probe_add(unsigned long port, unsigned int irq, 173 static int legacy_probe_add(unsigned long port, unsigned int irq,
174 enum controller type, unsigned long private) 174 enum controller type, unsigned long private)
175 { 175 {
176 struct legacy_probe *lp = &probe_list[0]; 176 struct legacy_probe *lp = &probe_list[0];
177 int i; 177 int i;
178 struct legacy_probe *free = NULL; 178 struct legacy_probe *free = NULL;
179 179
180 for (i = 0; i < NR_HOST; i++) { 180 for (i = 0; i < NR_HOST; i++) {
181 if (lp->port == 0 && free == NULL) 181 if (lp->port == 0 && free == NULL)
182 free = lp; 182 free = lp;
183 /* Matching port, or the correct slot for ordering */ 183 /* Matching port, or the correct slot for ordering */
184 if (lp->port == port || legacy_port[i] == port) { 184 if (lp->port == port || legacy_port[i] == port) {
185 free = lp; 185 free = lp;
186 break; 186 break;
187 } 187 }
188 lp++; 188 lp++;
189 } 189 }
190 if (free == NULL) { 190 if (free == NULL) {
191 printk(KERN_ERR "pata_legacy: Too many interfaces.\n"); 191 printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
192 return -1; 192 return -1;
193 } 193 }
194 /* Fill in the entry for later probing */ 194 /* Fill in the entry for later probing */
195 free->port = port; 195 free->port = port;
196 free->irq = irq; 196 free->irq = irq;
197 free->type = type; 197 free->type = type;
198 free->private = private; 198 free->private = private;
199 return 0; 199 return 0;
200 } 200 }
201 201
202 202
203 /** 203 /**
204 * legacy_set_mode - mode setting 204 * legacy_set_mode - mode setting
205 * @link: IDE link 205 * @link: IDE link
206 * @unused: Device that failed when error is returned 206 * @unused: Device that failed when error is returned
207 * 207 *
208 * Use a non standard set_mode function. We don't want to be tuned. 208 * Use a non standard set_mode function. We don't want to be tuned.
209 * 209 *
210 * The BIOS configured everything. Our job is not to fiddle. Just use 210 * The BIOS configured everything. Our job is not to fiddle. Just use
211 * whatever PIO the hardware is using and leave it at that. When we 211 * whatever PIO the hardware is using and leave it at that. When we
212 * get some kind of nice user driven API for control then we can 212 * get some kind of nice user driven API for control then we can
213 * expand on this as per hdparm in the base kernel. 213 * expand on this as per hdparm in the base kernel.
214 */ 214 */
215 215
216 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) 216 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
217 { 217 {
218 struct ata_device *dev; 218 struct ata_device *dev;
219 219
220 ata_for_each_dev(dev, link, ENABLED) { 220 ata_for_each_dev(dev, link, ENABLED) {
221 ata_dev_info(dev, "configured for PIO\n"); 221 ata_dev_info(dev, "configured for PIO\n");
222 dev->pio_mode = XFER_PIO_0; 222 dev->pio_mode = XFER_PIO_0;
223 dev->xfer_mode = XFER_PIO_0; 223 dev->xfer_mode = XFER_PIO_0;
224 dev->xfer_shift = ATA_SHIFT_PIO; 224 dev->xfer_shift = ATA_SHIFT_PIO;
225 dev->flags |= ATA_DFLAG_PIO; 225 dev->flags |= ATA_DFLAG_PIO;
226 } 226 }
227 return 0; 227 return 0;
228 } 228 }
229 229
230 static struct scsi_host_template legacy_sht = { 230 static struct scsi_host_template legacy_sht = {
231 ATA_PIO_SHT(DRV_NAME), 231 ATA_PIO_SHT(DRV_NAME),
232 }; 232 };
233 233
234 static const struct ata_port_operations legacy_base_port_ops = { 234 static const struct ata_port_operations legacy_base_port_ops = {
235 .inherits = &ata_sff_port_ops, 235 .inherits = &ata_sff_port_ops,
236 .cable_detect = ata_cable_40wire, 236 .cable_detect = ata_cable_40wire,
237 }; 237 };
238 238
239 /* 239 /*
240 * These ops are used if the user indicates the hardware 240 * These ops are used if the user indicates the hardware
241 * snoops the commands to decide on the mode and handles the 241 * snoops the commands to decide on the mode and handles the
242 * mode selection "magically" itself. Several legacy controllers 242 * mode selection "magically" itself. Several legacy controllers
243 * do this. The mode range can be set if it is not 0x1F by setting 243 * do this. The mode range can be set if it is not 0x1F by setting
244 * pio_mask as well. 244 * pio_mask as well.
245 */ 245 */
246 246
247 static struct ata_port_operations simple_port_ops = { 247 static struct ata_port_operations simple_port_ops = {
248 .inherits = &legacy_base_port_ops, 248 .inherits = &legacy_base_port_ops,
249 .sff_data_xfer = ata_sff_data_xfer_noirq, 249 .sff_data_xfer = ata_sff_data_xfer_noirq,
250 }; 250 };
251 251
252 static struct ata_port_operations legacy_port_ops = { 252 static struct ata_port_operations legacy_port_ops = {
253 .inherits = &legacy_base_port_ops, 253 .inherits = &legacy_base_port_ops,
254 .sff_data_xfer = ata_sff_data_xfer_noirq, 254 .sff_data_xfer = ata_sff_data_xfer_noirq,
255 .set_mode = legacy_set_mode, 255 .set_mode = legacy_set_mode,
256 }; 256 };
257 257
258 /* 258 /*
259 * Promise 20230C and 20620 support 259 * Promise 20230C and 20620 support
260 * 260 *
261 * This controller supports PIO0 to PIO2. We set PIO timings 261 * This controller supports PIO0 to PIO2. We set PIO timings
262 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA 262 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
263 * support is weird being DMA to controller and PIO'd to the host 263 * support is weird being DMA to controller and PIO'd to the host
264 * and not supported. 264 * and not supported.
265 */ 265 */
266 266
267 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) 267 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
268 { 268 {
269 int tries = 5; 269 int tries = 5;
270 int pio = adev->pio_mode - XFER_PIO_0; 270 int pio = adev->pio_mode - XFER_PIO_0;
271 u8 rt; 271 u8 rt;
272 unsigned long flags; 272 unsigned long flags;
273 273
274 /* Safe as UP only. Force I/Os to occur together */ 274 /* Safe as UP only. Force I/Os to occur together */
275 275
276 local_irq_save(flags); 276 local_irq_save(flags);
277 277
278 /* Unlock the control interface */ 278 /* Unlock the control interface */
279 do { 279 do {
280 inb(0x1F5); 280 inb(0x1F5);
281 outb(inb(0x1F2) | 0x80, 0x1F2); 281 outb(inb(0x1F2) | 0x80, 0x1F2);
282 inb(0x1F2); 282 inb(0x1F2);
283 inb(0x3F6); 283 inb(0x3F6);
284 inb(0x3F6); 284 inb(0x3F6);
285 inb(0x1F2); 285 inb(0x1F2);
286 inb(0x1F2); 286 inb(0x1F2);
287 } 287 }
288 while ((inb(0x1F2) & 0x80) && --tries); 288 while ((inb(0x1F2) & 0x80) && --tries);
289 289
290 local_irq_restore(flags); 290 local_irq_restore(flags);
291 291
292 outb(inb(0x1F4) & 0x07, 0x1F4); 292 outb(inb(0x1F4) & 0x07, 0x1F4);
293 293
294 rt = inb(0x1F3); 294 rt = inb(0x1F3);
295 rt &= 0x07 << (3 * adev->devno); 295 rt &= 0x07 << (3 * adev->devno);
296 if (pio) 296 if (pio)
297 rt |= (1 + 3 * pio) << (3 * adev->devno); 297 rt |= (1 + 3 * pio) << (3 * adev->devno);
298 298
299 udelay(100); 299 udelay(100);
300 outb(inb(0x1F2) | 0x01, 0x1F2); 300 outb(inb(0x1F2) | 0x01, 0x1F2);
301 udelay(100); 301 udelay(100);
302 inb(0x1F5); 302 inb(0x1F5);
303 303
304 } 304 }
305 305
306 static unsigned int pdc_data_xfer_vlb(struct ata_device *dev, 306 static unsigned int pdc_data_xfer_vlb(struct ata_device *dev,
307 unsigned char *buf, unsigned int buflen, int rw) 307 unsigned char *buf, unsigned int buflen, int rw)
308 { 308 {
309 int slop = buflen & 3; 309 int slop = buflen & 3;
310 struct ata_port *ap = dev->link->ap; 310 struct ata_port *ap = dev->link->ap;
311 311
312 /* 32bit I/O capable *and* we need to write a whole number of dwords */ 312 /* 32bit I/O capable *and* we need to write a whole number of dwords */
313 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3) 313 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
314 && (ap->pflags & ATA_PFLAG_PIO32)) { 314 && (ap->pflags & ATA_PFLAG_PIO32)) {
315 unsigned long flags; 315 unsigned long flags;
316 316
317 local_irq_save(flags); 317 local_irq_save(flags);
318 318
319 /* Perform the 32bit I/O synchronization sequence */ 319 /* Perform the 32bit I/O synchronization sequence */
320 ioread8(ap->ioaddr.nsect_addr); 320 ioread8(ap->ioaddr.nsect_addr);
321 ioread8(ap->ioaddr.nsect_addr); 321 ioread8(ap->ioaddr.nsect_addr);
322 ioread8(ap->ioaddr.nsect_addr); 322 ioread8(ap->ioaddr.nsect_addr);
323 323
324 /* Now the data */ 324 /* Now the data */
325 if (rw == READ) 325 if (rw == READ)
326 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 326 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
327 else 327 else
328 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 328 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
329 329
330 if (unlikely(slop)) { 330 if (unlikely(slop)) {
331 __le32 pad; 331 __le32 pad;
332 if (rw == READ) { 332 if (rw == READ) {
333 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 333 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
334 memcpy(buf + buflen - slop, &pad, slop); 334 memcpy(buf + buflen - slop, &pad, slop);
335 } else { 335 } else {
336 memcpy(&pad, buf + buflen - slop, slop); 336 memcpy(&pad, buf + buflen - slop, slop);
337 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 337 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
338 } 338 }
339 buflen += 4 - slop; 339 buflen += 4 - slop;
340 } 340 }
341 local_irq_restore(flags); 341 local_irq_restore(flags);
342 } else 342 } else
343 buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw); 343 buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw);
344 344
345 return buflen; 345 return buflen;
346 } 346 }
347 347
348 static struct ata_port_operations pdc20230_port_ops = { 348 static struct ata_port_operations pdc20230_port_ops = {
349 .inherits = &legacy_base_port_ops, 349 .inherits = &legacy_base_port_ops,
350 .set_piomode = pdc20230_set_piomode, 350 .set_piomode = pdc20230_set_piomode,
351 .sff_data_xfer = pdc_data_xfer_vlb, 351 .sff_data_xfer = pdc_data_xfer_vlb,
352 }; 352 };
353 353
354 /* 354 /*
355 * Holtek 6560A support 355 * Holtek 6560A support
356 * 356 *
357 * This controller supports PIO0 to PIO2 (no IORDY even though higher 357 * This controller supports PIO0 to PIO2 (no IORDY even though higher
358 * timings can be loaded). 358 * timings can be loaded).
359 */ 359 */
360 360
361 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) 361 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
362 { 362 {
363 u8 active, recover; 363 u8 active, recover;
364 struct ata_timing t; 364 struct ata_timing t;
365 365
366 /* Get the timing data in cycles. For now play safe at 50Mhz */ 366 /* Get the timing data in cycles. For now play safe at 50Mhz */
367 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 367 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
368 368
369 active = clamp_val(t.active, 2, 15); 369 active = clamp_val(t.active, 2, 15);
370 recover = clamp_val(t.recover, 4, 15); 370 recover = clamp_val(t.recover, 4, 15);
371 371
372 inb(0x3E6); 372 inb(0x3E6);
373 inb(0x3E6); 373 inb(0x3E6);
374 inb(0x3E6); 374 inb(0x3E6);
375 inb(0x3E6); 375 inb(0x3E6);
376 376
377 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 377 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
378 ioread8(ap->ioaddr.status_addr); 378 ioread8(ap->ioaddr.status_addr);
379 } 379 }
380 380
381 static struct ata_port_operations ht6560a_port_ops = { 381 static struct ata_port_operations ht6560a_port_ops = {
382 .inherits = &legacy_base_port_ops, 382 .inherits = &legacy_base_port_ops,
383 .set_piomode = ht6560a_set_piomode, 383 .set_piomode = ht6560a_set_piomode,
384 }; 384 };
385 385
386 /* 386 /*
387 * Holtek 6560B support 387 * Holtek 6560B support
388 * 388 *
389 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO 389 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
390 * setting unless we see an ATAPI device in which case we force it off. 390 * setting unless we see an ATAPI device in which case we force it off.
391 * 391 *
392 * FIXME: need to implement 2nd channel support. 392 * FIXME: need to implement 2nd channel support.
393 */ 393 */
394 394
395 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) 395 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
396 { 396 {
397 u8 active, recover; 397 u8 active, recover;
398 struct ata_timing t; 398 struct ata_timing t;
399 399
400 /* Get the timing data in cycles. For now play safe at 50Mhz */ 400 /* Get the timing data in cycles. For now play safe at 50Mhz */
401 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 401 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
402 402
403 active = clamp_val(t.active, 2, 15); 403 active = clamp_val(t.active, 2, 15);
404 recover = clamp_val(t.recover, 2, 16); 404 recover = clamp_val(t.recover, 2, 16);
405 recover &= 0x15; 405 recover &= 0x15;
406 406
407 inb(0x3E6); 407 inb(0x3E6);
408 inb(0x3E6); 408 inb(0x3E6);
409 inb(0x3E6); 409 inb(0x3E6);
410 inb(0x3E6); 410 inb(0x3E6);
411 411
412 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 412 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
413 413
414 if (adev->class != ATA_DEV_ATA) { 414 if (adev->class != ATA_DEV_ATA) {
415 u8 rconf = inb(0x3E6); 415 u8 rconf = inb(0x3E6);
416 if (rconf & 0x24) { 416 if (rconf & 0x24) {
417 rconf &= ~0x24; 417 rconf &= ~0x24;
418 outb(rconf, 0x3E6); 418 outb(rconf, 0x3E6);
419 } 419 }
420 } 420 }
421 ioread8(ap->ioaddr.status_addr); 421 ioread8(ap->ioaddr.status_addr);
422 } 422 }
423 423
424 static struct ata_port_operations ht6560b_port_ops = { 424 static struct ata_port_operations ht6560b_port_ops = {
425 .inherits = &legacy_base_port_ops, 425 .inherits = &legacy_base_port_ops,
426 .set_piomode = ht6560b_set_piomode, 426 .set_piomode = ht6560b_set_piomode,
427 }; 427 };
428 428
429 /* 429 /*
430 * Opti core chipset helpers 430 * Opti core chipset helpers
431 */ 431 */
432 432
433 /** 433 /**
434 * opti_syscfg - read OPTI chipset configuration 434 * opti_syscfg - read OPTI chipset configuration
435 * @reg: Configuration register to read 435 * @reg: Configuration register to read
436 * 436 *
437 * Returns the value of an OPTI system board configuration register. 437 * Returns the value of an OPTI system board configuration register.
438 */ 438 */
439 439
440 static u8 opti_syscfg(u8 reg) 440 static u8 opti_syscfg(u8 reg)
441 { 441 {
442 unsigned long flags; 442 unsigned long flags;
443 u8 r; 443 u8 r;
444 444
445 /* Uniprocessor chipset and must force cycles adjancent */ 445 /* Uniprocessor chipset and must force cycles adjancent */
446 local_irq_save(flags); 446 local_irq_save(flags);
447 outb(reg, 0x22); 447 outb(reg, 0x22);
448 r = inb(0x24); 448 r = inb(0x24);
449 local_irq_restore(flags); 449 local_irq_restore(flags);
450 return r; 450 return r;
451 } 451 }
452 452
453 /* 453 /*
454 * Opti 82C611A 454 * Opti 82C611A
455 * 455 *
456 * This controller supports PIO0 to PIO3. 456 * This controller supports PIO0 to PIO3.
457 */ 457 */
458 458
459 static void opti82c611a_set_piomode(struct ata_port *ap, 459 static void opti82c611a_set_piomode(struct ata_port *ap,
460 struct ata_device *adev) 460 struct ata_device *adev)
461 { 461 {
462 u8 active, recover, setup; 462 u8 active, recover, setup;
463 struct ata_timing t; 463 struct ata_timing t;
464 struct ata_device *pair = ata_dev_pair(adev); 464 struct ata_device *pair = ata_dev_pair(adev);
465 int clock; 465 int clock;
466 int khz[4] = { 50000, 40000, 33000, 25000 }; 466 int khz[4] = { 50000, 40000, 33000, 25000 };
467 u8 rc; 467 u8 rc;
468 468
469 /* Enter configuration mode */ 469 /* Enter configuration mode */
470 ioread16(ap->ioaddr.error_addr); 470 ioread16(ap->ioaddr.error_addr);
471 ioread16(ap->ioaddr.error_addr); 471 ioread16(ap->ioaddr.error_addr);
472 iowrite8(3, ap->ioaddr.nsect_addr); 472 iowrite8(3, ap->ioaddr.nsect_addr);
473 473
474 /* Read VLB clock strapping */ 474 /* Read VLB clock strapping */
475 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; 475 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
476 476
477 /* Get the timing data in cycles */ 477 /* Get the timing data in cycles */
478 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 478 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
479 479
480 /* Setup timing is shared */ 480 /* Setup timing is shared */
481 if (pair) { 481 if (pair) {
482 struct ata_timing tp; 482 struct ata_timing tp;
483 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 483 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
484 484
485 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 485 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
486 } 486 }
487 487
488 active = clamp_val(t.active, 2, 17) - 2; 488 active = clamp_val(t.active, 2, 17) - 2;
489 recover = clamp_val(t.recover, 1, 16) - 1; 489 recover = clamp_val(t.recover, 1, 16) - 1;
490 setup = clamp_val(t.setup, 1, 4) - 1; 490 setup = clamp_val(t.setup, 1, 4) - 1;
491 491
492 /* Select the right timing bank for write timing */ 492 /* Select the right timing bank for write timing */
493 rc = ioread8(ap->ioaddr.lbal_addr); 493 rc = ioread8(ap->ioaddr.lbal_addr);
494 rc &= 0x7F; 494 rc &= 0x7F;
495 rc |= (adev->devno << 7); 495 rc |= (adev->devno << 7);
496 iowrite8(rc, ap->ioaddr.lbal_addr); 496 iowrite8(rc, ap->ioaddr.lbal_addr);
497 497
498 /* Write the timings */ 498 /* Write the timings */
499 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 499 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
500 500
501 /* Select the right bank for read timings, also 501 /* Select the right bank for read timings, also
502 load the shared timings for address */ 502 load the shared timings for address */
503 rc = ioread8(ap->ioaddr.device_addr); 503 rc = ioread8(ap->ioaddr.device_addr);
504 rc &= 0xC0; 504 rc &= 0xC0;
505 rc |= adev->devno; /* Index select */ 505 rc |= adev->devno; /* Index select */
506 rc |= (setup << 4) | 0x04; 506 rc |= (setup << 4) | 0x04;
507 iowrite8(rc, ap->ioaddr.device_addr); 507 iowrite8(rc, ap->ioaddr.device_addr);
508 508
509 /* Load the read timings */ 509 /* Load the read timings */
510 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 510 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
511 511
512 /* Ensure the timing register mode is right */ 512 /* Ensure the timing register mode is right */
513 rc = ioread8(ap->ioaddr.lbal_addr); 513 rc = ioread8(ap->ioaddr.lbal_addr);
514 rc &= 0x73; 514 rc &= 0x73;
515 rc |= 0x84; 515 rc |= 0x84;
516 iowrite8(rc, ap->ioaddr.lbal_addr); 516 iowrite8(rc, ap->ioaddr.lbal_addr);
517 517
518 /* Exit command mode */ 518 /* Exit command mode */
519 iowrite8(0x83, ap->ioaddr.nsect_addr); 519 iowrite8(0x83, ap->ioaddr.nsect_addr);
520 } 520 }
521 521
522 522
523 static struct ata_port_operations opti82c611a_port_ops = { 523 static struct ata_port_operations opti82c611a_port_ops = {
524 .inherits = &legacy_base_port_ops, 524 .inherits = &legacy_base_port_ops,
525 .set_piomode = opti82c611a_set_piomode, 525 .set_piomode = opti82c611a_set_piomode,
526 }; 526 };
527 527
528 /* 528 /*
529 * Opti 82C465MV 529 * Opti 82C465MV
530 * 530 *
531 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB 531 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
532 * version is dual channel but doesn't have a lot of unique registers. 532 * version is dual channel but doesn't have a lot of unique registers.
533 */ 533 */
534 534
535 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) 535 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
536 { 536 {
537 u8 active, recover, setup; 537 u8 active, recover, setup;
538 struct ata_timing t; 538 struct ata_timing t;
539 struct ata_device *pair = ata_dev_pair(adev); 539 struct ata_device *pair = ata_dev_pair(adev);
540 int clock; 540 int clock;
541 int khz[4] = { 50000, 40000, 33000, 25000 }; 541 int khz[4] = { 50000, 40000, 33000, 25000 };
542 u8 rc; 542 u8 rc;
543 u8 sysclk; 543 u8 sysclk;
544 544
545 /* Get the clock */ 545 /* Get the clock */
546 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ 546 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */
547 547
548 /* Enter configuration mode */ 548 /* Enter configuration mode */
549 ioread16(ap->ioaddr.error_addr); 549 ioread16(ap->ioaddr.error_addr);
550 ioread16(ap->ioaddr.error_addr); 550 ioread16(ap->ioaddr.error_addr);
551 iowrite8(3, ap->ioaddr.nsect_addr); 551 iowrite8(3, ap->ioaddr.nsect_addr);
552 552
553 /* Read VLB clock strapping */ 553 /* Read VLB clock strapping */
554 clock = 1000000000 / khz[sysclk]; 554 clock = 1000000000 / khz[sysclk];
555 555
556 /* Get the timing data in cycles */ 556 /* Get the timing data in cycles */
557 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 557 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
558 558
559 /* Setup timing is shared */ 559 /* Setup timing is shared */
560 if (pair) { 560 if (pair) {
561 struct ata_timing tp; 561 struct ata_timing tp;
562 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 562 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
563 563
564 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 564 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
565 } 565 }
566 566
567 active = clamp_val(t.active, 2, 17) - 2; 567 active = clamp_val(t.active, 2, 17) - 2;
568 recover = clamp_val(t.recover, 1, 16) - 1; 568 recover = clamp_val(t.recover, 1, 16) - 1;
569 setup = clamp_val(t.setup, 1, 4) - 1; 569 setup = clamp_val(t.setup, 1, 4) - 1;
570 570
571 /* Select the right timing bank for write timing */ 571 /* Select the right timing bank for write timing */
572 rc = ioread8(ap->ioaddr.lbal_addr); 572 rc = ioread8(ap->ioaddr.lbal_addr);
573 rc &= 0x7F; 573 rc &= 0x7F;
574 rc |= (adev->devno << 7); 574 rc |= (adev->devno << 7);
575 iowrite8(rc, ap->ioaddr.lbal_addr); 575 iowrite8(rc, ap->ioaddr.lbal_addr);
576 576
577 /* Write the timings */ 577 /* Write the timings */
578 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 578 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
579 579
580 /* Select the right bank for read timings, also 580 /* Select the right bank for read timings, also
581 load the shared timings for address */ 581 load the shared timings for address */
582 rc = ioread8(ap->ioaddr.device_addr); 582 rc = ioread8(ap->ioaddr.device_addr);
583 rc &= 0xC0; 583 rc &= 0xC0;
584 rc |= adev->devno; /* Index select */ 584 rc |= adev->devno; /* Index select */
585 rc |= (setup << 4) | 0x04; 585 rc |= (setup << 4) | 0x04;
586 iowrite8(rc, ap->ioaddr.device_addr); 586 iowrite8(rc, ap->ioaddr.device_addr);
587 587
588 /* Load the read timings */ 588 /* Load the read timings */
589 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 589 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
590 590
591 /* Ensure the timing register mode is right */ 591 /* Ensure the timing register mode is right */
592 rc = ioread8(ap->ioaddr.lbal_addr); 592 rc = ioread8(ap->ioaddr.lbal_addr);
593 rc &= 0x73; 593 rc &= 0x73;
594 rc |= 0x84; 594 rc |= 0x84;
595 iowrite8(rc, ap->ioaddr.lbal_addr); 595 iowrite8(rc, ap->ioaddr.lbal_addr);
596 596
597 /* Exit command mode */ 597 /* Exit command mode */
598 iowrite8(0x83, ap->ioaddr.nsect_addr); 598 iowrite8(0x83, ap->ioaddr.nsect_addr);
599 599
600 /* We need to know this for quad device on the MVB */ 600 /* We need to know this for quad device on the MVB */
601 ap->host->private_data = ap; 601 ap->host->private_data = ap;
602 } 602 }
603 603
604 /** 604 /**
605 * opt82c465mv_qc_issue - command issue 605 * opt82c465mv_qc_issue - command issue
606 * @qc: command pending 606 * @qc: command pending
607 * 607 *
608 * Called when the libata layer is about to issue a command. We wrap 608 * Called when the libata layer is about to issue a command. We wrap
609 * this interface so that we can load the correct ATA timings. The 609 * this interface so that we can load the correct ATA timings. The
610 * MVB has a single set of timing registers and these are shared 610 * MVB has a single set of timing registers and these are shared
611 * across channels. As there are two registers we really ought to 611 * across channels. As there are two registers we really ought to
612 * track the last two used values as a sort of register window. For 612 * track the last two used values as a sort of register window. For
613 * now we just reload on a channel switch. On the single channel 613 * now we just reload on a channel switch. On the single channel
614 * setup this condition never fires so we do nothing extra. 614 * setup this condition never fires so we do nothing extra.
615 * 615 *
616 * FIXME: dual channel needs ->serialize support 616 * FIXME: dual channel needs ->serialize support
617 */ 617 */
618 618
619 static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) 619 static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
620 { 620 {
621 struct ata_port *ap = qc->ap; 621 struct ata_port *ap = qc->ap;
622 struct ata_device *adev = qc->dev; 622 struct ata_device *adev = qc->dev;
623 623
624 /* If timings are set and for the wrong channel (2nd test is 624 /* If timings are set and for the wrong channel (2nd test is
625 due to a libata shortcoming and will eventually go I hope) */ 625 due to a libata shortcoming and will eventually go I hope) */
626 if (ap->host->private_data != ap->host 626 if (ap->host->private_data != ap->host
627 && ap->host->private_data != NULL) 627 && ap->host->private_data != NULL)
628 opti82c46x_set_piomode(ap, adev); 628 opti82c46x_set_piomode(ap, adev);
629 629
630 return ata_sff_qc_issue(qc); 630 return ata_sff_qc_issue(qc);
631 } 631 }
632 632
633 static struct ata_port_operations opti82c46x_port_ops = { 633 static struct ata_port_operations opti82c46x_port_ops = {
634 .inherits = &legacy_base_port_ops, 634 .inherits = &legacy_base_port_ops,
635 .set_piomode = opti82c46x_set_piomode, 635 .set_piomode = opti82c46x_set_piomode,
636 .qc_issue = opti82c46x_qc_issue, 636 .qc_issue = opti82c46x_qc_issue,
637 }; 637 };
638 638
639 /** 639 /**
640 * qdi65x0_set_piomode - PIO setup for QDI65x0 640 * qdi65x0_set_piomode - PIO setup for QDI65x0
641 * @ap: Port 641 * @ap: Port
642 * @adev: Device 642 * @adev: Device
643 * 643 *
644 * In single channel mode the 6580 has one clock per device and we can 644 * In single channel mode the 6580 has one clock per device and we can
645 * avoid the requirement to clock switch. We also have to load the timing 645 * avoid the requirement to clock switch. We also have to load the timing
646 * into the right clock according to whether we are master or slave. 646 * into the right clock according to whether we are master or slave.
647 * 647 *
648 * In dual channel mode the 6580 has one clock per channel and we have 648 * In dual channel mode the 6580 has one clock per channel and we have
649 * to software clockswitch in qc_issue. 649 * to software clockswitch in qc_issue.
650 */ 650 */
651 651
652 static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev) 652 static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev)
653 { 653 {
654 struct ata_timing t; 654 struct ata_timing t;
655 struct legacy_data *ld_qdi = ap->host->private_data; 655 struct legacy_data *ld_qdi = ap->host->private_data;
656 int active, recovery; 656 int active, recovery;
657 u8 timing; 657 u8 timing;
658 658
659 /* Get the timing data in cycles */ 659 /* Get the timing data in cycles */
660 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 660 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
661 661
662 if (ld_qdi->fast) { 662 if (ld_qdi->fast) {
663 active = 8 - clamp_val(t.active, 1, 8); 663 active = 8 - clamp_val(t.active, 1, 8);
664 recovery = 18 - clamp_val(t.recover, 3, 18); 664 recovery = 18 - clamp_val(t.recover, 3, 18);
665 } else { 665 } else {
666 active = 9 - clamp_val(t.active, 2, 9); 666 active = 9 - clamp_val(t.active, 2, 9);
667 recovery = 15 - clamp_val(t.recover, 0, 15); 667 recovery = 15 - clamp_val(t.recover, 0, 15);
668 } 668 }
669 timing = (recovery << 4) | active | 0x08; 669 timing = (recovery << 4) | active | 0x08;
670 ld_qdi->clock[adev->devno] = timing; 670 ld_qdi->clock[adev->devno] = timing;
671 671
672 if (ld_qdi->type == QDI6580) 672 if (ld_qdi->type == QDI6580)
673 outb(timing, ld_qdi->timing + 2 * adev->devno); 673 outb(timing, ld_qdi->timing + 2 * adev->devno);
674 else 674 else
675 outb(timing, ld_qdi->timing + 2 * ap->port_no); 675 outb(timing, ld_qdi->timing + 2 * ap->port_no);
676 676
677 /* Clear the FIFO */ 677 /* Clear the FIFO */
678 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA) 678 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA)
679 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); 679 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
680 } 680 }
681 681
682 /** 682 /**
683 * qdi_qc_issue - command issue 683 * qdi_qc_issue - command issue
684 * @qc: command pending 684 * @qc: command pending
685 * 685 *
686 * Called when the libata layer is about to issue a command. We wrap 686 * Called when the libata layer is about to issue a command. We wrap
687 * this interface so that we can load the correct ATA timings. 687 * this interface so that we can load the correct ATA timings.
688 */ 688 */
689 689
690 static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) 690 static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
691 { 691 {
692 struct ata_port *ap = qc->ap; 692 struct ata_port *ap = qc->ap;
693 struct ata_device *adev = qc->dev; 693 struct ata_device *adev = qc->dev;
694 struct legacy_data *ld_qdi = ap->host->private_data; 694 struct legacy_data *ld_qdi = ap->host->private_data;
695 695
696 if (ld_qdi->clock[adev->devno] != ld_qdi->last) { 696 if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
697 if (adev->pio_mode) { 697 if (adev->pio_mode) {
698 ld_qdi->last = ld_qdi->clock[adev->devno]; 698 ld_qdi->last = ld_qdi->clock[adev->devno];
699 outb(ld_qdi->clock[adev->devno], ld_qdi->timing + 699 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
700 2 * ap->port_no); 700 2 * ap->port_no);
701 } 701 }
702 } 702 }
703 return ata_sff_qc_issue(qc); 703 return ata_sff_qc_issue(qc);
704 } 704 }
705 705
706 static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf, 706 static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf,
707 unsigned int buflen, int rw) 707 unsigned int buflen, int rw)
708 { 708 {
709 struct ata_port *ap = adev->link->ap; 709 struct ata_port *ap = adev->link->ap;
710 int slop = buflen & 3; 710 int slop = buflen & 3;
711 711
712 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3) 712 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
713 && (ap->pflags & ATA_PFLAG_PIO32)) { 713 && (ap->pflags & ATA_PFLAG_PIO32)) {
714 if (rw == WRITE) 714 if (rw == WRITE)
715 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 715 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
716 else 716 else
717 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 717 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
718 718
719 if (unlikely(slop)) { 719 if (unlikely(slop)) {
720 __le32 pad; 720 __le32 pad;
721 if (rw == WRITE) { 721 if (rw == WRITE) {
722 memcpy(&pad, buf + buflen - slop, slop); 722 memcpy(&pad, buf + buflen - slop, slop);
723 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 723 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
724 } else { 724 } else {
725 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 725 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
726 memcpy(buf + buflen - slop, &pad, slop); 726 memcpy(buf + buflen - slop, &pad, slop);
727 } 727 }
728 } 728 }
729 return (buflen + 3) & ~3; 729 return (buflen + 3) & ~3;
730 } else 730 } else
731 return ata_sff_data_xfer(adev, buf, buflen, rw); 731 return ata_sff_data_xfer(adev, buf, buflen, rw);
732 } 732 }
733 733
734 static int qdi_port(struct platform_device *dev, 734 static int qdi_port(struct platform_device *dev,
735 struct legacy_probe *lp, struct legacy_data *ld) 735 struct legacy_probe *lp, struct legacy_data *ld)
736 { 736 {
737 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) 737 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
738 return -EBUSY; 738 return -EBUSY;
739 ld->timing = lp->private; 739 ld->timing = lp->private;
740 return 0; 740 return 0;
741 } 741 }
742 742
743 static struct ata_port_operations qdi6500_port_ops = { 743 static struct ata_port_operations qdi6500_port_ops = {
744 .inherits = &legacy_base_port_ops, 744 .inherits = &legacy_base_port_ops,
745 .set_piomode = qdi65x0_set_piomode, 745 .set_piomode = qdi65x0_set_piomode,
746 .qc_issue = qdi_qc_issue, 746 .qc_issue = qdi_qc_issue,
747 .sff_data_xfer = vlb32_data_xfer, 747 .sff_data_xfer = vlb32_data_xfer,
748 }; 748 };
749 749
750 static struct ata_port_operations qdi6580_port_ops = { 750 static struct ata_port_operations qdi6580_port_ops = {
751 .inherits = &legacy_base_port_ops, 751 .inherits = &legacy_base_port_ops,
752 .set_piomode = qdi65x0_set_piomode, 752 .set_piomode = qdi65x0_set_piomode,
753 .sff_data_xfer = vlb32_data_xfer, 753 .sff_data_xfer = vlb32_data_xfer,
754 }; 754 };
755 755
756 static struct ata_port_operations qdi6580dp_port_ops = { 756 static struct ata_port_operations qdi6580dp_port_ops = {
757 .inherits = &legacy_base_port_ops, 757 .inherits = &legacy_base_port_ops,
758 .set_piomode = qdi65x0_set_piomode, 758 .set_piomode = qdi65x0_set_piomode,
759 .qc_issue = qdi_qc_issue, 759 .qc_issue = qdi_qc_issue,
760 .sff_data_xfer = vlb32_data_xfer, 760 .sff_data_xfer = vlb32_data_xfer,
761 }; 761 };
762 762
763 static DEFINE_SPINLOCK(winbond_lock); 763 static DEFINE_SPINLOCK(winbond_lock);
764 764
765 static void winbond_writecfg(unsigned long port, u8 reg, u8 val) 765 static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
766 { 766 {
767 unsigned long flags; 767 unsigned long flags;
768 spin_lock_irqsave(&winbond_lock, flags); 768 spin_lock_irqsave(&winbond_lock, flags);
769 outb(reg, port + 0x01); 769 outb(reg, port + 0x01);
770 outb(val, port + 0x02); 770 outb(val, port + 0x02);
771 spin_unlock_irqrestore(&winbond_lock, flags); 771 spin_unlock_irqrestore(&winbond_lock, flags);
772 } 772 }
773 773
774 static u8 winbond_readcfg(unsigned long port, u8 reg) 774 static u8 winbond_readcfg(unsigned long port, u8 reg)
775 { 775 {
776 u8 val; 776 u8 val;
777 777
778 unsigned long flags; 778 unsigned long flags;
779 spin_lock_irqsave(&winbond_lock, flags); 779 spin_lock_irqsave(&winbond_lock, flags);
780 outb(reg, port + 0x01); 780 outb(reg, port + 0x01);
781 val = inb(port + 0x02); 781 val = inb(port + 0x02);
782 spin_unlock_irqrestore(&winbond_lock, flags); 782 spin_unlock_irqrestore(&winbond_lock, flags);
783 783
784 return val; 784 return val;
785 } 785 }
786 786
787 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) 787 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
788 { 788 {
789 struct ata_timing t; 789 struct ata_timing t;
790 struct legacy_data *ld_winbond = ap->host->private_data; 790 struct legacy_data *ld_winbond = ap->host->private_data;
791 int active, recovery; 791 int active, recovery;
792 u8 reg; 792 u8 reg;
793 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); 793 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
794 794
795 reg = winbond_readcfg(ld_winbond->timing, 0x81); 795 reg = winbond_readcfg(ld_winbond->timing, 0x81);
796 796
797 /* Get the timing data in cycles */ 797 /* Get the timing data in cycles */
798 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ 798 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
799 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 799 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
800 else 800 else
801 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 801 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
802 802
803 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F; 803 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
804 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F; 804 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
805 timing = (active << 4) | recovery; 805 timing = (active << 4) | recovery;
806 winbond_writecfg(ld_winbond->timing, timing, reg); 806 winbond_writecfg(ld_winbond->timing, timing, reg);
807 807
808 /* Load the setup timing */ 808 /* Load the setup timing */
809 809
810 reg = 0x35; 810 reg = 0x35;
811 if (adev->class != ATA_DEV_ATA) 811 if (adev->class != ATA_DEV_ATA)
812 reg |= 0x08; /* FIFO off */ 812 reg |= 0x08; /* FIFO off */
813 if (!ata_pio_need_iordy(adev)) 813 if (!ata_pio_need_iordy(adev))
814 reg |= 0x02; /* IORDY off */ 814 reg |= 0x02; /* IORDY off */
815 reg |= (clamp_val(t.setup, 0, 3) << 6); 815 reg |= (clamp_val(t.setup, 0, 3) << 6);
816 winbond_writecfg(ld_winbond->timing, timing + 1, reg); 816 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
817 } 817 }
818 818
819 static int winbond_port(struct platform_device *dev, 819 static int winbond_port(struct platform_device *dev,
820 struct legacy_probe *lp, struct legacy_data *ld) 820 struct legacy_probe *lp, struct legacy_data *ld)
821 { 821 {
822 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) 822 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
823 return -EBUSY; 823 return -EBUSY;
824 ld->timing = lp->private; 824 ld->timing = lp->private;
825 return 0; 825 return 0;
826 } 826 }
827 827
828 static struct ata_port_operations winbond_port_ops = { 828 static struct ata_port_operations winbond_port_ops = {
829 .inherits = &legacy_base_port_ops, 829 .inherits = &legacy_base_port_ops,
830 .set_piomode = winbond_set_piomode, 830 .set_piomode = winbond_set_piomode,
831 .sff_data_xfer = vlb32_data_xfer, 831 .sff_data_xfer = vlb32_data_xfer,
832 }; 832 };
833 833
834 static struct legacy_controller controllers[] = { 834 static struct legacy_controller controllers[] = {
835 {"BIOS", &legacy_port_ops, 0x1F, 835 {"BIOS", &legacy_port_ops, ATA_PIO4,
836 ATA_FLAG_NO_IORDY, 0, NULL }, 836 ATA_FLAG_NO_IORDY, 0, NULL },
837 {"Snooping", &simple_port_ops, 0x1F, 837 {"Snooping", &simple_port_ops, ATA_PIO4,
838 0, 0, NULL }, 838 0, 0, NULL },
839 {"PDC20230", &pdc20230_port_ops, 0x7, 839 {"PDC20230", &pdc20230_port_ops, ATA_PIO2,
840 ATA_FLAG_NO_IORDY, 840 ATA_FLAG_NO_IORDY,
841 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL }, 841 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },
842 {"HT6560A", &ht6560a_port_ops, 0x07, 842 {"HT6560A", &ht6560a_port_ops, ATA_PIO2,
843 ATA_FLAG_NO_IORDY, 0, NULL }, 843 ATA_FLAG_NO_IORDY, 0, NULL },
844 {"HT6560B", &ht6560b_port_ops, 0x1F, 844 {"HT6560B", &ht6560b_port_ops, ATA_PIO4,
845 ATA_FLAG_NO_IORDY, 0, NULL }, 845 ATA_FLAG_NO_IORDY, 0, NULL },
846 {"OPTI82C611A", &opti82c611a_port_ops, 0x0F, 846 {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3,
847 0, 0, NULL }, 847 0, 0, NULL },
848 {"OPTI82C46X", &opti82c46x_port_ops, 0x0F, 848 {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3,
849 0, 0, NULL }, 849 0, 0, NULL },
850 {"QDI6500", &qdi6500_port_ops, 0x07, 850 {"QDI6500", &qdi6500_port_ops, ATA_PIO2,
851 ATA_FLAG_NO_IORDY, 851 ATA_FLAG_NO_IORDY,
852 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 852 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
853 {"QDI6580", &qdi6580_port_ops, 0x1F, 853 {"QDI6580", &qdi6580_port_ops, ATA_PIO4,
854 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 854 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
855 {"QDI6580DP", &qdi6580dp_port_ops, 0x1F, 855 {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4,
856 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 856 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
857 {"W83759A", &winbond_port_ops, 0x1F, 857 {"W83759A", &winbond_port_ops, ATA_PIO4,
858 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, 858 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
859 winbond_port } 859 winbond_port }
860 }; 860 };
861 861
862 /** 862 /**
863 * probe_chip_type - Discover controller 863 * probe_chip_type - Discover controller
864 * @probe: Probe entry to check 864 * @probe: Probe entry to check
865 * 865 *
866 * Probe an ATA port and identify the type of controller. We don't 866 * Probe an ATA port and identify the type of controller. We don't
867 * check if the controller appears to be driveless at this point. 867 * check if the controller appears to be driveless at this point.
868 */ 868 */
869 869
870 static __init int probe_chip_type(struct legacy_probe *probe) 870 static __init int probe_chip_type(struct legacy_probe *probe)
871 { 871 {
872 int mask = 1 << probe->slot; 872 int mask = 1 << probe->slot;
873 873
874 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { 874 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
875 u8 reg = winbond_readcfg(winbond, 0x81); 875 u8 reg = winbond_readcfg(winbond, 0x81);
876 reg |= 0x80; /* jumpered mode off */ 876 reg |= 0x80; /* jumpered mode off */
877 winbond_writecfg(winbond, 0x81, reg); 877 winbond_writecfg(winbond, 0x81, reg);
878 reg = winbond_readcfg(winbond, 0x83); 878 reg = winbond_readcfg(winbond, 0x83);
879 reg |= 0xF0; /* local control */ 879 reg |= 0xF0; /* local control */
880 winbond_writecfg(winbond, 0x83, reg); 880 winbond_writecfg(winbond, 0x83, reg);
881 reg = winbond_readcfg(winbond, 0x85); 881 reg = winbond_readcfg(winbond, 0x85);
882 reg |= 0xF0; /* programmable timing */ 882 reg |= 0xF0; /* programmable timing */
883 winbond_writecfg(winbond, 0x85, reg); 883 winbond_writecfg(winbond, 0x85, reg);
884 884
885 reg = winbond_readcfg(winbond, 0x81); 885 reg = winbond_readcfg(winbond, 0x81);
886 886
887 if (reg & mask) 887 if (reg & mask)
888 return W83759A; 888 return W83759A;
889 } 889 }
890 if (probe->port == 0x1F0) { 890 if (probe->port == 0x1F0) {
891 unsigned long flags; 891 unsigned long flags;
892 local_irq_save(flags); 892 local_irq_save(flags);
893 /* Probes */ 893 /* Probes */
894 outb(inb(0x1F2) | 0x80, 0x1F2); 894 outb(inb(0x1F2) | 0x80, 0x1F2);
895 inb(0x1F5); 895 inb(0x1F5);
896 inb(0x1F2); 896 inb(0x1F2);
897 inb(0x3F6); 897 inb(0x3F6);
898 inb(0x3F6); 898 inb(0x3F6);
899 inb(0x1F2); 899 inb(0x1F2);
900 inb(0x1F2); 900 inb(0x1F2);
901 901
902 if ((inb(0x1F2) & 0x80) == 0) { 902 if ((inb(0x1F2) & 0x80) == 0) {
903 /* PDC20230c or 20630 ? */ 903 /* PDC20230c or 20630 ? */
904 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" 904 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
905 " detected.\n"); 905 " detected.\n");
906 udelay(100); 906 udelay(100);
907 inb(0x1F5); 907 inb(0x1F5);
908 local_irq_restore(flags); 908 local_irq_restore(flags);
909 return PDC20230; 909 return PDC20230;
910 } else { 910 } else {
911 outb(0x55, 0x1F2); 911 outb(0x55, 0x1F2);
912 inb(0x1F2); 912 inb(0x1F2);
913 inb(0x1F2); 913 inb(0x1F2);
914 if (inb(0x1F2) == 0x00) 914 if (inb(0x1F2) == 0x00)
915 printk(KERN_INFO "PDC20230-B VLB ATA " 915 printk(KERN_INFO "PDC20230-B VLB ATA "
916 "controller detected.\n"); 916 "controller detected.\n");
917 local_irq_restore(flags); 917 local_irq_restore(flags);
918 return BIOS; 918 return BIOS;
919 } 919 }
920 local_irq_restore(flags); 920 local_irq_restore(flags);
921 } 921 }
922 922
923 if (ht6560a & mask) 923 if (ht6560a & mask)
924 return HT6560A; 924 return HT6560A;
925 if (ht6560b & mask) 925 if (ht6560b & mask)
926 return HT6560B; 926 return HT6560B;
927 if (opti82c611a & mask) 927 if (opti82c611a & mask)
928 return OPTI611A; 928 return OPTI611A;
929 if (opti82c46x & mask) 929 if (opti82c46x & mask)
930 return OPTI46X; 930 return OPTI46X;
931 if (autospeed & mask) 931 if (autospeed & mask)
932 return SNOOP; 932 return SNOOP;
933 return BIOS; 933 return BIOS;
934 } 934 }
935 935
936 936
937 /** 937 /**
938 * legacy_init_one - attach a legacy interface 938 * legacy_init_one - attach a legacy interface
939 * @pl: probe record 939 * @pl: probe record
940 * 940 *
941 * Register an ISA bus IDE interface. Such interfaces are PIO and we 941 * Register an ISA bus IDE interface. Such interfaces are PIO and we
942 * assume do not support IRQ sharing. 942 * assume do not support IRQ sharing.
943 */ 943 */
944 944
945 static __init int legacy_init_one(struct legacy_probe *probe) 945 static __init int legacy_init_one(struct legacy_probe *probe)
946 { 946 {
947 struct legacy_controller *controller = &controllers[probe->type]; 947 struct legacy_controller *controller = &controllers[probe->type];
948 int pio_modes = controller->pio_mask; 948 int pio_modes = controller->pio_mask;
949 unsigned long io = probe->port; 949 unsigned long io = probe->port;
950 u32 mask = (1 << probe->slot); 950 u32 mask = (1 << probe->slot);
951 struct ata_port_operations *ops = controller->ops; 951 struct ata_port_operations *ops = controller->ops;
952 struct legacy_data *ld = &legacy_data[probe->slot]; 952 struct legacy_data *ld = &legacy_data[probe->slot];
953 struct ata_host *host = NULL; 953 struct ata_host *host = NULL;
954 struct ata_port *ap; 954 struct ata_port *ap;
955 struct platform_device *pdev; 955 struct platform_device *pdev;
956 struct ata_device *dev; 956 struct ata_device *dev;
957 void __iomem *io_addr, *ctrl_addr; 957 void __iomem *io_addr, *ctrl_addr;
958 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; 958 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
959 int ret; 959 int ret;
960 960
961 iordy |= controller->flags; 961 iordy |= controller->flags;
962 962
963 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); 963 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
964 if (IS_ERR(pdev)) 964 if (IS_ERR(pdev))
965 return PTR_ERR(pdev); 965 return PTR_ERR(pdev);
966 966
967 ret = -EBUSY; 967 ret = -EBUSY;
968 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || 968 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
969 devm_request_region(&pdev->dev, io + 0x0206, 1, 969 devm_request_region(&pdev->dev, io + 0x0206, 1,
970 "pata_legacy") == NULL) 970 "pata_legacy") == NULL)
971 goto fail; 971 goto fail;
972 972
973 ret = -ENOMEM; 973 ret = -ENOMEM;
974 io_addr = devm_ioport_map(&pdev->dev, io, 8); 974 io_addr = devm_ioport_map(&pdev->dev, io, 8);
975 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); 975 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
976 if (!io_addr || !ctrl_addr) 976 if (!io_addr || !ctrl_addr)
977 goto fail; 977 goto fail;
978 ld->type = probe->type; 978 ld->type = probe->type;
979 if (controller->setup) 979 if (controller->setup)
980 if (controller->setup(pdev, probe, ld) < 0) 980 if (controller->setup(pdev, probe, ld) < 0)
981 goto fail; 981 goto fail;
982 host = ata_host_alloc(&pdev->dev, 1); 982 host = ata_host_alloc(&pdev->dev, 1);
983 if (!host) 983 if (!host)
984 goto fail; 984 goto fail;
985 ap = host->ports[0]; 985 ap = host->ports[0];
986 986
987 ap->ops = ops; 987 ap->ops = ops;
988 ap->pio_mask = pio_modes; 988 ap->pio_mask = pio_modes;
989 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; 989 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
990 ap->pflags |= controller->pflags; 990 ap->pflags |= controller->pflags;
991 ap->ioaddr.cmd_addr = io_addr; 991 ap->ioaddr.cmd_addr = io_addr;
992 ap->ioaddr.altstatus_addr = ctrl_addr; 992 ap->ioaddr.altstatus_addr = ctrl_addr;
993 ap->ioaddr.ctl_addr = ctrl_addr; 993 ap->ioaddr.ctl_addr = ctrl_addr;
994 ata_sff_std_ports(&ap->ioaddr); 994 ata_sff_std_ports(&ap->ioaddr);
995 ap->host->private_data = ld; 995 ap->host->private_data = ld;
996 996
997 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); 997 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
998 998
999 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0, 999 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
1000 &legacy_sht); 1000 &legacy_sht);
1001 if (ret) 1001 if (ret)
1002 goto fail; 1002 goto fail;
1003 async_synchronize_full(); 1003 async_synchronize_full();
1004 ld->platform_dev = pdev; 1004 ld->platform_dev = pdev;
1005 1005
1006 /* Nothing found means we drop the port as its probably not there */ 1006 /* Nothing found means we drop the port as its probably not there */
1007 1007
1008 ret = -ENODEV; 1008 ret = -ENODEV;
1009 ata_for_each_dev(dev, &ap->link, ALL) { 1009 ata_for_each_dev(dev, &ap->link, ALL) {
1010 if (!ata_dev_absent(dev)) { 1010 if (!ata_dev_absent(dev)) {
1011 legacy_host[probe->slot] = host; 1011 legacy_host[probe->slot] = host;
1012 ld->platform_dev = pdev; 1012 ld->platform_dev = pdev;
1013 return 0; 1013 return 0;
1014 } 1014 }
1015 } 1015 }
1016 ata_host_detach(host); 1016 ata_host_detach(host);
1017 fail: 1017 fail:
1018 platform_device_unregister(pdev); 1018 platform_device_unregister(pdev);
1019 return ret; 1019 return ret;
1020 } 1020 }
1021 1021
1022 /** 1022 /**
1023 * legacy_check_special_cases - ATA special cases 1023 * legacy_check_special_cases - ATA special cases
1024 * @p: PCI device to check 1024 * @p: PCI device to check
1025 * @master: set this if we find an ATA master 1025 * @master: set this if we find an ATA master
1026 * @master: set this if we find an ATA secondary 1026 * @master: set this if we find an ATA secondary
1027 * 1027 *
1028 * A small number of vendors implemented early PCI ATA interfaces 1028 * A small number of vendors implemented early PCI ATA interfaces
1029 * on bridge logic without the ATA interface being PCI visible. 1029 * on bridge logic without the ATA interface being PCI visible.
1030 * Where we have a matching PCI driver we must skip the relevant 1030 * Where we have a matching PCI driver we must skip the relevant
1031 * device here. If we don't know about it then the legacy driver 1031 * device here. If we don't know about it then the legacy driver
1032 * is the right driver anyway. 1032 * is the right driver anyway.
1033 */ 1033 */
1034 1034
1035 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, 1035 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1036 int *secondary) 1036 int *secondary)
1037 { 1037 {
1038 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ 1038 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1039 if (p->vendor == 0x1078 && p->device == 0x0000) { 1039 if (p->vendor == 0x1078 && p->device == 0x0000) {
1040 *primary = *secondary = 1; 1040 *primary = *secondary = 1;
1041 return; 1041 return;
1042 } 1042 }
1043 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ 1043 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1044 if (p->vendor == 0x1078 && p->device == 0x0002) { 1044 if (p->vendor == 0x1078 && p->device == 0x0002) {
1045 *primary = *secondary = 1; 1045 *primary = *secondary = 1;
1046 return; 1046 return;
1047 } 1047 }
1048 /* Intel MPIIX - PIO ATA on non PCI side of bridge */ 1048 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1049 if (p->vendor == 0x8086 && p->device == 0x1234) { 1049 if (p->vendor == 0x8086 && p->device == 0x1234) {
1050 u16 r; 1050 u16 r;
1051 pci_read_config_word(p, 0x6C, &r); 1051 pci_read_config_word(p, 0x6C, &r);
1052 if (r & 0x8000) { 1052 if (r & 0x8000) {
1053 /* ATA port enabled */ 1053 /* ATA port enabled */
1054 if (r & 0x4000) 1054 if (r & 0x4000)
1055 *secondary = 1; 1055 *secondary = 1;
1056 else 1056 else
1057 *primary = 1; 1057 *primary = 1;
1058 } 1058 }
1059 return; 1059 return;
1060 } 1060 }
1061 } 1061 }
1062 1062
1063 static __init void probe_opti_vlb(void) 1063 static __init void probe_opti_vlb(void)
1064 { 1064 {
1065 /* If an OPTI 82C46X is present find out where the channels are */ 1065 /* If an OPTI 82C46X is present find out where the channels are */
1066 static const char *optis[4] = { 1066 static const char *optis[4] = {
1067 "3/463MV", "5MV", 1067 "3/463MV", "5MV",
1068 "5MVA", "5MVB" 1068 "5MVA", "5MVB"
1069 }; 1069 };
1070 u8 chans = 1; 1070 u8 chans = 1;
1071 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; 1071 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1072 1072
1073 opti82c46x = 3; /* Assume master and slave first */ 1073 opti82c46x = 3; /* Assume master and slave first */
1074 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", 1074 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1075 optis[ctrl]); 1075 optis[ctrl]);
1076 if (ctrl == 3) 1076 if (ctrl == 3)
1077 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; 1077 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1078 ctrl = opti_syscfg(0xAC); 1078 ctrl = opti_syscfg(0xAC);
1079 /* Check enabled and this port is the 465MV port. On the 1079 /* Check enabled and this port is the 465MV port. On the
1080 MVB we may have two channels */ 1080 MVB we may have two channels */
1081 if (ctrl & 8) { 1081 if (ctrl & 8) {
1082 if (chans == 2) { 1082 if (chans == 2) {
1083 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1083 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1084 legacy_probe_add(0x170, 15, OPTI46X, 0); 1084 legacy_probe_add(0x170, 15, OPTI46X, 0);
1085 } 1085 }
1086 if (ctrl & 4) 1086 if (ctrl & 4)
1087 legacy_probe_add(0x170, 15, OPTI46X, 0); 1087 legacy_probe_add(0x170, 15, OPTI46X, 0);
1088 else 1088 else
1089 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1089 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1090 } else 1090 } else
1091 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1091 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1092 } 1092 }
1093 1093
1094 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) 1094 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1095 { 1095 {
1096 static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; 1096 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1097 /* Check card type */ 1097 /* Check card type */
1098 if ((r & 0xF0) == 0xC0) { 1098 if ((r & 0xF0) == 0xC0) {
1099 /* QD6500: single channel */ 1099 /* QD6500: single channel */
1100 if (r & 8) 1100 if (r & 8)
1101 /* Disabled ? */ 1101 /* Disabled ? */
1102 return; 1102 return;
1103 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1103 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1104 QDI6500, port); 1104 QDI6500, port);
1105 } 1105 }
1106 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { 1106 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1107 /* QD6580: dual channel */ 1107 /* QD6580: dual channel */
1108 if (!request_region(port + 2 , 2, "pata_qdi")) { 1108 if (!request_region(port + 2 , 2, "pata_qdi")) {
1109 release_region(port, 2); 1109 release_region(port, 2);
1110 return; 1110 return;
1111 } 1111 }
1112 res = inb(port + 3); 1112 res = inb(port + 3);
1113 /* Single channel mode ? */ 1113 /* Single channel mode ? */
1114 if (res & 1) 1114 if (res & 1)
1115 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1115 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1116 QDI6580, port); 1116 QDI6580, port);
1117 else { /* Dual channel mode */ 1117 else { /* Dual channel mode */
1118 legacy_probe_add(0x1F0, 14, QDI6580DP, port); 1118 legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1119 /* port + 0x02, r & 0x04 */ 1119 /* port + 0x02, r & 0x04 */
1120 legacy_probe_add(0x170, 15, QDI6580DP, port + 2); 1120 legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1121 } 1121 }
1122 release_region(port + 2, 2); 1122 release_region(port + 2, 2);
1123 } 1123 }
1124 } 1124 }
1125 1125
1126 static __init void probe_qdi_vlb(void) 1126 static __init void probe_qdi_vlb(void)
1127 { 1127 {
1128 unsigned long flags; 1128 unsigned long flags;
1129 static const unsigned long qd_port[2] = { 0x30, 0xB0 }; 1129 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1130 int i; 1130 int i;
1131 1131
1132 /* 1132 /*
1133 * Check each possible QD65xx base address 1133 * Check each possible QD65xx base address
1134 */ 1134 */
1135 1135
1136 for (i = 0; i < 2; i++) { 1136 for (i = 0; i < 2; i++) {
1137 unsigned long port = qd_port[i]; 1137 unsigned long port = qd_port[i];
1138 u8 r, res; 1138 u8 r, res;
1139 1139
1140 1140
1141 if (request_region(port, 2, "pata_qdi")) { 1141 if (request_region(port, 2, "pata_qdi")) {
1142 /* Check for a card */ 1142 /* Check for a card */
1143 local_irq_save(flags); 1143 local_irq_save(flags);
1144 /* I have no h/w that needs this delay but it 1144 /* I have no h/w that needs this delay but it
1145 is present in the historic code */ 1145 is present in the historic code */
1146 r = inb(port); 1146 r = inb(port);
1147 udelay(1); 1147 udelay(1);
1148 outb(0x19, port); 1148 outb(0x19, port);
1149 udelay(1); 1149 udelay(1);
1150 res = inb(port); 1150 res = inb(port);
1151 udelay(1); 1151 udelay(1);
1152 outb(r, port); 1152 outb(r, port);
1153 udelay(1); 1153 udelay(1);
1154 local_irq_restore(flags); 1154 local_irq_restore(flags);
1155 1155
1156 /* Fail */ 1156 /* Fail */
1157 if (res == 0x19) { 1157 if (res == 0x19) {
1158 release_region(port, 2); 1158 release_region(port, 2);
1159 continue; 1159 continue;
1160 } 1160 }
1161 /* Passes the presence test */ 1161 /* Passes the presence test */
1162 r = inb(port + 1); 1162 r = inb(port + 1);
1163 udelay(1); 1163 udelay(1);
1164 /* Check port agrees with port set */ 1164 /* Check port agrees with port set */
1165 if ((r & 2) >> 1 == i) 1165 if ((r & 2) >> 1 == i)
1166 qdi65_identify_port(r, res, port); 1166 qdi65_identify_port(r, res, port);
1167 release_region(port, 2); 1167 release_region(port, 2);
1168 } 1168 }
1169 } 1169 }
1170 } 1170 }
1171 1171
1172 /** 1172 /**
1173 * legacy_init - attach legacy interfaces 1173 * legacy_init - attach legacy interfaces
1174 * 1174 *
1175 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. 1175 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1176 * Right now we do not scan the ide0 and ide1 address but should do so 1176 * Right now we do not scan the ide0 and ide1 address but should do so
1177 * for non PCI systems or systems with no PCI IDE legacy mode devices. 1177 * for non PCI systems or systems with no PCI IDE legacy mode devices.
1178 * If you fix that note there are special cases to consider like VLB 1178 * If you fix that note there are special cases to consider like VLB
1179 * drivers and CS5510/20. 1179 * drivers and CS5510/20.
1180 */ 1180 */
1181 1181
1182 static __init int legacy_init(void) 1182 static __init int legacy_init(void)
1183 { 1183 {
1184 int i; 1184 int i;
1185 int ct = 0; 1185 int ct = 0;
1186 int primary = 0; 1186 int primary = 0;
1187 int secondary = 0; 1187 int secondary = 0;
1188 int pci_present = 0; 1188 int pci_present = 0;
1189 struct legacy_probe *pl = &probe_list[0]; 1189 struct legacy_probe *pl = &probe_list[0];
1190 int slot = 0; 1190 int slot = 0;
1191 1191
1192 struct pci_dev *p = NULL; 1192 struct pci_dev *p = NULL;
1193 1193
1194 for_each_pci_dev(p) { 1194 for_each_pci_dev(p) {
1195 int r; 1195 int r;
1196 /* Check for any overlap of the system ATA mappings. Native 1196 /* Check for any overlap of the system ATA mappings. Native
1197 mode controllers stuck on these addresses or some devices 1197 mode controllers stuck on these addresses or some devices
1198 in 'raid' mode won't be found by the storage class test */ 1198 in 'raid' mode won't be found by the storage class test */
1199 for (r = 0; r < 6; r++) { 1199 for (r = 0; r < 6; r++) {
1200 if (pci_resource_start(p, r) == 0x1f0) 1200 if (pci_resource_start(p, r) == 0x1f0)
1201 primary = 1; 1201 primary = 1;
1202 if (pci_resource_start(p, r) == 0x170) 1202 if (pci_resource_start(p, r) == 0x170)
1203 secondary = 1; 1203 secondary = 1;
1204 } 1204 }
1205 /* Check for special cases */ 1205 /* Check for special cases */
1206 legacy_check_special_cases(p, &primary, &secondary); 1206 legacy_check_special_cases(p, &primary, &secondary);
1207 1207
1208 /* If PCI bus is present then don't probe for tertiary 1208 /* If PCI bus is present then don't probe for tertiary
1209 legacy ports */ 1209 legacy ports */
1210 pci_present = 1; 1210 pci_present = 1;
1211 } 1211 }
1212 1212
1213 if (winbond == 1) 1213 if (winbond == 1)
1214 winbond = 0x130; /* Default port, alt is 1B0 */ 1214 winbond = 0x130; /* Default port, alt is 1B0 */
1215 1215
1216 if (primary == 0 || all) 1216 if (primary == 0 || all)
1217 legacy_probe_add(0x1F0, 14, UNKNOWN, 0); 1217 legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1218 if (secondary == 0 || all) 1218 if (secondary == 0 || all)
1219 legacy_probe_add(0x170, 15, UNKNOWN, 0); 1219 legacy_probe_add(0x170, 15, UNKNOWN, 0);
1220 1220
1221 if (probe_all || !pci_present) { 1221 if (probe_all || !pci_present) {
1222 /* ISA/VLB extra ports */ 1222 /* ISA/VLB extra ports */
1223 legacy_probe_add(0x1E8, 11, UNKNOWN, 0); 1223 legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1224 legacy_probe_add(0x168, 10, UNKNOWN, 0); 1224 legacy_probe_add(0x168, 10, UNKNOWN, 0);
1225 legacy_probe_add(0x1E0, 8, UNKNOWN, 0); 1225 legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1226 legacy_probe_add(0x160, 12, UNKNOWN, 0); 1226 legacy_probe_add(0x160, 12, UNKNOWN, 0);
1227 } 1227 }
1228 1228
1229 if (opti82c46x) 1229 if (opti82c46x)
1230 probe_opti_vlb(); 1230 probe_opti_vlb();
1231 if (qdi) 1231 if (qdi)
1232 probe_qdi_vlb(); 1232 probe_qdi_vlb();
1233 1233
1234 for (i = 0; i < NR_HOST; i++, pl++) { 1234 for (i = 0; i < NR_HOST; i++, pl++) {
1235 if (pl->port == 0) 1235 if (pl->port == 0)
1236 continue; 1236 continue;
1237 if (pl->type == UNKNOWN) 1237 if (pl->type == UNKNOWN)
1238 pl->type = probe_chip_type(pl); 1238 pl->type = probe_chip_type(pl);
1239 pl->slot = slot++; 1239 pl->slot = slot++;
1240 if (legacy_init_one(pl) == 0) 1240 if (legacy_init_one(pl) == 0)
1241 ct++; 1241 ct++;
1242 } 1242 }
1243 if (ct != 0) 1243 if (ct != 0)
1244 return 0; 1244 return 0;
1245 return -ENODEV; 1245 return -ENODEV;
1246 } 1246 }
1247 1247
1248 static __exit void legacy_exit(void) 1248 static __exit void legacy_exit(void)
1249 { 1249 {
1250 int i; 1250 int i;
1251 1251
1252 for (i = 0; i < nr_legacy_host; i++) { 1252 for (i = 0; i < nr_legacy_host; i++) {
1253 struct legacy_data *ld = &legacy_data[i]; 1253 struct legacy_data *ld = &legacy_data[i];
1254 ata_host_detach(legacy_host[i]); 1254 ata_host_detach(legacy_host[i]);
1255 platform_device_unregister(ld->platform_dev); 1255 platform_device_unregister(ld->platform_dev);
1256 } 1256 }
1257 } 1257 }
1258 1258
1259 MODULE_AUTHOR("Alan Cox"); 1259 MODULE_AUTHOR("Alan Cox");
1260 MODULE_DESCRIPTION("low-level driver for legacy ATA"); 1260 MODULE_DESCRIPTION("low-level driver for legacy ATA");
1261 MODULE_LICENSE("GPL"); 1261 MODULE_LICENSE("GPL");
1262 MODULE_VERSION(DRV_VERSION); 1262 MODULE_VERSION(DRV_VERSION);
1263 MODULE_ALIAS("pata_qdi"); 1263 MODULE_ALIAS("pata_qdi");
1264 MODULE_ALIAS("pata_winbond"); 1264 MODULE_ALIAS("pata_winbond");
1265 1265
1266 module_param(probe_all, int, 0); 1266 module_param(probe_all, int, 0);
1267 module_param(autospeed, int, 0); 1267 module_param(autospeed, int, 0);
1268 module_param(ht6560a, int, 0); 1268 module_param(ht6560a, int, 0);
1269 module_param(ht6560b, int, 0); 1269 module_param(ht6560b, int, 0);
1270 module_param(opti82c611a, int, 0); 1270 module_param(opti82c611a, int, 0);
1271 module_param(opti82c46x, int, 0); 1271 module_param(opti82c46x, int, 0);
1272 module_param(qdi, int, 0); 1272 module_param(qdi, int, 0);
1273 module_param(winbond, int, 0); 1273 module_param(winbond, int, 0);
1274 module_param(pio_mask, int, 0); 1274 module_param(pio_mask, int, 0);
1275 module_param(iordy_mask, int, 0); 1275 module_param(iordy_mask, int, 0);
1276 1276
1277 module_init(legacy_init); 1277 module_init(legacy_init);
1278 module_exit(legacy_exit); 1278 module_exit(legacy_exit);
1279 1279