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Commit b393c69652333be31ad7a8205761c0d5b7f3e167

Authored by Eric Miao
1 parent 5742964e91
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[ARM] pxa: move PCMCIA definitions out of pxa-regs.h into pxa2xx_base.c 

Move the processor specific initialization (largely resources initialization)
out of soc_common_drv_pcmcia_probe() into dedicated sa11xx_drv_pcmcia_probe()
and __pxa2xx_drv_pcmcia_probe().

By doing this, we are now able to move the PCMCIA related definitions out of
pxa-regs.h and back into pxa2xx_base.c.

As a result, remove that reference of _PCMCIA1IO in arch/arm/mach-pxa/viper.c.

Signed-off-by: Eric Miao <eric.miao@marvell.com>

Showing 6 changed files with 141 additions and 94 deletions Inline Diff

arch/arm/mach-pxa/include/mach/pxa-regs.h
Diff comments   View file @ b393c69
1 /* 1 /*
2 * arch/arm/mach-pxa/include/mach/pxa-regs.h 2 * arch/arm/mach-pxa/include/mach/pxa-regs.h
3 * 3 *
4 * Author: Nicolas Pitre 4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001 5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc. 6 * Copyright: MontaVista Software Inc.
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13 #ifndef __PXA_REGS_H 13 #ifndef __PXA_REGS_H
14 #define __PXA_REGS_H 14 #define __PXA_REGS_H
15 15
16 #include <mach/hardware.h> 16 #include <mach/hardware.h>
17 17
18 /* 18 /*
19 * PXA Chip selects 19 * PXA Chip selects
20 */ 20 */
21 21
22 #define PXA_CS0_PHYS 0x00000000 22 #define PXA_CS0_PHYS 0x00000000
23 #define PXA_CS1_PHYS 0x04000000 23 #define PXA_CS1_PHYS 0x04000000
24 #define PXA_CS2_PHYS 0x08000000 24 #define PXA_CS2_PHYS 0x08000000
25 #define PXA_CS3_PHYS 0x0C000000 25 #define PXA_CS3_PHYS 0x0C000000
26 #define PXA_CS4_PHYS 0x10000000 26 #define PXA_CS4_PHYS 0x10000000
27 #define PXA_CS5_PHYS 0x14000000 27 #define PXA_CS5_PHYS 0x14000000
28 28
29 29
30 /* 30 /*
31 * Personal Computer Memory Card International Association (PCMCIA) sockets
32 */
33
34 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
35 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
36 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
37 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
38 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
39
40 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
41 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
42 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
43 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
44
45 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
46 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
47 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
48 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
49
50 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
51 (0x20000000 + (Nb)*PCMCIASp)
52 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
53 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
54 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
55 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
56 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
57
58 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
59 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
60 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
61 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
62
63 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
64 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
65 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
66 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
67
68 /*
69 * Real Time Clock 31 * Real Time Clock
70 */ 32 */
71 33
72 #define RCNR __REG(0x40900000) /* RTC Count Register */ 34 #define RCNR __REG(0x40900000) /* RTC Count Register */
73 #define RTAR __REG(0x40900004) /* RTC Alarm Register */ 35 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
74 #define RTSR __REG(0x40900008) /* RTC Status Register */ 36 #define RTSR __REG(0x40900008) /* RTC Status Register */
75 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ 37 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
76 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ 38 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
77 39
78 #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ 40 #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
79 #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ 41 #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
80 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ 42 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
81 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ 43 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
82 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ 44 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
83 #define RTSR_AL (1 << 0) /* RTC alarm detected */ 45 #define RTSR_AL (1 << 0) /* RTC alarm detected */
84 46
85 47
86 /* 48 /*
87 * OS Timer & Match Registers 49 * OS Timer & Match Registers
88 */ 50 */
89 51
90 #define OSMR0 __REG(0x40A00000) /* */ 52 #define OSMR0 __REG(0x40A00000) /* */
91 #define OSMR1 __REG(0x40A00004) /* */ 53 #define OSMR1 __REG(0x40A00004) /* */
92 #define OSMR2 __REG(0x40A00008) /* */ 54 #define OSMR2 __REG(0x40A00008) /* */
93 #define OSMR3 __REG(0x40A0000C) /* */ 55 #define OSMR3 __REG(0x40A0000C) /* */
94 #define OSMR4 __REG(0x40A00080) /* */ 56 #define OSMR4 __REG(0x40A00080) /* */
95 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ 57 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
96 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ 58 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
97 #define OMCR4 __REG(0x40A000C0) /* */ 59 #define OMCR4 __REG(0x40A000C0) /* */
98 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ 60 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */
99 #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ 61 #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
100 #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ 62 #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
101 63
102 #define OSSR_M3 (1 << 3) /* Match status channel 3 */ 64 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
103 #define OSSR_M2 (1 << 2) /* Match status channel 2 */ 65 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
104 #define OSSR_M1 (1 << 1) /* Match status channel 1 */ 66 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
105 #define OSSR_M0 (1 << 0) /* Match status channel 0 */ 67 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
106 68
107 #define OWER_WME (1 << 0) /* Watchdog Match Enable */ 69 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
108 70
109 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ 71 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
110 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ 72 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
111 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ 73 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
112 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ 74 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
113 75
114 76
115 /* 77 /*
116 * Interrupt Controller 78 * Interrupt Controller
117 */ 79 */
118 80
119 #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ 81 #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
120 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ 82 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
121 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ 83 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
122 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ 84 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
123 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ 85 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
124 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ 86 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
125 87
126 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ 88 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
127 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ 89 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
128 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ 90 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
129 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ 91 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
130 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ 92 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
131 93
132 #endif 94 #endif
133 95
arch/arm/mach-pxa/viper.c
Diff comments   View file @ b393c69
1 /* 1 /*
2 * linux/arch/arm/mach-pxa/viper.c 2 * linux/arch/arm/mach-pxa/viper.c
3 * 3 *
4 * Support for the Arcom VIPER SBC. 4 * Support for the Arcom VIPER SBC.
5 * 5 *
6 * Author: Ian Campbell 6 * Author: Ian Campbell
7 * Created: Feb 03, 2003 7 * Created: Feb 03, 2003
8 * Copyright: Arcom Control Systems 8 * Copyright: Arcom Control Systems
9 * 9 *
10 * Maintained by Marc Zyngier <maz@misterjones.org> 10 * Maintained by Marc Zyngier <maz@misterjones.org>
11 * <marc.zyngier@altran.com> 11 * <marc.zyngier@altran.com>
12 * 12 *
13 * Based on lubbock.c: 13 * Based on lubbock.c:
14 * Author: Nicolas Pitre 14 * Author: Nicolas Pitre
15 * Created: Jun 15, 2001 15 * Created: Jun 15, 2001
16 * Copyright: MontaVista Software Inc. 16 * Copyright: MontaVista Software Inc.
17 * 17 *
18 * This program is free software; you can redistribute it and/or modify 18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as 19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation. 20 * published by the Free Software Foundation.
21 */ 21 */
22 22
23 #include <linux/types.h> 23 #include <linux/types.h>
24 #include <linux/memory.h> 24 #include <linux/memory.h>
25 #include <linux/cpu.h> 25 #include <linux/cpu.h>
26 #include <linux/cpufreq.h> 26 #include <linux/cpufreq.h>
27 #include <linux/delay.h> 27 #include <linux/delay.h>
28 #include <linux/fs.h> 28 #include <linux/fs.h>
29 #include <linux/init.h> 29 #include <linux/init.h>
30 #include <linux/interrupt.h> 30 #include <linux/interrupt.h>
31 #include <linux/major.h> 31 #include <linux/major.h>
32 #include <linux/module.h> 32 #include <linux/module.h>
33 #include <linux/pm.h> 33 #include <linux/pm.h>
34 #include <linux/sched.h> 34 #include <linux/sched.h>
35 #include <linux/gpio.h> 35 #include <linux/gpio.h>
36 #include <linux/i2c-gpio.h> 36 #include <linux/i2c-gpio.h>
37 #include <linux/serial_8250.h> 37 #include <linux/serial_8250.h>
38 #include <linux/smc91x.h> 38 #include <linux/smc91x.h>
39 #include <linux/pwm_backlight.h> 39 #include <linux/pwm_backlight.h>
40 #include <linux/usb/isp116x.h> 40 #include <linux/usb/isp116x.h>
41 #include <linux/mtd/mtd.h> 41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/partitions.h> 42 #include <linux/mtd/partitions.h>
43 #include <linux/mtd/physmap.h> 43 #include <linux/mtd/physmap.h>
44 44
45 #include <mach/pxa25x.h> 45 #include <mach/pxa25x.h>
46 #include <mach/audio.h> 46 #include <mach/audio.h>
47 #include <mach/pxafb.h> 47 #include <mach/pxafb.h>
48 #include <mach/i2c.h> 48 #include <mach/i2c.h>
49 #include <mach/viper.h> 49 #include <mach/viper.h>
50 50
51 #include <asm/setup.h> 51 #include <asm/setup.h>
52 #include <asm/mach-types.h> 52 #include <asm/mach-types.h>
53 #include <asm/irq.h> 53 #include <asm/irq.h>
54 #include <asm/sizes.h> 54 #include <asm/sizes.h>
55 55
56 #include <asm/mach/arch.h> 56 #include <asm/mach/arch.h>
57 #include <asm/mach/map.h> 57 #include <asm/mach/map.h>
58 #include <asm/mach/irq.h> 58 #include <asm/mach/irq.h>
59 59
60 #include "generic.h" 60 #include "generic.h"
61 #include "devices.h" 61 #include "devices.h"
62 62
63 static unsigned int icr; 63 static unsigned int icr;
64 64
65 static void viper_icr_set_bit(unsigned int bit) 65 static void viper_icr_set_bit(unsigned int bit)
66 { 66 {
67 icr |= bit; 67 icr |= bit;
68 VIPER_ICR = icr; 68 VIPER_ICR = icr;
69 } 69 }
70 70
71 static void viper_icr_clear_bit(unsigned int bit) 71 static void viper_icr_clear_bit(unsigned int bit)
72 { 72 {
73 icr &= ~bit; 73 icr &= ~bit;
74 VIPER_ICR = icr; 74 VIPER_ICR = icr;
75 } 75 }
76 76
77 /* This function is used from the pcmcia module to reset the CF */ 77 /* This function is used from the pcmcia module to reset the CF */
78 void viper_cf_rst(int state) 78 void viper_cf_rst(int state)
79 { 79 {
80 if (state) 80 if (state)
81 viper_icr_set_bit(VIPER_ICR_CF_RST); 81 viper_icr_set_bit(VIPER_ICR_CF_RST);
82 else 82 else
83 viper_icr_clear_bit(VIPER_ICR_CF_RST); 83 viper_icr_clear_bit(VIPER_ICR_CF_RST);
84 } 84 }
85 EXPORT_SYMBOL(viper_cf_rst); 85 EXPORT_SYMBOL(viper_cf_rst);
86 86
87 /* 87 /*
88 * The CPLD version register was not present on VIPER boards prior to 88 * The CPLD version register was not present on VIPER boards prior to
89 * v2i1. On v1 boards where the version register is not present we 89 * v2i1. On v1 boards where the version register is not present we
90 * will just read back the previous value from the databus. 90 * will just read back the previous value from the databus.
91 * 91 *
92 * Therefore we do two reads. The first time we write 0 to the 92 * Therefore we do two reads. The first time we write 0 to the
93 * (read-only) register before reading and the second time we write 93 * (read-only) register before reading and the second time we write
94 * 0xff first. If the two reads do not match or they read back as 0xff 94 * 0xff first. If the two reads do not match or they read back as 0xff
95 * or 0x00 then we have version 1 hardware. 95 * or 0x00 then we have version 1 hardware.
96 */ 96 */
97 static u8 viper_hw_version(void) 97 static u8 viper_hw_version(void)
98 { 98 {
99 u8 v1, v2; 99 u8 v1, v2;
100 unsigned long flags; 100 unsigned long flags;
101 101
102 local_irq_save(flags); 102 local_irq_save(flags);
103 103
104 VIPER_VERSION = 0; 104 VIPER_VERSION = 0;
105 v1 = VIPER_VERSION; 105 v1 = VIPER_VERSION;
106 VIPER_VERSION = 0xff; 106 VIPER_VERSION = 0xff;
107 v2 = VIPER_VERSION; 107 v2 = VIPER_VERSION;
108 108
109 v1 = (v1 != v2 || v1 == 0xff) ? 0 : v1; 109 v1 = (v1 != v2 || v1 == 0xff) ? 0 : v1;
110 110
111 local_irq_restore(flags); 111 local_irq_restore(flags);
112 return v1; 112 return v1;
113 } 113 }
114 114
115 /* CPU sysdev */ 115 /* CPU sysdev */
116 static int viper_cpu_suspend(struct sys_device *sysdev, pm_message_t state) 116 static int viper_cpu_suspend(struct sys_device *sysdev, pm_message_t state)
117 { 117 {
118 viper_icr_set_bit(VIPER_ICR_R_DIS); 118 viper_icr_set_bit(VIPER_ICR_R_DIS);
119 return 0; 119 return 0;
120 } 120 }
121 121
122 static int viper_cpu_resume(struct sys_device *sysdev) 122 static int viper_cpu_resume(struct sys_device *sysdev)
123 { 123 {
124 viper_icr_clear_bit(VIPER_ICR_R_DIS); 124 viper_icr_clear_bit(VIPER_ICR_R_DIS);
125 return 0; 125 return 0;
126 } 126 }
127 127
128 static struct sysdev_driver viper_cpu_sysdev_driver = { 128 static struct sysdev_driver viper_cpu_sysdev_driver = {
129 .suspend = viper_cpu_suspend, 129 .suspend = viper_cpu_suspend,
130 .resume = viper_cpu_resume, 130 .resume = viper_cpu_resume,
131 }; 131 };
132 132
133 static unsigned int current_voltage_divisor; 133 static unsigned int current_voltage_divisor;
134 134
135 /* 135 /*
136 * If force is not true then step from existing to new divisor. If 136 * If force is not true then step from existing to new divisor. If
137 * force is true then jump straight to the new divisor. Stepping is 137 * force is true then jump straight to the new divisor. Stepping is
138 * used because if the jump in voltage is too large, the VCC can dip 138 * used because if the jump in voltage is too large, the VCC can dip
139 * too low and the regulator cuts out. 139 * too low and the regulator cuts out.
140 * 140 *
141 * force can be used to initialize the divisor to a know state by 141 * force can be used to initialize the divisor to a know state by
142 * setting the value for the current clock speed, since we are already 142 * setting the value for the current clock speed, since we are already
143 * running at that speed we know the voltage should be pretty close so 143 * running at that speed we know the voltage should be pretty close so
144 * the jump won't be too large 144 * the jump won't be too large
145 */ 145 */
146 static void viper_set_core_cpu_voltage(unsigned long khz, int force) 146 static void viper_set_core_cpu_voltage(unsigned long khz, int force)
147 { 147 {
148 int i = 0; 148 int i = 0;
149 unsigned int divisor = 0; 149 unsigned int divisor = 0;
150 const char *v; 150 const char *v;
151 151
152 if (khz < 200000) { 152 if (khz < 200000) {
153 v = "1.0"; divisor = 0xfff; 153 v = "1.0"; divisor = 0xfff;
154 } else if (khz < 300000) { 154 } else if (khz < 300000) {
155 v = "1.1"; divisor = 0xde5; 155 v = "1.1"; divisor = 0xde5;
156 } else { 156 } else {
157 v = "1.3"; divisor = 0x325; 157 v = "1.3"; divisor = 0x325;
158 } 158 }
159 159
160 pr_debug("viper: setting CPU core voltage to %sV at %d.%03dMHz\n", 160 pr_debug("viper: setting CPU core voltage to %sV at %d.%03dMHz\n",
161 v, (int)khz / 1000, (int)khz % 1000); 161 v, (int)khz / 1000, (int)khz % 1000);
162 162
163 #define STEP 0x100 163 #define STEP 0x100
164 do { 164 do {
165 int step; 165 int step;
166 166
167 if (force) 167 if (force)
168 step = divisor; 168 step = divisor;
169 else if (current_voltage_divisor < divisor - STEP) 169 else if (current_voltage_divisor < divisor - STEP)
170 step = current_voltage_divisor + STEP; 170 step = current_voltage_divisor + STEP;
171 else if (current_voltage_divisor > divisor + STEP) 171 else if (current_voltage_divisor > divisor + STEP)
172 step = current_voltage_divisor - STEP; 172 step = current_voltage_divisor - STEP;
173 else 173 else
174 step = divisor; 174 step = divisor;
175 force = 0; 175 force = 0;
176 176
177 gpio_set_value(VIPER_PSU_CLK_GPIO, 0); 177 gpio_set_value(VIPER_PSU_CLK_GPIO, 0);
178 gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 0); 178 gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 0);
179 179
180 for (i = 1 << 11 ; i > 0 ; i >>= 1) { 180 for (i = 1 << 11 ; i > 0 ; i >>= 1) {
181 udelay(1); 181 udelay(1);
182 182
183 gpio_set_value(VIPER_PSU_DATA_GPIO, step & i); 183 gpio_set_value(VIPER_PSU_DATA_GPIO, step & i);
184 udelay(1); 184 udelay(1);
185 185
186 gpio_set_value(VIPER_PSU_CLK_GPIO, 1); 186 gpio_set_value(VIPER_PSU_CLK_GPIO, 1);
187 udelay(1); 187 udelay(1);
188 188
189 gpio_set_value(VIPER_PSU_CLK_GPIO, 0); 189 gpio_set_value(VIPER_PSU_CLK_GPIO, 0);
190 } 190 }
191 udelay(1); 191 udelay(1);
192 192
193 gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 1); 193 gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 1);
194 udelay(1); 194 udelay(1);
195 195
196 gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 0); 196 gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 0);
197 197
198 current_voltage_divisor = step; 198 current_voltage_divisor = step;
199 } while (current_voltage_divisor != divisor); 199 } while (current_voltage_divisor != divisor);
200 } 200 }
201 201
202 /* Interrupt handling */ 202 /* Interrupt handling */
203 static unsigned long viper_irq_enabled_mask; 203 static unsigned long viper_irq_enabled_mask;
204 static const int viper_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, 9, 14, 15 }; 204 static const int viper_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, 9, 14, 15 };
205 static const int viper_isa_irq_map[] = { 205 static const int viper_isa_irq_map[] = {
206 0, /* ISA irq #0, invalid */ 206 0, /* ISA irq #0, invalid */
207 0, /* ISA irq #1, invalid */ 207 0, /* ISA irq #1, invalid */
208 0, /* ISA irq #2, invalid */ 208 0, /* ISA irq #2, invalid */
209 1 << 0, /* ISA irq #3 */ 209 1 << 0, /* ISA irq #3 */
210 1 << 1, /* ISA irq #4 */ 210 1 << 1, /* ISA irq #4 */
211 1 << 2, /* ISA irq #5 */ 211 1 << 2, /* ISA irq #5 */
212 1 << 3, /* ISA irq #6 */ 212 1 << 3, /* ISA irq #6 */
213 1 << 4, /* ISA irq #7 */ 213 1 << 4, /* ISA irq #7 */
214 0, /* ISA irq #8, invalid */ 214 0, /* ISA irq #8, invalid */
215 1 << 8, /* ISA irq #9 */ 215 1 << 8, /* ISA irq #9 */
216 1 << 5, /* ISA irq #10 */ 216 1 << 5, /* ISA irq #10 */
217 1 << 6, /* ISA irq #11 */ 217 1 << 6, /* ISA irq #11 */
218 1 << 7, /* ISA irq #12 */ 218 1 << 7, /* ISA irq #12 */
219 0, /* ISA irq #13, invalid */ 219 0, /* ISA irq #13, invalid */
220 1 << 9, /* ISA irq #14 */ 220 1 << 9, /* ISA irq #14 */
221 1 << 10, /* ISA irq #15 */ 221 1 << 10, /* ISA irq #15 */
222 }; 222 };
223 223
224 static inline int viper_irq_to_bitmask(unsigned int irq) 224 static inline int viper_irq_to_bitmask(unsigned int irq)
225 { 225 {
226 return viper_isa_irq_map[irq - PXA_ISA_IRQ(0)]; 226 return viper_isa_irq_map[irq - PXA_ISA_IRQ(0)];
227 } 227 }
228 228
229 static inline int viper_bit_to_irq(int bit) 229 static inline int viper_bit_to_irq(int bit)
230 { 230 {
231 return viper_isa_irqs[bit] + PXA_ISA_IRQ(0); 231 return viper_isa_irqs[bit] + PXA_ISA_IRQ(0);
232 } 232 }
233 233
234 static void viper_ack_irq(unsigned int irq) 234 static void viper_ack_irq(unsigned int irq)
235 { 235 {
236 int viper_irq = viper_irq_to_bitmask(irq); 236 int viper_irq = viper_irq_to_bitmask(irq);
237 237
238 if (viper_irq & 0xff) 238 if (viper_irq & 0xff)
239 VIPER_LO_IRQ_STATUS = viper_irq; 239 VIPER_LO_IRQ_STATUS = viper_irq;
240 else 240 else
241 VIPER_HI_IRQ_STATUS = (viper_irq >> 8); 241 VIPER_HI_IRQ_STATUS = (viper_irq >> 8);
242 } 242 }
243 243
244 static void viper_mask_irq(unsigned int irq) 244 static void viper_mask_irq(unsigned int irq)
245 { 245 {
246 viper_irq_enabled_mask &= ~(viper_irq_to_bitmask(irq)); 246 viper_irq_enabled_mask &= ~(viper_irq_to_bitmask(irq));
247 } 247 }
248 248
249 static void viper_unmask_irq(unsigned int irq) 249 static void viper_unmask_irq(unsigned int irq)
250 { 250 {
251 viper_irq_enabled_mask |= viper_irq_to_bitmask(irq); 251 viper_irq_enabled_mask |= viper_irq_to_bitmask(irq);
252 } 252 }
253 253
254 static inline unsigned long viper_irq_pending(void) 254 static inline unsigned long viper_irq_pending(void)
255 { 255 {
256 return (VIPER_HI_IRQ_STATUS << 8 | VIPER_LO_IRQ_STATUS) & 256 return (VIPER_HI_IRQ_STATUS << 8 | VIPER_LO_IRQ_STATUS) &
257 viper_irq_enabled_mask; 257 viper_irq_enabled_mask;
258 } 258 }
259 259
260 static void viper_irq_handler(unsigned int irq, struct irq_desc *desc) 260 static void viper_irq_handler(unsigned int irq, struct irq_desc *desc)
261 { 261 {
262 unsigned long pending; 262 unsigned long pending;
263 263
264 pending = viper_irq_pending(); 264 pending = viper_irq_pending();
265 do { 265 do {
266 /* we're in a chained irq handler, 266 /* we're in a chained irq handler,
267 * so ack the interrupt by hand */ 267 * so ack the interrupt by hand */
268 GEDR(VIPER_CPLD_GPIO) = GPIO_bit(VIPER_CPLD_GPIO); 268 GEDR(VIPER_CPLD_GPIO) = GPIO_bit(VIPER_CPLD_GPIO);
269 269
270 if (likely(pending)) { 270 if (likely(pending)) {
271 irq = viper_bit_to_irq(__ffs(pending)); 271 irq = viper_bit_to_irq(__ffs(pending));
272 generic_handle_irq(irq); 272 generic_handle_irq(irq);
273 } 273 }
274 pending = viper_irq_pending(); 274 pending = viper_irq_pending();
275 } while (pending); 275 } while (pending);
276 } 276 }
277 277
278 static struct irq_chip viper_irq_chip = { 278 static struct irq_chip viper_irq_chip = {
279 .name = "ISA", 279 .name = "ISA",
280 .ack = viper_ack_irq, 280 .ack = viper_ack_irq,
281 .mask = viper_mask_irq, 281 .mask = viper_mask_irq,
282 .unmask = viper_unmask_irq 282 .unmask = viper_unmask_irq
283 }; 283 };
284 284
285 static void __init viper_init_irq(void) 285 static void __init viper_init_irq(void)
286 { 286 {
287 int level; 287 int level;
288 int isa_irq; 288 int isa_irq;
289 289
290 pxa25x_init_irq(); 290 pxa25x_init_irq();
291 291
292 /* setup ISA IRQs */ 292 /* setup ISA IRQs */
293 for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) { 293 for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) {
294 isa_irq = viper_bit_to_irq(level); 294 isa_irq = viper_bit_to_irq(level);
295 set_irq_chip(isa_irq, &viper_irq_chip); 295 set_irq_chip(isa_irq, &viper_irq_chip);
296 set_irq_handler(isa_irq, handle_edge_irq); 296 set_irq_handler(isa_irq, handle_edge_irq);
297 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); 297 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
298 } 298 }
299 299
300 set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), 300 set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
301 viper_irq_handler); 301 viper_irq_handler);
302 set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); 302 set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
303 303
304 #ifndef CONFIG_SERIAL_PXA 304 #ifndef CONFIG_SERIAL_PXA
305 /* 305 /*
306 * 8250 doesn't support IRQ_TYPE being passed as part 306 * 8250 doesn't support IRQ_TYPE being passed as part
307 * of the plat_serial8250_port structure... 307 * of the plat_serial8250_port structure...
308 */ 308 */
309 set_irq_type(gpio_to_irq(VIPER_UARTA_GPIO), IRQ_TYPE_EDGE_RISING); 309 set_irq_type(gpio_to_irq(VIPER_UARTA_GPIO), IRQ_TYPE_EDGE_RISING);
310 set_irq_type(gpio_to_irq(VIPER_UARTB_GPIO), IRQ_TYPE_EDGE_RISING); 310 set_irq_type(gpio_to_irq(VIPER_UARTB_GPIO), IRQ_TYPE_EDGE_RISING);
311 #endif 311 #endif
312 } 312 }
313 313
314 /* Flat Panel */ 314 /* Flat Panel */
315 static struct pxafb_mode_info fb_mode_info[] = { 315 static struct pxafb_mode_info fb_mode_info[] = {
316 { 316 {
317 .pixclock = 157500, 317 .pixclock = 157500,
318 318
319 .xres = 320, 319 .xres = 320,
320 .yres = 240, 320 .yres = 240,
321 321
322 .bpp = 16, 322 .bpp = 16,
323 323
324 .hsync_len = 63, 324 .hsync_len = 63,
325 .left_margin = 7, 325 .left_margin = 7,
326 .right_margin = 13, 326 .right_margin = 13,
327 327
328 .vsync_len = 20, 328 .vsync_len = 20,
329 .upper_margin = 0, 329 .upper_margin = 0,
330 .lower_margin = 0, 330 .lower_margin = 0,
331 331
332 .sync = 0, 332 .sync = 0,
333 }, 333 },
334 }; 334 };
335 335
336 static struct pxafb_mach_info fb_info = { 336 static struct pxafb_mach_info fb_info = {
337 .modes = fb_mode_info, 337 .modes = fb_mode_info,
338 .num_modes = 1, 338 .num_modes = 1,
339 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, 339 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
340 }; 340 };
341 341
342 static int viper_backlight_init(struct device *dev) 342 static int viper_backlight_init(struct device *dev)
343 { 343 {
344 int ret; 344 int ret;
345 345
346 /* GPIO9 and 10 control FB backlight. Initialise to off */ 346 /* GPIO9 and 10 control FB backlight. Initialise to off */
347 ret = gpio_request(VIPER_BCKLIGHT_EN_GPIO, "Backlight"); 347 ret = gpio_request(VIPER_BCKLIGHT_EN_GPIO, "Backlight");
348 if (ret) 348 if (ret)
349 goto err_request_bckl; 349 goto err_request_bckl;
350 350
351 ret = gpio_request(VIPER_LCD_EN_GPIO, "LCD"); 351 ret = gpio_request(VIPER_LCD_EN_GPIO, "LCD");
352 if (ret) 352 if (ret)
353 goto err_request_lcd; 353 goto err_request_lcd;
354 354
355 ret = gpio_direction_output(VIPER_BCKLIGHT_EN_GPIO, 0); 355 ret = gpio_direction_output(VIPER_BCKLIGHT_EN_GPIO, 0);
356 if (ret) 356 if (ret)
357 goto err_dir; 357 goto err_dir;
358 358
359 ret = gpio_direction_output(VIPER_LCD_EN_GPIO, 0); 359 ret = gpio_direction_output(VIPER_LCD_EN_GPIO, 0);
360 if (ret) 360 if (ret)
361 goto err_dir; 361 goto err_dir;
362 362
363 return 0; 363 return 0;
364 364
365 err_dir: 365 err_dir:
366 gpio_free(VIPER_LCD_EN_GPIO); 366 gpio_free(VIPER_LCD_EN_GPIO);
367 err_request_lcd: 367 err_request_lcd:
368 gpio_free(VIPER_BCKLIGHT_EN_GPIO); 368 gpio_free(VIPER_BCKLIGHT_EN_GPIO);
369 err_request_bckl: 369 err_request_bckl:
370 dev_err(dev, "Failed to setup LCD GPIOs\n"); 370 dev_err(dev, "Failed to setup LCD GPIOs\n");
371 371
372 return ret; 372 return ret;
373 } 373 }
374 374
375 static int viper_backlight_notify(int brightness) 375 static int viper_backlight_notify(int brightness)
376 { 376 {
377 gpio_set_value(VIPER_LCD_EN_GPIO, !!brightness); 377 gpio_set_value(VIPER_LCD_EN_GPIO, !!brightness);
378 gpio_set_value(VIPER_BCKLIGHT_EN_GPIO, !!brightness); 378 gpio_set_value(VIPER_BCKLIGHT_EN_GPIO, !!brightness);
379 379
380 return brightness; 380 return brightness;
381 } 381 }
382 382
383 static void viper_backlight_exit(struct device *dev) 383 static void viper_backlight_exit(struct device *dev)
384 { 384 {
385 gpio_free(VIPER_LCD_EN_GPIO); 385 gpio_free(VIPER_LCD_EN_GPIO);
386 gpio_free(VIPER_BCKLIGHT_EN_GPIO); 386 gpio_free(VIPER_BCKLIGHT_EN_GPIO);
387 } 387 }
388 388
389 static struct platform_pwm_backlight_data viper_backlight_data = { 389 static struct platform_pwm_backlight_data viper_backlight_data = {
390 .pwm_id = 0, 390 .pwm_id = 0,
391 .max_brightness = 100, 391 .max_brightness = 100,
392 .dft_brightness = 100, 392 .dft_brightness = 100,
393 .pwm_period_ns = 1000000, 393 .pwm_period_ns = 1000000,
394 .init = viper_backlight_init, 394 .init = viper_backlight_init,
395 .notify = viper_backlight_notify, 395 .notify = viper_backlight_notify,
396 .exit = viper_backlight_exit, 396 .exit = viper_backlight_exit,
397 }; 397 };
398 398
399 static struct platform_device viper_backlight_device = { 399 static struct platform_device viper_backlight_device = {
400 .name = "pwm-backlight", 400 .name = "pwm-backlight",
401 .dev = { 401 .dev = {
402 .parent = &pxa25x_device_pwm0.dev, 402 .parent = &pxa25x_device_pwm0.dev,
403 .platform_data = &viper_backlight_data, 403 .platform_data = &viper_backlight_data,
404 }, 404 },
405 }; 405 };
406 406
407 /* Ethernet */ 407 /* Ethernet */
408 static struct resource smc91x_resources[] = { 408 static struct resource smc91x_resources[] = {
409 [0] = { 409 [0] = {
410 .name = "smc91x-regs", 410 .name = "smc91x-regs",
411 .start = VIPER_ETH_PHYS + 0x300, 411 .start = VIPER_ETH_PHYS + 0x300,
412 .end = VIPER_ETH_PHYS + 0x30f, 412 .end = VIPER_ETH_PHYS + 0x30f,
413 .flags = IORESOURCE_MEM, 413 .flags = IORESOURCE_MEM,
414 }, 414 },
415 [1] = { 415 [1] = {
416 .start = gpio_to_irq(VIPER_ETH_GPIO), 416 .start = gpio_to_irq(VIPER_ETH_GPIO),
417 .end = gpio_to_irq(VIPER_ETH_GPIO), 417 .end = gpio_to_irq(VIPER_ETH_GPIO),
418 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, 418 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
419 }, 419 },
420 [2] = { 420 [2] = {
421 .name = "smc91x-data32", 421 .name = "smc91x-data32",
422 .start = VIPER_ETH_DATA_PHYS, 422 .start = VIPER_ETH_DATA_PHYS,
423 .end = VIPER_ETH_DATA_PHYS + 3, 423 .end = VIPER_ETH_DATA_PHYS + 3,
424 .flags = IORESOURCE_MEM, 424 .flags = IORESOURCE_MEM,
425 }, 425 },
426 }; 426 };
427 427
428 static struct smc91x_platdata viper_smc91x_info = { 428 static struct smc91x_platdata viper_smc91x_info = {
429 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, 429 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
430 .leda = RPC_LED_100_10, 430 .leda = RPC_LED_100_10,
431 .ledb = RPC_LED_TX_RX, 431 .ledb = RPC_LED_TX_RX,
432 }; 432 };
433 433
434 static struct platform_device smc91x_device = { 434 static struct platform_device smc91x_device = {
435 .name = "smc91x", 435 .name = "smc91x",
436 .id = -1, 436 .id = -1,
437 .num_resources = ARRAY_SIZE(smc91x_resources), 437 .num_resources = ARRAY_SIZE(smc91x_resources),
438 .resource = smc91x_resources, 438 .resource = smc91x_resources,
439 .dev = { 439 .dev = {
440 .platform_data = &viper_smc91x_info, 440 .platform_data = &viper_smc91x_info,
441 }, 441 },
442 }; 442 };
443 443
444 /* i2c */ 444 /* i2c */
445 static struct i2c_gpio_platform_data i2c_bus_data = { 445 static struct i2c_gpio_platform_data i2c_bus_data = {
446 .sda_pin = VIPER_RTC_I2C_SDA_GPIO, 446 .sda_pin = VIPER_RTC_I2C_SDA_GPIO,
447 .scl_pin = VIPER_RTC_I2C_SCL_GPIO, 447 .scl_pin = VIPER_RTC_I2C_SCL_GPIO,
448 .udelay = 10, 448 .udelay = 10,
449 .timeout = 100, 449 .timeout = 100,
450 }; 450 };
451 451
452 static struct platform_device i2c_bus_device = { 452 static struct platform_device i2c_bus_device = {
453 .name = "i2c-gpio", 453 .name = "i2c-gpio",
454 .id = 1, /* pxa2xx-i2c is bus 0, so start at 1 */ 454 .id = 1, /* pxa2xx-i2c is bus 0, so start at 1 */
455 .dev = { 455 .dev = {
456 .platform_data = &i2c_bus_data, 456 .platform_data = &i2c_bus_data,
457 } 457 }
458 }; 458 };
459 459
460 static struct i2c_board_info __initdata viper_i2c_devices[] = { 460 static struct i2c_board_info __initdata viper_i2c_devices[] = {
461 { 461 {
462 I2C_BOARD_INFO("ds1338", 0x68), 462 I2C_BOARD_INFO("ds1338", 0x68),
463 }, 463 },
464 }; 464 };
465 465
466 /* 466 /*
467 * Serial configuration: 467 * Serial configuration:
468 * You can either have the standard PXA ports driven by the PXA driver, 468 * You can either have the standard PXA ports driven by the PXA driver,
469 * or all the ports (PXA + 16850) driven by the 8250 driver. 469 * or all the ports (PXA + 16850) driven by the 8250 driver.
470 * Choose your poison. 470 * Choose your poison.
471 */ 471 */
472 472
473 static struct resource viper_serial_resources[] = { 473 static struct resource viper_serial_resources[] = {
474 #ifndef CONFIG_SERIAL_PXA 474 #ifndef CONFIG_SERIAL_PXA
475 { 475 {
476 .start = 0x40100000, 476 .start = 0x40100000,
477 .end = 0x4010001f, 477 .end = 0x4010001f,
478 .flags = IORESOURCE_MEM, 478 .flags = IORESOURCE_MEM,
479 }, 479 },
480 { 480 {
481 .start = 0x40200000, 481 .start = 0x40200000,
482 .end = 0x4020001f, 482 .end = 0x4020001f,
483 .flags = IORESOURCE_MEM, 483 .flags = IORESOURCE_MEM,
484 }, 484 },
485 { 485 {
486 .start = 0x40700000, 486 .start = 0x40700000,
487 .end = 0x4070001f, 487 .end = 0x4070001f,
488 .flags = IORESOURCE_MEM, 488 .flags = IORESOURCE_MEM,
489 }, 489 },
490 { 490 {
491 .start = VIPER_UARTA_PHYS, 491 .start = VIPER_UARTA_PHYS,
492 .end = VIPER_UARTA_PHYS + 0xf, 492 .end = VIPER_UARTA_PHYS + 0xf,
493 .flags = IORESOURCE_MEM, 493 .flags = IORESOURCE_MEM,
494 }, 494 },
495 { 495 {
496 .start = VIPER_UARTB_PHYS, 496 .start = VIPER_UARTB_PHYS,
497 .end = VIPER_UARTB_PHYS + 0xf, 497 .end = VIPER_UARTB_PHYS + 0xf,
498 .flags = IORESOURCE_MEM, 498 .flags = IORESOURCE_MEM,
499 }, 499 },
500 #else 500 #else
501 { 501 {
502 0, 502 0,
503 }, 503 },
504 #endif 504 #endif
505 }; 505 };
506 506
507 static struct plat_serial8250_port serial_platform_data[] = { 507 static struct plat_serial8250_port serial_platform_data[] = {
508 #ifndef CONFIG_SERIAL_PXA 508 #ifndef CONFIG_SERIAL_PXA
509 /* Internal UARTs */ 509 /* Internal UARTs */
510 { 510 {
511 .membase = (void *)&FFUART, 511 .membase = (void *)&FFUART,
512 .mapbase = __PREG(FFUART), 512 .mapbase = __PREG(FFUART),
513 .irq = IRQ_FFUART, 513 .irq = IRQ_FFUART,
514 .uartclk = 921600 * 16, 514 .uartclk = 921600 * 16,
515 .regshift = 2, 515 .regshift = 2,
516 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 516 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
517 .iotype = UPIO_MEM, 517 .iotype = UPIO_MEM,
518 }, 518 },
519 { 519 {
520 .membase = (void *)&BTUART, 520 .membase = (void *)&BTUART,
521 .mapbase = __PREG(BTUART), 521 .mapbase = __PREG(BTUART),
522 .irq = IRQ_BTUART, 522 .irq = IRQ_BTUART,
523 .uartclk = 921600 * 16, 523 .uartclk = 921600 * 16,
524 .regshift = 2, 524 .regshift = 2,
525 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 525 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
526 .iotype = UPIO_MEM, 526 .iotype = UPIO_MEM,
527 }, 527 },
528 { 528 {
529 .membase = (void *)&STUART, 529 .membase = (void *)&STUART,
530 .mapbase = __PREG(STUART), 530 .mapbase = __PREG(STUART),
531 .irq = IRQ_STUART, 531 .irq = IRQ_STUART,
532 .uartclk = 921600 * 16, 532 .uartclk = 921600 * 16,
533 .regshift = 2, 533 .regshift = 2,
534 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 534 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
535 .iotype = UPIO_MEM, 535 .iotype = UPIO_MEM,
536 }, 536 },
537 /* External UARTs */ 537 /* External UARTs */
538 { 538 {
539 .mapbase = VIPER_UARTA_PHYS, 539 .mapbase = VIPER_UARTA_PHYS,
540 .irq = gpio_to_irq(VIPER_UARTA_GPIO), 540 .irq = gpio_to_irq(VIPER_UARTA_GPIO),
541 .uartclk = 1843200, 541 .uartclk = 1843200,
542 .regshift = 1, 542 .regshift = 1,
543 .iotype = UPIO_MEM, 543 .iotype = UPIO_MEM,
544 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | 544 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP |
545 UPF_SKIP_TEST, 545 UPF_SKIP_TEST,
546 }, 546 },
547 { 547 {
548 .mapbase = VIPER_UARTB_PHYS, 548 .mapbase = VIPER_UARTB_PHYS,
549 .irq = gpio_to_irq(VIPER_UARTB_GPIO), 549 .irq = gpio_to_irq(VIPER_UARTB_GPIO),
550 .uartclk = 1843200, 550 .uartclk = 1843200,
551 .regshift = 1, 551 .regshift = 1,
552 .iotype = UPIO_MEM, 552 .iotype = UPIO_MEM,
553 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | 553 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP |
554 UPF_SKIP_TEST, 554 UPF_SKIP_TEST,
555 }, 555 },
556 #endif 556 #endif
557 { }, 557 { },
558 }; 558 };
559 559
560 static struct platform_device serial_device = { 560 static struct platform_device serial_device = {
561 .name = "serial8250", 561 .name = "serial8250",
562 .id = 0, 562 .id = 0,
563 .dev = { 563 .dev = {
564 .platform_data = serial_platform_data, 564 .platform_data = serial_platform_data,
565 }, 565 },
566 .num_resources = ARRAY_SIZE(viper_serial_resources), 566 .num_resources = ARRAY_SIZE(viper_serial_resources),
567 .resource = viper_serial_resources, 567 .resource = viper_serial_resources,
568 }; 568 };
569 569
570 /* USB */ 570 /* USB */
571 static void isp116x_delay(struct device *dev, int delay) 571 static void isp116x_delay(struct device *dev, int delay)
572 { 572 {
573 ndelay(delay); 573 ndelay(delay);
574 } 574 }
575 575
576 static struct resource isp116x_resources[] = { 576 static struct resource isp116x_resources[] = {
577 [0] = { /* DATA */ 577 [0] = { /* DATA */
578 .start = VIPER_USB_PHYS + 0, 578 .start = VIPER_USB_PHYS + 0,
579 .end = VIPER_USB_PHYS + 1, 579 .end = VIPER_USB_PHYS + 1,
580 .flags = IORESOURCE_MEM, 580 .flags = IORESOURCE_MEM,
581 }, 581 },
582 [1] = { /* ADDR */ 582 [1] = { /* ADDR */
583 .start = VIPER_USB_PHYS + 2, 583 .start = VIPER_USB_PHYS + 2,
584 .end = VIPER_USB_PHYS + 3, 584 .end = VIPER_USB_PHYS + 3,
585 .flags = IORESOURCE_MEM, 585 .flags = IORESOURCE_MEM,
586 }, 586 },
587 [2] = { 587 [2] = {
588 .start = gpio_to_irq(VIPER_USB_GPIO), 588 .start = gpio_to_irq(VIPER_USB_GPIO),
589 .end = gpio_to_irq(VIPER_USB_GPIO), 589 .end = gpio_to_irq(VIPER_USB_GPIO),
590 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, 590 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
591 }, 591 },
592 }; 592 };
593 593
594 /* (DataBusWidth16|AnalogOCEnable|DREQOutputPolarity|DownstreamPort15KRSel ) */ 594 /* (DataBusWidth16|AnalogOCEnable|DREQOutputPolarity|DownstreamPort15KRSel ) */
595 static struct isp116x_platform_data isp116x_platform_data = { 595 static struct isp116x_platform_data isp116x_platform_data = {
596 /* Enable internal resistors on downstream ports */ 596 /* Enable internal resistors on downstream ports */
597 .sel15Kres = 1, 597 .sel15Kres = 1,
598 /* On-chip overcurrent protection */ 598 /* On-chip overcurrent protection */
599 .oc_enable = 1, 599 .oc_enable = 1,
600 /* INT output polarity */ 600 /* INT output polarity */
601 .int_act_high = 1, 601 .int_act_high = 1,
602 /* INT edge or level triggered */ 602 /* INT edge or level triggered */
603 .int_edge_triggered = 0, 603 .int_edge_triggered = 0,
604 604
605 /* WAKEUP pin connected - NOT SUPPORTED */ 605 /* WAKEUP pin connected - NOT SUPPORTED */
606 /* .remote_wakeup_connected = 0, */ 606 /* .remote_wakeup_connected = 0, */
607 /* Wakeup by devices on usb bus enabled */ 607 /* Wakeup by devices on usb bus enabled */
608 .remote_wakeup_enable = 0, 608 .remote_wakeup_enable = 0,
609 .delay = isp116x_delay, 609 .delay = isp116x_delay,
610 }; 610 };
611 611
612 static struct platform_device isp116x_device = { 612 static struct platform_device isp116x_device = {
613 .name = "isp116x-hcd", 613 .name = "isp116x-hcd",
614 .id = -1, 614 .id = -1,
615 .num_resources = ARRAY_SIZE(isp116x_resources), 615 .num_resources = ARRAY_SIZE(isp116x_resources),
616 .resource = isp116x_resources, 616 .resource = isp116x_resources,
617 .dev = { 617 .dev = {
618 .platform_data = &isp116x_platform_data, 618 .platform_data = &isp116x_platform_data,
619 }, 619 },
620 620
621 }; 621 };
622 622
623 /* MTD */ 623 /* MTD */
624 static struct resource mtd_resources[] = { 624 static struct resource mtd_resources[] = {
625 [0] = { /* RedBoot config + filesystem flash */ 625 [0] = { /* RedBoot config + filesystem flash */
626 .start = VIPER_FLASH_PHYS, 626 .start = VIPER_FLASH_PHYS,
627 .end = VIPER_FLASH_PHYS + SZ_32M - 1, 627 .end = VIPER_FLASH_PHYS + SZ_32M - 1,
628 .flags = IORESOURCE_MEM, 628 .flags = IORESOURCE_MEM,
629 }, 629 },
630 [1] = { /* Boot flash */ 630 [1] = { /* Boot flash */
631 .start = VIPER_BOOT_PHYS, 631 .start = VIPER_BOOT_PHYS,
632 .end = VIPER_BOOT_PHYS + SZ_1M - 1, 632 .end = VIPER_BOOT_PHYS + SZ_1M - 1,
633 .flags = IORESOURCE_MEM, 633 .flags = IORESOURCE_MEM,
634 }, 634 },
635 [2] = { /* 635 [2] = { /*
636 * SRAM size is actually 256KB, 8bits, with a sparse mapping 636 * SRAM size is actually 256KB, 8bits, with a sparse mapping
637 * (each byte is on a 16bit boundary). 637 * (each byte is on a 16bit boundary).
638 */ 638 */
639 .start = _VIPER_SRAM_BASE, 639 .start = _VIPER_SRAM_BASE,
640 .end = _VIPER_SRAM_BASE + SZ_512K - 1, 640 .end = _VIPER_SRAM_BASE + SZ_512K - 1,
641 .flags = IORESOURCE_MEM, 641 .flags = IORESOURCE_MEM,
642 }, 642 },
643 }; 643 };
644 644
645 static struct mtd_partition viper_boot_flash_partition = { 645 static struct mtd_partition viper_boot_flash_partition = {
646 .name = "RedBoot", 646 .name = "RedBoot",
647 .size = SZ_1M, 647 .size = SZ_1M,
648 .offset = 0, 648 .offset = 0,
649 .mask_flags = MTD_WRITEABLE, /* force R/O */ 649 .mask_flags = MTD_WRITEABLE, /* force R/O */
650 }; 650 };
651 651
652 static struct physmap_flash_data viper_flash_data[] = { 652 static struct physmap_flash_data viper_flash_data[] = {
653 [0] = { 653 [0] = {
654 .width = 2, 654 .width = 2,
655 .parts = NULL, 655 .parts = NULL,
656 .nr_parts = 0, 656 .nr_parts = 0,
657 }, 657 },
658 [1] = { 658 [1] = {
659 .width = 2, 659 .width = 2,
660 .parts = &viper_boot_flash_partition, 660 .parts = &viper_boot_flash_partition,
661 .nr_parts = 1, 661 .nr_parts = 1,
662 }, 662 },
663 }; 663 };
664 664
665 static struct platform_device viper_mtd_devices[] = { 665 static struct platform_device viper_mtd_devices[] = {
666 [0] = { 666 [0] = {
667 .name = "physmap-flash", 667 .name = "physmap-flash",
668 .id = 0, 668 .id = 0,
669 .dev = { 669 .dev = {
670 .platform_data = &viper_flash_data[0], 670 .platform_data = &viper_flash_data[0],
671 }, 671 },
672 .resource = &mtd_resources[0], 672 .resource = &mtd_resources[0],
673 .num_resources = 1, 673 .num_resources = 1,
674 }, 674 },
675 [1] = { 675 [1] = {
676 .name = "physmap-flash", 676 .name = "physmap-flash",
677 .id = 1, 677 .id = 1,
678 .dev = { 678 .dev = {
679 .platform_data = &viper_flash_data[1], 679 .platform_data = &viper_flash_data[1],
680 }, 680 },
681 .resource = &mtd_resources[1], 681 .resource = &mtd_resources[1],
682 .num_resources = 1, 682 .num_resources = 1,
683 }, 683 },
684 }; 684 };
685 685
686 static struct platform_device *viper_devs[] __initdata = { 686 static struct platform_device *viper_devs[] __initdata = {
687 &smc91x_device, 687 &smc91x_device,
688 &i2c_bus_device, 688 &i2c_bus_device,
689 &serial_device, 689 &serial_device,
690 &isp116x_device, 690 &isp116x_device,
691 &viper_mtd_devices[0], 691 &viper_mtd_devices[0],
692 &viper_mtd_devices[1], 692 &viper_mtd_devices[1],
693 &viper_backlight_device, 693 &viper_backlight_device,
694 }; 694 };
695 695
696 static mfp_cfg_t viper_pin_config[] __initdata = { 696 static mfp_cfg_t viper_pin_config[] __initdata = {
697 /* Chip selects */ 697 /* Chip selects */
698 GPIO15_nCS_1, 698 GPIO15_nCS_1,
699 GPIO78_nCS_2, 699 GPIO78_nCS_2,
700 GPIO79_nCS_3, 700 GPIO79_nCS_3,
701 GPIO80_nCS_4, 701 GPIO80_nCS_4,
702 GPIO33_nCS_5, 702 GPIO33_nCS_5,
703 703
704 /* FP Backlight */ 704 /* FP Backlight */
705 GPIO9_GPIO, /* VIPER_BCKLIGHT_EN_GPIO */ 705 GPIO9_GPIO, /* VIPER_BCKLIGHT_EN_GPIO */
706 GPIO10_GPIO, /* VIPER_LCD_EN_GPIO */ 706 GPIO10_GPIO, /* VIPER_LCD_EN_GPIO */
707 GPIO16_PWM0_OUT, 707 GPIO16_PWM0_OUT,
708 708
709 /* Ethernet PHY Ready */ 709 /* Ethernet PHY Ready */
710 GPIO18_RDY, 710 GPIO18_RDY,
711 711
712 /* Serial shutdown */ 712 /* Serial shutdown */
713 GPIO12_GPIO | MFP_LPM_DRIVE_HIGH, /* VIPER_UART_SHDN_GPIO */ 713 GPIO12_GPIO | MFP_LPM_DRIVE_HIGH, /* VIPER_UART_SHDN_GPIO */
714 714
715 /* Compact-Flash / PC104 */ 715 /* Compact-Flash / PC104 */
716 GPIO48_nPOE, 716 GPIO48_nPOE,
717 GPIO49_nPWE, 717 GPIO49_nPWE,
718 GPIO50_nPIOR, 718 GPIO50_nPIOR,
719 GPIO51_nPIOW, 719 GPIO51_nPIOW,
720 GPIO52_nPCE_1, 720 GPIO52_nPCE_1,
721 GPIO53_nPCE_2, 721 GPIO53_nPCE_2,
722 GPIO54_nPSKTSEL, 722 GPIO54_nPSKTSEL,
723 GPIO55_nPREG, 723 GPIO55_nPREG,
724 GPIO56_nPWAIT, 724 GPIO56_nPWAIT,
725 GPIO57_nIOIS16, 725 GPIO57_nIOIS16,
726 GPIO8_GPIO, /* VIPER_CF_RDY_GPIO */ 726 GPIO8_GPIO, /* VIPER_CF_RDY_GPIO */
727 GPIO32_GPIO, /* VIPER_CF_CD_GPIO */ 727 GPIO32_GPIO, /* VIPER_CF_CD_GPIO */
728 GPIO82_GPIO, /* VIPER_CF_POWER_GPIO */ 728 GPIO82_GPIO, /* VIPER_CF_POWER_GPIO */
729 729
730 /* Integrated UPS control */ 730 /* Integrated UPS control */
731 GPIO20_GPIO, /* VIPER_UPS_GPIO */ 731 GPIO20_GPIO, /* VIPER_UPS_GPIO */
732 732
733 /* Vcc regulator control */ 733 /* Vcc regulator control */
734 GPIO6_GPIO, /* VIPER_PSU_DATA_GPIO */ 734 GPIO6_GPIO, /* VIPER_PSU_DATA_GPIO */
735 GPIO11_GPIO, /* VIPER_PSU_CLK_GPIO */ 735 GPIO11_GPIO, /* VIPER_PSU_CLK_GPIO */
736 GPIO19_GPIO, /* VIPER_PSU_nCS_LD_GPIO */ 736 GPIO19_GPIO, /* VIPER_PSU_nCS_LD_GPIO */
737 737
738 /* i2c busses */ 738 /* i2c busses */
739 GPIO26_GPIO, /* VIPER_TPM_I2C_SDA_GPIO */ 739 GPIO26_GPIO, /* VIPER_TPM_I2C_SDA_GPIO */
740 GPIO27_GPIO, /* VIPER_TPM_I2C_SCL_GPIO */ 740 GPIO27_GPIO, /* VIPER_TPM_I2C_SCL_GPIO */
741 GPIO83_GPIO, /* VIPER_RTC_I2C_SDA_GPIO */ 741 GPIO83_GPIO, /* VIPER_RTC_I2C_SDA_GPIO */
742 GPIO84_GPIO, /* VIPER_RTC_I2C_SCL_GPIO */ 742 GPIO84_GPIO, /* VIPER_RTC_I2C_SCL_GPIO */
743 743
744 /* PC/104 Interrupt */ 744 /* PC/104 Interrupt */
745 GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, /* VIPER_CPLD_GPIO */ 745 GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, /* VIPER_CPLD_GPIO */
746 }; 746 };
747 747
748 static unsigned long viper_tpm; 748 static unsigned long viper_tpm;
749 749
750 static int __init viper_tpm_setup(char *str) 750 static int __init viper_tpm_setup(char *str)
751 { 751 {
752 strict_strtoul(str, 10, &viper_tpm); 752 strict_strtoul(str, 10, &viper_tpm);
753 return 1; 753 return 1;
754 } 754 }
755 755
756 __setup("tpm=", viper_tpm_setup); 756 __setup("tpm=", viper_tpm_setup);
757 757
758 static void __init viper_tpm_init(void) 758 static void __init viper_tpm_init(void)
759 { 759 {
760 struct platform_device *tpm_device; 760 struct platform_device *tpm_device;
761 struct i2c_gpio_platform_data i2c_tpm_data = { 761 struct i2c_gpio_platform_data i2c_tpm_data = {
762 .sda_pin = VIPER_TPM_I2C_SDA_GPIO, 762 .sda_pin = VIPER_TPM_I2C_SDA_GPIO,
763 .scl_pin = VIPER_TPM_I2C_SCL_GPIO, 763 .scl_pin = VIPER_TPM_I2C_SCL_GPIO,
764 .udelay = 10, 764 .udelay = 10,
765 .timeout = 100, 765 .timeout = 100,
766 }; 766 };
767 char *errstr; 767 char *errstr;
768 768
769 /* Allocate TPM i2c bus if requested */ 769 /* Allocate TPM i2c bus if requested */
770 if (!viper_tpm) 770 if (!viper_tpm)
771 return; 771 return;
772 772
773 tpm_device = platform_device_alloc("i2c-gpio", 2); 773 tpm_device = platform_device_alloc("i2c-gpio", 2);
774 if (tpm_device) { 774 if (tpm_device) {
775 if (!platform_device_add_data(tpm_device, 775 if (!platform_device_add_data(tpm_device,
776 &i2c_tpm_data, 776 &i2c_tpm_data,
777 sizeof(i2c_tpm_data))) { 777 sizeof(i2c_tpm_data))) {
778 if (platform_device_add(tpm_device)) { 778 if (platform_device_add(tpm_device)) {
779 errstr = "register TPM i2c bus"; 779 errstr = "register TPM i2c bus";
780 goto error_free_tpm; 780 goto error_free_tpm;
781 } 781 }
782 } else { 782 } else {
783 errstr = "allocate TPM i2c bus data"; 783 errstr = "allocate TPM i2c bus data";
784 goto error_free_tpm; 784 goto error_free_tpm;
785 } 785 }
786 } else { 786 } else {
787 errstr = "allocate TPM i2c device"; 787 errstr = "allocate TPM i2c device";
788 goto error_tpm; 788 goto error_tpm;
789 } 789 }
790 790
791 return; 791 return;
792 792
793 error_free_tpm: 793 error_free_tpm:
794 kfree(tpm_device); 794 kfree(tpm_device);
795 error_tpm: 795 error_tpm:
796 pr_err("viper: Couldn't %s, giving up\n", errstr); 796 pr_err("viper: Couldn't %s, giving up\n", errstr);
797 } 797 }
798 798
799 static void __init viper_init_vcore_gpios(void) 799 static void __init viper_init_vcore_gpios(void)
800 { 800 {
801 if (gpio_request(VIPER_PSU_DATA_GPIO, "PSU data")) 801 if (gpio_request(VIPER_PSU_DATA_GPIO, "PSU data"))
802 goto err_request_data; 802 goto err_request_data;
803 803
804 if (gpio_request(VIPER_PSU_CLK_GPIO, "PSU clock")) 804 if (gpio_request(VIPER_PSU_CLK_GPIO, "PSU clock"))
805 goto err_request_clk; 805 goto err_request_clk;
806 806
807 if (gpio_request(VIPER_PSU_nCS_LD_GPIO, "PSU cs")) 807 if (gpio_request(VIPER_PSU_nCS_LD_GPIO, "PSU cs"))
808 goto err_request_cs; 808 goto err_request_cs;
809 809
810 if (gpio_direction_output(VIPER_PSU_DATA_GPIO, 0) || 810 if (gpio_direction_output(VIPER_PSU_DATA_GPIO, 0) ||
811 gpio_direction_output(VIPER_PSU_CLK_GPIO, 0) || 811 gpio_direction_output(VIPER_PSU_CLK_GPIO, 0) ||
812 gpio_direction_output(VIPER_PSU_nCS_LD_GPIO, 0)) 812 gpio_direction_output(VIPER_PSU_nCS_LD_GPIO, 0))
813 goto err_dir; 813 goto err_dir;
814 814
815 /* c/should assume redboot set the correct level ??? */ 815 /* c/should assume redboot set the correct level ??? */
816 viper_set_core_cpu_voltage(get_clk_frequency_khz(0), 1); 816 viper_set_core_cpu_voltage(get_clk_frequency_khz(0), 1);
817 817
818 return; 818 return;
819 819
820 err_dir: 820 err_dir:
821 gpio_free(VIPER_PSU_nCS_LD_GPIO); 821 gpio_free(VIPER_PSU_nCS_LD_GPIO);
822 err_request_cs: 822 err_request_cs:
823 gpio_free(VIPER_PSU_CLK_GPIO); 823 gpio_free(VIPER_PSU_CLK_GPIO);
824 err_request_clk: 824 err_request_clk:
825 gpio_free(VIPER_PSU_DATA_GPIO); 825 gpio_free(VIPER_PSU_DATA_GPIO);
826 err_request_data: 826 err_request_data:
827 pr_err("viper: Failed to setup vcore control GPIOs\n"); 827 pr_err("viper: Failed to setup vcore control GPIOs\n");
828 } 828 }
829 829
830 static void __init viper_init_serial_gpio(void) 830 static void __init viper_init_serial_gpio(void)
831 { 831 {
832 if (gpio_request(VIPER_UART_SHDN_GPIO, "UARTs shutdown")) 832 if (gpio_request(VIPER_UART_SHDN_GPIO, "UARTs shutdown"))
833 goto err_request; 833 goto err_request;
834 834
835 if (gpio_direction_output(VIPER_UART_SHDN_GPIO, 0)) 835 if (gpio_direction_output(VIPER_UART_SHDN_GPIO, 0))
836 goto err_dir; 836 goto err_dir;
837 837
838 return; 838 return;
839 839
840 err_dir: 840 err_dir:
841 gpio_free(VIPER_UART_SHDN_GPIO); 841 gpio_free(VIPER_UART_SHDN_GPIO);
842 err_request: 842 err_request:
843 pr_err("viper: Failed to setup UART shutdown GPIO\n"); 843 pr_err("viper: Failed to setup UART shutdown GPIO\n");
844 } 844 }
845 845
846 #ifdef CONFIG_CPU_FREQ 846 #ifdef CONFIG_CPU_FREQ
847 static int viper_cpufreq_notifier(struct notifier_block *nb, 847 static int viper_cpufreq_notifier(struct notifier_block *nb,
848 unsigned long val, void *data) 848 unsigned long val, void *data)
849 { 849 {
850 struct cpufreq_freqs *freq = data; 850 struct cpufreq_freqs *freq = data;
851 851
852 /* TODO: Adjust timings??? */ 852 /* TODO: Adjust timings??? */
853 853
854 switch (val) { 854 switch (val) {
855 case CPUFREQ_PRECHANGE: 855 case CPUFREQ_PRECHANGE:
856 if (freq->old < freq->new) { 856 if (freq->old < freq->new) {
857 /* we are getting faster so raise the voltage 857 /* we are getting faster so raise the voltage
858 * before we change freq */ 858 * before we change freq */
859 viper_set_core_cpu_voltage(freq->new, 0); 859 viper_set_core_cpu_voltage(freq->new, 0);
860 } 860 }
861 break; 861 break;
862 case CPUFREQ_POSTCHANGE: 862 case CPUFREQ_POSTCHANGE:
863 if (freq->old > freq->new) { 863 if (freq->old > freq->new) {
864 /* we are slowing down so drop the power 864 /* we are slowing down so drop the power
865 * after we change freq */ 865 * after we change freq */
866 viper_set_core_cpu_voltage(freq->new, 0); 866 viper_set_core_cpu_voltage(freq->new, 0);
867 } 867 }
868 break; 868 break;
869 case CPUFREQ_RESUMECHANGE: 869 case CPUFREQ_RESUMECHANGE:
870 viper_set_core_cpu_voltage(freq->new, 0); 870 viper_set_core_cpu_voltage(freq->new, 0);
871 break; 871 break;
872 default: 872 default:
873 /* ignore */ 873 /* ignore */
874 break; 874 break;
875 } 875 }
876 876
877 return 0; 877 return 0;
878 } 878 }
879 879
880 static struct notifier_block viper_cpufreq_notifier_block = { 880 static struct notifier_block viper_cpufreq_notifier_block = {
881 .notifier_call = viper_cpufreq_notifier 881 .notifier_call = viper_cpufreq_notifier
882 }; 882 };
883 883
884 static void __init viper_init_cpufreq(void) 884 static void __init viper_init_cpufreq(void)
885 { 885 {
886 if (cpufreq_register_notifier(&viper_cpufreq_notifier_block, 886 if (cpufreq_register_notifier(&viper_cpufreq_notifier_block,
887 CPUFREQ_TRANSITION_NOTIFIER)) 887 CPUFREQ_TRANSITION_NOTIFIER))
888 pr_err("viper: Failed to setup cpufreq notifier\n"); 888 pr_err("viper: Failed to setup cpufreq notifier\n");
889 } 889 }
890 #else 890 #else
891 static inline void viper_init_cpufreq(void) {} 891 static inline void viper_init_cpufreq(void) {}
892 #endif 892 #endif
893 893
894 static void viper_power_off(void) 894 static void viper_power_off(void)
895 { 895 {
896 pr_notice("Shutting off UPS\n"); 896 pr_notice("Shutting off UPS\n");
897 gpio_set_value(VIPER_UPS_GPIO, 1); 897 gpio_set_value(VIPER_UPS_GPIO, 1);
898 /* Spin to death... */ 898 /* Spin to death... */
899 while (1); 899 while (1);
900 } 900 }
901 901
902 static void __init viper_init(void) 902 static void __init viper_init(void)
903 { 903 {
904 u8 version; 904 u8 version;
905 905
906 pm_power_off = viper_power_off; 906 pm_power_off = viper_power_off;
907 907
908 pxa2xx_mfp_config(ARRAY_AND_SIZE(viper_pin_config)); 908 pxa2xx_mfp_config(ARRAY_AND_SIZE(viper_pin_config));
909 909
910 /* Wake-up serial console */ 910 /* Wake-up serial console */
911 viper_init_serial_gpio(); 911 viper_init_serial_gpio();
912 912
913 set_pxa_fb_info(&fb_info); 913 set_pxa_fb_info(&fb_info);
914 914
915 /* v1 hardware cannot use the datacs line */ 915 /* v1 hardware cannot use the datacs line */
916 version = viper_hw_version(); 916 version = viper_hw_version();
917 if (version == 0) 917 if (version == 0)
918 smc91x_device.num_resources--; 918 smc91x_device.num_resources--;
919 919
920 pxa_set_i2c_info(NULL); 920 pxa_set_i2c_info(NULL);
921 platform_add_devices(viper_devs, ARRAY_SIZE(viper_devs)); 921 platform_add_devices(viper_devs, ARRAY_SIZE(viper_devs));
922 922
923 viper_init_vcore_gpios(); 923 viper_init_vcore_gpios();
924 viper_init_cpufreq(); 924 viper_init_cpufreq();
925 925
926 sysdev_driver_register(&cpu_sysdev_class, &viper_cpu_sysdev_driver); 926 sysdev_driver_register(&cpu_sysdev_class, &viper_cpu_sysdev_driver);
927 927
928 if (version) { 928 if (version) {
929 pr_info("viper: hardware v%di%d detected. " 929 pr_info("viper: hardware v%di%d detected. "
930 "CPLD revision %d.\n", 930 "CPLD revision %d.\n",
931 VIPER_BOARD_VERSION(version), 931 VIPER_BOARD_VERSION(version),
932 VIPER_BOARD_ISSUE(version), 932 VIPER_BOARD_ISSUE(version),
933 VIPER_CPLD_REVISION(version)); 933 VIPER_CPLD_REVISION(version));
934 system_rev = (VIPER_BOARD_VERSION(version) << 8) | 934 system_rev = (VIPER_BOARD_VERSION(version) << 8) |
935 (VIPER_BOARD_ISSUE(version) << 4) | 935 (VIPER_BOARD_ISSUE(version) << 4) |
936 VIPER_CPLD_REVISION(version); 936 VIPER_CPLD_REVISION(version);
937 } else { 937 } else {
938 pr_info("viper: No version register.\n"); 938 pr_info("viper: No version register.\n");
939 } 939 }
940 940
941 i2c_register_board_info(1, ARRAY_AND_SIZE(viper_i2c_devices)); 941 i2c_register_board_info(1, ARRAY_AND_SIZE(viper_i2c_devices));
942 942
943 viper_tpm_init(); 943 viper_tpm_init();
944 pxa_set_ac97_info(NULL); 944 pxa_set_ac97_info(NULL);
945 } 945 }
946 946
947 static struct map_desc viper_io_desc[] __initdata = { 947 static struct map_desc viper_io_desc[] __initdata = {
948 { 948 {
949 .virtual = VIPER_CPLD_BASE, 949 .virtual = VIPER_CPLD_BASE,
950 .pfn = __phys_to_pfn(VIPER_CPLD_PHYS), 950 .pfn = __phys_to_pfn(VIPER_CPLD_PHYS),
951 .length = 0x00300000, 951 .length = 0x00300000,
952 .type = MT_DEVICE, 952 .type = MT_DEVICE,
953 }, 953 },
954 { 954 {
955 .virtual = VIPER_PC104IO_BASE, 955 .virtual = VIPER_PC104IO_BASE,
956 .pfn = __phys_to_pfn(_PCMCIA1IO), 956 .pfn = __phys_to_pfn(0x30000000),
957 .length = 0x00800000, 957 .length = 0x00800000,
958 .type = MT_DEVICE, 958 .type = MT_DEVICE,
959 }, 959 },
960 }; 960 };
961 961
962 static void __init viper_map_io(void) 962 static void __init viper_map_io(void)
963 { 963 {
964 pxa_map_io(); 964 pxa_map_io();
965 965
966 iotable_init(viper_io_desc, ARRAY_SIZE(viper_io_desc)); 966 iotable_init(viper_io_desc, ARRAY_SIZE(viper_io_desc));
967 967
968 PCFR |= PCFR_OPDE; 968 PCFR |= PCFR_OPDE;
969 } 969 }
970 970
971 MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC") 971 MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
972 /* Maintainer: Marc Zyngier <maz@misterjones.org> */ 972 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
973 .phys_io = 0x40000000, 973 .phys_io = 0x40000000,
974 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, 974 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
975 .boot_params = 0xa0000100, 975 .boot_params = 0xa0000100,
976 .map_io = viper_map_io, 976 .map_io = viper_map_io,
977 .init_irq = viper_init_irq, 977 .init_irq = viper_init_irq,
978 .timer = &pxa_timer, 978 .timer = &pxa_timer,
979 .init_machine = viper_init, 979 .init_machine = viper_init,
980 MACHINE_END 980 MACHINE_END
981 981
drivers/pcmcia/pxa2xx_base.c
Diff comments   View file @ b393c69
1 /*====================================================================== 1 /*======================================================================
2 2
3 Device driver for the PCMCIA control functionality of PXA2xx 3 Device driver for the PCMCIA control functionality of PXA2xx
4 microprocessors. 4 microprocessors.
5 5
6 The contents of this file may be used under the 6 The contents of this file may be used under the
7 terms of the GNU Public License version 2 (the "GPL") 7 terms of the GNU Public License version 2 (the "GPL")
8 8
9 (c) Ian Molton (spyro@f2s.com) 2003 9 (c) Ian Molton (spyro@f2s.com) 2003
10 (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4 10 (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
11 11
12 derived from sa11xx_base.c 12 derived from sa11xx_base.c
13 13
14 Portions created by John G. Dorsey are 14 Portions created by John G. Dorsey are
15 Copyright (C) 1999 John G. Dorsey. 15 Copyright (C) 1999 John G. Dorsey.
16 16
17 ======================================================================*/ 17 ======================================================================*/
18 18
19 #include <linux/module.h> 19 #include <linux/module.h>
20 #include <linux/init.h> 20 #include <linux/init.h>
21 #include <linux/cpufreq.h> 21 #include <linux/cpufreq.h>
22 #include <linux/ioport.h> 22 #include <linux/ioport.h>
23 #include <linux/kernel.h> 23 #include <linux/kernel.h>
24 #include <linux/spinlock.h> 24 #include <linux/spinlock.h>
25 #include <linux/platform_device.h> 25 #include <linux/platform_device.h>
26 26
27 #include <mach/hardware.h> 27 #include <mach/hardware.h>
28 #include <asm/io.h> 28 #include <asm/io.h>
29 #include <asm/irq.h> 29 #include <asm/irq.h>
30 #include <asm/system.h> 30 #include <asm/system.h>
31 #include <mach/pxa2xx-regs.h> 31 #include <mach/pxa2xx-regs.h>
32 #include <asm/mach-types.h> 32 #include <asm/mach-types.h>
33 33
34 #include <pcmcia/cs_types.h> 34 #include <pcmcia/cs_types.h>
35 #include <pcmcia/ss.h> 35 #include <pcmcia/ss.h>
36 #include <pcmcia/cistpl.h> 36 #include <pcmcia/cistpl.h>
37 37
38 #include "soc_common.h" 38 #include "soc_common.h"
39 #include "pxa2xx_base.h" 39 #include "pxa2xx_base.h"
40 40
41 /*
42 * Personal Computer Memory Card International Association (PCMCIA) sockets
43 */
41 44
45 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
46 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
47 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
48 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
49 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
50
51 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
52 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
53 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
54 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
55
56 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
57 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
58 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
59 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
60
61 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
62 (0x20000000 + (Nb) * PCMCIASp)
63 #define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
64 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
65 (_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
66 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
67 (_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
68
69 #define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
70 #define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
71 #define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
72 #define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
73
74 #define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
75 #define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
76 #define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
77 #define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
78
79
42 #define MCXX_SETUP_MASK (0x7f) 80 #define MCXX_SETUP_MASK (0x7f)
43 #define MCXX_ASST_MASK (0x1f) 81 #define MCXX_ASST_MASK (0x1f)
44 #define MCXX_HOLD_MASK (0x3f) 82 #define MCXX_HOLD_MASK (0x3f)
45 #define MCXX_SETUP_SHIFT (0) 83 #define MCXX_SETUP_SHIFT (0)
46 #define MCXX_ASST_SHIFT (7) 84 #define MCXX_ASST_SHIFT (7)
47 #define MCXX_HOLD_SHIFT (14) 85 #define MCXX_HOLD_SHIFT (14)
48 86
49 static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns, 87 static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
50 u_int mem_clk_10khz) 88 u_int mem_clk_10khz)
51 { 89 {
52 u_int code = pcmcia_cycle_ns * mem_clk_10khz; 90 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
53 return (code / 300000) + ((code % 300000) ? 1 : 0) - 1; 91 return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
54 } 92 }
55 93
56 static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns, 94 static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
57 u_int mem_clk_10khz) 95 u_int mem_clk_10khz)
58 { 96 {
59 u_int code = pcmcia_cycle_ns * mem_clk_10khz; 97 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
60 return (code / 300000) + ((code % 300000) ? 1 : 0) + 1; 98 return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
61 } 99 }
62 100
63 static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns, 101 static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
64 u_int mem_clk_10khz) 102 u_int mem_clk_10khz)
65 { 103 {
66 u_int code = pcmcia_cycle_ns * mem_clk_10khz; 104 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
67 return (code / 100000) + ((code % 100000) ? 1 : 0) - 1; 105 return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
68 } 106 }
69 107
70 /* This function returns the (approximate) command assertion period, in 108 /* This function returns the (approximate) command assertion period, in
71 * nanoseconds, for a given CPU clock frequency and MCXX_ASST value: 109 * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
72 */ 110 */
73 static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz, 111 static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
74 u_int pcmcia_mcxx_asst) 112 u_int pcmcia_mcxx_asst)
75 { 113 {
76 return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz); 114 return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
77 } 115 }
78 116
79 static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock ) 117 static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
80 { 118 {
81 MCMEM(sock) = ((pxa2xx_mcxx_setup(speed, clock) 119 MCMEM(sock) = ((pxa2xx_mcxx_setup(speed, clock)
82 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) 120 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
83 | ((pxa2xx_mcxx_asst(speed, clock) 121 | ((pxa2xx_mcxx_asst(speed, clock)
84 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) 122 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
85 | ((pxa2xx_mcxx_hold(speed, clock) 123 | ((pxa2xx_mcxx_hold(speed, clock)
86 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); 124 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
87 125
88 return 0; 126 return 0;
89 } 127 }
90 128
91 static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock ) 129 static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
92 { 130 {
93 MCIO(sock) = ((pxa2xx_mcxx_setup(speed, clock) 131 MCIO(sock) = ((pxa2xx_mcxx_setup(speed, clock)
94 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) 132 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
95 | ((pxa2xx_mcxx_asst(speed, clock) 133 | ((pxa2xx_mcxx_asst(speed, clock)
96 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) 134 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
97 | ((pxa2xx_mcxx_hold(speed, clock) 135 | ((pxa2xx_mcxx_hold(speed, clock)
98 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); 136 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
99 137
100 return 0; 138 return 0;
101 } 139 }
102 140
103 static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock ) 141 static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
104 { 142 {
105 MCATT(sock) = ((pxa2xx_mcxx_setup(speed, clock) 143 MCATT(sock) = ((pxa2xx_mcxx_setup(speed, clock)
106 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) 144 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
107 | ((pxa2xx_mcxx_asst(speed, clock) 145 | ((pxa2xx_mcxx_asst(speed, clock)
108 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) 146 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
109 | ((pxa2xx_mcxx_hold(speed, clock) 147 | ((pxa2xx_mcxx_hold(speed, clock)
110 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); 148 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
111 149
112 return 0; 150 return 0;
113 } 151 }
114 152
115 static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk) 153 static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
116 { 154 {
117 struct soc_pcmcia_timing timing; 155 struct soc_pcmcia_timing timing;
118 int sock = skt->nr; 156 int sock = skt->nr;
119 157
120 soc_common_pcmcia_get_timing(skt, &timing); 158 soc_common_pcmcia_get_timing(skt, &timing);
121 159
122 pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk); 160 pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
123 pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk); 161 pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
124 pxa2xx_pcmcia_set_mcio(sock, timing.io, clk); 162 pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);
125 163
126 return 0; 164 return 0;
127 } 165 }
128 166
129 static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt) 167 static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
130 { 168 {
131 unsigned int clk = get_memclk_frequency_10khz(); 169 unsigned int clk = get_memclk_frequency_10khz();
132 return pxa2xx_pcmcia_set_mcxx(skt, clk); 170 return pxa2xx_pcmcia_set_mcxx(skt, clk);
133 } 171 }
134 172
135 #ifdef CONFIG_CPU_FREQ 173 #ifdef CONFIG_CPU_FREQ
136 174
137 static int 175 static int
138 pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt, 176 pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
139 unsigned long val, 177 unsigned long val,
140 struct cpufreq_freqs *freqs) 178 struct cpufreq_freqs *freqs)
141 { 179 {
142 #warning "it's not clear if this is right since the core CPU (N) clock has no effect on the memory (L) clock" 180 #warning "it's not clear if this is right since the core CPU (N) clock has no effect on the memory (L) clock"
143 switch (val) { 181 switch (val) {
144 case CPUFREQ_PRECHANGE: 182 case CPUFREQ_PRECHANGE:
145 if (freqs->new > freqs->old) { 183 if (freqs->new > freqs->old) {
146 debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, " 184 debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
147 "pre-updating\n", 185 "pre-updating\n",
148 freqs->new / 1000, (freqs->new / 100) % 10, 186 freqs->new / 1000, (freqs->new / 100) % 10,
149 freqs->old / 1000, (freqs->old / 100) % 10); 187 freqs->old / 1000, (freqs->old / 100) % 10);
150 pxa2xx_pcmcia_set_mcxx(skt, freqs->new); 188 pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
151 } 189 }
152 break; 190 break;
153 191
154 case CPUFREQ_POSTCHANGE: 192 case CPUFREQ_POSTCHANGE:
155 if (freqs->new < freqs->old) { 193 if (freqs->new < freqs->old) {
156 debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, " 194 debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
157 "post-updating\n", 195 "post-updating\n",
158 freqs->new / 1000, (freqs->new / 100) % 10, 196 freqs->new / 1000, (freqs->new / 100) % 10,
159 freqs->old / 1000, (freqs->old / 100) % 10); 197 freqs->old / 1000, (freqs->old / 100) % 10);
160 pxa2xx_pcmcia_set_mcxx(skt, freqs->new); 198 pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
161 } 199 }
162 break; 200 break;
163 } 201 }
164 return 0; 202 return 0;
165 } 203 }
166 #endif 204 #endif
167 205
168 static void pxa2xx_configure_sockets(struct device *dev) 206 static void pxa2xx_configure_sockets(struct device *dev)
169 { 207 {
170 struct pcmcia_low_level *ops = dev->platform_data; 208 struct pcmcia_low_level *ops = dev->platform_data;
171 209
172 /* 210 /*
173 * We have at least one socket, so set MECR:CIT 211 * We have at least one socket, so set MECR:CIT
174 * (Card Is There) 212 * (Card Is There)
175 */ 213 */
176 MECR |= MECR_CIT; 214 MECR |= MECR_CIT;
177 215
178 /* Set MECR:NOS (Number Of Sockets) */ 216 /* Set MECR:NOS (Number Of Sockets) */
179 if (ops->nr > 1 || machine_is_viper()) 217 if (ops->nr > 1 || machine_is_viper())
180 MECR |= MECR_NOS; 218 MECR |= MECR_NOS;
181 else 219 else
182 MECR &= ~MECR_NOS; 220 MECR &= ~MECR_NOS;
183 } 221 }
184 222
223 static const char *skt_names[] = {
224 "PCMCIA socket 0",
225 "PCMCIA socket 1",
226 };
227
228 #define SKT_DEV_INFO_SIZE(n) \
229 (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
230
185 int __pxa2xx_drv_pcmcia_probe(struct device *dev) 231 int __pxa2xx_drv_pcmcia_probe(struct device *dev)
186 { 232 {
187 int ret; 233 int i, ret;
188 struct pcmcia_low_level *ops; 234 struct pcmcia_low_level *ops;
235 struct skt_dev_info *sinfo;
236 struct soc_pcmcia_socket *skt;
189 237
190 if (!dev || !dev->platform_data) 238 if (!dev || !dev->platform_data)
191 return -ENODEV; 239 return -ENODEV;
192 240
193 ops = (struct pcmcia_low_level *)dev->platform_data; 241 ops = (struct pcmcia_low_level *)dev->platform_data;
194 242
243 sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL);
244 if (!sinfo)
245 return -ENOMEM;
246
247 sinfo->nskt = ops->nr;
248
249 /* Initialize processor specific parameters */
250 for (i = 0; i < ops->nr; i++) {
251 skt = &sinfo->skt[i];
252
253 skt->nr = i;
254 skt->irq = NO_IRQ;
255
256 skt->res_skt.start = _PCMCIA(skt->nr);
257 skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
258 skt->res_skt.name = skt_names[skt->nr];
259 skt->res_skt.flags = IORESOURCE_MEM;
260
261 skt->res_io.start = _PCMCIAIO(skt->nr);
262 skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
263 skt->res_io.name = "io";
264 skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
265
266 skt->res_mem.start = _PCMCIAMem(skt->nr);
267 skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
268 skt->res_mem.name = "memory";
269 skt->res_mem.flags = IORESOURCE_MEM;
270
271 skt->res_attr.start = _PCMCIAAttr(skt->nr);
272 skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
273 skt->res_attr.name = "attribute";
274 skt->res_attr.flags = IORESOURCE_MEM;
275 }
276
195 /* Provide our PXA2xx specific timing routines. */ 277 /* Provide our PXA2xx specific timing routines. */
196 ops->set_timing = pxa2xx_pcmcia_set_timing; 278 ops->set_timing = pxa2xx_pcmcia_set_timing;
197 #ifdef CONFIG_CPU_FREQ 279 #ifdef CONFIG_CPU_FREQ
198 ops->frequency_change = pxa2xx_pcmcia_frequency_change; 280 ops->frequency_change = pxa2xx_pcmcia_frequency_change;
199 #endif 281 #endif
200 282
201 ret = soc_common_drv_pcmcia_probe(dev, ops, ops->first, ops->nr); 283 ret = soc_common_drv_pcmcia_probe(dev, ops, sinfo);
202 284
203 if (!ret) 285 if (!ret)
204 pxa2xx_configure_sockets(dev); 286 pxa2xx_configure_sockets(dev);
205 287
206 return ret; 288 return ret;
207 } 289 }
208 EXPORT_SYMBOL(__pxa2xx_drv_pcmcia_probe); 290 EXPORT_SYMBOL(__pxa2xx_drv_pcmcia_probe);
209 291
210 292
211 static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev) 293 static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
212 { 294 {
213 return __pxa2xx_drv_pcmcia_probe(&dev->dev); 295 return __pxa2xx_drv_pcmcia_probe(&dev->dev);
214 } 296 }
215 297
216 static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev) 298 static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
217 { 299 {
218 return soc_common_drv_pcmcia_remove(&dev->dev); 300 return soc_common_drv_pcmcia_remove(&dev->dev);
219 } 301 }
220 302
221 static int pxa2xx_drv_pcmcia_suspend(struct platform_device *dev, pm_message_t state) 303 static int pxa2xx_drv_pcmcia_suspend(struct platform_device *dev, pm_message_t state)
222 { 304 {
223 return pcmcia_socket_dev_suspend(&dev->dev, state); 305 return pcmcia_socket_dev_suspend(&dev->dev, state);
224 } 306 }
225 307
226 static int pxa2xx_drv_pcmcia_resume(struct platform_device *dev) 308 static int pxa2xx_drv_pcmcia_resume(struct platform_device *dev)
227 { 309 {
228 pxa2xx_configure_sockets(&dev->dev); 310 pxa2xx_configure_sockets(&dev->dev);
229 return pcmcia_socket_dev_resume(&dev->dev); 311 return pcmcia_socket_dev_resume(&dev->dev);
230 } 312 }
231 313
232 static struct platform_driver pxa2xx_pcmcia_driver = { 314 static struct platform_driver pxa2xx_pcmcia_driver = {
233 .probe = pxa2xx_drv_pcmcia_probe, 315 .probe = pxa2xx_drv_pcmcia_probe,
234 .remove = pxa2xx_drv_pcmcia_remove, 316 .remove = pxa2xx_drv_pcmcia_remove,
235 .suspend = pxa2xx_drv_pcmcia_suspend, 317 .suspend = pxa2xx_drv_pcmcia_suspend,
236 .resume = pxa2xx_drv_pcmcia_resume, 318 .resume = pxa2xx_drv_pcmcia_resume,
237 .driver = { 319 .driver = {
238 .name = "pxa2xx-pcmcia", 320 .name = "pxa2xx-pcmcia",
239 .owner = THIS_MODULE, 321 .owner = THIS_MODULE,
240 }, 322 },
241 }; 323 };
242 324
243 static int __init pxa2xx_pcmcia_init(void) 325 static int __init pxa2xx_pcmcia_init(void)
244 { 326 {
245 return platform_driver_register(&pxa2xx_pcmcia_driver); 327 return platform_driver_register(&pxa2xx_pcmcia_driver);
246 } 328 }
247 329
248 static void __exit pxa2xx_pcmcia_exit(void) 330 static void __exit pxa2xx_pcmcia_exit(void)
249 { 331 {
250 platform_driver_unregister(&pxa2xx_pcmcia_driver); 332 platform_driver_unregister(&pxa2xx_pcmcia_driver);
251 } 333 }
252 334
253 fs_initcall(pxa2xx_pcmcia_init); 335 fs_initcall(pxa2xx_pcmcia_init);
254 module_exit(pxa2xx_pcmcia_exit); 336 module_exit(pxa2xx_pcmcia_exit);
255 337
256 MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>"); 338 MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
257 MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver"); 339 MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
258 MODULE_LICENSE("GPL"); 340 MODULE_LICENSE("GPL");
259 MODULE_ALIAS("platform:pxa2xx-pcmcia"); 341 MODULE_ALIAS("platform:pxa2xx-pcmcia");
260 342
drivers/pcmcia/sa11xx_base.c
Diff comments   View file @ b393c69
1 /*====================================================================== 1 /*======================================================================
2 2
3 Device driver for the PCMCIA control functionality of StrongARM 3 Device driver for the PCMCIA control functionality of StrongARM
4 SA-1100 microprocessors. 4 SA-1100 microprocessors.
5 5
6 The contents of this file are subject to the Mozilla Public 6 The contents of this file are subject to the Mozilla Public
7 License Version 1.1 (the "License"); you may not use this file 7 License Version 1.1 (the "License"); you may not use this file
8 except in compliance with the License. You may obtain a copy of 8 except in compliance with the License. You may obtain a copy of
9 the License at http://www.mozilla.org/MPL/ 9 the License at http://www.mozilla.org/MPL/
10 10
11 Software distributed under the License is distributed on an "AS 11 Software distributed under the License is distributed on an "AS
12 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or 12 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
13 implied. See the License for the specific language governing 13 implied. See the License for the specific language governing
14 rights and limitations under the License. 14 rights and limitations under the License.
15 15
16 The initial developer of the original code is John G. Dorsey 16 The initial developer of the original code is John G. Dorsey
17 <john+@cs.cmu.edu>. Portions created by John G. Dorsey are 17 <john+@cs.cmu.edu>. Portions created by John G. Dorsey are
18 Copyright (C) 1999 John G. Dorsey. All Rights Reserved. 18 Copyright (C) 1999 John G. Dorsey. All Rights Reserved.
19 19
20 Alternatively, the contents of this file may be used under the 20 Alternatively, the contents of this file may be used under the
21 terms of the GNU Public License version 2 (the "GPL"), in which 21 terms of the GNU Public License version 2 (the "GPL"), in which
22 case the provisions of the GPL are applicable instead of the 22 case the provisions of the GPL are applicable instead of the
23 above. If you wish to allow the use of your version of this file 23 above. If you wish to allow the use of your version of this file
24 only under the terms of the GPL and not to allow others to use 24 only under the terms of the GPL and not to allow others to use
25 your version of this file under the MPL, indicate your decision 25 your version of this file under the MPL, indicate your decision
26 by deleting the provisions above and replace them with the notice 26 by deleting the provisions above and replace them with the notice
27 and other provisions required by the GPL. If you do not delete 27 and other provisions required by the GPL. If you do not delete
28 the provisions above, a recipient may use your version of this 28 the provisions above, a recipient may use your version of this
29 file under either the MPL or the GPL. 29 file under either the MPL or the GPL.
30 30
31 ======================================================================*/ 31 ======================================================================*/
32 32
33 #include <linux/module.h> 33 #include <linux/module.h>
34 #include <linux/init.h> 34 #include <linux/init.h>
35 #include <linux/cpufreq.h> 35 #include <linux/cpufreq.h>
36 #include <linux/ioport.h> 36 #include <linux/ioport.h>
37 #include <linux/kernel.h> 37 #include <linux/kernel.h>
38 #include <linux/spinlock.h> 38 #include <linux/spinlock.h>
39 39
40 #include <mach/hardware.h> 40 #include <mach/hardware.h>
41 #include <asm/io.h> 41 #include <asm/io.h>
42 #include <asm/irq.h> 42 #include <asm/irq.h>
43 #include <asm/system.h> 43 #include <asm/system.h>
44 44
45 #include "soc_common.h" 45 #include "soc_common.h"
46 #include "sa11xx_base.h" 46 #include "sa11xx_base.h"
47 47
48 48
49 /* 49 /*
50 * sa1100_pcmcia_default_mecr_timing 50 * sa1100_pcmcia_default_mecr_timing
51 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 51 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
52 * 52 *
53 * Calculate MECR clock wait states for given CPU clock 53 * Calculate MECR clock wait states for given CPU clock
54 * speed and command wait state. This function can be over- 54 * speed and command wait state. This function can be over-
55 * written by a board specific version. 55 * written by a board specific version.
56 * 56 *
57 * The default is to simply calculate the BS values as specified in 57 * The default is to simply calculate the BS values as specified in
58 * the INTEL SA1100 development manual 58 * the INTEL SA1100 development manual
59 * "Expansion Memory (PCMCIA) Configuration Register (MECR)" 59 * "Expansion Memory (PCMCIA) Configuration Register (MECR)"
60 * that's section 10.2.5 in _my_ version of the manual ;) 60 * that's section 10.2.5 in _my_ version of the manual ;)
61 */ 61 */
62 static unsigned int 62 static unsigned int
63 sa1100_pcmcia_default_mecr_timing(struct soc_pcmcia_socket *skt, 63 sa1100_pcmcia_default_mecr_timing(struct soc_pcmcia_socket *skt,
64 unsigned int cpu_speed, 64 unsigned int cpu_speed,
65 unsigned int cmd_time) 65 unsigned int cmd_time)
66 { 66 {
67 return sa1100_pcmcia_mecr_bs(cmd_time, cpu_speed); 67 return sa1100_pcmcia_mecr_bs(cmd_time, cpu_speed);
68 } 68 }
69 69
70 /* sa1100_pcmcia_set_mecr() 70 /* sa1100_pcmcia_set_mecr()
71 * ^^^^^^^^^^^^^^^^^^^^^^^^ 71 * ^^^^^^^^^^^^^^^^^^^^^^^^
72 * 72 *
73 * set MECR value for socket <sock> based on this sockets 73 * set MECR value for socket <sock> based on this sockets
74 * io, mem and attribute space access speed. 74 * io, mem and attribute space access speed.
75 * Call board specific BS value calculation to allow boards 75 * Call board specific BS value calculation to allow boards
76 * to tweak the BS values. 76 * to tweak the BS values.
77 */ 77 */
78 static int 78 static int
79 sa1100_pcmcia_set_mecr(struct soc_pcmcia_socket *skt, unsigned int cpu_clock) 79 sa1100_pcmcia_set_mecr(struct soc_pcmcia_socket *skt, unsigned int cpu_clock)
80 { 80 {
81 struct soc_pcmcia_timing timing; 81 struct soc_pcmcia_timing timing;
82 u32 mecr, old_mecr; 82 u32 mecr, old_mecr;
83 unsigned long flags; 83 unsigned long flags;
84 unsigned int bs_io, bs_mem, bs_attr; 84 unsigned int bs_io, bs_mem, bs_attr;
85 85
86 soc_common_pcmcia_get_timing(skt, &timing); 86 soc_common_pcmcia_get_timing(skt, &timing);
87 87
88 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io); 88 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io);
89 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem); 89 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem);
90 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr); 90 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr);
91 91
92 local_irq_save(flags); 92 local_irq_save(flags);
93 93
94 old_mecr = mecr = MECR; 94 old_mecr = mecr = MECR;
95 MECR_FAST_SET(mecr, skt->nr, 0); 95 MECR_FAST_SET(mecr, skt->nr, 0);
96 MECR_BSIO_SET(mecr, skt->nr, bs_io); 96 MECR_BSIO_SET(mecr, skt->nr, bs_io);
97 MECR_BSA_SET(mecr, skt->nr, bs_attr); 97 MECR_BSA_SET(mecr, skt->nr, bs_attr);
98 MECR_BSM_SET(mecr, skt->nr, bs_mem); 98 MECR_BSM_SET(mecr, skt->nr, bs_mem);
99 if (old_mecr != mecr) 99 if (old_mecr != mecr)
100 MECR = mecr; 100 MECR = mecr;
101 101
102 local_irq_restore(flags); 102 local_irq_restore(flags);
103 103
104 debug(skt, 2, "FAST %X BSM %X BSA %X BSIO %X\n", 104 debug(skt, 2, "FAST %X BSM %X BSA %X BSIO %X\n",
105 MECR_FAST_GET(mecr, skt->nr), 105 MECR_FAST_GET(mecr, skt->nr),
106 MECR_BSM_GET(mecr, skt->nr), MECR_BSA_GET(mecr, skt->nr), 106 MECR_BSM_GET(mecr, skt->nr), MECR_BSA_GET(mecr, skt->nr),
107 MECR_BSIO_GET(mecr, skt->nr)); 107 MECR_BSIO_GET(mecr, skt->nr));
108 108
109 return 0; 109 return 0;
110 } 110 }
111 111
112 #ifdef CONFIG_CPU_FREQ 112 #ifdef CONFIG_CPU_FREQ
113 static int 113 static int
114 sa1100_pcmcia_frequency_change(struct soc_pcmcia_socket *skt, 114 sa1100_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
115 unsigned long val, 115 unsigned long val,
116 struct cpufreq_freqs *freqs) 116 struct cpufreq_freqs *freqs)
117 { 117 {
118 switch (val) { 118 switch (val) {
119 case CPUFREQ_PRECHANGE: 119 case CPUFREQ_PRECHANGE:
120 if (freqs->new > freqs->old) 120 if (freqs->new > freqs->old)
121 sa1100_pcmcia_set_mecr(skt, freqs->new); 121 sa1100_pcmcia_set_mecr(skt, freqs->new);
122 break; 122 break;
123 123
124 case CPUFREQ_POSTCHANGE: 124 case CPUFREQ_POSTCHANGE:
125 if (freqs->new < freqs->old) 125 if (freqs->new < freqs->old)
126 sa1100_pcmcia_set_mecr(skt, freqs->new); 126 sa1100_pcmcia_set_mecr(skt, freqs->new);
127 break; 127 break;
128 case CPUFREQ_RESUMECHANGE: 128 case CPUFREQ_RESUMECHANGE:
129 sa1100_pcmcia_set_mecr(skt, freqs->new); 129 sa1100_pcmcia_set_mecr(skt, freqs->new);
130 break; 130 break;
131 } 131 }
132 132
133 return 0; 133 return 0;
134 } 134 }
135 135
136 #endif 136 #endif
137 137
138 static int 138 static int
139 sa1100_pcmcia_set_timing(struct soc_pcmcia_socket *skt) 139 sa1100_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
140 { 140 {
141 return sa1100_pcmcia_set_mecr(skt, cpufreq_get(0)); 141 return sa1100_pcmcia_set_mecr(skt, cpufreq_get(0));
142 } 142 }
143 143
144 static int 144 static int
145 sa1100_pcmcia_show_timing(struct soc_pcmcia_socket *skt, char *buf) 145 sa1100_pcmcia_show_timing(struct soc_pcmcia_socket *skt, char *buf)
146 { 146 {
147 struct soc_pcmcia_timing timing; 147 struct soc_pcmcia_timing timing;
148 unsigned int clock = cpufreq_get(0); 148 unsigned int clock = cpufreq_get(0);
149 unsigned long mecr = MECR; 149 unsigned long mecr = MECR;
150 char *p = buf; 150 char *p = buf;
151 151
152 soc_common_pcmcia_get_timing(skt, &timing); 152 soc_common_pcmcia_get_timing(skt, &timing);
153 153
154 p+=sprintf(p, "I/O : %u (%u)\n", timing.io, 154 p+=sprintf(p, "I/O : %u (%u)\n", timing.io,
155 sa1100_pcmcia_cmd_time(clock, MECR_BSIO_GET(mecr, skt->nr))); 155 sa1100_pcmcia_cmd_time(clock, MECR_BSIO_GET(mecr, skt->nr)));
156 156
157 p+=sprintf(p, "attribute: %u (%u)\n", timing.attr, 157 p+=sprintf(p, "attribute: %u (%u)\n", timing.attr,
158 sa1100_pcmcia_cmd_time(clock, MECR_BSA_GET(mecr, skt->nr))); 158 sa1100_pcmcia_cmd_time(clock, MECR_BSA_GET(mecr, skt->nr)));
159 159
160 p+=sprintf(p, "common : %u (%u)\n", timing.mem, 160 p+=sprintf(p, "common : %u (%u)\n", timing.mem,
161 sa1100_pcmcia_cmd_time(clock, MECR_BSM_GET(mecr, skt->nr))); 161 sa1100_pcmcia_cmd_time(clock, MECR_BSM_GET(mecr, skt->nr)));
162 162
163 return p - buf; 163 return p - buf;
164 } 164 }
165 165
166 static const char *skt_names[] = {
167 "PCMCIA socket 0",
168 "PCMCIA socket 1",
169 };
170
171 #define SKT_DEV_INFO_SIZE(n) \
172 (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
173
166 int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, 174 int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops,
167 int first, int nr) 175 int first, int nr)
168 { 176 {
177 struct skt_dev_info *sinfo;
178 struct soc_pcmcia_socket *skt;
179 int i;
180
181 sinfo = kzalloc(SKT_DEV_INFO_SIZE(nr), GFP_KERNEL);
182 if (!sinfo)
183 return -ENOMEM;
184
185 sinfo->nskt = nr;
186
187 /* Initiliaze processor specific parameters */
188 for (i = 0; i < nr; i++) {
189 skt = &sinfo->skt[i];
190
191 skt->nr = first + i;
192 skt->irq = NO_IRQ;
193
194 skt->res_skt.start = _PCMCIA(skt->nr);
195 skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
196 skt->res_skt.name = skt_names[skt->nr];
197 skt->res_skt.flags = IORESOURCE_MEM;
198
199 skt->res_io.start = _PCMCIAIO(skt->nr);
200 skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
201 skt->res_io.name = "io";
202 skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
203
204 skt->res_mem.start = _PCMCIAMem(skt->nr);
205 skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
206 skt->res_mem.name = "memory";
207 skt->res_mem.flags = IORESOURCE_MEM;
208
209 skt->res_attr.start = _PCMCIAAttr(skt->nr);
210 skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
211 skt->res_attr.name = "attribute";
212 skt->res_attr.flags = IORESOURCE_MEM;
213 }
214
169 /* 215 /*
170 * set default MECR calculation if the board specific 216 * set default MECR calculation if the board specific
171 * code did not specify one... 217 * code did not specify one...
172 */ 218 */
173 if (!ops->get_timing) 219 if (!ops->get_timing)
174 ops->get_timing = sa1100_pcmcia_default_mecr_timing; 220 ops->get_timing = sa1100_pcmcia_default_mecr_timing;
175 221
176 /* Provide our SA11x0 specific timing routines. */ 222 /* Provide our SA11x0 specific timing routines. */
177 ops->set_timing = sa1100_pcmcia_set_timing; 223 ops->set_timing = sa1100_pcmcia_set_timing;
178 ops->show_timing = sa1100_pcmcia_show_timing; 224 ops->show_timing = sa1100_pcmcia_show_timing;
179 #ifdef CONFIG_CPU_FREQ 225 #ifdef CONFIG_CPU_FREQ
180 ops->frequency_change = sa1100_pcmcia_frequency_change; 226 ops->frequency_change = sa1100_pcmcia_frequency_change;
181 #endif 227 #endif
182 228
183 return soc_common_drv_pcmcia_probe(dev, ops, first, nr); 229 return soc_common_drv_pcmcia_probe(dev, ops, sinfo);
184 } 230 }
185 EXPORT_SYMBOL(sa11xx_drv_pcmcia_probe); 231 EXPORT_SYMBOL(sa11xx_drv_pcmcia_probe);
186 232
187 static int __init sa11xx_pcmcia_init(void) 233 static int __init sa11xx_pcmcia_init(void)
188 { 234 {
189 return 0; 235 return 0;
190 } 236 }
191 fs_initcall(sa11xx_pcmcia_init); 237 fs_initcall(sa11xx_pcmcia_init);
192 238
193 static void __exit sa11xx_pcmcia_exit(void) {} 239 static void __exit sa11xx_pcmcia_exit(void) {}
194 240
195 module_exit(sa11xx_pcmcia_exit); 241 module_exit(sa11xx_pcmcia_exit);
196 242
197 MODULE_AUTHOR("John Dorsey <john+@cs.cmu.edu>"); 243 MODULE_AUTHOR("John Dorsey <john+@cs.cmu.edu>");
198 MODULE_DESCRIPTION("Linux PCMCIA Card Services: SA-11xx core socket driver"); 244 MODULE_DESCRIPTION("Linux PCMCIA Card Services: SA-11xx core socket driver");
199 MODULE_LICENSE("Dual MPL/GPL"); 245 MODULE_LICENSE("Dual MPL/GPL");
200 246
drivers/pcmcia/soc_common.c
Diff comments   View file @ b393c69
1 /*====================================================================== 1 /*======================================================================
2 2
3 Common support code for the PCMCIA control functionality of 3 Common support code for the PCMCIA control functionality of
4 integrated SOCs like the SA-11x0 and PXA2xx microprocessors. 4 integrated SOCs like the SA-11x0 and PXA2xx microprocessors.
5 5
6 The contents of this file are subject to the Mozilla Public 6 The contents of this file are subject to the Mozilla Public
7 License Version 1.1 (the "License"); you may not use this file 7 License Version 1.1 (the "License"); you may not use this file
8 except in compliance with the License. You may obtain a copy of 8 except in compliance with the License. You may obtain a copy of
9 the License at http://www.mozilla.org/MPL/ 9 the License at http://www.mozilla.org/MPL/
10 10
11 Software distributed under the License is distributed on an "AS 11 Software distributed under the License is distributed on an "AS
12 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or 12 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
13 implied. See the License for the specific language governing 13 implied. See the License for the specific language governing
14 rights and limitations under the License. 14 rights and limitations under the License.
15 15
16 The initial developer of the original code is John G. Dorsey 16 The initial developer of the original code is John G. Dorsey
17 <john+@cs.cmu.edu>. Portions created by John G. Dorsey are 17 <john+@cs.cmu.edu>. Portions created by John G. Dorsey are
18 Copyright (C) 1999 John G. Dorsey. All Rights Reserved. 18 Copyright (C) 1999 John G. Dorsey. All Rights Reserved.
19 19
20 Alternatively, the contents of this file may be used under the 20 Alternatively, the contents of this file may be used under the
21 terms of the GNU Public License version 2 (the "GPL"), in which 21 terms of the GNU Public License version 2 (the "GPL"), in which
22 case the provisions of the GPL are applicable instead of the 22 case the provisions of the GPL are applicable instead of the
23 above. If you wish to allow the use of your version of this file 23 above. If you wish to allow the use of your version of this file
24 only under the terms of the GPL and not to allow others to use 24 only under the terms of the GPL and not to allow others to use
25 your version of this file under the MPL, indicate your decision 25 your version of this file under the MPL, indicate your decision
26 by deleting the provisions above and replace them with the notice 26 by deleting the provisions above and replace them with the notice
27 and other provisions required by the GPL. If you do not delete 27 and other provisions required by the GPL. If you do not delete
28 the provisions above, a recipient may use your version of this 28 the provisions above, a recipient may use your version of this
29 file under either the MPL or the GPL. 29 file under either the MPL or the GPL.
30 30
31 ======================================================================*/ 31 ======================================================================*/
32 32
33 33
34 #include <linux/module.h> 34 #include <linux/module.h>
35 #include <linux/moduleparam.h> 35 #include <linux/moduleparam.h>
36 #include <linux/init.h> 36 #include <linux/init.h>
37 #include <linux/kernel.h> 37 #include <linux/kernel.h>
38 #include <linux/timer.h> 38 #include <linux/timer.h>
39 #include <linux/mm.h> 39 #include <linux/mm.h>
40 #include <linux/mutex.h> 40 #include <linux/mutex.h>
41 #include <linux/interrupt.h> 41 #include <linux/interrupt.h>
42 #include <linux/irq.h> 42 #include <linux/irq.h>
43 #include <linux/spinlock.h> 43 #include <linux/spinlock.h>
44 #include <linux/cpufreq.h> 44 #include <linux/cpufreq.h>
45 45
46 #include <mach/hardware.h> 46 #include <mach/hardware.h>
47 #include <asm/io.h> 47 #include <asm/io.h>
48 #include <asm/system.h> 48 #include <asm/system.h>
49 49
50 #include "soc_common.h" 50 #include "soc_common.h"
51 51
52 /* FIXME: platform dependent resource declaration has to move out of this file */
53 #ifdef CONFIG_ARCH_PXA
54 #include <mach/pxa-regs.h>
55 #endif
56
57 #ifdef CONFIG_PCMCIA_DEBUG 52 #ifdef CONFIG_PCMCIA_DEBUG
58 53
59 static int pc_debug; 54 static int pc_debug;
60 module_param(pc_debug, int, 0644); 55 module_param(pc_debug, int, 0644);
61 56
62 void soc_pcmcia_debug(struct soc_pcmcia_socket *skt, const char *func, 57 void soc_pcmcia_debug(struct soc_pcmcia_socket *skt, const char *func,
63 int lvl, const char *fmt, ...) 58 int lvl, const char *fmt, ...)
64 { 59 {
65 va_list args; 60 va_list args;
66 if (pc_debug > lvl) { 61 if (pc_debug > lvl) {
67 printk(KERN_DEBUG "skt%u: %s: ", skt->nr, func); 62 printk(KERN_DEBUG "skt%u: %s: ", skt->nr, func);
68 va_start(args, fmt); 63 va_start(args, fmt);
69 vprintk(fmt, args); 64 vprintk(fmt, args);
70 va_end(args); 65 va_end(args);
71 } 66 }
72 } 67 }
73 68
74 #endif 69 #endif
75 70
76 #define to_soc_pcmcia_socket(x) container_of(x, struct soc_pcmcia_socket, socket) 71 #define to_soc_pcmcia_socket(x) container_of(x, struct soc_pcmcia_socket, socket)
77 72
78 static unsigned short 73 static unsigned short
79 calc_speed(unsigned short *spds, int num, unsigned short dflt) 74 calc_speed(unsigned short *spds, int num, unsigned short dflt)
80 { 75 {
81 unsigned short speed = 0; 76 unsigned short speed = 0;
82 int i; 77 int i;
83 78
84 for (i = 0; i < num; i++) 79 for (i = 0; i < num; i++)
85 if (speed < spds[i]) 80 if (speed < spds[i])
86 speed = spds[i]; 81 speed = spds[i];
87 if (speed == 0) 82 if (speed == 0)
88 speed = dflt; 83 speed = dflt;
89 84
90 return speed; 85 return speed;
91 } 86 }
92 87
93 void soc_common_pcmcia_get_timing(struct soc_pcmcia_socket *skt, struct soc_pcmcia_timing *timing) 88 void soc_common_pcmcia_get_timing(struct soc_pcmcia_socket *skt, struct soc_pcmcia_timing *timing)
94 { 89 {
95 timing->io = calc_speed(skt->spd_io, MAX_IO_WIN, SOC_PCMCIA_IO_ACCESS); 90 timing->io = calc_speed(skt->spd_io, MAX_IO_WIN, SOC_PCMCIA_IO_ACCESS);
96 timing->mem = calc_speed(skt->spd_mem, MAX_WIN, SOC_PCMCIA_3V_MEM_ACCESS); 91 timing->mem = calc_speed(skt->spd_mem, MAX_WIN, SOC_PCMCIA_3V_MEM_ACCESS);
97 timing->attr = calc_speed(skt->spd_attr, MAX_WIN, SOC_PCMCIA_3V_MEM_ACCESS); 92 timing->attr = calc_speed(skt->spd_attr, MAX_WIN, SOC_PCMCIA_3V_MEM_ACCESS);
98 } 93 }
99 EXPORT_SYMBOL(soc_common_pcmcia_get_timing); 94 EXPORT_SYMBOL(soc_common_pcmcia_get_timing);
100 95
101 static unsigned int soc_common_pcmcia_skt_state(struct soc_pcmcia_socket *skt) 96 static unsigned int soc_common_pcmcia_skt_state(struct soc_pcmcia_socket *skt)
102 { 97 {
103 struct pcmcia_state state; 98 struct pcmcia_state state;
104 unsigned int stat; 99 unsigned int stat;
105 100
106 memset(&state, 0, sizeof(struct pcmcia_state)); 101 memset(&state, 0, sizeof(struct pcmcia_state));
107 102
108 skt->ops->socket_state(skt, &state); 103 skt->ops->socket_state(skt, &state);
109 104
110 stat = state.detect ? SS_DETECT : 0; 105 stat = state.detect ? SS_DETECT : 0;
111 stat |= state.ready ? SS_READY : 0; 106 stat |= state.ready ? SS_READY : 0;
112 stat |= state.wrprot ? SS_WRPROT : 0; 107 stat |= state.wrprot ? SS_WRPROT : 0;
113 stat |= state.vs_3v ? SS_3VCARD : 0; 108 stat |= state.vs_3v ? SS_3VCARD : 0;
114 stat |= state.vs_Xv ? SS_XVCARD : 0; 109 stat |= state.vs_Xv ? SS_XVCARD : 0;
115 110
116 /* The power status of individual sockets is not available 111 /* The power status of individual sockets is not available
117 * explicitly from the hardware, so we just remember the state 112 * explicitly from the hardware, so we just remember the state
118 * and regurgitate it upon request: 113 * and regurgitate it upon request:
119 */ 114 */
120 stat |= skt->cs_state.Vcc ? SS_POWERON : 0; 115 stat |= skt->cs_state.Vcc ? SS_POWERON : 0;
121 116
122 if (skt->cs_state.flags & SS_IOCARD) 117 if (skt->cs_state.flags & SS_IOCARD)
123 stat |= state.bvd1 ? SS_STSCHG : 0; 118 stat |= state.bvd1 ? SS_STSCHG : 0;
124 else { 119 else {
125 if (state.bvd1 == 0) 120 if (state.bvd1 == 0)
126 stat |= SS_BATDEAD; 121 stat |= SS_BATDEAD;
127 else if (state.bvd2 == 0) 122 else if (state.bvd2 == 0)
128 stat |= SS_BATWARN; 123 stat |= SS_BATWARN;
129 } 124 }
130 return stat; 125 return stat;
131 } 126 }
132 127
133 /* 128 /*
134 * soc_common_pcmcia_config_skt 129 * soc_common_pcmcia_config_skt
135 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 130 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
136 * 131 *
137 * Convert PCMCIA socket state to our socket configure structure. 132 * Convert PCMCIA socket state to our socket configure structure.
138 */ 133 */
139 static int 134 static int
140 soc_common_pcmcia_config_skt(struct soc_pcmcia_socket *skt, socket_state_t *state) 135 soc_common_pcmcia_config_skt(struct soc_pcmcia_socket *skt, socket_state_t *state)
141 { 136 {
142 int ret; 137 int ret;
143 138
144 ret = skt->ops->configure_socket(skt, state); 139 ret = skt->ops->configure_socket(skt, state);
145 if (ret == 0) { 140 if (ret == 0) {
146 /* 141 /*
147 * This really needs a better solution. The IRQ 142 * This really needs a better solution. The IRQ
148 * may or may not be claimed by the driver. 143 * may or may not be claimed by the driver.
149 */ 144 */
150 if (skt->irq_state != 1 && state->io_irq) { 145 if (skt->irq_state != 1 && state->io_irq) {
151 skt->irq_state = 1; 146 skt->irq_state = 1;
152 set_irq_type(skt->irq, IRQ_TYPE_EDGE_FALLING); 147 set_irq_type(skt->irq, IRQ_TYPE_EDGE_FALLING);
153 } else if (skt->irq_state == 1 && state->io_irq == 0) { 148 } else if (skt->irq_state == 1 && state->io_irq == 0) {
154 skt->irq_state = 0; 149 skt->irq_state = 0;
155 set_irq_type(skt->irq, IRQ_TYPE_NONE); 150 set_irq_type(skt->irq, IRQ_TYPE_NONE);
156 } 151 }
157 152
158 skt->cs_state = *state; 153 skt->cs_state = *state;
159 } 154 }
160 155
161 if (ret < 0) 156 if (ret < 0)
162 printk(KERN_ERR "soc_common_pcmcia: unable to configure " 157 printk(KERN_ERR "soc_common_pcmcia: unable to configure "
163 "socket %d\n", skt->nr); 158 "socket %d\n", skt->nr);
164 159
165 return ret; 160 return ret;
166 } 161 }
167 162
168 /* soc_common_pcmcia_sock_init() 163 /* soc_common_pcmcia_sock_init()
169 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 164 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
170 * 165 *
171 * (Re-)Initialise the socket, turning on status interrupts 166 * (Re-)Initialise the socket, turning on status interrupts
172 * and PCMCIA bus. This must wait for power to stabilise 167 * and PCMCIA bus. This must wait for power to stabilise
173 * so that the card status signals report correctly. 168 * so that the card status signals report correctly.
174 * 169 *
175 * Returns: 0 170 * Returns: 0
176 */ 171 */
177 static int soc_common_pcmcia_sock_init(struct pcmcia_socket *sock) 172 static int soc_common_pcmcia_sock_init(struct pcmcia_socket *sock)
178 { 173 {
179 struct soc_pcmcia_socket *skt = to_soc_pcmcia_socket(sock); 174 struct soc_pcmcia_socket *skt = to_soc_pcmcia_socket(sock);
180 175
181 debug(skt, 2, "initializing socket\n"); 176 debug(skt, 2, "initializing socket\n");
182 177
183 skt->ops->socket_init(skt); 178 skt->ops->socket_init(skt);
184 return 0; 179 return 0;
185 } 180 }
186 181
187 182
188 /* 183 /*
189 * soc_common_pcmcia_suspend() 184 * soc_common_pcmcia_suspend()
190 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^ 185 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^
191 * 186 *
192 * Remove power on the socket, disable IRQs from the card. 187 * Remove power on the socket, disable IRQs from the card.
193 * Turn off status interrupts, and disable the PCMCIA bus. 188 * Turn off status interrupts, and disable the PCMCIA bus.
194 * 189 *
195 * Returns: 0 190 * Returns: 0
196 */ 191 */
197 static int soc_common_pcmcia_suspend(struct pcmcia_socket *sock) 192 static int soc_common_pcmcia_suspend(struct pcmcia_socket *sock)
198 { 193 {
199 struct soc_pcmcia_socket *skt = to_soc_pcmcia_socket(sock); 194 struct soc_pcmcia_socket *skt = to_soc_pcmcia_socket(sock);
200 195
201 debug(skt, 2, "suspending socket\n"); 196 debug(skt, 2, "suspending socket\n");
202 197
203 skt->ops->socket_suspend(skt); 198 skt->ops->socket_suspend(skt);
204 199
205 return 0; 200 return 0;
206 } 201 }
207 202
208 static DEFINE_SPINLOCK(status_lock); 203 static DEFINE_SPINLOCK(status_lock);
209 204
210 static void soc_common_check_status(struct soc_pcmcia_socket *skt) 205 static void soc_common_check_status(struct soc_pcmcia_socket *skt)
211 { 206 {
212 unsigned int events; 207 unsigned int events;
213 208
214 debug(skt, 4, "entering PCMCIA monitoring thread\n"); 209 debug(skt, 4, "entering PCMCIA monitoring thread\n");
215 210
216 do { 211 do {
217 unsigned int status; 212 unsigned int status;
218 unsigned long flags; 213 unsigned long flags;
219 214
220 status = soc_common_pcmcia_skt_state(skt); 215 status = soc_common_pcmcia_skt_state(skt);
221 216
222 spin_lock_irqsave(&status_lock, flags); 217 spin_lock_irqsave(&status_lock, flags);
223 events = (status ^ skt->status) & skt->cs_state.csc_mask; 218 events = (status ^ skt->status) & skt->cs_state.csc_mask;
224 skt->status = status; 219 skt->status = status;
225 spin_unlock_irqrestore(&status_lock, flags); 220 spin_unlock_irqrestore(&status_lock, flags);
226 221
227 debug(skt, 4, "events: %s%s%s%s%s%s\n", 222 debug(skt, 4, "events: %s%s%s%s%s%s\n",
228 events == 0 ? "<NONE>" : "", 223 events == 0 ? "<NONE>" : "",
229 events & SS_DETECT ? "DETECT " : "", 224 events & SS_DETECT ? "DETECT " : "",
230 events & SS_READY ? "READY " : "", 225 events & SS_READY ? "READY " : "",
231 events & SS_BATDEAD ? "BATDEAD " : "", 226 events & SS_BATDEAD ? "BATDEAD " : "",
232 events & SS_BATWARN ? "BATWARN " : "", 227 events & SS_BATWARN ? "BATWARN " : "",
233 events & SS_STSCHG ? "STSCHG " : ""); 228 events & SS_STSCHG ? "STSCHG " : "");
234 229
235 if (events) 230 if (events)
236 pcmcia_parse_events(&skt->socket, events); 231 pcmcia_parse_events(&skt->socket, events);
237 } while (events); 232 } while (events);
238 } 233 }
239 234
240 /* Let's poll for events in addition to IRQs since IRQ only is unreliable... */ 235 /* Let's poll for events in addition to IRQs since IRQ only is unreliable... */
241 static void soc_common_pcmcia_poll_event(unsigned long dummy) 236 static void soc_common_pcmcia_poll_event(unsigned long dummy)
242 { 237 {
243 struct soc_pcmcia_socket *skt = (struct soc_pcmcia_socket *)dummy; 238 struct soc_pcmcia_socket *skt = (struct soc_pcmcia_socket *)dummy;
244 debug(skt, 4, "polling for events\n"); 239 debug(skt, 4, "polling for events\n");
245 240
246 mod_timer(&skt->poll_timer, jiffies + SOC_PCMCIA_POLL_PERIOD); 241 mod_timer(&skt->poll_timer, jiffies + SOC_PCMCIA_POLL_PERIOD);
247 242
248 soc_common_check_status(skt); 243 soc_common_check_status(skt);
249 } 244 }
250 245
251 246
252 /* 247 /*
253 * Service routine for socket driver interrupts (requested by the 248 * Service routine for socket driver interrupts (requested by the
254 * low-level PCMCIA init() operation via soc_common_pcmcia_thread()). 249 * low-level PCMCIA init() operation via soc_common_pcmcia_thread()).
255 * The actual interrupt-servicing work is performed by 250 * The actual interrupt-servicing work is performed by
256 * soc_common_pcmcia_thread(), largely because the Card Services event- 251 * soc_common_pcmcia_thread(), largely because the Card Services event-
257 * handling code performs scheduling operations which cannot be 252 * handling code performs scheduling operations which cannot be
258 * executed from within an interrupt context. 253 * executed from within an interrupt context.
259 */ 254 */
260 static irqreturn_t soc_common_pcmcia_interrupt(int irq, void *dev) 255 static irqreturn_t soc_common_pcmcia_interrupt(int irq, void *dev)
261 { 256 {
262 struct soc_pcmcia_socket *skt = dev; 257 struct soc_pcmcia_socket *skt = dev;
263 258
264 debug(skt, 3, "servicing IRQ %d\n", irq); 259 debug(skt, 3, "servicing IRQ %d\n", irq);
265 260
266 soc_common_check_status(skt); 261 soc_common_check_status(skt);
267 262
268 return IRQ_HANDLED; 263 return IRQ_HANDLED;
269 } 264 }
270 265
271 266
272 /* 267 /*
273 * Implements the get_status() operation for the in-kernel PCMCIA 268 * Implements the get_status() operation for the in-kernel PCMCIA
274 * service (formerly SS_GetStatus in Card Services). Essentially just 269 * service (formerly SS_GetStatus in Card Services). Essentially just
275 * fills in bits in `status' according to internal driver state or 270 * fills in bits in `status' according to internal driver state or
276 * the value of the voltage detect chipselect register. 271 * the value of the voltage detect chipselect register.
277 * 272 *
278 * As a debugging note, during card startup, the PCMCIA core issues 273 * As a debugging note, during card startup, the PCMCIA core issues
279 * three set_socket() commands in a row the first with RESET deasserted, 274 * three set_socket() commands in a row the first with RESET deasserted,
280 * the second with RESET asserted, and the last with RESET deasserted 275 * the second with RESET asserted, and the last with RESET deasserted
281 * again. Following the third set_socket(), a get_status() command will 276 * again. Following the third set_socket(), a get_status() command will
282 * be issued. The kernel is looking for the SS_READY flag (see 277 * be issued. The kernel is looking for the SS_READY flag (see
283 * setup_socket(), reset_socket(), and unreset_socket() in cs.c). 278 * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
284 * 279 *
285 * Returns: 0 280 * Returns: 0
286 */ 281 */
287 static int 282 static int
288 soc_common_pcmcia_get_status(struct pcmcia_socket *sock, unsigned int *status) 283 soc_common_pcmcia_get_status(struct pcmcia_socket *sock, unsigned int *status)
289 { 284 {
290 struct soc_pcmcia_socket *skt = to_soc_pcmcia_socket(sock); 285 struct soc_pcmcia_socket *skt = to_soc_pcmcia_socket(sock);
291 286
292 skt->status = soc_common_pcmcia_skt_state(skt); 287 skt->status = soc_common_pcmcia_skt_state(skt);
293 *status = skt->status; 288 *status = skt->status;
294 289
295 return 0; 290 return 0;
296 } 291 }
297 292
298 293
299 /* 294 /*
300 * Implements the set_socket() operation for the in-kernel PCMCIA 295 * Implements the set_socket() operation for the in-kernel PCMCIA
301 * service (formerly SS_SetSocket in Card Services). We more or 296 * service (formerly SS_SetSocket in Card Services). We more or
302 * less punt all of this work and let the kernel handle the details 297 * less punt all of this work and let the kernel handle the details
303 * of power configuration, reset, &c. We also record the value of 298 * of power configuration, reset, &c. We also record the value of
304 * `state' in order to regurgitate it to the PCMCIA core later. 299 * `state' in order to regurgitate it to the PCMCIA core later.
305 */ 300 */
306 static int 301 static int
307 soc_common_pcmcia_set_socket(struct pcmcia_socket *sock, socket_state_t *state) 302 soc_common_pcmcia_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
308 { 303 {
309 struct soc_pcmcia_socket *skt = to_soc_pcmcia_socket(sock); 304 struct soc_pcmcia_socket *skt = to_soc_pcmcia_socket(sock);
310 305
311 debug(skt, 2, "mask: %s%s%s%s%s%sflags: %s%s%s%s%s%sVcc %d Vpp %d irq %d\n", 306 debug(skt, 2, "mask: %s%s%s%s%s%sflags: %s%s%s%s%s%sVcc %d Vpp %d irq %d\n",
312 (state->csc_mask==0)?"<NONE> ":"", 307 (state->csc_mask==0)?"<NONE> ":"",
313 (state->csc_mask&SS_DETECT)?"DETECT ":"", 308 (state->csc_mask&SS_DETECT)?"DETECT ":"",
314 (state->csc_mask&SS_READY)?"READY ":"", 309 (state->csc_mask&SS_READY)?"READY ":"",
315 (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"", 310 (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"",
316 (state->csc_mask&SS_BATWARN)?"BATWARN ":"", 311 (state->csc_mask&SS_BATWARN)?"BATWARN ":"",
317 (state->csc_mask&SS_STSCHG)?"STSCHG ":"", 312 (state->csc_mask&SS_STSCHG)?"STSCHG ":"",
318 (state->flags==0)?"<NONE> ":"", 313 (state->flags==0)?"<NONE> ":"",
319 (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"", 314 (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"",
320 (state->flags&SS_IOCARD)?"IOCARD ":"", 315 (state->flags&SS_IOCARD)?"IOCARD ":"",
321 (state->flags&SS_RESET)?"RESET ":"", 316 (state->flags&SS_RESET)?"RESET ":"",
322 (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"", 317 (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"",
323 (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":"", 318 (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":"",
324 state->Vcc, state->Vpp, state->io_irq); 319 state->Vcc, state->Vpp, state->io_irq);
325 320
326 return soc_common_pcmcia_config_skt(skt, state); 321 return soc_common_pcmcia_config_skt(skt, state);
327 } 322 }
328 323
329 324
330 /* 325 /*
331 * Implements the set_io_map() operation for the in-kernel PCMCIA 326 * Implements the set_io_map() operation for the in-kernel PCMCIA
332 * service (formerly SS_SetIOMap in Card Services). We configure 327 * service (formerly SS_SetIOMap in Card Services). We configure
333 * the map speed as requested, but override the address ranges 328 * the map speed as requested, but override the address ranges
334 * supplied by Card Services. 329 * supplied by Card Services.
335 * 330 *
336 * Returns: 0 on success, -1 on error 331 * Returns: 0 on success, -1 on error
337 */ 332 */
338 static int 333 static int
339 soc_common_pcmcia_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *map) 334 soc_common_pcmcia_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *map)
340 { 335 {
341 struct soc_pcmcia_socket *skt = to_soc_pcmcia_socket(sock); 336 struct soc_pcmcia_socket *skt = to_soc_pcmcia_socket(sock);
342 unsigned short speed = map->speed; 337 unsigned short speed = map->speed;
343 338
344 debug(skt, 2, "map %u speed %u start 0x%08x stop 0x%08x\n", 339 debug(skt, 2, "map %u speed %u start 0x%08x stop 0x%08x\n",
345 map->map, map->speed, map->start, map->stop); 340 map->map, map->speed, map->start, map->stop);
346 debug(skt, 2, "flags: %s%s%s%s%s%s%s%s\n", 341 debug(skt, 2, "flags: %s%s%s%s%s%s%s%s\n",
347 (map->flags==0)?"<NONE>":"", 342 (map->flags==0)?"<NONE>":"",
348 (map->flags&MAP_ACTIVE)?"ACTIVE ":"", 343 (map->flags&MAP_ACTIVE)?"ACTIVE ":"",
349 (map->flags&MAP_16BIT)?"16BIT ":"", 344 (map->flags&MAP_16BIT)?"16BIT ":"",
350 (map->flags&MAP_AUTOSZ)?"AUTOSZ ":"", 345 (map->flags&MAP_AUTOSZ)?"AUTOSZ ":"",
351 (map->flags&MAP_0WS)?"0WS ":"", 346 (map->flags&MAP_0WS)?"0WS ":"",
352 (map->flags&MAP_WRPROT)?"WRPROT ":"", 347 (map->flags&MAP_WRPROT)?"WRPROT ":"",
353 (map->flags&MAP_USE_WAIT)?"USE_WAIT ":"", 348 (map->flags&MAP_USE_WAIT)?"USE_WAIT ":"",
354 (map->flags&MAP_PREFETCH)?"PREFETCH ":""); 349 (map->flags&MAP_PREFETCH)?"PREFETCH ":"");
355 350
356 if (map->map >= MAX_IO_WIN) { 351 if (map->map >= MAX_IO_WIN) {
357 printk(KERN_ERR "%s(): map (%d) out of range\n", __func__, 352 printk(KERN_ERR "%s(): map (%d) out of range\n", __func__,
358 map->map); 353 map->map);
359 return -1; 354 return -1;
360 } 355 }
361 356
362 if (map->flags & MAP_ACTIVE) { 357 if (map->flags & MAP_ACTIVE) {
363 if (speed == 0) 358 if (speed == 0)
364 speed = SOC_PCMCIA_IO_ACCESS; 359 speed = SOC_PCMCIA_IO_ACCESS;
365 } else { 360 } else {
366 speed = 0; 361 speed = 0;
367 } 362 }
368 363
369 skt->spd_io[map->map] = speed; 364 skt->spd_io[map->map] = speed;
370 skt->ops->set_timing(skt); 365 skt->ops->set_timing(skt);
371 366
372 if (map->stop == 1) 367 if (map->stop == 1)
373 map->stop = PAGE_SIZE-1; 368 map->stop = PAGE_SIZE-1;
374 369
375 map->stop -= map->start; 370 map->stop -= map->start;
376 map->stop += skt->socket.io_offset; 371 map->stop += skt->socket.io_offset;
377 map->start = skt->socket.io_offset; 372 map->start = skt->socket.io_offset;
378 373
379 return 0; 374 return 0;
380 } 375 }
381 376
382 377
383 /* 378 /*
384 * Implements the set_mem_map() operation for the in-kernel PCMCIA 379 * Implements the set_mem_map() operation for the in-kernel PCMCIA
385 * service (formerly SS_SetMemMap in Card Services). We configure 380 * service (formerly SS_SetMemMap in Card Services). We configure
386 * the map speed as requested, but override the address ranges 381 * the map speed as requested, but override the address ranges
387 * supplied by Card Services. 382 * supplied by Card Services.
388 * 383 *
389 * Returns: 0 on success, -ERRNO on error 384 * Returns: 0 on success, -ERRNO on error
390 */ 385 */
391 static int 386 static int
392 soc_common_pcmcia_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *map) 387 soc_common_pcmcia_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *map)
393 { 388 {
394 struct soc_pcmcia_socket *skt = to_soc_pcmcia_socket(sock); 389 struct soc_pcmcia_socket *skt = to_soc_pcmcia_socket(sock);
395 struct resource *res; 390 struct resource *res;
396 unsigned short speed = map->speed; 391 unsigned short speed = map->speed;
397 392
398 debug(skt, 2, "map %u speed %u card_start %08x\n", 393 debug(skt, 2, "map %u speed %u card_start %08x\n",
399 map->map, map->speed, map->card_start); 394 map->map, map->speed, map->card_start);
400 debug(skt, 2, "flags: %s%s%s%s%s%s%s%s\n", 395 debug(skt, 2, "flags: %s%s%s%s%s%s%s%s\n",
401 (map->flags==0)?"<NONE>":"", 396 (map->flags==0)?"<NONE>":"",
402 (map->flags&MAP_ACTIVE)?"ACTIVE ":"", 397 (map->flags&MAP_ACTIVE)?"ACTIVE ":"",
403 (map->flags&MAP_16BIT)?"16BIT ":"", 398 (map->flags&MAP_16BIT)?"16BIT ":"",
404 (map->flags&MAP_AUTOSZ)?"AUTOSZ ":"", 399 (map->flags&MAP_AUTOSZ)?"AUTOSZ ":"",
405 (map->flags&MAP_0WS)?"0WS ":"", 400 (map->flags&MAP_0WS)?"0WS ":"",
406 (map->flags&MAP_WRPROT)?"WRPROT ":"", 401 (map->flags&MAP_WRPROT)?"WRPROT ":"",
407 (map->flags&MAP_ATTRIB)?"ATTRIB ":"", 402 (map->flags&MAP_ATTRIB)?"ATTRIB ":"",
408 (map->flags&MAP_USE_WAIT)?"USE_WAIT ":""); 403 (map->flags&MAP_USE_WAIT)?"USE_WAIT ":"");
409 404
410 if (map->map >= MAX_WIN) 405 if (map->map >= MAX_WIN)
411 return -EINVAL; 406 return -EINVAL;
412 407
413 if (map->flags & MAP_ACTIVE) { 408 if (map->flags & MAP_ACTIVE) {
414 if (speed == 0) 409 if (speed == 0)
415 speed = 300; 410 speed = 300;
416 } else { 411 } else {
417 speed = 0; 412 speed = 0;
418 } 413 }
419 414
420 if (map->flags & MAP_ATTRIB) { 415 if (map->flags & MAP_ATTRIB) {
421 res = &skt->res_attr; 416 res = &skt->res_attr;
422 skt->spd_attr[map->map] = speed; 417 skt->spd_attr[map->map] = speed;
423 skt->spd_mem[map->map] = 0; 418 skt->spd_mem[map->map] = 0;
424 } else { 419 } else {
425 res = &skt->res_mem; 420 res = &skt->res_mem;
426 skt->spd_attr[map->map] = 0; 421 skt->spd_attr[map->map] = 0;
427 skt->spd_mem[map->map] = speed; 422 skt->spd_mem[map->map] = speed;
428 } 423 }
429 424
430 skt->ops->set_timing(skt); 425 skt->ops->set_timing(skt);
431 426
432 map->static_start = res->start + map->card_start; 427 map->static_start = res->start + map->card_start;
433 428
434 return 0; 429 return 0;
435 } 430 }
436 431
437 struct bittbl { 432 struct bittbl {
438 unsigned int mask; 433 unsigned int mask;
439 const char *name; 434 const char *name;
440 }; 435 };
441 436
442 static struct bittbl status_bits[] = { 437 static struct bittbl status_bits[] = {
443 { SS_WRPROT, "SS_WRPROT" }, 438 { SS_WRPROT, "SS_WRPROT" },
444 { SS_BATDEAD, "SS_BATDEAD" }, 439 { SS_BATDEAD, "SS_BATDEAD" },
445 { SS_BATWARN, "SS_BATWARN" }, 440 { SS_BATWARN, "SS_BATWARN" },
446 { SS_READY, "SS_READY" }, 441 { SS_READY, "SS_READY" },
447 { SS_DETECT, "SS_DETECT" }, 442 { SS_DETECT, "SS_DETECT" },
448 { SS_POWERON, "SS_POWERON" }, 443 { SS_POWERON, "SS_POWERON" },
449 { SS_STSCHG, "SS_STSCHG" }, 444 { SS_STSCHG, "SS_STSCHG" },
450 { SS_3VCARD, "SS_3VCARD" }, 445 { SS_3VCARD, "SS_3VCARD" },
451 { SS_XVCARD, "SS_XVCARD" }, 446 { SS_XVCARD, "SS_XVCARD" },
452 }; 447 };
453 448
454 static struct bittbl conf_bits[] = { 449 static struct bittbl conf_bits[] = {
455 { SS_PWR_AUTO, "SS_PWR_AUTO" }, 450 { SS_PWR_AUTO, "SS_PWR_AUTO" },
456 { SS_IOCARD, "SS_IOCARD" }, 451 { SS_IOCARD, "SS_IOCARD" },
457 { SS_RESET, "SS_RESET" }, 452 { SS_RESET, "SS_RESET" },
458 { SS_DMA_MODE, "SS_DMA_MODE" }, 453 { SS_DMA_MODE, "SS_DMA_MODE" },
459 { SS_SPKR_ENA, "SS_SPKR_ENA" }, 454 { SS_SPKR_ENA, "SS_SPKR_ENA" },
460 { SS_OUTPUT_ENA, "SS_OUTPUT_ENA" }, 455 { SS_OUTPUT_ENA, "SS_OUTPUT_ENA" },
461 }; 456 };
462 457
463 static void 458 static void
464 dump_bits(char **p, const char *prefix, unsigned int val, struct bittbl *bits, int sz) 459 dump_bits(char **p, const char *prefix, unsigned int val, struct bittbl *bits, int sz)
465 { 460 {
466 char *b = *p; 461 char *b = *p;
467 int i; 462 int i;
468 463
469 b += sprintf(b, "%-9s:", prefix); 464 b += sprintf(b, "%-9s:", prefix);
470 for (i = 0; i < sz; i++) 465 for (i = 0; i < sz; i++)
471 if (val & bits[i].mask) 466 if (val & bits[i].mask)
472 b += sprintf(b, " %s", bits[i].name); 467 b += sprintf(b, " %s", bits[i].name);
473 *b++ = '\n'; 468 *b++ = '\n';
474 *p = b; 469 *p = b;
475 } 470 }
476 471
477 /* 472 /*
478 * Implements the /sys/class/pcmcia_socket/??/status file. 473 * Implements the /sys/class/pcmcia_socket/??/status file.
479 * 474 *
480 * Returns: the number of characters added to the buffer 475 * Returns: the number of characters added to the buffer
481 */ 476 */
482 static ssize_t show_status(struct device *dev, struct device_attribute *attr, char *buf) 477 static ssize_t show_status(struct device *dev, struct device_attribute *attr, char *buf)
483 { 478 {
484 struct soc_pcmcia_socket *skt = 479 struct soc_pcmcia_socket *skt =
485 container_of(dev, struct soc_pcmcia_socket, socket.dev); 480 container_of(dev, struct soc_pcmcia_socket, socket.dev);
486 char *p = buf; 481 char *p = buf;
487 482
488 p+=sprintf(p, "slot : %d\n", skt->nr); 483 p+=sprintf(p, "slot : %d\n", skt->nr);
489 484
490 dump_bits(&p, "status", skt->status, 485 dump_bits(&p, "status", skt->status,
491 status_bits, ARRAY_SIZE(status_bits)); 486 status_bits, ARRAY_SIZE(status_bits));
492 dump_bits(&p, "csc_mask", skt->cs_state.csc_mask, 487 dump_bits(&p, "csc_mask", skt->cs_state.csc_mask,
493 status_bits, ARRAY_SIZE(status_bits)); 488 status_bits, ARRAY_SIZE(status_bits));
494 dump_bits(&p, "cs_flags", skt->cs_state.flags, 489 dump_bits(&p, "cs_flags", skt->cs_state.flags,
495 conf_bits, ARRAY_SIZE(conf_bits)); 490 conf_bits, ARRAY_SIZE(conf_bits));
496 491
497 p+=sprintf(p, "Vcc : %d\n", skt->cs_state.Vcc); 492 p+=sprintf(p, "Vcc : %d\n", skt->cs_state.Vcc);
498 p+=sprintf(p, "Vpp : %d\n", skt->cs_state.Vpp); 493 p+=sprintf(p, "Vpp : %d\n", skt->cs_state.Vpp);
499 p+=sprintf(p, "IRQ : %d (%d)\n", skt->cs_state.io_irq, skt->irq); 494 p+=sprintf(p, "IRQ : %d (%d)\n", skt->cs_state.io_irq, skt->irq);
500 if (skt->ops->show_timing) 495 if (skt->ops->show_timing)
501 p+=skt->ops->show_timing(skt, p); 496 p+=skt->ops->show_timing(skt, p);
502 497
503 return p-buf; 498 return p-buf;
504 } 499 }
505 static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); 500 static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
506 501
507 502
508 static struct pccard_operations soc_common_pcmcia_operations = { 503 static struct pccard_operations soc_common_pcmcia_operations = {
509 .init = soc_common_pcmcia_sock_init, 504 .init = soc_common_pcmcia_sock_init,
510 .suspend = soc_common_pcmcia_suspend, 505 .suspend = soc_common_pcmcia_suspend,
511 .get_status = soc_common_pcmcia_get_status, 506 .get_status = soc_common_pcmcia_get_status,
512 .set_socket = soc_common_pcmcia_set_socket, 507 .set_socket = soc_common_pcmcia_set_socket,
513 .set_io_map = soc_common_pcmcia_set_io_map, 508 .set_io_map = soc_common_pcmcia_set_io_map,
514 .set_mem_map = soc_common_pcmcia_set_mem_map, 509 .set_mem_map = soc_common_pcmcia_set_mem_map,
515 }; 510 };
516 511
517 512
518 int soc_pcmcia_request_irqs(struct soc_pcmcia_socket *skt, 513 int soc_pcmcia_request_irqs(struct soc_pcmcia_socket *skt,
519 struct pcmcia_irqs *irqs, int nr) 514 struct pcmcia_irqs *irqs, int nr)
520 { 515 {
521 int i, res = 0; 516 int i, res = 0;
522 517
523 for (i = 0; i < nr; i++) { 518 for (i = 0; i < nr; i++) {
524 if (irqs[i].sock != skt->nr) 519 if (irqs[i].sock != skt->nr)
525 continue; 520 continue;
526 res = request_irq(irqs[i].irq, soc_common_pcmcia_interrupt, 521 res = request_irq(irqs[i].irq, soc_common_pcmcia_interrupt,
527 IRQF_DISABLED, irqs[i].str, skt); 522 IRQF_DISABLED, irqs[i].str, skt);
528 if (res) 523 if (res)
529 break; 524 break;
530 set_irq_type(irqs[i].irq, IRQ_TYPE_NONE); 525 set_irq_type(irqs[i].irq, IRQ_TYPE_NONE);
531 } 526 }
532 527
533 if (res) { 528 if (res) {
534 printk(KERN_ERR "PCMCIA: request for IRQ%d failed (%d)\n", 529 printk(KERN_ERR "PCMCIA: request for IRQ%d failed (%d)\n",
535 irqs[i].irq, res); 530 irqs[i].irq, res);
536 531
537 while (i--) 532 while (i--)
538 if (irqs[i].sock == skt->nr) 533 if (irqs[i].sock == skt->nr)
539 free_irq(irqs[i].irq, skt); 534 free_irq(irqs[i].irq, skt);
540 } 535 }
541 return res; 536 return res;
542 } 537 }
543 EXPORT_SYMBOL(soc_pcmcia_request_irqs); 538 EXPORT_SYMBOL(soc_pcmcia_request_irqs);
544 539
545 void soc_pcmcia_free_irqs(struct soc_pcmcia_socket *skt, 540 void soc_pcmcia_free_irqs(struct soc_pcmcia_socket *skt,
546 struct pcmcia_irqs *irqs, int nr) 541 struct pcmcia_irqs *irqs, int nr)
547 { 542 {
548 int i; 543 int i;
549 544
550 for (i = 0; i < nr; i++) 545 for (i = 0; i < nr; i++)
551 if (irqs[i].sock == skt->nr) 546 if (irqs[i].sock == skt->nr)
552 free_irq(irqs[i].irq, skt); 547 free_irq(irqs[i].irq, skt);
553 } 548 }
554 EXPORT_SYMBOL(soc_pcmcia_free_irqs); 549 EXPORT_SYMBOL(soc_pcmcia_free_irqs);
555 550
556 void soc_pcmcia_disable_irqs(struct soc_pcmcia_socket *skt, 551 void soc_pcmcia_disable_irqs(struct soc_pcmcia_socket *skt,
557 struct pcmcia_irqs *irqs, int nr) 552 struct pcmcia_irqs *irqs, int nr)
558 { 553 {
559 int i; 554 int i;
560 555
561 for (i = 0; i < nr; i++) 556 for (i = 0; i < nr; i++)
562 if (irqs[i].sock == skt->nr) 557 if (irqs[i].sock == skt->nr)
563 set_irq_type(irqs[i].irq, IRQ_TYPE_NONE); 558 set_irq_type(irqs[i].irq, IRQ_TYPE_NONE);
564 } 559 }
565 EXPORT_SYMBOL(soc_pcmcia_disable_irqs); 560 EXPORT_SYMBOL(soc_pcmcia_disable_irqs);
566 561
567 void soc_pcmcia_enable_irqs(struct soc_pcmcia_socket *skt, 562 void soc_pcmcia_enable_irqs(struct soc_pcmcia_socket *skt,
568 struct pcmcia_irqs *irqs, int nr) 563 struct pcmcia_irqs *irqs, int nr)
569 { 564 {
570 int i; 565 int i;
571 566
572 for (i = 0; i < nr; i++) 567 for (i = 0; i < nr; i++)
573 if (irqs[i].sock == skt->nr) { 568 if (irqs[i].sock == skt->nr) {
574 set_irq_type(irqs[i].irq, IRQ_TYPE_EDGE_RISING); 569 set_irq_type(irqs[i].irq, IRQ_TYPE_EDGE_RISING);
575 set_irq_type(irqs[i].irq, IRQ_TYPE_EDGE_BOTH); 570 set_irq_type(irqs[i].irq, IRQ_TYPE_EDGE_BOTH);
576 } 571 }
577 } 572 }
578 EXPORT_SYMBOL(soc_pcmcia_enable_irqs); 573 EXPORT_SYMBOL(soc_pcmcia_enable_irqs);
579 574
580 575
581 LIST_HEAD(soc_pcmcia_sockets); 576 LIST_HEAD(soc_pcmcia_sockets);
582 static DEFINE_MUTEX(soc_pcmcia_sockets_lock); 577 static DEFINE_MUTEX(soc_pcmcia_sockets_lock);
583 578
584 static const char *skt_names[] = {
585 "PCMCIA socket 0",
586 "PCMCIA socket 1",
587 };
588
589 struct skt_dev_info {
590 int nskt;
591 struct soc_pcmcia_socket skt[0];
592 };
593
594 #define SKT_DEV_INFO_SIZE(n) \
595 (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
596
597 #ifdef CONFIG_CPU_FREQ 579 #ifdef CONFIG_CPU_FREQ
598 static int 580 static int
599 soc_pcmcia_notifier(struct notifier_block *nb, unsigned long val, void *data) 581 soc_pcmcia_notifier(struct notifier_block *nb, unsigned long val, void *data)
600 { 582 {
601 struct soc_pcmcia_socket *skt; 583 struct soc_pcmcia_socket *skt;
602 struct cpufreq_freqs *freqs = data; 584 struct cpufreq_freqs *freqs = data;
603 int ret = 0; 585 int ret = 0;
604 586
605 mutex_lock(&soc_pcmcia_sockets_lock); 587 mutex_lock(&soc_pcmcia_sockets_lock);
606 list_for_each_entry(skt, &soc_pcmcia_sockets, node) 588 list_for_each_entry(skt, &soc_pcmcia_sockets, node)
607 if ( skt->ops->frequency_change ) 589 if ( skt->ops->frequency_change )
608 ret += skt->ops->frequency_change(skt, val, freqs); 590 ret += skt->ops->frequency_change(skt, val, freqs);
609 mutex_unlock(&soc_pcmcia_sockets_lock); 591 mutex_unlock(&soc_pcmcia_sockets_lock);
610 592
611 return ret; 593 return ret;
612 } 594 }
613 595
614 static struct notifier_block soc_pcmcia_notifier_block = { 596 static struct notifier_block soc_pcmcia_notifier_block = {
615 .notifier_call = soc_pcmcia_notifier 597 .notifier_call = soc_pcmcia_notifier
616 }; 598 };
617 599
618 static int soc_pcmcia_cpufreq_register(void) 600 static int soc_pcmcia_cpufreq_register(void)
619 { 601 {
620 int ret; 602 int ret;
621 603
622 ret = cpufreq_register_notifier(&soc_pcmcia_notifier_block, 604 ret = cpufreq_register_notifier(&soc_pcmcia_notifier_block,
623 CPUFREQ_TRANSITION_NOTIFIER); 605 CPUFREQ_TRANSITION_NOTIFIER);
624 if (ret < 0) 606 if (ret < 0)
625 printk(KERN_ERR "Unable to register CPU frequency change " 607 printk(KERN_ERR "Unable to register CPU frequency change "
626 "notifier for PCMCIA (%d)\n", ret); 608 "notifier for PCMCIA (%d)\n", ret);
627 return ret; 609 return ret;
628 } 610 }
629 611
630 static void soc_pcmcia_cpufreq_unregister(void) 612 static void soc_pcmcia_cpufreq_unregister(void)
631 { 613 {
632 cpufreq_unregister_notifier(&soc_pcmcia_notifier_block, CPUFREQ_TRANSITION_NOTIFIER); 614 cpufreq_unregister_notifier(&soc_pcmcia_notifier_block, CPUFREQ_TRANSITION_NOTIFIER);
633 } 615 }
634 616
635 #else 617 #else
636 static int soc_pcmcia_cpufreq_register(void) { return 0; } 618 static int soc_pcmcia_cpufreq_register(void) { return 0; }
637 static void soc_pcmcia_cpufreq_unregister(void) {} 619 static void soc_pcmcia_cpufreq_unregister(void) {}
638 #endif 620 #endif
639 621
640 int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr) 622 int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops,
623 struct skt_dev_info *sinfo)
641 { 624 {
642 struct skt_dev_info *sinfo;
643 struct soc_pcmcia_socket *skt; 625 struct soc_pcmcia_socket *skt;
644 int ret, i; 626 int ret, i;
645 627
646 mutex_lock(&soc_pcmcia_sockets_lock); 628 mutex_lock(&soc_pcmcia_sockets_lock);
647 629
648 sinfo = kzalloc(SKT_DEV_INFO_SIZE(nr), GFP_KERNEL);
649 if (!sinfo) {
650 ret = -ENOMEM;
651 goto out;
652 }
653
654 sinfo->nskt = nr;
655
656 /* 630 /*
657 * Initialise the per-socket structure. 631 * Initialise the per-socket structure.
658 */ 632 */
659 for (i = 0; i < nr; i++) { 633 for (i = 0; i < sinfo->nskt; i++) {
660 skt = &sinfo->skt[i]; 634 skt = &sinfo->skt[i];
661 635
662 skt->socket.ops = &soc_common_pcmcia_operations; 636 skt->socket.ops = &soc_common_pcmcia_operations;
663 skt->socket.owner = ops->owner; 637 skt->socket.owner = ops->owner;
664 skt->socket.dev.parent = dev; 638 skt->socket.dev.parent = dev;
665 639
666 init_timer(&skt->poll_timer); 640 init_timer(&skt->poll_timer);
667 skt->poll_timer.function = soc_common_pcmcia_poll_event; 641 skt->poll_timer.function = soc_common_pcmcia_poll_event;
668 skt->poll_timer.data = (unsigned long)skt; 642 skt->poll_timer.data = (unsigned long)skt;
669 skt->poll_timer.expires = jiffies + SOC_PCMCIA_POLL_PERIOD; 643 skt->poll_timer.expires = jiffies + SOC_PCMCIA_POLL_PERIOD;
670 644
671 skt->nr = first + i;
672 skt->irq = NO_IRQ;
673 skt->dev = dev; 645 skt->dev = dev;
674 skt->ops = ops; 646 skt->ops = ops;
675 647
676 skt->res_skt.start = _PCMCIA(skt->nr);
677 skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
678 skt->res_skt.name = skt_names[skt->nr];
679 skt->res_skt.flags = IORESOURCE_MEM;
680
681 ret = request_resource(&iomem_resource, &skt->res_skt); 648 ret = request_resource(&iomem_resource, &skt->res_skt);
682 if (ret) 649 if (ret)
683 goto out_err_1; 650 goto out_err_1;
684 651
685 skt->res_io.start = _PCMCIAIO(skt->nr);
686 skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
687 skt->res_io.name = "io";
688 skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
689
690 ret = request_resource(&skt->res_skt, &skt->res_io); 652 ret = request_resource(&skt->res_skt, &skt->res_io);
691 if (ret) 653 if (ret)
692 goto out_err_2; 654 goto out_err_2;
693 655
694 skt->res_mem.start = _PCMCIAMem(skt->nr);
695 skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
696 skt->res_mem.name = "memory";
697 skt->res_mem.flags = IORESOURCE_MEM;
698
699 ret = request_resource(&skt->res_skt, &skt->res_mem); 656 ret = request_resource(&skt->res_skt, &skt->res_mem);
700 if (ret) 657 if (ret)
701 goto out_err_3; 658 goto out_err_3;
702
703 skt->res_attr.start = _PCMCIAAttr(skt->nr);
704 skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
705 skt->res_attr.name = "attribute";
706 skt->res_attr.flags = IORESOURCE_MEM;
707 659
708 ret = request_resource(&skt->res_skt, &skt->res_attr); 660 ret = request_resource(&skt->res_skt, &skt->res_attr);
709 if (ret) 661 if (ret)
710 goto out_err_4; 662 goto out_err_4;
711 663
712 skt->virt_io = ioremap(skt->res_io.start, 0x10000); 664 skt->virt_io = ioremap(skt->res_io.start, 0x10000);
713 if (skt->virt_io == NULL) { 665 if (skt->virt_io == NULL) {
714 ret = -ENOMEM; 666 ret = -ENOMEM;
715 goto out_err_5; 667 goto out_err_5;
716 } 668 }
717 669
718 if (list_empty(&soc_pcmcia_sockets)) 670 if (list_empty(&soc_pcmcia_sockets))
719 soc_pcmcia_cpufreq_register(); 671 soc_pcmcia_cpufreq_register();
720 672
721 list_add(&skt->node, &soc_pcmcia_sockets); 673 list_add(&skt->node, &soc_pcmcia_sockets);
722 674
723 /* 675 /*
724 * We initialize default socket timing here, because 676 * We initialize default socket timing here, because
725 * we are not guaranteed to see a SetIOMap operation at 677 * we are not guaranteed to see a SetIOMap operation at
726 * runtime. 678 * runtime.
727 */ 679 */
728 ops->set_timing(skt); 680 ops->set_timing(skt);
729 681
730 ret = ops->hw_init(skt); 682 ret = ops->hw_init(skt);
731 if (ret) 683 if (ret)
732 goto out_err_6; 684 goto out_err_6;
733 685
734 skt->socket.features = SS_CAP_STATIC_MAP|SS_CAP_PCCARD; 686 skt->socket.features = SS_CAP_STATIC_MAP|SS_CAP_PCCARD;
735 skt->socket.resource_ops = &pccard_static_ops; 687 skt->socket.resource_ops = &pccard_static_ops;
736 skt->socket.irq_mask = 0; 688 skt->socket.irq_mask = 0;
737 skt->socket.map_size = PAGE_SIZE; 689 skt->socket.map_size = PAGE_SIZE;
738 skt->socket.pci_irq = skt->irq; 690 skt->socket.pci_irq = skt->irq;
739 skt->socket.io_offset = (unsigned long)skt->virt_io; 691 skt->socket.io_offset = (unsigned long)skt->virt_io;
740 692
741 skt->status = soc_common_pcmcia_skt_state(skt); 693 skt->status = soc_common_pcmcia_skt_state(skt);
742 694
743 ret = pcmcia_register_socket(&skt->socket); 695 ret = pcmcia_register_socket(&skt->socket);
744 if (ret) 696 if (ret)
745 goto out_err_7; 697 goto out_err_7;
746 698
747 WARN_ON(skt->socket.sock != i); 699 WARN_ON(skt->socket.sock != i);
748 700
749 add_timer(&skt->poll_timer); 701 add_timer(&skt->poll_timer);
750 702
751 ret = device_create_file(&skt->socket.dev, &dev_attr_status); 703 ret = device_create_file(&skt->socket.dev, &dev_attr_status);
752 if (ret) 704 if (ret)
753 goto out_err_8; 705 goto out_err_8;
754 } 706 }
755 707
756 dev_set_drvdata(dev, sinfo); 708 dev_set_drvdata(dev, sinfo);
757 ret = 0; 709 ret = 0;
758 goto out; 710 goto out;
759 711
760 do { 712 do {
761 skt = &sinfo->skt[i]; 713 skt = &sinfo->skt[i];
762 714
763 device_remove_file(&skt->socket.dev, &dev_attr_status); 715 device_remove_file(&skt->socket.dev, &dev_attr_status);
764 out_err_8: 716 out_err_8:
765 del_timer_sync(&skt->poll_timer); 717 del_timer_sync(&skt->poll_timer);
766 pcmcia_unregister_socket(&skt->socket); 718 pcmcia_unregister_socket(&skt->socket);
767 719
768 out_err_7: 720 out_err_7:
769 flush_scheduled_work(); 721 flush_scheduled_work();
770 722
771 ops->hw_shutdown(skt); 723 ops->hw_shutdown(skt);
772 out_err_6: 724 out_err_6:
773 list_del(&skt->node); 725 list_del(&skt->node);
774 iounmap(skt->virt_io); 726 iounmap(skt->virt_io);
775 out_err_5: 727 out_err_5:
776 release_resource(&skt->res_attr); 728 release_resource(&skt->res_attr);
777 out_err_4: 729 out_err_4:
778 release_resource(&skt->res_mem); 730 release_resource(&skt->res_mem);
779 out_err_3: 731 out_err_3:
780 release_resource(&skt->res_io); 732 release_resource(&skt->res_io);
781 out_err_2: 733 out_err_2:
782 release_resource(&skt->res_skt); 734 release_resource(&skt->res_skt);
783 out_err_1: 735 out_err_1:
784 i--; 736 i--;
785 } while (i > 0); 737 } while (i > 0);
786 738
787 kfree(sinfo); 739 kfree(sinfo);
788 740
789 out: 741 out:
790 mutex_unlock(&soc_pcmcia_sockets_lock); 742 mutex_unlock(&soc_pcmcia_sockets_lock);
791 return ret; 743 return ret;
792 } 744 }
793 745
794 int soc_common_drv_pcmcia_remove(struct device *dev) 746 int soc_common_drv_pcmcia_remove(struct device *dev)
795 { 747 {
796 struct skt_dev_info *sinfo = dev_get_drvdata(dev); 748 struct skt_dev_info *sinfo = dev_get_drvdata(dev);
797 int i; 749 int i;
798 750
799 dev_set_drvdata(dev, NULL); 751 dev_set_drvdata(dev, NULL);
800 752
801 mutex_lock(&soc_pcmcia_sockets_lock); 753 mutex_lock(&soc_pcmcia_sockets_lock);
802 for (i = 0; i < sinfo->nskt; i++) { 754 for (i = 0; i < sinfo->nskt; i++) {
803 struct soc_pcmcia_socket *skt = &sinfo->skt[i]; 755 struct soc_pcmcia_socket *skt = &sinfo->skt[i];
804 756
805 del_timer_sync(&skt->poll_timer); 757 del_timer_sync(&skt->poll_timer);
806 758
807 pcmcia_unregister_socket(&skt->socket); 759 pcmcia_unregister_socket(&skt->socket);
808 760
809 flush_scheduled_work(); 761 flush_scheduled_work();
810 762
811 skt->ops->hw_shutdown(skt); 763 skt->ops->hw_shutdown(skt);
812 764
813 soc_common_pcmcia_config_skt(skt, &dead_socket); 765 soc_common_pcmcia_config_skt(skt, &dead_socket);
814 766
815 list_del(&skt->node); 767 list_del(&skt->node);
816 iounmap(skt->virt_io); 768 iounmap(skt->virt_io);
817 skt->virt_io = NULL; 769 skt->virt_io = NULL;
818 release_resource(&skt->res_attr); 770 release_resource(&skt->res_attr);
819 release_resource(&skt->res_mem); 771 release_resource(&skt->res_mem);
820 release_resource(&skt->res_io); 772 release_resource(&skt->res_io);
821 release_resource(&skt->res_skt); 773 release_resource(&skt->res_skt);
822 } 774 }
823 if (list_empty(&soc_pcmcia_sockets)) 775 if (list_empty(&soc_pcmcia_sockets))
824 soc_pcmcia_cpufreq_unregister(); 776 soc_pcmcia_cpufreq_unregister();
825 777
826 mutex_unlock(&soc_pcmcia_sockets_lock); 778 mutex_unlock(&soc_pcmcia_sockets_lock);
827 779
828 kfree(sinfo); 780 kfree(sinfo);
829 781
830 return 0; 782 return 0;
831 } 783 }
832 EXPORT_SYMBOL(soc_common_drv_pcmcia_remove); 784 EXPORT_SYMBOL(soc_common_drv_pcmcia_remove);
drivers/pcmcia/soc_common.h
Diff comments   View file @ b393c69
1 /* 1 /*
2 * linux/drivers/pcmcia/soc_common.h 2 * linux/drivers/pcmcia/soc_common.h
3 * 3 *
4 * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu> 4 * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
5 * 5 *
6 * This file contains definitions for the PCMCIA support code common to 6 * This file contains definitions for the PCMCIA support code common to
7 * integrated SOCs like the SA-11x0 and PXA2xx microprocessors. 7 * integrated SOCs like the SA-11x0 and PXA2xx microprocessors.
8 */ 8 */
9 #ifndef _ASM_ARCH_PCMCIA 9 #ifndef _ASM_ARCH_PCMCIA
10 #define _ASM_ARCH_PCMCIA 10 #define _ASM_ARCH_PCMCIA
11 11
12 /* include the world */ 12 /* include the world */
13 #include <linux/cpufreq.h> 13 #include <linux/cpufreq.h>
14 #include <pcmcia/cs_types.h> 14 #include <pcmcia/cs_types.h>
15 #include <pcmcia/cs.h> 15 #include <pcmcia/cs.h>
16 #include <pcmcia/ss.h> 16 #include <pcmcia/ss.h>
17 #include <pcmcia/cistpl.h> 17 #include <pcmcia/cistpl.h>
18 18
19 19
20 struct device; 20 struct device;
21 struct pcmcia_low_level; 21 struct pcmcia_low_level;
22 22
23 /* 23 /*
24 * This structure encapsulates per-socket state which we might need to 24 * This structure encapsulates per-socket state which we might need to
25 * use when responding to a Card Services query of some kind. 25 * use when responding to a Card Services query of some kind.
26 */ 26 */
27 struct soc_pcmcia_socket { 27 struct soc_pcmcia_socket {
28 struct pcmcia_socket socket; 28 struct pcmcia_socket socket;
29 29
30 /* 30 /*
31 * Info from low level handler 31 * Info from low level handler
32 */ 32 */
33 struct device *dev; 33 struct device *dev;
34 unsigned int nr; 34 unsigned int nr;
35 unsigned int irq; 35 unsigned int irq;
36 36
37 /* 37 /*
38 * Core PCMCIA state 38 * Core PCMCIA state
39 */ 39 */
40 struct pcmcia_low_level *ops; 40 struct pcmcia_low_level *ops;
41 41
42 unsigned int status; 42 unsigned int status;
43 socket_state_t cs_state; 43 socket_state_t cs_state;
44 44
45 unsigned short spd_io[MAX_IO_WIN]; 45 unsigned short spd_io[MAX_IO_WIN];
46 unsigned short spd_mem[MAX_WIN]; 46 unsigned short spd_mem[MAX_WIN];
47 unsigned short spd_attr[MAX_WIN]; 47 unsigned short spd_attr[MAX_WIN];
48 48
49 struct resource res_skt; 49 struct resource res_skt;
50 struct resource res_io; 50 struct resource res_io;
51 struct resource res_mem; 51 struct resource res_mem;
52 struct resource res_attr; 52 struct resource res_attr;
53 void __iomem *virt_io; 53 void __iomem *virt_io;
54 54
55 unsigned int irq_state; 55 unsigned int irq_state;
56 56
57 struct timer_list poll_timer; 57 struct timer_list poll_timer;
58 struct list_head node; 58 struct list_head node;
59 }; 59 };
60 60
61 struct skt_dev_info {
62 int nskt;
63 struct soc_pcmcia_socket skt[0];
64 };
65
61 struct pcmcia_state { 66 struct pcmcia_state {
62 unsigned detect: 1, 67 unsigned detect: 1,
63 ready: 1, 68 ready: 1,
64 bvd1: 1, 69 bvd1: 1,
65 bvd2: 1, 70 bvd2: 1,
66 wrprot: 1, 71 wrprot: 1,
67 vs_3v: 1, 72 vs_3v: 1,
68 vs_Xv: 1; 73 vs_Xv: 1;
69 }; 74 };
70 75
71 struct pcmcia_low_level { 76 struct pcmcia_low_level {
72 struct module *owner; 77 struct module *owner;
73 78
74 /* first socket in system */ 79 /* first socket in system */
75 int first; 80 int first;
76 /* nr of sockets */ 81 /* nr of sockets */
77 int nr; 82 int nr;
78 83
79 int (*hw_init)(struct soc_pcmcia_socket *); 84 int (*hw_init)(struct soc_pcmcia_socket *);
80 void (*hw_shutdown)(struct soc_pcmcia_socket *); 85 void (*hw_shutdown)(struct soc_pcmcia_socket *);
81 86
82 void (*socket_state)(struct soc_pcmcia_socket *, struct pcmcia_state *); 87 void (*socket_state)(struct soc_pcmcia_socket *, struct pcmcia_state *);
83 int (*configure_socket)(struct soc_pcmcia_socket *, const socket_state_t *); 88 int (*configure_socket)(struct soc_pcmcia_socket *, const socket_state_t *);
84 89
85 /* 90 /*
86 * Enable card status IRQs on (re-)initialisation. This can 91 * Enable card status IRQs on (re-)initialisation. This can
87 * be called at initialisation, power management event, or 92 * be called at initialisation, power management event, or
88 * pcmcia event. 93 * pcmcia event.
89 */ 94 */
90 void (*socket_init)(struct soc_pcmcia_socket *); 95 void (*socket_init)(struct soc_pcmcia_socket *);
91 96
92 /* 97 /*
93 * Disable card status IRQs and PCMCIA bus on suspend. 98 * Disable card status IRQs and PCMCIA bus on suspend.
94 */ 99 */
95 void (*socket_suspend)(struct soc_pcmcia_socket *); 100 void (*socket_suspend)(struct soc_pcmcia_socket *);
96 101
97 /* 102 /*
98 * Hardware specific timing routines. 103 * Hardware specific timing routines.
99 * If provided, the get_timing routine overrides the SOC default. 104 * If provided, the get_timing routine overrides the SOC default.
100 */ 105 */
101 unsigned int (*get_timing)(struct soc_pcmcia_socket *, unsigned int, unsigned int); 106 unsigned int (*get_timing)(struct soc_pcmcia_socket *, unsigned int, unsigned int);
102 int (*set_timing)(struct soc_pcmcia_socket *); 107 int (*set_timing)(struct soc_pcmcia_socket *);
103 int (*show_timing)(struct soc_pcmcia_socket *, char *); 108 int (*show_timing)(struct soc_pcmcia_socket *, char *);
104 109
105 #ifdef CONFIG_CPU_FREQ 110 #ifdef CONFIG_CPU_FREQ
106 /* 111 /*
107 * CPUFREQ support. 112 * CPUFREQ support.
108 */ 113 */
109 int (*frequency_change)(struct soc_pcmcia_socket *, unsigned long, struct cpufreq_freqs *); 114 int (*frequency_change)(struct soc_pcmcia_socket *, unsigned long, struct cpufreq_freqs *);
110 #endif 115 #endif
111 }; 116 };
112 117
113 118
114 struct pcmcia_irqs { 119 struct pcmcia_irqs {
115 int sock; 120 int sock;
116 int irq; 121 int irq;
117 const char *str; 122 const char *str;
118 }; 123 };
119 124
120 struct soc_pcmcia_timing { 125 struct soc_pcmcia_timing {
121 unsigned short io; 126 unsigned short io;
122 unsigned short mem; 127 unsigned short mem;
123 unsigned short attr; 128 unsigned short attr;
124 }; 129 };
125 130
126 extern int soc_pcmcia_request_irqs(struct soc_pcmcia_socket *skt, struct pcmcia_irqs *irqs, int nr); 131 extern int soc_pcmcia_request_irqs(struct soc_pcmcia_socket *skt, struct pcmcia_irqs *irqs, int nr);
127 extern void soc_pcmcia_free_irqs(struct soc_pcmcia_socket *skt, struct pcmcia_irqs *irqs, int nr); 132 extern void soc_pcmcia_free_irqs(struct soc_pcmcia_socket *skt, struct pcmcia_irqs *irqs, int nr);
128 extern void soc_pcmcia_disable_irqs(struct soc_pcmcia_socket *skt, struct pcmcia_irqs *irqs, int nr); 133 extern void soc_pcmcia_disable_irqs(struct soc_pcmcia_socket *skt, struct pcmcia_irqs *irqs, int nr);
129 extern void soc_pcmcia_enable_irqs(struct soc_pcmcia_socket *skt, struct pcmcia_irqs *irqs, int nr); 134 extern void soc_pcmcia_enable_irqs(struct soc_pcmcia_socket *skt, struct pcmcia_irqs *irqs, int nr);
130 extern void soc_common_pcmcia_get_timing(struct soc_pcmcia_socket *, struct soc_pcmcia_timing *); 135 extern void soc_common_pcmcia_get_timing(struct soc_pcmcia_socket *, struct soc_pcmcia_timing *);
131 136
132 137
133 extern struct list_head soc_pcmcia_sockets; 138 extern struct list_head soc_pcmcia_sockets;
134 139
135 extern int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr); 140 extern int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, struct skt_dev_info *sinfo);
136 extern int soc_common_drv_pcmcia_remove(struct device *dev); 141 extern int soc_common_drv_pcmcia_remove(struct device *dev);
137 142
138 143
139 #ifdef CONFIG_PCMCIA_DEBUG 144 #ifdef CONFIG_PCMCIA_DEBUG
140 145
141 extern void soc_pcmcia_debug(struct soc_pcmcia_socket *skt, const char *func, 146 extern void soc_pcmcia_debug(struct soc_pcmcia_socket *skt, const char *func,
142 int lvl, const char *fmt, ...); 147 int lvl, const char *fmt, ...);
143 148
144 #define debug(skt, lvl, fmt, arg...) \ 149 #define debug(skt, lvl, fmt, arg...) \
145 soc_pcmcia_debug(skt, __func__, lvl, fmt , ## arg) 150 soc_pcmcia_debug(skt, __func__, lvl, fmt , ## arg)
146 151
147 #else 152 #else
148 #define debug(skt, lvl, fmt, arg...) do { } while (0) 153 #define debug(skt, lvl, fmt, arg...) do { } while (0)
149 #endif 154 #endif
150 155
151 156
152 /* 157 /*
153 * The PC Card Standard, Release 7, section 4.13.4, says that twIORD 158 * The PC Card Standard, Release 7, section 4.13.4, says that twIORD
154 * has a minimum value of 165ns. Section 4.13.5 says that twIOWR has 159 * has a minimum value of 165ns. Section 4.13.5 says that twIOWR has
155 * a minimum value of 165ns, as well. Section 4.7.2 (describing 160 * a minimum value of 165ns, as well. Section 4.7.2 (describing
156 * common and attribute memory write timing) says that twWE has a 161 * common and attribute memory write timing) says that twWE has a
157 * minimum value of 150ns for a 250ns cycle time (for 5V operation; 162 * minimum value of 150ns for a 250ns cycle time (for 5V operation;
158 * see section 4.7.4), or 300ns for a 600ns cycle time (for 3.3V 163 * see section 4.7.4), or 300ns for a 600ns cycle time (for 3.3V
159 * operation, also section 4.7.4). Section 4.7.3 says that taOE 164 * operation, also section 4.7.4). Section 4.7.3 says that taOE
160 * has a maximum value of 150ns for a 300ns cycle time (for 5V 165 * has a maximum value of 150ns for a 300ns cycle time (for 5V
161 * operation), or 300ns for a 600ns cycle time (for 3.3V operation). 166 * operation), or 300ns for a 600ns cycle time (for 3.3V operation).
162 * 167 *
163 * When configuring memory maps, Card Services appears to adopt the policy 168 * When configuring memory maps, Card Services appears to adopt the policy
164 * that a memory access time of "0" means "use the default." The default 169 * that a memory access time of "0" means "use the default." The default
165 * PCMCIA I/O command width time is 165ns. The default PCMCIA 5V attribute 170 * PCMCIA I/O command width time is 165ns. The default PCMCIA 5V attribute
166 * and memory command width time is 150ns; the PCMCIA 3.3V attribute and 171 * and memory command width time is 150ns; the PCMCIA 3.3V attribute and
167 * memory command width time is 300ns. 172 * memory command width time is 300ns.
168 */ 173 */
169 #define SOC_PCMCIA_IO_ACCESS (165) 174 #define SOC_PCMCIA_IO_ACCESS (165)
170 #define SOC_PCMCIA_5V_MEM_ACCESS (150) 175 #define SOC_PCMCIA_5V_MEM_ACCESS (150)
171 #define SOC_PCMCIA_3V_MEM_ACCESS (300) 176 #define SOC_PCMCIA_3V_MEM_ACCESS (300)
172 #define SOC_PCMCIA_ATTR_MEM_ACCESS (300) 177 #define SOC_PCMCIA_ATTR_MEM_ACCESS (300)
173 178
174 /* 179 /*
175 * The socket driver actually works nicely in interrupt-driven form, 180 * The socket driver actually works nicely in interrupt-driven form,
176 * so the (relatively infrequent) polling is "just to be sure." 181 * so the (relatively infrequent) polling is "just to be sure."
177 */ 182 */
178 #define SOC_PCMCIA_POLL_PERIOD (2*HZ) 183 #define SOC_PCMCIA_POLL_PERIOD (2*HZ)
179 184
180 185
181 /* I/O pins replacing memory pins 186 /* I/O pins replacing memory pins
182 * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75) 187 * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
183 * 188 *
184 * These signals change meaning when going from memory-only to 189 * These signals change meaning when going from memory-only to
185 * memory-or-I/O interface: 190 * memory-or-I/O interface:
186 */ 191 */
187 #define iostschg bvd1 192 #define iostschg bvd1
188 #define iospkr bvd2 193 #define iospkr bvd2
189 194
190 #endif 195 #endif
191 196