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Commit bc98d13f5cce1b617305966c3e95f7b2e62aa820

Authored by Steven King
Committed by Grant Likely
1 parent 5fda88f5e1
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

spi: refactor spi-coldfire-qspi to use SPI queue framework. 

Use the new SPI queue framework; remove use of workqueue, replace
mcfqspi_transfer with mcfqspi_transfer_one_message, add
mcfqspi_prepare_transfer_hw and mcfqspi_unprepare_transfer_hw, update power
management routines.

Signed-off-by: Steven King <sfking@fdwdc.com>
Acked-by: Greg Ungerer <gerg@snapgear.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

Showing 1 changed file with 114 additions and 141 deletions Inline Diff

drivers/spi/spi-coldfire-qspi.c
Diff comments   View file @ bc98d13
1 /* 1 /*
2 * Freescale/Motorola Coldfire Queued SPI driver 2 * Freescale/Motorola Coldfire Queued SPI driver
3 * 3 *
4 * Copyright 2010 Steven King <sfking@fdwdc.com> 4 * Copyright 2010 Steven King <sfking@fdwdc.com>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or 8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version. 9 * (at your option) any later version.
10 * 10 *
11 * This program is distributed in the hope that it will be useful, 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 * 15 *
16 * You should have received a copy of the GNU General Public License 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA
19 * 19 *
20 */ 20 */
21 21
22 #include <linux/kernel.h> 22 #include <linux/kernel.h>
23 #include <linux/module.h> 23 #include <linux/module.h>
24 #include <linux/interrupt.h> 24 #include <linux/interrupt.h>
25 #include <linux/errno.h> 25 #include <linux/errno.h>
26 #include <linux/platform_device.h> 26 #include <linux/platform_device.h>
27 #include <linux/sched.h> 27 #include <linux/sched.h>
28 #include <linux/workqueue.h>
29 #include <linux/delay.h> 28 #include <linux/delay.h>
30 #include <linux/io.h> 29 #include <linux/io.h>
31 #include <linux/clk.h> 30 #include <linux/clk.h>
32 #include <linux/err.h> 31 #include <linux/err.h>
33 #include <linux/spi/spi.h> 32 #include <linux/spi/spi.h>
33 #include <linux/pm_runtime.h>
34 34
35 #include <asm/coldfire.h> 35 #include <asm/coldfire.h>
36 #include <asm/mcfsim.h> 36 #include <asm/mcfsim.h>
37 #include <asm/mcfqspi.h> 37 #include <asm/mcfqspi.h>
38 38
39 #define DRIVER_NAME "mcfqspi" 39 #define DRIVER_NAME "mcfqspi"
40 40
41 #define MCFQSPI_BUSCLK (MCF_BUSCLK / 2) 41 #define MCFQSPI_BUSCLK (MCF_BUSCLK / 2)
42 42
43 #define MCFQSPI_QMR 0x00 43 #define MCFQSPI_QMR 0x00
44 #define MCFQSPI_QMR_MSTR 0x8000 44 #define MCFQSPI_QMR_MSTR 0x8000
45 #define MCFQSPI_QMR_CPOL 0x0200 45 #define MCFQSPI_QMR_CPOL 0x0200
46 #define MCFQSPI_QMR_CPHA 0x0100 46 #define MCFQSPI_QMR_CPHA 0x0100
47 #define MCFQSPI_QDLYR 0x04 47 #define MCFQSPI_QDLYR 0x04
48 #define MCFQSPI_QDLYR_SPE 0x8000 48 #define MCFQSPI_QDLYR_SPE 0x8000
49 #define MCFQSPI_QWR 0x08 49 #define MCFQSPI_QWR 0x08
50 #define MCFQSPI_QWR_HALT 0x8000 50 #define MCFQSPI_QWR_HALT 0x8000
51 #define MCFQSPI_QWR_WREN 0x4000 51 #define MCFQSPI_QWR_WREN 0x4000
52 #define MCFQSPI_QWR_CSIV 0x1000 52 #define MCFQSPI_QWR_CSIV 0x1000
53 #define MCFQSPI_QIR 0x0C 53 #define MCFQSPI_QIR 0x0C
54 #define MCFQSPI_QIR_WCEFB 0x8000 54 #define MCFQSPI_QIR_WCEFB 0x8000
55 #define MCFQSPI_QIR_ABRTB 0x4000 55 #define MCFQSPI_QIR_ABRTB 0x4000
56 #define MCFQSPI_QIR_ABRTL 0x1000 56 #define MCFQSPI_QIR_ABRTL 0x1000
57 #define MCFQSPI_QIR_WCEFE 0x0800 57 #define MCFQSPI_QIR_WCEFE 0x0800
58 #define MCFQSPI_QIR_ABRTE 0x0400 58 #define MCFQSPI_QIR_ABRTE 0x0400
59 #define MCFQSPI_QIR_SPIFE 0x0100 59 #define MCFQSPI_QIR_SPIFE 0x0100
60 #define MCFQSPI_QIR_WCEF 0x0008 60 #define MCFQSPI_QIR_WCEF 0x0008
61 #define MCFQSPI_QIR_ABRT 0x0004 61 #define MCFQSPI_QIR_ABRT 0x0004
62 #define MCFQSPI_QIR_SPIF 0x0001 62 #define MCFQSPI_QIR_SPIF 0x0001
63 #define MCFQSPI_QAR 0x010 63 #define MCFQSPI_QAR 0x010
64 #define MCFQSPI_QAR_TXBUF 0x00 64 #define MCFQSPI_QAR_TXBUF 0x00
65 #define MCFQSPI_QAR_RXBUF 0x10 65 #define MCFQSPI_QAR_RXBUF 0x10
66 #define MCFQSPI_QAR_CMDBUF 0x20 66 #define MCFQSPI_QAR_CMDBUF 0x20
67 #define MCFQSPI_QDR 0x014 67 #define MCFQSPI_QDR 0x014
68 #define MCFQSPI_QCR 0x014 68 #define MCFQSPI_QCR 0x014
69 #define MCFQSPI_QCR_CONT 0x8000 69 #define MCFQSPI_QCR_CONT 0x8000
70 #define MCFQSPI_QCR_BITSE 0x4000 70 #define MCFQSPI_QCR_BITSE 0x4000
71 #define MCFQSPI_QCR_DT 0x2000 71 #define MCFQSPI_QCR_DT 0x2000
72 72
73 struct mcfqspi { 73 struct mcfqspi {
74 void __iomem *iobase; 74 void __iomem *iobase;
75 int irq; 75 int irq;
76 struct clk *clk; 76 struct clk *clk;
77 struct mcfqspi_cs_control *cs_control; 77 struct mcfqspi_cs_control *cs_control;
78 78
79 wait_queue_head_t waitq; 79 wait_queue_head_t waitq;
80 80
81 struct work_struct work; 81 struct device *dev;
82 struct workqueue_struct *workq;
83 spinlock_t lock;
84 struct list_head msgq;
85 }; 82 };
86 83
87 static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val) 84 static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
88 { 85 {
89 writew(val, mcfqspi->iobase + MCFQSPI_QMR); 86 writew(val, mcfqspi->iobase + MCFQSPI_QMR);
90 } 87 }
91 88
92 static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val) 89 static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
93 { 90 {
94 writew(val, mcfqspi->iobase + MCFQSPI_QDLYR); 91 writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
95 } 92 }
96 93
97 static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi) 94 static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
98 { 95 {
99 return readw(mcfqspi->iobase + MCFQSPI_QDLYR); 96 return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
100 } 97 }
101 98
102 static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val) 99 static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
103 { 100 {
104 writew(val, mcfqspi->iobase + MCFQSPI_QWR); 101 writew(val, mcfqspi->iobase + MCFQSPI_QWR);
105 } 102 }
106 103
107 static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val) 104 static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
108 { 105 {
109 writew(val, mcfqspi->iobase + MCFQSPI_QIR); 106 writew(val, mcfqspi->iobase + MCFQSPI_QIR);
110 } 107 }
111 108
112 static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val) 109 static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
113 { 110 {
114 writew(val, mcfqspi->iobase + MCFQSPI_QAR); 111 writew(val, mcfqspi->iobase + MCFQSPI_QAR);
115 } 112 }
116 113
117 static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val) 114 static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
118 { 115 {
119 writew(val, mcfqspi->iobase + MCFQSPI_QDR); 116 writew(val, mcfqspi->iobase + MCFQSPI_QDR);
120 } 117 }
121 118
122 static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi) 119 static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
123 { 120 {
124 return readw(mcfqspi->iobase + MCFQSPI_QDR); 121 return readw(mcfqspi->iobase + MCFQSPI_QDR);
125 } 122 }
126 123
127 static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select, 124 static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
128 bool cs_high) 125 bool cs_high)
129 { 126 {
130 mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high); 127 mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
131 } 128 }
132 129
133 static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select, 130 static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
134 bool cs_high) 131 bool cs_high)
135 { 132 {
136 mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high); 133 mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
137 } 134 }
138 135
139 static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi) 136 static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
140 { 137 {
141 return (mcfqspi->cs_control && mcfqspi->cs_control->setup) ? 138 return (mcfqspi->cs_control && mcfqspi->cs_control->setup) ?
142 mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0; 139 mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
143 } 140 }
144 141
145 static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi) 142 static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
146 { 143 {
147 if (mcfqspi->cs_control && mcfqspi->cs_control->teardown) 144 if (mcfqspi->cs_control && mcfqspi->cs_control->teardown)
148 mcfqspi->cs_control->teardown(mcfqspi->cs_control); 145 mcfqspi->cs_control->teardown(mcfqspi->cs_control);
149 } 146 }
150 147
151 static u8 mcfqspi_qmr_baud(u32 speed_hz) 148 static u8 mcfqspi_qmr_baud(u32 speed_hz)
152 { 149 {
153 return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u); 150 return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
154 } 151 }
155 152
156 static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi) 153 static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
157 { 154 {
158 return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE; 155 return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
159 } 156 }
160 157
161 static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id) 158 static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
162 { 159 {
163 struct mcfqspi *mcfqspi = dev_id; 160 struct mcfqspi *mcfqspi = dev_id;
164 161
165 /* clear interrupt */ 162 /* clear interrupt */
166 mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF); 163 mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF);
167 wake_up(&mcfqspi->waitq); 164 wake_up(&mcfqspi->waitq);
168 165
169 return IRQ_HANDLED; 166 return IRQ_HANDLED;
170 } 167 }
171 168
172 static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count, 169 static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
173 const u8 *txbuf, u8 *rxbuf) 170 const u8 *txbuf, u8 *rxbuf)
174 { 171 {
175 unsigned i, n, offset = 0; 172 unsigned i, n, offset = 0;
176 173
177 n = min(count, 16u); 174 n = min(count, 16u);
178 175
179 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF); 176 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
180 for (i = 0; i < n; ++i) 177 for (i = 0; i < n; ++i)
181 mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE); 178 mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
182 179
183 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF); 180 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
184 if (txbuf) 181 if (txbuf)
185 for (i = 0; i < n; ++i) 182 for (i = 0; i < n; ++i)
186 mcfqspi_wr_qdr(mcfqspi, *txbuf++); 183 mcfqspi_wr_qdr(mcfqspi, *txbuf++);
187 else 184 else
188 for (i = 0; i < count; ++i) 185 for (i = 0; i < count; ++i)
189 mcfqspi_wr_qdr(mcfqspi, 0); 186 mcfqspi_wr_qdr(mcfqspi, 0);
190 187
191 count -= n; 188 count -= n;
192 if (count) { 189 if (count) {
193 u16 qwr = 0xf08; 190 u16 qwr = 0xf08;
194 mcfqspi_wr_qwr(mcfqspi, 0x700); 191 mcfqspi_wr_qwr(mcfqspi, 0x700);
195 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); 192 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
196 193
197 do { 194 do {
198 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); 195 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
199 mcfqspi_wr_qwr(mcfqspi, qwr); 196 mcfqspi_wr_qwr(mcfqspi, qwr);
200 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); 197 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
201 if (rxbuf) { 198 if (rxbuf) {
202 mcfqspi_wr_qar(mcfqspi, 199 mcfqspi_wr_qar(mcfqspi,
203 MCFQSPI_QAR_RXBUF + offset); 200 MCFQSPI_QAR_RXBUF + offset);
204 for (i = 0; i < 8; ++i) 201 for (i = 0; i < 8; ++i)
205 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); 202 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
206 } 203 }
207 n = min(count, 8u); 204 n = min(count, 8u);
208 if (txbuf) { 205 if (txbuf) {
209 mcfqspi_wr_qar(mcfqspi, 206 mcfqspi_wr_qar(mcfqspi,
210 MCFQSPI_QAR_TXBUF + offset); 207 MCFQSPI_QAR_TXBUF + offset);
211 for (i = 0; i < n; ++i) 208 for (i = 0; i < n; ++i)
212 mcfqspi_wr_qdr(mcfqspi, *txbuf++); 209 mcfqspi_wr_qdr(mcfqspi, *txbuf++);
213 } 210 }
214 qwr = (offset ? 0x808 : 0) + ((n - 1) << 8); 211 qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
215 offset ^= 8; 212 offset ^= 8;
216 count -= n; 213 count -= n;
217 } while (count); 214 } while (count);
218 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); 215 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
219 mcfqspi_wr_qwr(mcfqspi, qwr); 216 mcfqspi_wr_qwr(mcfqspi, qwr);
220 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); 217 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
221 if (rxbuf) { 218 if (rxbuf) {
222 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); 219 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
223 for (i = 0; i < 8; ++i) 220 for (i = 0; i < 8; ++i)
224 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); 221 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
225 offset ^= 8; 222 offset ^= 8;
226 } 223 }
227 } else { 224 } else {
228 mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8); 225 mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
229 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); 226 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
230 } 227 }
231 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); 228 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
232 if (rxbuf) { 229 if (rxbuf) {
233 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); 230 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
234 for (i = 0; i < n; ++i) 231 for (i = 0; i < n; ++i)
235 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); 232 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
236 } 233 }
237 } 234 }
238 235
239 static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count, 236 static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
240 const u16 *txbuf, u16 *rxbuf) 237 const u16 *txbuf, u16 *rxbuf)
241 { 238 {
242 unsigned i, n, offset = 0; 239 unsigned i, n, offset = 0;
243 240
244 n = min(count, 16u); 241 n = min(count, 16u);
245 242
246 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF); 243 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
247 for (i = 0; i < n; ++i) 244 for (i = 0; i < n; ++i)
248 mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE); 245 mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
249 246
250 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF); 247 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
251 if (txbuf) 248 if (txbuf)
252 for (i = 0; i < n; ++i) 249 for (i = 0; i < n; ++i)
253 mcfqspi_wr_qdr(mcfqspi, *txbuf++); 250 mcfqspi_wr_qdr(mcfqspi, *txbuf++);
254 else 251 else
255 for (i = 0; i < count; ++i) 252 for (i = 0; i < count; ++i)
256 mcfqspi_wr_qdr(mcfqspi, 0); 253 mcfqspi_wr_qdr(mcfqspi, 0);
257 254
258 count -= n; 255 count -= n;
259 if (count) { 256 if (count) {
260 u16 qwr = 0xf08; 257 u16 qwr = 0xf08;
261 mcfqspi_wr_qwr(mcfqspi, 0x700); 258 mcfqspi_wr_qwr(mcfqspi, 0x700);
262 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); 259 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
263 260
264 do { 261 do {
265 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); 262 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
266 mcfqspi_wr_qwr(mcfqspi, qwr); 263 mcfqspi_wr_qwr(mcfqspi, qwr);
267 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); 264 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
268 if (rxbuf) { 265 if (rxbuf) {
269 mcfqspi_wr_qar(mcfqspi, 266 mcfqspi_wr_qar(mcfqspi,
270 MCFQSPI_QAR_RXBUF + offset); 267 MCFQSPI_QAR_RXBUF + offset);
271 for (i = 0; i < 8; ++i) 268 for (i = 0; i < 8; ++i)
272 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); 269 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
273 } 270 }
274 n = min(count, 8u); 271 n = min(count, 8u);
275 if (txbuf) { 272 if (txbuf) {
276 mcfqspi_wr_qar(mcfqspi, 273 mcfqspi_wr_qar(mcfqspi,
277 MCFQSPI_QAR_TXBUF + offset); 274 MCFQSPI_QAR_TXBUF + offset);
278 for (i = 0; i < n; ++i) 275 for (i = 0; i < n; ++i)
279 mcfqspi_wr_qdr(mcfqspi, *txbuf++); 276 mcfqspi_wr_qdr(mcfqspi, *txbuf++);
280 } 277 }
281 qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8); 278 qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
282 offset ^= 8; 279 offset ^= 8;
283 count -= n; 280 count -= n;
284 } while (count); 281 } while (count);
285 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); 282 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
286 mcfqspi_wr_qwr(mcfqspi, qwr); 283 mcfqspi_wr_qwr(mcfqspi, qwr);
287 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); 284 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
288 if (rxbuf) { 285 if (rxbuf) {
289 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); 286 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
290 for (i = 0; i < 8; ++i) 287 for (i = 0; i < 8; ++i)
291 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); 288 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
292 offset ^= 8; 289 offset ^= 8;
293 } 290 }
294 } else { 291 } else {
295 mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8); 292 mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
296 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); 293 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
297 } 294 }
298 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); 295 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
299 if (rxbuf) { 296 if (rxbuf) {
300 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); 297 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
301 for (i = 0; i < n; ++i) 298 for (i = 0; i < n; ++i)
302 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); 299 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
303 } 300 }
304 } 301 }
305 302
306 static void mcfqspi_work(struct work_struct *work) 303 static int mcfqspi_transfer_one_message(struct spi_master *master,
304 struct spi_message *msg)
307 { 305 {
308 struct mcfqspi *mcfqspi = container_of(work, struct mcfqspi, work); 306 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
309 unsigned long flags; 307 struct spi_device *spi = msg->spi;
308 struct spi_transfer *t;
309 int status = 0;
310 310
311 spin_lock_irqsave(&mcfqspi->lock, flags); 311 list_for_each_entry(t, &msg->transfers, transfer_list) {
312 while (!list_empty(&mcfqspi->msgq)) { 312 bool cs_high = spi->mode & SPI_CS_HIGH;
313 struct spi_message *msg; 313 u16 qmr = MCFQSPI_QMR_MSTR;
314 struct spi_device *spi;
315 struct spi_transfer *xfer;
316 int status = 0;
317 314
318 msg = container_of(mcfqspi->msgq.next, struct spi_message, 315 if (t->bits_per_word)
319 queue); 316 qmr |= t->bits_per_word << 10;
317 else
318 qmr |= spi->bits_per_word << 10;
319 if (spi->mode & SPI_CPHA)
320 qmr |= MCFQSPI_QMR_CPHA;
321 if (spi->mode & SPI_CPOL)
322 qmr |= MCFQSPI_QMR_CPOL;
323 if (t->speed_hz)
324 qmr |= mcfqspi_qmr_baud(t->speed_hz);
325 else
326 qmr |= mcfqspi_qmr_baud(spi->max_speed_hz);
327 mcfqspi_wr_qmr(mcfqspi, qmr);
320 328
321 list_del_init(&msg->queue); 329 mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
322 spin_unlock_irqrestore(&mcfqspi->lock, flags);
323 330
324 spi = msg->spi; 331 mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
332 if ((t->bits_per_word ? t->bits_per_word :
333 spi->bits_per_word) == 8)
334 mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf,
335 t->rx_buf);
336 else
337 mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
338 t->rx_buf);
339 mcfqspi_wr_qir(mcfqspi, 0);
325 340
326 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 341 if (t->delay_usecs)
327 bool cs_high = spi->mode & SPI_CS_HIGH; 342 udelay(t->delay_usecs);
328 u16 qmr = MCFQSPI_QMR_MSTR; 343 if (t->cs_change) {
344 if (!list_is_last(&t->transfer_list, &msg->transfers))
345 mcfqspi_cs_deselect(mcfqspi, spi->chip_select,
346 cs_high);
347 } else {
348 if (list_is_last(&t->transfer_list, &msg->transfers))
349 mcfqspi_cs_deselect(mcfqspi, spi->chip_select,
350 cs_high);
351 }
352 msg->actual_length += t->len;
353 }
354 msg->status = status;
355 spi_finalize_current_message(master);
329 356
330 if (xfer->bits_per_word) 357 return status;
331 qmr |= xfer->bits_per_word << 10;
332 else
333 qmr |= spi->bits_per_word << 10;
334 if (spi->mode & SPI_CPHA)
335 qmr |= MCFQSPI_QMR_CPHA;
336 if (spi->mode & SPI_CPOL)
337 qmr |= MCFQSPI_QMR_CPOL;
338 if (xfer->speed_hz)
339 qmr |= mcfqspi_qmr_baud(xfer->speed_hz);
340 else
341 qmr |= mcfqspi_qmr_baud(spi->max_speed_hz);
342 mcfqspi_wr_qmr(mcfqspi, qmr);
343 358
344 mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high); 359 }
345 360
346 mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE); 361 static int mcfqspi_prepare_transfer_hw(struct spi_master *master)
347 if ((xfer->bits_per_word ? xfer->bits_per_word : 362 {
348 spi->bits_per_word) == 8) 363 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
349 mcfqspi_transfer_msg8(mcfqspi, xfer->len,
350 xfer->tx_buf,
351 xfer->rx_buf);
352 else
353 mcfqspi_transfer_msg16(mcfqspi, xfer->len / 2,
354 xfer->tx_buf,
355 xfer->rx_buf);
356 mcfqspi_wr_qir(mcfqspi, 0);
357 364
358 if (xfer->delay_usecs) 365 pm_runtime_get_sync(mcfqspi->dev);
359 udelay(xfer->delay_usecs);
360 if (xfer->cs_change) {
361 if (!list_is_last(&xfer->transfer_list,
362 &msg->transfers))
363 mcfqspi_cs_deselect(mcfqspi,
364 spi->chip_select,
365 cs_high);
366 } else {
367 if (list_is_last(&xfer->transfer_list,
368 &msg->transfers))
369 mcfqspi_cs_deselect(mcfqspi,
370 spi->chip_select,
371 cs_high);
372 }
373 msg->actual_length += xfer->len;
374 }
375 msg->status = status;
376 msg->complete(msg->context);
377 366
378 spin_lock_irqsave(&mcfqspi->lock, flags); 367 return 0;
379 }
380 spin_unlock_irqrestore(&mcfqspi->lock, flags);
381 } 368 }
382 369
383 static int mcfqspi_transfer(struct spi_device *spi, struct spi_message *msg) 370 static int mcfqspi_unprepare_transfer_hw(struct spi_master *master)
384 { 371 {
385 struct mcfqspi *mcfqspi; 372 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
386 struct spi_transfer *xfer;
387 unsigned long flags;
388 373
389 mcfqspi = spi_master_get_devdata(spi->master); 374 pm_runtime_put_sync(mcfqspi->dev);
390 375
391 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
392 if (xfer->bits_per_word && ((xfer->bits_per_word < 8)
393 || (xfer->bits_per_word > 16))) {
394 dev_dbg(&spi->dev,
395 "%d bits per word is not supported\n",
396 xfer->bits_per_word);
397 goto fail;
398 }
399 if (xfer->speed_hz) {
400 u32 real_speed = MCFQSPI_BUSCLK /
401 mcfqspi_qmr_baud(xfer->speed_hz);
402 if (real_speed != xfer->speed_hz)
403 dev_dbg(&spi->dev,
404 "using speed %d instead of %d\n",
405 real_speed, xfer->speed_hz);
406 }
407 }
408 msg->status = -EINPROGRESS;
409 msg->actual_length = 0;
410
411 spin_lock_irqsave(&mcfqspi->lock, flags);
412 list_add_tail(&msg->queue, &mcfqspi->msgq);
413 queue_work(mcfqspi->workq, &mcfqspi->work);
414 spin_unlock_irqrestore(&mcfqspi->lock, flags);
415
416 return 0; 376 return 0;
417 fail:
418 msg->status = -EINVAL;
419 return -EINVAL;
420 } 377 }
421 378
422 static int mcfqspi_setup(struct spi_device *spi) 379 static int mcfqspi_setup(struct spi_device *spi)
423 { 380 {
424 if ((spi->bits_per_word < 8) || (spi->bits_per_word > 16)) { 381 if ((spi->bits_per_word < 8) || (spi->bits_per_word > 16)) {
425 dev_dbg(&spi->dev, "%d bits per word is not supported\n", 382 dev_dbg(&spi->dev, "%d bits per word is not supported\n",
426 spi->bits_per_word); 383 spi->bits_per_word);
427 return -EINVAL; 384 return -EINVAL;
428 } 385 }
429 if (spi->chip_select >= spi->master->num_chipselect) { 386 if (spi->chip_select >= spi->master->num_chipselect) {
430 dev_dbg(&spi->dev, "%d chip select is out of range\n", 387 dev_dbg(&spi->dev, "%d chip select is out of range\n",
431 spi->chip_select); 388 spi->chip_select);
432 return -EINVAL; 389 return -EINVAL;
433 } 390 }
434 391
435 mcfqspi_cs_deselect(spi_master_get_devdata(spi->master), 392 mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
436 spi->chip_select, spi->mode & SPI_CS_HIGH); 393 spi->chip_select, spi->mode & SPI_CS_HIGH);
437 394
438 dev_dbg(&spi->dev, 395 dev_dbg(&spi->dev,
439 "bits per word %d, chip select %d, speed %d KHz\n", 396 "bits per word %d, chip select %d, speed %d KHz\n",
440 spi->bits_per_word, spi->chip_select, 397 spi->bits_per_word, spi->chip_select,
441 (MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz)) 398 (MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
442 / 1000); 399 / 1000);
443 400
444 return 0; 401 return 0;
445 } 402 }
446 403
447 static int __devinit mcfqspi_probe(struct platform_device *pdev) 404 static int __devinit mcfqspi_probe(struct platform_device *pdev)
448 { 405 {
449 struct spi_master *master; 406 struct spi_master *master;
450 struct mcfqspi *mcfqspi; 407 struct mcfqspi *mcfqspi;
451 struct resource *res; 408 struct resource *res;
452 struct mcfqspi_platform_data *pdata; 409 struct mcfqspi_platform_data *pdata;
453 int status; 410 int status;
454 411
455 master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi)); 412 master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
456 if (master == NULL) { 413 if (master == NULL) {
457 dev_dbg(&pdev->dev, "spi_alloc_master failed\n"); 414 dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
458 return -ENOMEM; 415 return -ENOMEM;
459 } 416 }
460 417
461 mcfqspi = spi_master_get_devdata(master); 418 mcfqspi = spi_master_get_devdata(master);
462 419
463 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 420 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
464 if (!res) { 421 if (!res) {
465 dev_dbg(&pdev->dev, "platform_get_resource failed\n"); 422 dev_dbg(&pdev->dev, "platform_get_resource failed\n");
466 status = -ENXIO; 423 status = -ENXIO;
467 goto fail0; 424 goto fail0;
468 } 425 }
469 426
470 if (!request_mem_region(res->start, resource_size(res), pdev->name)) { 427 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
471 dev_dbg(&pdev->dev, "request_mem_region failed\n"); 428 dev_dbg(&pdev->dev, "request_mem_region failed\n");
472 status = -EBUSY; 429 status = -EBUSY;
473 goto fail0; 430 goto fail0;
474 } 431 }
475 432
476 mcfqspi->iobase = ioremap(res->start, resource_size(res)); 433 mcfqspi->iobase = ioremap(res->start, resource_size(res));
477 if (!mcfqspi->iobase) { 434 if (!mcfqspi->iobase) {
478 dev_dbg(&pdev->dev, "ioremap failed\n"); 435 dev_dbg(&pdev->dev, "ioremap failed\n");
479 status = -ENOMEM; 436 status = -ENOMEM;
480 goto fail1; 437 goto fail1;
481 } 438 }
482 439
483 mcfqspi->irq = platform_get_irq(pdev, 0); 440 mcfqspi->irq = platform_get_irq(pdev, 0);
484 if (mcfqspi->irq < 0) { 441 if (mcfqspi->irq < 0) {
485 dev_dbg(&pdev->dev, "platform_get_irq failed\n"); 442 dev_dbg(&pdev->dev, "platform_get_irq failed\n");
486 status = -ENXIO; 443 status = -ENXIO;
487 goto fail2; 444 goto fail2;
488 } 445 }
489 446
490 status = request_irq(mcfqspi->irq, mcfqspi_irq_handler, 0, 447 status = request_irq(mcfqspi->irq, mcfqspi_irq_handler, 0,
491 pdev->name, mcfqspi); 448 pdev->name, mcfqspi);
492 if (status) { 449 if (status) {
493 dev_dbg(&pdev->dev, "request_irq failed\n"); 450 dev_dbg(&pdev->dev, "request_irq failed\n");
494 goto fail2; 451 goto fail2;
495 } 452 }
496 453
497 mcfqspi->clk = clk_get(&pdev->dev, "qspi_clk"); 454 mcfqspi->clk = clk_get(&pdev->dev, "qspi_clk");
498 if (IS_ERR(mcfqspi->clk)) { 455 if (IS_ERR(mcfqspi->clk)) {
499 dev_dbg(&pdev->dev, "clk_get failed\n"); 456 dev_dbg(&pdev->dev, "clk_get failed\n");
500 status = PTR_ERR(mcfqspi->clk); 457 status = PTR_ERR(mcfqspi->clk);
501 goto fail3; 458 goto fail3;
502 } 459 }
503 clk_enable(mcfqspi->clk); 460 clk_enable(mcfqspi->clk);
504 461
505 mcfqspi->workq = create_singlethread_workqueue(dev_name(master->dev.parent));
506 if (!mcfqspi->workq) {
507 dev_dbg(&pdev->dev, "create_workqueue failed\n");
508 status = -ENOMEM;
509 goto fail4;
510 }
511 INIT_WORK(&mcfqspi->work, mcfqspi_work);
512 spin_lock_init(&mcfqspi->lock);
513 INIT_LIST_HEAD(&mcfqspi->msgq);
514 init_waitqueue_head(&mcfqspi->waitq);
515
516 pdata = pdev->dev.platform_data; 462 pdata = pdev->dev.platform_data;
517 if (!pdata) { 463 if (!pdata) {
518 dev_dbg(&pdev->dev, "platform data is missing\n"); 464 dev_dbg(&pdev->dev, "platform data is missing\n");
519 goto fail5; 465 goto fail4;
520 } 466 }
521 master->bus_num = pdata->bus_num; 467 master->bus_num = pdata->bus_num;
522 master->num_chipselect = pdata->num_chipselect; 468 master->num_chipselect = pdata->num_chipselect;
523 469
524 mcfqspi->cs_control = pdata->cs_control; 470 mcfqspi->cs_control = pdata->cs_control;
525 status = mcfqspi_cs_setup(mcfqspi); 471 status = mcfqspi_cs_setup(mcfqspi);
526 if (status) { 472 if (status) {
527 dev_dbg(&pdev->dev, "error initializing cs_control\n"); 473 dev_dbg(&pdev->dev, "error initializing cs_control\n");
528 goto fail5; 474 goto fail4;
529 } 475 }
530 476
477 init_waitqueue_head(&mcfqspi->waitq);
478 mcfqspi->dev = &pdev->dev;
479
531 master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA; 480 master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
532 master->setup = mcfqspi_setup; 481 master->setup = mcfqspi_setup;
533 master->transfer = mcfqspi_transfer; 482 master->transfer_one_message = mcfqspi_transfer_one_message;
483 master->prepare_transfer_hardware = mcfqspi_prepare_transfer_hw;
484 master->unprepare_transfer_hardware = mcfqspi_unprepare_transfer_hw;
534 485
535 platform_set_drvdata(pdev, master); 486 platform_set_drvdata(pdev, master);
536 487
537 status = spi_register_master(master); 488 status = spi_register_master(master);
538 if (status) { 489 if (status) {
539 dev_dbg(&pdev->dev, "spi_register_master failed\n"); 490 dev_dbg(&pdev->dev, "spi_register_master failed\n");
540 goto fail6; 491 goto fail5;
541 } 492 }
493 pm_runtime_enable(mcfqspi->dev);
494
542 dev_info(&pdev->dev, "Coldfire QSPI bus driver\n"); 495 dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
543 496
544 return 0; 497 return 0;
545 498
546 fail6:
547 mcfqspi_cs_teardown(mcfqspi);
548 fail5: 499 fail5:
549 destroy_workqueue(mcfqspi->workq); 500 mcfqspi_cs_teardown(mcfqspi);
550 fail4: 501 fail4:
551 clk_disable(mcfqspi->clk); 502 clk_disable(mcfqspi->clk);
552 clk_put(mcfqspi->clk); 503 clk_put(mcfqspi->clk);
553 fail3: 504 fail3:
554 free_irq(mcfqspi->irq, mcfqspi); 505 free_irq(mcfqspi->irq, mcfqspi);
555 fail2: 506 fail2:
556 iounmap(mcfqspi->iobase); 507 iounmap(mcfqspi->iobase);
557 fail1: 508 fail1:
558 release_mem_region(res->start, resource_size(res)); 509 release_mem_region(res->start, resource_size(res));
559 fail0: 510 fail0:
560 spi_master_put(master); 511 spi_master_put(master);
561 512
562 dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n"); 513 dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");
563 514
564 return status; 515 return status;
565 } 516 }
566 517
567 static int __devexit mcfqspi_remove(struct platform_device *pdev) 518 static int __devexit mcfqspi_remove(struct platform_device *pdev)
568 { 519 {
569 struct spi_master *master = platform_get_drvdata(pdev); 520 struct spi_master *master = platform_get_drvdata(pdev);
570 struct mcfqspi *mcfqspi = spi_master_get_devdata(master); 521 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
571 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 522 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
572 523
524 pm_runtime_disable(mcfqspi->dev);
573 /* disable the hardware (set the baud rate to 0) */ 525 /* disable the hardware (set the baud rate to 0) */
574 mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR); 526 mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
575 527
576 platform_set_drvdata(pdev, NULL); 528 platform_set_drvdata(pdev, NULL);
577 mcfqspi_cs_teardown(mcfqspi); 529 mcfqspi_cs_teardown(mcfqspi);
578 destroy_workqueue(mcfqspi->workq);
579 clk_disable(mcfqspi->clk); 530 clk_disable(mcfqspi->clk);
580 clk_put(mcfqspi->clk); 531 clk_put(mcfqspi->clk);
581 free_irq(mcfqspi->irq, mcfqspi); 532 free_irq(mcfqspi->irq, mcfqspi);
582 iounmap(mcfqspi->iobase); 533 iounmap(mcfqspi->iobase);
583 release_mem_region(res->start, resource_size(res)); 534 release_mem_region(res->start, resource_size(res));
584 spi_unregister_master(master); 535 spi_unregister_master(master);
585 spi_master_put(master); 536 spi_master_put(master);
586 537
587 return 0; 538 return 0;
588 } 539 }
589 540
590 #ifdef CONFIG_PM 541 #ifdef CONFIG_PM_SLEEP