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Commit bd12976c366486ea90aebd83f1cf2863ee47c76a

Authored by Vineet Gupta
1 parent 63d2dfdbf4
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

ARC: cacheflush refactor #3: Unify the {d,i}cache flush leaf helpers 

With Line length being constant now, we can fold the 2 helpers into 1.
This allows applying any optimizations (forthcoming) to single place.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

Showing 1 changed file with 55 additions and 84 deletions Inline Diff

arch/arc/mm/cache_arc700.c
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1 /* 1 /*
2 * ARC700 VIPT Cache Management 2 * ARC700 VIPT Cache Management
3 * 3 *
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 * 9 *
10 * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs 10 * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
11 * -flush_cache_dup_mm (fork) 11 * -flush_cache_dup_mm (fork)
12 * -likewise for flush_cache_mm (exit/execve) 12 * -likewise for flush_cache_mm (exit/execve)
13 * -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break) 13 * -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break)
14 * 14 *
15 * vineetg: Apr 2011 15 * vineetg: Apr 2011
16 * -Now that MMU can support larger pg sz (16K), the determiniation of 16 * -Now that MMU can support larger pg sz (16K), the determiniation of
17 * aliasing shd not be based on assumption of 8k pg 17 * aliasing shd not be based on assumption of 8k pg
18 * 18 *
19 * vineetg: Mar 2011 19 * vineetg: Mar 2011
20 * -optimised version of flush_icache_range( ) for making I/D coherent 20 * -optimised version of flush_icache_range( ) for making I/D coherent
21 * when vaddr is available (agnostic of num of aliases) 21 * when vaddr is available (agnostic of num of aliases)
22 * 22 *
23 * vineetg: Mar 2011 23 * vineetg: Mar 2011
24 * -Added documentation about I-cache aliasing on ARC700 and the way it 24 * -Added documentation about I-cache aliasing on ARC700 and the way it
25 * was handled up until MMU V2. 25 * was handled up until MMU V2.
26 * -Spotted a three year old bug when killing the 4 aliases, which needs 26 * -Spotted a three year old bug when killing the 4 aliases, which needs
27 * bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03} 27 * bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03}
28 * instead of paddr | {0x00, 0x01, 0x10, 0x11} 28 * instead of paddr | {0x00, 0x01, 0x10, 0x11}
29 * (Rajesh you owe me one now) 29 * (Rajesh you owe me one now)
30 * 30 *
31 * vineetg: Dec 2010 31 * vineetg: Dec 2010
32 * -Off-by-one error when computing num_of_lines to flush 32 * -Off-by-one error when computing num_of_lines to flush
33 * This broke signal handling with bionic which uses synthetic sigret stub 33 * This broke signal handling with bionic which uses synthetic sigret stub
34 * 34 *
35 * vineetg: Mar 2010 35 * vineetg: Mar 2010
36 * -GCC can't generate ZOL for core cache flush loops. 36 * -GCC can't generate ZOL for core cache flush loops.
37 * Conv them into iterations based as opposed to while (start < end) types 37 * Conv them into iterations based as opposed to while (start < end) types
38 * 38 *
39 * Vineetg: July 2009 39 * Vineetg: July 2009
40 * -In I-cache flush routine we used to chk for aliasing for every line INV. 40 * -In I-cache flush routine we used to chk for aliasing for every line INV.
41 * Instead now we setup routines per cache geometry and invoke them 41 * Instead now we setup routines per cache geometry and invoke them
42 * via function pointers. 42 * via function pointers.
43 * 43 *
44 * Vineetg: Jan 2009 44 * Vineetg: Jan 2009
45 * -Cache Line flush routines used to flush an extra line beyond end addr 45 * -Cache Line flush routines used to flush an extra line beyond end addr
46 * because check was while (end >= start) instead of (end > start) 46 * because check was while (end >= start) instead of (end > start)
47 * =Some call sites had to work around by doing -1, -4 etc to end param 47 * =Some call sites had to work around by doing -1, -4 etc to end param
48 * =Some callers didnt care. This was spec bad in case of INV routines 48 * =Some callers didnt care. This was spec bad in case of INV routines
49 * which would discard valid data (cause of the horrible ext2 bug 49 * which would discard valid data (cause of the horrible ext2 bug
50 * in ARC IDE driver) 50 * in ARC IDE driver)
51 * 51 *
52 * vineetg: June 11th 2008: Fixed flush_icache_range( ) 52 * vineetg: June 11th 2008: Fixed flush_icache_range( )
53 * -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need 53 * -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need
54 * to be flushed, which it was not doing. 54 * to be flushed, which it was not doing.
55 * -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API, 55 * -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API,
56 * however ARC cache maintenance OPs require PHY addr. Thus need to do 56 * however ARC cache maintenance OPs require PHY addr. Thus need to do
57 * vmalloc_to_phy. 57 * vmalloc_to_phy.
58 * -Also added optimisation there, that for range > PAGE SIZE we flush the 58 * -Also added optimisation there, that for range > PAGE SIZE we flush the
59 * entire cache in one shot rather than line by line. For e.g. a module 59 * entire cache in one shot rather than line by line. For e.g. a module
60 * with Code sz 600k, old code flushed 600k worth of cache (line-by-line), 60 * with Code sz 600k, old code flushed 600k worth of cache (line-by-line),
61 * while cache is only 16 or 32k. 61 * while cache is only 16 or 32k.
62 */ 62 */
63 63
64 #include <linux/module.h> 64 #include <linux/module.h>
65 #include <linux/mm.h> 65 #include <linux/mm.h>
66 #include <linux/sched.h> 66 #include <linux/sched.h>
67 #include <linux/cache.h> 67 #include <linux/cache.h>
68 #include <linux/mmu_context.h> 68 #include <linux/mmu_context.h>
69 #include <linux/syscalls.h> 69 #include <linux/syscalls.h>
70 #include <linux/uaccess.h> 70 #include <linux/uaccess.h>
71 #include <linux/pagemap.h> 71 #include <linux/pagemap.h>
72 #include <asm/cacheflush.h> 72 #include <asm/cacheflush.h>
73 #include <asm/cachectl.h> 73 #include <asm/cachectl.h>
74 #include <asm/setup.h> 74 #include <asm/setup.h>
75 75
76 /* Instruction cache related Auxiliary registers */ 76 /* Instruction cache related Auxiliary registers */
77 #define ARC_REG_IC_BCR 0x77 /* Build Config reg */ 77 #define ARC_REG_IC_BCR 0x77 /* Build Config reg */
78 #define ARC_REG_IC_IVIC 0x10 78 #define ARC_REG_IC_IVIC 0x10
79 #define ARC_REG_IC_CTRL 0x11 79 #define ARC_REG_IC_CTRL 0x11
80 #define ARC_REG_IC_IVIL 0x19 80 #define ARC_REG_IC_IVIL 0x19
81 #if (CONFIG_ARC_MMU_VER > 2) 81 #if (CONFIG_ARC_MMU_VER > 2)
82 #define ARC_REG_IC_PTAG 0x1E 82 #define ARC_REG_IC_PTAG 0x1E
83 #endif 83 #endif
84 84
85 /* Bit val in IC_CTRL */ 85 /* Bit val in IC_CTRL */
86 #define IC_CTRL_CACHE_DISABLE 0x1 86 #define IC_CTRL_CACHE_DISABLE 0x1
87 87
88 /* Data cache related Auxiliary registers */ 88 /* Data cache related Auxiliary registers */
89 #define ARC_REG_DC_BCR 0x72 /* Build Config reg */ 89 #define ARC_REG_DC_BCR 0x72 /* Build Config reg */
90 #define ARC_REG_DC_IVDC 0x47 90 #define ARC_REG_DC_IVDC 0x47
91 #define ARC_REG_DC_CTRL 0x48 91 #define ARC_REG_DC_CTRL 0x48
92 #define ARC_REG_DC_IVDL 0x4A 92 #define ARC_REG_DC_IVDL 0x4A
93 #define ARC_REG_DC_FLSH 0x4B 93 #define ARC_REG_DC_FLSH 0x4B
94 #define ARC_REG_DC_FLDL 0x4C 94 #define ARC_REG_DC_FLDL 0x4C
95 #if (CONFIG_ARC_MMU_VER > 2) 95 #if (CONFIG_ARC_MMU_VER > 2)
96 #define ARC_REG_DC_PTAG 0x5C 96 #define ARC_REG_DC_PTAG 0x5C
97 #endif 97 #endif
98 98
99 /* Bit val in DC_CTRL */ 99 /* Bit val in DC_CTRL */
100 #define DC_CTRL_INV_MODE_FLUSH 0x40 100 #define DC_CTRL_INV_MODE_FLUSH 0x40
101 #define DC_CTRL_FLUSH_STATUS 0x100 101 #define DC_CTRL_FLUSH_STATUS 0x100
102 102
103 char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len) 103 char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
104 { 104 {
105 int n = 0; 105 int n = 0;
106 unsigned int c = smp_processor_id(); 106 unsigned int c = smp_processor_id();
107 107
108 #define PR_CACHE(p, enb, str) \ 108 #define PR_CACHE(p, enb, str) \
109 { \ 109 { \
110 if (!(p)->ver) \ 110 if (!(p)->ver) \
111 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ 111 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
112 else \ 112 else \
113 n += scnprintf(buf + n, len - n, \ 113 n += scnprintf(buf + n, len - n, \
114 str"\t\t: (%uK) VIPT, %dway set-asc, %ub Line %s\n", \ 114 str"\t\t: (%uK) VIPT, %dway set-asc, %ub Line %s\n", \
115 TO_KB((p)->sz), (p)->assoc, (p)->line_len, \ 115 TO_KB((p)->sz), (p)->assoc, (p)->line_len, \
116 enb ? "" : "DISABLED (kernel-build)"); \ 116 enb ? "" : "DISABLED (kernel-build)"); \
117 } 117 }
118 118
119 PR_CACHE(&cpuinfo_arc700[c].icache, IS_ENABLED(CONFIG_ARC_HAS_ICACHE), 119 PR_CACHE(&cpuinfo_arc700[c].icache, IS_ENABLED(CONFIG_ARC_HAS_ICACHE),
120 "I-Cache"); 120 "I-Cache");
121 PR_CACHE(&cpuinfo_arc700[c].dcache, IS_ENABLED(CONFIG_ARC_HAS_DCACHE), 121 PR_CACHE(&cpuinfo_arc700[c].dcache, IS_ENABLED(CONFIG_ARC_HAS_DCACHE),
122 "D-Cache"); 122 "D-Cache");
123 123
124 return buf; 124 return buf;
125 } 125 }
126 126
127 /* 127 /*
128 * Read the Cache Build Confuration Registers, Decode them and save into 128 * Read the Cache Build Confuration Registers, Decode them and save into
129 * the cpuinfo structure for later use. 129 * the cpuinfo structure for later use.
130 * No Validation done here, simply read/convert the BCRs 130 * No Validation done here, simply read/convert the BCRs
131 */ 131 */
132 void read_decode_cache_bcr(void) 132 void read_decode_cache_bcr(void)
133 { 133 {
134 struct cpuinfo_arc_cache *p_ic, *p_dc; 134 struct cpuinfo_arc_cache *p_ic, *p_dc;
135 unsigned int cpu = smp_processor_id(); 135 unsigned int cpu = smp_processor_id();
136 struct bcr_cache { 136 struct bcr_cache {
137 #ifdef CONFIG_CPU_BIG_ENDIAN 137 #ifdef CONFIG_CPU_BIG_ENDIAN
138 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; 138 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
139 #else 139 #else
140 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; 140 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
141 #endif 141 #endif
142 } ibcr, dbcr; 142 } ibcr, dbcr;
143 143
144 p_ic = &cpuinfo_arc700[cpu].icache; 144 p_ic = &cpuinfo_arc700[cpu].icache;
145 READ_BCR(ARC_REG_IC_BCR, ibcr); 145 READ_BCR(ARC_REG_IC_BCR, ibcr);
146 146
147 BUG_ON(ibcr.config != 3); 147 BUG_ON(ibcr.config != 3);
148 p_ic->assoc = 2; /* Fixed to 2w set assoc */ 148 p_ic->assoc = 2; /* Fixed to 2w set assoc */
149 p_ic->line_len = 8 << ibcr.line_len; 149 p_ic->line_len = 8 << ibcr.line_len;
150 p_ic->sz = 0x200 << ibcr.sz; 150 p_ic->sz = 0x200 << ibcr.sz;
151 p_ic->ver = ibcr.ver; 151 p_ic->ver = ibcr.ver;
152 152
153 p_dc = &cpuinfo_arc700[cpu].dcache; 153 p_dc = &cpuinfo_arc700[cpu].dcache;
154 READ_BCR(ARC_REG_DC_BCR, dbcr); 154 READ_BCR(ARC_REG_DC_BCR, dbcr);
155 155
156 BUG_ON(dbcr.config != 2); 156 BUG_ON(dbcr.config != 2);
157 p_dc->assoc = 4; /* Fixed to 4w set assoc */ 157 p_dc->assoc = 4; /* Fixed to 4w set assoc */
158 p_dc->line_len = 16 << dbcr.line_len; 158 p_dc->line_len = 16 << dbcr.line_len;
159 p_dc->sz = 0x200 << dbcr.sz; 159 p_dc->sz = 0x200 << dbcr.sz;
160 p_dc->ver = dbcr.ver; 160 p_dc->ver = dbcr.ver;
161 } 161 }
162 162
163 /* 163 /*
164 * 1. Validate the Cache Geomtery (compile time config matches hardware) 164 * 1. Validate the Cache Geomtery (compile time config matches hardware)
165 * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn) 165 * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn)
166 * (aliasing D-cache configurations are not supported YET) 166 * (aliasing D-cache configurations are not supported YET)
167 * 3. Enable the Caches, setup default flush mode for D-Cache 167 * 3. Enable the Caches, setup default flush mode for D-Cache
168 * 3. Calculate the SHMLBA used by user space 168 * 3. Calculate the SHMLBA used by user space
169 */ 169 */
170 void arc_cache_init(void) 170 void arc_cache_init(void)
171 { 171 {
172 unsigned int cpu = smp_processor_id(); 172 unsigned int cpu = smp_processor_id();
173 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; 173 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
174 struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; 174 struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
175 unsigned int dcache_does_alias, temp; 175 unsigned int dcache_does_alias, temp;
176 char str[256]; 176 char str[256];
177 177
178 printk(arc_cache_mumbojumbo(0, str, sizeof(str))); 178 printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
179 179
180 if (!ic->ver) 180 if (!ic->ver)
181 goto chk_dc; 181 goto chk_dc;
182 182
183 #ifdef CONFIG_ARC_HAS_ICACHE 183 #ifdef CONFIG_ARC_HAS_ICACHE
184 /* 1. Confirm some of I-cache params which Linux assumes */ 184 /* 1. Confirm some of I-cache params which Linux assumes */
185 if (ic->line_len != L1_CACHE_BYTES) 185 if (ic->line_len != L1_CACHE_BYTES)
186 panic("Cache H/W doesn't match kernel Config"); 186 panic("Cache H/W doesn't match kernel Config");
187 187
188 if (ic->ver != CONFIG_ARC_MMU_VER) 188 if (ic->ver != CONFIG_ARC_MMU_VER)
189 panic("Cache ver doesn't match MMU ver\n"); 189 panic("Cache ver doesn't match MMU ver\n");
190 #endif 190 #endif
191 191
192 /* Enable/disable I-Cache */ 192 /* Enable/disable I-Cache */
193 temp = read_aux_reg(ARC_REG_IC_CTRL); 193 temp = read_aux_reg(ARC_REG_IC_CTRL);
194 194
195 #ifdef CONFIG_ARC_HAS_ICACHE 195 #ifdef CONFIG_ARC_HAS_ICACHE
196 temp &= ~IC_CTRL_CACHE_DISABLE; 196 temp &= ~IC_CTRL_CACHE_DISABLE;
197 #else 197 #else
198 temp |= IC_CTRL_CACHE_DISABLE; 198 temp |= IC_CTRL_CACHE_DISABLE;
199 #endif 199 #endif
200 200
201 write_aux_reg(ARC_REG_IC_CTRL, temp); 201 write_aux_reg(ARC_REG_IC_CTRL, temp);
202 202
203 chk_dc: 203 chk_dc:
204 if (!dc->ver) 204 if (!dc->ver)
205 return; 205 return;
206 206
207 #ifdef CONFIG_ARC_HAS_DCACHE 207 #ifdef CONFIG_ARC_HAS_DCACHE
208 if (dc->line_len != L1_CACHE_BYTES) 208 if (dc->line_len != L1_CACHE_BYTES)
209 panic("Cache H/W doesn't match kernel Config"); 209 panic("Cache H/W doesn't match kernel Config");
210 210
211 /* check for D-Cache aliasing */ 211 /* check for D-Cache aliasing */
212 dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE; 212 dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE;
213 213
214 if (dcache_does_alias && !cache_is_vipt_aliasing()) 214 if (dcache_does_alias && !cache_is_vipt_aliasing())
215 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); 215 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
216 else if (!dcache_does_alias && cache_is_vipt_aliasing()) 216 else if (!dcache_does_alias && cache_is_vipt_aliasing())
217 panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n"); 217 panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
218 #endif 218 #endif
219 219
220 /* Set the default Invalidate Mode to "simpy discard dirty lines" 220 /* Set the default Invalidate Mode to "simpy discard dirty lines"
221 * as this is more frequent then flush before invalidate 221 * as this is more frequent then flush before invalidate
222 * Ofcourse we toggle this default behviour when desired 222 * Ofcourse we toggle this default behviour when desired
223 */ 223 */
224 temp = read_aux_reg(ARC_REG_DC_CTRL); 224 temp = read_aux_reg(ARC_REG_DC_CTRL);
225 temp &= ~DC_CTRL_INV_MODE_FLUSH; 225 temp &= ~DC_CTRL_INV_MODE_FLUSH;
226 226
227 #ifdef CONFIG_ARC_HAS_DCACHE 227 #ifdef CONFIG_ARC_HAS_DCACHE
228 /* Enable D-Cache: Clear Bit 0 */ 228 /* Enable D-Cache: Clear Bit 0 */
229 write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE); 229 write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE);
230 #else 230 #else
231 /* Flush D cache */ 231 /* Flush D cache */
232 write_aux_reg(ARC_REG_DC_FLSH, 0x1); 232 write_aux_reg(ARC_REG_DC_FLSH, 0x1);
233 /* Disable D cache */ 233 /* Disable D cache */
234 write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE); 234 write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE);
235 #endif 235 #endif
236 236
237 return; 237 return;
238 } 238 }
239 239
240 #define OP_INV 0x1 240 #define OP_INV 0x1
241 #define OP_FLUSH 0x2 241 #define OP_FLUSH 0x2
242 #define OP_FLUSH_N_INV 0x3 242 #define OP_FLUSH_N_INV 0x3
243 #define OP_INV_IC 0x4
243 244
245 /*
246 * Common Helper for Line Operations on {I,D}-Cache
247 */
248 static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr,
249 unsigned long sz, const int cacheop)
250 {
251 unsigned int aux_cmd, aux_tag;
252 int num_lines;
253
254 if (cacheop == OP_INV_IC) {
255 aux_cmd = ARC_REG_IC_IVIL;
256 aux_tag = ARC_REG_IC_PTAG;
257 }
258 else {
259 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
260 aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
261 aux_tag = ARC_REG_DC_PTAG;
262 }
263
264 /* Ensure we properly floor/ceil the non-line aligned/sized requests
265 * and have @paddr - aligned to cache line and integral @num_lines.
266 * This however can be avoided for page sized since:
267 * -@paddr will be cache-line aligned already (being page aligned)
268 * -@sz will be integral multiple of line size (being page sized).
269 */
270 if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) {
271 sz += paddr & ~CACHE_LINE_MASK;
272 paddr &= CACHE_LINE_MASK;
273 vaddr &= CACHE_LINE_MASK;
274 }
275
276 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
277
278 #if (CONFIG_ARC_MMU_VER <= 2)
279 /* MMUv2 and before: paddr contains stuffed vaddrs bits */
280 paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
281 #endif
282
283 while (num_lines-- > 0) {
284 #if (CONFIG_ARC_MMU_VER > 2)
285 /* MMUv3, cache ops require paddr seperately */
286 write_aux_reg(ARC_REG_DC_PTAG, paddr);
287
288 write_aux_reg(aux_cmd, vaddr);
289 vaddr += L1_CACHE_BYTES;
290 #else
291 write_aux_reg(aux, paddr);
292 #endif
293 paddr += L1_CACHE_BYTES;
294 }
295 }
296
244 #ifdef CONFIG_ARC_HAS_DCACHE 297 #ifdef CONFIG_ARC_HAS_DCACHE
245 298
246 /*************************************************************** 299 /***************************************************************
247 * Machine specific helpers for Entire D-Cache or Per Line ops 300 * Machine specific helpers for Entire D-Cache or Per Line ops
248 */ 301 */
249 302
250 static inline void wait_for_flush(void) 303 static inline void wait_for_flush(void)
251 { 304 {
252 while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS) 305 while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
253 ; 306 ;
254 } 307 }
255 308
256 /* 309 /*
257 * Operation on Entire D-Cache 310 * Operation on Entire D-Cache
258 * @cacheop = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV} 311 * @cacheop = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
259 * Note that constant propagation ensures all the checks are gone 312 * Note that constant propagation ensures all the checks are gone
260 * in generated code 313 * in generated code
261 */ 314 */
262 static inline void __dc_entire_op(const int cacheop) 315 static inline void __dc_entire_op(const int cacheop)
263 { 316 {
264 unsigned int tmp = tmp; 317 unsigned int tmp = tmp;
265 int aux; 318 int aux;
266 319
267 if (cacheop == OP_FLUSH_N_INV) { 320 if (cacheop == OP_FLUSH_N_INV) {
268 /* Dcache provides 2 cmd: FLUSH or INV 321 /* Dcache provides 2 cmd: FLUSH or INV
269 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE 322 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
270 * flush-n-inv is achieved by INV cmd but with IM=1 323 * flush-n-inv is achieved by INV cmd but with IM=1
271 * Default INV sub-mode is DISCARD, which needs to be toggled 324 * Default INV sub-mode is DISCARD, which needs to be toggled
272 */ 325 */
273 tmp = read_aux_reg(ARC_REG_DC_CTRL); 326 tmp = read_aux_reg(ARC_REG_DC_CTRL);
274 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH); 327 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
275 } 328 }
276 329
277 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 330 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
278 aux = ARC_REG_DC_IVDC; 331 aux = ARC_REG_DC_IVDC;
279 else 332 else
280 aux = ARC_REG_DC_FLSH; 333 aux = ARC_REG_DC_FLSH;
281 334
282 write_aux_reg(aux, 0x1); 335 write_aux_reg(aux, 0x1);
283 336
284 if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */ 337 if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
285 wait_for_flush(); 338 wait_for_flush();
286 339
287 /* Switch back the DISCARD ONLY Invalidate mode */ 340 /* Switch back the DISCARD ONLY Invalidate mode */
288 if (cacheop == OP_FLUSH_N_INV) 341 if (cacheop == OP_FLUSH_N_INV)
289 write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH); 342 write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
290 } 343 }
291 344
292 /*
293 * Per Line Operation on D-Cache
294 * Doesn't deal with type-of-op/IRQ-disabling/waiting-for-flush-to-complete
295 * It's sole purpose is to help gcc generate ZOL
296 * (aliasing VIPT dcache flushing needs both vaddr and paddr)
297 */
298 static inline void __dc_line_loop(unsigned long paddr, unsigned long vaddr,
299 unsigned long sz, const int cacheop)
300 {
301 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
302 const int aux = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
303 int num_lines;
304
305 /* Ensure we properly floor/ceil the non-line aligned/sized requests
306 * and have @paddr - aligned to cache line and integral @num_lines.
307 * This however can be avoided for page sized since:
308 * -@paddr will be cache-line aligned already (being page aligned)
309 * -@sz will be integral multiple of line size (being page sized).
310 */
311 if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) {
312 sz += paddr & ~CACHE_LINE_MASK;
313 paddr &= CACHE_LINE_MASK;
314 vaddr &= CACHE_LINE_MASK;
315 }
316
317 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
318
319 #if (CONFIG_ARC_MMU_VER <= 2)
320 paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
321 #endif
322
323 while (num_lines-- > 0) {
324 #if (CONFIG_ARC_MMU_VER > 2)
325 /*
326 * Just as for I$, in MMU v3, D$ ops also require
327 * "tag" bits in DC_PTAG, "index" bits in FLDL,IVDL ops
328 */
329 write_aux_reg(ARC_REG_DC_PTAG, paddr);
330
331 write_aux_reg(aux, vaddr);
332 vaddr += L1_CACHE_BYTES;
333 #else
334 /* paddr contains stuffed vaddrs bits */
335 write_aux_reg(aux, paddr);
336 #endif
337 paddr += L1_CACHE_BYTES;
338 }
339 }
340
341 /* For kernel mappings cache operation: index is same as paddr */ 345 /* For kernel mappings cache operation: index is same as paddr */
342 #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op) 346 #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
343 347
344 /* 348 /*
345 * D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback) 349 * D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback)
346 */ 350 */
347 static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr, 351 static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr,
348 unsigned long sz, const int cacheop) 352 unsigned long sz, const int cacheop)
349 { 353 {
350 unsigned long flags, tmp = tmp; 354 unsigned long flags, tmp = tmp;
351 355
352 local_irq_save(flags); 356 local_irq_save(flags);
353 357
354 if (cacheop == OP_FLUSH_N_INV) { 358 if (cacheop == OP_FLUSH_N_INV) {
355 /* 359 /*
356 * Dcache provides 2 cmd: FLUSH or INV 360 * Dcache provides 2 cmd: FLUSH or INV
357 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE 361 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
358 * flush-n-inv is achieved by INV cmd but with IM=1 362 * flush-n-inv is achieved by INV cmd but with IM=1
359 * Default INV sub-mode is DISCARD, which needs to be toggled 363 * Default INV sub-mode is DISCARD, which needs to be toggled
360 */ 364 */
361 tmp = read_aux_reg(ARC_REG_DC_CTRL); 365 tmp = read_aux_reg(ARC_REG_DC_CTRL);
362 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH); 366 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
363 } 367 }
364 368
365 __dc_line_loop(paddr, vaddr, sz, cacheop); 369 __cache_line_loop(paddr, vaddr, sz, cacheop);
366 370
367 if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */ 371 if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
368 wait_for_flush(); 372 wait_for_flush();
369 373
370 /* Switch back the DISCARD ONLY Invalidate mode */ 374 /* Switch back the DISCARD ONLY Invalidate mode */
371 if (cacheop == OP_FLUSH_N_INV) 375 if (cacheop == OP_FLUSH_N_INV)
372 write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH); 376 write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
373 377
374 local_irq_restore(flags); 378 local_irq_restore(flags);
375 } 379 }
376 380
377 #else 381 #else
378 382
379 #define __dc_entire_op(cacheop) 383 #define __dc_entire_op(cacheop)
380 #define __dc_line_op(paddr, vaddr, sz, cacheop) 384 #define __dc_line_op(paddr, vaddr, sz, cacheop)
381 #define __dc_line_op_k(paddr, sz, cacheop) 385 #define __dc_line_op_k(paddr, sz, cacheop)
382 386
383 #endif /* CONFIG_ARC_HAS_DCACHE */ 387 #endif /* CONFIG_ARC_HAS_DCACHE */
384 388
385 389
386 #ifdef CONFIG_ARC_HAS_ICACHE 390 #ifdef CONFIG_ARC_HAS_ICACHE
387 391
388 /* 392 /*
389 * I-Cache Aliasing in ARC700 VIPT caches 393 * I-Cache Aliasing in ARC700 VIPT caches
390 * 394 *
391 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag. 395 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
392 * The orig Cache Management Module "CDU" only required paddr to invalidate a 396 * The orig Cache Management Module "CDU" only required paddr to invalidate a
393 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry. 397 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
394 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching 398 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
395 * the exact same line. 399 * the exact same line.
396 * 400 *
397 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config, 401 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
398 * paddr alone could not be used to correctly index the cache. 402 * paddr alone could not be used to correctly index the cache.
399 * 403 *
400 * ------------------ 404 * ------------------
401 * MMU v1/v2 (Fixed Page Size 8k) 405 * MMU v1/v2 (Fixed Page Size 8k)
402 * ------------------ 406 * ------------------
403 * The solution was to provide CDU with these additonal vaddr bits. These 407 * The solution was to provide CDU with these additonal vaddr bits. These
404 * would be bits [x:13], x would depend on cache-geometry, 13 comes from 408 * would be bits [x:13], x would depend on cache-geometry, 13 comes from
405 * standard page size of 8k. 409 * standard page size of 8k.
406 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits 410 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
407 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the 411 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
408 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they 412 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they
409 * represent the offset within cache-line. The adv of using this "clumsy" 413 * represent the offset within cache-line. The adv of using this "clumsy"
410 * interface for additional info was no new reg was needed in CDU programming 414 * interface for additional info was no new reg was needed in CDU programming
411 * model. 415 * model.
412 * 416 *
413 * 17:13 represented the max num of bits passable, actual bits needed were 417 * 17:13 represented the max num of bits passable, actual bits needed were
414 * fewer, based on the num-of-aliases possible. 418 * fewer, based on the num-of-aliases possible.
415 * -for 2 alias possibility, only bit 13 needed (32K cache) 419 * -for 2 alias possibility, only bit 13 needed (32K cache)
416 * -for 4 alias possibility, bits 14:13 needed (64K cache) 420 * -for 4 alias possibility, bits 14:13 needed (64K cache)
417 * 421 *
418 * ------------------ 422 * ------------------
419 * MMU v3 423 * MMU v3
420 * ------------------ 424 * ------------------
421 * This ver of MMU supports variable page sizes (1k-16k): although Linux will 425 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
422 * only support 8k (default), 16k and 4k. 426 * only support 8k (default), 16k and 4k.
423 * However from hardware perspective, smaller page sizes aggrevate aliasing 427 * However from hardware perspective, smaller page sizes aggrevate aliasing
424 * meaning more vaddr bits needed to disambiguate the cache-line-op ; 428 * meaning more vaddr bits needed to disambiguate the cache-line-op ;
425 * the existing scheme of piggybacking won't work for certain configurations. 429 * the existing scheme of piggybacking won't work for certain configurations.
426 * Two new registers IC_PTAG and DC_PTAG inttoduced. 430 * Two new registers IC_PTAG and DC_PTAG inttoduced.
427 * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs 431 * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
428 */ 432 */
429 433
430 /*********************************************************** 434 /***********************************************************
431 * Machine specific helper for per line I-Cache invalidate. 435 * Machine specific helper for per line I-Cache invalidate.
432 */ 436 */
433 static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr, 437 static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr,
434 unsigned long sz) 438 unsigned long sz)
435 { 439 {
436 unsigned long flags; 440 unsigned long flags;
437 int num_lines;
438 441
439 /*
440 * Ensure we properly floor/ceil the non-line aligned/sized requests:
441 * However page sized flushes can be compile time optimised.
442 * -@paddr will be cache-line aligned already (being page aligned)
443 * -@sz will be integral multiple of line size (being page sized).
444 */
445 if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) {
446 sz += paddr & ~CACHE_LINE_MASK;
447 paddr &= CACHE_LINE_MASK;
448 vaddr &= CACHE_LINE_MASK;
449 }
450
451 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
452
453 #if (CONFIG_ARC_MMU_VER <= 2)
454 /* bits 17:13 of vaddr go as bits 4:0 of paddr */
455 paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
456 #endif
457
458 local_irq_save(flags); 442 local_irq_save(flags);
459 while (num_lines-- > 0) { 443 __cache_line_loop(paddr, vaddr, sz, OP_INV_IC);
460 #if (CONFIG_ARC_MMU_VER > 2)
461 /* tag comes from phy addr */
462 write_aux_reg(ARC_REG_IC_PTAG, paddr);
463
464 /* index bits come from vaddr */
465 write_aux_reg(ARC_REG_IC_IVIL, vaddr);
466 vaddr += L1_CACHE_BYTES;
467 #else
468 /* paddr contains stuffed vaddrs bits */
469 write_aux_reg(ARC_REG_IC_IVIL, paddr);
470 #endif
471 paddr += L1_CACHE_BYTES;
472 }
473 local_irq_restore(flags); 444 local_irq_restore(flags);
474 } 445 }
475 446
476 static inline void __ic_entire_inv(void) 447 static inline void __ic_entire_inv(void)
477 { 448 {
478 write_aux_reg(ARC_REG_IC_IVIC, 1); 449 write_aux_reg(ARC_REG_IC_IVIC, 1);
479 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ 450 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */
480 } 451 }
481 452
482 #else 453 #else
483 454
484 #define __ic_entire_inv() 455 #define __ic_entire_inv()
485 #define __ic_line_inv_vaddr(pstart, vstart, sz) 456 #define __ic_line_inv_vaddr(pstart, vstart, sz)
486 457
487 #endif /* CONFIG_ARC_HAS_ICACHE */ 458 #endif /* CONFIG_ARC_HAS_ICACHE */
488 459
489 460
490 /*********************************************************** 461 /***********************************************************
491 * Exported APIs 462 * Exported APIs
492 */ 463 */
493 464
494 /* 465 /*
495 * Handle cache congruency of kernel and userspace mappings of page when kernel 466 * Handle cache congruency of kernel and userspace mappings of page when kernel
496 * writes-to/reads-from 467 * writes-to/reads-from
497 * 468 *
498 * The idea is to defer flushing of kernel mapping after a WRITE, possible if: 469 * The idea is to defer flushing of kernel mapping after a WRITE, possible if:
499 * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent 470 * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent
500 * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache) 471 * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache)
501 * -In SMP, if hardware caches are coherent 472 * -In SMP, if hardware caches are coherent
502 * 473 *
503 * There's a corollary case, where kernel READs from a userspace mapped page. 474 * There's a corollary case, where kernel READs from a userspace mapped page.
504 * If the U-mapping is not congruent to to K-mapping, former needs flushing. 475 * If the U-mapping is not congruent to to K-mapping, former needs flushing.
505 */ 476 */
506 void flush_dcache_page(struct page *page) 477 void flush_dcache_page(struct page *page)
507 { 478 {
508 struct address_space *mapping; 479 struct address_space *mapping;
509 480
510 if (!cache_is_vipt_aliasing()) { 481 if (!cache_is_vipt_aliasing()) {
511 clear_bit(PG_dc_clean, &page->flags); 482 clear_bit(PG_dc_clean, &page->flags);
512 return; 483 return;
513 } 484 }
514 485
515 /* don't handle anon pages here */ 486 /* don't handle anon pages here */
516 mapping = page_mapping(page); 487 mapping = page_mapping(page);
517 if (!mapping) 488 if (!mapping)
518 return; 489 return;
519 490
520 /* 491 /*
521 * pagecache page, file not yet mapped to userspace 492 * pagecache page, file not yet mapped to userspace
522 * Make a note that K-mapping is dirty 493 * Make a note that K-mapping is dirty
523 */ 494 */
524 if (!mapping_mapped(mapping)) { 495 if (!mapping_mapped(mapping)) {
525 clear_bit(PG_dc_clean, &page->flags); 496 clear_bit(PG_dc_clean, &page->flags);
526 } else if (page_mapped(page)) { 497 } else if (page_mapped(page)) {
527 498
528 /* kernel reading from page with U-mapping */ 499 /* kernel reading from page with U-mapping */
529 void *paddr = page_address(page); 500 void *paddr = page_address(page);
530 unsigned long vaddr = page->index << PAGE_CACHE_SHIFT; 501 unsigned long vaddr = page->index << PAGE_CACHE_SHIFT;
531 502
532 if (addr_not_cache_congruent(paddr, vaddr)) 503 if (addr_not_cache_congruent(paddr, vaddr))
533 __flush_dcache_page(paddr, vaddr); 504 __flush_dcache_page(paddr, vaddr);
534 } 505 }
535 } 506 }
536 EXPORT_SYMBOL(flush_dcache_page); 507 EXPORT_SYMBOL(flush_dcache_page);
537 508
538 509
539 void dma_cache_wback_inv(unsigned long start, unsigned long sz) 510 void dma_cache_wback_inv(unsigned long start, unsigned long sz)
540 { 511 {
541 __dc_line_op_k(start, sz, OP_FLUSH_N_INV); 512 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
542 } 513 }
543 EXPORT_SYMBOL(dma_cache_wback_inv); 514 EXPORT_SYMBOL(dma_cache_wback_inv);
544 515
545 void dma_cache_inv(unsigned long start, unsigned long sz) 516 void dma_cache_inv(unsigned long start, unsigned long sz)
546 { 517 {
547 __dc_line_op_k(start, sz, OP_INV); 518 __dc_line_op_k(start, sz, OP_INV);
548 } 519 }
549 EXPORT_SYMBOL(dma_cache_inv); 520 EXPORT_SYMBOL(dma_cache_inv);
550 521
551 void dma_cache_wback(unsigned long start, unsigned long sz) 522 void dma_cache_wback(unsigned long start, unsigned long sz)
552 { 523 {
553 __dc_line_op_k(start, sz, OP_FLUSH); 524 __dc_line_op_k(start, sz, OP_FLUSH);
554 } 525 }
555 EXPORT_SYMBOL(dma_cache_wback); 526 EXPORT_SYMBOL(dma_cache_wback);
556 527
557 /* 528 /*
558 * This is API for making I/D Caches consistent when modifying 529 * This is API for making I/D Caches consistent when modifying
559 * kernel code (loadable modules, kprobes, kgdb...) 530 * kernel code (loadable modules, kprobes, kgdb...)
560 * This is called on insmod, with kernel virtual address for CODE of 531 * This is called on insmod, with kernel virtual address for CODE of
561 * the module. ARC cache maintenance ops require PHY address thus we 532 * the module. ARC cache maintenance ops require PHY address thus we
562 * need to convert vmalloc addr to PHY addr 533 * need to convert vmalloc addr to PHY addr
563 */ 534 */
564 void flush_icache_range(unsigned long kstart, unsigned long kend) 535 void flush_icache_range(unsigned long kstart, unsigned long kend)
565 { 536 {
566 unsigned int tot_sz, off, sz; 537 unsigned int tot_sz, off, sz;
567 unsigned long phy, pfn; 538 unsigned long phy, pfn;
568 539
569 /* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */ 540 /* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */
570 541
571 /* This is not the right API for user virtual address */ 542 /* This is not the right API for user virtual address */
572 if (kstart < TASK_SIZE) { 543 if (kstart < TASK_SIZE) {
573 BUG_ON("Flush icache range for user virtual addr space"); 544 BUG_ON("Flush icache range for user virtual addr space");
574 return; 545 return;
575 } 546 }
576 547
577 /* Shortcut for bigger flush ranges. 548 /* Shortcut for bigger flush ranges.
578 * Here we don't care if this was kernel virtual or phy addr 549 * Here we don't care if this was kernel virtual or phy addr
579 */ 550 */
580 tot_sz = kend - kstart; 551 tot_sz = kend - kstart;
581 if (tot_sz > PAGE_SIZE) { 552 if (tot_sz > PAGE_SIZE) {
582 flush_cache_all(); 553 flush_cache_all();
583 return; 554 return;
584 } 555 }
585 556
586 /* Case: Kernel Phy addr (0x8000_0000 onwards) */ 557 /* Case: Kernel Phy addr (0x8000_0000 onwards) */
587 if (likely(kstart > PAGE_OFFSET)) { 558 if (likely(kstart > PAGE_OFFSET)) {
588 /* 559 /*
589 * The 2nd arg despite being paddr will be used to index icache 560 * The 2nd arg despite being paddr will be used to index icache
590 * This is OK since no alternate virtual mappings will exist 561 * This is OK since no alternate virtual mappings will exist
591 * given the callers for this case: kprobe/kgdb in built-in 562 * given the callers for this case: kprobe/kgdb in built-in
592 * kernel code only. 563 * kernel code only.
593 */ 564 */
594 __sync_icache_dcache(kstart, kstart, kend - kstart); 565 __sync_icache_dcache(kstart, kstart, kend - kstart);
595 return; 566 return;
596 } 567 }
597 568
598 /* 569 /*
599 * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff) 570 * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff)
600 * (1) ARC Cache Maintenance ops only take Phy addr, hence special 571 * (1) ARC Cache Maintenance ops only take Phy addr, hence special
601 * handling of kernel vaddr. 572 * handling of kernel vaddr.
602 * 573 *
603 * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already), 574 * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already),
604 * it still needs to handle a 2 page scenario, where the range 575 * it still needs to handle a 2 page scenario, where the range
605 * straddles across 2 virtual pages and hence need for loop 576 * straddles across 2 virtual pages and hence need for loop
606 */ 577 */
607 while (tot_sz > 0) { 578 while (tot_sz > 0) {
608 off = kstart % PAGE_SIZE; 579 off = kstart % PAGE_SIZE;
609 pfn = vmalloc_to_pfn((void *)kstart); 580 pfn = vmalloc_to_pfn((void *)kstart);
610 phy = (pfn << PAGE_SHIFT) + off; 581 phy = (pfn << PAGE_SHIFT) + off;
611 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off); 582 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off);
612 __sync_icache_dcache(phy, kstart, sz); 583 __sync_icache_dcache(phy, kstart, sz);
613 kstart += sz; 584 kstart += sz;
614 tot_sz -= sz; 585 tot_sz -= sz;
615 } 586 }
616 } 587 }
617 588
618 /* 589 /*
619 * General purpose helper to make I and D cache lines consistent. 590 * General purpose helper to make I and D cache lines consistent.
620 * @paddr is phy addr of region 591 * @paddr is phy addr of region
621 * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc) 592 * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
622 * However in one instance, when called by kprobe (for a breakpt in 593 * However in one instance, when called by kprobe (for a breakpt in
623 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will 594 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
624 * use a paddr to index the cache (despite VIPT). This is fine since since a 595 * use a paddr to index the cache (despite VIPT). This is fine since since a
625 * builtin kernel page will not have any virtual mappings. 596 * builtin kernel page will not have any virtual mappings.
626 * kprobe on loadable module will be kernel vaddr. 597 * kprobe on loadable module will be kernel vaddr.
627 */ 598 */
628 void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len) 599 void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len)
629 { 600 {
630 unsigned long flags; 601 unsigned long flags;
631 602
632 local_irq_save(flags); 603 local_irq_save(flags);
633 __ic_line_inv_vaddr(paddr, vaddr, len); 604 __ic_line_inv_vaddr(paddr, vaddr, len);
634 __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV); 605 __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV);
635 local_irq_restore(flags); 606 local_irq_restore(flags);
636 } 607 }
637 608
638 /* wrapper to compile time eliminate alignment checks in flush loop */ 609 /* wrapper to compile time eliminate alignment checks in flush loop */
639 void __inv_icache_page(unsigned long paddr, unsigned long vaddr) 610 void __inv_icache_page(unsigned long paddr, unsigned long vaddr)
640 { 611 {
641 __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE); 612 __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
642 } 613 }
643 614
644 /* 615 /*
645 * wrapper to clearout kernel or userspace mappings of a page 616 * wrapper to clearout kernel or userspace mappings of a page
646 * For kernel mappings @vaddr == @paddr 617 * For kernel mappings @vaddr == @paddr
647 */ 618 */
648 void ___flush_dcache_page(unsigned long paddr, unsigned long vaddr) 619 void ___flush_dcache_page(unsigned long paddr, unsigned long vaddr)
649 { 620 {
650 __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV); 621 __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV);
651 } 622 }
652 623
653 noinline void flush_cache_all(void) 624 noinline void flush_cache_all(void)
654 { 625 {
655 unsigned long flags; 626 unsigned long flags;
656 627
657 local_irq_save(flags); 628 local_irq_save(flags);
658 629
659 __ic_entire_inv(); 630 __ic_entire_inv();
660 __dc_entire_op(OP_FLUSH_N_INV); 631 __dc_entire_op(OP_FLUSH_N_INV);
661 632
662 local_irq_restore(flags); 633 local_irq_restore(flags);
663 634
664 } 635 }
665 636
666 #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING 637 #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
667 638
668 void flush_cache_mm(struct mm_struct *mm) 639 void flush_cache_mm(struct mm_struct *mm)
669 { 640 {
670 flush_cache_all(); 641 flush_cache_all();
671 } 642 }
672 643
673 void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr, 644 void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr,
674 unsigned long pfn) 645 unsigned long pfn)
675 { 646 {
676 unsigned int paddr = pfn << PAGE_SHIFT; 647 unsigned int paddr = pfn << PAGE_SHIFT;
677 648
678 u_vaddr &= PAGE_MASK; 649 u_vaddr &= PAGE_MASK;
679 650
680 ___flush_dcache_page(paddr, u_vaddr); 651 ___flush_dcache_page(paddr, u_vaddr);
681 652
682 if (vma->vm_flags & VM_EXEC) 653 if (vma->vm_flags & VM_EXEC)
683 __inv_icache_page(paddr, u_vaddr); 654 __inv_icache_page(paddr, u_vaddr);
684 } 655 }
685 656
686 void flush_cache_range(struct vm_area_struct *vma, unsigned long start, 657 void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
687 unsigned long end) 658 unsigned long end)
688 { 659 {
689 flush_cache_all(); 660 flush_cache_all();
690 } 661 }
691 662
692 void flush_anon_page(struct vm_area_struct *vma, struct page *page, 663 void flush_anon_page(struct vm_area_struct *vma, struct page *page,
693 unsigned long u_vaddr) 664 unsigned long u_vaddr)
694 { 665 {
695 /* TBD: do we really need to clear the kernel mapping */ 666 /* TBD: do we really need to clear the kernel mapping */
696 __flush_dcache_page(page_address(page), u_vaddr); 667 __flush_dcache_page(page_address(page), u_vaddr);
697 __flush_dcache_page(page_address(page), page_address(page)); 668 __flush_dcache_page(page_address(page), page_address(page));
698 669
699 } 670 }
700 671
701 #endif 672 #endif
702 673
703 void copy_user_highpage(struct page *to, struct page *from, 674 void copy_user_highpage(struct page *to, struct page *from,
704 unsigned long u_vaddr, struct vm_area_struct *vma) 675 unsigned long u_vaddr, struct vm_area_struct *vma)
705 { 676 {
706 void *kfrom = page_address(from); 677 void *kfrom = page_address(from);
707 void *kto = page_address(to); 678 void *kto = page_address(to);
708 int clean_src_k_mappings = 0; 679 int clean_src_k_mappings = 0;
709 680
710 /* 681 /*
711 * If SRC page was already mapped in userspace AND it's U-mapping is 682 * If SRC page was already mapped in userspace AND it's U-mapping is