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Commit c2c93dbc97622e26dc19edc71e50ebaa996d7804

Authored by Mauro Carvalho Chehab
1 parent c66b5a79a9
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

edac: remove proc_name from mci structure 

proc_name isn't used anywhere. Remove it.

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

Showing 1 changed file with 0 additions and 2 deletions Inline Diff

include/linux/edac.h
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1 /* 1 /*
2 * Generic EDAC defs 2 * Generic EDAC defs
3 * 3 *
4 * Author: Dave Jiang <djiang@mvista.com> 4 * Author: Dave Jiang <djiang@mvista.com>
5 * 5 *
6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under 6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
10 * 10 *
11 */ 11 */
12 #ifndef _LINUX_EDAC_H_ 12 #ifndef _LINUX_EDAC_H_
13 #define _LINUX_EDAC_H_ 13 #define _LINUX_EDAC_H_
14 14
15 #include <linux/atomic.h> 15 #include <linux/atomic.h>
16 #include <linux/device.h> 16 #include <linux/device.h>
17 #include <linux/completion.h> 17 #include <linux/completion.h>
18 #include <linux/workqueue.h> 18 #include <linux/workqueue.h>
19 #include <linux/debugfs.h> 19 #include <linux/debugfs.h>
20 20
21 struct device; 21 struct device;
22 22
23 #define EDAC_OPSTATE_INVAL -1 23 #define EDAC_OPSTATE_INVAL -1
24 #define EDAC_OPSTATE_POLL 0 24 #define EDAC_OPSTATE_POLL 0
25 #define EDAC_OPSTATE_NMI 1 25 #define EDAC_OPSTATE_NMI 1
26 #define EDAC_OPSTATE_INT 2 26 #define EDAC_OPSTATE_INT 2
27 27
28 extern int edac_op_state; 28 extern int edac_op_state;
29 extern int edac_err_assert; 29 extern int edac_err_assert;
30 extern atomic_t edac_handlers; 30 extern atomic_t edac_handlers;
31 extern struct bus_type edac_subsys; 31 extern struct bus_type edac_subsys;
32 32
33 extern int edac_handler_set(void); 33 extern int edac_handler_set(void);
34 extern void edac_atomic_assert_error(void); 34 extern void edac_atomic_assert_error(void);
35 extern struct bus_type *edac_get_sysfs_subsys(void); 35 extern struct bus_type *edac_get_sysfs_subsys(void);
36 extern void edac_put_sysfs_subsys(void); 36 extern void edac_put_sysfs_subsys(void);
37 37
38 static inline void opstate_init(void) 38 static inline void opstate_init(void)
39 { 39 {
40 switch (edac_op_state) { 40 switch (edac_op_state) {
41 case EDAC_OPSTATE_POLL: 41 case EDAC_OPSTATE_POLL:
42 case EDAC_OPSTATE_NMI: 42 case EDAC_OPSTATE_NMI:
43 break; 43 break;
44 default: 44 default:
45 edac_op_state = EDAC_OPSTATE_POLL; 45 edac_op_state = EDAC_OPSTATE_POLL;
46 } 46 }
47 return; 47 return;
48 } 48 }
49 49
50 #define EDAC_MC_LABEL_LEN 31 50 #define EDAC_MC_LABEL_LEN 31
51 #define MC_PROC_NAME_MAX_LEN 7
52 51
53 /** 52 /**
54 * enum dev_type - describe the type of memory DRAM chips used at the stick 53 * enum dev_type - describe the type of memory DRAM chips used at the stick
55 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it 54 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
56 * @DEV_X1: 1 bit for data 55 * @DEV_X1: 1 bit for data
57 * @DEV_X2: 2 bits for data 56 * @DEV_X2: 2 bits for data
58 * @DEV_X4: 4 bits for data 57 * @DEV_X4: 4 bits for data
59 * @DEV_X8: 8 bits for data 58 * @DEV_X8: 8 bits for data
60 * @DEV_X16: 16 bits for data 59 * @DEV_X16: 16 bits for data
61 * @DEV_X32: 32 bits for data 60 * @DEV_X32: 32 bits for data
62 * @DEV_X64: 64 bits for data 61 * @DEV_X64: 64 bits for data
63 * 62 *
64 * Typical values are x4 and x8. 63 * Typical values are x4 and x8.
65 */ 64 */
66 enum dev_type { 65 enum dev_type {
67 DEV_UNKNOWN = 0, 66 DEV_UNKNOWN = 0,
68 DEV_X1, 67 DEV_X1,
69 DEV_X2, 68 DEV_X2,
70 DEV_X4, 69 DEV_X4,
71 DEV_X8, 70 DEV_X8,
72 DEV_X16, 71 DEV_X16,
73 DEV_X32, /* Do these parts exist? */ 72 DEV_X32, /* Do these parts exist? */
74 DEV_X64 /* Do these parts exist? */ 73 DEV_X64 /* Do these parts exist? */
75 }; 74 };
76 75
77 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) 76 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
78 #define DEV_FLAG_X1 BIT(DEV_X1) 77 #define DEV_FLAG_X1 BIT(DEV_X1)
79 #define DEV_FLAG_X2 BIT(DEV_X2) 78 #define DEV_FLAG_X2 BIT(DEV_X2)
80 #define DEV_FLAG_X4 BIT(DEV_X4) 79 #define DEV_FLAG_X4 BIT(DEV_X4)
81 #define DEV_FLAG_X8 BIT(DEV_X8) 80 #define DEV_FLAG_X8 BIT(DEV_X8)
82 #define DEV_FLAG_X16 BIT(DEV_X16) 81 #define DEV_FLAG_X16 BIT(DEV_X16)
83 #define DEV_FLAG_X32 BIT(DEV_X32) 82 #define DEV_FLAG_X32 BIT(DEV_X32)
84 #define DEV_FLAG_X64 BIT(DEV_X64) 83 #define DEV_FLAG_X64 BIT(DEV_X64)
85 84
86 /** 85 /**
87 * enum hw_event_mc_err_type - type of the detected error 86 * enum hw_event_mc_err_type - type of the detected error
88 * 87 *
89 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC 88 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
90 * corrected error was detected 89 * corrected error was detected
91 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that 90 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
92 * can't be corrected by ECC, but it is not 91 * can't be corrected by ECC, but it is not
93 * fatal (maybe it is on an unused memory area, 92 * fatal (maybe it is on an unused memory area,
94 * or the memory controller could recover from 93 * or the memory controller could recover from
95 * it for example, by re-trying the operation). 94 * it for example, by re-trying the operation).
96 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not 95 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
97 * be recovered. 96 * be recovered.
98 */ 97 */
99 enum hw_event_mc_err_type { 98 enum hw_event_mc_err_type {
100 HW_EVENT_ERR_CORRECTED, 99 HW_EVENT_ERR_CORRECTED,
101 HW_EVENT_ERR_UNCORRECTED, 100 HW_EVENT_ERR_UNCORRECTED,
102 HW_EVENT_ERR_FATAL, 101 HW_EVENT_ERR_FATAL,
103 }; 102 };
104 103
105 /** 104 /**
106 * enum mem_type - memory types. For a more detailed reference, please see 105 * enum mem_type - memory types. For a more detailed reference, please see
107 * http://en.wikipedia.org/wiki/DRAM 106 * http://en.wikipedia.org/wiki/DRAM
108 * 107 *
109 * @MEM_EMPTY Empty csrow 108 * @MEM_EMPTY Empty csrow
110 * @MEM_RESERVED: Reserved csrow type 109 * @MEM_RESERVED: Reserved csrow type
111 * @MEM_UNKNOWN: Unknown csrow type 110 * @MEM_UNKNOWN: Unknown csrow type
112 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995. 111 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
113 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998. 112 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
114 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant. 113 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
115 * @MEM_SDR: SDR - Single data rate SDRAM 114 * @MEM_SDR: SDR - Single data rate SDRAM
116 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory 115 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
117 * They use 3 pins for chip select: Pins 0 and 2 are 116 * They use 3 pins for chip select: Pins 0 and 2 are
118 * for rank 0; pins 1 and 3 are for rank 1, if the memory 117 * for rank 0; pins 1 and 3 are for rank 1, if the memory
119 * is dual-rank. 118 * is dual-rank.
120 * @MEM_RDR: Registered SDR SDRAM 119 * @MEM_RDR: Registered SDR SDRAM
121 * @MEM_DDR: Double data rate SDRAM 120 * @MEM_DDR: Double data rate SDRAM
122 * http://en.wikipedia.org/wiki/DDR_SDRAM 121 * http://en.wikipedia.org/wiki/DDR_SDRAM
123 * @MEM_RDDR: Registered Double data rate SDRAM 122 * @MEM_RDDR: Registered Double data rate SDRAM
124 * This is a variant of the DDR memories. 123 * This is a variant of the DDR memories.
125 * A registered memory has a buffer inside it, hiding 124 * A registered memory has a buffer inside it, hiding
126 * part of the memory details to the memory controller. 125 * part of the memory details to the memory controller.
127 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers. 126 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
128 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F. 127 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
129 * Those memories are labed as "PC2-" instead of "PC" to 128 * Those memories are labed as "PC2-" instead of "PC" to
130 * differenciate from DDR. 129 * differenciate from DDR.
131 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205 130 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
132 * and JESD206. 131 * and JESD206.
133 * Those memories are accessed per DIMM slot, and not by 132 * Those memories are accessed per DIMM slot, and not by
134 * a chip select signal. 133 * a chip select signal.
135 * @MEM_RDDR2: Registered DDR2 RAM 134 * @MEM_RDDR2: Registered DDR2 RAM
136 * This is a variant of the DDR2 memories. 135 * This is a variant of the DDR2 memories.
137 * @MEM_XDR: Rambus XDR 136 * @MEM_XDR: Rambus XDR
138 * It is an evolution of the original RAMBUS memories, 137 * It is an evolution of the original RAMBUS memories,
139 * created to compete with DDR2. Weren't used on any 138 * created to compete with DDR2. Weren't used on any
140 * x86 arch, but cell_edac PPC memory controller uses it. 139 * x86 arch, but cell_edac PPC memory controller uses it.
141 * @MEM_DDR3: DDR3 RAM 140 * @MEM_DDR3: DDR3 RAM
142 * @MEM_RDDR3: Registered DDR3 RAM 141 * @MEM_RDDR3: Registered DDR3 RAM
143 * This is a variant of the DDR3 memories. 142 * This is a variant of the DDR3 memories.
144 */ 143 */
145 enum mem_type { 144 enum mem_type {
146 MEM_EMPTY = 0, 145 MEM_EMPTY = 0,
147 MEM_RESERVED, 146 MEM_RESERVED,
148 MEM_UNKNOWN, 147 MEM_UNKNOWN,
149 MEM_FPM, 148 MEM_FPM,
150 MEM_EDO, 149 MEM_EDO,
151 MEM_BEDO, 150 MEM_BEDO,
152 MEM_SDR, 151 MEM_SDR,
153 MEM_RDR, 152 MEM_RDR,
154 MEM_DDR, 153 MEM_DDR,
155 MEM_RDDR, 154 MEM_RDDR,
156 MEM_RMBS, 155 MEM_RMBS,
157 MEM_DDR2, 156 MEM_DDR2,
158 MEM_FB_DDR2, 157 MEM_FB_DDR2,
159 MEM_RDDR2, 158 MEM_RDDR2,
160 MEM_XDR, 159 MEM_XDR,
161 MEM_DDR3, 160 MEM_DDR3,
162 MEM_RDDR3, 161 MEM_RDDR3,
163 }; 162 };
164 163
165 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) 164 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
166 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED) 165 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
167 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) 166 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
168 #define MEM_FLAG_FPM BIT(MEM_FPM) 167 #define MEM_FLAG_FPM BIT(MEM_FPM)
169 #define MEM_FLAG_EDO BIT(MEM_EDO) 168 #define MEM_FLAG_EDO BIT(MEM_EDO)
170 #define MEM_FLAG_BEDO BIT(MEM_BEDO) 169 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
171 #define MEM_FLAG_SDR BIT(MEM_SDR) 170 #define MEM_FLAG_SDR BIT(MEM_SDR)
172 #define MEM_FLAG_RDR BIT(MEM_RDR) 171 #define MEM_FLAG_RDR BIT(MEM_RDR)
173 #define MEM_FLAG_DDR BIT(MEM_DDR) 172 #define MEM_FLAG_DDR BIT(MEM_DDR)
174 #define MEM_FLAG_RDDR BIT(MEM_RDDR) 173 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
175 #define MEM_FLAG_RMBS BIT(MEM_RMBS) 174 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
176 #define MEM_FLAG_DDR2 BIT(MEM_DDR2) 175 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
177 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) 176 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
178 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) 177 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
179 #define MEM_FLAG_XDR BIT(MEM_XDR) 178 #define MEM_FLAG_XDR BIT(MEM_XDR)
180 #define MEM_FLAG_DDR3 BIT(MEM_DDR3) 179 #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
181 #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3) 180 #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
182 181
183 /** 182 /**
184 * enum edac-type - Error Detection and Correction capabilities and mode 183 * enum edac-type - Error Detection and Correction capabilities and mode
185 * @EDAC_UNKNOWN: Unknown if ECC is available 184 * @EDAC_UNKNOWN: Unknown if ECC is available
186 * @EDAC_NONE: Doesn't support ECC 185 * @EDAC_NONE: Doesn't support ECC
187 * @EDAC_RESERVED: Reserved ECC type 186 * @EDAC_RESERVED: Reserved ECC type
188 * @EDAC_PARITY: Detects parity errors 187 * @EDAC_PARITY: Detects parity errors
189 * @EDAC_EC: Error Checking - no correction 188 * @EDAC_EC: Error Checking - no correction
190 * @EDAC_SECDED: Single bit error correction, Double detection 189 * @EDAC_SECDED: Single bit error correction, Double detection
191 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist? 190 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
192 * @EDAC_S4ECD4ED: Chipkill x4 devices 191 * @EDAC_S4ECD4ED: Chipkill x4 devices
193 * @EDAC_S8ECD8ED: Chipkill x8 devices 192 * @EDAC_S8ECD8ED: Chipkill x8 devices
194 * @EDAC_S16ECD16ED: Chipkill x16 devices 193 * @EDAC_S16ECD16ED: Chipkill x16 devices
195 */ 194 */
196 enum edac_type { 195 enum edac_type {
197 EDAC_UNKNOWN = 0, 196 EDAC_UNKNOWN = 0,
198 EDAC_NONE, 197 EDAC_NONE,
199 EDAC_RESERVED, 198 EDAC_RESERVED,
200 EDAC_PARITY, 199 EDAC_PARITY,
201 EDAC_EC, 200 EDAC_EC,
202 EDAC_SECDED, 201 EDAC_SECDED,
203 EDAC_S2ECD2ED, 202 EDAC_S2ECD2ED,
204 EDAC_S4ECD4ED, 203 EDAC_S4ECD4ED,
205 EDAC_S8ECD8ED, 204 EDAC_S8ECD8ED,
206 EDAC_S16ECD16ED, 205 EDAC_S16ECD16ED,
207 }; 206 };
208 207
209 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) 208 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
210 #define EDAC_FLAG_NONE BIT(EDAC_NONE) 209 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
211 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY) 210 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
212 #define EDAC_FLAG_EC BIT(EDAC_EC) 211 #define EDAC_FLAG_EC BIT(EDAC_EC)
213 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED) 212 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
214 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) 213 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
215 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) 214 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
216 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) 215 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
217 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) 216 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
218 217
219 /** 218 /**
220 * enum scrub_type - scrubbing capabilities 219 * enum scrub_type - scrubbing capabilities
221 * @SCRUB_UNKNOWN Unknown if scrubber is available 220 * @SCRUB_UNKNOWN Unknown if scrubber is available
222 * @SCRUB_NONE: No scrubber 221 * @SCRUB_NONE: No scrubber
223 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing 222 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
224 * @SCRUB_SW_SRC: Software scrub only errors 223 * @SCRUB_SW_SRC: Software scrub only errors
225 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error 224 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
226 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable 225 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
227 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing 226 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
228 * @SCRUB_HW_SRC: Hardware scrub only errors 227 * @SCRUB_HW_SRC: Hardware scrub only errors
229 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error 228 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
230 * SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable 229 * SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
231 */ 230 */
232 enum scrub_type { 231 enum scrub_type {
233 SCRUB_UNKNOWN = 0, 232 SCRUB_UNKNOWN = 0,
234 SCRUB_NONE, 233 SCRUB_NONE,
235 SCRUB_SW_PROG, 234 SCRUB_SW_PROG,
236 SCRUB_SW_SRC, 235 SCRUB_SW_SRC,
237 SCRUB_SW_PROG_SRC, 236 SCRUB_SW_PROG_SRC,
238 SCRUB_SW_TUNABLE, 237 SCRUB_SW_TUNABLE,
239 SCRUB_HW_PROG, 238 SCRUB_HW_PROG,
240 SCRUB_HW_SRC, 239 SCRUB_HW_SRC,
241 SCRUB_HW_PROG_SRC, 240 SCRUB_HW_PROG_SRC,
242 SCRUB_HW_TUNABLE 241 SCRUB_HW_TUNABLE
243 }; 242 };
244 243
245 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) 244 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
246 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC) 245 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
247 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC) 246 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
248 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE) 247 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
249 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) 248 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
250 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC) 249 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
251 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC) 250 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
252 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) 251 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
253 252
254 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */ 253 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
255 254
256 /* EDAC internal operation states */ 255 /* EDAC internal operation states */
257 #define OP_ALLOC 0x100 256 #define OP_ALLOC 0x100
258 #define OP_RUNNING_POLL 0x201 257 #define OP_RUNNING_POLL 0x201
259 #define OP_RUNNING_INTERRUPT 0x202 258 #define OP_RUNNING_INTERRUPT 0x202
260 #define OP_RUNNING_POLL_INTR 0x203 259 #define OP_RUNNING_POLL_INTR 0x203
261 #define OP_OFFLINE 0x300 260 #define OP_OFFLINE 0x300
262 261
263 /* 262 /*
264 * Concepts used at the EDAC subsystem 263 * Concepts used at the EDAC subsystem
265 * 264 *
266 * There are several things to be aware of that aren't at all obvious: 265 * There are several things to be aware of that aren't at all obvious:
267 * 266 *
268 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc.. 267 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
269 * 268 *
270 * These are some of the many terms that are thrown about that don't always 269 * These are some of the many terms that are thrown about that don't always
271 * mean what people think they mean (Inconceivable!). In the interest of 270 * mean what people think they mean (Inconceivable!). In the interest of
272 * creating a common ground for discussion, terms and their definitions 271 * creating a common ground for discussion, terms and their definitions
273 * will be established. 272 * will be established.
274 * 273 *
275 * Memory devices: The individual DRAM chips on a memory stick. These 274 * Memory devices: The individual DRAM chips on a memory stick. These
276 * devices commonly output 4 and 8 bits each (x4, x8). 275 * devices commonly output 4 and 8 bits each (x4, x8).
277 * Grouping several of these in parallel provides the 276 * Grouping several of these in parallel provides the
278 * number of bits that the memory controller expects: 277 * number of bits that the memory controller expects:
279 * typically 72 bits, in order to provide 64 bits + 278 * typically 72 bits, in order to provide 64 bits +
280 * 8 bits of ECC data. 279 * 8 bits of ECC data.
281 * 280 *
282 * Memory Stick: A printed circuit board that aggregates multiple 281 * Memory Stick: A printed circuit board that aggregates multiple
283 * memory devices in parallel. In general, this is the 282 * memory devices in parallel. In general, this is the
284 * Field Replaceable Unit (FRU) which gets replaced, in 283 * Field Replaceable Unit (FRU) which gets replaced, in
285 * the case of excessive errors. Most often it is also 284 * the case of excessive errors. Most often it is also
286 * called DIMM (Dual Inline Memory Module). 285 * called DIMM (Dual Inline Memory Module).
287 * 286 *
288 * Memory Socket: A physical connector on the motherboard that accepts 287 * Memory Socket: A physical connector on the motherboard that accepts
289 * a single memory stick. Also called as "slot" on several 288 * a single memory stick. Also called as "slot" on several
290 * datasheets. 289 * datasheets.
291 * 290 *
292 * Channel: A memory controller channel, responsible to communicate 291 * Channel: A memory controller channel, responsible to communicate
293 * with a group of DIMMs. Each channel has its own 292 * with a group of DIMMs. Each channel has its own
294 * independent control (command) and data bus, and can 293 * independent control (command) and data bus, and can
295 * be used independently or grouped with other channels. 294 * be used independently or grouped with other channels.
296 * 295 *
297 * Branch: It is typically the highest hierarchy on a 296 * Branch: It is typically the highest hierarchy on a
298 * Fully-Buffered DIMM memory controller. 297 * Fully-Buffered DIMM memory controller.
299 * Typically, it contains two channels. 298 * Typically, it contains two channels.
300 * Two channels at the same branch can be used in single 299 * Two channels at the same branch can be used in single
301 * mode or in lockstep mode. 300 * mode or in lockstep mode.
302 * When lockstep is enabled, the cacheline is doubled, 301 * When lockstep is enabled, the cacheline is doubled,
303 * but it generally brings some performance penalty. 302 * but it generally brings some performance penalty.
304 * Also, it is generally not possible to point to just one 303 * Also, it is generally not possible to point to just one
305 * memory stick when an error occurs, as the error 304 * memory stick when an error occurs, as the error
306 * correction code is calculated using two DIMMs instead 305 * correction code is calculated using two DIMMs instead
307 * of one. Due to that, it is capable of correcting more 306 * of one. Due to that, it is capable of correcting more
308 * errors than on single mode. 307 * errors than on single mode.
309 * 308 *
310 * Single-channel: The data accessed by the memory controller is contained 309 * Single-channel: The data accessed by the memory controller is contained
311 * into one dimm only. E. g. if the data is 64 bits-wide, 310 * into one dimm only. E. g. if the data is 64 bits-wide,
312 * the data flows to the CPU using one 64 bits parallel 311 * the data flows to the CPU using one 64 bits parallel
313 * access. 312 * access.
314 * Typically used with SDR, DDR, DDR2 and DDR3 memories. 313 * Typically used with SDR, DDR, DDR2 and DDR3 memories.
315 * FB-DIMM and RAMBUS use a different concept for channel, 314 * FB-DIMM and RAMBUS use a different concept for channel,
316 * so this concept doesn't apply there. 315 * so this concept doesn't apply there.
317 * 316 *
318 * Double-channel: The data size accessed by the memory controller is 317 * Double-channel: The data size accessed by the memory controller is
319 * interlaced into two dimms, accessed at the same time. 318 * interlaced into two dimms, accessed at the same time.
320 * E. g. if the DIMM is 64 bits-wide (72 bits with ECC), 319 * E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
321 * the data flows to the CPU using a 128 bits parallel 320 * the data flows to the CPU using a 128 bits parallel
322 * access. 321 * access.
323 * 322 *
324 * Chip-select row: This is the name of the DRAM signal used to select the 323 * Chip-select row: This is the name of the DRAM signal used to select the
325 * DRAM ranks to be accessed. Common chip-select rows for 324 * DRAM ranks to be accessed. Common chip-select rows for
326 * single channel are 64 bits, for dual channel 128 bits. 325 * single channel are 64 bits, for dual channel 128 bits.
327 * It may not be visible by the memory controller, as some 326 * It may not be visible by the memory controller, as some
328 * DIMM types have a memory buffer that can hide direct 327 * DIMM types have a memory buffer that can hide direct
329 * access to it from the Memory Controller. 328 * access to it from the Memory Controller.
330 * 329 *
331 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory. 330 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
332 * Motherboards commonly drive two chip-select pins to 331 * Motherboards commonly drive two chip-select pins to
333 * a memory stick. A single-ranked stick, will occupy 332 * a memory stick. A single-ranked stick, will occupy
334 * only one of those rows. The other will be unused. 333 * only one of those rows. The other will be unused.
335 * 334 *
336 * Double-Ranked stick: A double-ranked stick has two chip-select rows which 335 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
337 * access different sets of memory devices. The two 336 * access different sets of memory devices. The two
338 * rows cannot be accessed concurrently. 337 * rows cannot be accessed concurrently.
339 * 338 *
340 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick. 339 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
341 * A double-sided stick has two chip-select rows which 340 * A double-sided stick has two chip-select rows which
342 * access different sets of memory devices. The two 341 * access different sets of memory devices. The two
343 * rows cannot be accessed concurrently. "Double-sided" 342 * rows cannot be accessed concurrently. "Double-sided"
344 * is irrespective of the memory devices being mounted 343 * is irrespective of the memory devices being mounted
345 * on both sides of the memory stick. 344 * on both sides of the memory stick.
346 * 345 *
347 * Socket set: All of the memory sticks that are required for 346 * Socket set: All of the memory sticks that are required for
348 * a single memory access or all of the memory sticks 347 * a single memory access or all of the memory sticks
349 * spanned by a chip-select row. A single socket set 348 * spanned by a chip-select row. A single socket set
350 * has two chip-select rows and if double-sided sticks 349 * has two chip-select rows and if double-sided sticks
351 * are used these will occupy those chip-select rows. 350 * are used these will occupy those chip-select rows.
352 * 351 *
353 * Bank: This term is avoided because it is unclear when 352 * Bank: This term is avoided because it is unclear when
354 * needing to distinguish between chip-select rows and 353 * needing to distinguish between chip-select rows and
355 * socket sets. 354 * socket sets.
356 * 355 *
357 * Controller pages: 356 * Controller pages:
358 * 357 *
359 * Physical pages: 358 * Physical pages:
360 * 359 *
361 * Virtual pages: 360 * Virtual pages:
362 * 361 *
363 * 362 *
364 * STRUCTURE ORGANIZATION AND CHOICES 363 * STRUCTURE ORGANIZATION AND CHOICES
365 * 364 *
366 * 365 *
367 * 366 *
368 * PS - I enjoyed writing all that about as much as you enjoyed reading it. 367 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
369 */ 368 */
370 369
371 /** 370 /**
372 * enum edac_mc_layer - memory controller hierarchy layer 371 * enum edac_mc_layer - memory controller hierarchy layer
373 * 372 *
374 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch" 373 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
375 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel" 374 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
376 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot" 375 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
377 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select" 376 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
378 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped 377 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
379 * as a single memory area. This is used when 378 * as a single memory area. This is used when
380 * retrieving errors from a firmware driven driver. 379 * retrieving errors from a firmware driven driver.
381 * 380 *
382 * This enum is used by the drivers to tell edac_mc_sysfs what name should 381 * This enum is used by the drivers to tell edac_mc_sysfs what name should
383 * be used when describing a memory stick location. 382 * be used when describing a memory stick location.
384 */ 383 */
385 enum edac_mc_layer_type { 384 enum edac_mc_layer_type {
386 EDAC_MC_LAYER_BRANCH, 385 EDAC_MC_LAYER_BRANCH,
387 EDAC_MC_LAYER_CHANNEL, 386 EDAC_MC_LAYER_CHANNEL,
388 EDAC_MC_LAYER_SLOT, 387 EDAC_MC_LAYER_SLOT,
389 EDAC_MC_LAYER_CHIP_SELECT, 388 EDAC_MC_LAYER_CHIP_SELECT,
390 EDAC_MC_LAYER_ALL_MEM, 389 EDAC_MC_LAYER_ALL_MEM,
391 }; 390 };
392 391
393 /** 392 /**
394 * struct edac_mc_layer - describes the memory controller hierarchy 393 * struct edac_mc_layer - describes the memory controller hierarchy
395 * @layer: layer type 394 * @layer: layer type
396 * @size: number of components per layer. For example, 395 * @size: number of components per layer. For example,
397 * if the channel layer has two channels, size = 2 396 * if the channel layer has two channels, size = 2
398 * @is_virt_csrow: This layer is part of the "csrow" when old API 397 * @is_virt_csrow: This layer is part of the "csrow" when old API
399 * compatibility mode is enabled. Otherwise, it is 398 * compatibility mode is enabled. Otherwise, it is
400 * a channel 399 * a channel
401 */ 400 */
402 struct edac_mc_layer { 401 struct edac_mc_layer {
403 enum edac_mc_layer_type type; 402 enum edac_mc_layer_type type;
404 unsigned size; 403 unsigned size;
405 bool is_virt_csrow; 404 bool is_virt_csrow;
406 }; 405 };
407 406
408 /* 407 /*
409 * Maximum number of layers used by the memory controller to uniquely 408 * Maximum number of layers used by the memory controller to uniquely
410 * identify a single memory stick. 409 * identify a single memory stick.
411 * NOTE: Changing this constant requires not only to change the constant 410 * NOTE: Changing this constant requires not only to change the constant
412 * below, but also to change the existing code at the core, as there are 411 * below, but also to change the existing code at the core, as there are
413 * some code there that are optimized for 3 layers. 412 * some code there that are optimized for 3 layers.
414 */ 413 */
415 #define EDAC_MAX_LAYERS 3 414 #define EDAC_MAX_LAYERS 3
416 415
417 /** 416 /**
418 * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer array 417 * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer array
419 * for the element given by [layer0,layer1,layer2] position 418 * for the element given by [layer0,layer1,layer2] position
420 * 419 *
421 * @layers: a struct edac_mc_layer array, describing how many elements 420 * @layers: a struct edac_mc_layer array, describing how many elements
422 * were allocated for each layer 421 * were allocated for each layer
423 * @n_layers: Number of layers at the @layers array 422 * @n_layers: Number of layers at the @layers array
424 * @layer0: layer0 position 423 * @layer0: layer0 position
425 * @layer1: layer1 position. Unused if n_layers < 2 424 * @layer1: layer1 position. Unused if n_layers < 2
426 * @layer2: layer2 position. Unused if n_layers < 3 425 * @layer2: layer2 position. Unused if n_layers < 3
427 * 426 *
428 * For 1 layer, this macro returns &var[layer0] - &var 427 * For 1 layer, this macro returns &var[layer0] - &var
429 * For 2 layers, this macro is similar to allocate a bi-dimensional array 428 * For 2 layers, this macro is similar to allocate a bi-dimensional array
430 * and to return "&var[layer0][layer1] - &var" 429 * and to return "&var[layer0][layer1] - &var"
431 * For 3 layers, this macro is similar to allocate a tri-dimensional array 430 * For 3 layers, this macro is similar to allocate a tri-dimensional array
432 * and to return "&var[layer0][layer1][layer2] - &var" 431 * and to return "&var[layer0][layer1][layer2] - &var"
433 * 432 *
434 * A loop could be used here to make it more generic, but, as we only have 433 * A loop could be used here to make it more generic, but, as we only have
435 * 3 layers, this is a little faster. 434 * 3 layers, this is a little faster.
436 * By design, layers can never be 0 or more than 3. If that ever happens, 435 * By design, layers can never be 0 or more than 3. If that ever happens,
437 * a NULL is returned, causing an OOPS during the memory allocation routine, 436 * a NULL is returned, causing an OOPS during the memory allocation routine,
438 * with would point to the developer that he's doing something wrong. 437 * with would point to the developer that he's doing something wrong.
439 */ 438 */
440 #define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \ 439 #define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \
441 int __i; \ 440 int __i; \
442 if ((nlayers) == 1) \ 441 if ((nlayers) == 1) \
443 __i = layer0; \ 442 __i = layer0; \
444 else if ((nlayers) == 2) \ 443 else if ((nlayers) == 2) \
445 __i = (layer1) + ((layers[1]).size * (layer0)); \ 444 __i = (layer1) + ((layers[1]).size * (layer0)); \
446 else if ((nlayers) == 3) \ 445 else if ((nlayers) == 3) \
447 __i = (layer2) + ((layers[2]).size * ((layer1) + \ 446 __i = (layer2) + ((layers[2]).size * ((layer1) + \
448 ((layers[1]).size * (layer0)))); \ 447 ((layers[1]).size * (layer0)))); \
449 else \ 448 else \
450 __i = -EINVAL; \ 449 __i = -EINVAL; \
451 __i; \ 450 __i; \
452 }) 451 })
453 452
454 /** 453 /**
455 * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array 454 * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array
456 * for the element given by [layer0,layer1,layer2] position 455 * for the element given by [layer0,layer1,layer2] position
457 * 456 *
458 * @layers: a struct edac_mc_layer array, describing how many elements 457 * @layers: a struct edac_mc_layer array, describing how many elements
459 * were allocated for each layer 458 * were allocated for each layer
460 * @var: name of the var where we want to get the pointer 459 * @var: name of the var where we want to get the pointer
461 * (like mci->dimms) 460 * (like mci->dimms)
462 * @n_layers: Number of layers at the @layers array 461 * @n_layers: Number of layers at the @layers array
463 * @layer0: layer0 position 462 * @layer0: layer0 position
464 * @layer1: layer1 position. Unused if n_layers < 2 463 * @layer1: layer1 position. Unused if n_layers < 2
465 * @layer2: layer2 position. Unused if n_layers < 3 464 * @layer2: layer2 position. Unused if n_layers < 3
466 * 465 *
467 * For 1 layer, this macro returns &var[layer0] 466 * For 1 layer, this macro returns &var[layer0]
468 * For 2 layers, this macro is similar to allocate a bi-dimensional array 467 * For 2 layers, this macro is similar to allocate a bi-dimensional array
469 * and to return "&var[layer0][layer1]" 468 * and to return "&var[layer0][layer1]"
470 * For 3 layers, this macro is similar to allocate a tri-dimensional array 469 * For 3 layers, this macro is similar to allocate a tri-dimensional array
471 * and to return "&var[layer0][layer1][layer2]" 470 * and to return "&var[layer0][layer1][layer2]"
472 */ 471 */
473 #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \ 472 #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
474 typeof(*var) __p; \ 473 typeof(*var) __p; \
475 int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \ 474 int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \
476 if (___i < 0) \ 475 if (___i < 0) \
477 __p = NULL; \ 476 __p = NULL; \
478 else \ 477 else \
479 __p = (var)[___i]; \ 478 __p = (var)[___i]; \
480 __p; \ 479 __p; \
481 }) 480 })
482 481
483 struct dimm_info { 482 struct dimm_info {
484 struct device dev; 483 struct device dev;
485 484
486 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ 485 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
487 486
488 /* Memory location data */ 487 /* Memory location data */
489 unsigned location[EDAC_MAX_LAYERS]; 488 unsigned location[EDAC_MAX_LAYERS];
490 489
491 struct mem_ctl_info *mci; /* the parent */ 490 struct mem_ctl_info *mci; /* the parent */
492 491
493 u32 grain; /* granularity of reported error in bytes */ 492 u32 grain; /* granularity of reported error in bytes */
494 enum dev_type dtype; /* memory device type */ 493 enum dev_type dtype; /* memory device type */
495 enum mem_type mtype; /* memory dimm type */ 494 enum mem_type mtype; /* memory dimm type */
496 enum edac_type edac_mode; /* EDAC mode for this dimm */ 495 enum edac_type edac_mode; /* EDAC mode for this dimm */
497 496
498 u32 nr_pages; /* number of pages on this dimm */ 497 u32 nr_pages; /* number of pages on this dimm */
499 498
500 unsigned csrow, cschannel; /* Points to the old API data */ 499 unsigned csrow, cschannel; /* Points to the old API data */
501 }; 500 };
502 501
503 /** 502 /**
504 * struct rank_info - contains the information for one DIMM rank 503 * struct rank_info - contains the information for one DIMM rank
505 * 504 *
506 * @chan_idx: channel number where the rank is (typically, 0 or 1) 505 * @chan_idx: channel number where the rank is (typically, 0 or 1)
507 * @ce_count: number of correctable errors for this rank 506 * @ce_count: number of correctable errors for this rank
508 * @csrow: A pointer to the chip select row structure (the parent 507 * @csrow: A pointer to the chip select row structure (the parent
509 * structure). The location of the rank is given by 508 * structure). The location of the rank is given by
510 * the (csrow->csrow_idx, chan_idx) vector. 509 * the (csrow->csrow_idx, chan_idx) vector.
511 * @dimm: A pointer to the DIMM structure, where the DIMM label 510 * @dimm: A pointer to the DIMM structure, where the DIMM label
512 * information is stored. 511 * information is stored.
513 * 512 *
514 * FIXME: Currently, the EDAC core model will assume one DIMM per rank. 513 * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
515 * This is a bad assumption, but it makes this patch easier. Later 514 * This is a bad assumption, but it makes this patch easier. Later
516 * patches in this series will fix this issue. 515 * patches in this series will fix this issue.
517 */ 516 */
518 struct rank_info { 517 struct rank_info {
519 int chan_idx; 518 int chan_idx;
520 struct csrow_info *csrow; 519 struct csrow_info *csrow;
521 struct dimm_info *dimm; 520 struct dimm_info *dimm;
522 521
523 u32 ce_count; /* Correctable Errors for this csrow */ 522 u32 ce_count; /* Correctable Errors for this csrow */
524 }; 523 };
525 524
526 struct csrow_info { 525 struct csrow_info {
527 struct device dev; 526 struct device dev;
528 527
529 /* Used only by edac_mc_find_csrow_by_page() */ 528 /* Used only by edac_mc_find_csrow_by_page() */
530 unsigned long first_page; /* first page number in csrow */ 529 unsigned long first_page; /* first page number in csrow */
531 unsigned long last_page; /* last page number in csrow */ 530 unsigned long last_page; /* last page number in csrow */
532 unsigned long page_mask; /* used for interleaving - 531 unsigned long page_mask; /* used for interleaving -
533 * 0UL for non intlv */ 532 * 0UL for non intlv */
534 533
535 int csrow_idx; /* the chip-select row */ 534 int csrow_idx; /* the chip-select row */
536 535
537 u32 ue_count; /* Uncorrectable Errors for this csrow */ 536 u32 ue_count; /* Uncorrectable Errors for this csrow */
538 u32 ce_count; /* Correctable Errors for this csrow */ 537 u32 ce_count; /* Correctable Errors for this csrow */
539 u32 nr_pages; /* combined pages count of all channels */ 538 u32 nr_pages; /* combined pages count of all channels */
540 539
541 struct mem_ctl_info *mci; /* the parent */ 540 struct mem_ctl_info *mci; /* the parent */
542 541
543 /* channel information for this csrow */ 542 /* channel information for this csrow */
544 u32 nr_channels; 543 u32 nr_channels;
545 struct rank_info **channels; 544 struct rank_info **channels;
546 }; 545 };
547 546
548 /* 547 /*
549 * struct errcount_attribute - used to store the several error counts 548 * struct errcount_attribute - used to store the several error counts
550 */ 549 */
551 struct errcount_attribute_data { 550 struct errcount_attribute_data {
552 int n_layers; 551 int n_layers;
553 int pos[EDAC_MAX_LAYERS]; 552 int pos[EDAC_MAX_LAYERS];
554 int layer0, layer1, layer2; 553 int layer0, layer1, layer2;
555 }; 554 };
556 555
557 /* MEMORY controller information structure 556 /* MEMORY controller information structure
558 */ 557 */
559 struct mem_ctl_info { 558 struct mem_ctl_info {
560 struct device dev; 559 struct device dev;
561 struct bus_type bus; 560 struct bus_type bus;
562 561
563 struct list_head link; /* for global list of mem_ctl_info structs */ 562 struct list_head link; /* for global list of mem_ctl_info structs */
564 563
565 struct module *owner; /* Module owner of this control struct */ 564 struct module *owner; /* Module owner of this control struct */
566 565
567 unsigned long mtype_cap; /* memory types supported by mc */ 566 unsigned long mtype_cap; /* memory types supported by mc */
568 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */ 567 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
569 unsigned long edac_cap; /* configuration capabilities - this is 568 unsigned long edac_cap; /* configuration capabilities - this is
570 * closely related to edac_ctl_cap. The 569 * closely related to edac_ctl_cap. The
571 * difference is that the controller may be 570 * difference is that the controller may be
572 * capable of s4ecd4ed which would be listed 571 * capable of s4ecd4ed which would be listed
573 * in edac_ctl_cap, but if channels aren't 572 * in edac_ctl_cap, but if channels aren't
574 * capable of s4ecd4ed then the edac_cap would 573 * capable of s4ecd4ed then the edac_cap would
575 * not have that capability. 574 * not have that capability.
576 */ 575 */
577 unsigned long scrub_cap; /* chipset scrub capabilities */ 576 unsigned long scrub_cap; /* chipset scrub capabilities */
578 enum scrub_type scrub_mode; /* current scrub mode */ 577 enum scrub_type scrub_mode; /* current scrub mode */
579 578
580 /* Translates sdram memory scrub rate given in bytes/sec to the 579 /* Translates sdram memory scrub rate given in bytes/sec to the
581 internal representation and configures whatever else needs 580 internal representation and configures whatever else needs
582 to be configured. 581 to be configured.
583 */ 582 */
584 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw); 583 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
585 584
586 /* Get the current sdram memory scrub rate from the internal 585 /* Get the current sdram memory scrub rate from the internal
587 representation and converts it to the closest matching 586 representation and converts it to the closest matching
588 bandwidth in bytes/sec. 587 bandwidth in bytes/sec.
589 */ 588 */
590 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci); 589 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
591 590
592 591
593 /* pointer to edac checking routine */ 592 /* pointer to edac checking routine */
594 void (*edac_check) (struct mem_ctl_info * mci); 593 void (*edac_check) (struct mem_ctl_info * mci);
595 594
596 /* 595 /*
597 * Remaps memory pages: controller pages to physical pages. 596 * Remaps memory pages: controller pages to physical pages.
598 * For most MC's, this will be NULL. 597 * For most MC's, this will be NULL.
599 */ 598 */
600 /* FIXME - why not send the phys page to begin with? */ 599 /* FIXME - why not send the phys page to begin with? */
601 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci, 600 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
602 unsigned long page); 601 unsigned long page);
603 int mc_idx; 602 int mc_idx;
604 struct csrow_info **csrows; 603 struct csrow_info **csrows;
605 unsigned nr_csrows, num_cschannel; 604 unsigned nr_csrows, num_cschannel;
606 605
607 /* 606 /*
608 * Memory Controller hierarchy 607 * Memory Controller hierarchy
609 * 608 *
610 * There are basically two types of memory controller: the ones that 609 * There are basically two types of memory controller: the ones that
611 * sees memory sticks ("dimms"), and the ones that sees memory ranks. 610 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
612 * All old memory controllers enumerate memories per rank, but most 611 * All old memory controllers enumerate memories per rank, but most
613 * of the recent drivers enumerate memories per DIMM, instead. 612 * of the recent drivers enumerate memories per DIMM, instead.
614 * When the memory controller is per rank, mem_is_per_rank is true. 613 * When the memory controller is per rank, mem_is_per_rank is true.
615 */ 614 */
616 unsigned n_layers; 615 unsigned n_layers;
617 struct edac_mc_layer *layers; 616 struct edac_mc_layer *layers;
618 bool mem_is_per_rank; 617 bool mem_is_per_rank;
619 618
620 /* 619 /*
621 * DIMM info. Will eventually remove the entire csrows_info some day 620 * DIMM info. Will eventually remove the entire csrows_info some day
622 */ 621 */
623 unsigned tot_dimms; 622 unsigned tot_dimms;
624 struct dimm_info **dimms; 623 struct dimm_info **dimms;
625 624
626 /* 625 /*
627 * FIXME - what about controllers on other busses? - IDs must be 626 * FIXME - what about controllers on other busses? - IDs must be
628 * unique. dev pointer should be sufficiently unique, but 627 * unique. dev pointer should be sufficiently unique, but
629 * BUS:SLOT.FUNC numbers may not be unique. 628 * BUS:SLOT.FUNC numbers may not be unique.
630 */ 629 */
631 struct device *pdev; 630 struct device *pdev;
632 const char *mod_name; 631 const char *mod_name;
633 const char *mod_ver; 632 const char *mod_ver;
634 const char *ctl_name; 633 const char *ctl_name;
635 const char *dev_name; 634 const char *dev_name;
636 char proc_name[MC_PROC_NAME_MAX_LEN + 1];
637 void *pvt_info; 635 void *pvt_info;
638 unsigned long start_time; /* mci load start time (in jiffies) */ 636 unsigned long start_time; /* mci load start time (in jiffies) */
639 637
640 /* 638 /*
641 * drivers shouldn't access those fields directly, as the core 639 * drivers shouldn't access those fields directly, as the core
642 * already handles that. 640 * already handles that.
643 */ 641 */
644 u32 ce_noinfo_count, ue_noinfo_count; 642 u32 ce_noinfo_count, ue_noinfo_count;
645 u32 ue_mc, ce_mc; 643 u32 ue_mc, ce_mc;
646 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; 644 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
647 645
648 struct completion complete; 646 struct completion complete;
649 647
650 /* Additional top controller level attributes, but specified 648 /* Additional top controller level attributes, but specified
651 * by the low level driver. 649 * by the low level driver.
652 * 650 *
653 * Set by the low level driver to provide attributes at the 651 * Set by the low level driver to provide attributes at the
654 * controller level. 652 * controller level.
655 * An array of structures, NULL terminated 653 * An array of structures, NULL terminated
656 * 654 *
657 * If attributes are desired, then set to array of attributes 655 * If attributes are desired, then set to array of attributes
658 * If no attributes are desired, leave NULL 656 * If no attributes are desired, leave NULL
659 */ 657 */
660 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes; 658 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
661 659
662 /* work struct for this MC */ 660 /* work struct for this MC */
663 struct delayed_work work; 661 struct delayed_work work;
664 662
665 /* the internal state of this controller instance */ 663 /* the internal state of this controller instance */
666 int op_state; 664 int op_state;
667 665
668 #ifdef CONFIG_EDAC_DEBUG 666 #ifdef CONFIG_EDAC_DEBUG
669 struct dentry *debugfs; 667 struct dentry *debugfs;
670 u8 fake_inject_layer[EDAC_MAX_LAYERS]; 668 u8 fake_inject_layer[EDAC_MAX_LAYERS];
671 u32 fake_inject_ue; 669 u32 fake_inject_ue;
672 u16 fake_inject_count; 670 u16 fake_inject_count;
673 #endif 671 #endif
674 __u8 csbased : 1, /* csrow-based memory controller */ 672 __u8 csbased : 1, /* csrow-based memory controller */
675 __resv : 7; 673 __resv : 7;
676 }; 674 };
677 675
678 #endif 676 #endif
679 677