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Commit ce4bbeeddb1dfc710554cc69fc21599311975077

Authored by H Hartley Sweeten
Committed by David Woodhouse
1 parent 8b62b0877b
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

sh: Use the plat_nand default partition parser 

Use the default partition parser, cmdlinepart, provided by the plat_nand driver.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

Showing 1 changed file with 0 additions and 1 deletions Inline Diff

arch/sh/boards/mach-migor/setup.c
Diff comments   View file @ ce4bbee
1 /* 1 /*
2 * Renesas System Solutions Asia Pte. Ltd - Migo-R 2 * Renesas System Solutions Asia Pte. Ltd - Migo-R
3 * 3 *
4 * Copyright (C) 2008 Magnus Damm 4 * Copyright (C) 2008 Magnus Damm
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details. 8 * for more details.
9 */ 9 */
10 #include <linux/init.h> 10 #include <linux/init.h>
11 #include <linux/platform_device.h> 11 #include <linux/platform_device.h>
12 #include <linux/interrupt.h> 12 #include <linux/interrupt.h>
13 #include <linux/input.h> 13 #include <linux/input.h>
14 #include <linux/input/sh_keysc.h> 14 #include <linux/input/sh_keysc.h>
15 #include <linux/mmc/host.h> 15 #include <linux/mmc/host.h>
16 #include <linux/mmc/sh_mobile_sdhi.h> 16 #include <linux/mmc/sh_mobile_sdhi.h>
17 #include <linux/mtd/physmap.h> 17 #include <linux/mtd/physmap.h>
18 #include <linux/mtd/nand.h> 18 #include <linux/mtd/nand.h>
19 #include <linux/i2c.h> 19 #include <linux/i2c.h>
20 #include <linux/smc91x.h> 20 #include <linux/smc91x.h>
21 #include <linux/delay.h> 21 #include <linux/delay.h>
22 #include <linux/clk.h> 22 #include <linux/clk.h>
23 #include <linux/gpio.h> 23 #include <linux/gpio.h>
24 #include <linux/videodev2.h> 24 #include <linux/videodev2.h>
25 #include <video/sh_mobile_lcdc.h> 25 #include <video/sh_mobile_lcdc.h>
26 #include <media/sh_mobile_ceu.h> 26 #include <media/sh_mobile_ceu.h>
27 #include <media/ov772x.h> 27 #include <media/ov772x.h>
28 #include <media/soc_camera.h> 28 #include <media/soc_camera.h>
29 #include <media/tw9910.h> 29 #include <media/tw9910.h>
30 #include <asm/clock.h> 30 #include <asm/clock.h>
31 #include <asm/machvec.h> 31 #include <asm/machvec.h>
32 #include <asm/io.h> 32 #include <asm/io.h>
33 #include <asm/suspend.h> 33 #include <asm/suspend.h>
34 #include <mach/migor.h> 34 #include <mach/migor.h>
35 #include <cpu/sh7722.h> 35 #include <cpu/sh7722.h>
36 36
37 /* Address IRQ Size Bus Description 37 /* Address IRQ Size Bus Description
38 * 0x00000000 64MB 16 NOR Flash (SP29PL256N) 38 * 0x00000000 64MB 16 NOR Flash (SP29PL256N)
39 * 0x0c000000 64MB 64 SDRAM (2xK4M563233G) 39 * 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
40 * 0x10000000 IRQ0 16 Ethernet (SMC91C111) 40 * 0x10000000 IRQ0 16 Ethernet (SMC91C111)
41 * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596) 41 * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
42 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A) 42 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
43 */ 43 */
44 44
45 static struct smc91x_platdata smc91x_info = { 45 static struct smc91x_platdata smc91x_info = {
46 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, 46 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
47 }; 47 };
48 48
49 static struct resource smc91x_eth_resources[] = { 49 static struct resource smc91x_eth_resources[] = {
50 [0] = { 50 [0] = {
51 .name = "SMC91C111" , 51 .name = "SMC91C111" ,
52 .start = 0x10000300, 52 .start = 0x10000300,
53 .end = 0x1000030f, 53 .end = 0x1000030f,
54 .flags = IORESOURCE_MEM, 54 .flags = IORESOURCE_MEM,
55 }, 55 },
56 [1] = { 56 [1] = {
57 .start = 32, /* IRQ0 */ 57 .start = 32, /* IRQ0 */
58 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 58 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
59 }, 59 },
60 }; 60 };
61 61
62 static struct platform_device smc91x_eth_device = { 62 static struct platform_device smc91x_eth_device = {
63 .name = "smc91x", 63 .name = "smc91x",
64 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 64 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
65 .resource = smc91x_eth_resources, 65 .resource = smc91x_eth_resources,
66 .dev = { 66 .dev = {
67 .platform_data = &smc91x_info, 67 .platform_data = &smc91x_info,
68 }, 68 },
69 }; 69 };
70 70
71 static struct sh_keysc_info sh_keysc_info = { 71 static struct sh_keysc_info sh_keysc_info = {
72 .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */ 72 .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
73 .scan_timing = 3, 73 .scan_timing = 3,
74 .delay = 5, 74 .delay = 5,
75 .keycodes = { 75 .keycodes = {
76 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER, 76 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
77 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1, 77 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
78 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6, 78 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
79 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0, 79 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
80 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD, 80 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
81 }, 81 },
82 }; 82 };
83 83
84 static struct resource sh_keysc_resources[] = { 84 static struct resource sh_keysc_resources[] = {
85 [0] = { 85 [0] = {
86 .start = 0x044b0000, 86 .start = 0x044b0000,
87 .end = 0x044b000f, 87 .end = 0x044b000f,
88 .flags = IORESOURCE_MEM, 88 .flags = IORESOURCE_MEM,
89 }, 89 },
90 [1] = { 90 [1] = {
91 .start = 79, 91 .start = 79,
92 .flags = IORESOURCE_IRQ, 92 .flags = IORESOURCE_IRQ,
93 }, 93 },
94 }; 94 };
95 95
96 static struct platform_device sh_keysc_device = { 96 static struct platform_device sh_keysc_device = {
97 .name = "sh_keysc", 97 .name = "sh_keysc",
98 .id = 0, /* "keysc0" clock */ 98 .id = 0, /* "keysc0" clock */
99 .num_resources = ARRAY_SIZE(sh_keysc_resources), 99 .num_resources = ARRAY_SIZE(sh_keysc_resources),
100 .resource = sh_keysc_resources, 100 .resource = sh_keysc_resources,
101 .dev = { 101 .dev = {
102 .platform_data = &sh_keysc_info, 102 .platform_data = &sh_keysc_info,
103 }, 103 },
104 }; 104 };
105 105
106 static struct mtd_partition migor_nor_flash_partitions[] = 106 static struct mtd_partition migor_nor_flash_partitions[] =
107 { 107 {
108 { 108 {
109 .name = "uboot", 109 .name = "uboot",
110 .offset = 0, 110 .offset = 0,
111 .size = (1 * 1024 * 1024), 111 .size = (1 * 1024 * 1024),
112 .mask_flags = MTD_WRITEABLE, /* Read-only */ 112 .mask_flags = MTD_WRITEABLE, /* Read-only */
113 }, 113 },
114 { 114 {
115 .name = "rootfs", 115 .name = "rootfs",
116 .offset = MTDPART_OFS_APPEND, 116 .offset = MTDPART_OFS_APPEND,
117 .size = (15 * 1024 * 1024), 117 .size = (15 * 1024 * 1024),
118 }, 118 },
119 { 119 {
120 .name = "other", 120 .name = "other",
121 .offset = MTDPART_OFS_APPEND, 121 .offset = MTDPART_OFS_APPEND,
122 .size = MTDPART_SIZ_FULL, 122 .size = MTDPART_SIZ_FULL,
123 }, 123 },
124 }; 124 };
125 125
126 static struct physmap_flash_data migor_nor_flash_data = { 126 static struct physmap_flash_data migor_nor_flash_data = {
127 .width = 2, 127 .width = 2,
128 .parts = migor_nor_flash_partitions, 128 .parts = migor_nor_flash_partitions,
129 .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions), 129 .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
130 }; 130 };
131 131
132 static struct resource migor_nor_flash_resources[] = { 132 static struct resource migor_nor_flash_resources[] = {
133 [0] = { 133 [0] = {
134 .name = "NOR Flash", 134 .name = "NOR Flash",
135 .start = 0x00000000, 135 .start = 0x00000000,
136 .end = 0x03ffffff, 136 .end = 0x03ffffff,
137 .flags = IORESOURCE_MEM, 137 .flags = IORESOURCE_MEM,
138 } 138 }
139 }; 139 };
140 140
141 static struct platform_device migor_nor_flash_device = { 141 static struct platform_device migor_nor_flash_device = {
142 .name = "physmap-flash", 142 .name = "physmap-flash",
143 .resource = migor_nor_flash_resources, 143 .resource = migor_nor_flash_resources,
144 .num_resources = ARRAY_SIZE(migor_nor_flash_resources), 144 .num_resources = ARRAY_SIZE(migor_nor_flash_resources),
145 .dev = { 145 .dev = {
146 .platform_data = &migor_nor_flash_data, 146 .platform_data = &migor_nor_flash_data,
147 }, 147 },
148 }; 148 };
149 149
150 static struct mtd_partition migor_nand_flash_partitions[] = { 150 static struct mtd_partition migor_nand_flash_partitions[] = {
151 { 151 {
152 .name = "nanddata1", 152 .name = "nanddata1",
153 .offset = 0x0, 153 .offset = 0x0,
154 .size = 512 * 1024 * 1024, 154 .size = 512 * 1024 * 1024,
155 }, 155 },
156 { 156 {
157 .name = "nanddata2", 157 .name = "nanddata2",
158 .offset = MTDPART_OFS_APPEND, 158 .offset = MTDPART_OFS_APPEND,
159 .size = 512 * 1024 * 1024, 159 .size = 512 * 1024 * 1024,
160 }, 160 },
161 }; 161 };
162 162
163 static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd, 163 static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
164 unsigned int ctrl) 164 unsigned int ctrl)
165 { 165 {
166 struct nand_chip *chip = mtd->priv; 166 struct nand_chip *chip = mtd->priv;
167 167
168 if (cmd == NAND_CMD_NONE) 168 if (cmd == NAND_CMD_NONE)
169 return; 169 return;
170 170
171 if (ctrl & NAND_CLE) 171 if (ctrl & NAND_CLE)
172 writeb(cmd, chip->IO_ADDR_W + 0x00400000); 172 writeb(cmd, chip->IO_ADDR_W + 0x00400000);
173 else if (ctrl & NAND_ALE) 173 else if (ctrl & NAND_ALE)
174 writeb(cmd, chip->IO_ADDR_W + 0x00800000); 174 writeb(cmd, chip->IO_ADDR_W + 0x00800000);
175 else 175 else
176 writeb(cmd, chip->IO_ADDR_W); 176 writeb(cmd, chip->IO_ADDR_W);
177 } 177 }
178 178
179 static int migor_nand_flash_ready(struct mtd_info *mtd) 179 static int migor_nand_flash_ready(struct mtd_info *mtd)
180 { 180 {
181 return gpio_get_value(GPIO_PTA1); /* NAND_RBn */ 181 return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
182 } 182 }
183 183
184 static struct platform_nand_data migor_nand_flash_data = { 184 static struct platform_nand_data migor_nand_flash_data = {
185 .chip = { 185 .chip = {
186 .nr_chips = 1, 186 .nr_chips = 1,
187 .partitions = migor_nand_flash_partitions, 187 .partitions = migor_nand_flash_partitions,
188 .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions), 188 .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
189 .chip_delay = 20, 189 .chip_delay = 20,
190 .part_probe_types = (const char *[]) { "cmdlinepart", NULL },
191 }, 190 },
192 .ctrl = { 191 .ctrl = {
193 .dev_ready = migor_nand_flash_ready, 192 .dev_ready = migor_nand_flash_ready,
194 .cmd_ctrl = migor_nand_flash_cmd_ctl, 193 .cmd_ctrl = migor_nand_flash_cmd_ctl,
195 }, 194 },
196 }; 195 };
197 196
198 static struct resource migor_nand_flash_resources[] = { 197 static struct resource migor_nand_flash_resources[] = {
199 [0] = { 198 [0] = {
200 .name = "NAND Flash", 199 .name = "NAND Flash",
201 .start = 0x18000000, 200 .start = 0x18000000,
202 .end = 0x18ffffff, 201 .end = 0x18ffffff,
203 .flags = IORESOURCE_MEM, 202 .flags = IORESOURCE_MEM,
204 }, 203 },
205 }; 204 };
206 205
207 static struct platform_device migor_nand_flash_device = { 206 static struct platform_device migor_nand_flash_device = {
208 .name = "gen_nand", 207 .name = "gen_nand",
209 .resource = migor_nand_flash_resources, 208 .resource = migor_nand_flash_resources,
210 .num_resources = ARRAY_SIZE(migor_nand_flash_resources), 209 .num_resources = ARRAY_SIZE(migor_nand_flash_resources),
211 .dev = { 210 .dev = {
212 .platform_data = &migor_nand_flash_data, 211 .platform_data = &migor_nand_flash_data,
213 } 212 }
214 }; 213 };
215 214
216 static const struct fb_videomode migor_lcd_modes[] = { 215 static const struct fb_videomode migor_lcd_modes[] = {
217 { 216 {
218 #if defined(CONFIG_SH_MIGOR_RTA_WVGA) 217 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
219 .name = "LB070WV1", 218 .name = "LB070WV1",
220 .xres = 800, 219 .xres = 800,
221 .yres = 480, 220 .yres = 480,
222 .left_margin = 64, 221 .left_margin = 64,
223 .right_margin = 16, 222 .right_margin = 16,
224 .hsync_len = 120, 223 .hsync_len = 120,
225 .sync = 0, 224 .sync = 0,
226 #elif defined(CONFIG_SH_MIGOR_QVGA) 225 #elif defined(CONFIG_SH_MIGOR_QVGA)
227 .name = "PH240320T", 226 .name = "PH240320T",
228 .xres = 320, 227 .xres = 320,
229 .yres = 240, 228 .yres = 240,
230 .left_margin = 0, 229 .left_margin = 0,
231 .right_margin = 16, 230 .right_margin = 16,
232 .hsync_len = 8, 231 .hsync_len = 8,
233 .sync = FB_SYNC_HOR_HIGH_ACT, 232 .sync = FB_SYNC_HOR_HIGH_ACT,
234 #endif 233 #endif
235 .upper_margin = 1, 234 .upper_margin = 1,
236 .lower_margin = 17, 235 .lower_margin = 17,
237 .vsync_len = 2, 236 .vsync_len = 2,
238 }, 237 },
239 }; 238 };
240 239
241 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = { 240 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
242 #if defined(CONFIG_SH_MIGOR_RTA_WVGA) 241 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
243 .clock_source = LCDC_CLK_BUS, 242 .clock_source = LCDC_CLK_BUS,
244 .ch[0] = { 243 .ch[0] = {
245 .chan = LCDC_CHAN_MAINLCD, 244 .chan = LCDC_CHAN_MAINLCD,
246 .fourcc = V4L2_PIX_FMT_RGB565, 245 .fourcc = V4L2_PIX_FMT_RGB565,
247 .interface_type = RGB16, 246 .interface_type = RGB16,
248 .clock_divider = 2, 247 .clock_divider = 2,
249 .lcd_modes = migor_lcd_modes, 248 .lcd_modes = migor_lcd_modes,
250 .num_modes = ARRAY_SIZE(migor_lcd_modes), 249 .num_modes = ARRAY_SIZE(migor_lcd_modes),
251 .panel_cfg = { /* 7.0 inch */ 250 .panel_cfg = { /* 7.0 inch */
252 .width = 152, 251 .width = 152,
253 .height = 91, 252 .height = 91,
254 }, 253 },
255 } 254 }
256 #elif defined(CONFIG_SH_MIGOR_QVGA) 255 #elif defined(CONFIG_SH_MIGOR_QVGA)
257 .clock_source = LCDC_CLK_PERIPHERAL, 256 .clock_source = LCDC_CLK_PERIPHERAL,
258 .ch[0] = { 257 .ch[0] = {
259 .chan = LCDC_CHAN_MAINLCD, 258 .chan = LCDC_CHAN_MAINLCD,
260 .fourcc = V4L2_PIX_FMT_RGB565, 259 .fourcc = V4L2_PIX_FMT_RGB565,
261 .interface_type = SYS16A, 260 .interface_type = SYS16A,
262 .clock_divider = 10, 261 .clock_divider = 10,
263 .lcd_modes = migor_lcd_modes, 262 .lcd_modes = migor_lcd_modes,
264 .num_modes = ARRAY_SIZE(migor_lcd_modes), 263 .num_modes = ARRAY_SIZE(migor_lcd_modes),
265 .panel_cfg = { 264 .panel_cfg = {
266 .width = 49, /* 2.4 inch */ 265 .width = 49, /* 2.4 inch */
267 .height = 37, 266 .height = 37,
268 .setup_sys = migor_lcd_qvga_setup, 267 .setup_sys = migor_lcd_qvga_setup,
269 }, 268 },
270 .sys_bus_cfg = { 269 .sys_bus_cfg = {
271 .ldmt2r = 0x06000a09, 270 .ldmt2r = 0x06000a09,
272 .ldmt3r = 0x180e3418, 271 .ldmt3r = 0x180e3418,
273 /* set 1s delay to encourage fsync() */ 272 /* set 1s delay to encourage fsync() */
274 .deferred_io_msec = 1000, 273 .deferred_io_msec = 1000,
275 }, 274 },
276 } 275 }
277 #endif 276 #endif
278 }; 277 };
279 278
280 static struct resource migor_lcdc_resources[] = { 279 static struct resource migor_lcdc_resources[] = {
281 [0] = { 280 [0] = {
282 .name = "LCDC", 281 .name = "LCDC",
283 .start = 0xfe940000, /* P4-only space */ 282 .start = 0xfe940000, /* P4-only space */
284 .end = 0xfe942fff, 283 .end = 0xfe942fff,
285 .flags = IORESOURCE_MEM, 284 .flags = IORESOURCE_MEM,
286 }, 285 },
287 [1] = { 286 [1] = {
288 .start = 28, 287 .start = 28,
289 .flags = IORESOURCE_IRQ, 288 .flags = IORESOURCE_IRQ,
290 }, 289 },
291 }; 290 };
292 291
293 static struct platform_device migor_lcdc_device = { 292 static struct platform_device migor_lcdc_device = {
294 .name = "sh_mobile_lcdc_fb", 293 .name = "sh_mobile_lcdc_fb",
295 .num_resources = ARRAY_SIZE(migor_lcdc_resources), 294 .num_resources = ARRAY_SIZE(migor_lcdc_resources),
296 .resource = migor_lcdc_resources, 295 .resource = migor_lcdc_resources,
297 .dev = { 296 .dev = {
298 .platform_data = &sh_mobile_lcdc_info, 297 .platform_data = &sh_mobile_lcdc_info,
299 }, 298 },
300 }; 299 };
301 300
302 static struct clk *camera_clk; 301 static struct clk *camera_clk;
303 static DEFINE_MUTEX(camera_lock); 302 static DEFINE_MUTEX(camera_lock);
304 303
305 static void camera_power_on(int is_tw) 304 static void camera_power_on(int is_tw)
306 { 305 {
307 mutex_lock(&camera_lock); 306 mutex_lock(&camera_lock);
308 307
309 /* Use 10 MHz VIO_CKO instead of 24 MHz to work 308 /* Use 10 MHz VIO_CKO instead of 24 MHz to work
310 * around signal quality issues on Panel Board V2.1. 309 * around signal quality issues on Panel Board V2.1.
311 */ 310 */
312 camera_clk = clk_get(NULL, "video_clk"); 311 camera_clk = clk_get(NULL, "video_clk");
313 clk_set_rate(camera_clk, 10000000); 312 clk_set_rate(camera_clk, 10000000);
314 clk_enable(camera_clk); /* start VIO_CKO */ 313 clk_enable(camera_clk); /* start VIO_CKO */
315 314
316 /* use VIO_RST to take camera out of reset */ 315 /* use VIO_RST to take camera out of reset */
317 mdelay(10); 316 mdelay(10);
318 if (is_tw) { 317 if (is_tw) {
319 gpio_set_value(GPIO_PTT2, 0); 318 gpio_set_value(GPIO_PTT2, 0);
320 gpio_set_value(GPIO_PTT0, 0); 319 gpio_set_value(GPIO_PTT0, 0);
321 } else { 320 } else {
322 gpio_set_value(GPIO_PTT0, 1); 321 gpio_set_value(GPIO_PTT0, 1);
323 } 322 }
324 gpio_set_value(GPIO_PTT3, 0); 323 gpio_set_value(GPIO_PTT3, 0);
325 mdelay(10); 324 mdelay(10);
326 gpio_set_value(GPIO_PTT3, 1); 325 gpio_set_value(GPIO_PTT3, 1);
327 mdelay(10); /* wait to let chip come out of reset */ 326 mdelay(10); /* wait to let chip come out of reset */
328 } 327 }
329 328
330 static void camera_power_off(void) 329 static void camera_power_off(void)
331 { 330 {
332 clk_disable(camera_clk); /* stop VIO_CKO */ 331 clk_disable(camera_clk); /* stop VIO_CKO */
333 clk_put(camera_clk); 332 clk_put(camera_clk);
334 333
335 gpio_set_value(GPIO_PTT3, 0); 334 gpio_set_value(GPIO_PTT3, 0);
336 mutex_unlock(&camera_lock); 335 mutex_unlock(&camera_lock);
337 } 336 }
338 337
339 static int ov7725_power(struct device *dev, int mode) 338 static int ov7725_power(struct device *dev, int mode)
340 { 339 {
341 if (mode) 340 if (mode)
342 camera_power_on(0); 341 camera_power_on(0);
343 else 342 else
344 camera_power_off(); 343 camera_power_off();
345 344
346 return 0; 345 return 0;
347 } 346 }
348 347
349 static int tw9910_power(struct device *dev, int mode) 348 static int tw9910_power(struct device *dev, int mode)
350 { 349 {
351 if (mode) 350 if (mode)
352 camera_power_on(1); 351 camera_power_on(1);
353 else 352 else
354 camera_power_off(); 353 camera_power_off();
355 354
356 return 0; 355 return 0;
357 } 356 }
358 357
359 static struct sh_mobile_ceu_info sh_mobile_ceu_info = { 358 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
360 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 359 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
361 }; 360 };
362 361
363 static struct resource migor_ceu_resources[] = { 362 static struct resource migor_ceu_resources[] = {
364 [0] = { 363 [0] = {
365 .name = "CEU", 364 .name = "CEU",
366 .start = 0xfe910000, 365 .start = 0xfe910000,
367 .end = 0xfe91009f, 366 .end = 0xfe91009f,
368 .flags = IORESOURCE_MEM, 367 .flags = IORESOURCE_MEM,
369 }, 368 },
370 [1] = { 369 [1] = {
371 .start = 52, 370 .start = 52,
372 .flags = IORESOURCE_IRQ, 371 .flags = IORESOURCE_IRQ,
373 }, 372 },
374 [2] = { 373 [2] = {
375 /* place holder for contiguous memory */ 374 /* place holder for contiguous memory */
376 }, 375 },
377 }; 376 };
378 377
379 static struct platform_device migor_ceu_device = { 378 static struct platform_device migor_ceu_device = {
380 .name = "sh_mobile_ceu", 379 .name = "sh_mobile_ceu",
381 .id = 0, /* "ceu0" clock */ 380 .id = 0, /* "ceu0" clock */
382 .num_resources = ARRAY_SIZE(migor_ceu_resources), 381 .num_resources = ARRAY_SIZE(migor_ceu_resources),
383 .resource = migor_ceu_resources, 382 .resource = migor_ceu_resources,
384 .dev = { 383 .dev = {
385 .platform_data = &sh_mobile_ceu_info, 384 .platform_data = &sh_mobile_ceu_info,
386 }, 385 },
387 }; 386 };
388 387
389 static struct resource sdhi_cn9_resources[] = { 388 static struct resource sdhi_cn9_resources[] = {
390 [0] = { 389 [0] = {
391 .name = "SDHI", 390 .name = "SDHI",
392 .start = 0x04ce0000, 391 .start = 0x04ce0000,
393 .end = 0x04ce00ff, 392 .end = 0x04ce00ff,
394 .flags = IORESOURCE_MEM, 393 .flags = IORESOURCE_MEM,
395 }, 394 },
396 [1] = { 395 [1] = {
397 .start = 100, 396 .start = 100,
398 .flags = IORESOURCE_IRQ, 397 .flags = IORESOURCE_IRQ,
399 }, 398 },
400 }; 399 };
401 400
402 static struct sh_mobile_sdhi_info sh7724_sdhi_data = { 401 static struct sh_mobile_sdhi_info sh7724_sdhi_data = {
403 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 402 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
404 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 403 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
405 .tmio_caps = MMC_CAP_SDIO_IRQ, 404 .tmio_caps = MMC_CAP_SDIO_IRQ,
406 }; 405 };
407 406
408 static struct platform_device sdhi_cn9_device = { 407 static struct platform_device sdhi_cn9_device = {
409 .name = "sh_mobile_sdhi", 408 .name = "sh_mobile_sdhi",
410 .num_resources = ARRAY_SIZE(sdhi_cn9_resources), 409 .num_resources = ARRAY_SIZE(sdhi_cn9_resources),
411 .resource = sdhi_cn9_resources, 410 .resource = sdhi_cn9_resources,
412 .dev = { 411 .dev = {
413 .platform_data = &sh7724_sdhi_data, 412 .platform_data = &sh7724_sdhi_data,
414 }, 413 },
415 }; 414 };
416 415
417 static struct i2c_board_info migor_i2c_devices[] = { 416 static struct i2c_board_info migor_i2c_devices[] = {
418 { 417 {
419 I2C_BOARD_INFO("rs5c372b", 0x32), 418 I2C_BOARD_INFO("rs5c372b", 0x32),
420 }, 419 },
421 { 420 {
422 I2C_BOARD_INFO("migor_ts", 0x51), 421 I2C_BOARD_INFO("migor_ts", 0x51),
423 .irq = 38, /* IRQ6 */ 422 .irq = 38, /* IRQ6 */
424 }, 423 },
425 { 424 {
426 I2C_BOARD_INFO("wm8978", 0x1a), 425 I2C_BOARD_INFO("wm8978", 0x1a),
427 }, 426 },
428 }; 427 };
429 428
430 static struct i2c_board_info migor_i2c_camera[] = { 429 static struct i2c_board_info migor_i2c_camera[] = {
431 { 430 {
432 I2C_BOARD_INFO("ov772x", 0x21), 431 I2C_BOARD_INFO("ov772x", 0x21),
433 }, 432 },
434 { 433 {
435 I2C_BOARD_INFO("tw9910", 0x45), 434 I2C_BOARD_INFO("tw9910", 0x45),
436 }, 435 },
437 }; 436 };
438 437
439 static struct ov772x_camera_info ov7725_info; 438 static struct ov772x_camera_info ov7725_info;
440 439
441 static struct soc_camera_link ov7725_link = { 440 static struct soc_camera_link ov7725_link = {
442 .power = ov7725_power, 441 .power = ov7725_power,
443 .board_info = &migor_i2c_camera[0], 442 .board_info = &migor_i2c_camera[0],
444 .i2c_adapter_id = 0, 443 .i2c_adapter_id = 0,
445 .priv = &ov7725_info, 444 .priv = &ov7725_info,
446 }; 445 };
447 446
448 static struct tw9910_video_info tw9910_info = { 447 static struct tw9910_video_info tw9910_info = {
449 .buswidth = SOCAM_DATAWIDTH_8, 448 .buswidth = SOCAM_DATAWIDTH_8,
450 .mpout = TW9910_MPO_FIELD, 449 .mpout = TW9910_MPO_FIELD,
451 }; 450 };
452 451
453 static struct soc_camera_link tw9910_link = { 452 static struct soc_camera_link tw9910_link = {
454 .power = tw9910_power, 453 .power = tw9910_power,
455 .board_info = &migor_i2c_camera[1], 454 .board_info = &migor_i2c_camera[1],
456 .i2c_adapter_id = 0, 455 .i2c_adapter_id = 0,
457 .priv = &tw9910_info, 456 .priv = &tw9910_info,
458 }; 457 };
459 458
460 static struct platform_device migor_camera[] = { 459 static struct platform_device migor_camera[] = {
461 { 460 {
462 .name = "soc-camera-pdrv", 461 .name = "soc-camera-pdrv",
463 .id = 0, 462 .id = 0,
464 .dev = { 463 .dev = {
465 .platform_data = &ov7725_link, 464 .platform_data = &ov7725_link,
466 }, 465 },
467 }, { 466 }, {
468 .name = "soc-camera-pdrv", 467 .name = "soc-camera-pdrv",
469 .id = 1, 468 .id = 1,
470 .dev = { 469 .dev = {
471 .platform_data = &tw9910_link, 470 .platform_data = &tw9910_link,
472 }, 471 },
473 }, 472 },
474 }; 473 };
475 474
476 static struct platform_device *migor_devices[] __initdata = { 475 static struct platform_device *migor_devices[] __initdata = {
477 &smc91x_eth_device, 476 &smc91x_eth_device,
478 &sh_keysc_device, 477 &sh_keysc_device,
479 &migor_lcdc_device, 478 &migor_lcdc_device,
480 &migor_ceu_device, 479 &migor_ceu_device,
481 &migor_nor_flash_device, 480 &migor_nor_flash_device,
482 &migor_nand_flash_device, 481 &migor_nand_flash_device,
483 &sdhi_cn9_device, 482 &sdhi_cn9_device,
484 &migor_camera[0], 483 &migor_camera[0],
485 &migor_camera[1], 484 &migor_camera[1],
486 }; 485 };
487 486
488 extern char migor_sdram_enter_start; 487 extern char migor_sdram_enter_start;
489 extern char migor_sdram_enter_end; 488 extern char migor_sdram_enter_end;
490 extern char migor_sdram_leave_start; 489 extern char migor_sdram_leave_start;
491 extern char migor_sdram_leave_end; 490 extern char migor_sdram_leave_end;
492 491
493 static int __init migor_devices_setup(void) 492 static int __init migor_devices_setup(void)
494 { 493 {
495 /* register board specific self-refresh code */ 494 /* register board specific self-refresh code */
496 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF, 495 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
497 &migor_sdram_enter_start, 496 &migor_sdram_enter_start,
498 &migor_sdram_enter_end, 497 &migor_sdram_enter_end,
499 &migor_sdram_leave_start, 498 &migor_sdram_leave_start,
500 &migor_sdram_leave_end); 499 &migor_sdram_leave_end);
501 /* Let D11 LED show STATUS0 */ 500 /* Let D11 LED show STATUS0 */
502 gpio_request(GPIO_FN_STATUS0, NULL); 501 gpio_request(GPIO_FN_STATUS0, NULL);
503 502
504 /* Lit D12 LED show PDSTATUS */ 503 /* Lit D12 LED show PDSTATUS */
505 gpio_request(GPIO_FN_PDSTATUS, NULL); 504 gpio_request(GPIO_FN_PDSTATUS, NULL);
506 505
507 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */ 506 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
508 gpio_request(GPIO_FN_IRQ0, NULL); 507 gpio_request(GPIO_FN_IRQ0, NULL);
509 __raw_writel(0x00003400, BSC_CS4BCR); 508 __raw_writel(0x00003400, BSC_CS4BCR);
510 __raw_writel(0x00110080, BSC_CS4WCR); 509 __raw_writel(0x00110080, BSC_CS4WCR);
511 510
512 /* KEYSC */ 511 /* KEYSC */
513 gpio_request(GPIO_FN_KEYOUT0, NULL); 512 gpio_request(GPIO_FN_KEYOUT0, NULL);
514 gpio_request(GPIO_FN_KEYOUT1, NULL); 513 gpio_request(GPIO_FN_KEYOUT1, NULL);
515 gpio_request(GPIO_FN_KEYOUT2, NULL); 514 gpio_request(GPIO_FN_KEYOUT2, NULL);
516 gpio_request(GPIO_FN_KEYOUT3, NULL); 515 gpio_request(GPIO_FN_KEYOUT3, NULL);
517 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); 516 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
518 gpio_request(GPIO_FN_KEYIN1, NULL); 517 gpio_request(GPIO_FN_KEYIN1, NULL);
519 gpio_request(GPIO_FN_KEYIN2, NULL); 518 gpio_request(GPIO_FN_KEYIN2, NULL);
520 gpio_request(GPIO_FN_KEYIN3, NULL); 519 gpio_request(GPIO_FN_KEYIN3, NULL);
521 gpio_request(GPIO_FN_KEYIN4, NULL); 520 gpio_request(GPIO_FN_KEYIN4, NULL);
522 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); 521 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
523 522
524 /* NAND Flash */ 523 /* NAND Flash */
525 gpio_request(GPIO_FN_CS6A_CE2B, NULL); 524 gpio_request(GPIO_FN_CS6A_CE2B, NULL);
526 __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR); 525 __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
527 gpio_request(GPIO_PTA1, NULL); 526 gpio_request(GPIO_PTA1, NULL);
528 gpio_direction_input(GPIO_PTA1); 527 gpio_direction_input(GPIO_PTA1);
529 528
530 /* SDHI */ 529 /* SDHI */
531 gpio_request(GPIO_FN_SDHICD, NULL); 530 gpio_request(GPIO_FN_SDHICD, NULL);
532 gpio_request(GPIO_FN_SDHIWP, NULL); 531 gpio_request(GPIO_FN_SDHIWP, NULL);
533 gpio_request(GPIO_FN_SDHID3, NULL); 532 gpio_request(GPIO_FN_SDHID3, NULL);
534 gpio_request(GPIO_FN_SDHID2, NULL); 533 gpio_request(GPIO_FN_SDHID2, NULL);
535 gpio_request(GPIO_FN_SDHID1, NULL); 534 gpio_request(GPIO_FN_SDHID1, NULL);
536 gpio_request(GPIO_FN_SDHID0, NULL); 535 gpio_request(GPIO_FN_SDHID0, NULL);
537 gpio_request(GPIO_FN_SDHICMD, NULL); 536 gpio_request(GPIO_FN_SDHICMD, NULL);
538 gpio_request(GPIO_FN_SDHICLK, NULL); 537 gpio_request(GPIO_FN_SDHICLK, NULL);
539 538
540 /* Touch Panel */ 539 /* Touch Panel */
541 gpio_request(GPIO_FN_IRQ6, NULL); 540 gpio_request(GPIO_FN_IRQ6, NULL);
542 541
543 /* LCD Panel */ 542 /* LCD Panel */
544 #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */ 543 #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
545 gpio_request(GPIO_FN_LCDD17, NULL); 544 gpio_request(GPIO_FN_LCDD17, NULL);
546 gpio_request(GPIO_FN_LCDD16, NULL); 545 gpio_request(GPIO_FN_LCDD16, NULL);
547 gpio_request(GPIO_FN_LCDD15, NULL); 546 gpio_request(GPIO_FN_LCDD15, NULL);
548 gpio_request(GPIO_FN_LCDD14, NULL); 547 gpio_request(GPIO_FN_LCDD14, NULL);
549 gpio_request(GPIO_FN_LCDD13, NULL); 548 gpio_request(GPIO_FN_LCDD13, NULL);
550 gpio_request(GPIO_FN_LCDD12, NULL); 549 gpio_request(GPIO_FN_LCDD12, NULL);
551 gpio_request(GPIO_FN_LCDD11, NULL); 550 gpio_request(GPIO_FN_LCDD11, NULL);
552 gpio_request(GPIO_FN_LCDD10, NULL); 551 gpio_request(GPIO_FN_LCDD10, NULL);
553 gpio_request(GPIO_FN_LCDD8, NULL); 552 gpio_request(GPIO_FN_LCDD8, NULL);
554 gpio_request(GPIO_FN_LCDD7, NULL); 553 gpio_request(GPIO_FN_LCDD7, NULL);
555 gpio_request(GPIO_FN_LCDD6, NULL); 554 gpio_request(GPIO_FN_LCDD6, NULL);
556 gpio_request(GPIO_FN_LCDD5, NULL); 555 gpio_request(GPIO_FN_LCDD5, NULL);
557 gpio_request(GPIO_FN_LCDD4, NULL); 556 gpio_request(GPIO_FN_LCDD4, NULL);
558 gpio_request(GPIO_FN_LCDD3, NULL); 557 gpio_request(GPIO_FN_LCDD3, NULL);
559 gpio_request(GPIO_FN_LCDD2, NULL); 558 gpio_request(GPIO_FN_LCDD2, NULL);
560 gpio_request(GPIO_FN_LCDD1, NULL); 559 gpio_request(GPIO_FN_LCDD1, NULL);
561 gpio_request(GPIO_FN_LCDRS, NULL); 560 gpio_request(GPIO_FN_LCDRS, NULL);
562 gpio_request(GPIO_FN_LCDCS, NULL); 561 gpio_request(GPIO_FN_LCDCS, NULL);
563 gpio_request(GPIO_FN_LCDRD, NULL); 562 gpio_request(GPIO_FN_LCDRD, NULL);
564 gpio_request(GPIO_FN_LCDWR, NULL); 563 gpio_request(GPIO_FN_LCDWR, NULL);
565 gpio_request(GPIO_PTH2, NULL); /* LCD_DON */ 564 gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
566 gpio_direction_output(GPIO_PTH2, 1); 565 gpio_direction_output(GPIO_PTH2, 1);
567 #endif 566 #endif
568 #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */ 567 #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
569 gpio_request(GPIO_FN_LCDD15, NULL); 568 gpio_request(GPIO_FN_LCDD15, NULL);
570 gpio_request(GPIO_FN_LCDD14, NULL); 569 gpio_request(GPIO_FN_LCDD14, NULL);
571 gpio_request(GPIO_FN_LCDD13, NULL); 570 gpio_request(GPIO_FN_LCDD13, NULL);
572 gpio_request(GPIO_FN_LCDD12, NULL); 571 gpio_request(GPIO_FN_LCDD12, NULL);
573 gpio_request(GPIO_FN_LCDD11, NULL); 572 gpio_request(GPIO_FN_LCDD11, NULL);
574 gpio_request(GPIO_FN_LCDD10, NULL); 573 gpio_request(GPIO_FN_LCDD10, NULL);
575 gpio_request(GPIO_FN_LCDD9, NULL); 574 gpio_request(GPIO_FN_LCDD9, NULL);
576 gpio_request(GPIO_FN_LCDD8, NULL); 575 gpio_request(GPIO_FN_LCDD8, NULL);
577 gpio_request(GPIO_FN_LCDD7, NULL); 576 gpio_request(GPIO_FN_LCDD7, NULL);
578 gpio_request(GPIO_FN_LCDD6, NULL); 577 gpio_request(GPIO_FN_LCDD6, NULL);
579 gpio_request(GPIO_FN_LCDD5, NULL); 578 gpio_request(GPIO_FN_LCDD5, NULL);
580 gpio_request(GPIO_FN_LCDD4, NULL); 579 gpio_request(GPIO_FN_LCDD4, NULL);
581 gpio_request(GPIO_FN_LCDD3, NULL); 580 gpio_request(GPIO_FN_LCDD3, NULL);
582 gpio_request(GPIO_FN_LCDD2, NULL); 581 gpio_request(GPIO_FN_LCDD2, NULL);
583 gpio_request(GPIO_FN_LCDD1, NULL); 582 gpio_request(GPIO_FN_LCDD1, NULL);
584 gpio_request(GPIO_FN_LCDD0, NULL); 583 gpio_request(GPIO_FN_LCDD0, NULL);
585 gpio_request(GPIO_FN_LCDLCLK, NULL); 584 gpio_request(GPIO_FN_LCDLCLK, NULL);
586 gpio_request(GPIO_FN_LCDDCK, NULL); 585 gpio_request(GPIO_FN_LCDDCK, NULL);
587 gpio_request(GPIO_FN_LCDVEPWC, NULL); 586 gpio_request(GPIO_FN_LCDVEPWC, NULL);
588 gpio_request(GPIO_FN_LCDVCPWC, NULL); 587 gpio_request(GPIO_FN_LCDVCPWC, NULL);
589 gpio_request(GPIO_FN_LCDVSYN, NULL); 588 gpio_request(GPIO_FN_LCDVSYN, NULL);
590 gpio_request(GPIO_FN_LCDHSYN, NULL); 589 gpio_request(GPIO_FN_LCDHSYN, NULL);
591 gpio_request(GPIO_FN_LCDDISP, NULL); 590 gpio_request(GPIO_FN_LCDDISP, NULL);
592 gpio_request(GPIO_FN_LCDDON, NULL); 591 gpio_request(GPIO_FN_LCDDON, NULL);
593 #endif 592 #endif
594 593
595 /* CEU */ 594 /* CEU */
596 gpio_request(GPIO_FN_VIO_CLK2, NULL); 595 gpio_request(GPIO_FN_VIO_CLK2, NULL);
597 gpio_request(GPIO_FN_VIO_VD2, NULL); 596 gpio_request(GPIO_FN_VIO_VD2, NULL);
598 gpio_request(GPIO_FN_VIO_HD2, NULL); 597 gpio_request(GPIO_FN_VIO_HD2, NULL);
599 gpio_request(GPIO_FN_VIO_FLD, NULL); 598 gpio_request(GPIO_FN_VIO_FLD, NULL);
600 gpio_request(GPIO_FN_VIO_CKO, NULL); 599 gpio_request(GPIO_FN_VIO_CKO, NULL);
601 gpio_request(GPIO_FN_VIO_D15, NULL); 600 gpio_request(GPIO_FN_VIO_D15, NULL);
602 gpio_request(GPIO_FN_VIO_D14, NULL); 601 gpio_request(GPIO_FN_VIO_D14, NULL);
603 gpio_request(GPIO_FN_VIO_D13, NULL); 602 gpio_request(GPIO_FN_VIO_D13, NULL);
604 gpio_request(GPIO_FN_VIO_D12, NULL); 603 gpio_request(GPIO_FN_VIO_D12, NULL);
605 gpio_request(GPIO_FN_VIO_D11, NULL); 604 gpio_request(GPIO_FN_VIO_D11, NULL);
606 gpio_request(GPIO_FN_VIO_D10, NULL); 605 gpio_request(GPIO_FN_VIO_D10, NULL);
607 gpio_request(GPIO_FN_VIO_D9, NULL); 606 gpio_request(GPIO_FN_VIO_D9, NULL);
608 gpio_request(GPIO_FN_VIO_D8, NULL); 607 gpio_request(GPIO_FN_VIO_D8, NULL);
609 608
610 gpio_request(GPIO_PTT3, NULL); /* VIO_RST */ 609 gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
611 gpio_direction_output(GPIO_PTT3, 0); 610 gpio_direction_output(GPIO_PTT3, 0);
612 gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */ 611 gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
613 gpio_direction_output(GPIO_PTT2, 1); 612 gpio_direction_output(GPIO_PTT2, 1);
614 gpio_request(GPIO_PTT0, NULL); /* CAM_EN */ 613 gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
615 #ifdef CONFIG_SH_MIGOR_RTA_WVGA 614 #ifdef CONFIG_SH_MIGOR_RTA_WVGA
616 gpio_direction_output(GPIO_PTT0, 0); 615 gpio_direction_output(GPIO_PTT0, 0);
617 #else 616 #else
618 gpio_direction_output(GPIO_PTT0, 1); 617 gpio_direction_output(GPIO_PTT0, 1);
619 #endif 618 #endif
620 __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */ 619 __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
621 620
622 platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20); 621 platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
623 622
624 /* SIU: Port B */ 623 /* SIU: Port B */
625 gpio_request(GPIO_FN_SIUBOLR, NULL); 624 gpio_request(GPIO_FN_SIUBOLR, NULL);
626 gpio_request(GPIO_FN_SIUBOBT, NULL); 625 gpio_request(GPIO_FN_SIUBOBT, NULL);
627 gpio_request(GPIO_FN_SIUBISLD, NULL); 626 gpio_request(GPIO_FN_SIUBISLD, NULL);
628 gpio_request(GPIO_FN_SIUBOSLD, NULL); 627 gpio_request(GPIO_FN_SIUBOSLD, NULL);
629 gpio_request(GPIO_FN_SIUMCKB, NULL); 628 gpio_request(GPIO_FN_SIUMCKB, NULL);
630 629
631 /* 630 /*
632 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to 631 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
633 * output. Need only SIUB, set to output for master mode (table 34.2) 632 * output. Need only SIUB, set to output for master mode (table 34.2)
634 */ 633 */
635 __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA); 634 __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
636 635
637 i2c_register_board_info(0, migor_i2c_devices, 636 i2c_register_board_info(0, migor_i2c_devices,
638 ARRAY_SIZE(migor_i2c_devices)); 637 ARRAY_SIZE(migor_i2c_devices));
639 638
640 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices)); 639 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
641 } 640 }
642 arch_initcall(migor_devices_setup); 641 arch_initcall(migor_devices_setup);
643 642
644 /* Return the board specific boot mode pin configuration */ 643 /* Return the board specific boot mode pin configuration */
645 static int migor_mode_pins(void) 644 static int migor_mode_pins(void)
646 { 645 {
647 /* MD0=1, MD1=1, MD2=0: Clock Mode 3 646 /* MD0=1, MD1=1, MD2=0: Clock Mode 3
648 * MD3=0: 16-bit Area0 Bus Width 647 * MD3=0: 16-bit Area0 Bus Width
649 * MD5=1: Little Endian 648 * MD5=1: Little Endian
650 * TSTMD=1, MD8=0: Test Mode Disabled 649 * TSTMD=1, MD8=0: Test Mode Disabled
651 */ 650 */
652 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5; 651 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
653 } 652 }
654 653
655 /* 654 /*
656 * The Machine Vector 655 * The Machine Vector
657 */ 656 */
658 static struct sh_machine_vector mv_migor __initmv = { 657 static struct sh_machine_vector mv_migor __initmv = {
659 .mv_name = "Migo-R", 658 .mv_name = "Migo-R",
660 .mv_mode_pins = migor_mode_pins, 659 .mv_mode_pins = migor_mode_pins,
661 }; 660 };
662 661