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Commit cf48fb6a2bf2e59990e1438d0dedc706df911996

Authored by Bjorn Helgaas
Committed by Jesse Barnes
1 parent 63ab387ca0
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

PCI: fix bridge I/O window bus-to-resource conversion 

In 5bfa14ed9f3c, I forgot to initialize res2.flags before calling
pcibios_bus_to_resource(), which depends on the resource type to locate the
correct aperture.  This bug won't hurt x86, which currently never has an
offset between bus and CPU addresses, but will affect other architectures.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Showing 1 changed file with 1 additions and 0 deletions Inline Diff

1 /* 1 /*
2 * probe.c - PCI detection and setup code 2 * probe.c - PCI detection and setup code
3 */ 3 */
4 4
5 #include <linux/kernel.h> 5 #include <linux/kernel.h>
6 #include <linux/delay.h> 6 #include <linux/delay.h>
7 #include <linux/init.h> 7 #include <linux/init.h>
8 #include <linux/pci.h> 8 #include <linux/pci.h>
9 #include <linux/slab.h> 9 #include <linux/slab.h>
10 #include <linux/module.h> 10 #include <linux/module.h>
11 #include <linux/cpumask.h> 11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h> 12 #include <linux/pci-aspm.h>
13 #include "pci.h" 13 #include "pci.h"
14 14
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3 16 #define CARDBUS_RESERVE_BUSNR 3
17 17
18 static LIST_HEAD(pci_host_bridges); 18 static LIST_HEAD(pci_host_bridges);
19 19
20 /* Ugh. Need to stop exporting this to modules. */ 20 /* Ugh. Need to stop exporting this to modules. */
21 LIST_HEAD(pci_root_buses); 21 LIST_HEAD(pci_root_buses);
22 EXPORT_SYMBOL(pci_root_buses); 22 EXPORT_SYMBOL(pci_root_buses);
23 23
24 24
25 static int find_anything(struct device *dev, void *data) 25 static int find_anything(struct device *dev, void *data)
26 { 26 {
27 return 1; 27 return 1;
28 } 28 }
29 29
30 /* 30 /*
31 * Some device drivers need know if pci is initiated. 31 * Some device drivers need know if pci is initiated.
32 * Basically, we think pci is not initiated when there 32 * Basically, we think pci is not initiated when there
33 * is no device to be found on the pci_bus_type. 33 * is no device to be found on the pci_bus_type.
34 */ 34 */
35 int no_pci_devices(void) 35 int no_pci_devices(void)
36 { 36 {
37 struct device *dev; 37 struct device *dev;
38 int no_devices; 38 int no_devices;
39 39
40 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); 40 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
41 no_devices = (dev == NULL); 41 no_devices = (dev == NULL);
42 put_device(dev); 42 put_device(dev);
43 return no_devices; 43 return no_devices;
44 } 44 }
45 EXPORT_SYMBOL(no_pci_devices); 45 EXPORT_SYMBOL(no_pci_devices);
46 46
47 static struct pci_host_bridge *pci_host_bridge(struct pci_dev *dev) 47 static struct pci_host_bridge *pci_host_bridge(struct pci_dev *dev)
48 { 48 {
49 struct pci_bus *bus; 49 struct pci_bus *bus;
50 struct pci_host_bridge *bridge; 50 struct pci_host_bridge *bridge;
51 51
52 bus = dev->bus; 52 bus = dev->bus;
53 while (bus->parent) 53 while (bus->parent)
54 bus = bus->parent; 54 bus = bus->parent;
55 55
56 list_for_each_entry(bridge, &pci_host_bridges, list) { 56 list_for_each_entry(bridge, &pci_host_bridges, list) {
57 if (bridge->bus == bus) 57 if (bridge->bus == bus)
58 return bridge; 58 return bridge;
59 } 59 }
60 60
61 return NULL; 61 return NULL;
62 } 62 }
63 63
64 static bool resource_contains(struct resource *res1, struct resource *res2) 64 static bool resource_contains(struct resource *res1, struct resource *res2)
65 { 65 {
66 return res1->start <= res2->start && res1->end >= res2->end; 66 return res1->start <= res2->start && res1->end >= res2->end;
67 } 67 }
68 68
69 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 69 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
70 struct resource *res) 70 struct resource *res)
71 { 71 {
72 struct pci_host_bridge *bridge = pci_host_bridge(dev); 72 struct pci_host_bridge *bridge = pci_host_bridge(dev);
73 struct pci_host_bridge_window *window; 73 struct pci_host_bridge_window *window;
74 resource_size_t offset = 0; 74 resource_size_t offset = 0;
75 75
76 list_for_each_entry(window, &bridge->windows, list) { 76 list_for_each_entry(window, &bridge->windows, list) {
77 if (resource_type(res) != resource_type(window->res)) 77 if (resource_type(res) != resource_type(window->res))
78 continue; 78 continue;
79 79
80 if (resource_contains(window->res, res)) { 80 if (resource_contains(window->res, res)) {
81 offset = window->offset; 81 offset = window->offset;
82 break; 82 break;
83 } 83 }
84 } 84 }
85 85
86 region->start = res->start - offset; 86 region->start = res->start - offset;
87 region->end = res->end - offset; 87 region->end = res->end - offset;
88 } 88 }
89 EXPORT_SYMBOL(pcibios_resource_to_bus); 89 EXPORT_SYMBOL(pcibios_resource_to_bus);
90 90
91 static bool region_contains(struct pci_bus_region *region1, 91 static bool region_contains(struct pci_bus_region *region1,
92 struct pci_bus_region *region2) 92 struct pci_bus_region *region2)
93 { 93 {
94 return region1->start <= region2->start && region1->end >= region2->end; 94 return region1->start <= region2->start && region1->end >= region2->end;
95 } 95 }
96 96
97 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 97 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
98 struct pci_bus_region *region) 98 struct pci_bus_region *region)
99 { 99 {
100 struct pci_host_bridge *bridge = pci_host_bridge(dev); 100 struct pci_host_bridge *bridge = pci_host_bridge(dev);
101 struct pci_host_bridge_window *window; 101 struct pci_host_bridge_window *window;
102 struct pci_bus_region bus_region; 102 struct pci_bus_region bus_region;
103 resource_size_t offset = 0; 103 resource_size_t offset = 0;
104 104
105 list_for_each_entry(window, &bridge->windows, list) { 105 list_for_each_entry(window, &bridge->windows, list) {
106 if (resource_type(res) != resource_type(window->res)) 106 if (resource_type(res) != resource_type(window->res))
107 continue; 107 continue;
108 108
109 bus_region.start = window->res->start - window->offset; 109 bus_region.start = window->res->start - window->offset;
110 bus_region.end = window->res->end - window->offset; 110 bus_region.end = window->res->end - window->offset;
111 111
112 if (region_contains(&bus_region, region)) { 112 if (region_contains(&bus_region, region)) {
113 offset = window->offset; 113 offset = window->offset;
114 break; 114 break;
115 } 115 }
116 } 116 }
117 117
118 res->start = region->start + offset; 118 res->start = region->start + offset;
119 res->end = region->end + offset; 119 res->end = region->end + offset;
120 } 120 }
121 EXPORT_SYMBOL(pcibios_bus_to_resource); 121 EXPORT_SYMBOL(pcibios_bus_to_resource);
122 122
123 /* 123 /*
124 * PCI Bus Class 124 * PCI Bus Class
125 */ 125 */
126 static void release_pcibus_dev(struct device *dev) 126 static void release_pcibus_dev(struct device *dev)
127 { 127 {
128 struct pci_bus *pci_bus = to_pci_bus(dev); 128 struct pci_bus *pci_bus = to_pci_bus(dev);
129 129
130 if (pci_bus->bridge) 130 if (pci_bus->bridge)
131 put_device(pci_bus->bridge); 131 put_device(pci_bus->bridge);
132 pci_bus_remove_resources(pci_bus); 132 pci_bus_remove_resources(pci_bus);
133 pci_release_bus_of_node(pci_bus); 133 pci_release_bus_of_node(pci_bus);
134 kfree(pci_bus); 134 kfree(pci_bus);
135 } 135 }
136 136
137 static struct class pcibus_class = { 137 static struct class pcibus_class = {
138 .name = "pci_bus", 138 .name = "pci_bus",
139 .dev_release = &release_pcibus_dev, 139 .dev_release = &release_pcibus_dev,
140 .dev_attrs = pcibus_dev_attrs, 140 .dev_attrs = pcibus_dev_attrs,
141 }; 141 };
142 142
143 static int __init pcibus_class_init(void) 143 static int __init pcibus_class_init(void)
144 { 144 {
145 return class_register(&pcibus_class); 145 return class_register(&pcibus_class);
146 } 146 }
147 postcore_initcall(pcibus_class_init); 147 postcore_initcall(pcibus_class_init);
148 148
149 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 149 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
150 { 150 {
151 u64 size = mask & maxbase; /* Find the significant bits */ 151 u64 size = mask & maxbase; /* Find the significant bits */
152 if (!size) 152 if (!size)
153 return 0; 153 return 0;
154 154
155 /* Get the lowest of them to find the decode size, and 155 /* Get the lowest of them to find the decode size, and
156 from that the extent. */ 156 from that the extent. */
157 size = (size & ~(size-1)) - 1; 157 size = (size & ~(size-1)) - 1;
158 158
159 /* base == maxbase can be valid only if the BAR has 159 /* base == maxbase can be valid only if the BAR has
160 already been programmed with all 1s. */ 160 already been programmed with all 1s. */
161 if (base == maxbase && ((base | size) & mask) != mask) 161 if (base == maxbase && ((base | size) & mask) != mask)
162 return 0; 162 return 0;
163 163
164 return size; 164 return size;
165 } 165 }
166 166
167 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 167 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
168 { 168 {
169 u32 mem_type; 169 u32 mem_type;
170 unsigned long flags; 170 unsigned long flags;
171 171
172 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 172 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
173 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 173 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
174 flags |= IORESOURCE_IO; 174 flags |= IORESOURCE_IO;
175 return flags; 175 return flags;
176 } 176 }
177 177
178 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 178 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
179 flags |= IORESOURCE_MEM; 179 flags |= IORESOURCE_MEM;
180 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 180 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
181 flags |= IORESOURCE_PREFETCH; 181 flags |= IORESOURCE_PREFETCH;
182 182
183 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 183 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
184 switch (mem_type) { 184 switch (mem_type) {
185 case PCI_BASE_ADDRESS_MEM_TYPE_32: 185 case PCI_BASE_ADDRESS_MEM_TYPE_32:
186 break; 186 break;
187 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 187 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
188 dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n"); 188 dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
189 break; 189 break;
190 case PCI_BASE_ADDRESS_MEM_TYPE_64: 190 case PCI_BASE_ADDRESS_MEM_TYPE_64:
191 flags |= IORESOURCE_MEM_64; 191 flags |= IORESOURCE_MEM_64;
192 break; 192 break;
193 default: 193 default:
194 dev_warn(&dev->dev, 194 dev_warn(&dev->dev,
195 "mem unknown type %x treated as 32-bit BAR\n", 195 "mem unknown type %x treated as 32-bit BAR\n",
196 mem_type); 196 mem_type);
197 break; 197 break;
198 } 198 }
199 return flags; 199 return flags;
200 } 200 }
201 201
202 /** 202 /**
203 * pci_read_base - read a PCI BAR 203 * pci_read_base - read a PCI BAR
204 * @dev: the PCI device 204 * @dev: the PCI device
205 * @type: type of the BAR 205 * @type: type of the BAR
206 * @res: resource buffer to be filled in 206 * @res: resource buffer to be filled in
207 * @pos: BAR position in the config space 207 * @pos: BAR position in the config space
208 * 208 *
209 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 209 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
210 */ 210 */
211 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 211 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
212 struct resource *res, unsigned int pos) 212 struct resource *res, unsigned int pos)
213 { 213 {
214 u32 l, sz, mask; 214 u32 l, sz, mask;
215 u16 orig_cmd; 215 u16 orig_cmd;
216 struct pci_bus_region region; 216 struct pci_bus_region region;
217 217
218 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 218 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
219 219
220 if (!dev->mmio_always_on) { 220 if (!dev->mmio_always_on) {
221 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 221 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
222 pci_write_config_word(dev, PCI_COMMAND, 222 pci_write_config_word(dev, PCI_COMMAND,
223 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); 223 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
224 } 224 }
225 225
226 res->name = pci_name(dev); 226 res->name = pci_name(dev);
227 227
228 pci_read_config_dword(dev, pos, &l); 228 pci_read_config_dword(dev, pos, &l);
229 pci_write_config_dword(dev, pos, l | mask); 229 pci_write_config_dword(dev, pos, l | mask);
230 pci_read_config_dword(dev, pos, &sz); 230 pci_read_config_dword(dev, pos, &sz);
231 pci_write_config_dword(dev, pos, l); 231 pci_write_config_dword(dev, pos, l);
232 232
233 if (!dev->mmio_always_on) 233 if (!dev->mmio_always_on)
234 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 234 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
235 235
236 /* 236 /*
237 * All bits set in sz means the device isn't working properly. 237 * All bits set in sz means the device isn't working properly.
238 * If the BAR isn't implemented, all bits must be 0. If it's a 238 * If the BAR isn't implemented, all bits must be 0. If it's a
239 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 239 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
240 * 1 must be clear. 240 * 1 must be clear.
241 */ 241 */
242 if (!sz || sz == 0xffffffff) 242 if (!sz || sz == 0xffffffff)
243 goto fail; 243 goto fail;
244 244
245 /* 245 /*
246 * I don't know how l can have all bits set. Copied from old code. 246 * I don't know how l can have all bits set. Copied from old code.
247 * Maybe it fixes a bug on some ancient platform. 247 * Maybe it fixes a bug on some ancient platform.
248 */ 248 */
249 if (l == 0xffffffff) 249 if (l == 0xffffffff)
250 l = 0; 250 l = 0;
251 251
252 if (type == pci_bar_unknown) { 252 if (type == pci_bar_unknown) {
253 res->flags = decode_bar(dev, l); 253 res->flags = decode_bar(dev, l);
254 res->flags |= IORESOURCE_SIZEALIGN; 254 res->flags |= IORESOURCE_SIZEALIGN;
255 if (res->flags & IORESOURCE_IO) { 255 if (res->flags & IORESOURCE_IO) {
256 l &= PCI_BASE_ADDRESS_IO_MASK; 256 l &= PCI_BASE_ADDRESS_IO_MASK;
257 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT; 257 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
258 } else { 258 } else {
259 l &= PCI_BASE_ADDRESS_MEM_MASK; 259 l &= PCI_BASE_ADDRESS_MEM_MASK;
260 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 260 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
261 } 261 }
262 } else { 262 } else {
263 res->flags |= (l & IORESOURCE_ROM_ENABLE); 263 res->flags |= (l & IORESOURCE_ROM_ENABLE);
264 l &= PCI_ROM_ADDRESS_MASK; 264 l &= PCI_ROM_ADDRESS_MASK;
265 mask = (u32)PCI_ROM_ADDRESS_MASK; 265 mask = (u32)PCI_ROM_ADDRESS_MASK;
266 } 266 }
267 267
268 if (res->flags & IORESOURCE_MEM_64) { 268 if (res->flags & IORESOURCE_MEM_64) {
269 u64 l64 = l; 269 u64 l64 = l;
270 u64 sz64 = sz; 270 u64 sz64 = sz;
271 u64 mask64 = mask | (u64)~0 << 32; 271 u64 mask64 = mask | (u64)~0 << 32;
272 272
273 pci_read_config_dword(dev, pos + 4, &l); 273 pci_read_config_dword(dev, pos + 4, &l);
274 pci_write_config_dword(dev, pos + 4, ~0); 274 pci_write_config_dword(dev, pos + 4, ~0);
275 pci_read_config_dword(dev, pos + 4, &sz); 275 pci_read_config_dword(dev, pos + 4, &sz);
276 pci_write_config_dword(dev, pos + 4, l); 276 pci_write_config_dword(dev, pos + 4, l);
277 277
278 l64 |= ((u64)l << 32); 278 l64 |= ((u64)l << 32);
279 sz64 |= ((u64)sz << 32); 279 sz64 |= ((u64)sz << 32);
280 280
281 sz64 = pci_size(l64, sz64, mask64); 281 sz64 = pci_size(l64, sz64, mask64);
282 282
283 if (!sz64) 283 if (!sz64)
284 goto fail; 284 goto fail;
285 285
286 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { 286 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
287 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", 287 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
288 pos); 288 pos);
289 goto fail; 289 goto fail;
290 } 290 }
291 291
292 if ((sizeof(resource_size_t) < 8) && l) { 292 if ((sizeof(resource_size_t) < 8) && l) {
293 /* Address above 32-bit boundary; disable the BAR */ 293 /* Address above 32-bit boundary; disable the BAR */
294 pci_write_config_dword(dev, pos, 0); 294 pci_write_config_dword(dev, pos, 0);
295 pci_write_config_dword(dev, pos + 4, 0); 295 pci_write_config_dword(dev, pos + 4, 0);
296 region.start = 0; 296 region.start = 0;
297 region.end = sz64; 297 region.end = sz64;
298 pcibios_bus_to_resource(dev, res, &region); 298 pcibios_bus_to_resource(dev, res, &region);
299 } else { 299 } else {
300 region.start = l64; 300 region.start = l64;
301 region.end = l64 + sz64; 301 region.end = l64 + sz64;
302 pcibios_bus_to_resource(dev, res, &region); 302 pcibios_bus_to_resource(dev, res, &region);
303 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", 303 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
304 pos, res); 304 pos, res);
305 } 305 }
306 } else { 306 } else {
307 sz = pci_size(l, sz, mask); 307 sz = pci_size(l, sz, mask);
308 308
309 if (!sz) 309 if (!sz)
310 goto fail; 310 goto fail;
311 311
312 region.start = l; 312 region.start = l;
313 region.end = l + sz; 313 region.end = l + sz;
314 pcibios_bus_to_resource(dev, res, &region); 314 pcibios_bus_to_resource(dev, res, &region);
315 315
316 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); 316 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
317 } 317 }
318 318
319 out: 319 out:
320 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 320 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
321 fail: 321 fail:
322 res->flags = 0; 322 res->flags = 0;
323 goto out; 323 goto out;
324 } 324 }
325 325
326 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 326 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
327 { 327 {
328 unsigned int pos, reg; 328 unsigned int pos, reg;
329 329
330 for (pos = 0; pos < howmany; pos++) { 330 for (pos = 0; pos < howmany; pos++) {
331 struct resource *res = &dev->resource[pos]; 331 struct resource *res = &dev->resource[pos];
332 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 332 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
333 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 333 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
334 } 334 }
335 335
336 if (rom) { 336 if (rom) {
337 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 337 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
338 dev->rom_base_reg = rom; 338 dev->rom_base_reg = rom;
339 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 339 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
340 IORESOURCE_READONLY | IORESOURCE_CACHEABLE | 340 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
341 IORESOURCE_SIZEALIGN; 341 IORESOURCE_SIZEALIGN;
342 __pci_read_base(dev, pci_bar_mem32, res, rom); 342 __pci_read_base(dev, pci_bar_mem32, res, rom);
343 } 343 }
344 } 344 }
345 345
346 static void __devinit pci_read_bridge_io(struct pci_bus *child) 346 static void __devinit pci_read_bridge_io(struct pci_bus *child)
347 { 347 {
348 struct pci_dev *dev = child->self; 348 struct pci_dev *dev = child->self;
349 u8 io_base_lo, io_limit_lo; 349 u8 io_base_lo, io_limit_lo;
350 unsigned long base, limit; 350 unsigned long base, limit;
351 struct pci_bus_region region; 351 struct pci_bus_region region;
352 struct resource *res, res2; 352 struct resource *res, res2;
353 353
354 res = child->resource[0]; 354 res = child->resource[0];
355 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 355 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
356 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 356 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
357 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; 357 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
358 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; 358 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
359 359
360 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 360 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
361 u16 io_base_hi, io_limit_hi; 361 u16 io_base_hi, io_limit_hi;
362 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 362 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
363 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 363 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
364 base |= (io_base_hi << 16); 364 base |= (io_base_hi << 16);
365 limit |= (io_limit_hi << 16); 365 limit |= (io_limit_hi << 16);
366 } 366 }
367 367
368 if (base && base <= limit) { 368 if (base && base <= limit) {
369 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 369 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
370 res2.flags = res->flags;
370 region.start = base; 371 region.start = base;
371 region.end = limit + 0xfff; 372 region.end = limit + 0xfff;
372 pcibios_bus_to_resource(dev, &res2, &region); 373 pcibios_bus_to_resource(dev, &res2, &region);
373 if (!res->start) 374 if (!res->start)
374 res->start = res2.start; 375 res->start = res2.start;
375 if (!res->end) 376 if (!res->end)
376 res->end = res2.end; 377 res->end = res2.end;
377 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 378 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
378 } 379 }
379 } 380 }
380 381
381 static void __devinit pci_read_bridge_mmio(struct pci_bus *child) 382 static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
382 { 383 {
383 struct pci_dev *dev = child->self; 384 struct pci_dev *dev = child->self;
384 u16 mem_base_lo, mem_limit_lo; 385 u16 mem_base_lo, mem_limit_lo;
385 unsigned long base, limit; 386 unsigned long base, limit;
386 struct pci_bus_region region; 387 struct pci_bus_region region;
387 struct resource *res; 388 struct resource *res;
388 389
389 res = child->resource[1]; 390 res = child->resource[1];
390 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 391 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
391 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 392 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
392 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 393 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
393 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 394 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
394 if (base && base <= limit) { 395 if (base && base <= limit) {
395 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 396 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
396 region.start = base; 397 region.start = base;
397 region.end = limit + 0xfffff; 398 region.end = limit + 0xfffff;
398 pcibios_bus_to_resource(dev, res, &region); 399 pcibios_bus_to_resource(dev, res, &region);
399 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 400 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
400 } 401 }
401 } 402 }
402 403
403 static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) 404 static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
404 { 405 {
405 struct pci_dev *dev = child->self; 406 struct pci_dev *dev = child->self;
406 u16 mem_base_lo, mem_limit_lo; 407 u16 mem_base_lo, mem_limit_lo;
407 unsigned long base, limit; 408 unsigned long base, limit;
408 struct pci_bus_region region; 409 struct pci_bus_region region;
409 struct resource *res; 410 struct resource *res;
410 411
411 res = child->resource[2]; 412 res = child->resource[2];
412 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 413 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
413 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 414 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
414 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 415 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
415 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 416 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
416 417
417 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 418 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
418 u32 mem_base_hi, mem_limit_hi; 419 u32 mem_base_hi, mem_limit_hi;
419 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 420 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
420 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 421 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
421 422
422 /* 423 /*
423 * Some bridges set the base > limit by default, and some 424 * Some bridges set the base > limit by default, and some
424 * (broken) BIOSes do not initialize them. If we find 425 * (broken) BIOSes do not initialize them. If we find
425 * this, just assume they are not being used. 426 * this, just assume they are not being used.
426 */ 427 */
427 if (mem_base_hi <= mem_limit_hi) { 428 if (mem_base_hi <= mem_limit_hi) {
428 #if BITS_PER_LONG == 64 429 #if BITS_PER_LONG == 64
429 base |= ((long) mem_base_hi) << 32; 430 base |= ((long) mem_base_hi) << 32;
430 limit |= ((long) mem_limit_hi) << 32; 431 limit |= ((long) mem_limit_hi) << 32;
431 #else 432 #else
432 if (mem_base_hi || mem_limit_hi) { 433 if (mem_base_hi || mem_limit_hi) {
433 dev_err(&dev->dev, "can't handle 64-bit " 434 dev_err(&dev->dev, "can't handle 64-bit "
434 "address space for bridge\n"); 435 "address space for bridge\n");
435 return; 436 return;
436 } 437 }
437 #endif 438 #endif
438 } 439 }
439 } 440 }
440 if (base && base <= limit) { 441 if (base && base <= limit) {
441 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 442 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
442 IORESOURCE_MEM | IORESOURCE_PREFETCH; 443 IORESOURCE_MEM | IORESOURCE_PREFETCH;
443 if (res->flags & PCI_PREF_RANGE_TYPE_64) 444 if (res->flags & PCI_PREF_RANGE_TYPE_64)
444 res->flags |= IORESOURCE_MEM_64; 445 res->flags |= IORESOURCE_MEM_64;
445 region.start = base; 446 region.start = base;
446 region.end = limit + 0xfffff; 447 region.end = limit + 0xfffff;
447 pcibios_bus_to_resource(dev, res, &region); 448 pcibios_bus_to_resource(dev, res, &region);
448 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 449 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
449 } 450 }
450 } 451 }
451 452
452 void __devinit pci_read_bridge_bases(struct pci_bus *child) 453 void __devinit pci_read_bridge_bases(struct pci_bus *child)
453 { 454 {
454 struct pci_dev *dev = child->self; 455 struct pci_dev *dev = child->self;
455 struct resource *res; 456 struct resource *res;
456 int i; 457 int i;
457 458
458 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 459 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
459 return; 460 return;
460 461
461 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n", 462 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
462 child->secondary, child->subordinate, 463 child->secondary, child->subordinate,
463 dev->transparent ? " (subtractive decode)" : ""); 464 dev->transparent ? " (subtractive decode)" : "");
464 465
465 pci_bus_remove_resources(child); 466 pci_bus_remove_resources(child);
466 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 467 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
467 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 468 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
468 469
469 pci_read_bridge_io(child); 470 pci_read_bridge_io(child);
470 pci_read_bridge_mmio(child); 471 pci_read_bridge_mmio(child);
471 pci_read_bridge_mmio_pref(child); 472 pci_read_bridge_mmio_pref(child);
472 473
473 if (dev->transparent) { 474 if (dev->transparent) {
474 pci_bus_for_each_resource(child->parent, res, i) { 475 pci_bus_for_each_resource(child->parent, res, i) {
475 if (res) { 476 if (res) {
476 pci_bus_add_resource(child, res, 477 pci_bus_add_resource(child, res,
477 PCI_SUBTRACTIVE_DECODE); 478 PCI_SUBTRACTIVE_DECODE);
478 dev_printk(KERN_DEBUG, &dev->dev, 479 dev_printk(KERN_DEBUG, &dev->dev,
479 " bridge window %pR (subtractive decode)\n", 480 " bridge window %pR (subtractive decode)\n",
480 res); 481 res);
481 } 482 }
482 } 483 }
483 } 484 }
484 } 485 }
485 486
486 static struct pci_bus * pci_alloc_bus(void) 487 static struct pci_bus * pci_alloc_bus(void)
487 { 488 {
488 struct pci_bus *b; 489 struct pci_bus *b;
489 490
490 b = kzalloc(sizeof(*b), GFP_KERNEL); 491 b = kzalloc(sizeof(*b), GFP_KERNEL);
491 if (b) { 492 if (b) {
492 INIT_LIST_HEAD(&b->node); 493 INIT_LIST_HEAD(&b->node);
493 INIT_LIST_HEAD(&b->children); 494 INIT_LIST_HEAD(&b->children);
494 INIT_LIST_HEAD(&b->devices); 495 INIT_LIST_HEAD(&b->devices);
495 INIT_LIST_HEAD(&b->slots); 496 INIT_LIST_HEAD(&b->slots);
496 INIT_LIST_HEAD(&b->resources); 497 INIT_LIST_HEAD(&b->resources);
497 b->max_bus_speed = PCI_SPEED_UNKNOWN; 498 b->max_bus_speed = PCI_SPEED_UNKNOWN;
498 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 499 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
499 } 500 }
500 return b; 501 return b;
501 } 502 }
502 503
503 static unsigned char pcix_bus_speed[] = { 504 static unsigned char pcix_bus_speed[] = {
504 PCI_SPEED_UNKNOWN, /* 0 */ 505 PCI_SPEED_UNKNOWN, /* 0 */
505 PCI_SPEED_66MHz_PCIX, /* 1 */ 506 PCI_SPEED_66MHz_PCIX, /* 1 */
506 PCI_SPEED_100MHz_PCIX, /* 2 */ 507 PCI_SPEED_100MHz_PCIX, /* 2 */
507 PCI_SPEED_133MHz_PCIX, /* 3 */ 508 PCI_SPEED_133MHz_PCIX, /* 3 */
508 PCI_SPEED_UNKNOWN, /* 4 */ 509 PCI_SPEED_UNKNOWN, /* 4 */
509 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 510 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
510 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 511 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
511 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 512 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
512 PCI_SPEED_UNKNOWN, /* 8 */ 513 PCI_SPEED_UNKNOWN, /* 8 */
513 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 514 PCI_SPEED_66MHz_PCIX_266, /* 9 */
514 PCI_SPEED_100MHz_PCIX_266, /* A */ 515 PCI_SPEED_100MHz_PCIX_266, /* A */
515 PCI_SPEED_133MHz_PCIX_266, /* B */ 516 PCI_SPEED_133MHz_PCIX_266, /* B */
516 PCI_SPEED_UNKNOWN, /* C */ 517 PCI_SPEED_UNKNOWN, /* C */
517 PCI_SPEED_66MHz_PCIX_533, /* D */ 518 PCI_SPEED_66MHz_PCIX_533, /* D */
518 PCI_SPEED_100MHz_PCIX_533, /* E */ 519 PCI_SPEED_100MHz_PCIX_533, /* E */
519 PCI_SPEED_133MHz_PCIX_533 /* F */ 520 PCI_SPEED_133MHz_PCIX_533 /* F */
520 }; 521 };
521 522
522 static unsigned char pcie_link_speed[] = { 523 static unsigned char pcie_link_speed[] = {
523 PCI_SPEED_UNKNOWN, /* 0 */ 524 PCI_SPEED_UNKNOWN, /* 0 */
524 PCIE_SPEED_2_5GT, /* 1 */ 525 PCIE_SPEED_2_5GT, /* 1 */
525 PCIE_SPEED_5_0GT, /* 2 */ 526 PCIE_SPEED_5_0GT, /* 2 */
526 PCIE_SPEED_8_0GT, /* 3 */ 527 PCIE_SPEED_8_0GT, /* 3 */
527 PCI_SPEED_UNKNOWN, /* 4 */ 528 PCI_SPEED_UNKNOWN, /* 4 */
528 PCI_SPEED_UNKNOWN, /* 5 */ 529 PCI_SPEED_UNKNOWN, /* 5 */
529 PCI_SPEED_UNKNOWN, /* 6 */ 530 PCI_SPEED_UNKNOWN, /* 6 */
530 PCI_SPEED_UNKNOWN, /* 7 */ 531 PCI_SPEED_UNKNOWN, /* 7 */
531 PCI_SPEED_UNKNOWN, /* 8 */ 532 PCI_SPEED_UNKNOWN, /* 8 */
532 PCI_SPEED_UNKNOWN, /* 9 */ 533 PCI_SPEED_UNKNOWN, /* 9 */
533 PCI_SPEED_UNKNOWN, /* A */ 534 PCI_SPEED_UNKNOWN, /* A */
534 PCI_SPEED_UNKNOWN, /* B */ 535 PCI_SPEED_UNKNOWN, /* B */
535 PCI_SPEED_UNKNOWN, /* C */ 536 PCI_SPEED_UNKNOWN, /* C */
536 PCI_SPEED_UNKNOWN, /* D */ 537 PCI_SPEED_UNKNOWN, /* D */
537 PCI_SPEED_UNKNOWN, /* E */ 538 PCI_SPEED_UNKNOWN, /* E */
538 PCI_SPEED_UNKNOWN /* F */ 539 PCI_SPEED_UNKNOWN /* F */
539 }; 540 };
540 541
541 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 542 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
542 { 543 {
543 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf]; 544 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
544 } 545 }
545 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 546 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
546 547
547 static unsigned char agp_speeds[] = { 548 static unsigned char agp_speeds[] = {
548 AGP_UNKNOWN, 549 AGP_UNKNOWN,
549 AGP_1X, 550 AGP_1X,
550 AGP_2X, 551 AGP_2X,
551 AGP_4X, 552 AGP_4X,
552 AGP_8X 553 AGP_8X
553 }; 554 };
554 555
555 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 556 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
556 { 557 {
557 int index = 0; 558 int index = 0;
558 559
559 if (agpstat & 4) 560 if (agpstat & 4)
560 index = 3; 561 index = 3;
561 else if (agpstat & 2) 562 else if (agpstat & 2)
562 index = 2; 563 index = 2;
563 else if (agpstat & 1) 564 else if (agpstat & 1)
564 index = 1; 565 index = 1;
565 else 566 else
566 goto out; 567 goto out;
567 568
568 if (agp3) { 569 if (agp3) {
569 index += 2; 570 index += 2;
570 if (index == 5) 571 if (index == 5)
571 index = 0; 572 index = 0;
572 } 573 }
573 574
574 out: 575 out:
575 return agp_speeds[index]; 576 return agp_speeds[index];
576 } 577 }
577 578
578 579
579 static void pci_set_bus_speed(struct pci_bus *bus) 580 static void pci_set_bus_speed(struct pci_bus *bus)
580 { 581 {
581 struct pci_dev *bridge = bus->self; 582 struct pci_dev *bridge = bus->self;
582 int pos; 583 int pos;
583 584
584 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 585 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
585 if (!pos) 586 if (!pos)
586 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 587 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
587 if (pos) { 588 if (pos) {
588 u32 agpstat, agpcmd; 589 u32 agpstat, agpcmd;
589 590
590 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 591 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
591 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 592 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
592 593
593 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 594 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
594 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 595 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
595 } 596 }
596 597
597 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 598 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
598 if (pos) { 599 if (pos) {
599 u16 status; 600 u16 status;
600 enum pci_bus_speed max; 601 enum pci_bus_speed max;
601 pci_read_config_word(bridge, pos + 2, &status); 602 pci_read_config_word(bridge, pos + 2, &status);
602 603
603 if (status & 0x8000) { 604 if (status & 0x8000) {
604 max = PCI_SPEED_133MHz_PCIX_533; 605 max = PCI_SPEED_133MHz_PCIX_533;
605 } else if (status & 0x4000) { 606 } else if (status & 0x4000) {
606 max = PCI_SPEED_133MHz_PCIX_266; 607 max = PCI_SPEED_133MHz_PCIX_266;
607 } else if (status & 0x0002) { 608 } else if (status & 0x0002) {
608 if (((status >> 12) & 0x3) == 2) { 609 if (((status >> 12) & 0x3) == 2) {
609 max = PCI_SPEED_133MHz_PCIX_ECC; 610 max = PCI_SPEED_133MHz_PCIX_ECC;
610 } else { 611 } else {
611 max = PCI_SPEED_133MHz_PCIX; 612 max = PCI_SPEED_133MHz_PCIX;
612 } 613 }
613 } else { 614 } else {
614 max = PCI_SPEED_66MHz_PCIX; 615 max = PCI_SPEED_66MHz_PCIX;
615 } 616 }
616 617
617 bus->max_bus_speed = max; 618 bus->max_bus_speed = max;
618 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; 619 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
619 620
620 return; 621 return;
621 } 622 }
622 623
623 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); 624 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
624 if (pos) { 625 if (pos) {
625 u32 linkcap; 626 u32 linkcap;
626 u16 linksta; 627 u16 linksta;
627 628
628 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap); 629 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
629 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; 630 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
630 631
631 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta); 632 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
632 pcie_update_link_speed(bus, linksta); 633 pcie_update_link_speed(bus, linksta);
633 } 634 }
634 } 635 }
635 636
636 637
637 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 638 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
638 struct pci_dev *bridge, int busnr) 639 struct pci_dev *bridge, int busnr)
639 { 640 {
640 struct pci_bus *child; 641 struct pci_bus *child;
641 int i; 642 int i;
642 643
643 /* 644 /*
644 * Allocate a new bus, and inherit stuff from the parent.. 645 * Allocate a new bus, and inherit stuff from the parent..
645 */ 646 */
646 child = pci_alloc_bus(); 647 child = pci_alloc_bus();
647 if (!child) 648 if (!child)
648 return NULL; 649 return NULL;
649 650
650 child->parent = parent; 651 child->parent = parent;
651 child->ops = parent->ops; 652 child->ops = parent->ops;
652 child->sysdata = parent->sysdata; 653 child->sysdata = parent->sysdata;
653 child->bus_flags = parent->bus_flags; 654 child->bus_flags = parent->bus_flags;
654 655
655 /* initialize some portions of the bus device, but don't register it 656 /* initialize some portions of the bus device, but don't register it
656 * now as the parent is not properly set up yet. This device will get 657 * now as the parent is not properly set up yet. This device will get
657 * registered later in pci_bus_add_devices() 658 * registered later in pci_bus_add_devices()
658 */ 659 */
659 child->dev.class = &pcibus_class; 660 child->dev.class = &pcibus_class;
660 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 661 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
661 662
662 /* 663 /*
663 * Set up the primary, secondary and subordinate 664 * Set up the primary, secondary and subordinate
664 * bus numbers. 665 * bus numbers.
665 */ 666 */
666 child->number = child->secondary = busnr; 667 child->number = child->secondary = busnr;
667 child->primary = parent->secondary; 668 child->primary = parent->secondary;
668 child->subordinate = 0xff; 669 child->subordinate = 0xff;
669 670
670 if (!bridge) 671 if (!bridge)
671 return child; 672 return child;
672 673
673 child->self = bridge; 674 child->self = bridge;
674 child->bridge = get_device(&bridge->dev); 675 child->bridge = get_device(&bridge->dev);
675 pci_set_bus_of_node(child); 676 pci_set_bus_of_node(child);
676 pci_set_bus_speed(child); 677 pci_set_bus_speed(child);
677 678
678 /* Set up default resource pointers and names.. */ 679 /* Set up default resource pointers and names.. */
679 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 680 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
680 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 681 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
681 child->resource[i]->name = child->name; 682 child->resource[i]->name = child->name;
682 } 683 }
683 bridge->subordinate = child; 684 bridge->subordinate = child;
684 685
685 return child; 686 return child;
686 } 687 }
687 688
688 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) 689 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
689 { 690 {
690 struct pci_bus *child; 691 struct pci_bus *child;
691 692
692 child = pci_alloc_child_bus(parent, dev, busnr); 693 child = pci_alloc_child_bus(parent, dev, busnr);
693 if (child) { 694 if (child) {
694 down_write(&pci_bus_sem); 695 down_write(&pci_bus_sem);
695 list_add_tail(&child->node, &parent->children); 696 list_add_tail(&child->node, &parent->children);
696 up_write(&pci_bus_sem); 697 up_write(&pci_bus_sem);
697 } 698 }
698 return child; 699 return child;
699 } 700 }
700 701
701 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) 702 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
702 { 703 {
703 struct pci_bus *parent = child->parent; 704 struct pci_bus *parent = child->parent;
704 705
705 /* Attempts to fix that up are really dangerous unless 706 /* Attempts to fix that up are really dangerous unless
706 we're going to re-assign all bus numbers. */ 707 we're going to re-assign all bus numbers. */
707 if (!pcibios_assign_all_busses()) 708 if (!pcibios_assign_all_busses())
708 return; 709 return;
709 710
710 while (parent->parent && parent->subordinate < max) { 711 while (parent->parent && parent->subordinate < max) {
711 parent->subordinate = max; 712 parent->subordinate = max;
712 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); 713 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
713 parent = parent->parent; 714 parent = parent->parent;
714 } 715 }
715 } 716 }
716 717
717 /* 718 /*
718 * If it's a bridge, configure it and scan the bus behind it. 719 * If it's a bridge, configure it and scan the bus behind it.
719 * For CardBus bridges, we don't scan behind as the devices will 720 * For CardBus bridges, we don't scan behind as the devices will
720 * be handled by the bridge driver itself. 721 * be handled by the bridge driver itself.
721 * 722 *
722 * We need to process bridges in two passes -- first we scan those 723 * We need to process bridges in two passes -- first we scan those
723 * already configured by the BIOS and after we are done with all of 724 * already configured by the BIOS and after we are done with all of
724 * them, we proceed to assigning numbers to the remaining buses in 725 * them, we proceed to assigning numbers to the remaining buses in
725 * order to avoid overlaps between old and new bus numbers. 726 * order to avoid overlaps between old and new bus numbers.
726 */ 727 */
727 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 728 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
728 { 729 {
729 struct pci_bus *child; 730 struct pci_bus *child;
730 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 731 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
731 u32 buses, i, j = 0; 732 u32 buses, i, j = 0;
732 u16 bctl; 733 u16 bctl;
733 u8 primary, secondary, subordinate; 734 u8 primary, secondary, subordinate;
734 int broken = 0; 735 int broken = 0;
735 736
736 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 737 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
737 primary = buses & 0xFF; 738 primary = buses & 0xFF;
738 secondary = (buses >> 8) & 0xFF; 739 secondary = (buses >> 8) & 0xFF;
739 subordinate = (buses >> 16) & 0xFF; 740 subordinate = (buses >> 16) & 0xFF;
740 741
741 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 742 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
742 secondary, subordinate, pass); 743 secondary, subordinate, pass);
743 744
744 if (!primary && (primary != bus->number) && secondary && subordinate) { 745 if (!primary && (primary != bus->number) && secondary && subordinate) {
745 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n"); 746 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
746 primary = bus->number; 747 primary = bus->number;
747 } 748 }
748 749
749 /* Check if setup is sensible at all */ 750 /* Check if setup is sensible at all */
750 if (!pass && 751 if (!pass &&
751 (primary != bus->number || secondary <= bus->number)) { 752 (primary != bus->number || secondary <= bus->number)) {
752 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); 753 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
753 broken = 1; 754 broken = 1;
754 } 755 }
755 756
756 /* Disable MasterAbortMode during probing to avoid reporting 757 /* Disable MasterAbortMode during probing to avoid reporting
757 of bus errors (in some architectures) */ 758 of bus errors (in some architectures) */
758 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 759 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
759 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 760 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
760 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 761 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
761 762
762 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 763 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
763 !is_cardbus && !broken) { 764 !is_cardbus && !broken) {
764 unsigned int cmax; 765 unsigned int cmax;
765 /* 766 /*
766 * Bus already configured by firmware, process it in the first 767 * Bus already configured by firmware, process it in the first
767 * pass and just note the configuration. 768 * pass and just note the configuration.
768 */ 769 */
769 if (pass) 770 if (pass)
770 goto out; 771 goto out;
771 772
772 /* 773 /*
773 * If we already got to this bus through a different bridge, 774 * If we already got to this bus through a different bridge,
774 * don't re-add it. This can happen with the i450NX chipset. 775 * don't re-add it. This can happen with the i450NX chipset.
775 * 776 *
776 * However, we continue to descend down the hierarchy and 777 * However, we continue to descend down the hierarchy and
777 * scan remaining child buses. 778 * scan remaining child buses.
778 */ 779 */
779 child = pci_find_bus(pci_domain_nr(bus), secondary); 780 child = pci_find_bus(pci_domain_nr(bus), secondary);
780 if (!child) { 781 if (!child) {
781 child = pci_add_new_bus(bus, dev, secondary); 782 child = pci_add_new_bus(bus, dev, secondary);
782 if (!child) 783 if (!child)
783 goto out; 784 goto out;
784 child->primary = primary; 785 child->primary = primary;
785 child->subordinate = subordinate; 786 child->subordinate = subordinate;
786 child->bridge_ctl = bctl; 787 child->bridge_ctl = bctl;
787 } 788 }
788 789
789 cmax = pci_scan_child_bus(child); 790 cmax = pci_scan_child_bus(child);
790 if (cmax > max) 791 if (cmax > max)
791 max = cmax; 792 max = cmax;
792 if (child->subordinate > max) 793 if (child->subordinate > max)
793 max = child->subordinate; 794 max = child->subordinate;
794 } else { 795 } else {
795 /* 796 /*
796 * We need to assign a number to this bus which we always 797 * We need to assign a number to this bus which we always
797 * do in the second pass. 798 * do in the second pass.
798 */ 799 */
799 if (!pass) { 800 if (!pass) {
800 if (pcibios_assign_all_busses() || broken) 801 if (pcibios_assign_all_busses() || broken)
801 /* Temporarily disable forwarding of the 802 /* Temporarily disable forwarding of the
802 configuration cycles on all bridges in 803 configuration cycles on all bridges in
803 this bus segment to avoid possible 804 this bus segment to avoid possible
804 conflicts in the second pass between two 805 conflicts in the second pass between two
805 bridges programmed with overlapping 806 bridges programmed with overlapping
806 bus ranges. */ 807 bus ranges. */
807 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 808 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
808 buses & ~0xffffff); 809 buses & ~0xffffff);
809 goto out; 810 goto out;
810 } 811 }
811 812
812 /* Clear errors */ 813 /* Clear errors */
813 pci_write_config_word(dev, PCI_STATUS, 0xffff); 814 pci_write_config_word(dev, PCI_STATUS, 0xffff);
814 815
815 /* Prevent assigning a bus number that already exists. 816 /* Prevent assigning a bus number that already exists.
816 * This can happen when a bridge is hot-plugged, so in 817 * This can happen when a bridge is hot-plugged, so in
817 * this case we only re-scan this bus. */ 818 * this case we only re-scan this bus. */
818 child = pci_find_bus(pci_domain_nr(bus), max+1); 819 child = pci_find_bus(pci_domain_nr(bus), max+1);
819 if (!child) { 820 if (!child) {
820 child = pci_add_new_bus(bus, dev, ++max); 821 child = pci_add_new_bus(bus, dev, ++max);
821 if (!child) 822 if (!child)
822 goto out; 823 goto out;
823 } 824 }
824 buses = (buses & 0xff000000) 825 buses = (buses & 0xff000000)
825 | ((unsigned int)(child->primary) << 0) 826 | ((unsigned int)(child->primary) << 0)
826 | ((unsigned int)(child->secondary) << 8) 827 | ((unsigned int)(child->secondary) << 8)
827 | ((unsigned int)(child->subordinate) << 16); 828 | ((unsigned int)(child->subordinate) << 16);
828 829
829 /* 830 /*
830 * yenta.c forces a secondary latency timer of 176. 831 * yenta.c forces a secondary latency timer of 176.
831 * Copy that behaviour here. 832 * Copy that behaviour here.
832 */ 833 */
833 if (is_cardbus) { 834 if (is_cardbus) {
834 buses &= ~0xff000000; 835 buses &= ~0xff000000;
835 buses |= CARDBUS_LATENCY_TIMER << 24; 836 buses |= CARDBUS_LATENCY_TIMER << 24;
836 } 837 }
837 838
838 /* 839 /*
839 * We need to blast all three values with a single write. 840 * We need to blast all three values with a single write.
840 */ 841 */
841 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 842 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
842 843
843 if (!is_cardbus) { 844 if (!is_cardbus) {
844 child->bridge_ctl = bctl; 845 child->bridge_ctl = bctl;
845 /* 846 /*
846 * Adjust subordinate busnr in parent buses. 847 * Adjust subordinate busnr in parent buses.
847 * We do this before scanning for children because 848 * We do this before scanning for children because
848 * some devices may not be detected if the bios 849 * some devices may not be detected if the bios
849 * was lazy. 850 * was lazy.
850 */ 851 */
851 pci_fixup_parent_subordinate_busnr(child, max); 852 pci_fixup_parent_subordinate_busnr(child, max);
852 /* Now we can scan all subordinate buses... */ 853 /* Now we can scan all subordinate buses... */
853 max = pci_scan_child_bus(child); 854 max = pci_scan_child_bus(child);
854 /* 855 /*
855 * now fix it up again since we have found 856 * now fix it up again since we have found
856 * the real value of max. 857 * the real value of max.
857 */ 858 */
858 pci_fixup_parent_subordinate_busnr(child, max); 859 pci_fixup_parent_subordinate_busnr(child, max);
859 } else { 860 } else {
860 /* 861 /*
861 * For CardBus bridges, we leave 4 bus numbers 862 * For CardBus bridges, we leave 4 bus numbers
862 * as cards with a PCI-to-PCI bridge can be 863 * as cards with a PCI-to-PCI bridge can be
863 * inserted later. 864 * inserted later.
864 */ 865 */
865 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { 866 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
866 struct pci_bus *parent = bus; 867 struct pci_bus *parent = bus;
867 if (pci_find_bus(pci_domain_nr(bus), 868 if (pci_find_bus(pci_domain_nr(bus),
868 max+i+1)) 869 max+i+1))
869 break; 870 break;
870 while (parent->parent) { 871 while (parent->parent) {
871 if ((!pcibios_assign_all_busses()) && 872 if ((!pcibios_assign_all_busses()) &&
872 (parent->subordinate > max) && 873 (parent->subordinate > max) &&
873 (parent->subordinate <= max+i)) { 874 (parent->subordinate <= max+i)) {
874 j = 1; 875 j = 1;
875 } 876 }
876 parent = parent->parent; 877 parent = parent->parent;
877 } 878 }
878 if (j) { 879 if (j) {
879 /* 880 /*
880 * Often, there are two cardbus bridges 881 * Often, there are two cardbus bridges
881 * -- try to leave one valid bus number 882 * -- try to leave one valid bus number
882 * for each one. 883 * for each one.
883 */ 884 */
884 i /= 2; 885 i /= 2;
885 break; 886 break;
886 } 887 }
887 } 888 }
888 max += i; 889 max += i;
889 pci_fixup_parent_subordinate_busnr(child, max); 890 pci_fixup_parent_subordinate_busnr(child, max);
890 } 891 }
891 /* 892 /*
892 * Set the subordinate bus number to its real value. 893 * Set the subordinate bus number to its real value.
893 */ 894 */
894 child->subordinate = max; 895 child->subordinate = max;
895 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 896 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
896 } 897 }
897 898
898 sprintf(child->name, 899 sprintf(child->name,
899 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 900 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
900 pci_domain_nr(bus), child->number); 901 pci_domain_nr(bus), child->number);
901 902
902 /* Has only triggered on CardBus, fixup is in yenta_socket */ 903 /* Has only triggered on CardBus, fixup is in yenta_socket */
903 while (bus->parent) { 904 while (bus->parent) {
904 if ((child->subordinate > bus->subordinate) || 905 if ((child->subordinate > bus->subordinate) ||
905 (child->number > bus->subordinate) || 906 (child->number > bus->subordinate) ||
906 (child->number < bus->number) || 907 (child->number < bus->number) ||
907 (child->subordinate < bus->number)) { 908 (child->subordinate < bus->number)) {
908 dev_info(&child->dev, "[bus %02x-%02x] %s " 909 dev_info(&child->dev, "[bus %02x-%02x] %s "
909 "hidden behind%s bridge %s [bus %02x-%02x]\n", 910 "hidden behind%s bridge %s [bus %02x-%02x]\n",
910 child->number, child->subordinate, 911 child->number, child->subordinate,
911 (bus->number > child->subordinate && 912 (bus->number > child->subordinate &&
912 bus->subordinate < child->number) ? 913 bus->subordinate < child->number) ?
913 "wholly" : "partially", 914 "wholly" : "partially",
914 bus->self->transparent ? " transparent" : "", 915 bus->self->transparent ? " transparent" : "",
915 dev_name(&bus->dev), 916 dev_name(&bus->dev),
916 bus->number, bus->subordinate); 917 bus->number, bus->subordinate);
917 } 918 }
918 bus = bus->parent; 919 bus = bus->parent;
919 } 920 }
920 921
921 out: 922 out:
922 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 923 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
923 924
924 return max; 925 return max;
925 } 926 }
926 927
927 /* 928 /*
928 * Read interrupt line and base address registers. 929 * Read interrupt line and base address registers.
929 * The architecture-dependent code can tweak these, of course. 930 * The architecture-dependent code can tweak these, of course.
930 */ 931 */
931 static void pci_read_irq(struct pci_dev *dev) 932 static void pci_read_irq(struct pci_dev *dev)
932 { 933 {
933 unsigned char irq; 934 unsigned char irq;
934 935
935 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 936 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
936 dev->pin = irq; 937 dev->pin = irq;
937 if (irq) 938 if (irq)
938 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 939 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
939 dev->irq = irq; 940 dev->irq = irq;
940 } 941 }
941 942
942 void set_pcie_port_type(struct pci_dev *pdev) 943 void set_pcie_port_type(struct pci_dev *pdev)
943 { 944 {
944 int pos; 945 int pos;
945 u16 reg16; 946 u16 reg16;
946 947
947 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 948 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
948 if (!pos) 949 if (!pos)
949 return; 950 return;
950 pdev->is_pcie = 1; 951 pdev->is_pcie = 1;
951 pdev->pcie_cap = pos; 952 pdev->pcie_cap = pos;
952 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16); 953 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
953 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; 954 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
954 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16); 955 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
955 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 956 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
956 } 957 }
957 958
958 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 959 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
959 { 960 {
960 int pos; 961 int pos;
961 u16 reg16; 962 u16 reg16;
962 u32 reg32; 963 u32 reg32;
963 964
964 pos = pci_pcie_cap(pdev); 965 pos = pci_pcie_cap(pdev);
965 if (!pos) 966 if (!pos)
966 return; 967 return;
967 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16); 968 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
968 if (!(reg16 & PCI_EXP_FLAGS_SLOT)) 969 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
969 return; 970 return;
970 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32); 971 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
971 if (reg32 & PCI_EXP_SLTCAP_HPC) 972 if (reg32 & PCI_EXP_SLTCAP_HPC)
972 pdev->is_hotplug_bridge = 1; 973 pdev->is_hotplug_bridge = 1;
973 } 974 }
974 975
975 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 976 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
976 977
977 /** 978 /**
978 * pci_setup_device - fill in class and map information of a device 979 * pci_setup_device - fill in class and map information of a device
979 * @dev: the device structure to fill 980 * @dev: the device structure to fill
980 * 981 *
981 * Initialize the device structure with information about the device's 982 * Initialize the device structure with information about the device's
982 * vendor,class,memory and IO-space addresses,IRQ lines etc. 983 * vendor,class,memory and IO-space addresses,IRQ lines etc.
983 * Called at initialisation of the PCI subsystem and by CardBus services. 984 * Called at initialisation of the PCI subsystem and by CardBus services.
984 * Returns 0 on success and negative if unknown type of device (not normal, 985 * Returns 0 on success and negative if unknown type of device (not normal,
985 * bridge or CardBus). 986 * bridge or CardBus).
986 */ 987 */
987 int pci_setup_device(struct pci_dev *dev) 988 int pci_setup_device(struct pci_dev *dev)
988 { 989 {
989 u32 class; 990 u32 class;
990 u8 hdr_type; 991 u8 hdr_type;
991 struct pci_slot *slot; 992 struct pci_slot *slot;
992 int pos = 0; 993 int pos = 0;
993 struct pci_bus_region region; 994 struct pci_bus_region region;
994 struct resource *res; 995 struct resource *res;
995 996
996 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) 997 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
997 return -EIO; 998 return -EIO;
998 999
999 dev->sysdata = dev->bus->sysdata; 1000 dev->sysdata = dev->bus->sysdata;
1000 dev->dev.parent = dev->bus->bridge; 1001 dev->dev.parent = dev->bus->bridge;
1001 dev->dev.bus = &pci_bus_type; 1002 dev->dev.bus = &pci_bus_type;
1002 dev->hdr_type = hdr_type & 0x7f; 1003 dev->hdr_type = hdr_type & 0x7f;
1003 dev->multifunction = !!(hdr_type & 0x80); 1004 dev->multifunction = !!(hdr_type & 0x80);
1004 dev->error_state = pci_channel_io_normal; 1005 dev->error_state = pci_channel_io_normal;
1005 set_pcie_port_type(dev); 1006 set_pcie_port_type(dev);
1006 1007
1007 list_for_each_entry(slot, &dev->bus->slots, list) 1008 list_for_each_entry(slot, &dev->bus->slots, list)
1008 if (PCI_SLOT(dev->devfn) == slot->number) 1009 if (PCI_SLOT(dev->devfn) == slot->number)
1009 dev->slot = slot; 1010 dev->slot = slot;
1010 1011
1011 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1012 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1012 set this higher, assuming the system even supports it. */ 1013 set this higher, assuming the system even supports it. */
1013 dev->dma_mask = 0xffffffff; 1014 dev->dma_mask = 0xffffffff;
1014 1015
1015 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1016 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1016 dev->bus->number, PCI_SLOT(dev->devfn), 1017 dev->bus->number, PCI_SLOT(dev->devfn),
1017 PCI_FUNC(dev->devfn)); 1018 PCI_FUNC(dev->devfn));
1018 1019
1019 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1020 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1020 dev->revision = class & 0xff; 1021 dev->revision = class & 0xff;
1021 dev->class = class >> 8; /* upper 3 bytes */ 1022 dev->class = class >> 8; /* upper 3 bytes */
1022 1023
1023 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n", 1024 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1024 dev->vendor, dev->device, dev->hdr_type, dev->class); 1025 dev->vendor, dev->device, dev->hdr_type, dev->class);
1025 1026
1026 /* need to have dev->class ready */ 1027 /* need to have dev->class ready */
1027 dev->cfg_size = pci_cfg_space_size(dev); 1028 dev->cfg_size = pci_cfg_space_size(dev);
1028 1029
1029 /* "Unknown power state" */ 1030 /* "Unknown power state" */
1030 dev->current_state = PCI_UNKNOWN; 1031 dev->current_state = PCI_UNKNOWN;
1031 1032
1032 /* Early fixups, before probing the BARs */ 1033 /* Early fixups, before probing the BARs */
1033 pci_fixup_device(pci_fixup_early, dev); 1034 pci_fixup_device(pci_fixup_early, dev);
1034 /* device class may be changed after fixup */ 1035 /* device class may be changed after fixup */
1035 class = dev->class >> 8; 1036 class = dev->class >> 8;
1036 1037
1037 switch (dev->hdr_type) { /* header type */ 1038 switch (dev->hdr_type) { /* header type */
1038 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1039 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1039 if (class == PCI_CLASS_BRIDGE_PCI) 1040 if (class == PCI_CLASS_BRIDGE_PCI)
1040 goto bad; 1041 goto bad;
1041 pci_read_irq(dev); 1042 pci_read_irq(dev);
1042 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1043 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1043 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1044 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1044 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); 1045 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1045 1046
1046 /* 1047 /*
1047 * Do the ugly legacy mode stuff here rather than broken chip 1048 * Do the ugly legacy mode stuff here rather than broken chip
1048 * quirk code. Legacy mode ATA controllers have fixed 1049 * quirk code. Legacy mode ATA controllers have fixed
1049 * addresses. These are not always echoed in BAR0-3, and 1050 * addresses. These are not always echoed in BAR0-3, and
1050 * BAR0-3 in a few cases contain junk! 1051 * BAR0-3 in a few cases contain junk!
1051 */ 1052 */
1052 if (class == PCI_CLASS_STORAGE_IDE) { 1053 if (class == PCI_CLASS_STORAGE_IDE) {
1053 u8 progif; 1054 u8 progif;
1054 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1055 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1055 if ((progif & 1) == 0) { 1056 if ((progif & 1) == 0) {
1056 region.start = 0x1F0; 1057 region.start = 0x1F0;
1057 region.end = 0x1F7; 1058 region.end = 0x1F7;
1058 res = &dev->resource[0]; 1059 res = &dev->resource[0];
1059 res->flags = LEGACY_IO_RESOURCE; 1060 res->flags = LEGACY_IO_RESOURCE;
1060 pcibios_bus_to_resource(dev, res, &region); 1061 pcibios_bus_to_resource(dev, res, &region);
1061 region.start = 0x3F6; 1062 region.start = 0x3F6;
1062 region.end = 0x3F6; 1063 region.end = 0x3F6;
1063 res = &dev->resource[1]; 1064 res = &dev->resource[1];
1064 res->flags = LEGACY_IO_RESOURCE; 1065 res->flags = LEGACY_IO_RESOURCE;
1065 pcibios_bus_to_resource(dev, res, &region); 1066 pcibios_bus_to_resource(dev, res, &region);
1066 } 1067 }
1067 if ((progif & 4) == 0) { 1068 if ((progif & 4) == 0) {
1068 region.start = 0x170; 1069 region.start = 0x170;
1069 region.end = 0x177; 1070 region.end = 0x177;
1070 res = &dev->resource[2]; 1071 res = &dev->resource[2];
1071 res->flags = LEGACY_IO_RESOURCE; 1072 res->flags = LEGACY_IO_RESOURCE;
1072 pcibios_bus_to_resource(dev, res, &region); 1073 pcibios_bus_to_resource(dev, res, &region);
1073 region.start = 0x376; 1074 region.start = 0x376;
1074 region.end = 0x376; 1075 region.end = 0x376;
1075 res = &dev->resource[3]; 1076 res = &dev->resource[3];
1076 res->flags = LEGACY_IO_RESOURCE; 1077 res->flags = LEGACY_IO_RESOURCE;
1077 pcibios_bus_to_resource(dev, res, &region); 1078 pcibios_bus_to_resource(dev, res, &region);
1078 } 1079 }
1079 } 1080 }
1080 break; 1081 break;
1081 1082
1082 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1083 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1083 if (class != PCI_CLASS_BRIDGE_PCI) 1084 if (class != PCI_CLASS_BRIDGE_PCI)
1084 goto bad; 1085 goto bad;
1085 /* The PCI-to-PCI bridge spec requires that subtractive 1086 /* The PCI-to-PCI bridge spec requires that subtractive
1086 decoding (i.e. transparent) bridge must have programming 1087 decoding (i.e. transparent) bridge must have programming
1087 interface code of 0x01. */ 1088 interface code of 0x01. */
1088 pci_read_irq(dev); 1089 pci_read_irq(dev);
1089 dev->transparent = ((dev->class & 0xff) == 1); 1090 dev->transparent = ((dev->class & 0xff) == 1);
1090 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1091 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1091 set_pcie_hotplug_bridge(dev); 1092 set_pcie_hotplug_bridge(dev);
1092 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1093 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1093 if (pos) { 1094 if (pos) {
1094 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1095 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1095 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1096 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1096 } 1097 }
1097 break; 1098 break;
1098 1099
1099 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1100 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1100 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1101 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1101 goto bad; 1102 goto bad;
1102 pci_read_irq(dev); 1103 pci_read_irq(dev);
1103 pci_read_bases(dev, 1, 0); 1104 pci_read_bases(dev, 1, 0);
1104 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1105 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1105 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1106 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1106 break; 1107 break;
1107 1108
1108 default: /* unknown header */ 1109 default: /* unknown header */
1109 dev_err(&dev->dev, "unknown header type %02x, " 1110 dev_err(&dev->dev, "unknown header type %02x, "
1110 "ignoring device\n", dev->hdr_type); 1111 "ignoring device\n", dev->hdr_type);
1111 return -EIO; 1112 return -EIO;
1112 1113
1113 bad: 1114 bad:
1114 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header " 1115 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header "
1115 "type %02x)\n", dev->class, dev->hdr_type); 1116 "type %02x)\n", dev->class, dev->hdr_type);
1116 dev->class = PCI_CLASS_NOT_DEFINED; 1117 dev->class = PCI_CLASS_NOT_DEFINED;
1117 } 1118 }
1118 1119
1119 /* We found a fine healthy device, go go go... */ 1120 /* We found a fine healthy device, go go go... */
1120 return 0; 1121 return 0;
1121 } 1122 }
1122 1123
1123 static void pci_release_capabilities(struct pci_dev *dev) 1124 static void pci_release_capabilities(struct pci_dev *dev)
1124 { 1125 {
1125 pci_vpd_release(dev); 1126 pci_vpd_release(dev);
1126 pci_iov_release(dev); 1127 pci_iov_release(dev);
1127 pci_free_cap_save_buffers(dev); 1128 pci_free_cap_save_buffers(dev);
1128 } 1129 }
1129 1130
1130 /** 1131 /**
1131 * pci_release_dev - free a pci device structure when all users of it are finished. 1132 * pci_release_dev - free a pci device structure when all users of it are finished.
1132 * @dev: device that's been disconnected 1133 * @dev: device that's been disconnected
1133 * 1134 *
1134 * Will be called only by the device core when all users of this pci device are 1135 * Will be called only by the device core when all users of this pci device are
1135 * done. 1136 * done.
1136 */ 1137 */
1137 static void pci_release_dev(struct device *dev) 1138 static void pci_release_dev(struct device *dev)
1138 { 1139 {
1139 struct pci_dev *pci_dev; 1140 struct pci_dev *pci_dev;
1140 1141
1141 pci_dev = to_pci_dev(dev); 1142 pci_dev = to_pci_dev(dev);
1142 pci_release_capabilities(pci_dev); 1143 pci_release_capabilities(pci_dev);
1143 pci_release_of_node(pci_dev); 1144 pci_release_of_node(pci_dev);
1144 kfree(pci_dev); 1145 kfree(pci_dev);
1145 } 1146 }
1146 1147
1147 /** 1148 /**
1148 * pci_cfg_space_size - get the configuration space size of the PCI device. 1149 * pci_cfg_space_size - get the configuration space size of the PCI device.
1149 * @dev: PCI device 1150 * @dev: PCI device
1150 * 1151 *
1151 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1152 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1152 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1153 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1153 * access it. Maybe we don't have a way to generate extended config space 1154 * access it. Maybe we don't have a way to generate extended config space
1154 * accesses, or the device is behind a reverse Express bridge. So we try 1155 * accesses, or the device is behind a reverse Express bridge. So we try
1155 * reading the dword at 0x100 which must either be 0 or a valid extended 1156 * reading the dword at 0x100 which must either be 0 or a valid extended
1156 * capability header. 1157 * capability header.
1157 */ 1158 */
1158 int pci_cfg_space_size_ext(struct pci_dev *dev) 1159 int pci_cfg_space_size_ext(struct pci_dev *dev)
1159 { 1160 {
1160 u32 status; 1161 u32 status;
1161 int pos = PCI_CFG_SPACE_SIZE; 1162 int pos = PCI_CFG_SPACE_SIZE;
1162 1163
1163 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1164 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1164 goto fail; 1165 goto fail;
1165 if (status == 0xffffffff) 1166 if (status == 0xffffffff)
1166 goto fail; 1167 goto fail;
1167 1168
1168 return PCI_CFG_SPACE_EXP_SIZE; 1169 return PCI_CFG_SPACE_EXP_SIZE;
1169 1170
1170 fail: 1171 fail:
1171 return PCI_CFG_SPACE_SIZE; 1172 return PCI_CFG_SPACE_SIZE;
1172 } 1173 }
1173 1174
1174 int pci_cfg_space_size(struct pci_dev *dev) 1175 int pci_cfg_space_size(struct pci_dev *dev)
1175 { 1176 {
1176 int pos; 1177 int pos;
1177 u32 status; 1178 u32 status;
1178 u16 class; 1179 u16 class;
1179 1180
1180 class = dev->class >> 8; 1181 class = dev->class >> 8;
1181 if (class == PCI_CLASS_BRIDGE_HOST) 1182 if (class == PCI_CLASS_BRIDGE_HOST)
1182 return pci_cfg_space_size_ext(dev); 1183 return pci_cfg_space_size_ext(dev);
1183 1184
1184 pos = pci_pcie_cap(dev); 1185 pos = pci_pcie_cap(dev);
1185 if (!pos) { 1186 if (!pos) {
1186 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1187 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1187 if (!pos) 1188 if (!pos)
1188 goto fail; 1189 goto fail;
1189 1190
1190 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1191 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1191 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) 1192 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1192 goto fail; 1193 goto fail;
1193 } 1194 }
1194 1195
1195 return pci_cfg_space_size_ext(dev); 1196 return pci_cfg_space_size_ext(dev);
1196 1197
1197 fail: 1198 fail:
1198 return PCI_CFG_SPACE_SIZE; 1199 return PCI_CFG_SPACE_SIZE;
1199 } 1200 }
1200 1201
1201 static void pci_release_bus_bridge_dev(struct device *dev) 1202 static void pci_release_bus_bridge_dev(struct device *dev)
1202 { 1203 {
1203 kfree(dev); 1204 kfree(dev);
1204 } 1205 }
1205 1206
1206 struct pci_dev *alloc_pci_dev(void) 1207 struct pci_dev *alloc_pci_dev(void)
1207 { 1208 {
1208 struct pci_dev *dev; 1209 struct pci_dev *dev;
1209 1210
1210 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 1211 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1211 if (!dev) 1212 if (!dev)
1212 return NULL; 1213 return NULL;
1213 1214
1214 INIT_LIST_HEAD(&dev->bus_list); 1215 INIT_LIST_HEAD(&dev->bus_list);
1215 1216
1216 return dev; 1217 return dev;
1217 } 1218 }
1218 EXPORT_SYMBOL(alloc_pci_dev); 1219 EXPORT_SYMBOL(alloc_pci_dev);
1219 1220
1220 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 1221 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1221 int crs_timeout) 1222 int crs_timeout)
1222 { 1223 {
1223 int delay = 1; 1224 int delay = 1;
1224 1225
1225 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 1226 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1226 return false; 1227 return false;
1227 1228
1228 /* some broken boards return 0 or ~0 if a slot is empty: */ 1229 /* some broken boards return 0 or ~0 if a slot is empty: */
1229 if (*l == 0xffffffff || *l == 0x00000000 || 1230 if (*l == 0xffffffff || *l == 0x00000000 ||
1230 *l == 0x0000ffff || *l == 0xffff0000) 1231 *l == 0x0000ffff || *l == 0xffff0000)
1231 return false; 1232 return false;
1232 1233
1233 /* Configuration request Retry Status */ 1234 /* Configuration request Retry Status */
1234 while (*l == 0xffff0001) { 1235 while (*l == 0xffff0001) {
1235 if (!crs_timeout) 1236 if (!crs_timeout)
1236 return false; 1237 return false;
1237 1238
1238 msleep(delay); 1239 msleep(delay);
1239 delay *= 2; 1240 delay *= 2;
1240 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 1241 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1241 return false; 1242 return false;
1242 /* Card hasn't responded in 60 seconds? Must be stuck. */ 1243 /* Card hasn't responded in 60 seconds? Must be stuck. */
1243 if (delay > crs_timeout) { 1244 if (delay > crs_timeout) {
1244 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " 1245 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1245 "responding\n", pci_domain_nr(bus), 1246 "responding\n", pci_domain_nr(bus),
1246 bus->number, PCI_SLOT(devfn), 1247 bus->number, PCI_SLOT(devfn),
1247 PCI_FUNC(devfn)); 1248 PCI_FUNC(devfn));
1248 return false; 1249 return false;
1249 } 1250 }
1250 } 1251 }
1251 1252
1252 return true; 1253 return true;
1253 } 1254 }
1254 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 1255 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1255 1256
1256 /* 1257 /*
1257 * Read the config data for a PCI device, sanity-check it 1258 * Read the config data for a PCI device, sanity-check it
1258 * and fill in the dev structure... 1259 * and fill in the dev structure...
1259 */ 1260 */
1260 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 1261 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1261 { 1262 {
1262 struct pci_dev *dev; 1263 struct pci_dev *dev;
1263 u32 l; 1264 u32 l;
1264 1265
1265 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 1266 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1266 return NULL; 1267 return NULL;
1267 1268
1268 dev = alloc_pci_dev(); 1269 dev = alloc_pci_dev();
1269 if (!dev) 1270 if (!dev)
1270 return NULL; 1271 return NULL;
1271 1272
1272 dev->bus = bus; 1273 dev->bus = bus;
1273 dev->devfn = devfn; 1274 dev->devfn = devfn;
1274 dev->vendor = l & 0xffff; 1275 dev->vendor = l & 0xffff;
1275 dev->device = (l >> 16) & 0xffff; 1276 dev->device = (l >> 16) & 0xffff;
1276 1277
1277 pci_set_of_node(dev); 1278 pci_set_of_node(dev);
1278 1279
1279 if (pci_setup_device(dev)) { 1280 if (pci_setup_device(dev)) {
1280 kfree(dev); 1281 kfree(dev);
1281 return NULL; 1282 return NULL;
1282 } 1283 }
1283 1284
1284 return dev; 1285 return dev;
1285 } 1286 }
1286 1287
1287 static void pci_init_capabilities(struct pci_dev *dev) 1288 static void pci_init_capabilities(struct pci_dev *dev)
1288 { 1289 {
1289 /* MSI/MSI-X list */ 1290 /* MSI/MSI-X list */
1290 pci_msi_init_pci_dev(dev); 1291 pci_msi_init_pci_dev(dev);
1291 1292
1292 /* Buffers for saving PCIe and PCI-X capabilities */ 1293 /* Buffers for saving PCIe and PCI-X capabilities */
1293 pci_allocate_cap_save_buffers(dev); 1294 pci_allocate_cap_save_buffers(dev);
1294 1295
1295 /* Power Management */ 1296 /* Power Management */
1296 pci_pm_init(dev); 1297 pci_pm_init(dev);
1297 platform_pci_wakeup_init(dev); 1298 platform_pci_wakeup_init(dev);
1298 1299
1299 /* Vital Product Data */ 1300 /* Vital Product Data */
1300 pci_vpd_pci22_init(dev); 1301 pci_vpd_pci22_init(dev);
1301 1302
1302 /* Alternative Routing-ID Forwarding */ 1303 /* Alternative Routing-ID Forwarding */
1303 pci_enable_ari(dev); 1304 pci_enable_ari(dev);
1304 1305
1305 /* Single Root I/O Virtualization */ 1306 /* Single Root I/O Virtualization */
1306 pci_iov_init(dev); 1307 pci_iov_init(dev);
1307 1308
1308 /* Enable ACS P2P upstream forwarding */ 1309 /* Enable ACS P2P upstream forwarding */
1309 pci_enable_acs(dev); 1310 pci_enable_acs(dev);
1310 } 1311 }
1311 1312
1312 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 1313 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1313 { 1314 {
1314 device_initialize(&dev->dev); 1315 device_initialize(&dev->dev);
1315 dev->dev.release = pci_release_dev; 1316 dev->dev.release = pci_release_dev;
1316 pci_dev_get(dev); 1317 pci_dev_get(dev);
1317 1318
1318 dev->dev.dma_mask = &dev->dma_mask; 1319 dev->dev.dma_mask = &dev->dma_mask;
1319 dev->dev.dma_parms = &dev->dma_parms; 1320 dev->dev.dma_parms = &dev->dma_parms;
1320 dev->dev.coherent_dma_mask = 0xffffffffull; 1321 dev->dev.coherent_dma_mask = 0xffffffffull;
1321 1322
1322 pci_set_dma_max_seg_size(dev, 65536); 1323 pci_set_dma_max_seg_size(dev, 65536);
1323 pci_set_dma_seg_boundary(dev, 0xffffffff); 1324 pci_set_dma_seg_boundary(dev, 0xffffffff);
1324 1325
1325 /* Fix up broken headers */ 1326 /* Fix up broken headers */
1326 pci_fixup_device(pci_fixup_header, dev); 1327 pci_fixup_device(pci_fixup_header, dev);
1327 1328
1328 /* moved out from quirk header fixup code */ 1329 /* moved out from quirk header fixup code */
1329 pci_reassigndev_resource_alignment(dev); 1330 pci_reassigndev_resource_alignment(dev);
1330 1331
1331 /* Clear the state_saved flag. */ 1332 /* Clear the state_saved flag. */
1332 dev->state_saved = false; 1333 dev->state_saved = false;
1333 1334
1334 /* Initialize various capabilities */ 1335 /* Initialize various capabilities */
1335 pci_init_capabilities(dev); 1336 pci_init_capabilities(dev);
1336 1337
1337 /* 1338 /*
1338 * Add the device to our list of discovered devices 1339 * Add the device to our list of discovered devices
1339 * and the bus list for fixup functions, etc. 1340 * and the bus list for fixup functions, etc.
1340 */ 1341 */
1341 down_write(&pci_bus_sem); 1342 down_write(&pci_bus_sem);
1342 list_add_tail(&dev->bus_list, &bus->devices); 1343 list_add_tail(&dev->bus_list, &bus->devices);
1343 up_write(&pci_bus_sem); 1344 up_write(&pci_bus_sem);
1344 } 1345 }
1345 1346
1346 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) 1347 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1347 { 1348 {
1348 struct pci_dev *dev; 1349 struct pci_dev *dev;
1349 1350
1350 dev = pci_get_slot(bus, devfn); 1351 dev = pci_get_slot(bus, devfn);
1351 if (dev) { 1352 if (dev) {
1352 pci_dev_put(dev); 1353 pci_dev_put(dev);
1353 return dev; 1354 return dev;
1354 } 1355 }
1355 1356
1356 dev = pci_scan_device(bus, devfn); 1357 dev = pci_scan_device(bus, devfn);
1357 if (!dev) 1358 if (!dev)
1358 return NULL; 1359 return NULL;
1359 1360
1360 pci_device_add(dev, bus); 1361 pci_device_add(dev, bus);
1361 1362
1362 return dev; 1363 return dev;
1363 } 1364 }
1364 EXPORT_SYMBOL(pci_scan_single_device); 1365 EXPORT_SYMBOL(pci_scan_single_device);
1365 1366
1366 static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn) 1367 static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1367 { 1368 {
1368 u16 cap; 1369 u16 cap;
1369 unsigned pos, next_fn; 1370 unsigned pos, next_fn;
1370 1371
1371 if (!dev) 1372 if (!dev)
1372 return 0; 1373 return 0;
1373 1374
1374 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 1375 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1375 if (!pos) 1376 if (!pos)
1376 return 0; 1377 return 0;
1377 pci_read_config_word(dev, pos + 4, &cap); 1378 pci_read_config_word(dev, pos + 4, &cap);
1378 next_fn = cap >> 8; 1379 next_fn = cap >> 8;
1379 if (next_fn <= fn) 1380 if (next_fn <= fn)
1380 return 0; 1381 return 0;
1381 return next_fn; 1382 return next_fn;
1382 } 1383 }
1383 1384
1384 static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn) 1385 static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1385 { 1386 {
1386 return (fn + 1) % 8; 1387 return (fn + 1) % 8;
1387 } 1388 }
1388 1389
1389 static unsigned no_next_fn(struct pci_dev *dev, unsigned fn) 1390 static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1390 { 1391 {
1391 return 0; 1392 return 0;
1392 } 1393 }
1393 1394
1394 static int only_one_child(struct pci_bus *bus) 1395 static int only_one_child(struct pci_bus *bus)
1395 { 1396 {
1396 struct pci_dev *parent = bus->self; 1397 struct pci_dev *parent = bus->self;
1397 if (!parent || !pci_is_pcie(parent)) 1398 if (!parent || !pci_is_pcie(parent))
1398 return 0; 1399 return 0;
1399 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT || 1400 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1400 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) 1401 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1401 return 1; 1402 return 1;
1402 return 0; 1403 return 0;
1403 } 1404 }
1404 1405
1405 /** 1406 /**
1406 * pci_scan_slot - scan a PCI slot on a bus for devices. 1407 * pci_scan_slot - scan a PCI slot on a bus for devices.
1407 * @bus: PCI bus to scan 1408 * @bus: PCI bus to scan
1408 * @devfn: slot number to scan (must have zero function.) 1409 * @devfn: slot number to scan (must have zero function.)
1409 * 1410 *
1410 * Scan a PCI slot on the specified PCI bus for devices, adding 1411 * Scan a PCI slot on the specified PCI bus for devices, adding
1411 * discovered devices to the @bus->devices list. New devices 1412 * discovered devices to the @bus->devices list. New devices
1412 * will not have is_added set. 1413 * will not have is_added set.
1413 * 1414 *
1414 * Returns the number of new devices found. 1415 * Returns the number of new devices found.
1415 */ 1416 */
1416 int pci_scan_slot(struct pci_bus *bus, int devfn) 1417 int pci_scan_slot(struct pci_bus *bus, int devfn)
1417 { 1418 {
1418 unsigned fn, nr = 0; 1419 unsigned fn, nr = 0;
1419 struct pci_dev *dev; 1420 struct pci_dev *dev;
1420 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn; 1421 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1421 1422
1422 if (only_one_child(bus) && (devfn > 0)) 1423 if (only_one_child(bus) && (devfn > 0))
1423 return 0; /* Already scanned the entire slot */ 1424 return 0; /* Already scanned the entire slot */
1424 1425
1425 dev = pci_scan_single_device(bus, devfn); 1426 dev = pci_scan_single_device(bus, devfn);
1426 if (!dev) 1427 if (!dev)
1427 return 0; 1428 return 0;
1428 if (!dev->is_added) 1429 if (!dev->is_added)
1429 nr++; 1430 nr++;
1430 1431
1431 if (pci_ari_enabled(bus)) 1432 if (pci_ari_enabled(bus))
1432 next_fn = next_ari_fn; 1433 next_fn = next_ari_fn;
1433 else if (dev->multifunction) 1434 else if (dev->multifunction)
1434 next_fn = next_trad_fn; 1435 next_fn = next_trad_fn;
1435 1436
1436 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) { 1437 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1437 dev = pci_scan_single_device(bus, devfn + fn); 1438 dev = pci_scan_single_device(bus, devfn + fn);
1438 if (dev) { 1439 if (dev) {
1439 if (!dev->is_added) 1440 if (!dev->is_added)
1440 nr++; 1441 nr++;
1441 dev->multifunction = 1; 1442 dev->multifunction = 1;
1442 } 1443 }
1443 } 1444 }
1444 1445
1445 /* only one slot has pcie device */ 1446 /* only one slot has pcie device */
1446 if (bus->self && nr) 1447 if (bus->self && nr)
1447 pcie_aspm_init_link_state(bus->self); 1448 pcie_aspm_init_link_state(bus->self);
1448 1449
1449 return nr; 1450 return nr;
1450 } 1451 }
1451 1452
1452 static int pcie_find_smpss(struct pci_dev *dev, void *data) 1453 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1453 { 1454 {
1454 u8 *smpss = data; 1455 u8 *smpss = data;
1455 1456
1456 if (!pci_is_pcie(dev)) 1457 if (!pci_is_pcie(dev))
1457 return 0; 1458 return 0;
1458 1459
1459 /* For PCIE hotplug enabled slots not connected directly to a 1460 /* For PCIE hotplug enabled slots not connected directly to a
1460 * PCI-E root port, there can be problems when hotplugging 1461 * PCI-E root port, there can be problems when hotplugging
1461 * devices. This is due to the possibility of hotplugging a 1462 * devices. This is due to the possibility of hotplugging a
1462 * device into the fabric with a smaller MPS that the devices 1463 * device into the fabric with a smaller MPS that the devices
1463 * currently running have configured. Modifying the MPS on the 1464 * currently running have configured. Modifying the MPS on the
1464 * running devices could cause a fatal bus error due to an 1465 * running devices could cause a fatal bus error due to an
1465 * incoming frame being larger than the newly configured MPS. 1466 * incoming frame being larger than the newly configured MPS.
1466 * To work around this, the MPS for the entire fabric must be 1467 * To work around this, the MPS for the entire fabric must be
1467 * set to the minimum size. Any devices hotplugged into this 1468 * set to the minimum size. Any devices hotplugged into this
1468 * fabric will have the minimum MPS set. If the PCI hotplug 1469 * fabric will have the minimum MPS set. If the PCI hotplug
1469 * slot is directly connected to the root port and there are not 1470 * slot is directly connected to the root port and there are not
1470 * other devices on the fabric (which seems to be the most 1471 * other devices on the fabric (which seems to be the most
1471 * common case), then this is not an issue and MPS discovery 1472 * common case), then this is not an issue and MPS discovery
1472 * will occur as normal. 1473 * will occur as normal.
1473 */ 1474 */
1474 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) || 1475 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
1475 (dev->bus->self && 1476 (dev->bus->self &&
1476 dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT))) 1477 dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)))
1477 *smpss = 0; 1478 *smpss = 0;
1478 1479
1479 if (*smpss > dev->pcie_mpss) 1480 if (*smpss > dev->pcie_mpss)
1480 *smpss = dev->pcie_mpss; 1481 *smpss = dev->pcie_mpss;
1481 1482
1482 return 0; 1483 return 0;
1483 } 1484 }
1484 1485
1485 static void pcie_write_mps(struct pci_dev *dev, int mps) 1486 static void pcie_write_mps(struct pci_dev *dev, int mps)
1486 { 1487 {
1487 int rc; 1488 int rc;
1488 1489
1489 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 1490 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1490 mps = 128 << dev->pcie_mpss; 1491 mps = 128 << dev->pcie_mpss;
1491 1492
1492 if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self) 1493 if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self)
1493 /* For "Performance", the assumption is made that 1494 /* For "Performance", the assumption is made that
1494 * downstream communication will never be larger than 1495 * downstream communication will never be larger than
1495 * the MRRS. So, the MPS only needs to be configured 1496 * the MRRS. So, the MPS only needs to be configured
1496 * for the upstream communication. This being the case, 1497 * for the upstream communication. This being the case,
1497 * walk from the top down and set the MPS of the child 1498 * walk from the top down and set the MPS of the child
1498 * to that of the parent bus. 1499 * to that of the parent bus.
1499 * 1500 *
1500 * Configure the device MPS with the smaller of the 1501 * Configure the device MPS with the smaller of the
1501 * device MPSS or the bridge MPS (which is assumed to be 1502 * device MPSS or the bridge MPS (which is assumed to be
1502 * properly configured at this point to the largest 1503 * properly configured at this point to the largest
1503 * allowable MPS based on its parent bus). 1504 * allowable MPS based on its parent bus).
1504 */ 1505 */
1505 mps = min(mps, pcie_get_mps(dev->bus->self)); 1506 mps = min(mps, pcie_get_mps(dev->bus->self));
1506 } 1507 }
1507 1508
1508 rc = pcie_set_mps(dev, mps); 1509 rc = pcie_set_mps(dev, mps);
1509 if (rc) 1510 if (rc)
1510 dev_err(&dev->dev, "Failed attempting to set the MPS\n"); 1511 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1511 } 1512 }
1512 1513
1513 static void pcie_write_mrrs(struct pci_dev *dev) 1514 static void pcie_write_mrrs(struct pci_dev *dev)
1514 { 1515 {
1515 int rc, mrrs; 1516 int rc, mrrs;
1516 1517
1517 /* In the "safe" case, do not configure the MRRS. There appear to be 1518 /* In the "safe" case, do not configure the MRRS. There appear to be
1518 * issues with setting MRRS to 0 on a number of devices. 1519 * issues with setting MRRS to 0 on a number of devices.
1519 */ 1520 */
1520 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 1521 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1521 return; 1522 return;
1522 1523
1523 /* For Max performance, the MRRS must be set to the largest supported 1524 /* For Max performance, the MRRS must be set to the largest supported
1524 * value. However, it cannot be configured larger than the MPS the 1525 * value. However, it cannot be configured larger than the MPS the
1525 * device or the bus can support. This should already be properly 1526 * device or the bus can support. This should already be properly
1526 * configured by a prior call to pcie_write_mps. 1527 * configured by a prior call to pcie_write_mps.
1527 */ 1528 */
1528 mrrs = pcie_get_mps(dev); 1529 mrrs = pcie_get_mps(dev);
1529 1530
1530 /* MRRS is a R/W register. Invalid values can be written, but a 1531 /* MRRS is a R/W register. Invalid values can be written, but a
1531 * subsequent read will verify if the value is acceptable or not. 1532 * subsequent read will verify if the value is acceptable or not.
1532 * If the MRRS value provided is not acceptable (e.g., too large), 1533 * If the MRRS value provided is not acceptable (e.g., too large),
1533 * shrink the value until it is acceptable to the HW. 1534 * shrink the value until it is acceptable to the HW.
1534 */ 1535 */
1535 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 1536 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1536 rc = pcie_set_readrq(dev, mrrs); 1537 rc = pcie_set_readrq(dev, mrrs);
1537 if (!rc) 1538 if (!rc)
1538 break; 1539 break;
1539 1540
1540 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n"); 1541 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1541 mrrs /= 2; 1542 mrrs /= 2;
1542 } 1543 }
1543 1544
1544 if (mrrs < 128) 1545 if (mrrs < 128)
1545 dev_err(&dev->dev, "MRRS was unable to be configured with a " 1546 dev_err(&dev->dev, "MRRS was unable to be configured with a "
1546 "safe value. If problems are experienced, try running " 1547 "safe value. If problems are experienced, try running "
1547 "with pci=pcie_bus_safe.\n"); 1548 "with pci=pcie_bus_safe.\n");
1548 } 1549 }
1549 1550
1550 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 1551 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1551 { 1552 {
1552 int mps, orig_mps; 1553 int mps, orig_mps;
1553 1554
1554 if (!pci_is_pcie(dev)) 1555 if (!pci_is_pcie(dev))
1555 return 0; 1556 return 0;
1556 1557
1557 mps = 128 << *(u8 *)data; 1558 mps = 128 << *(u8 *)data;
1558 orig_mps = pcie_get_mps(dev); 1559 orig_mps = pcie_get_mps(dev);
1559 1560
1560 pcie_write_mps(dev, mps); 1561 pcie_write_mps(dev, mps);
1561 pcie_write_mrrs(dev); 1562 pcie_write_mrrs(dev);
1562 1563
1563 dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), " 1564 dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), "
1564 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss, 1565 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
1565 orig_mps, pcie_get_readrq(dev)); 1566 orig_mps, pcie_get_readrq(dev));
1566 1567
1567 return 0; 1568 return 0;
1568 } 1569 }
1569 1570
1570 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, 1571 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1571 * parents then children fashion. If this changes, then this code will not 1572 * parents then children fashion. If this changes, then this code will not
1572 * work as designed. 1573 * work as designed.
1573 */ 1574 */
1574 void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss) 1575 void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1575 { 1576 {
1576 u8 smpss; 1577 u8 smpss;
1577 1578
1578 if (!pci_is_pcie(bus->self)) 1579 if (!pci_is_pcie(bus->self))
1579 return; 1580 return;
1580 1581
1581 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) 1582 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1582 return; 1583 return;
1583 1584
1584 /* FIXME - Peer to peer DMA is possible, though the endpoint would need 1585 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1585 * to be aware to the MPS of the destination. To work around this, 1586 * to be aware to the MPS of the destination. To work around this,
1586 * simply force the MPS of the entire system to the smallest possible. 1587 * simply force the MPS of the entire system to the smallest possible.
1587 */ 1588 */
1588 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 1589 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1589 smpss = 0; 1590 smpss = 0;
1590 1591
1591 if (pcie_bus_config == PCIE_BUS_SAFE) { 1592 if (pcie_bus_config == PCIE_BUS_SAFE) {
1592 smpss = mpss; 1593 smpss = mpss;
1593 1594
1594 pcie_find_smpss(bus->self, &smpss); 1595 pcie_find_smpss(bus->self, &smpss);
1595 pci_walk_bus(bus, pcie_find_smpss, &smpss); 1596 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1596 } 1597 }
1597 1598
1598 pcie_bus_configure_set(bus->self, &smpss); 1599 pcie_bus_configure_set(bus->self, &smpss);
1599 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 1600 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1600 } 1601 }
1601 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 1602 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1602 1603
1603 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) 1604 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1604 { 1605 {
1605 unsigned int devfn, pass, max = bus->secondary; 1606 unsigned int devfn, pass, max = bus->secondary;
1606 struct pci_dev *dev; 1607 struct pci_dev *dev;
1607 1608
1608 dev_dbg(&bus->dev, "scanning bus\n"); 1609 dev_dbg(&bus->dev, "scanning bus\n");
1609 1610
1610 /* Go find them, Rover! */ 1611 /* Go find them, Rover! */
1611 for (devfn = 0; devfn < 0x100; devfn += 8) 1612 for (devfn = 0; devfn < 0x100; devfn += 8)
1612 pci_scan_slot(bus, devfn); 1613 pci_scan_slot(bus, devfn);
1613 1614
1614 /* Reserve buses for SR-IOV capability. */ 1615 /* Reserve buses for SR-IOV capability. */
1615 max += pci_iov_bus_range(bus); 1616 max += pci_iov_bus_range(bus);
1616 1617
1617 /* 1618 /*
1618 * After performing arch-dependent fixup of the bus, look behind 1619 * After performing arch-dependent fixup of the bus, look behind
1619 * all PCI-to-PCI bridges on this bus. 1620 * all PCI-to-PCI bridges on this bus.
1620 */ 1621 */
1621 if (!bus->is_added) { 1622 if (!bus->is_added) {
1622 dev_dbg(&bus->dev, "fixups for bus\n"); 1623 dev_dbg(&bus->dev, "fixups for bus\n");
1623 pcibios_fixup_bus(bus); 1624 pcibios_fixup_bus(bus);
1624 if (pci_is_root_bus(bus)) 1625 if (pci_is_root_bus(bus))
1625 bus->is_added = 1; 1626 bus->is_added = 1;
1626 } 1627 }
1627 1628
1628 for (pass=0; pass < 2; pass++) 1629 for (pass=0; pass < 2; pass++)
1629 list_for_each_entry(dev, &bus->devices, bus_list) { 1630 list_for_each_entry(dev, &bus->devices, bus_list) {
1630 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1631 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1631 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 1632 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1632 max = pci_scan_bridge(bus, dev, max, pass); 1633 max = pci_scan_bridge(bus, dev, max, pass);
1633 } 1634 }
1634 1635
1635 /* 1636 /*
1636 * We've scanned the bus and so we know all about what's on 1637 * We've scanned the bus and so we know all about what's on
1637 * the other side of any bridges that may be on this bus plus 1638 * the other side of any bridges that may be on this bus plus
1638 * any devices. 1639 * any devices.
1639 * 1640 *
1640 * Return how far we've got finding sub-buses. 1641 * Return how far we've got finding sub-buses.
1641 */ 1642 */
1642 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 1643 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1643 return max; 1644 return max;
1644 } 1645 }
1645 1646
1646 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1647 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1647 struct pci_ops *ops, void *sysdata, struct list_head *resources) 1648 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1648 { 1649 {
1649 int error; 1650 int error;
1650 struct pci_host_bridge *bridge; 1651 struct pci_host_bridge *bridge;
1651 struct pci_bus *b, *b2; 1652 struct pci_bus *b, *b2;
1652 struct device *dev; 1653 struct device *dev;
1653 struct pci_host_bridge_window *window, *n; 1654 struct pci_host_bridge_window *window, *n;
1654 struct resource *res; 1655 struct resource *res;
1655 resource_size_t offset; 1656 resource_size_t offset;
1656 char bus_addr[64]; 1657 char bus_addr[64];
1657 char *fmt; 1658 char *fmt;
1658 1659
1659 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL); 1660 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
1660 if (!bridge) 1661 if (!bridge)
1661 return NULL; 1662 return NULL;
1662 1663
1663 b = pci_alloc_bus(); 1664 b = pci_alloc_bus();
1664 if (!b) 1665 if (!b)
1665 goto err_bus; 1666 goto err_bus;
1666 1667
1667 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1668 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1668 if (!dev) 1669 if (!dev)
1669 goto err_dev; 1670 goto err_dev;
1670 1671
1671 b->sysdata = sysdata; 1672 b->sysdata = sysdata;
1672 b->ops = ops; 1673 b->ops = ops;
1673 1674
1674 b2 = pci_find_bus(pci_domain_nr(b), bus); 1675 b2 = pci_find_bus(pci_domain_nr(b), bus);
1675 if (b2) { 1676 if (b2) {
1676 /* If we already got to this bus through a different bridge, ignore it */ 1677 /* If we already got to this bus through a different bridge, ignore it */
1677 dev_dbg(&b2->dev, "bus already known\n"); 1678 dev_dbg(&b2->dev, "bus already known\n");
1678 goto err_out; 1679 goto err_out;
1679 } 1680 }
1680 1681
1681 dev->parent = parent; 1682 dev->parent = parent;
1682 dev->release = pci_release_bus_bridge_dev; 1683 dev->release = pci_release_bus_bridge_dev;
1683 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus); 1684 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1684 error = device_register(dev); 1685 error = device_register(dev);
1685 if (error) 1686 if (error)
1686 goto dev_reg_err; 1687 goto dev_reg_err;
1687 b->bridge = get_device(dev); 1688 b->bridge = get_device(dev);
1688 device_enable_async_suspend(b->bridge); 1689 device_enable_async_suspend(b->bridge);
1689 pci_set_bus_of_node(b); 1690 pci_set_bus_of_node(b);
1690 1691
1691 if (!parent) 1692 if (!parent)
1692 set_dev_node(b->bridge, pcibus_to_node(b)); 1693 set_dev_node(b->bridge, pcibus_to_node(b));
1693 1694
1694 b->dev.class = &pcibus_class; 1695 b->dev.class = &pcibus_class;
1695 b->dev.parent = b->bridge; 1696 b->dev.parent = b->bridge;
1696 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); 1697 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1697 error = device_register(&b->dev); 1698 error = device_register(&b->dev);
1698 if (error) 1699 if (error)
1699 goto class_dev_reg_err; 1700 goto class_dev_reg_err;
1700 1701
1701 /* Create legacy_io and legacy_mem files for this bus */ 1702 /* Create legacy_io and legacy_mem files for this bus */
1702 pci_create_legacy_files(b); 1703 pci_create_legacy_files(b);
1703 1704
1704 b->number = b->secondary = bus; 1705 b->number = b->secondary = bus;
1705 1706
1706 bridge->bus = b; 1707 bridge->bus = b;
1707 INIT_LIST_HEAD(&bridge->windows); 1708 INIT_LIST_HEAD(&bridge->windows);
1708 1709
1709 if (parent) 1710 if (parent)
1710 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev)); 1711 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1711 else 1712 else
1712 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev)); 1713 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1713 1714
1714 /* Add initial resources to the bus */ 1715 /* Add initial resources to the bus */
1715 list_for_each_entry_safe(window, n, resources, list) { 1716 list_for_each_entry_safe(window, n, resources, list) {
1716 list_move_tail(&window->list, &bridge->windows); 1717 list_move_tail(&window->list, &bridge->windows);
1717 res = window->res; 1718 res = window->res;
1718 offset = window->offset; 1719 offset = window->offset;
1719 pci_bus_add_resource(b, res, 0); 1720 pci_bus_add_resource(b, res, 0);
1720 if (offset) { 1721 if (offset) {
1721 if (resource_type(res) == IORESOURCE_IO) 1722 if (resource_type(res) == IORESOURCE_IO)
1722 fmt = " (bus address [%#06llx-%#06llx])"; 1723 fmt = " (bus address [%#06llx-%#06llx])";
1723 else 1724 else
1724 fmt = " (bus address [%#010llx-%#010llx])"; 1725 fmt = " (bus address [%#010llx-%#010llx])";
1725 snprintf(bus_addr, sizeof(bus_addr), fmt, 1726 snprintf(bus_addr, sizeof(bus_addr), fmt,
1726 (unsigned long long) (res->start - offset), 1727 (unsigned long long) (res->start - offset),
1727 (unsigned long long) (res->end - offset)); 1728 (unsigned long long) (res->end - offset));
1728 } else 1729 } else
1729 bus_addr[0] = '\0'; 1730 bus_addr[0] = '\0';
1730 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr); 1731 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
1731 } 1732 }
1732 1733
1733 down_write(&pci_bus_sem); 1734 down_write(&pci_bus_sem);
1734 list_add_tail(&bridge->list, &pci_host_bridges); 1735 list_add_tail(&bridge->list, &pci_host_bridges);
1735 list_add_tail(&b->node, &pci_root_buses); 1736 list_add_tail(&b->node, &pci_root_buses);
1736 up_write(&pci_bus_sem); 1737 up_write(&pci_bus_sem);
1737 1738
1738 return b; 1739 return b;
1739 1740
1740 class_dev_reg_err: 1741 class_dev_reg_err:
1741 device_unregister(dev); 1742 device_unregister(dev);
1742 dev_reg_err: 1743 dev_reg_err:
1743 down_write(&pci_bus_sem); 1744 down_write(&pci_bus_sem);
1744 list_del(&bridge->list); 1745 list_del(&bridge->list);
1745 list_del(&b->node); 1746 list_del(&b->node);
1746 up_write(&pci_bus_sem); 1747 up_write(&pci_bus_sem);
1747 err_out: 1748 err_out:
1748 kfree(dev); 1749 kfree(dev);
1749 err_dev: 1750 err_dev:
1750 kfree(b); 1751 kfree(b);
1751 err_bus: 1752 err_bus:
1752 kfree(bridge); 1753 kfree(bridge);
1753 return NULL; 1754 return NULL;
1754 } 1755 }
1755 1756
1756 struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus, 1757 struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
1757 struct pci_ops *ops, void *sysdata, struct list_head *resources) 1758 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1758 { 1759 {
1759 struct pci_bus *b; 1760 struct pci_bus *b;
1760 1761
1761 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 1762 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
1762 if (!b) 1763 if (!b)
1763 return NULL; 1764 return NULL;
1764 1765
1765 b->subordinate = pci_scan_child_bus(b); 1766 b->subordinate = pci_scan_child_bus(b);
1766 pci_bus_add_devices(b); 1767 pci_bus_add_devices(b);
1767 return b; 1768 return b;
1768 } 1769 }
1769 EXPORT_SYMBOL(pci_scan_root_bus); 1770 EXPORT_SYMBOL(pci_scan_root_bus);
1770 1771
1771 /* Deprecated; use pci_scan_root_bus() instead */ 1772 /* Deprecated; use pci_scan_root_bus() instead */
1772 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, 1773 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1773 int bus, struct pci_ops *ops, void *sysdata) 1774 int bus, struct pci_ops *ops, void *sysdata)
1774 { 1775 {
1775 LIST_HEAD(resources); 1776 LIST_HEAD(resources);
1776 struct pci_bus *b; 1777 struct pci_bus *b;
1777 1778
1778 pci_add_resource(&resources, &ioport_resource); 1779 pci_add_resource(&resources, &ioport_resource);
1779 pci_add_resource(&resources, &iomem_resource); 1780 pci_add_resource(&resources, &iomem_resource);
1780 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources); 1781 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
1781 if (b) 1782 if (b)
1782 b->subordinate = pci_scan_child_bus(b); 1783 b->subordinate = pci_scan_child_bus(b);
1783 else 1784 else
1784 pci_free_resource_list(&resources); 1785 pci_free_resource_list(&resources);
1785 return b; 1786 return b;
1786 } 1787 }
1787 EXPORT_SYMBOL(pci_scan_bus_parented); 1788 EXPORT_SYMBOL(pci_scan_bus_parented);
1788 1789
1789 struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, 1790 struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
1790 void *sysdata) 1791 void *sysdata)
1791 { 1792 {
1792 LIST_HEAD(resources); 1793 LIST_HEAD(resources);
1793 struct pci_bus *b; 1794 struct pci_bus *b;
1794 1795
1795 pci_add_resource(&resources, &ioport_resource); 1796 pci_add_resource(&resources, &ioport_resource);
1796 pci_add_resource(&resources, &iomem_resource); 1797 pci_add_resource(&resources, &iomem_resource);
1797 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 1798 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
1798 if (b) { 1799 if (b) {
1799 b->subordinate = pci_scan_child_bus(b); 1800 b->subordinate = pci_scan_child_bus(b);
1800 pci_bus_add_devices(b); 1801 pci_bus_add_devices(b);
1801 } else { 1802 } else {
1802 pci_free_resource_list(&resources); 1803 pci_free_resource_list(&resources);
1803 } 1804 }
1804 return b; 1805 return b;
1805 } 1806 }
1806 EXPORT_SYMBOL(pci_scan_bus); 1807 EXPORT_SYMBOL(pci_scan_bus);
1807 1808
1808 #ifdef CONFIG_HOTPLUG 1809 #ifdef CONFIG_HOTPLUG
1809 /** 1810 /**
1810 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices. 1811 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
1811 * @bridge: PCI bridge for the bus to scan 1812 * @bridge: PCI bridge for the bus to scan
1812 * 1813 *
1813 * Scan a PCI bus and child buses for new devices, add them, 1814 * Scan a PCI bus and child buses for new devices, add them,
1814 * and enable them, resizing bridge mmio/io resource if necessary 1815 * and enable them, resizing bridge mmio/io resource if necessary
1815 * and possible. The caller must ensure the child devices are already 1816 * and possible. The caller must ensure the child devices are already
1816 * removed for resizing to occur. 1817 * removed for resizing to occur.
1817 * 1818 *
1818 * Returns the max number of subordinate bus discovered. 1819 * Returns the max number of subordinate bus discovered.
1819 */ 1820 */
1820 unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 1821 unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
1821 { 1822 {
1822 unsigned int max; 1823 unsigned int max;
1823 struct pci_bus *bus = bridge->subordinate; 1824 struct pci_bus *bus = bridge->subordinate;
1824 1825
1825 max = pci_scan_child_bus(bus); 1826 max = pci_scan_child_bus(bus);
1826 1827
1827 pci_assign_unassigned_bridge_resources(bridge); 1828 pci_assign_unassigned_bridge_resources(bridge);
1828 1829
1829 pci_bus_add_devices(bus); 1830 pci_bus_add_devices(bus);
1830 1831
1831 return max; 1832 return max;
1832 } 1833 }
1833 1834
1834 EXPORT_SYMBOL(pci_add_new_bus); 1835 EXPORT_SYMBOL(pci_add_new_bus);
1835 EXPORT_SYMBOL(pci_scan_slot); 1836 EXPORT_SYMBOL(pci_scan_slot);
1836 EXPORT_SYMBOL(pci_scan_bridge); 1837 EXPORT_SYMBOL(pci_scan_bridge);
1837 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 1838 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1838 #endif 1839 #endif
1839 1840
1840 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) 1841 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1841 { 1842 {
1842 const struct pci_dev *a = to_pci_dev(d_a); 1843 const struct pci_dev *a = to_pci_dev(d_a);
1843 const struct pci_dev *b = to_pci_dev(d_b); 1844 const struct pci_dev *b = to_pci_dev(d_b);
1844 1845
1845 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 1846 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1846 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 1847 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1847 1848
1848 if (a->bus->number < b->bus->number) return -1; 1849 if (a->bus->number < b->bus->number) return -1;
1849 else if (a->bus->number > b->bus->number) return 1; 1850 else if (a->bus->number > b->bus->number) return 1;
1850 1851
1851 if (a->devfn < b->devfn) return -1; 1852 if (a->devfn < b->devfn) return -1;
1852 else if (a->devfn > b->devfn) return 1; 1853 else if (a->devfn > b->devfn) return 1;
1853 1854
1854 return 0; 1855 return 0;
1855 } 1856 }
1856 1857
1857 void __init pci_sort_breadthfirst(void) 1858 void __init pci_sort_breadthfirst(void)
1858 { 1859 {
1859 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 1860 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1860 } 1861 }
1861 1862