Doug / smarc-fsl-linux-kernel | Embedian Git Server

Commit d4be4f37d9d2a5afc8e79a95beafbac4b83f20c5

Authored by Stephen Rothwell 2005-11-09 13:19:53 +0800

Exists in master and in 7 other branches

ppc64: remove ppc_irq_dispatch_handler

Use __do_IRQ instead. The only difference is that every controller
is now assumed to have an end() routine (only xics_8259 did not).

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>

Showing 7 changed files with 12 additions and 118 deletions Inline Diff

arch/powerpc/kernel/misc_64.S
arch/powerpc/platforms/iseries/irq.c
arch/powerpc/platforms/pseries/xics.c
arch/ppc64/kernel/irq.c
arch/ppc64/kernel/misc.S
include/asm-powerpc/hw_irq.h
include/asm-powerpc/irq.h

arch/powerpc/kernel/misc_64.S

Diff comments View file @ d4be4f3

1	/*	1	/*
2	* arch/powerpc/kernel/misc64.S	2	* arch/powerpc/kernel/misc64.S
3	*	3	*
4	* This file contains miscellaneous low-level functions.	4	* This file contains miscellaneous low-level functions.
5	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)	5	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6	*	6	*
7	* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)	7	* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
8	* and Paul Mackerras.	8	* and Paul Mackerras.
9	* Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)	9	* Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
10	* PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)	10	* PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
11	*	11	*
12	* This program is free software; you can redistribute it and/or	12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License	13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation; either version	14	* as published by the Free Software Foundation; either version
15	* 2 of the License, or (at your option) any later version.	15	* 2 of the License, or (at your option) any later version.
16	*	16	*
17	*/	17	*/
18		18
19	#include <linux/config.h>	19	#include <linux/config.h>
20	#include <linux/sys.h>	20	#include <linux/sys.h>
21	#include <asm/unistd.h>	21	#include <asm/unistd.h>
22	#include <asm/errno.h>	22	#include <asm/errno.h>
23	#include <asm/processor.h>	23	#include <asm/processor.h>
24	#include <asm/page.h>	24	#include <asm/page.h>
25	#include <asm/cache.h>	25	#include <asm/cache.h>
26	#include <asm/ppc_asm.h>	26	#include <asm/ppc_asm.h>
27	#include <asm/asm-offsets.h>	27	#include <asm/asm-offsets.h>
28	#include <asm/cputable.h>	28	#include <asm/cputable.h>
29	#include <asm/thread_info.h>	29	#include <asm/thread_info.h>
30		30
31	.text	31	.text
32		32
33	/*	33	/*
34	* Returns (address we are running at) - (address we were linked at)	34	* Returns (address we are running at) - (address we were linked at)
35	* for use before the text and data are mapped to KERNELBASE.	35	* for use before the text and data are mapped to KERNELBASE.
36	*/	36	*/
37		37
38	_GLOBAL(reloc_offset)	38	_GLOBAL(reloc_offset)
39	mflr r0	39	mflr r0
40	bl 1f	40	bl 1f
41	1: mflr r3	41	1: mflr r3
42	LOADADDR(r4,1b)	42	LOADADDR(r4,1b)
43	subf r3,r4,r3	43	subf r3,r4,r3
44	mtlr r0	44	mtlr r0
45	blr	45	blr
46		46
47	/*	47	/*
48	* add_reloc_offset(x) returns x + reloc_offset().	48	* add_reloc_offset(x) returns x + reloc_offset().
49	*/	49	*/
50	_GLOBAL(add_reloc_offset)	50	_GLOBAL(add_reloc_offset)
51	mflr r0	51	mflr r0
52	bl 1f	52	bl 1f
53	1: mflr r5	53	1: mflr r5
54	LOADADDR(r4,1b)	54	LOADADDR(r4,1b)
55	subf r5,r4,r5	55	subf r5,r4,r5
56	add r3,r3,r5	56	add r3,r3,r5
57	mtlr r0	57	mtlr r0
58	blr	58	blr
59		59
60	_GLOBAL(get_msr)	60	_GLOBAL(get_msr)
61	mfmsr r3	61	mfmsr r3
62	blr	62	blr
63		63
64	_GLOBAL(get_dar)	64	_GLOBAL(get_dar)
65	mfdar r3	65	mfdar r3
66	blr	66	blr
67		67
68	_GLOBAL(get_srr0)	68	_GLOBAL(get_srr0)
69	mfsrr0 r3	69	mfsrr0 r3
70	blr	70	blr
71		71
72	_GLOBAL(get_srr1)	72	_GLOBAL(get_srr1)
73	mfsrr1 r3	73	mfsrr1 r3
74	blr	74	blr
75		75
76	_GLOBAL(get_sp)	76	_GLOBAL(get_sp)
77	mr r3,r1	77	mr r3,r1
78	blr	78	blr
79		79
80	#ifdef CONFIG_IRQSTACKS	80	#ifdef CONFIG_IRQSTACKS
81	_GLOBAL(call_do_softirq)	81	_GLOBAL(call_do_softirq)
82	mflr r0	82	mflr r0
83	std r0,16(r1)	83	std r0,16(r1)
84	stdu r1,THREAD_SIZE-112(r3)	84	stdu r1,THREAD_SIZE-112(r3)
85	mr r1,r3	85	mr r1,r3
86	bl .__do_softirq	86	bl .__do_softirq
87	ld r1,0(r1)	87	ld r1,0(r1)
88	ld r0,16(r1)	88	ld r0,16(r1)
89	mtlr r0	89	mtlr r0
90	blr	90	blr
91		91
92	_GLOBAL(call_ppc_irq_dispatch_handler)	92	_GLOBAL(call___do_IRQ)
93	mflr r0	93	mflr r0
94	std r0,16(r1)	94	std r0,16(r1)
95	stdu r1,THREAD_SIZE-112(r5)	95	stdu r1,THREAD_SIZE-112(r5)
96	mr r1,r5	96	mr r1,r5
97	bl .ppc_irq_dispatch_handler	97	bl .__do_IRQ
98	ld r1,0(r1)	98	ld r1,0(r1)
99	ld r0,16(r1)	99	ld r0,16(r1)
100	mtlr r0	100	mtlr r0
101	blr	101	blr
102	#endif /* CONFIG_IRQSTACKS */	102	#endif /* CONFIG_IRQSTACKS */
103		103
104	/*	104	/*
105	* To be called by C code which needs to do some operations with MMU	105	* To be called by C code which needs to do some operations with MMU
106	* disabled. Note that interrupts have to be disabled by the caller	106	* disabled. Note that interrupts have to be disabled by the caller
107	* prior to calling us. The code called _MUST_ be in the RMO of course	107	* prior to calling us. The code called _MUST_ be in the RMO of course
108	* and part of the linear mapping as we don't attempt to translate the	108	* and part of the linear mapping as we don't attempt to translate the
109	* stack pointer at all. The function is called with the stack switched	109	* stack pointer at all. The function is called with the stack switched
110	* to this CPU emergency stack	110	* to this CPU emergency stack
111	*	111	*
112	* prototype is void call_with_mmu_off(void func, void *data);	112	* prototype is void call_with_mmu_off(void func, void *data);
113	*	113	*
114	* the called function is expected to be of the form	114	* the called function is expected to be of the form
115	*	115	*
116	* void called(void data);	116	* void called(void data);
117	*/	117	*/
118	_GLOBAL(call_with_mmu_off)	118	_GLOBAL(call_with_mmu_off)
119	mflr r0 /* get link, save it on stackframe */	119	mflr r0 /* get link, save it on stackframe */
120	std r0,16(r1)	120	std r0,16(r1)
121	mr r1,r5 /* save old stack ptr */	121	mr r1,r5 /* save old stack ptr */
122	ld r1,PACAEMERGSP(r13) /* get emerg. stack */	122	ld r1,PACAEMERGSP(r13) /* get emerg. stack */
123	subi r1,r1,STACK_FRAME_OVERHEAD	123	subi r1,r1,STACK_FRAME_OVERHEAD
124	std r0,16(r1) /* save link on emerg. stack */	124	std r0,16(r1) /* save link on emerg. stack */
125	std r5,0(r1) /* save old stack ptr in backchain */	125	std r5,0(r1) /* save old stack ptr in backchain */
126	ld r3,0(r3) /* get to real function ptr (assume same TOC) */	126	ld r3,0(r3) /* get to real function ptr (assume same TOC) */
127	bl 2f /* we need LR to return, continue at label 2 */	127	bl 2f /* we need LR to return, continue at label 2 */
128		128
129	ld r0,16(r1) /* we return here from the call, get LR and */	129	ld r0,16(r1) /* we return here from the call, get LR and */
130	ld r1,0(r1) /* .. old stack ptr */	130	ld r1,0(r1) /* .. old stack ptr */
131	mtspr SPRN_SRR0,r0 /* and get back to virtual mode with these */	131	mtspr SPRN_SRR0,r0 /* and get back to virtual mode with these */
132	mfmsr r4	132	mfmsr r4
133	ori r4,r4,MSR_IR\|MSR_DR	133	ori r4,r4,MSR_IR\|MSR_DR
134	mtspr SPRN_SRR1,r4	134	mtspr SPRN_SRR1,r4
135	rfid	135	rfid
136		136
137	2: mtspr SPRN_SRR0,r3 /* coming from above, enter real mode */	137	2: mtspr SPRN_SRR0,r3 /* coming from above, enter real mode */
138	mr r3,r4 /* get parameter */	138	mr r3,r4 /* get parameter */
139	mfmsr r0	139	mfmsr r0
140	ori r0,r0,MSR_IR\|MSR_DR	140	ori r0,r0,MSR_IR\|MSR_DR
141	xori r0,r0,MSR_IR\|MSR_DR	141	xori r0,r0,MSR_IR\|MSR_DR
142	mtspr SPRN_SRR1,r0	142	mtspr SPRN_SRR1,r0
143	rfid	143	rfid
144		144
145		145
146	.section ".toc","aw"	146	.section ".toc","aw"
147	PPC64_CACHES:	147	PPC64_CACHES:
148	.tc ppc64_caches[TC],ppc64_caches	148	.tc ppc64_caches[TC],ppc64_caches
149	.section ".text"	149	.section ".text"
150		150
151	/*	151	/*
152	* Write any modified data cache blocks out to memory	152	* Write any modified data cache blocks out to memory
153	* and invalidate the corresponding instruction cache blocks.	153	* and invalidate the corresponding instruction cache blocks.
154	*	154	*
155	* flush_icache_range(unsigned long start, unsigned long stop)	155	* flush_icache_range(unsigned long start, unsigned long stop)
156	*	156	*
157	* flush all bytes from start through stop-1 inclusive	157	* flush all bytes from start through stop-1 inclusive
158	*/	158	*/
159		159
160	_KPROBE(__flush_icache_range)	160	_KPROBE(__flush_icache_range)
161		161
162	/*	162	/*
163	* Flush the data cache to memory	163	* Flush the data cache to memory
164	*	164	*
165	* Different systems have different cache line sizes	165	* Different systems have different cache line sizes
166	* and in some cases i-cache and d-cache line sizes differ from	166	* and in some cases i-cache and d-cache line sizes differ from
167	* each other.	167	* each other.
168	*/	168	*/
169	ld r10,PPC64_CACHES@toc(r2)	169	ld r10,PPC64_CACHES@toc(r2)
170	lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */	170	lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
171	addi r5,r7,-1	171	addi r5,r7,-1
172	andc r6,r3,r5 /* round low to line bdy */	172	andc r6,r3,r5 /* round low to line bdy */
173	subf r8,r6,r4 /* compute length */	173	subf r8,r6,r4 /* compute length */
174	add r8,r8,r5 /* ensure we get enough */	174	add r8,r8,r5 /* ensure we get enough */
175	lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */	175	lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
176	srw. r8,r8,r9 /* compute line count */	176	srw. r8,r8,r9 /* compute line count */
177	beqlr /* nothing to do? */	177	beqlr /* nothing to do? */
178	mtctr r8	178	mtctr r8
179	1: dcbst 0,r6	179	1: dcbst 0,r6
180	add r6,r6,r7	180	add r6,r6,r7
181	bdnz 1b	181	bdnz 1b
182	sync	182	sync
183		183
184	/* Now invalidate the instruction cache */	184	/* Now invalidate the instruction cache */
185		185
186	lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */	186	lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
187	addi r5,r7,-1	187	addi r5,r7,-1
188	andc r6,r3,r5 /* round low to line bdy */	188	andc r6,r3,r5 /* round low to line bdy */
189	subf r8,r6,r4 /* compute length */	189	subf r8,r6,r4 /* compute length */
190	add r8,r8,r5	190	add r8,r8,r5
191	lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */	191	lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
192	srw. r8,r8,r9 /* compute line count */	192	srw. r8,r8,r9 /* compute line count */
193	beqlr /* nothing to do? */	193	beqlr /* nothing to do? */
194	mtctr r8	194	mtctr r8
195	2: icbi 0,r6	195	2: icbi 0,r6
196	add r6,r6,r7	196	add r6,r6,r7
197	bdnz 2b	197	bdnz 2b
198	isync	198	isync
199	blr	199	blr
200	.previous .text	200	.previous .text
201	/*	201	/*
202	* Like above, but only do the D-cache.	202	* Like above, but only do the D-cache.
203	*	203	*
204	* flush_dcache_range(unsigned long start, unsigned long stop)	204	* flush_dcache_range(unsigned long start, unsigned long stop)
205	*	205	*
206	* flush all bytes from start to stop-1 inclusive	206	* flush all bytes from start to stop-1 inclusive
207	*/	207	*/
208	_GLOBAL(flush_dcache_range)	208	_GLOBAL(flush_dcache_range)
209		209
210	/*	210	/*
211	* Flush the data cache to memory	211	* Flush the data cache to memory
212	*	212	*
213	* Different systems have different cache line sizes	213	* Different systems have different cache line sizes
214	*/	214	*/
215	ld r10,PPC64_CACHES@toc(r2)	215	ld r10,PPC64_CACHES@toc(r2)
216	lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */	216	lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
217	addi r5,r7,-1	217	addi r5,r7,-1
218	andc r6,r3,r5 /* round low to line bdy */	218	andc r6,r3,r5 /* round low to line bdy */
219	subf r8,r6,r4 /* compute length */	219	subf r8,r6,r4 /* compute length */
220	add r8,r8,r5 /* ensure we get enough */	220	add r8,r8,r5 /* ensure we get enough */
221	lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */	221	lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
222	srw. r8,r8,r9 /* compute line count */	222	srw. r8,r8,r9 /* compute line count */
223	beqlr /* nothing to do? */	223	beqlr /* nothing to do? */
224	mtctr r8	224	mtctr r8
225	0: dcbst 0,r6	225	0: dcbst 0,r6
226	add r6,r6,r7	226	add r6,r6,r7
227	bdnz 0b	227	bdnz 0b
228	sync	228	sync
229	blr	229	blr
230		230
231	/*	231	/*
232	* Like above, but works on non-mapped physical addresses.	232	* Like above, but works on non-mapped physical addresses.
233	* Use only for non-LPAR setups ! It also assumes real mode	233	* Use only for non-LPAR setups ! It also assumes real mode
234	* is cacheable. Used for flushing out the DART before using	234	* is cacheable. Used for flushing out the DART before using
235	* it as uncacheable memory	235	* it as uncacheable memory
236	*	236	*
237	* flush_dcache_phys_range(unsigned long start, unsigned long stop)	237	* flush_dcache_phys_range(unsigned long start, unsigned long stop)
238	*	238	*
239	* flush all bytes from start to stop-1 inclusive	239	* flush all bytes from start to stop-1 inclusive
240	*/	240	*/
241	_GLOBAL(flush_dcache_phys_range)	241	_GLOBAL(flush_dcache_phys_range)
242	ld r10,PPC64_CACHES@toc(r2)	242	ld r10,PPC64_CACHES@toc(r2)
243	lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */	243	lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
244	addi r5,r7,-1	244	addi r5,r7,-1
245	andc r6,r3,r5 /* round low to line bdy */	245	andc r6,r3,r5 /* round low to line bdy */
246	subf r8,r6,r4 /* compute length */	246	subf r8,r6,r4 /* compute length */
247	add r8,r8,r5 /* ensure we get enough */	247	add r8,r8,r5 /* ensure we get enough */
248	lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */	248	lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
249	srw. r8,r8,r9 /* compute line count */	249	srw. r8,r8,r9 /* compute line count */
250	beqlr /* nothing to do? */	250	beqlr /* nothing to do? */
251	mfmsr r5 /* Disable MMU Data Relocation */	251	mfmsr r5 /* Disable MMU Data Relocation */
252	ori r0,r5,MSR_DR	252	ori r0,r5,MSR_DR
253	xori r0,r0,MSR_DR	253	xori r0,r0,MSR_DR
254	sync	254	sync
255	mtmsr r0	255	mtmsr r0
256	sync	256	sync
257	isync	257	isync
258	mtctr r8	258	mtctr r8
259	0: dcbst 0,r6	259	0: dcbst 0,r6
260	add r6,r6,r7	260	add r6,r6,r7
261	bdnz 0b	261	bdnz 0b
262	sync	262	sync
263	isync	263	isync
264	mtmsr r5 /* Re-enable MMU Data Relocation */	264	mtmsr r5 /* Re-enable MMU Data Relocation */
265	sync	265	sync
266	isync	266	isync
267	blr	267	blr
268		268
269	_GLOBAL(flush_inval_dcache_range)	269	_GLOBAL(flush_inval_dcache_range)
270	ld r10,PPC64_CACHES@toc(r2)	270	ld r10,PPC64_CACHES@toc(r2)
271	lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */	271	lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
272	addi r5,r7,-1	272	addi r5,r7,-1
273	andc r6,r3,r5 /* round low to line bdy */	273	andc r6,r3,r5 /* round low to line bdy */
274	subf r8,r6,r4 /* compute length */	274	subf r8,r6,r4 /* compute length */
275	add r8,r8,r5 /* ensure we get enough */	275	add r8,r8,r5 /* ensure we get enough */
276	lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */	276	lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
277	srw. r8,r8,r9 /* compute line count */	277	srw. r8,r8,r9 /* compute line count */
278	beqlr /* nothing to do? */	278	beqlr /* nothing to do? */
279	sync	279	sync
280	isync	280	isync
281	mtctr r8	281	mtctr r8
282	0: dcbf 0,r6	282	0: dcbf 0,r6
283	add r6,r6,r7	283	add r6,r6,r7
284	bdnz 0b	284	bdnz 0b
285	sync	285	sync
286	isync	286	isync
287	blr	287	blr
288		288
289		289
290	/*	290	/*
291	* Flush a particular page from the data cache to RAM.	291	* Flush a particular page from the data cache to RAM.
292	* Note: this is necessary because the instruction cache does not	292	* Note: this is necessary because the instruction cache does not
293	* snoop from the data cache.	293	* snoop from the data cache.
294	*	294	*
295	* void __flush_dcache_icache(void *page)	295	* void __flush_dcache_icache(void *page)
296	*/	296	*/
297	_GLOBAL(__flush_dcache_icache)	297	_GLOBAL(__flush_dcache_icache)
298	/*	298	/*
299	* Flush the data cache to memory	299	* Flush the data cache to memory
300	*	300	*
301	* Different systems have different cache line sizes	301	* Different systems have different cache line sizes
302	*/	302	*/
303		303
304	/* Flush the dcache */	304	/* Flush the dcache */
305	ld r7,PPC64_CACHES@toc(r2)	305	ld r7,PPC64_CACHES@toc(r2)
306	clrrdi r3,r3,PAGE_SHIFT /* Page align */	306	clrrdi r3,r3,PAGE_SHIFT /* Page align */
307	lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */	307	lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
308	lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */	308	lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
309	mr r6,r3	309	mr r6,r3
310	mtctr r4	310	mtctr r4
311	0: dcbst 0,r6	311	0: dcbst 0,r6
312	add r6,r6,r5	312	add r6,r6,r5
313	bdnz 0b	313	bdnz 0b
314	sync	314	sync
315		315
316	/* Now invalidate the icache */	316	/* Now invalidate the icache */
317		317
318	lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */	318	lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
319	lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */	319	lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
320	mtctr r4	320	mtctr r4
321	1: icbi 0,r3	321	1: icbi 0,r3
322	add r3,r3,r5	322	add r3,r3,r5
323	bdnz 1b	323	bdnz 1b
324	isync	324	isync
325	blr	325	blr
326		326
327	/*	327	/*
328	* I/O string operations	328	* I/O string operations
329	*	329	*
330	* insb(port, buf, len)	330	* insb(port, buf, len)
331	* outsb(port, buf, len)	331	* outsb(port, buf, len)
332	* insw(port, buf, len)	332	* insw(port, buf, len)
333	* outsw(port, buf, len)	333	* outsw(port, buf, len)
334	* insl(port, buf, len)	334	* insl(port, buf, len)
335	* outsl(port, buf, len)	335	* outsl(port, buf, len)
336	* insw_ns(port, buf, len)	336	* insw_ns(port, buf, len)
337	* outsw_ns(port, buf, len)	337	* outsw_ns(port, buf, len)
338	* insl_ns(port, buf, len)	338	* insl_ns(port, buf, len)
339	* outsl_ns(port, buf, len)	339	* outsl_ns(port, buf, len)
340	*	340	*
341	* The *_ns versions don't do byte-swapping.	341	* The *_ns versions don't do byte-swapping.
342	*/	342	*/
343	_GLOBAL(_insb)	343	_GLOBAL(_insb)
344	cmpwi 0,r5,0	344	cmpwi 0,r5,0
345	mtctr r5	345	mtctr r5
346	subi r4,r4,1	346	subi r4,r4,1
347	blelr-	347	blelr-
348	00: lbz r5,0(r3)	348	00: lbz r5,0(r3)
349	eieio	349	eieio
350	stbu r5,1(r4)	350	stbu r5,1(r4)
351	bdnz 00b	351	bdnz 00b
352	twi 0,r5,0	352	twi 0,r5,0
353	isync	353	isync
354	blr	354	blr
355		355
356	_GLOBAL(_outsb)	356	_GLOBAL(_outsb)
357	cmpwi 0,r5,0	357	cmpwi 0,r5,0
358	mtctr r5	358	mtctr r5
359	subi r4,r4,1	359	subi r4,r4,1
360	blelr-	360	blelr-
361	00: lbzu r5,1(r4)	361	00: lbzu r5,1(r4)
362	stb r5,0(r3)	362	stb r5,0(r3)
363	bdnz 00b	363	bdnz 00b
364	sync	364	sync
365	blr	365	blr
366		366
367	_GLOBAL(_insw)	367	_GLOBAL(_insw)
368	cmpwi 0,r5,0	368	cmpwi 0,r5,0
369	mtctr r5	369	mtctr r5
370	subi r4,r4,2	370	subi r4,r4,2
371	blelr-	371	blelr-
372	00: lhbrx r5,0,r3	372	00: lhbrx r5,0,r3
373	eieio	373	eieio
374	sthu r5,2(r4)	374	sthu r5,2(r4)
375	bdnz 00b	375	bdnz 00b
376	twi 0,r5,0	376	twi 0,r5,0
377	isync	377	isync
378	blr	378	blr
379		379
380	_GLOBAL(_outsw)	380	_GLOBAL(_outsw)
381	cmpwi 0,r5,0	381	cmpwi 0,r5,0
382	mtctr r5	382	mtctr r5
383	subi r4,r4,2	383	subi r4,r4,2
384	blelr-	384	blelr-
385	00: lhzu r5,2(r4)	385	00: lhzu r5,2(r4)
386	sthbrx r5,0,r3	386	sthbrx r5,0,r3
387	bdnz 00b	387	bdnz 00b
388	sync	388	sync
389	blr	389	blr
390		390
391	_GLOBAL(_insl)	391	_GLOBAL(_insl)
392	cmpwi 0,r5,0	392	cmpwi 0,r5,0
393	mtctr r5	393	mtctr r5
394	subi r4,r4,4	394	subi r4,r4,4
395	blelr-	395	blelr-
396	00: lwbrx r5,0,r3	396	00: lwbrx r5,0,r3
397	eieio	397	eieio
398	stwu r5,4(r4)	398	stwu r5,4(r4)
399	bdnz 00b	399	bdnz 00b
400	twi 0,r5,0	400	twi 0,r5,0
401	isync	401	isync
402	blr	402	blr
403		403
404	_GLOBAL(_outsl)	404	_GLOBAL(_outsl)
405	cmpwi 0,r5,0	405	cmpwi 0,r5,0
406	mtctr r5	406	mtctr r5
407	subi r4,r4,4	407	subi r4,r4,4
408	blelr-	408	blelr-
409	00: lwzu r5,4(r4)	409	00: lwzu r5,4(r4)
410	stwbrx r5,0,r3	410	stwbrx r5,0,r3
411	bdnz 00b	411	bdnz 00b
412	sync	412	sync
413	blr	413	blr
414		414
415	/* _GLOBAL(ide_insw) now in drivers/ide/ide-iops.c */	415	/* _GLOBAL(ide_insw) now in drivers/ide/ide-iops.c */
416	_GLOBAL(_insw_ns)	416	_GLOBAL(_insw_ns)
417	cmpwi 0,r5,0	417	cmpwi 0,r5,0
418	mtctr r5	418	mtctr r5
419	subi r4,r4,2	419	subi r4,r4,2
420	blelr-	420	blelr-
421	00: lhz r5,0(r3)	421	00: lhz r5,0(r3)
422	eieio	422	eieio
423	sthu r5,2(r4)	423	sthu r5,2(r4)
424	bdnz 00b	424	bdnz 00b
425	twi 0,r5,0	425	twi 0,r5,0
426	isync	426	isync
427	blr	427	blr
428		428
429	/* _GLOBAL(ide_outsw) now in drivers/ide/ide-iops.c */	429	/* _GLOBAL(ide_outsw) now in drivers/ide/ide-iops.c */
430	_GLOBAL(_outsw_ns)	430	_GLOBAL(_outsw_ns)
431	cmpwi 0,r5,0	431	cmpwi 0,r5,0
432	mtctr r5	432	mtctr r5
433	subi r4,r4,2	433	subi r4,r4,2
434	blelr-	434	blelr-
435	00: lhzu r5,2(r4)	435	00: lhzu r5,2(r4)
436	sth r5,0(r3)	436	sth r5,0(r3)
437	bdnz 00b	437	bdnz 00b
438	sync	438	sync
439	blr	439	blr
440		440
441	_GLOBAL(_insl_ns)	441	_GLOBAL(_insl_ns)
442	cmpwi 0,r5,0	442	cmpwi 0,r5,0
443	mtctr r5	443	mtctr r5
444	subi r4,r4,4	444	subi r4,r4,4
445	blelr-	445	blelr-
446	00: lwz r5,0(r3)	446	00: lwz r5,0(r3)
447	eieio	447	eieio
448	stwu r5,4(r4)	448	stwu r5,4(r4)
449	bdnz 00b	449	bdnz 00b
450	twi 0,r5,0	450	twi 0,r5,0
451	isync	451	isync
452	blr	452	blr
453		453
454	_GLOBAL(_outsl_ns)	454	_GLOBAL(_outsl_ns)
455	cmpwi 0,r5,0	455	cmpwi 0,r5,0
456	mtctr r5	456	mtctr r5
457	subi r4,r4,4	457	subi r4,r4,4
458	blelr-	458	blelr-
459	00: lwzu r5,4(r4)	459	00: lwzu r5,4(r4)
460	stw r5,0(r3)	460	stw r5,0(r3)
461	bdnz 00b	461	bdnz 00b
462	sync	462	sync
463	blr	463	blr
464		464
465	/*	465	/*
466	* identify_cpu and calls setup_cpu	466	* identify_cpu and calls setup_cpu
467	* In: r3 = base of the cpu_specs array	467	* In: r3 = base of the cpu_specs array
468	* r4 = address of cur_cpu_spec	468	* r4 = address of cur_cpu_spec
469	* r5 = relocation offset	469	* r5 = relocation offset
470	*/	470	*/
471	_GLOBAL(identify_cpu)	471	_GLOBAL(identify_cpu)
472	mfpvr r7	472	mfpvr r7
473	1:	473	1:
474	lwz r8,CPU_SPEC_PVR_MASK(r3)	474	lwz r8,CPU_SPEC_PVR_MASK(r3)
475	and r8,r8,r7	475	and r8,r8,r7
476	lwz r9,CPU_SPEC_PVR_VALUE(r3)	476	lwz r9,CPU_SPEC_PVR_VALUE(r3)
477	cmplw 0,r9,r8	477	cmplw 0,r9,r8
478	beq 1f	478	beq 1f
479	addi r3,r3,CPU_SPEC_ENTRY_SIZE	479	addi r3,r3,CPU_SPEC_ENTRY_SIZE
480	b 1b	480	b 1b
481	1:	481	1:
482	sub r0,r3,r5	482	sub r0,r3,r5
483	std r0,0(r4)	483	std r0,0(r4)
484	ld r4,CPU_SPEC_SETUP(r3)	484	ld r4,CPU_SPEC_SETUP(r3)
485	add r4,r4,r5	485	add r4,r4,r5
486	ld r4,0(r4)	486	ld r4,0(r4)
487	add r4,r4,r5	487	add r4,r4,r5
488	mtctr r4	488	mtctr r4
489	/* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */	489	/* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */
490	mr r4,r3	490	mr r4,r3
491	mr r3,r5	491	mr r3,r5
492	bctr	492	bctr
493		493
494	/*	494	/*
495	* do_cpu_ftr_fixups - goes through the list of CPU feature fixups	495	* do_cpu_ftr_fixups - goes through the list of CPU feature fixups
496	* and writes nop's over sections of code that don't apply for this cpu.	496	* and writes nop's over sections of code that don't apply for this cpu.
497	* r3 = data offset (not changed)	497	* r3 = data offset (not changed)
498	*/	498	*/
499	_GLOBAL(do_cpu_ftr_fixups)	499	_GLOBAL(do_cpu_ftr_fixups)
500	/* Get CPU 0 features */	500	/* Get CPU 0 features */
501	LOADADDR(r6,cur_cpu_spec)	501	LOADADDR(r6,cur_cpu_spec)
502	sub r6,r6,r3	502	sub r6,r6,r3
503	ld r4,0(r6)	503	ld r4,0(r6)
504	sub r4,r4,r3	504	sub r4,r4,r3
505	ld r4,CPU_SPEC_FEATURES(r4)	505	ld r4,CPU_SPEC_FEATURES(r4)
506	/* Get the fixup table */	506	/* Get the fixup table */
507	LOADADDR(r6,__start___ftr_fixup)	507	LOADADDR(r6,__start___ftr_fixup)
508	sub r6,r6,r3	508	sub r6,r6,r3
509	LOADADDR(r7,__stop___ftr_fixup)	509	LOADADDR(r7,__stop___ftr_fixup)
510	sub r7,r7,r3	510	sub r7,r7,r3
511	/* Do the fixup */	511	/* Do the fixup */
512	1: cmpld r6,r7	512	1: cmpld r6,r7
513	bgelr	513	bgelr
514	addi r6,r6,32	514	addi r6,r6,32
515	ld r8,-32(r6) /* mask */	515	ld r8,-32(r6) /* mask */
516	and r8,r8,r4	516	and r8,r8,r4
517	ld r9,-24(r6) /* value */	517	ld r9,-24(r6) /* value */
518	cmpld r8,r9	518	cmpld r8,r9
519	beq 1b	519	beq 1b
520	ld r8,-16(r6) /* section begin */	520	ld r8,-16(r6) /* section begin */
521	ld r9,-8(r6) /* section end */	521	ld r9,-8(r6) /* section end */
522	subf. r9,r8,r9	522	subf. r9,r8,r9
523	beq 1b	523	beq 1b
524	/* write nops over the section of code */	524	/* write nops over the section of code */
525	/* todo: if large section, add a branch at the start of it */	525	/* todo: if large section, add a branch at the start of it */
526	srwi r9,r9,2	526	srwi r9,r9,2
527	mtctr r9	527	mtctr r9
528	sub r8,r8,r3	528	sub r8,r8,r3
529	lis r0,0x60000000@h /* nop */	529	lis r0,0x60000000@h /* nop */
530	3: stw r0,0(r8)	530	3: stw r0,0(r8)
531	andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l	531	andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
532	beq 2f	532	beq 2f
533	dcbst 0,r8 /* suboptimal, but simpler */	533	dcbst 0,r8 /* suboptimal, but simpler */
534	sync	534	sync
535	icbi 0,r8	535	icbi 0,r8
536	2: addi r8,r8,4	536	2: addi r8,r8,4
537	bdnz 3b	537	bdnz 3b
538	sync /* additional sync needed on g4 */	538	sync /* additional sync needed on g4 */
539	isync	539	isync
540	b 1b	540	b 1b
541		541
542	#if defined(CONFIG_PPC_PMAC) \|\| defined(CONFIG_PPC_MAPLE)	542	#if defined(CONFIG_PPC_PMAC) \|\| defined(CONFIG_PPC_MAPLE)
543	/*	543	/*
544	* Do an IO access in real mode	544	* Do an IO access in real mode
545	*/	545	*/
546	_GLOBAL(real_readb)	546	_GLOBAL(real_readb)
547	mfmsr r7	547	mfmsr r7
548	ori r0,r7,MSR_DR	548	ori r0,r7,MSR_DR
549	xori r0,r0,MSR_DR	549	xori r0,r0,MSR_DR
550	sync	550	sync
551	mtmsrd r0	551	mtmsrd r0
552	sync	552	sync
553	isync	553	isync
554	mfspr r6,SPRN_HID4	554	mfspr r6,SPRN_HID4
555	rldicl r5,r6,32,0	555	rldicl r5,r6,32,0
556	ori r5,r5,0x100	556	ori r5,r5,0x100
557	rldicl r5,r5,32,0	557	rldicl r5,r5,32,0
558	sync	558	sync
559	mtspr SPRN_HID4,r5	559	mtspr SPRN_HID4,r5
560	isync	560	isync
561	slbia	561	slbia
562	isync	562	isync
563	lbz r3,0(r3)	563	lbz r3,0(r3)
564	sync	564	sync
565	mtspr SPRN_HID4,r6	565	mtspr SPRN_HID4,r6
566	isync	566	isync
567	slbia	567	slbia
568	isync	568	isync
569	mtmsrd r7	569	mtmsrd r7
570	sync	570	sync
571	isync	571	isync
572	blr	572	blr
573		573
574	/*	574	/*
575	* Do an IO access in real mode	575	* Do an IO access in real mode
576	*/	576	*/
577	_GLOBAL(real_writeb)	577	_GLOBAL(real_writeb)
578	mfmsr r7	578	mfmsr r7
579	ori r0,r7,MSR_DR	579	ori r0,r7,MSR_DR
580	xori r0,r0,MSR_DR	580	xori r0,r0,MSR_DR
581	sync	581	sync
582	mtmsrd r0	582	mtmsrd r0
583	sync	583	sync
584	isync	584	isync
585	mfspr r6,SPRN_HID4	585	mfspr r6,SPRN_HID4
586	rldicl r5,r6,32,0	586	rldicl r5,r6,32,0
587	ori r5,r5,0x100	587	ori r5,r5,0x100
588	rldicl r5,r5,32,0	588	rldicl r5,r5,32,0
589	sync	589	sync
590	mtspr SPRN_HID4,r5	590	mtspr SPRN_HID4,r5
591	isync	591	isync
592	slbia	592	slbia
593	isync	593	isync
594	stb r3,0(r4)	594	stb r3,0(r4)
595	sync	595	sync
596	mtspr SPRN_HID4,r6	596	mtspr SPRN_HID4,r6
597	isync	597	isync
598	slbia	598	slbia
599	isync	599	isync
600	mtmsrd r7	600	mtmsrd r7
601	sync	601	sync
602	isync	602	isync
603	blr	603	blr
604	#endif /* defined(CONFIG_PPC_PMAC) \|\| defined(CONFIG_PPC_MAPLE) */	604	#endif /* defined(CONFIG_PPC_PMAC) \|\| defined(CONFIG_PPC_MAPLE) */
605		605
606	/*	606	/*
607	* SCOM access functions for 970 (FX only for now)	607	* SCOM access functions for 970 (FX only for now)
608	*	608	*
609	* unsigned long scom970_read(unsigned int address);	609	* unsigned long scom970_read(unsigned int address);
610	* void scom970_write(unsigned int address, unsigned long value);	610	* void scom970_write(unsigned int address, unsigned long value);
611	*	611	*
612	* The address passed in is the 24 bits register address. This code	612	* The address passed in is the 24 bits register address. This code
613	* is 970 specific and will not check the status bits, so you should	613	* is 970 specific and will not check the status bits, so you should
614	* know what you are doing.	614	* know what you are doing.
615	*/	615	*/
616	_GLOBAL(scom970_read)	616	_GLOBAL(scom970_read)
617	/* interrupts off */	617	/* interrupts off */
618	mfmsr r4	618	mfmsr r4
619	ori r0,r4,MSR_EE	619	ori r0,r4,MSR_EE
620	xori r0,r0,MSR_EE	620	xori r0,r0,MSR_EE
621	mtmsrd r0,1	621	mtmsrd r0,1
622		622
623	/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits	623	/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
624	* (including parity). On current CPUs they must be 0'd,	624	* (including parity). On current CPUs they must be 0'd,
625	* and finally or in RW bit	625	* and finally or in RW bit
626	*/	626	*/
627	rlwinm r3,r3,8,0,15	627	rlwinm r3,r3,8,0,15
628	ori r3,r3,0x8000	628	ori r3,r3,0x8000
629		629
630	/* do the actual scom read */	630	/* do the actual scom read */
631	sync	631	sync
632	mtspr SPRN_SCOMC,r3	632	mtspr SPRN_SCOMC,r3
633	isync	633	isync
634	mfspr r3,SPRN_SCOMD	634	mfspr r3,SPRN_SCOMD
635	isync	635	isync
636	mfspr r0,SPRN_SCOMC	636	mfspr r0,SPRN_SCOMC
637	isync	637	isync
638		638
639	/* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah	639	/* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
640	* that's the best we can do). Not implemented yet as we don't use	640	* that's the best we can do). Not implemented yet as we don't use
641	* the scom on any of the bogus CPUs yet, but may have to be done	641	* the scom on any of the bogus CPUs yet, but may have to be done
642	* ultimately	642	* ultimately
643	*/	643	*/
644		644
645	/* restore interrupts */	645	/* restore interrupts */
646	mtmsrd r4,1	646	mtmsrd r4,1
647	blr	647	blr
648		648
649		649
650	_GLOBAL(scom970_write)	650	_GLOBAL(scom970_write)
651	/* interrupts off */	651	/* interrupts off */
652	mfmsr r5	652	mfmsr r5
653	ori r0,r5,MSR_EE	653	ori r0,r5,MSR_EE
654	xori r0,r0,MSR_EE	654	xori r0,r0,MSR_EE
655	mtmsrd r0,1	655	mtmsrd r0,1
656		656
657	/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits	657	/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
658	* (including parity). On current CPUs they must be 0'd.	658	* (including parity). On current CPUs they must be 0'd.
659	*/	659	*/
660		660
661	rlwinm r3,r3,8,0,15	661	rlwinm r3,r3,8,0,15
662		662
663	sync	663	sync
664	mtspr SPRN_SCOMD,r4 /* write data */	664	mtspr SPRN_SCOMD,r4 /* write data */
665	isync	665	isync
666	mtspr SPRN_SCOMC,r3 /* write command */	666	mtspr SPRN_SCOMC,r3 /* write command */
667	isync	667	isync
668	mfspr 3,SPRN_SCOMC	668	mfspr 3,SPRN_SCOMC
669	isync	669	isync
670		670
671	/* restore interrupts */	671	/* restore interrupts */
672	mtmsrd r5,1	672	mtmsrd r5,1
673	blr	673	blr
674		674
675		675
676	/*	676	/*
677	* Create a kernel thread	677	* Create a kernel thread
678	* kernel_thread(fn, arg, flags)	678	* kernel_thread(fn, arg, flags)
679	*/	679	*/
680	_GLOBAL(kernel_thread)	680	_GLOBAL(kernel_thread)
681	std r29,-24(r1)	681	std r29,-24(r1)
682	std r30,-16(r1)	682	std r30,-16(r1)
683	stdu r1,-STACK_FRAME_OVERHEAD(r1)	683	stdu r1,-STACK_FRAME_OVERHEAD(r1)
684	mr r29,r3	684	mr r29,r3
685	mr r30,r4	685	mr r30,r4
686	ori r3,r5,CLONE_VM /* flags */	686	ori r3,r5,CLONE_VM /* flags */
687	oris r3,r3,(CLONE_UNTRACED>>16)	687	oris r3,r3,(CLONE_UNTRACED>>16)
688	li r4,0 /* new sp (unused) */	688	li r4,0 /* new sp (unused) */
689	li r0,__NR_clone	689	li r0,__NR_clone
690	sc	690	sc
691	cmpdi 0,r3,0 /* parent or child? */	691	cmpdi 0,r3,0 /* parent or child? */
692	bne 1f /* return if parent */	692	bne 1f /* return if parent */
693	li r0,0	693	li r0,0
694	stdu r0,-STACK_FRAME_OVERHEAD(r1)	694	stdu r0,-STACK_FRAME_OVERHEAD(r1)
695	ld r2,8(r29)	695	ld r2,8(r29)
696	ld r29,0(r29)	696	ld r29,0(r29)
697	mtlr r29 /* fn addr in lr */	697	mtlr r29 /* fn addr in lr */
698	mr r3,r30 /* load arg and call fn */	698	mr r3,r30 /* load arg and call fn */
699	blrl	699	blrl
700	li r0,__NR_exit /* exit after child exits */	700	li r0,__NR_exit /* exit after child exits */
701	li r3,0	701	li r3,0
702	sc	702	sc
703	1: addi r1,r1,STACK_FRAME_OVERHEAD	703	1: addi r1,r1,STACK_FRAME_OVERHEAD
704	ld r29,-24(r1)	704	ld r29,-24(r1)
705	ld r30,-16(r1)	705	ld r30,-16(r1)
706	blr	706	blr
707		707
708	/*	708	/*
709	* disable_kernel_fp()	709	* disable_kernel_fp()
710	* Disable the FPU.	710	* Disable the FPU.
711	*/	711	*/
712	_GLOBAL(disable_kernel_fp)	712	_GLOBAL(disable_kernel_fp)
713	mfmsr r3	713	mfmsr r3
714	rldicl r0,r3,(63-MSR_FP_LG),1	714	rldicl r0,r3,(63-MSR_FP_LG),1
715	rldicl r3,r0,(MSR_FP_LG+1),0	715	rldicl r3,r0,(MSR_FP_LG+1),0
716	mtmsrd r3 /* disable use of fpu now */	716	mtmsrd r3 /* disable use of fpu now */
717	isync	717	isync
718	blr	718	blr
719		719
720	#ifdef CONFIG_ALTIVEC	720	#ifdef CONFIG_ALTIVEC
721		721
722	#if 0 /* this has no callers for now */	722	#if 0 /* this has no callers for now */
723	/*	723	/*
724	* disable_kernel_altivec()	724	* disable_kernel_altivec()
725	* Disable the VMX.	725	* Disable the VMX.
726	*/	726	*/
727	_GLOBAL(disable_kernel_altivec)	727	_GLOBAL(disable_kernel_altivec)
728	mfmsr r3	728	mfmsr r3
729	rldicl r0,r3,(63-MSR_VEC_LG),1	729	rldicl r0,r3,(63-MSR_VEC_LG),1
730	rldicl r3,r0,(MSR_VEC_LG+1),0	730	rldicl r3,r0,(MSR_VEC_LG+1),0
731	mtmsrd r3 /* disable use of VMX now */	731	mtmsrd r3 /* disable use of VMX now */
732	isync	732	isync
733	blr	733	blr
734	#endif /* 0 */	734	#endif /* 0 */
735		735
736	/*	736	/*
737	* giveup_altivec(tsk)	737	* giveup_altivec(tsk)
738	* Disable VMX for the task given as the argument,	738	* Disable VMX for the task given as the argument,
739	* and save the vector registers in its thread_struct.	739	* and save the vector registers in its thread_struct.
740	* Enables the VMX for use in the kernel on return.	740	* Enables the VMX for use in the kernel on return.
741	*/	741	*/
742	_GLOBAL(giveup_altivec)	742	_GLOBAL(giveup_altivec)
743	mfmsr r5	743	mfmsr r5
744	oris r5,r5,MSR_VEC@h	744	oris r5,r5,MSR_VEC@h
745	mtmsrd r5 /* enable use of VMX now */	745	mtmsrd r5 /* enable use of VMX now */
746	isync	746	isync
747	cmpdi 0,r3,0	747	cmpdi 0,r3,0
748	beqlr- /* if no previous owner, done */	748	beqlr- /* if no previous owner, done */
749	addi r3,r3,THREAD /* want THREAD of task */	749	addi r3,r3,THREAD /* want THREAD of task */
750	ld r5,PT_REGS(r3)	750	ld r5,PT_REGS(r3)
751	cmpdi 0,r5,0	751	cmpdi 0,r5,0
752	SAVE_32VRS(0,r4,r3)	752	SAVE_32VRS(0,r4,r3)
753	mfvscr vr0	753	mfvscr vr0
754	li r4,THREAD_VSCR	754	li r4,THREAD_VSCR
755	stvx vr0,r4,r3	755	stvx vr0,r4,r3
756	beq 1f	756	beq 1f
757	ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)	757	ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
758	lis r3,MSR_VEC@h	758	lis r3,MSR_VEC@h
759	andc r4,r4,r3 /* disable FP for previous task */	759	andc r4,r4,r3 /* disable FP for previous task */
760	std r4,_MSR-STACK_FRAME_OVERHEAD(r5)	760	std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
761	1:	761	1:
762	#ifndef CONFIG_SMP	762	#ifndef CONFIG_SMP
763	li r5,0	763	li r5,0
764	ld r4,last_task_used_altivec@got(r2)	764	ld r4,last_task_used_altivec@got(r2)
765	std r5,0(r4)	765	std r5,0(r4)
766	#endif /* CONFIG_SMP */	766	#endif /* CONFIG_SMP */
767	blr	767	blr
768		768
769	#endif /* CONFIG_ALTIVEC */	769	#endif /* CONFIG_ALTIVEC */
770		770
771	_GLOBAL(__setup_cpu_power3)	771	_GLOBAL(__setup_cpu_power3)
772	blr	772	blr
773		773
774	_GLOBAL(execve)	774	_GLOBAL(execve)
775	li r0,__NR_execve	775	li r0,__NR_execve
776	sc	776	sc
777	bnslr	777	bnslr
778	neg r3,r3	778	neg r3,r3
779	blr	779	blr
780		780
781	/* kexec_wait(phys_cpu)	781	/* kexec_wait(phys_cpu)
782	*	782	*
783	* wait for the flag to change, indicating this kernel is going away but	783	* wait for the flag to change, indicating this kernel is going away but
784	* the slave code for the next one is at addresses 0 to 100.	784	* the slave code for the next one is at addresses 0 to 100.
785	*	785	*
786	* This is used by all slaves.	786	* This is used by all slaves.
787	*	787	*
788	* Physical (hardware) cpu id should be in r3.	788	* Physical (hardware) cpu id should be in r3.
789	*/	789	*/
790	_GLOBAL(kexec_wait)	790	_GLOBAL(kexec_wait)
791	bl 1f	791	bl 1f
792	1: mflr r5	792	1: mflr r5
793	addi r5,r5,kexec_flag-1b	793	addi r5,r5,kexec_flag-1b
794		794
795	99: HMT_LOW	795	99: HMT_LOW
796	#ifdef CONFIG_KEXEC /* use no memory without kexec */	796	#ifdef CONFIG_KEXEC /* use no memory without kexec */
797	lwz r4,0(r5)	797	lwz r4,0(r5)
798	cmpwi 0,r4,0	798	cmpwi 0,r4,0
799	bnea 0x60	799	bnea 0x60
800	#endif	800	#endif
801	b 99b	801	b 99b
802		802
803	/* this can be in text because we won't change it until we are	803	/* this can be in text because we won't change it until we are
804	* running in real anyways	804	* running in real anyways
805	*/	805	*/
806	kexec_flag:	806	kexec_flag:
807	.long 0	807	.long 0
808		808
809		809
810	#ifdef CONFIG_KEXEC	810	#ifdef CONFIG_KEXEC
811		811
812	/* kexec_smp_wait(void)	812	/* kexec_smp_wait(void)
813	*	813	*
814	* call with interrupts off	814	* call with interrupts off
815	* note: this is a terminal routine, it does not save lr	815	* note: this is a terminal routine, it does not save lr
816	*	816	*
817	* get phys id from paca	817	* get phys id from paca
818	* set paca id to -1 to say we got here	818	* set paca id to -1 to say we got here
819	* switch to real mode	819	* switch to real mode
820	* join other cpus in kexec_wait(phys_id)	820	* join other cpus in kexec_wait(phys_id)
821	*/	821	*/
822	_GLOBAL(kexec_smp_wait)	822	_GLOBAL(kexec_smp_wait)
823	lhz r3,PACAHWCPUID(r13)	823	lhz r3,PACAHWCPUID(r13)
824	li r4,-1	824	li r4,-1
825	sth r4,PACAHWCPUID(r13) /* let others know we left */	825	sth r4,PACAHWCPUID(r13) /* let others know we left */
826	bl real_mode	826	bl real_mode
827	b .kexec_wait	827	b .kexec_wait
828		828
829	/*	829	/*
830	* switch to real mode (turn mmu off)	830	* switch to real mode (turn mmu off)
831	* we use the early kernel trick that the hardware ignores bits	831	* we use the early kernel trick that the hardware ignores bits
832	* 0 and 1 (big endian) of the effective address in real mode	832	* 0 and 1 (big endian) of the effective address in real mode
833	*	833	*
834	* don't overwrite r3 here, it is live for kexec_wait above.	834	* don't overwrite r3 here, it is live for kexec_wait above.
835	*/	835	*/
836	real_mode: /* assume normal blr return */	836	real_mode: /* assume normal blr return */
837	1: li r9,MSR_RI	837	1: li r9,MSR_RI
838	li r10,MSR_DR\|MSR_IR	838	li r10,MSR_DR\|MSR_IR
839	mflr r11 /* return address to SRR0 */	839	mflr r11 /* return address to SRR0 */
840	mfmsr r12	840	mfmsr r12
841	andc r9,r12,r9	841	andc r9,r12,r9
842	andc r10,r12,r10	842	andc r10,r12,r10
843		843
844	mtmsrd r9,1	844	mtmsrd r9,1
845	mtspr SPRN_SRR1,r10	845	mtspr SPRN_SRR1,r10
846	mtspr SPRN_SRR0,r11	846	mtspr SPRN_SRR0,r11
847	rfid	847	rfid
848		848
849		849
850	/*	850	/*
851	* kexec_sequence(newstack, start, image, control, clear_all())	851	* kexec_sequence(newstack, start, image, control, clear_all())
852	*	852	*
853	* does the grungy work with stack switching and real mode switches	853	* does the grungy work with stack switching and real mode switches
854	* also does simple calls to other code	854	* also does simple calls to other code
855	*/	855	*/
856		856
857	_GLOBAL(kexec_sequence)	857	_GLOBAL(kexec_sequence)
858	mflr r0	858	mflr r0
859	std r0,16(r1)	859	std r0,16(r1)
860		860
861	/* switch stacks to newstack -- &kexec_stack.stack */	861	/* switch stacks to newstack -- &kexec_stack.stack */
862	stdu r1,THREAD_SIZE-112(r3)	862	stdu r1,THREAD_SIZE-112(r3)
863	mr r1,r3	863	mr r1,r3
864		864
865	li r0,0	865	li r0,0
866	std r0,16(r1)	866	std r0,16(r1)
867		867
868	/* save regs for local vars on new stack.	868	/* save regs for local vars on new stack.
869	* yes, we won't go back, but ...	869	* yes, we won't go back, but ...
870	*/	870	*/
871	std r31,-8(r1)	871	std r31,-8(r1)
872	std r30,-16(r1)	872	std r30,-16(r1)
873	std r29,-24(r1)	873	std r29,-24(r1)
874	std r28,-32(r1)	874	std r28,-32(r1)
875	std r27,-40(r1)	875	std r27,-40(r1)
876	std r26,-48(r1)	876	std r26,-48(r1)
877	std r25,-56(r1)	877	std r25,-56(r1)
878		878
879	stdu r1,-112-64(r1)	879	stdu r1,-112-64(r1)
880		880
881	/* save args into preserved regs */	881	/* save args into preserved regs */
882	mr r31,r3 /* newstack (both) */	882	mr r31,r3 /* newstack (both) */
883	mr r30,r4 /* start (real) */	883	mr r30,r4 /* start (real) */
884	mr r29,r5 /* image (virt) */	884	mr r29,r5 /* image (virt) */
885	mr r28,r6 /* control, unused */	885	mr r28,r6 /* control, unused */
886	mr r27,r7 /* clear_all() fn desc */	886	mr r27,r7 /* clear_all() fn desc */
887	mr r26,r8 /* spare */	887	mr r26,r8 /* spare */
888	lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */	888	lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
889		889
890	/* disable interrupts, we are overwriting kernel data next */	890	/* disable interrupts, we are overwriting kernel data next */
891	mfmsr r3	891	mfmsr r3
892	rlwinm r3,r3,0,17,15	892	rlwinm r3,r3,0,17,15
893	mtmsrd r3,1	893	mtmsrd r3,1
894		894
895	/* copy dest pages, flush whole dest image */	895	/* copy dest pages, flush whole dest image */
896	mr r3,r29	896	mr r3,r29
897	bl .kexec_copy_flush /* (image) */	897	bl .kexec_copy_flush /* (image) */
898		898
899	/* turn off mmu */	899	/* turn off mmu */
900	bl real_mode	900	bl real_mode
901		901
902	/* clear out hardware hash page table and tlb */	902	/* clear out hardware hash page table and tlb */
903	ld r5,0(r27) /* deref function descriptor */	903	ld r5,0(r27) /* deref function descriptor */
904	mtctr r5	904	mtctr r5
905	bctrl /* ppc_md.hash_clear_all(void); */	905	bctrl /* ppc_md.hash_clear_all(void); */
906		906
907	/*	907	/*
908	* kexec image calling is:	908	* kexec image calling is:
909	* the first 0x100 bytes of the entry point are copied to 0	909	* the first 0x100 bytes of the entry point are copied to 0
910	*	910	*
911	* all slaves branch to slave = 0x60 (absolute)	911	* all slaves branch to slave = 0x60 (absolute)
912	* slave(phys_cpu_id);	912	* slave(phys_cpu_id);
913	*	913	*
914	* master goes to start = entry point	914	* master goes to start = entry point
915	* start(phys_cpu_id, start, 0);	915	* start(phys_cpu_id, start, 0);
916	*	916	*
917	*	917	*
918	* a wrapper is needed to call existing kernels, here is an approximate	918	* a wrapper is needed to call existing kernels, here is an approximate
919	* description of one method:	919	* description of one method:
920	*	920	*
921	* v2: (2.6.10)	921	* v2: (2.6.10)
922	* start will be near the boot_block (maybe 0x100 bytes before it?)	922	* start will be near the boot_block (maybe 0x100 bytes before it?)
923	* it will have a 0x60, which will b to boot_block, where it will wait	923	* it will have a 0x60, which will b to boot_block, where it will wait
924	* and 0 will store phys into struct boot-block and load r3 from there,	924	* and 0 will store phys into struct boot-block and load r3 from there,
925	* copy kernel 0-0x100 and tell slaves to back down to 0x60 again	925	* copy kernel 0-0x100 and tell slaves to back down to 0x60 again
926	*	926	*
927	* v1: (2.6.9)	927	* v1: (2.6.9)
928	* boot block will have all cpus scanning device tree to see if they	928	* boot block will have all cpus scanning device tree to see if they
929	* are the boot cpu ?????	929	* are the boot cpu ?????
930	* other device tree differences (prop sizes, va vs pa, etc)...	930	* other device tree differences (prop sizes, va vs pa, etc)...
931	*/	931	*/
932		932
933	/* copy 0x100 bytes starting at start to 0 */	933	/* copy 0x100 bytes starting at start to 0 */
934	li r3,0	934	li r3,0
935	mr r4,r30	935	mr r4,r30
936	li r5,0x100	936	li r5,0x100
937	li r6,0	937	li r6,0
938	bl .copy_and_flush /* (dest, src, copy limit, start offset) */	938	bl .copy_and_flush /* (dest, src, copy limit, start offset) */
939	1: /* assume normal blr return */	939	1: /* assume normal blr return */
940		940
941	/* release other cpus to the new kernel secondary start at 0x60 */	941	/* release other cpus to the new kernel secondary start at 0x60 */
942	mflr r5	942	mflr r5
943	li r6,1	943	li r6,1
944	stw r6,kexec_flag-1b(5)	944	stw r6,kexec_flag-1b(5)
945	mr r3,r25 # my phys cpu	945	mr r3,r25 # my phys cpu
946	mr r4,r30 # start, aka phys mem offset	946	mr r4,r30 # start, aka phys mem offset
947	mtlr 4	947	mtlr 4
948	li r5,0	948	li r5,0
949	blr /* image->start(physid, image->start, 0); */	949	blr /* image->start(physid, image->start, 0); */
950	#endif /* CONFIG_KEXEC */	950	#endif /* CONFIG_KEXEC */
951		951

arch/powerpc/platforms/iseries/irq.c

Diff comments View file @ d4be4f3

 /*
  * This module supports the iSeries PCI bus interrupt handling
  * Copyright (C) 20yy  <Robert L Holtorf> <IBM Corp>
  * Copyright (C) 2004-2005 IBM Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the:
  * Free Software Foundation, Inc.,
  * 59 Temple Place, Suite 330,
  * Boston, MA  02111-1307  USA
  *
  * Change Activity:
  *   Created, December 13, 2000 by Wayne Holm
  * End Change Activity
  */
 #include <linux/config.h>
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/threads.h>
 #include <linux/smp.h>
 #include <linux/param.h>
 #include <linux/string.h>
 #include <linux/bootmem.h>
 #include <linux/ide.h>
 #include <linux/irq.h>
 #include <linux/spinlock.h>
 #include <asm/iseries/hv_types.h>
 #include <asm/iseries/hv_lp_event.h>
 #include <asm/iseries/hv_call_xm.h>
 #include "irq.h"
 #include "call_pci.h"
 /* This maps virtual irq numbers to real irqs */
 unsigned int virt_irq_to_real_map[NR_IRQS];
 /* The next available virtual irq number */
 /* Note: the pcnet32 driver assumes irq numbers < 2 aren't valid. :( */
 static int next_virtual_irq = 2;
 static long Pci_Interrupt_Count;
 static long Pci_Event_Count;
 enum XmPciLpEvent_Subtype {
 	XmPciLpEvent_BusCreated		= 0,	// PHB has been created
 	XmPciLpEvent_BusError		= 1,	// PHB has failed
 	XmPciLpEvent_BusFailed		= 2,	// Msg to Secondary, Primary failed bus
 	XmPciLpEvent_NodeFailed		= 4,	// Multi-adapter bridge has failed
 	XmPciLpEvent_NodeRecovered	= 5,	// Multi-adapter bridge has recovered
 	XmPciLpEvent_BusRecovered	= 12,	// PHB has been recovered
 	XmPciLpEvent_UnQuiesceBus	= 18,	// Secondary bus unqiescing
 	XmPciLpEvent_BridgeError	= 21,	// Bridge Error
 	XmPciLpEvent_SlotInterrupt	= 22	// Slot interrupt
 };
 struct XmPciLpEvent_BusInterrupt {
 	HvBusNumber	busNumber;
 	HvSubBusNumber	subBusNumber;
 };
 struct XmPciLpEvent_NodeInterrupt {
 	HvBusNumber	busNumber;
 	HvSubBusNumber	subBusNumber;
 	HvAgentId	deviceId;
 };
 struct XmPciLpEvent {
 	struct HvLpEvent hvLpEvent;
 	union {
 		u64 alignData;			// Align on an 8-byte boundary
 		struct {
 			u32		fisr;
 			HvBusNumber	busNumber;
 			HvSubBusNumber	subBusNumber;
 			HvAgentId	deviceId;
 		} slotInterrupt;
 		struct XmPciLpEvent_BusInterrupt busFailed;
 		struct XmPciLpEvent_BusInterrupt busRecovered;
 		struct XmPciLpEvent_BusInterrupt busCreated;
 		struct XmPciLpEvent_NodeInterrupt nodeFailed;
 		struct XmPciLpEvent_NodeInterrupt nodeRecovered;
 	} eventData;
 };
 static void intReceived(struct XmPciLpEvent *eventParm,
 		struct pt_regs *regsParm)
 {
 	int irq;
 #ifdef CONFIG_IRQSTACKS
 	struct thread_info *curtp, *irqtp;
 #endif
 	++Pci_Interrupt_Count;
 	switch (eventParm->hvLpEvent.xSubtype) {
 	case XmPciLpEvent_SlotInterrupt:
 		irq = eventParm->hvLpEvent.xCorrelationToken;
 		/* Dispatch the interrupt handlers for this irq */
 #ifdef CONFIG_IRQSTACKS
 		/* Switch to the irq stack to handle this */
 		curtp = current_thread_info();
 		irqtp = hardirq_ctx[smp_processor_id()];
 		if (curtp != irqtp) {
 			irqtp->task = curtp->task;
 			irqtp->flags = 0;
-			call_ppc_irq_dispatch_handler(regsParm, irq, irqtp);
+			call___do_IRQ(irq, regsParm, irqtp);
 			irqtp->task = NULL;
 			if (irqtp->flags)
 				set_bits(irqtp->flags, &curtp->flags);
 		} else
 #endif
-			ppc_irq_dispatch_handler(regsParm, irq);
+			__do_IRQ(irq, regsParm);
 		HvCallPci_eoi(eventParm->eventData.slotInterrupt.busNumber,
 			eventParm->eventData.slotInterrupt.subBusNumber,
 			eventParm->eventData.slotInterrupt.deviceId);
 		break;
 		/* Ignore error recovery events for now */
 	case XmPciLpEvent_BusCreated:
 		printk(KERN_INFO "intReceived: system bus %d created\n",
 			eventParm->eventData.busCreated.busNumber);
 		break;
 	case XmPciLpEvent_BusError:
 	case XmPciLpEvent_BusFailed:
 		printk(KERN_INFO "intReceived: system bus %d failed\n",
 			eventParm->eventData.busFailed.busNumber);
 		break;
 	case XmPciLpEvent_BusRecovered:
 	case XmPciLpEvent_UnQuiesceBus:
 		printk(KERN_INFO "intReceived: system bus %d recovered\n",
 			eventParm->eventData.busRecovered.busNumber);
 		break;
 	case XmPciLpEvent_NodeFailed:
 	case XmPciLpEvent_BridgeError:
 		printk(KERN_INFO
 			"intReceived: multi-adapter bridge %d/%d/%d failed\n",
 			eventParm->eventData.nodeFailed.busNumber,
 			eventParm->eventData.nodeFailed.subBusNumber,
 			eventParm->eventData.nodeFailed.deviceId);
 		break;
 	case XmPciLpEvent_NodeRecovered:
 		printk(KERN_INFO
 			"intReceived: multi-adapter bridge %d/%d/%d recovered\n",
 			eventParm->eventData.nodeRecovered.busNumber,
 			eventParm->eventData.nodeRecovered.subBusNumber,
 			eventParm->eventData.nodeRecovered.deviceId);
 		break;
 	default:
 		printk(KERN_ERR
 			"intReceived: unrecognized event subtype 0x%x\n",
 			eventParm->hvLpEvent.xSubtype);
 		break;
 	}
 }
 static void XmPciLpEvent_handler(struct HvLpEvent *eventParm,
 		struct pt_regs *regsParm)
 {
 #ifdef CONFIG_PCI
 	++Pci_Event_Count;
 	if (eventParm && (eventParm->xType == HvLpEvent_Type_PciIo)) {
 		switch (eventParm->xFlags.xFunction) {
 		case HvLpEvent_Function_Int:
 			intReceived((struct XmPciLpEvent *)eventParm, regsParm);
 			break;
 		case HvLpEvent_Function_Ack:
 			printk(KERN_ERR
 				"XmPciLpEvent_handler: unexpected ack received\n");
 			break;
 		default:
 			printk(KERN_ERR
 				"XmPciLpEvent_handler: unexpected event function %d\n",
 				(int)eventParm->xFlags.xFunction);
 			break;
 		}
 	} else if (eventParm)
 		printk(KERN_ERR
 			"XmPciLpEvent_handler: Unrecognized PCI event type 0x%x\n",
 			(int)eventParm->xType);
 	else
 		printk(KERN_ERR "XmPciLpEvent_handler: NULL event received\n");
 #endif
 }
 /*
  * This is called by init_IRQ.  set in ppc_md.init_IRQ by iSeries_setup.c
  * It must be called before the bus walk.
  */
 void __init iSeries_init_IRQ(void)
 {
 	/* Register PCI event handler and open an event path */
 	int xRc;
 	xRc = HvLpEvent_registerHandler(HvLpEvent_Type_PciIo,
 			&XmPciLpEvent_handler);
 	if (xRc == 0) {
 		xRc = HvLpEvent_openPath(HvLpEvent_Type_PciIo, 0);
 		if (xRc != 0)
 			printk(KERN_ERR "iSeries_init_IRQ: open event path "
 					"failed with rc 0x%x\n", xRc);
 	} else
 		printk(KERN_ERR "iSeries_init_IRQ: register handler "
 				"failed with rc 0x%x\n", xRc);
 }
 #define REAL_IRQ_TO_BUS(irq)	((((irq) >> 6) & 0xff) + 1)
 #define REAL_IRQ_TO_IDSEL(irq)	((((irq) >> 3) & 7) + 1)
 #define REAL_IRQ_TO_FUNC(irq)	((irq) & 7)
 /*
  * This will be called by device drivers (via enable_IRQ)
  * to enable INTA in the bridge interrupt status register.
  */
 static void iSeries_enable_IRQ(unsigned int irq)
 {
 	u32 bus, deviceId, function, mask;
 	const u32 subBus = 0;
 	unsigned int rirq = virt_irq_to_real_map[irq];
 	/* The IRQ has already been locked by the caller */
 	bus = REAL_IRQ_TO_BUS(rirq);
 	function = REAL_IRQ_TO_FUNC(rirq);
 	deviceId = (REAL_IRQ_TO_IDSEL(rirq) << 4) + function;
 	/* Unmask secondary INTA */
 	mask = 0x80000000;
 	HvCallPci_unmaskInterrupts(bus, subBus, deviceId, mask);
 }
 /* This is called by iSeries_activate_IRQs */
 static unsigned int iSeries_startup_IRQ(unsigned int irq)
 {
 	u32 bus, deviceId, function, mask;
 	const u32 subBus = 0;
 	unsigned int rirq = virt_irq_to_real_map[irq];
 	bus = REAL_IRQ_TO_BUS(rirq);
 	function = REAL_IRQ_TO_FUNC(rirq);
 	deviceId = (REAL_IRQ_TO_IDSEL(rirq) << 4) + function;
 	/* Link the IRQ number to the bridge */
 	HvCallXm_connectBusUnit(bus, subBus, deviceId, irq);
 	/* Unmask bridge interrupts in the FISR */
 	mask = 0x01010000 << function;
 	HvCallPci_unmaskFisr(bus, subBus, deviceId, mask);
 	iSeries_enable_IRQ(irq);
 	return 0;
 }
 /*
  * This is called out of iSeries_fixup to activate interrupt
  * generation for usable slots
  */
 void __init iSeries_activate_IRQs()
 {
 	int irq;
 	unsigned long flags;
 	for_each_irq (irq) {
 		irq_desc_t *desc = get_irq_desc(irq);
 		if (desc && desc->handler && desc->handler->startup) {
 			spin_lock_irqsave(&desc->lock, flags);
 			desc->handler->startup(irq);
 			spin_unlock_irqrestore(&desc->lock, flags);
 		}
 	}
 }
 /*  this is not called anywhere currently */
 static void iSeries_shutdown_IRQ(unsigned int irq)
 {
 	u32 bus, deviceId, function, mask;
 	const u32 subBus = 0;
 	unsigned int rirq = virt_irq_to_real_map[irq];
 	/* irq should be locked by the caller */
 	bus = REAL_IRQ_TO_BUS(rirq);
 	function = REAL_IRQ_TO_FUNC(rirq);
 	deviceId = (REAL_IRQ_TO_IDSEL(rirq) << 4) + function;
 	/* Invalidate the IRQ number in the bridge */
 	HvCallXm_connectBusUnit(bus, subBus, deviceId, 0);
 	/* Mask bridge interrupts in the FISR */
 	mask = 0x01010000 << function;
 	HvCallPci_maskFisr(bus, subBus, deviceId, mask);
 }
 /*
  * This will be called by device drivers (via disable_IRQ)
  * to disable INTA in the bridge interrupt status register.
  */
 static void iSeries_disable_IRQ(unsigned int irq)
 {
 	u32 bus, deviceId, function, mask;
 	const u32 subBus = 0;
 	unsigned int rirq = virt_irq_to_real_map[irq];
 	/* The IRQ has already been locked by the caller */
 	bus = REAL_IRQ_TO_BUS(rirq);
 	function = REAL_IRQ_TO_FUNC(rirq);
 	deviceId = (REAL_IRQ_TO_IDSEL(rirq) << 4) + function;
 	/* Mask secondary INTA   */
 	mask = 0x80000000;
 	HvCallPci_maskInterrupts(bus, subBus, deviceId, mask);
 }
 /*
- * Need to define this so ppc_irq_dispatch_handler will NOT call
+ * This does nothing because there is not enough information
- * enable_IRQ at the end of interrupt handling.  However, this does
+ * provided to do the EOI HvCall.  This is done by XmPciLpEvent.c
- * nothing because there is not enough information provided to do
- * the EOI HvCall.  This is done by XmPciLpEvent.c
  */
 static void iSeries_end_IRQ(unsigned int irq)
 {
 }
 static hw_irq_controller iSeries_IRQ_handler = {
 	.typename = "iSeries irq controller",
 	.startup = iSeries_startup_IRQ,
 	.shutdown = iSeries_shutdown_IRQ,
 	.enable = iSeries_enable_IRQ,
 	.disable = iSeries_disable_IRQ,
 	.end = iSeries_end_IRQ
 };
 /*
  * This is called out of iSeries_scan_slot to allocate an IRQ for an EADS slot
  * It calculates the irq value for the slot.
  * Note that subBusNumber is always 0 (at the moment at least).
  */
 int __init iSeries_allocate_IRQ(HvBusNumber busNumber,
 		HvSubBusNumber subBusNumber, HvAgentId deviceId)
 {
 	unsigned int realirq, virtirq;
 	u8 idsel = (deviceId >> 4);
 	u8 function = deviceId & 7;
 	virtirq = next_virtual_irq++;
 	realirq = ((busNumber - 1) << 6) + ((idsel - 1) << 3) + function;
 	virt_irq_to_real_map[virtirq] = realirq;
 	irq_desc[virtirq].handler = &iSeries_IRQ_handler;
 	return virtirq;
 }
 int virt_irq_create_mapping(unsigned int real_irq)
 {
 	BUG(); /* Don't call this on iSeries, yet */
 	return 0;
 }
 void virt_irq_init(void)
 {
 	return;
 }

arch/powerpc/platforms/pseries/xics.c

Diff comments View file @ d4be4f3

 /*
  * arch/powerpc/platforms/pseries/xics.c
  *
  * Copyright 2000 IBM Corporation.
  *
  *  This program is free software; you can redistribute it and/or
  *  modify it under the terms of the GNU General Public License
  *  as published by the Free Software Foundation; either version
  *  2 of the License, or (at your option) any later version.
  */
 #include <linux/config.h>
 #include <linux/types.h>
 #include <linux/threads.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
 #include <linux/smp.h>
 #include <linux/interrupt.h>
 #include <linux/signal.h>
 #include <linux/init.h>
 #include <linux/gfp.h>
 #include <linux/radix-tree.h>
 #include <linux/cpu.h>
 #include <asm/prom.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/smp.h>
 #include <asm/rtas.h>
 #include <asm/hvcall.h>
 #include <asm/machdep.h>
 #include <asm/i8259.h>
 #include "xics.h"
 static unsigned int xics_startup(unsigned int irq);
 static void xics_enable_irq(unsigned int irq);
 static void xics_disable_irq(unsigned int irq);
 static void xics_mask_and_ack_irq(unsigned int irq);
 static void xics_end_irq(unsigned int irq);
 static void xics_set_affinity(unsigned int irq_nr, cpumask_t cpumask);
 static struct hw_interrupt_type xics_pic = {
 	.typename = " XICS     ",
 	.startup = xics_startup,
 	.enable = xics_enable_irq,
 	.disable = xics_disable_irq,
 	.ack = xics_mask_and_ack_irq,
 	.end = xics_end_irq,
 	.set_affinity = xics_set_affinity
 };
 static struct hw_interrupt_type xics_8259_pic = {
 	.typename = " XICS/8259",
 	.ack = xics_mask_and_ack_irq,
 };
 /* This is used to map real irq numbers to virtual */
 static struct radix_tree_root irq_map = RADIX_TREE_INIT(GFP_ATOMIC);
 #define XICS_IPI		2
 #define XICS_IRQ_SPURIOUS	0
 /* Want a priority other than 0.  Various HW issues require this. */
 #define	DEFAULT_PRIORITY	5
 /*
  * Mark IPIs as higher priority so we can take them inside interrupts that
  * arent marked SA_INTERRUPT
  */
 #define IPI_PRIORITY		4
 struct xics_ipl {
 	union {
 		u32 word;
 		u8 bytes[4];
 	} xirr_poll;
 	union {
 		u32 word;
 		u8 bytes[4];
 	} xirr;
 	u32 dummy;
 	union {
 		u32 word;
 		u8 bytes[4];
 	} qirr;
 };
 static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
 static int xics_irq_8259_cascade = 0;
 static int xics_irq_8259_cascade_real = 0;
 static unsigned int default_server = 0xFF;
 static unsigned int default_distrib_server = 0;
 static unsigned int interrupt_server_size = 8;
 /*
  * XICS only has a single IPI, so encode the messages per CPU
  */
 struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
 /* RTAS service tokens */
 static int ibm_get_xive;
 static int ibm_set_xive;
 static int ibm_int_on;
 static int ibm_int_off;
 typedef struct {
 	int (*xirr_info_get)(int cpu);
 	void (*xirr_info_set)(int cpu, int val);
 	void (*cppr_info)(int cpu, u8 val);
 	void (*qirr_info)(int cpu, u8 val);
 } xics_ops;
 /* SMP */
 static int pSeries_xirr_info_get(int n_cpu)
 {
 	return in_be32(&xics_per_cpu[n_cpu]->xirr.word);
 }
 static void pSeries_xirr_info_set(int n_cpu, int value)
 {
 	out_be32(&xics_per_cpu[n_cpu]->xirr.word, value);
 }
 static void pSeries_cppr_info(int n_cpu, u8 value)
 {
 	out_8(&xics_per_cpu[n_cpu]->xirr.bytes[0], value);
 }
 static void pSeries_qirr_info(int n_cpu, u8 value)
 {
 	out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
 }
 static xics_ops pSeries_ops = {
 	pSeries_xirr_info_get,
 	pSeries_xirr_info_set,
 	pSeries_cppr_info,
 	pSeries_qirr_info
 };
 static xics_ops *ops = &pSeries_ops;
 /* LPAR */
 static inline long plpar_eoi(unsigned long xirr)
 {
 	return plpar_hcall_norets(H_EOI, xirr);
 }
 static inline long plpar_cppr(unsigned long cppr)
 {
 	return plpar_hcall_norets(H_CPPR, cppr);
 }
 static inline long plpar_ipi(unsigned long servernum, unsigned long mfrr)
 {
 	return plpar_hcall_norets(H_IPI, servernum, mfrr);
 }
 static inline long plpar_xirr(unsigned long *xirr_ret)
 {
 	unsigned long dummy;
 	return plpar_hcall(H_XIRR, 0, 0, 0, 0, xirr_ret, &dummy, &dummy);
 }
 static int pSeriesLP_xirr_info_get(int n_cpu)
 {
 	unsigned long lpar_rc;
 	unsigned long return_value;
 	lpar_rc = plpar_xirr(&return_value);
 	if (lpar_rc != H_Success)
 		panic(" bad return code xirr - rc = %lx \n", lpar_rc);
 	return (int)return_value;
 }
 static void pSeriesLP_xirr_info_set(int n_cpu, int value)
 {
 	unsigned long lpar_rc;
 	unsigned long val64 = value & 0xffffffff;
 	lpar_rc = plpar_eoi(val64);
 	if (lpar_rc != H_Success)
 		panic("bad return code EOI - rc = %ld, value=%lx\n", lpar_rc,
 		      val64);
 }
 void pSeriesLP_cppr_info(int n_cpu, u8 value)
 {
 	unsigned long lpar_rc;
 	lpar_rc = plpar_cppr(value);
 	if (lpar_rc != H_Success)
 		panic("bad return code cppr - rc = %lx\n", lpar_rc);
 }
 static void pSeriesLP_qirr_info(int n_cpu , u8 value)
 {
 	unsigned long lpar_rc;
 	lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
 	if (lpar_rc != H_Success)
 		panic("bad return code qirr - rc = %lx\n", lpar_rc);
 }
 xics_ops pSeriesLP_ops = {
 	pSeriesLP_xirr_info_get,
 	pSeriesLP_xirr_info_set,
 	pSeriesLP_cppr_info,
 	pSeriesLP_qirr_info
 };
 static unsigned int xics_startup(unsigned int virq)
 {
 	unsigned int irq;
 	irq = irq_offset_down(virq);
 	if (radix_tree_insert(&irq_map, virt_irq_to_real(irq),
 			      &virt_irq_to_real_map[irq]) == -ENOMEM)
 		printk(KERN_CRIT "Out of memory creating real -> virtual"
 		       " IRQ mapping for irq %u (real 0x%x)\n",
 		       virq, virt_irq_to_real(irq));
 	xics_enable_irq(virq);
 	return 0;	/* return value is ignored */
 }
 static unsigned int real_irq_to_virt(unsigned int real_irq)
 {
 	unsigned int *ptr;
 	ptr = radix_tree_lookup(&irq_map, real_irq);
 	if (ptr == NULL)
 		return NO_IRQ;
 	return ptr - virt_irq_to_real_map;
 }
 #ifdef CONFIG_SMP
 static int get_irq_server(unsigned int irq)
 {
 	unsigned int server;
 	/* For the moment only implement delivery to all cpus or one cpu */
 	cpumask_t cpumask = irq_affinity[irq];
 	cpumask_t tmp = CPU_MASK_NONE;
 	if (!distribute_irqs)
 		return default_server;
 	if (cpus_equal(cpumask, CPU_MASK_ALL)) {
 		server = default_distrib_server;
 	} else {
 		cpus_and(tmp, cpu_online_map, cpumask);
 		if (cpus_empty(tmp))
 			server = default_distrib_server;
 		else
 			server = get_hard_smp_processor_id(first_cpu(tmp));
 	}
 	return server;
 }
 #else
 static int get_irq_server(unsigned int irq)
 {
 	return default_server;
 }
 #endif
 static void xics_enable_irq(unsigned int virq)
 {
 	unsigned int irq;
 	int call_status;
 	unsigned int server;
 	irq = virt_irq_to_real(irq_offset_down(virq));
 	if (irq == XICS_IPI)
 		return;
 	server = get_irq_server(virq);
 	call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
 				DEFAULT_PRIORITY);
 	if (call_status != 0) {
 		printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_set_xive "
 		       "returned %d\n", irq, call_status);
 		printk("set_xive %x, server %x\n", ibm_set_xive, server);
 		return;
 	}
 	/* Now unmask the interrupt (often a no-op) */
 	call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
 	if (call_status != 0) {
 		printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_int_on "
 		       "returned %d\n", irq, call_status);
 		return;
 	}
 }
 static void xics_disable_real_irq(unsigned int irq)
 {
 	int call_status;
 	unsigned int server;
 	if (irq == XICS_IPI)
 		return;
 	call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
 	if (call_status != 0) {
 		printk(KERN_ERR "xics_disable_real_irq: irq=%u: "
 		       "ibm_int_off returned %d\n", irq, call_status);
 		return;
 	}
 	server = get_irq_server(irq);
 	/* Have to set XIVE to 0xff to be able to remove a slot */
 	call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, 0xff);
 	if (call_status != 0) {
 		printk(KERN_ERR "xics_disable_irq: irq=%u: ibm_set_xive(0xff)"
 		       " returned %d\n", irq, call_status);
 		return;
 	}
 }
 static void xics_disable_irq(unsigned int virq)
 {
 	unsigned int irq;
 	irq = virt_irq_to_real(irq_offset_down(virq));
 	xics_disable_real_irq(irq);
 }
 static void xics_end_irq(unsigned int irq)
 {
 	int cpu = smp_processor_id();
 	iosync();
 	ops->xirr_info_set(cpu, ((0xff << 24) |
 				 (virt_irq_to_real(irq_offset_down(irq)))));
 }
 static void xics_mask_and_ack_irq(unsigned int irq)
 {
 	int cpu = smp_processor_id();
 	if (irq < irq_offset_value()) {
 		i8259_pic.ack(irq);
 		iosync();
 		ops->xirr_info_set(cpu, ((0xff<<24) |
 					 xics_irq_8259_cascade_real));
 		iosync();
 	}
 }
 int xics_get_irq(struct pt_regs *regs)
 {
 	unsigned int cpu = smp_processor_id();
 	unsigned int vec;
 	int irq;
 	vec = ops->xirr_info_get(cpu);
 	/*  (vec >> 24) == old priority */
 	vec &= 0x00ffffff;
 	/* for sanity, this had better be < NR_IRQS - 16 */
 	if (vec == xics_irq_8259_cascade_real) {
 		irq = i8259_irq(regs);
 		if (irq == -1) {
 			/* Spurious cascaded interrupt.  Still must ack xics */
 			xics_end_irq(irq_offset_up(xics_irq_8259_cascade));
 			irq = -1;
 		}
 	} else if (vec == XICS_IRQ_SPURIOUS) {
 		irq = -1;
 	} else {
 		irq = real_irq_to_virt(vec);
 		if (irq == NO_IRQ)
 			irq = real_irq_to_virt_slowpath(vec);
 		if (irq == NO_IRQ) {
 			printk(KERN_ERR "Interrupt %u (real) is invalid,"
 			       " disabling it.\n", vec);
 			xics_disable_real_irq(vec);
 		} else
 			irq = irq_offset_up(irq);
 	}
 	return irq;
 }
 #ifdef CONFIG_SMP
 irqreturn_t xics_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
 {
 	int cpu = smp_processor_id();
 	ops->qirr_info(cpu, 0xff);
 	WARN_ON(cpu_is_offline(cpu));
 	while (xics_ipi_message[cpu].value) {
 		if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
 				       &xics_ipi_message[cpu].value)) {
 			mb();
 			smp_message_recv(PPC_MSG_CALL_FUNCTION, regs);
 		}
 		if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
 				       &xics_ipi_message[cpu].value)) {
 			mb();
 			smp_message_recv(PPC_MSG_RESCHEDULE, regs);
 		}
 #if 0
 		if (test_and_clear_bit(PPC_MSG_MIGRATE_TASK,
 				       &xics_ipi_message[cpu].value)) {
 			mb();
 			smp_message_recv(PPC_MSG_MIGRATE_TASK, regs);
 		}
 #endif
 #ifdef CONFIG_DEBUGGER
 		if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
 				       &xics_ipi_message[cpu].value)) {
 			mb();
 			smp_message_recv(PPC_MSG_DEBUGGER_BREAK, regs);
 		}
 #endif
 	}
 	return IRQ_HANDLED;
 }
 void xics_cause_IPI(int cpu)
 {
 	ops->qirr_info(cpu, IPI_PRIORITY);
 }
 #endif /* CONFIG_SMP */
 void xics_setup_cpu(void)
 {
 	int cpu = smp_processor_id();
 	ops->cppr_info(cpu, 0xff);
 	iosync();
 	/*
 	 * Put the calling processor into the GIQ.  This is really only
 	 * necessary from a secondary thread as the OF start-cpu interface
 	 * performs this function for us on primary threads.
 	 *
 	 * XXX: undo of teardown on kexec needs this too, as may hotplug
 	 */
 	rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE,
 		(1UL << interrupt_server_size) - 1 - default_distrib_server, 1);
 }
 void xics_init_IRQ(void)
 {
 	int i;
 	unsigned long intr_size = 0;
 	struct device_node *np;
 	uint *ireg, ilen, indx = 0;
 	unsigned long intr_base = 0;
 	struct xics_interrupt_node {
 		unsigned long addr;
 		unsigned long size;
 	} intnodes[NR_CPUS];
 	ppc64_boot_msg(0x20, "XICS Init");
 	ibm_get_xive = rtas_token("ibm,get-xive");
 	ibm_set_xive = rtas_token("ibm,set-xive");
 	ibm_int_on  = rtas_token("ibm,int-on");
 	ibm_int_off = rtas_token("ibm,int-off");
 	np = of_find_node_by_type(NULL, "PowerPC-External-Interrupt-Presentation");
 	if (!np)
 		panic("xics_init_IRQ: can't find interrupt presentation");
 nextnode:
 	ireg = (uint *)get_property(np, "ibm,interrupt-server-ranges", NULL);
 	if (ireg) {
 		/*
 		 * set node starting index for this node
 		 */
 		indx = *ireg;
 	}
 	ireg = (uint *)get_property(np, "reg", &ilen);
 	if (!ireg)
 		panic("xics_init_IRQ: can't find interrupt reg property");
 	while (ilen) {
 		intnodes[indx].addr = (unsigned long)*ireg++ << 32;
 		ilen -= sizeof(uint);
 		intnodes[indx].addr |= *ireg++;
 		ilen -= sizeof(uint);
 		intnodes[indx].size = (unsigned long)*ireg++ << 32;
 		ilen -= sizeof(uint);
 		intnodes[indx].size |= *ireg++;
 		ilen -= sizeof(uint);
 		indx++;
 		if (indx >= NR_CPUS) break;
 	}
 	np = of_find_node_by_type(np, "PowerPC-External-Interrupt-Presentation");
 	if ((indx < NR_CPUS) && np) goto nextnode;
 	/* Find the server numbers for the boot cpu. */
 	for (np = of_find_node_by_type(NULL, "cpu");
 	     np;
 	     np = of_find_node_by_type(np, "cpu")) {
 		ireg = (uint *)get_property(np, "reg", &ilen);
 		if (ireg && ireg[0] == boot_cpuid_phys) {
 			ireg = (uint *)get_property(np, "ibm,ppc-interrupt-gserver#s",
 						    &ilen);
 			i = ilen / sizeof(int);
 			if (ireg && i > 0) {
 				default_server = ireg[0];
 				default_distrib_server = ireg[i-1]; /* take last element */
 			}
 			ireg = (uint *)get_property(np,
 					"ibm,interrupt-server#-size", NULL);
 			if (ireg)
 				interrupt_server_size = *ireg;
 			break;
 		}
 	}
 	of_node_put(np);
 	intr_base = intnodes[0].addr;
 	intr_size = intnodes[0].size;
 	np = of_find_node_by_type(NULL, "interrupt-controller");
 	if (!np) {
 		printk(KERN_WARNING "xics: no ISA interrupt controller\n");
 		xics_irq_8259_cascade_real = -1;
 		xics_irq_8259_cascade = -1;
 	} else {
 		ireg = (uint *) get_property(np, "interrupts", NULL);
 		if (!ireg)
 			panic("xics_init_IRQ: can't find ISA interrupts property");
 		xics_irq_8259_cascade_real = *ireg;
 		xics_irq_8259_cascade
 			= virt_irq_create_mapping(xics_irq_8259_cascade_real);
 		of_node_put(np);
 	}
 	if (systemcfg->platform == PLATFORM_PSERIES) {
 #ifdef CONFIG_SMP
 		for_each_cpu(i) {
 			int hard_id;
 			/* FIXME: Do this dynamically! --RR */
 			if (!cpu_present(i))
 				continue;
 			hard_id = get_hard_smp_processor_id(i);
 			xics_per_cpu[i] = ioremap(intnodes[hard_id].addr,
 						  intnodes[hard_id].size);
 		}
 #else
 		xics_per_cpu[0] = ioremap(intr_base, intr_size);
 #endif /* CONFIG_SMP */
 	} else if (systemcfg->platform == PLATFORM_PSERIES_LPAR) {
 		ops = &pSeriesLP_ops;
 	}
 	xics_8259_pic.enable = i8259_pic.enable;
 	xics_8259_pic.disable = i8259_pic.disable;
+	xics_8259_pic.end = i8259_pic.end;
 	for (i = 0; i < 16; ++i)
 		get_irq_desc(i)->handler = &xics_8259_pic;
 	for (; i < NR_IRQS; ++i)
 		get_irq_desc(i)->handler = &xics_pic;
 	xics_setup_cpu();
 	ppc64_boot_msg(0x21, "XICS Done");
 }
 /*
  * We cant do this in init_IRQ because we need the memory subsystem up for
  * request_irq()
  */
 static int __init xics_setup_i8259(void)
 {
 	if (ppc64_interrupt_controller == IC_PPC_XIC &&
 	    xics_irq_8259_cascade != -1) {
 		if (request_irq(irq_offset_up(xics_irq_8259_cascade),
 				no_action, 0, "8259 cascade", NULL))
 			printk(KERN_ERR "xics_setup_i8259: couldn't get 8259 "
 					"cascade\n");
 		i8259_init(0, 0);
 	}
 	return 0;
 }
 arch_initcall(xics_setup_i8259);
 #ifdef CONFIG_SMP
 void xics_request_IPIs(void)
 {
 	virt_irq_to_real_map[XICS_IPI] = XICS_IPI;
 	/* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
 	request_irq(irq_offset_up(XICS_IPI), xics_ipi_action, SA_INTERRUPT,
 		    "IPI", NULL);
 	get_irq_desc(irq_offset_up(XICS_IPI))->status |= IRQ_PER_CPU;
 }
 #endif
 static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
 {
 	unsigned int irq;
 	int status;
 	int xics_status[2];
 	unsigned long newmask;
 	cpumask_t tmp = CPU_MASK_NONE;
 	irq = virt_irq_to_real(irq_offset_down(virq));
 	if (irq == XICS_IPI || irq == NO_IRQ)
 		return;
 	status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
 	if (status) {
 		printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive "
 		       "returns %d\n", irq, status);
 		return;
 	}
 	/* For the moment only implement delivery to all cpus or one cpu */
 	if (cpus_equal(cpumask, CPU_MASK_ALL)) {
 		newmask = default_distrib_server;
 	} else {
 		cpus_and(tmp, cpu_online_map, cpumask);
 		if (cpus_empty(tmp))
 			return;
 		newmask = get_hard_smp_processor_id(first_cpu(tmp));
 	}
 	status = rtas_call(ibm_set_xive, 3, 1, NULL,
 				irq, newmask, xics_status[1]);
 	if (status) {
 		printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive "
 		       "returns %d\n", irq, status);
 		return;
 	}
 }
 void xics_teardown_cpu(int secondary)
 {
 	int cpu = smp_processor_id();
 	ops->cppr_info(cpu, 0x00);
 	iosync();
 	/*
 	 * Some machines need to have at least one cpu in the GIQ,
 	 * so leave the master cpu in the group.
 	 */
 	if (secondary) {
 		/*
 		 * we need to EOI the IPI if we got here from kexec down IPI
 		 *
 		 * probably need to check all the other interrupts too
 		 * should we be flagging idle loop instead?
 		 * or creating some task to be scheduled?
 		 */
 		ops->xirr_info_set(cpu, XICS_IPI);
 		rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE,
 			(1UL << interrupt_server_size) - 1 -
 			default_distrib_server, 0);
 	}
 }
 #ifdef CONFIG_HOTPLUG_CPU
 /* Interrupts are disabled. */
 void xics_migrate_irqs_away(void)
 {
 	int status;
 	unsigned int irq, virq, cpu = smp_processor_id();
 	/* Reject any interrupt that was queued to us... */
 	ops->cppr_info(cpu, 0);
 	iosync();
 	/* remove ourselves from the global interrupt queue */
 	status = rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE,
 		(1UL << interrupt_server_size) - 1 - default_distrib_server, 0);
 	WARN_ON(status < 0);
 	/* Allow IPIs again... */
 	ops->cppr_info(cpu, DEFAULT_PRIORITY);
 	iosync();
 	for_each_irq(virq) {
 		irq_desc_t *desc;
 		int xics_status[2];
 		unsigned long flags;
 		/* We cant set affinity on ISA interrupts */
 		if (virq < irq_offset_value())
 			continue;
 		desc = get_irq_desc(virq);
 		irq = virt_irq_to_real(irq_offset_down(virq));
 		/* We need to get IPIs still. */
 		if (irq == XICS_IPI || irq == NO_IRQ)
 			continue;
 		/* We only need to migrate enabled IRQS */
 		if (desc == NULL || desc->handler == NULL
 		    || desc->action == NULL
 		    || desc->handler->set_affinity == NULL)
 			continue;
 		spin_lock_irqsave(&desc->lock, flags);
 		status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
 		if (status) {
 			printk(KERN_ERR "migrate_irqs_away: irq=%u "
 					"ibm,get-xive returns %d\n",
 					virq, status);
 			goto unlock;
 		}
 		/*
 		 * We only support delivery to all cpus or to one cpu.
 		 * The irq has to be migrated only in the single cpu
 		 * case.
 		 */
 		if (xics_status[0] != get_hard_smp_processor_id(cpu))
 			goto unlock;
 		printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
 		       virq, cpu);
 		/* Reset affinity to all cpus */
 		desc->handler->set_affinity(virq, CPU_MASK_ALL);
 		irq_affinity[virq] = CPU_MASK_ALL;
 unlock:
 		spin_unlock_irqrestore(&desc->lock, flags);
 	}
 }
 #endif

arch/ppc64/kernel/irq.c

Diff comments View file @ d4be4f3

 /*
  *  arch/ppc/kernel/irq.c
  *
  *  Derived from arch/i386/kernel/irq.c
  *    Copyright (C) 1992 Linus Torvalds
  *  Adapted from arch/i386 by Gary Thomas
  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu)
  *    Copyright (C) 1996 Cort Dougan
  *  Adapted for Power Macintosh by Paul Mackerras
  *    Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
  *  Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  *
  * This file contains the code used by various IRQ handling routines:
  * asking for different IRQ's should be done through these routines
  * instead of just grabbing them. Thus setups with different IRQ numbers
  * shouldn't result in any weird surprises, and installing new handlers
  * should be easier.
  */
 #include <linux/errno.h>
 #include <linux/module.h>
 #include <linux/threads.h>
 #include <linux/kernel_stat.h>
 #include <linux/signal.h>
 #include <linux/sched.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/timex.h>
 #include <linux/config.h>
 #include <linux/init.h>
 #include <linux/slab.h>
 #include <linux/pci.h>
 #include <linux/delay.h>
 #include <linux/irq.h>
 #include <linux/proc_fs.h>
 #include <linux/random.h>
 #include <linux/kallsyms.h>
 #include <linux/profile.h>
 #include <linux/bitops.h>
 #include <asm/uaccess.h>
 #include <asm/system.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/irq.h>
 #include <asm/cache.h>
 #include <asm/prom.h>
 #include <asm/ptrace.h>
 #include <asm/iseries/it_lp_queue.h>
 #include <asm/machdep.h>
 #include <asm/paca.h>
 #ifdef CONFIG_SMP
 extern void iSeries_smp_message_recv( struct pt_regs * );
 #endif
 extern irq_desc_t irq_desc[NR_IRQS];
 EXPORT_SYMBOL(irq_desc);
 int distribute_irqs = 1;
 int __irq_offset_value;
 int ppc_spurious_interrupts;
 u64 ppc64_interrupt_controller;
 int show_interrupts(struct seq_file *p, void *v)
 {
 	int i = *(loff_t *) v, j;
 	struct irqaction * action;
 	irq_desc_t *desc;
 	unsigned long flags;
 	if (i == 0) {
 		seq_printf(p, "           ");
 		for (j=0; j<NR_CPUS; j++) {
 			if (cpu_online(j))
 				seq_printf(p, "CPU%d       ",j);
 		}
 		seq_putc(p, '\n');
 	}
 	if (i < NR_IRQS) {
 		desc = get_irq_desc(i);
 		spin_lock_irqsave(&desc->lock, flags);
 		action = desc->action;
 		if (!action || !action->handler)
 			goto skip;
 		seq_printf(p, "%3d: ", i);
 #ifdef CONFIG_SMP
 		for (j = 0; j < NR_CPUS; j++) {
 			if (cpu_online(j))
 				seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
 		}
 #else
 		seq_printf(p, "%10u ", kstat_irqs(i));
 #endif /* CONFIG_SMP */
 		if (desc->handler)
 			seq_printf(p, " %s ", desc->handler->typename );
 		else
 			seq_printf(p, "  None      ");
 		seq_printf(p, "%s", (desc->status & IRQ_LEVEL) ? "Level " : "Edge  ");
 		seq_printf(p, "    %s",action->name);
 		for (action=action->next; action; action = action->next)
 			seq_printf(p, ", %s", action->name);
 		seq_putc(p, '\n');
 skip:
 		spin_unlock_irqrestore(&desc->lock, flags);
 	} else if (i == NR_IRQS)
 		seq_printf(p, "BAD: %10u\n", ppc_spurious_interrupts);
 	return 0;
 }
 #ifdef CONFIG_HOTPLUG_CPU
 void fixup_irqs(cpumask_t map)
 {
 	unsigned int irq;
 	static int warned;
 	for_each_irq(irq) {
 		cpumask_t mask;
 		if (irq_desc[irq].status & IRQ_PER_CPU)
 			continue;
 		cpus_and(mask, irq_affinity[irq], map);
 		if (any_online_cpu(mask) == NR_CPUS) {
 			printk("Breaking affinity for irq %i\n", irq);
 			mask = map;
 		}
 		if (irq_desc[irq].handler->set_affinity)
 			irq_desc[irq].handler->set_affinity(irq, mask);
 		else if (irq_desc[irq].action && !(warned++))
 			printk("Cannot set affinity for irq %i\n", irq);
 	}
 	local_irq_enable();
 	mdelay(1);
 	local_irq_disable();
 }
 #endif
-extern int noirqdebug;
-/*
- * Eventually, this should take an array of interrupts and an array size
- * so it can dispatch multiple interrupts.
- */
-void ppc_irq_dispatch_handler(struct pt_regs *regs, int irq)
-{
-	int status;
-	struct irqaction *action;
-	int cpu = smp_processor_id();
-	irq_desc_t *desc = get_irq_desc(irq);
-	irqreturn_t action_ret;
-	kstat_cpu(cpu).irqs[irq]++;
-	if (desc->status & IRQ_PER_CPU) {
-		/* no locking required for CPU-local interrupts: */
-		ack_irq(irq);
-		action_ret = handle_IRQ_event(irq, regs, desc->action);
-		desc->handler->end(irq);
-		return;
-	}
-	spin_lock(&desc->lock);
-	ack_irq(irq);
-	/*
-	   REPLAY is when Linux resends an IRQ that was dropped earlier
-	   WAITING is used by probe to mark irqs that are being tested
-	   */
-	status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING);
-	status |= IRQ_PENDING; /* we _want_ to handle it */
-	/*
-	 * If the IRQ is disabled for whatever reason, we cannot
-	 * use the action we have.
-	 */
-	action = NULL;
-	if (likely(!(status & (IRQ_DISABLED | IRQ_INPROGRESS)))) {
-		action = desc->action;
-		if (!action || !action->handler) {
-			ppc_spurious_interrupts++;
-			printk(KERN_DEBUG "Unhandled interrupt %x, disabled\n", irq);
-			/* We can't call disable_irq here, it would deadlock */
-			if (!desc->depth)
-				desc->depth = 1;
-			desc->status |= IRQ_DISABLED;
-			/* This is not a real spurrious interrupt, we
-			 * have to eoi it, so we jump to out
-			 */
-			mask_irq(irq);
-			goto out;
-		}
-		status &= ~IRQ_PENDING; /* we commit to handling */
-		status |= IRQ_INPROGRESS; /* we are handling it */
-	}
-	desc->status = status;
-	/*
-	 * If there is no IRQ handler or it was disabled, exit early.
-	   Since we set PENDING, if another processor is handling
-	   a different instance of this same irq, the other processor
-	   will take care of it.
-	 */
-	if (unlikely(!action))
-		goto out;
-	/*
-	 * Edge triggered interrupts need to remember
-	 * pending events.
-	 * This applies to any hw interrupts that allow a second
-	 * instance of the same irq to arrive while we are in do_IRQ
-	 * or in the handler. But the code here only handles the _second_
-	 * instance of the irq, not the third or fourth. So it is mostly
-	 * useful for irq hardware that does not mask cleanly in an
-	 * SMP environment.
-	 */
-	for (;;) {
-		spin_unlock(&desc->lock);
-		action_ret = handle_IRQ_event(irq, regs, action);
-		spin_lock(&desc->lock);
-		if (!noirqdebug)
-			note_interrupt(irq, desc, action_ret, regs);
-		if (likely(!(desc->status & IRQ_PENDING)))
-			break;
-		desc->status &= ~IRQ_PENDING;
-	}
-out:
-	desc->status &= ~IRQ_INPROGRESS;
-	/*
-	 * The ->end() handler has to deal with interrupts which got
-	 * disabled while the handler was running.
-	 */
-	if (desc->handler) {
-		if (desc->handler->end)
-			desc->handler->end(irq);
-		else if (desc->handler->enable)
-			desc->handler->enable(irq);
-	}
-	spin_unlock(&desc->lock);
-}
 #ifdef CONFIG_PPC_ISERIES
 void do_IRQ(struct pt_regs *regs)
 {
 	struct paca_struct *lpaca;
 	irq_enter();
 #ifdef CONFIG_DEBUG_STACKOVERFLOW
 	/* Debugging check for stack overflow: is there less than 2KB free? */
 	{
 		long sp;
 		sp = __get_SP() & (THREAD_SIZE-1);
 		if (unlikely(sp < (sizeof(struct thread_info) + 2048))) {
 			printk("do_IRQ: stack overflow: %ld\n",
 				sp - sizeof(struct thread_info));
 			dump_stack();
 		}
 	}
 #endif
 	lpaca = get_paca();
 #ifdef CONFIG_SMP
 	if (lpaca->lppaca.int_dword.fields.ipi_cnt) {
 		lpaca->lppaca.int_dword.fields.ipi_cnt = 0;
 		iSeries_smp_message_recv(regs);
 	}
 #endif /* CONFIG_SMP */
 	if (hvlpevent_is_pending())
 		process_hvlpevents(regs);
 	irq_exit();
 	if (lpaca->lppaca.int_dword.fields.decr_int) {
 		lpaca->lppaca.int_dword.fields.decr_int = 0;
 		/* Signal a fake decrementer interrupt */
 		timer_interrupt(regs);
 	}
 }
 #else	/* CONFIG_PPC_ISERIES */
 void do_IRQ(struct pt_regs *regs)
 {
 	int irq;
 #ifdef CONFIG_IRQSTACKS
 	struct thread_info *curtp, *irqtp;
 #endif
 	irq_enter();
 #ifdef CONFIG_DEBUG_STACKOVERFLOW
 	/* Debugging check for stack overflow: is there less than 2KB free? */
 	{
 		long sp;
 		sp = __get_SP() & (THREAD_SIZE-1);
 		if (unlikely(sp < (sizeof(struct thread_info) + 2048))) {
 			printk("do_IRQ: stack overflow: %ld\n",
 				sp - sizeof(struct thread_info));
 			dump_stack();
 		}
 	}
 #endif
 	irq = ppc_md.get_irq(regs);
 	if (irq >= 0) {
 #ifdef CONFIG_IRQSTACKS
 		/* Switch to the irq stack to handle this */
 		curtp = current_thread_info();
 		irqtp = hardirq_ctx[smp_processor_id()];
 		if (curtp != irqtp) {
 			irqtp->task = curtp->task;
 			irqtp->flags = 0;
-			call_ppc_irq_dispatch_handler(regs, irq, irqtp);
+			call___do_IRQ(irq, regs, irqtp);
 			irqtp->task = NULL;
 			if (irqtp->flags)
 				set_bits(irqtp->flags, &curtp->flags);
 		} else
 #endif
-			ppc_irq_dispatch_handler(regs, irq);
+			__do_IRQ(irq, regs);
 	} else
 		/* That's not SMP safe ... but who cares ? */
 		ppc_spurious_interrupts++;
 	irq_exit();
 }
 #endif	/* CONFIG_PPC_ISERIES */
 void __init init_IRQ(void)
 {
 	static int once = 0;
 	if (once)
 		return;
 	once++;
 	ppc_md.init_IRQ();
 	irq_ctx_init();
 }
 #ifndef CONFIG_PPC_ISERIES
 /*
  * Virtual IRQ mapping code, used on systems with XICS interrupt controllers.
  */
 #define UNDEFINED_IRQ 0xffffffff
 unsigned int virt_irq_to_real_map[NR_IRQS];
 /*
  * Don't use virtual irqs 0, 1, 2 for devices.
  * The pcnet32 driver considers interrupt numbers < 2 to be invalid,
  * and 2 is the XICS IPI interrupt.
  * We limit virtual irqs to 17 less than NR_IRQS so that when we
  * offset them by 16 (to reserve the first 16 for ISA interrupts)
  * we don't end up with an interrupt number >= NR_IRQS.
  */
 #define MIN_VIRT_IRQ	3
 #define MAX_VIRT_IRQ	(NR_IRQS - NUM_ISA_INTERRUPTS - 1)
 #define NR_VIRT_IRQS	(MAX_VIRT_IRQ - MIN_VIRT_IRQ + 1)
 void
 virt_irq_init(void)
 {
 	int i;
 	for (i = 0; i < NR_IRQS; i++)
 		virt_irq_to_real_map[i] = UNDEFINED_IRQ;
 }
 /* Create a mapping for a real_irq if it doesn't already exist.
  * Return the virtual irq as a convenience.
  */
 int virt_irq_create_mapping(unsigned int real_irq)
 {
 	unsigned int virq, first_virq;
 	static int warned;
 	if (ppc64_interrupt_controller == IC_OPEN_PIC)
 		return real_irq;	/* no mapping for openpic (for now) */
 	if (ppc64_interrupt_controller == IC_CELL_PIC)
 		return real_irq;	/* no mapping for iic either */
 	/* don't map interrupts < MIN_VIRT_IRQ */
 	if (real_irq < MIN_VIRT_IRQ) {
 		virt_irq_to_real_map[real_irq] = real_irq;
 		return real_irq;
 	}
 	/* map to a number between MIN_VIRT_IRQ and MAX_VIRT_IRQ */
 	virq = real_irq;
 	if (virq > MAX_VIRT_IRQ)
 		virq = (virq % NR_VIRT_IRQS) + MIN_VIRT_IRQ;
 	/* search for this number or a free slot */
 	first_virq = virq;
 	while (virt_irq_to_real_map[virq] != UNDEFINED_IRQ) {
 		if (virt_irq_to_real_map[virq] == real_irq)
 			return virq;
 		if (++virq > MAX_VIRT_IRQ)
 			virq = MIN_VIRT_IRQ;
 		if (virq == first_virq)
 			goto nospace;	/* oops, no free slots */
 	}
 	virt_irq_to_real_map[virq] = real_irq;
 	return virq;
  nospace:
 	if (!warned) {
 		printk(KERN_CRIT "Interrupt table is full\n");
 		printk(KERN_CRIT "Increase NR_IRQS (currently %d) "
 		       "in your kernel sources and rebuild.\n", NR_IRQS);
 		warned = 1;
 	}
 	return NO_IRQ;
 }
 /*
  * In most cases will get a hit on the very first slot checked in the
  * virt_irq_to_real_map.  Only when there are a large number of
  * IRQs will this be expensive.
  */
 unsigned int real_irq_to_virt_slowpath(unsigned int real_irq)
 {
 	unsigned int virq;
 	unsigned int first_virq;
 	virq = real_irq;
 	if (virq > MAX_VIRT_IRQ)
 		virq = (virq % NR_VIRT_IRQS) + MIN_VIRT_IRQ;
 	first_virq = virq;
 	do {
 		if (virt_irq_to_real_map[virq] == real_irq)
 			return virq;
 		virq++;
 		if (virq >= MAX_VIRT_IRQ)
 			virq = 0;
 	} while (first_virq != virq);
 	return NO_IRQ;
 }
 #endif /* CONFIG_PPC_ISERIES */
 #ifdef CONFIG_IRQSTACKS
 struct thread_info *softirq_ctx[NR_CPUS];
 struct thread_info *hardirq_ctx[NR_CPUS];
 void irq_ctx_init(void)
 {
 	struct thread_info *tp;
 	int i;
 	for_each_cpu(i) {
 		memset((void *)softirq_ctx[i], 0, THREAD_SIZE);
 		tp = softirq_ctx[i];
 		tp->cpu = i;
 		tp->preempt_count = SOFTIRQ_OFFSET;
 		memset((void *)hardirq_ctx[i], 0, THREAD_SIZE);
 		tp = hardirq_ctx[i];
 		tp->cpu = i;
 		tp->preempt_count = HARDIRQ_OFFSET;
 	}
 }
 void do_softirq(void)
 {
 	unsigned long flags;
 	struct thread_info *curtp, *irqtp;
 	if (in_interrupt())
 		return;
 	local_irq_save(flags);
 	if (local_softirq_pending()) {
 		curtp = current_thread_info();
 		irqtp = softirq_ctx[smp_processor_id()];
 		irqtp->task = curtp->task;
 		call_do_softirq(irqtp);
 		irqtp->task = NULL;
 	}
 	local_irq_restore(flags);
 }
 EXPORT_SYMBOL(do_softirq);
 #endif /* CONFIG_IRQSTACKS */
 static int __init setup_noirqdistrib(char *str)
 {
 	distribute_irqs = 0;
 	return 1;
 }
 __setup("noirqdistrib", setup_noirqdistrib);

arch/ppc64/kernel/misc.S

Diff comments View file @ d4be4f3

1	/*	1	/*
2	* arch/ppc/kernel/misc.S	2	* arch/ppc/kernel/misc.S
3	*	3	*
4	*	4	*
5	*	5	*
6	* This file contains miscellaneous low-level functions.	6	* This file contains miscellaneous low-level functions.
7	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)	7	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8	*	8	*
9	* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)	9	* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
10	* and Paul Mackerras.	10	* and Paul Mackerras.
11	* Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)	11	* Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
12	* PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)	12	* PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
13	*	13	*
14	* This program is free software; you can redistribute it and/or	14	* This program is free software; you can redistribute it and/or
15	* modify it under the terms of the GNU General Public License	15	* modify it under the terms of the GNU General Public License
16	* as published by the Free Software Foundation; either version	16	* as published by the Free Software Foundation; either version
17	* 2 of the License, or (at your option) any later version.	17	* 2 of the License, or (at your option) any later version.
18	*	18	*
19	*/	19	*/
20		20
21	#include <linux/config.h>	21	#include <linux/config.h>
22	#include <linux/sys.h>	22	#include <linux/sys.h>
23	#include <asm/unistd.h>	23	#include <asm/unistd.h>
24	#include <asm/errno.h>	24	#include <asm/errno.h>
25	#include <asm/processor.h>	25	#include <asm/processor.h>
26	#include <asm/page.h>	26	#include <asm/page.h>
27	#include <asm/cache.h>	27	#include <asm/cache.h>
28	#include <asm/ppc_asm.h>	28	#include <asm/ppc_asm.h>
29	#include <asm/asm-offsets.h>	29	#include <asm/asm-offsets.h>
30	#include <asm/cputable.h>	30	#include <asm/cputable.h>
31	#include <asm/thread_info.h>	31	#include <asm/thread_info.h>
32		32
33	.text	33	.text
34		34
35	/*	35	/*
36	* Returns (address we were linked at) - (address we are running at)	36	* Returns (address we were linked at) - (address we are running at)
37	* for use before the text and data are mapped to KERNELBASE.	37	* for use before the text and data are mapped to KERNELBASE.
38	*/	38	*/
39		39
40	_GLOBAL(reloc_offset)	40	_GLOBAL(reloc_offset)
41	mflr r0	41	mflr r0
42	bl 1f	42	bl 1f
43	1: mflr r3	43	1: mflr r3
44	LOADADDR(r4,1b)	44	LOADADDR(r4,1b)
45	sub r3,r4,r3	45	sub r3,r4,r3
46	mtlr r0	46	mtlr r0
47	blr	47	blr
48		48
49	_GLOBAL(get_msr)	49	_GLOBAL(get_msr)
50	mfmsr r3	50	mfmsr r3
51	blr	51	blr
52		52
53	_GLOBAL(get_dar)	53	_GLOBAL(get_dar)
54	mfdar r3	54	mfdar r3
55	blr	55	blr
56		56
57	_GLOBAL(get_srr0)	57	_GLOBAL(get_srr0)
58	mfsrr0 r3	58	mfsrr0 r3
59	blr	59	blr
60		60
61	_GLOBAL(get_srr1)	61	_GLOBAL(get_srr1)
62	mfsrr1 r3	62	mfsrr1 r3
63	blr	63	blr
64		64
65	_GLOBAL(get_sp)	65	_GLOBAL(get_sp)
66	mr r3,r1	66	mr r3,r1
67	blr	67	blr
68		68
69	#ifdef CONFIG_IRQSTACKS	69	#ifdef CONFIG_IRQSTACKS
70	_GLOBAL(call_do_softirq)	70	_GLOBAL(call_do_softirq)
71	mflr r0	71	mflr r0
72	std r0,16(r1)	72	std r0,16(r1)
73	stdu r1,THREAD_SIZE-112(r3)	73	stdu r1,THREAD_SIZE-112(r3)
74	mr r1,r3	74	mr r1,r3
75	bl .__do_softirq	75	bl .__do_softirq
76	ld r1,0(r1)	76	ld r1,0(r1)
77	ld r0,16(r1)	77	ld r0,16(r1)
78	mtlr r0	78	mtlr r0
79	blr	79	blr
80		80
81	_GLOBAL(call_ppc_irq_dispatch_handler)	81	_GLOBAL(call___do_IRQ)
82	mflr r0	82	mflr r0
83	std r0,16(r1)	83	std r0,16(r1)
84	stdu r1,THREAD_SIZE-112(r5)	84	stdu r1,THREAD_SIZE-112(r5)
85	mr r1,r5	85	mr r1,r5
86	bl .ppc_irq_dispatch_handler	86	bl .__do_IRQ
87	ld r1,0(r1)	87	ld r1,0(r1)
88	ld r0,16(r1)	88	ld r0,16(r1)
89	mtlr r0	89	mtlr r0
90	blr	90	blr
91	#endif /* CONFIG_IRQSTACKS */	91	#endif /* CONFIG_IRQSTACKS */
92		92
93	/*	93	/*
94	* To be called by C code which needs to do some operations with MMU	94	* To be called by C code which needs to do some operations with MMU
95	* disabled. Note that interrupts have to be disabled by the caller	95	* disabled. Note that interrupts have to be disabled by the caller
96	* prior to calling us. The code called _MUST_ be in the RMO of course	96	* prior to calling us. The code called _MUST_ be in the RMO of course
97	* and part of the linear mapping as we don't attempt to translate the	97	* and part of the linear mapping as we don't attempt to translate the
98	* stack pointer at all. The function is called with the stack switched	98	* stack pointer at all. The function is called with the stack switched
99	* to this CPU emergency stack	99	* to this CPU emergency stack
100	*	100	*
101	* prototype is void call_with_mmu_off(void func, void *data);	101	* prototype is void call_with_mmu_off(void func, void *data);
102	*	102	*
103	* the called function is expected to be of the form	103	* the called function is expected to be of the form
104	*	104	*
105	* void called(void data);	105	* void called(void data);
106	*/	106	*/
107	_GLOBAL(call_with_mmu_off)	107	_GLOBAL(call_with_mmu_off)
108	mflr r0 /* get link, save it on stackframe */	108	mflr r0 /* get link, save it on stackframe */
109	std r0,16(r1)	109	std r0,16(r1)
110	mr r1,r5 /* save old stack ptr */	110	mr r1,r5 /* save old stack ptr */
111	ld r1,PACAEMERGSP(r13) /* get emerg. stack */	111	ld r1,PACAEMERGSP(r13) /* get emerg. stack */
112	subi r1,r1,STACK_FRAME_OVERHEAD	112	subi r1,r1,STACK_FRAME_OVERHEAD
113	std r0,16(r1) /* save link on emerg. stack */	113	std r0,16(r1) /* save link on emerg. stack */
114	std r5,0(r1) /* save old stack ptr in backchain */	114	std r5,0(r1) /* save old stack ptr in backchain */
115	ld r3,0(r3) /* get to real function ptr (assume same TOC) */	115	ld r3,0(r3) /* get to real function ptr (assume same TOC) */
116	bl 2f /* we need LR to return, continue at label 2 */	116	bl 2f /* we need LR to return, continue at label 2 */
117		117
118	ld r0,16(r1) /* we return here from the call, get LR and */	118	ld r0,16(r1) /* we return here from the call, get LR and */
119	ld r1,0(r1) /* .. old stack ptr */	119	ld r1,0(r1) /* .. old stack ptr */
120	mtspr SPRN_SRR0,r0 /* and get back to virtual mode with these */	120	mtspr SPRN_SRR0,r0 /* and get back to virtual mode with these */
121	mfmsr r4	121	mfmsr r4
122	ori r4,r4,MSR_IR\|MSR_DR	122	ori r4,r4,MSR_IR\|MSR_DR
123	mtspr SPRN_SRR1,r4	123	mtspr SPRN_SRR1,r4
124	rfid	124	rfid
125		125
126	2: mtspr SPRN_SRR0,r3 /* coming from above, enter real mode */	126	2: mtspr SPRN_SRR0,r3 /* coming from above, enter real mode */
127	mr r3,r4 /* get parameter */	127	mr r3,r4 /* get parameter */
128	mfmsr r0	128	mfmsr r0
129	ori r0,r0,MSR_IR\|MSR_DR	129	ori r0,r0,MSR_IR\|MSR_DR
130	xori r0,r0,MSR_IR\|MSR_DR	130	xori r0,r0,MSR_IR\|MSR_DR
131	mtspr SPRN_SRR1,r0	131	mtspr SPRN_SRR1,r0
132	rfid	132	rfid
133		133
134		134
135	.section ".toc","aw"	135	.section ".toc","aw"
136	PPC64_CACHES:	136	PPC64_CACHES:
137	.tc ppc64_caches[TC],ppc64_caches	137	.tc ppc64_caches[TC],ppc64_caches
138	.section ".text"	138	.section ".text"
139		139
140	/*	140	/*
141	* Write any modified data cache blocks out to memory	141	* Write any modified data cache blocks out to memory
142	* and invalidate the corresponding instruction cache blocks.	142	* and invalidate the corresponding instruction cache blocks.
143	*	143	*
144	* flush_icache_range(unsigned long start, unsigned long stop)	144	* flush_icache_range(unsigned long start, unsigned long stop)
145	*	145	*
146	* flush all bytes from start through stop-1 inclusive	146	* flush all bytes from start through stop-1 inclusive
147	*/	147	*/
148		148
149	_KPROBE(__flush_icache_range)	149	_KPROBE(__flush_icache_range)
150		150
151	/*	151	/*
152	* Flush the data cache to memory	152	* Flush the data cache to memory
153	*	153	*
154	* Different systems have different cache line sizes	154	* Different systems have different cache line sizes
155	* and in some cases i-cache and d-cache line sizes differ from	155	* and in some cases i-cache and d-cache line sizes differ from
156	* each other.	156	* each other.
157	*/	157	*/
158	ld r10,PPC64_CACHES@toc(r2)	158	ld r10,PPC64_CACHES@toc(r2)
159	lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */	159	lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
160	addi r5,r7,-1	160	addi r5,r7,-1
161	andc r6,r3,r5 /* round low to line bdy */	161	andc r6,r3,r5 /* round low to line bdy */
162	subf r8,r6,r4 /* compute length */	162	subf r8,r6,r4 /* compute length */
163	add r8,r8,r5 /* ensure we get enough */	163	add r8,r8,r5 /* ensure we get enough */
164	lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */	164	lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
165	srw. r8,r8,r9 /* compute line count */	165	srw. r8,r8,r9 /* compute line count */
166	beqlr /* nothing to do? */	166	beqlr /* nothing to do? */
167	mtctr r8	167	mtctr r8
168	1: dcbst 0,r6	168	1: dcbst 0,r6
169	add r6,r6,r7	169	add r6,r6,r7
170	bdnz 1b	170	bdnz 1b
171	sync	171	sync
172		172
173	/* Now invalidate the instruction cache */	173	/* Now invalidate the instruction cache */
174		174
175	lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */	175	lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
176	addi r5,r7,-1	176	addi r5,r7,-1
177	andc r6,r3,r5 /* round low to line bdy */	177	andc r6,r3,r5 /* round low to line bdy */
178	subf r8,r6,r4 /* compute length */	178	subf r8,r6,r4 /* compute length */
179	add r8,r8,r5	179	add r8,r8,r5
180	lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */	180	lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
181	srw. r8,r8,r9 /* compute line count */	181	srw. r8,r8,r9 /* compute line count */
182	beqlr /* nothing to do? */	182	beqlr /* nothing to do? */
183	mtctr r8	183	mtctr r8
184	2: icbi 0,r6	184	2: icbi 0,r6
185	add r6,r6,r7	185	add r6,r6,r7
186	bdnz 2b	186	bdnz 2b
187	isync	187	isync
188	blr	188	blr
189	.previous .text	189	.previous .text
190	/*	190	/*
191	* Like above, but only do the D-cache.	191	* Like above, but only do the D-cache.
192	*	192	*
193	* flush_dcache_range(unsigned long start, unsigned long stop)	193	* flush_dcache_range(unsigned long start, unsigned long stop)
194	*	194	*
195	* flush all bytes from start to stop-1 inclusive	195	* flush all bytes from start to stop-1 inclusive
196	*/	196	*/
197	_GLOBAL(flush_dcache_range)	197	_GLOBAL(flush_dcache_range)
198		198
199	/*	199	/*
200	* Flush the data cache to memory	200	* Flush the data cache to memory
201	*	201	*
202	* Different systems have different cache line sizes	202	* Different systems have different cache line sizes
203	*/	203	*/
204	ld r10,PPC64_CACHES@toc(r2)	204	ld r10,PPC64_CACHES@toc(r2)
205	lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */	205	lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
206	addi r5,r7,-1	206	addi r5,r7,-1
207	andc r6,r3,r5 /* round low to line bdy */	207	andc r6,r3,r5 /* round low to line bdy */
208	subf r8,r6,r4 /* compute length */	208	subf r8,r6,r4 /* compute length */
209	add r8,r8,r5 /* ensure we get enough */	209	add r8,r8,r5 /* ensure we get enough */
210	lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */	210	lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
211	srw. r8,r8,r9 /* compute line count */	211	srw. r8,r8,r9 /* compute line count */
212	beqlr /* nothing to do? */	212	beqlr /* nothing to do? */
213	mtctr r8	213	mtctr r8
214	0: dcbst 0,r6	214	0: dcbst 0,r6
215	add r6,r6,r7	215	add r6,r6,r7
216	bdnz 0b	216	bdnz 0b
217	sync	217	sync
218	blr	218	blr
219		219
220	/*	220	/*
221	* Like above, but works on non-mapped physical addresses.	221	* Like above, but works on non-mapped physical addresses.
222	* Use only for non-LPAR setups ! It also assumes real mode	222	* Use only for non-LPAR setups ! It also assumes real mode
223	* is cacheable. Used for flushing out the DART before using	223	* is cacheable. Used for flushing out the DART before using
224	* it as uncacheable memory	224	* it as uncacheable memory
225	*	225	*
226	* flush_dcache_phys_range(unsigned long start, unsigned long stop)	226	* flush_dcache_phys_range(unsigned long start, unsigned long stop)
227	*	227	*
228	* flush all bytes from start to stop-1 inclusive	228	* flush all bytes from start to stop-1 inclusive
229	*/	229	*/
230	_GLOBAL(flush_dcache_phys_range)	230	_GLOBAL(flush_dcache_phys_range)
231	ld r10,PPC64_CACHES@toc(r2)	231	ld r10,PPC64_CACHES@toc(r2)
232	lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */	232	lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
233	addi r5,r7,-1	233	addi r5,r7,-1
234	andc r6,r3,r5 /* round low to line bdy */	234	andc r6,r3,r5 /* round low to line bdy */
235	subf r8,r6,r4 /* compute length */	235	subf r8,r6,r4 /* compute length */
236	add r8,r8,r5 /* ensure we get enough */	236	add r8,r8,r5 /* ensure we get enough */
237	lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */	237	lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
238	srw. r8,r8,r9 /* compute line count */	238	srw. r8,r8,r9 /* compute line count */
239	beqlr /* nothing to do? */	239	beqlr /* nothing to do? */
240	mfmsr r5 /* Disable MMU Data Relocation */	240	mfmsr r5 /* Disable MMU Data Relocation */
241	ori r0,r5,MSR_DR	241	ori r0,r5,MSR_DR
242	xori r0,r0,MSR_DR	242	xori r0,r0,MSR_DR
243	sync	243	sync
244	mtmsr r0	244	mtmsr r0
245	sync	245	sync
246	isync	246	isync
247	mtctr r8	247	mtctr r8
248	0: dcbst 0,r6	248	0: dcbst 0,r6
249	add r6,r6,r7	249	add r6,r6,r7
250	bdnz 0b	250	bdnz 0b
251	sync	251	sync
252	isync	252	isync
253	mtmsr r5 /* Re-enable MMU Data Relocation */	253	mtmsr r5 /* Re-enable MMU Data Relocation */
254	sync	254	sync
255	isync	255	isync
256	blr	256	blr
257		257
258	_GLOBAL(flush_inval_dcache_range)	258	_GLOBAL(flush_inval_dcache_range)
259	ld r10,PPC64_CACHES@toc(r2)	259	ld r10,PPC64_CACHES@toc(r2)
260	lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */	260	lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
261	addi r5,r7,-1	261	addi r5,r7,-1
262	andc r6,r3,r5 /* round low to line bdy */	262	andc r6,r3,r5 /* round low to line bdy */
263	subf r8,r6,r4 /* compute length */	263	subf r8,r6,r4 /* compute length */
264	add r8,r8,r5 /* ensure we get enough */	264	add r8,r8,r5 /* ensure we get enough */
265	lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */	265	lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
266	srw. r8,r8,r9 /* compute line count */	266	srw. r8,r8,r9 /* compute line count */
267	beqlr /* nothing to do? */	267	beqlr /* nothing to do? */
268	sync	268	sync
269	isync	269	isync
270	mtctr r8	270	mtctr r8
271	0: dcbf 0,r6	271	0: dcbf 0,r6
272	add r6,r6,r7	272	add r6,r6,r7
273	bdnz 0b	273	bdnz 0b
274	sync	274	sync
275	isync	275	isync
276	blr	276	blr
277		277
278		278
279	/*	279	/*
280	* Flush a particular page from the data cache to RAM.	280	* Flush a particular page from the data cache to RAM.
281	* Note: this is necessary because the instruction cache does not	281	* Note: this is necessary because the instruction cache does not
282	* snoop from the data cache.	282	* snoop from the data cache.
283	*	283	*
284	* void __flush_dcache_icache(void *page)	284	* void __flush_dcache_icache(void *page)
285	*/	285	*/
286	_GLOBAL(__flush_dcache_icache)	286	_GLOBAL(__flush_dcache_icache)
287	/*	287	/*
288	* Flush the data cache to memory	288	* Flush the data cache to memory
289	*	289	*
290	* Different systems have different cache line sizes	290	* Different systems have different cache line sizes
291	*/	291	*/
292		292
293	/* Flush the dcache */	293	/* Flush the dcache */
294	ld r7,PPC64_CACHES@toc(r2)	294	ld r7,PPC64_CACHES@toc(r2)
295	clrrdi r3,r3,PAGE_SHIFT /* Page align */	295	clrrdi r3,r3,PAGE_SHIFT /* Page align */
296	lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */	296	lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
297	lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */	297	lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
298	mr r6,r3	298	mr r6,r3
299	mtctr r4	299	mtctr r4
300	0: dcbst 0,r6	300	0: dcbst 0,r6
301	add r6,r6,r5	301	add r6,r6,r5
302	bdnz 0b	302	bdnz 0b
303	sync	303	sync
304		304
305	/* Now invalidate the icache */	305	/* Now invalidate the icache */
306		306
307	lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */	307	lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
308	lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */	308	lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
309	mtctr r4	309	mtctr r4
310	1: icbi 0,r3	310	1: icbi 0,r3
311	add r3,r3,r5	311	add r3,r3,r5
312	bdnz 1b	312	bdnz 1b
313	isync	313	isync
314	blr	314	blr
315		315
316	/*	316	/*
317	* I/O string operations	317	* I/O string operations
318	*	318	*
319	* insb(port, buf, len)	319	* insb(port, buf, len)
320	* outsb(port, buf, len)	320	* outsb(port, buf, len)
321	* insw(port, buf, len)	321	* insw(port, buf, len)
322	* outsw(port, buf, len)	322	* outsw(port, buf, len)
323	* insl(port, buf, len)	323	* insl(port, buf, len)
324	* outsl(port, buf, len)	324	* outsl(port, buf, len)
325	* insw_ns(port, buf, len)	325	* insw_ns(port, buf, len)
326	* outsw_ns(port, buf, len)	326	* outsw_ns(port, buf, len)
327	* insl_ns(port, buf, len)	327	* insl_ns(port, buf, len)
328	* outsl_ns(port, buf, len)	328	* outsl_ns(port, buf, len)
329	*	329	*
330	* The *_ns versions don't do byte-swapping.	330	* The *_ns versions don't do byte-swapping.
331	*/	331	*/
332	_GLOBAL(_insb)	332	_GLOBAL(_insb)
333	cmpwi 0,r5,0	333	cmpwi 0,r5,0
334	mtctr r5	334	mtctr r5
335	subi r4,r4,1	335	subi r4,r4,1
336	blelr-	336	blelr-
337	00: lbz r5,0(r3)	337	00: lbz r5,0(r3)
338	eieio	338	eieio
339	stbu r5,1(r4)	339	stbu r5,1(r4)
340	bdnz 00b	340	bdnz 00b
341	twi 0,r5,0	341	twi 0,r5,0
342	isync	342	isync
343	blr	343	blr
344		344
345	_GLOBAL(_outsb)	345	_GLOBAL(_outsb)
346	cmpwi 0,r5,0	346	cmpwi 0,r5,0
347	mtctr r5	347	mtctr r5
348	subi r4,r4,1	348	subi r4,r4,1
349	blelr-	349	blelr-
350	00: lbzu r5,1(r4)	350	00: lbzu r5,1(r4)
351	stb r5,0(r3)	351	stb r5,0(r3)
352	bdnz 00b	352	bdnz 00b
353	sync	353	sync
354	blr	354	blr
355		355
356	_GLOBAL(_insw)	356	_GLOBAL(_insw)
357	cmpwi 0,r5,0	357	cmpwi 0,r5,0
358	mtctr r5	358	mtctr r5
359	subi r4,r4,2	359	subi r4,r4,2
360	blelr-	360	blelr-
361	00: lhbrx r5,0,r3	361	00: lhbrx r5,0,r3
362	eieio	362	eieio
363	sthu r5,2(r4)	363	sthu r5,2(r4)
364	bdnz 00b	364	bdnz 00b
365	twi 0,r5,0	365	twi 0,r5,0
366	isync	366	isync
367	blr	367	blr
368		368
369	_GLOBAL(_outsw)	369	_GLOBAL(_outsw)
370	cmpwi 0,r5,0	370	cmpwi 0,r5,0
371	mtctr r5	371	mtctr r5
372	subi r4,r4,2	372	subi r4,r4,2
373	blelr-	373	blelr-
374	00: lhzu r5,2(r4)	374	00: lhzu r5,2(r4)
375	sthbrx r5,0,r3	375	sthbrx r5,0,r3
376	bdnz 00b	376	bdnz 00b
377	sync	377	sync
378	blr	378	blr
379		379
380	_GLOBAL(_insl)	380	_GLOBAL(_insl)
381	cmpwi 0,r5,0	381	cmpwi 0,r5,0
382	mtctr r5	382	mtctr r5
383	subi r4,r4,4	383	subi r4,r4,4
384	blelr-	384	blelr-
385	00: lwbrx r5,0,r3	385	00: lwbrx r5,0,r3
386	eieio	386	eieio
387	stwu r5,4(r4)	387	stwu r5,4(r4)
388	bdnz 00b	388	bdnz 00b
389	twi 0,r5,0	389	twi 0,r5,0
390	isync	390	isync
391	blr	391	blr
392		392
393	_GLOBAL(_outsl)	393	_GLOBAL(_outsl)
394	cmpwi 0,r5,0	394	cmpwi 0,r5,0
395	mtctr r5	395	mtctr r5
396	subi r4,r4,4	396	subi r4,r4,4
397	blelr-	397	blelr-
398	00: lwzu r5,4(r4)	398	00: lwzu r5,4(r4)
399	stwbrx r5,0,r3	399	stwbrx r5,0,r3
400	bdnz 00b	400	bdnz 00b
401	sync	401	sync
402	blr	402	blr
403		403
404	/* _GLOBAL(ide_insw) now in drivers/ide/ide-iops.c */	404	/* _GLOBAL(ide_insw) now in drivers/ide/ide-iops.c */
405	_GLOBAL(_insw_ns)	405	_GLOBAL(_insw_ns)
406	cmpwi 0,r5,0	406	cmpwi 0,r5,0
407	mtctr r5	407	mtctr r5
408	subi r4,r4,2	408	subi r4,r4,2
409	blelr-	409	blelr-
410	00: lhz r5,0(r3)	410	00: lhz r5,0(r3)
411	eieio	411	eieio
412	sthu r5,2(r4)	412	sthu r5,2(r4)
413	bdnz 00b	413	bdnz 00b
414	twi 0,r5,0	414	twi 0,r5,0
415	isync	415	isync
416	blr	416	blr
417		417
418	/* _GLOBAL(ide_outsw) now in drivers/ide/ide-iops.c */	418	/* _GLOBAL(ide_outsw) now in drivers/ide/ide-iops.c */
419	_GLOBAL(_outsw_ns)	419	_GLOBAL(_outsw_ns)
420	cmpwi 0,r5,0	420	cmpwi 0,r5,0
421	mtctr r5	421	mtctr r5
422	subi r4,r4,2	422	subi r4,r4,2
423	blelr-	423	blelr-
424	00: lhzu r5,2(r4)	424	00: lhzu r5,2(r4)
425	sth r5,0(r3)	425	sth r5,0(r3)
426	bdnz 00b	426	bdnz 00b
427	sync	427	sync
428	blr	428	blr
429		429
430	_GLOBAL(_insl_ns)	430	_GLOBAL(_insl_ns)
431	cmpwi 0,r5,0	431	cmpwi 0,r5,0
432	mtctr r5	432	mtctr r5
433	subi r4,r4,4	433	subi r4,r4,4
434	blelr-	434	blelr-
435	00: lwz r5,0(r3)	435	00: lwz r5,0(r3)
436	eieio	436	eieio
437	stwu r5,4(r4)	437	stwu r5,4(r4)
438	bdnz 00b	438	bdnz 00b
439	twi 0,r5,0	439	twi 0,r5,0
440	isync	440	isync
441	blr	441	blr
442		442
443	_GLOBAL(_outsl_ns)	443	_GLOBAL(_outsl_ns)
444	cmpwi 0,r5,0	444	cmpwi 0,r5,0
445	mtctr r5	445	mtctr r5
446	subi r4,r4,4	446	subi r4,r4,4
447	blelr-	447	blelr-
448	00: lwzu r5,4(r4)	448	00: lwzu r5,4(r4)
449	stw r5,0(r3)	449	stw r5,0(r3)
450	bdnz 00b	450	bdnz 00b
451	sync	451	sync
452	blr	452	blr
453		453
454	/*	454	/*
455	* identify_cpu and calls setup_cpu	455	* identify_cpu and calls setup_cpu
456	* In: r3 = base of the cpu_specs array	456	* In: r3 = base of the cpu_specs array
457	* r4 = address of cur_cpu_spec	457	* r4 = address of cur_cpu_spec
458	* r5 = relocation offset	458	* r5 = relocation offset
459	*/	459	*/
460	_GLOBAL(identify_cpu)	460	_GLOBAL(identify_cpu)
461	mfpvr r7	461	mfpvr r7
462	1:	462	1:
463	lwz r8,CPU_SPEC_PVR_MASK(r3)	463	lwz r8,CPU_SPEC_PVR_MASK(r3)
464	and r8,r8,r7	464	and r8,r8,r7
465	lwz r9,CPU_SPEC_PVR_VALUE(r3)	465	lwz r9,CPU_SPEC_PVR_VALUE(r3)
466	cmplw 0,r9,r8	466	cmplw 0,r9,r8
467	beq 1f	467	beq 1f
468	addi r3,r3,CPU_SPEC_ENTRY_SIZE	468	addi r3,r3,CPU_SPEC_ENTRY_SIZE
469	b 1b	469	b 1b
470	1:	470	1:
471	add r0,r3,r5	471	add r0,r3,r5
472	std r0,0(r4)	472	std r0,0(r4)
473	ld r4,CPU_SPEC_SETUP(r3)	473	ld r4,CPU_SPEC_SETUP(r3)
474	sub r4,r4,r5	474	sub r4,r4,r5
475	ld r4,0(r4)	475	ld r4,0(r4)
476	sub r4,r4,r5	476	sub r4,r4,r5
477	mtctr r4	477	mtctr r4
478	/* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */	478	/* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */
479	mr r4,r3	479	mr r4,r3
480	mr r3,r5	480	mr r3,r5
481	bctr	481	bctr
482		482
483	/*	483	/*
484	* do_cpu_ftr_fixups - goes through the list of CPU feature fixups	484	* do_cpu_ftr_fixups - goes through the list of CPU feature fixups
485	* and writes nop's over sections of code that don't apply for this cpu.	485	* and writes nop's over sections of code that don't apply for this cpu.
486	* r3 = data offset (not changed)	486	* r3 = data offset (not changed)
487	*/	487	*/
488	_GLOBAL(do_cpu_ftr_fixups)	488	_GLOBAL(do_cpu_ftr_fixups)
489	/* Get CPU 0 features */	489	/* Get CPU 0 features */
490	LOADADDR(r6,cur_cpu_spec)	490	LOADADDR(r6,cur_cpu_spec)
491	sub r6,r6,r3	491	sub r6,r6,r3
492	ld r4,0(r6)	492	ld r4,0(r6)
493	sub r4,r4,r3	493	sub r4,r4,r3
494	ld r4,CPU_SPEC_FEATURES(r4)	494	ld r4,CPU_SPEC_FEATURES(r4)
495	/* Get the fixup table */	495	/* Get the fixup table */
496	LOADADDR(r6,__start___ftr_fixup)	496	LOADADDR(r6,__start___ftr_fixup)
497	sub r6,r6,r3	497	sub r6,r6,r3
498	LOADADDR(r7,__stop___ftr_fixup)	498	LOADADDR(r7,__stop___ftr_fixup)
499	sub r7,r7,r3	499	sub r7,r7,r3
500	/* Do the fixup */	500	/* Do the fixup */
501	1: cmpld r6,r7	501	1: cmpld r6,r7
502	bgelr	502	bgelr
503	addi r6,r6,32	503	addi r6,r6,32
504	ld r8,-32(r6) /* mask */	504	ld r8,-32(r6) /* mask */
505	and r8,r8,r4	505	and r8,r8,r4
506	ld r9,-24(r6) /* value */	506	ld r9,-24(r6) /* value */
507	cmpld r8,r9	507	cmpld r8,r9
508	beq 1b	508	beq 1b
509	ld r8,-16(r6) /* section begin */	509	ld r8,-16(r6) /* section begin */
510	ld r9,-8(r6) /* section end */	510	ld r9,-8(r6) /* section end */
511	subf. r9,r8,r9	511	subf. r9,r8,r9
512	beq 1b	512	beq 1b
513	/* write nops over the section of code */	513	/* write nops over the section of code */
514	/* todo: if large section, add a branch at the start of it */	514	/* todo: if large section, add a branch at the start of it */
515	srwi r9,r9,2	515	srwi r9,r9,2
516	mtctr r9	516	mtctr r9
517	sub r8,r8,r3	517	sub r8,r8,r3
518	lis r0,0x60000000@h /* nop */	518	lis r0,0x60000000@h /* nop */
519	3: stw r0,0(r8)	519	3: stw r0,0(r8)
520	andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l	520	andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
521	beq 2f	521	beq 2f
522	dcbst 0,r8 /* suboptimal, but simpler */	522	dcbst 0,r8 /* suboptimal, but simpler */
523	sync	523	sync
524	icbi 0,r8	524	icbi 0,r8
525	2: addi r8,r8,4	525	2: addi r8,r8,4
526	bdnz 3b	526	bdnz 3b
527	sync /* additional sync needed on g4 */	527	sync /* additional sync needed on g4 */
528	isync	528	isync
529	b 1b	529	b 1b
530		530
531	#if defined(CONFIG_PPC_PMAC) \|\| defined(CONFIG_PPC_MAPLE)	531	#if defined(CONFIG_PPC_PMAC) \|\| defined(CONFIG_PPC_MAPLE)
532	/*	532	/*
533	* Do an IO access in real mode	533	* Do an IO access in real mode
534	*/	534	*/
535	_GLOBAL(real_readb)	535	_GLOBAL(real_readb)
536	mfmsr r7	536	mfmsr r7
537	ori r0,r7,MSR_DR	537	ori r0,r7,MSR_DR
538	xori r0,r0,MSR_DR	538	xori r0,r0,MSR_DR
539	sync	539	sync
540	mtmsrd r0	540	mtmsrd r0
541	sync	541	sync
542	isync	542	isync
543	mfspr r6,SPRN_HID4	543	mfspr r6,SPRN_HID4
544	rldicl r5,r6,32,0	544	rldicl r5,r6,32,0
545	ori r5,r5,0x100	545	ori r5,r5,0x100
546	rldicl r5,r5,32,0	546	rldicl r5,r5,32,0
547	sync	547	sync
548	mtspr SPRN_HID4,r5	548	mtspr SPRN_HID4,r5
549	isync	549	isync
550	slbia	550	slbia
551	isync	551	isync
552	lbz r3,0(r3)	552	lbz r3,0(r3)
553	sync	553	sync
554	mtspr SPRN_HID4,r6	554	mtspr SPRN_HID4,r6
555	isync	555	isync
556	slbia	556	slbia
557	isync	557	isync
558	mtmsrd r7	558	mtmsrd r7
559	sync	559	sync
560	isync	560	isync
561	blr	561	blr
562		562
563	/*	563	/*
564	* Do an IO access in real mode	564	* Do an IO access in real mode
565	*/	565	*/
566	_GLOBAL(real_writeb)	566	_GLOBAL(real_writeb)
567	mfmsr r7	567	mfmsr r7
568	ori r0,r7,MSR_DR	568	ori r0,r7,MSR_DR
569	xori r0,r0,MSR_DR	569	xori r0,r0,MSR_DR
570	sync	570	sync
571	mtmsrd r0	571	mtmsrd r0
572	sync	572	sync
573	isync	573	isync
574	mfspr r6,SPRN_HID4	574	mfspr r6,SPRN_HID4
575	rldicl r5,r6,32,0	575	rldicl r5,r6,32,0
576	ori r5,r5,0x100	576	ori r5,r5,0x100
577	rldicl r5,r5,32,0	577	rldicl r5,r5,32,0
578	sync	578	sync
579	mtspr SPRN_HID4,r5	579	mtspr SPRN_HID4,r5
580	isync	580	isync
581	slbia	581	slbia
582	isync	582	isync
583	stb r3,0(r4)	583	stb r3,0(r4)
584	sync	584	sync
585	mtspr SPRN_HID4,r6	585	mtspr SPRN_HID4,r6
586	isync	586	isync
587	slbia	587	slbia
588	isync	588	isync
589	mtmsrd r7	589	mtmsrd r7
590	sync	590	sync
591	isync	591	isync
592	blr	592	blr
593	#endif /* defined(CONFIG_PPC_PMAC) \|\| defined(CONFIG_PPC_MAPLE) */	593	#endif /* defined(CONFIG_PPC_PMAC) \|\| defined(CONFIG_PPC_MAPLE) */
594		594
595	/*	595	/*
596	* SCOM access functions for 970 (FX only for now)	596	* SCOM access functions for 970 (FX only for now)
597	*	597	*
598	* unsigned long scom970_read(unsigned int address);	598	* unsigned long scom970_read(unsigned int address);
599	* void scom970_write(unsigned int address, unsigned long value);	599	* void scom970_write(unsigned int address, unsigned long value);
600	*	600	*
601	* The address passed in is the 24 bits register address. This code	601	* The address passed in is the 24 bits register address. This code
602	* is 970 specific and will not check the status bits, so you should	602	* is 970 specific and will not check the status bits, so you should
603	* know what you are doing.	603	* know what you are doing.
604	*/	604	*/
605	_GLOBAL(scom970_read)	605	_GLOBAL(scom970_read)
606	/* interrupts off */	606	/* interrupts off */
607	mfmsr r4	607	mfmsr r4
608	ori r0,r4,MSR_EE	608	ori r0,r4,MSR_EE
609	xori r0,r0,MSR_EE	609	xori r0,r0,MSR_EE
610	mtmsrd r0,1	610	mtmsrd r0,1
611		611
612	/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits	612	/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
613	* (including parity). On current CPUs they must be 0'd,	613	* (including parity). On current CPUs they must be 0'd,
614	* and finally or in RW bit	614	* and finally or in RW bit
615	*/	615	*/
616	rlwinm r3,r3,8,0,15	616	rlwinm r3,r3,8,0,15
617	ori r3,r3,0x8000	617	ori r3,r3,0x8000
618		618
619	/* do the actual scom read */	619	/* do the actual scom read */
620	sync	620	sync
621	mtspr SPRN_SCOMC,r3	621	mtspr SPRN_SCOMC,r3
622	isync	622	isync
623	mfspr r3,SPRN_SCOMD	623	mfspr r3,SPRN_SCOMD
624	isync	624	isync
625	mfspr r0,SPRN_SCOMC	625	mfspr r0,SPRN_SCOMC
626	isync	626	isync
627		627
628	/* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah	628	/* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
629	* that's the best we can do). Not implemented yet as we don't use	629	* that's the best we can do). Not implemented yet as we don't use
630	* the scom on any of the bogus CPUs yet, but may have to be done	630	* the scom on any of the bogus CPUs yet, but may have to be done
631	* ultimately	631	* ultimately
632	*/	632	*/
633		633
634	/* restore interrupts */	634	/* restore interrupts */
635	mtmsrd r4,1	635	mtmsrd r4,1
636	blr	636	blr
637		637
638		638
639	_GLOBAL(scom970_write)	639	_GLOBAL(scom970_write)
640	/* interrupts off */	640	/* interrupts off */
641	mfmsr r5	641	mfmsr r5
642	ori r0,r5,MSR_EE	642	ori r0,r5,MSR_EE
643	xori r0,r0,MSR_EE	643	xori r0,r0,MSR_EE
644	mtmsrd r0,1	644	mtmsrd r0,1
645		645
646	/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits	646	/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
647	* (including parity). On current CPUs they must be 0'd.	647	* (including parity). On current CPUs they must be 0'd.
648	*/	648	*/
649		649
650	rlwinm r3,r3,8,0,15	650	rlwinm r3,r3,8,0,15
651		651
652	sync	652	sync
653	mtspr SPRN_SCOMD,r4 /* write data */	653	mtspr SPRN_SCOMD,r4 /* write data */
654	isync	654	isync
655	mtspr SPRN_SCOMC,r3 /* write command */	655	mtspr SPRN_SCOMC,r3 /* write command */
656	isync	656	isync
657	mfspr 3,SPRN_SCOMC	657	mfspr 3,SPRN_SCOMC
658	isync	658	isync
659		659
660	/* restore interrupts */	660	/* restore interrupts */
661	mtmsrd r5,1	661	mtmsrd r5,1
662	blr	662	blr
663		663
664		664
665	/*	665	/*
666	* Create a kernel thread	666	* Create a kernel thread
667	* kernel_thread(fn, arg, flags)	667	* kernel_thread(fn, arg, flags)
668	*/	668	*/
669	_GLOBAL(kernel_thread)	669	_GLOBAL(kernel_thread)
670	std r29,-24(r1)	670	std r29,-24(r1)
671	std r30,-16(r1)	671	std r30,-16(r1)
672	stdu r1,-STACK_FRAME_OVERHEAD(r1)	672	stdu r1,-STACK_FRAME_OVERHEAD(r1)
673	mr r29,r3	673	mr r29,r3
674	mr r30,r4	674	mr r30,r4
675	ori r3,r5,CLONE_VM /* flags */	675	ori r3,r5,CLONE_VM /* flags */
676	oris r3,r3,(CLONE_UNTRACED>>16)	676	oris r3,r3,(CLONE_UNTRACED>>16)
677	li r4,0 /* new sp (unused) */	677	li r4,0 /* new sp (unused) */
678	li r0,__NR_clone	678	li r0,__NR_clone
679	sc	679	sc
680	cmpdi 0,r3,0 /* parent or child? */	680	cmpdi 0,r3,0 /* parent or child? */
681	bne 1f /* return if parent */	681	bne 1f /* return if parent */
682	li r0,0	682	li r0,0
683	stdu r0,-STACK_FRAME_OVERHEAD(r1)	683	stdu r0,-STACK_FRAME_OVERHEAD(r1)
684	ld r2,8(r29)	684	ld r2,8(r29)
685	ld r29,0(r29)	685	ld r29,0(r29)
686	mtlr r29 /* fn addr in lr */	686	mtlr r29 /* fn addr in lr */
687	mr r3,r30 /* load arg and call fn */	687	mr r3,r30 /* load arg and call fn */
688	blrl	688	blrl
689	li r0,__NR_exit /* exit after child exits */	689	li r0,__NR_exit /* exit after child exits */
690	li r3,0	690	li r3,0
691	sc	691	sc
692	1: addi r1,r1,STACK_FRAME_OVERHEAD	692	1: addi r1,r1,STACK_FRAME_OVERHEAD
693	ld r29,-24(r1)	693	ld r29,-24(r1)
694	ld r30,-16(r1)	694	ld r30,-16(r1)
695	blr	695	blr
696		696
697	/*	697	/*
698	* disable_kernel_fp()	698	* disable_kernel_fp()
699	* Disable the FPU.	699	* Disable the FPU.
700	*/	700	*/
701	_GLOBAL(disable_kernel_fp)	701	_GLOBAL(disable_kernel_fp)
702	mfmsr r3	702	mfmsr r3
703	rldicl r0,r3,(63-MSR_FP_LG),1	703	rldicl r0,r3,(63-MSR_FP_LG),1
704	rldicl r3,r0,(MSR_FP_LG+1),0	704	rldicl r3,r0,(MSR_FP_LG+1),0
705	mtmsrd r3 /* disable use of fpu now */	705	mtmsrd r3 /* disable use of fpu now */
706	isync	706	isync
707	blr	707	blr
708		708
709	#ifdef CONFIG_ALTIVEC	709	#ifdef CONFIG_ALTIVEC
710		710
711	#if 0 /* this has no callers for now */	711	#if 0 /* this has no callers for now */
712	/*	712	/*
713	* disable_kernel_altivec()	713	* disable_kernel_altivec()
714	* Disable the VMX.	714	* Disable the VMX.
715	*/	715	*/
716	_GLOBAL(disable_kernel_altivec)	716	_GLOBAL(disable_kernel_altivec)
717	mfmsr r3	717	mfmsr r3
718	rldicl r0,r3,(63-MSR_VEC_LG),1	718	rldicl r0,r3,(63-MSR_VEC_LG),1
719	rldicl r3,r0,(MSR_VEC_LG+1),0	719	rldicl r3,r0,(MSR_VEC_LG+1),0
720	mtmsrd r3 /* disable use of VMX now */	720	mtmsrd r3 /* disable use of VMX now */
721	isync	721	isync
722	blr	722	blr
723	#endif /* 0 */	723	#endif /* 0 */
724		724
725	/*	725	/*
726	* giveup_altivec(tsk)	726	* giveup_altivec(tsk)
727	* Disable VMX for the task given as the argument,	727	* Disable VMX for the task given as the argument,
728	* and save the vector registers in its thread_struct.	728	* and save the vector registers in its thread_struct.
729	* Enables the VMX for use in the kernel on return.	729	* Enables the VMX for use in the kernel on return.
730	*/	730	*/
731	_GLOBAL(giveup_altivec)	731	_GLOBAL(giveup_altivec)
732	mfmsr r5	732	mfmsr r5
733	oris r5,r5,MSR_VEC@h	733	oris r5,r5,MSR_VEC@h
734	mtmsrd r5 /* enable use of VMX now */	734	mtmsrd r5 /* enable use of VMX now */
735	isync	735	isync
736	cmpdi 0,r3,0	736	cmpdi 0,r3,0
737	beqlr- /* if no previous owner, done */	737	beqlr- /* if no previous owner, done */
738	addi r3,r3,THREAD /* want THREAD of task */	738	addi r3,r3,THREAD /* want THREAD of task */
739	ld r5,PT_REGS(r3)	739	ld r5,PT_REGS(r3)
740	cmpdi 0,r5,0	740	cmpdi 0,r5,0
741	SAVE_32VRS(0,r4,r3)	741	SAVE_32VRS(0,r4,r3)
742	mfvscr vr0	742	mfvscr vr0
743	li r4,THREAD_VSCR	743	li r4,THREAD_VSCR
744	stvx vr0,r4,r3	744	stvx vr0,r4,r3
745	beq 1f	745	beq 1f
746	ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)	746	ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
747	lis r3,MSR_VEC@h	747	lis r3,MSR_VEC@h
748	andc r4,r4,r3 /* disable FP for previous task */	748	andc r4,r4,r3 /* disable FP for previous task */
749	std r4,_MSR-STACK_FRAME_OVERHEAD(r5)	749	std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
750	1:	750	1:
751	#ifndef CONFIG_SMP	751	#ifndef CONFIG_SMP
752	li r5,0	752	li r5,0
753	ld r4,last_task_used_altivec@got(r2)	753	ld r4,last_task_used_altivec@got(r2)
754	std r5,0(r4)	754	std r5,0(r4)
755	#endif /* CONFIG_SMP */	755	#endif /* CONFIG_SMP */
756	blr	756	blr
757		757
758	#endif /* CONFIG_ALTIVEC */	758	#endif /* CONFIG_ALTIVEC */
759		759
760	_GLOBAL(__setup_cpu_power3)	760	_GLOBAL(__setup_cpu_power3)
761	blr	761	blr
762		762
763	_GLOBAL(execve)	763	_GLOBAL(execve)
764	li r0,__NR_execve	764	li r0,__NR_execve
765	sc	765	sc
766	bnslr	766	bnslr
767	neg r3,r3	767	neg r3,r3
768	blr	768	blr
769		769
770	/* kexec_wait(phys_cpu)	770	/* kexec_wait(phys_cpu)
771	*	771	*
772	* wait for the flag to change, indicating this kernel is going away but	772	* wait for the flag to change, indicating this kernel is going away but
773	* the slave code for the next one is at addresses 0 to 100.	773	* the slave code for the next one is at addresses 0 to 100.
774	*	774	*
775	* This is used by all slaves.	775	* This is used by all slaves.
776	*	776	*
777	* Physical (hardware) cpu id should be in r3.	777	* Physical (hardware) cpu id should be in r3.
778	*/	778	*/
779	_GLOBAL(kexec_wait)	779	_GLOBAL(kexec_wait)
780	bl 1f	780	bl 1f
781	1: mflr r5	781	1: mflr r5
782	addi r5,r5,kexec_flag-1b	782	addi r5,r5,kexec_flag-1b
783		783
784	99: HMT_LOW	784	99: HMT_LOW
785	#ifdef CONFIG_KEXEC /* use no memory without kexec */	785	#ifdef CONFIG_KEXEC /* use no memory without kexec */
786	lwz r4,0(r5)	786	lwz r4,0(r5)
787	cmpwi 0,r4,0	787	cmpwi 0,r4,0
788	bnea 0x60	788	bnea 0x60
789	#endif	789	#endif
790	b 99b	790	b 99b
791		791
792	/* this can be in text because we won't change it until we are	792	/* this can be in text because we won't change it until we are
793	* running in real anyways	793	* running in real anyways
794	*/	794	*/
795	kexec_flag:	795	kexec_flag:
796	.long 0	796	.long 0
797		797
798		798
799	#ifdef CONFIG_KEXEC	799	#ifdef CONFIG_KEXEC
800		800
801	/* kexec_smp_wait(void)	801	/* kexec_smp_wait(void)
802	*	802	*
803	* call with interrupts off	803	* call with interrupts off
804	* note: this is a terminal routine, it does not save lr	804	* note: this is a terminal routine, it does not save lr
805	*	805	*
806	* get phys id from paca	806	* get phys id from paca
807	* set paca id to -1 to say we got here	807	* set paca id to -1 to say we got here
808	* switch to real mode	808	* switch to real mode
809	* join other cpus in kexec_wait(phys_id)	809	* join other cpus in kexec_wait(phys_id)
810	*/	810	*/
811	_GLOBAL(kexec_smp_wait)	811	_GLOBAL(kexec_smp_wait)
812	lhz r3,PACAHWCPUID(r13)	812	lhz r3,PACAHWCPUID(r13)
813	li r4,-1	813	li r4,-1
814	sth r4,PACAHWCPUID(r13) /* let others know we left */	814	sth r4,PACAHWCPUID(r13) /* let others know we left */
815	bl real_mode	815	bl real_mode
816	b .kexec_wait	816	b .kexec_wait
817		817
818	/*	818	/*
819	* switch to real mode (turn mmu off)	819	* switch to real mode (turn mmu off)
820	* we use the early kernel trick that the hardware ignores bits	820	* we use the early kernel trick that the hardware ignores bits
821	* 0 and 1 (big endian) of the effective address in real mode	821	* 0 and 1 (big endian) of the effective address in real mode
822	*	822	*
823	* don't overwrite r3 here, it is live for kexec_wait above.	823	* don't overwrite r3 here, it is live for kexec_wait above.
824	*/	824	*/
825	real_mode: /* assume normal blr return */	825	real_mode: /* assume normal blr return */
826	1: li r9,MSR_RI	826	1: li r9,MSR_RI
827	li r10,MSR_DR\|MSR_IR	827	li r10,MSR_DR\|MSR_IR
828	mflr r11 /* return address to SRR0 */	828	mflr r11 /* return address to SRR0 */
829	mfmsr r12	829	mfmsr r12
830	andc r9,r12,r9	830	andc r9,r12,r9
831	andc r10,r12,r10	831	andc r10,r12,r10
832		832
833	mtmsrd r9,1	833	mtmsrd r9,1
834	mtspr SPRN_SRR1,r10	834	mtspr SPRN_SRR1,r10
835	mtspr SPRN_SRR0,r11	835	mtspr SPRN_SRR0,r11
836	rfid	836	rfid
837		837
838		838
839	/*	839	/*
840	* kexec_sequence(newstack, start, image, control, clear_all())	840	* kexec_sequence(newstack, start, image, control, clear_all())
841	*	841	*
842	* does the grungy work with stack switching and real mode switches	842	* does the grungy work with stack switching and real mode switches
843	* also does simple calls to other code	843	* also does simple calls to other code
844	*/	844	*/
845		845
846	_GLOBAL(kexec_sequence)	846	_GLOBAL(kexec_sequence)
847	mflr r0	847	mflr r0
848	std r0,16(r1)	848	std r0,16(r1)
849		849
850	/* switch stacks to newstack -- &kexec_stack.stack */	850	/* switch stacks to newstack -- &kexec_stack.stack */
851	stdu r1,THREAD_SIZE-112(r3)	851	stdu r1,THREAD_SIZE-112(r3)
852	mr r1,r3	852	mr r1,r3
853		853
854	li r0,0	854	li r0,0
855	std r0,16(r1)	855	std r0,16(r1)
856		856
857	/* save regs for local vars on new stack.	857	/* save regs for local vars on new stack.
858	* yes, we won't go back, but ...	858	* yes, we won't go back, but ...
859	*/	859	*/
860	std r31,-8(r1)	860	std r31,-8(r1)
861	std r30,-16(r1)	861	std r30,-16(r1)
862	std r29,-24(r1)	862	std r29,-24(r1)
863	std r28,-32(r1)	863	std r28,-32(r1)
864	std r27,-40(r1)	864	std r27,-40(r1)
865	std r26,-48(r1)	865	std r26,-48(r1)
866	std r25,-56(r1)	866	std r25,-56(r1)
867		867
868	stdu r1,-112-64(r1)	868	stdu r1,-112-64(r1)
869		869
870	/* save args into preserved regs */	870	/* save args into preserved regs */
871	mr r31,r3 /* newstack (both) */	871	mr r31,r3 /* newstack (both) */
872	mr r30,r4 /* start (real) */	872	mr r30,r4 /* start (real) */
873	mr r29,r5 /* image (virt) */	873	mr r29,r5 /* image (virt) */
874	mr r28,r6 /* control, unused */	874	mr r28,r6 /* control, unused */
875	mr r27,r7 /* clear_all() fn desc */	875	mr r27,r7 /* clear_all() fn desc */
876	mr r26,r8 /* spare */	876	mr r26,r8 /* spare */
877	lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */	877	lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
878		878
879	/* disable interrupts, we are overwriting kernel data next */	879	/* disable interrupts, we are overwriting kernel data next */
880	mfmsr r3	880	mfmsr r3
881	rlwinm r3,r3,0,17,15	881	rlwinm r3,r3,0,17,15
882	mtmsrd r3,1	882	mtmsrd r3,1
883		883
884	/* copy dest pages, flush whole dest image */	884	/* copy dest pages, flush whole dest image */
885	mr r3,r29	885	mr r3,r29
886	bl .kexec_copy_flush /* (image) */	886	bl .kexec_copy_flush /* (image) */
887		887
888	/* turn off mmu */	888	/* turn off mmu */
889	bl real_mode	889	bl real_mode
890		890
891	/* clear out hardware hash page table and tlb */	891	/* clear out hardware hash page table and tlb */
892	ld r5,0(r27) /* deref function descriptor */	892	ld r5,0(r27) /* deref function descriptor */
893	mtctr r5	893	mtctr r5
894	bctrl /* ppc_md.hash_clear_all(void); */	894	bctrl /* ppc_md.hash_clear_all(void); */
895		895
896	/*	896	/*
897	* kexec image calling is:	897	* kexec image calling is:
898	* the first 0x100 bytes of the entry point are copied to 0	898	* the first 0x100 bytes of the entry point are copied to 0
899	*	899	*
900	* all slaves branch to slave = 0x60 (absolute)	900	* all slaves branch to slave = 0x60 (absolute)
901	* slave(phys_cpu_id);	901	* slave(phys_cpu_id);
902	*	902	*
903	* master goes to start = entry point	903	* master goes to start = entry point
904	* start(phys_cpu_id, start, 0);	904	* start(phys_cpu_id, start, 0);
905	*	905	*
906	*	906	*
907	* a wrapper is needed to call existing kernels, here is an approximate	907	* a wrapper is needed to call existing kernels, here is an approximate
908	* description of one method:	908	* description of one method:
909	*	909	*
910	* v2: (2.6.10)	910	* v2: (2.6.10)
911	* start will be near the boot_block (maybe 0x100 bytes before it?)	911	* start will be near the boot_block (maybe 0x100 bytes before it?)
912	* it will have a 0x60, which will b to boot_block, where it will wait	912	* it will have a 0x60, which will b to boot_block, where it will wait
913	* and 0 will store phys into struct boot-block and load r3 from there,	913	* and 0 will store phys into struct boot-block and load r3 from there,
914	* copy kernel 0-0x100 and tell slaves to back down to 0x60 again	914	* copy kernel 0-0x100 and tell slaves to back down to 0x60 again
915	*	915	*
916	* v1: (2.6.9)	916	* v1: (2.6.9)
917	* boot block will have all cpus scanning device tree to see if they	917	* boot block will have all cpus scanning device tree to see if they
918	* are the boot cpu ?????	918	* are the boot cpu ?????
919	* other device tree differences (prop sizes, va vs pa, etc)...	919	* other device tree differences (prop sizes, va vs pa, etc)...
920	*/	920	*/
921		921
922	/* copy 0x100 bytes starting at start to 0 */	922	/* copy 0x100 bytes starting at start to 0 */
923	li r3,0	923	li r3,0
924	mr r4,r30	924	mr r4,r30
925	li r5,0x100	925	li r5,0x100
926	li r6,0	926	li r6,0
927	bl .copy_and_flush /* (dest, src, copy limit, start offset) */	927	bl .copy_and_flush /* (dest, src, copy limit, start offset) */
928	1: /* assume normal blr return */	928	1: /* assume normal blr return */
929		929
930	/* release other cpus to the new kernel secondary start at 0x60 */	930	/* release other cpus to the new kernel secondary start at 0x60 */
931	mflr r5	931	mflr r5
932	li r6,1	932	li r6,1
933	stw r6,kexec_flag-1b(5)	933	stw r6,kexec_flag-1b(5)
934	mr r3,r25 # my phys cpu	934	mr r3,r25 # my phys cpu
935	mr r4,r30 # start, aka phys mem offset	935	mr r4,r30 # start, aka phys mem offset
936	mtlr 4	936	mtlr 4
937	li r5,0	937	li r5,0
938	blr /* image->start(physid, image->start, 0); */	938	blr /* image->start(physid, image->start, 0); */
939	#endif /* CONFIG_KEXEC */	939	#endif /* CONFIG_KEXEC */
940		940

include/asm-powerpc/hw_irq.h

Diff comments View file @ d4be4f3

 /*
  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
  */
 #ifndef _ASM_POWERPC_HW_IRQ_H
 #define _ASM_POWERPC_HW_IRQ_H
 #ifdef __KERNEL__
 #include <linux/config.h>
 #include <linux/errno.h>
 #include <asm/ptrace.h>
 #include <asm/processor.h>
 extern void timer_interrupt(struct pt_regs *);
-extern void ppc_irq_dispatch_handler(struct pt_regs *regs, int irq);
 #ifdef CONFIG_PPC_ISERIES
 extern unsigned long local_get_flags(void);
 extern unsigned long local_irq_disable(void);
 extern void local_irq_restore(unsigned long);
 #define local_irq_enable()	local_irq_restore(1)
 #define local_save_flags(flags)	((flags) = local_get_flags())
 #define local_irq_save(flags)	((flags) = local_irq_disable())
 #define irqs_disabled()		(local_get_flags() == 0)
 #else
 #if defined(CONFIG_BOOKE)
 #define SET_MSR_EE(x)	mtmsr(x)
 #define local_irq_restore(flags)	__asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
 #elif defined(__powerpc64__)
 #define SET_MSR_EE(x)	__mtmsrd(x, 1)
 #define local_irq_restore(flags) do { \
 	__asm__ __volatile__("": : :"memory"); \
 	__mtmsrd((flags), 1); \
 } while(0)
 #else
 #define SET_MSR_EE(x)	mtmsr(x)
 #define local_irq_restore(flags)	mtmsr(flags)
 #endif
 static inline void local_irq_disable(void)
 {
 #ifdef CONFIG_BOOKE
 	__asm__ __volatile__("wrteei 0": : :"memory");
 #else
 	unsigned long msr;
 	__asm__ __volatile__("": : :"memory");
 	msr = mfmsr();
 	SET_MSR_EE(msr & ~MSR_EE);
 #endif
 }
 static inline void local_irq_enable(void)
 {
 #ifdef CONFIG_BOOKE
 	__asm__ __volatile__("wrteei 1": : :"memory");
 #else
 	unsigned long msr;
 	__asm__ __volatile__("": : :"memory");
 	msr = mfmsr();
 	SET_MSR_EE(msr | MSR_EE);
 #endif
 }
 static inline void local_irq_save_ptr(unsigned long *flags)
 {
 	unsigned long msr;
 	msr = mfmsr();
 	*flags = msr;
 #ifdef CONFIG_BOOKE
 	__asm__ __volatile__("wrteei 0": : :"memory");
 #else
 	SET_MSR_EE(msr & ~MSR_EE);
 #endif
 	__asm__ __volatile__("": : :"memory");
 }
 #define local_save_flags(flags)	((flags) = mfmsr())
 #define local_irq_save(flags)	local_irq_save_ptr(&flags)
 #define irqs_disabled()		((mfmsr() & MSR_EE) == 0)
 #endif /* CONFIG_PPC_ISERIES */
 #define mask_irq(irq)						\
 	({							\
 	 	irq_desc_t *desc = get_irq_desc(irq);		\
 		if (desc->handler && desc->handler->disable)	\
 			desc->handler->disable(irq);		\
 	})
 #define unmask_irq(irq)						\
 	({							\
 	 	irq_desc_t *desc = get_irq_desc(irq);		\
 		if (desc->handler && desc->handler->enable)	\
 			desc->handler->enable(irq);		\
 	})
 #define ack_irq(irq)						\
 	({							\
 	 	irq_desc_t *desc = get_irq_desc(irq);		\
 		if (desc->handler && desc->handler->ack)	\
 			desc->handler->ack(irq);		\
 	})
 /* Should we handle this via lost interrupts and IPIs or should we don't care like
  * we do now ? --BenH.
  */
 struct hw_interrupt_type;
 static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
 #endif	/* __KERNEL__ */
 #endif	/* _ASM_POWERPC_HW_IRQ_H */

include/asm-powerpc/irq.h

Diff comments View file @ d4be4f3