Commit db77ec270d00098ff4fbf15f62f4506f6efb25d2

Authored by Alan Curry
Committed by Linus Torvalds
1 parent 59153f7d7e

[PATCH] framebuffer: cmap-setting return values

A set of 3 small bugfixes, all of which are related to bogus return values
of fb colormap-setting functions.

First, fb_alloc_cmap returns -1 if memory allocation fails. This is a hard
condition to reproduce since you'd have to be really low on memory, but from
studying the contexts in which it is called, I think this function should be
returning a negative errno, and the -1 will be seen as an EPERM. Switching it
to -ENOMEM makes sense.

Second, the store_cmap function which is called for writes to
/sys/class/graphics/fb0/color_map returns 0 for success, but it should be
returning the count of bytes written since its return value ends up in
userspace as the result of the write() syscall.

Third, radeonfb returns 1 instead of a negative errno when FBIOPUTCMAP is
called with an oversized colormap.  This is seen in userspace as a return
value of 1 from the ioctl() syscall with errno left unchanged.  A more
useful return value would be -EINVAL.

Signed-off-by: Alan Curry <pacman@TheWorld.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Showing 3 changed files with 7 additions and 7 deletions Inline Diff

drivers/video/aty/radeon_base.c
1 /* 1 /*
2 * drivers/video/aty/radeon_base.c 2 * drivers/video/aty/radeon_base.c
3 * 3 *
4 * framebuffer driver for ATI Radeon chipset video boards 4 * framebuffer driver for ATI Radeon chipset video boards
5 * 5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org> 6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org> 7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 * 8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net> 9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 * 10 *
11 * Special thanks to ATI DevRel team for their hardware donations. 11 * Special thanks to ATI DevRel team for their hardware donations.
12 * 12 *
13 * ...Insert GPL boilerplate here... 13 * ...Insert GPL boilerplate here...
14 * 14 *
15 * Significant portions of this driver apdated from XFree86 Radeon 15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice: 16 * driver which has the following copyright notice:
17 * 17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California. 19 * VA Linux Systems Inc., Fremont, California.
20 * 20 *
21 * All Rights Reserved. 21 * All Rights Reserved.
22 * 22 *
23 * Permission is hereby granted, free of charge, to any person obtaining 23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the 24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including 25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge, 26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software, 27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so, 28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions: 29 * subject to the following conditions:
30 * 30 *
31 * The above copyright notice and this permission notice (including the 31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial 32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software. 33 * portions of the Software.
34 * 34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE. 42 * DEALINGS IN THE SOFTWARE.
43 * 43 *
44 * XFree86 driver authors: 44 * XFree86 driver authors:
45 * 45 *
46 * Kevin E. Martin <martin@xfree86.org> 46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com> 47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk> 48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 * 49 *
50 */ 50 */
51 51
52 52
53 #define RADEON_VERSION "0.2.0" 53 #define RADEON_VERSION "0.2.0"
54 54
55 #include <linux/config.h> 55 #include <linux/config.h>
56 #include <linux/module.h> 56 #include <linux/module.h>
57 #include <linux/moduleparam.h> 57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h> 58 #include <linux/kernel.h>
59 #include <linux/errno.h> 59 #include <linux/errno.h>
60 #include <linux/string.h> 60 #include <linux/string.h>
61 #include <linux/mm.h> 61 #include <linux/mm.h>
62 #include <linux/tty.h> 62 #include <linux/tty.h>
63 #include <linux/slab.h> 63 #include <linux/slab.h>
64 #include <linux/delay.h> 64 #include <linux/delay.h>
65 #include <linux/time.h> 65 #include <linux/time.h>
66 #include <linux/fb.h> 66 #include <linux/fb.h>
67 #include <linux/ioport.h> 67 #include <linux/ioport.h>
68 #include <linux/init.h> 68 #include <linux/init.h>
69 #include <linux/pci.h> 69 #include <linux/pci.h>
70 #include <linux/vmalloc.h> 70 #include <linux/vmalloc.h>
71 #include <linux/device.h> 71 #include <linux/device.h>
72 72
73 #include <asm/io.h> 73 #include <asm/io.h>
74 #include <asm/uaccess.h> 74 #include <asm/uaccess.h>
75 75
76 #ifdef CONFIG_PPC_OF 76 #ifdef CONFIG_PPC_OF
77 77
78 #include <asm/pci-bridge.h> 78 #include <asm/pci-bridge.h>
79 #include "../macmodes.h" 79 #include "../macmodes.h"
80 80
81 #ifdef CONFIG_PMAC_BACKLIGHT 81 #ifdef CONFIG_PMAC_BACKLIGHT
82 #include <asm/backlight.h> 82 #include <asm/backlight.h>
83 #endif 83 #endif
84 84
85 #ifdef CONFIG_BOOTX_TEXT 85 #ifdef CONFIG_BOOTX_TEXT
86 #include <asm/btext.h> 86 #include <asm/btext.h>
87 #endif 87 #endif
88 88
89 #endif /* CONFIG_PPC_OF */ 89 #endif /* CONFIG_PPC_OF */
90 90
91 #ifdef CONFIG_MTRR 91 #ifdef CONFIG_MTRR
92 #include <asm/mtrr.h> 92 #include <asm/mtrr.h>
93 #endif 93 #endif
94 94
95 #include <video/radeon.h> 95 #include <video/radeon.h>
96 #include <linux/radeonfb.h> 96 #include <linux/radeonfb.h>
97 97
98 #include "../edid.h" // MOVE THAT TO include/video 98 #include "../edid.h" // MOVE THAT TO include/video
99 #include "ati_ids.h" 99 #include "ati_ids.h"
100 #include "radeonfb.h" 100 #include "radeonfb.h"
101 101
102 #define MAX_MAPPED_VRAM (2048*2048*4) 102 #define MAX_MAPPED_VRAM (2048*2048*4)
103 #define MIN_MAPPED_VRAM (1024*768*1) 103 #define MIN_MAPPED_VRAM (1024*768*1)
104 104
105 #define CHIP_DEF(id, family, flags) \ 105 #define CHIP_DEF(id, family, flags) \
106 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) } 106 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
107 107
108 static struct pci_device_id radeonfb_pci_table[] = { 108 static struct pci_device_id radeonfb_pci_table[] = {
109 /* Mobility M6 */ 109 /* Mobility M6 */
110 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 110 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
111 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 111 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
112 /* Radeon VE/7000 */ 112 /* Radeon VE/7000 */
113 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2), 113 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
114 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2), 114 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
115 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2), 115 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
116 /* Radeon IGP320M (U1) */ 116 /* Radeon IGP320M (U1) */
117 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 117 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
118 /* Radeon IGP320 (A3) */ 118 /* Radeon IGP320 (A3) */
119 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 119 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
120 /* IGP330M/340M/350M (U2) */ 120 /* IGP330M/340M/350M (U2) */
121 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 121 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
122 /* IGP330/340/350 (A4) */ 122 /* IGP330/340/350 (A4) */
123 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 123 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
124 /* Mobility 7000 IGP */ 124 /* Mobility 7000 IGP */
125 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 125 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
126 /* 7000 IGP (A4+) */ 126 /* 7000 IGP (A4+) */
127 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 127 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
128 /* 8500 AIW */ 128 /* 8500 AIW */
129 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2), 129 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
130 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2), 130 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
131 /* 8700/8800 */ 131 /* 8700/8800 */
132 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2), 132 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
133 /* 8500 */ 133 /* 8500 */
134 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2), 134 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
135 /* 9100 */ 135 /* 9100 */
136 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2), 136 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
137 /* Mobility M7 */ 137 /* Mobility M7 */
138 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 138 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 139 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 /* 7500 */ 140 /* 7500 */
141 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2), 141 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
142 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2), 142 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
143 /* Mobility M9 */ 143 /* Mobility M9 */
144 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 144 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 145 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
146 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 146 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
147 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 147 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
148 /* 9000/Pro */ 148 /* 9000/Pro */
149 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2), 149 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
150 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2), 150 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
151 /* Mobility 9100 IGP (U3) */ 151 /* Mobility 9100 IGP (U3) */
152 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 152 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
153 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 153 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
154 /* 9100 IGP (A5) */ 154 /* 9100 IGP (A5) */
155 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 155 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
156 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 156 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
157 /* Mobility 9200 (M9+) */ 157 /* Mobility 9200 (M9+) */
158 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 158 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
159 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 159 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
160 /* 9200 */ 160 /* 9200 */
161 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2), 161 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
162 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2), 162 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2), 163 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2), 164 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
165 /* 9500 */ 165 /* 9500 */
166 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2), 166 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
167 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2), 167 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
168 /* 9600TX / FireGL Z1 */ 168 /* 9600TX / FireGL Z1 */
169 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2), 169 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
170 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2), 170 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
171 /* 9700/9500/Pro/FireGL X1 */ 171 /* 9700/9500/Pro/FireGL X1 */
172 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2), 172 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
173 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2), 173 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
174 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2), 174 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
175 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2), 175 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
176 /* Mobility M10/M11 */ 176 /* Mobility M10/M11 */
177 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 177 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 178 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 179 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 180 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 181 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 182 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
183 /* 9600/FireGL T2 */ 183 /* 9600/FireGL T2 */
184 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2), 184 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
185 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2), 185 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2), 186 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2), 187 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2), 188 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2), 189 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
190 /* 9800/Pro/FileGL X2 */ 190 /* 9800/Pro/FileGL X2 */
191 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2), 191 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2), 192 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2), 193 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2), 194 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2), 195 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2), 196 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2), 197 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2), 198 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
199 /* Newer stuff */ 199 /* Newer stuff */
200 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2), 200 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2), 201 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 202 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
203 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 203 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2), 204 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2), 205 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2), 206 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2), 207 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 208 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
209 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 209 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
210 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2), 210 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
211 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2), 211 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2), 212 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2), 213 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2), 214 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2), 215 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 216 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
217 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2), 217 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2), 218 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2), 219 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2), 220 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2), 221 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2), 222 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2), 223 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
224 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2), 224 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
225 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2), 225 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
226 /* Original Radeon/7200 */ 226 /* Original Radeon/7200 */
227 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0), 227 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
228 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0), 228 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
229 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0), 229 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
230 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0), 230 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
231 { 0, } 231 { 0, }
232 }; 232 };
233 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table); 233 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
234 234
235 235
236 typedef struct { 236 typedef struct {
237 u16 reg; 237 u16 reg;
238 u32 val; 238 u32 val;
239 } reg_val; 239 } reg_val;
240 240
241 241
242 /* these common regs are cleared before mode setting so they do not 242 /* these common regs are cleared before mode setting so they do not
243 * interfere with anything 243 * interfere with anything
244 */ 244 */
245 static reg_val common_regs[] = { 245 static reg_val common_regs[] = {
246 { OVR_CLR, 0 }, 246 { OVR_CLR, 0 },
247 { OVR_WID_LEFT_RIGHT, 0 }, 247 { OVR_WID_LEFT_RIGHT, 0 },
248 { OVR_WID_TOP_BOTTOM, 0 }, 248 { OVR_WID_TOP_BOTTOM, 0 },
249 { OV0_SCALE_CNTL, 0 }, 249 { OV0_SCALE_CNTL, 0 },
250 { SUBPIC_CNTL, 0 }, 250 { SUBPIC_CNTL, 0 },
251 { VIPH_CONTROL, 0 }, 251 { VIPH_CONTROL, 0 },
252 { I2C_CNTL_1, 0 }, 252 { I2C_CNTL_1, 0 },
253 { GEN_INT_CNTL, 0 }, 253 { GEN_INT_CNTL, 0 },
254 { CAP0_TRIG_CNTL, 0 }, 254 { CAP0_TRIG_CNTL, 0 },
255 { CAP1_TRIG_CNTL, 0 }, 255 { CAP1_TRIG_CNTL, 0 },
256 }; 256 };
257 257
258 /* 258 /*
259 * globals 259 * globals
260 */ 260 */
261 261
262 static char *mode_option; 262 static char *mode_option;
263 static char *monitor_layout; 263 static char *monitor_layout;
264 static int noaccel = 0; 264 static int noaccel = 0;
265 static int default_dynclk = -2; 265 static int default_dynclk = -2;
266 static int nomodeset = 0; 266 static int nomodeset = 0;
267 static int ignore_edid = 0; 267 static int ignore_edid = 0;
268 static int mirror = 0; 268 static int mirror = 0;
269 static int panel_yres = 0; 269 static int panel_yres = 0;
270 static int force_dfp = 0; 270 static int force_dfp = 0;
271 static int force_measure_pll = 0; 271 static int force_measure_pll = 0;
272 #ifdef CONFIG_MTRR 272 #ifdef CONFIG_MTRR
273 static int nomtrr = 0; 273 static int nomtrr = 0;
274 #endif 274 #endif
275 275
276 /* 276 /*
277 * prototypes 277 * prototypes
278 */ 278 */
279 279
280 280
281 #ifdef CONFIG_PPC_OF 281 #ifdef CONFIG_PPC_OF
282 282
283 #ifdef CONFIG_PMAC_BACKLIGHT 283 #ifdef CONFIG_PMAC_BACKLIGHT
284 static int radeon_set_backlight_enable(int on, int level, void *data); 284 static int radeon_set_backlight_enable(int on, int level, void *data);
285 static int radeon_set_backlight_level(int level, void *data); 285 static int radeon_set_backlight_level(int level, void *data);
286 static struct backlight_controller radeon_backlight_controller = { 286 static struct backlight_controller radeon_backlight_controller = {
287 radeon_set_backlight_enable, 287 radeon_set_backlight_enable,
288 radeon_set_backlight_level 288 radeon_set_backlight_level
289 }; 289 };
290 #endif /* CONFIG_PMAC_BACKLIGHT */ 290 #endif /* CONFIG_PMAC_BACKLIGHT */
291 291
292 #endif /* CONFIG_PPC_OF */ 292 #endif /* CONFIG_PPC_OF */
293 293
294 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev) 294 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
295 { 295 {
296 if (!rinfo->bios_seg) 296 if (!rinfo->bios_seg)
297 return; 297 return;
298 pci_unmap_rom(dev, rinfo->bios_seg); 298 pci_unmap_rom(dev, rinfo->bios_seg);
299 } 299 }
300 300
301 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev) 301 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
302 { 302 {
303 void __iomem *rom; 303 void __iomem *rom;
304 u16 dptr; 304 u16 dptr;
305 u8 rom_type; 305 u8 rom_type;
306 size_t rom_size; 306 size_t rom_size;
307 307
308 /* If this is a primary card, there is a shadow copy of the 308 /* If this is a primary card, there is a shadow copy of the
309 * ROM somewhere in the first meg. We will just ignore the copy 309 * ROM somewhere in the first meg. We will just ignore the copy
310 * and use the ROM directly. 310 * and use the ROM directly.
311 */ 311 */
312 312
313 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */ 313 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
314 unsigned int temp; 314 unsigned int temp;
315 temp = INREG(MPP_TB_CONFIG); 315 temp = INREG(MPP_TB_CONFIG);
316 temp &= 0x00ffffffu; 316 temp &= 0x00ffffffu;
317 temp |= 0x04 << 24; 317 temp |= 0x04 << 24;
318 OUTREG(MPP_TB_CONFIG, temp); 318 OUTREG(MPP_TB_CONFIG, temp);
319 temp = INREG(MPP_TB_CONFIG); 319 temp = INREG(MPP_TB_CONFIG);
320 320
321 rom = pci_map_rom(dev, &rom_size); 321 rom = pci_map_rom(dev, &rom_size);
322 if (!rom) { 322 if (!rom) {
323 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n", 323 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
324 pci_name(rinfo->pdev)); 324 pci_name(rinfo->pdev));
325 return -ENOMEM; 325 return -ENOMEM;
326 } 326 }
327 327
328 rinfo->bios_seg = rom; 328 rinfo->bios_seg = rom;
329 329
330 /* Very simple test to make sure it appeared */ 330 /* Very simple test to make sure it appeared */
331 if (BIOS_IN16(0) != 0xaa55) { 331 if (BIOS_IN16(0) != 0xaa55) {
332 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x " 332 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
333 "should be 0xaa55\n", 333 "should be 0xaa55\n",
334 pci_name(rinfo->pdev), BIOS_IN16(0)); 334 pci_name(rinfo->pdev), BIOS_IN16(0));
335 goto failed; 335 goto failed;
336 } 336 }
337 /* Look for the PCI data to check the ROM type */ 337 /* Look for the PCI data to check the ROM type */
338 dptr = BIOS_IN16(0x18); 338 dptr = BIOS_IN16(0x18);
339 339
340 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM 340 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
341 * for now, until I've verified this works everywhere. The goal here is more 341 * for now, until I've verified this works everywhere. The goal here is more
342 * to phase out Open Firmware images. 342 * to phase out Open Firmware images.
343 * 343 *
344 * Currently, we only look at the first PCI data, we could iteratre and deal with 344 * Currently, we only look at the first PCI data, we could iteratre and deal with
345 * them all, and we should use fb_bios_start relative to start of image and not 345 * them all, and we should use fb_bios_start relative to start of image and not
346 * relative start of ROM, but so far, I never found a dual-image ATI card 346 * relative start of ROM, but so far, I never found a dual-image ATI card
347 * 347 *
348 * typedef struct { 348 * typedef struct {
349 * u32 signature; + 0x00 349 * u32 signature; + 0x00
350 * u16 vendor; + 0x04 350 * u16 vendor; + 0x04
351 * u16 device; + 0x06 351 * u16 device; + 0x06
352 * u16 reserved_1; + 0x08 352 * u16 reserved_1; + 0x08
353 * u16 dlen; + 0x0a 353 * u16 dlen; + 0x0a
354 * u8 drevision; + 0x0c 354 * u8 drevision; + 0x0c
355 * u8 class_hi; + 0x0d 355 * u8 class_hi; + 0x0d
356 * u16 class_lo; + 0x0e 356 * u16 class_lo; + 0x0e
357 * u16 ilen; + 0x10 357 * u16 ilen; + 0x10
358 * u16 irevision; + 0x12 358 * u16 irevision; + 0x12
359 * u8 type; + 0x14 359 * u8 type; + 0x14
360 * u8 indicator; + 0x15 360 * u8 indicator; + 0x15
361 * u16 reserved_2; + 0x16 361 * u16 reserved_2; + 0x16
362 * } pci_data_t; 362 * } pci_data_t;
363 */ 363 */
364 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 364 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
365 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM" 365 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
366 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr)); 366 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
367 goto anyway; 367 goto anyway;
368 } 368 }
369 rom_type = BIOS_IN8(dptr + 0x14); 369 rom_type = BIOS_IN8(dptr + 0x14);
370 switch(rom_type) { 370 switch(rom_type) {
371 case 0: 371 case 0:
372 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n"); 372 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
373 break; 373 break;
374 case 1: 374 case 1:
375 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n"); 375 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
376 goto failed; 376 goto failed;
377 case 2: 377 case 2:
378 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n"); 378 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
379 goto failed; 379 goto failed;
380 default: 380 default:
381 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type); 381 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
382 goto failed; 382 goto failed;
383 } 383 }
384 anyway: 384 anyway:
385 /* Locate the flat panel infos, do some sanity checking !!! */ 385 /* Locate the flat panel infos, do some sanity checking !!! */
386 rinfo->fp_bios_start = BIOS_IN16(0x48); 386 rinfo->fp_bios_start = BIOS_IN16(0x48);
387 return 0; 387 return 0;
388 388
389 failed: 389 failed:
390 rinfo->bios_seg = NULL; 390 rinfo->bios_seg = NULL;
391 radeon_unmap_ROM(rinfo, dev); 391 radeon_unmap_ROM(rinfo, dev);
392 return -ENXIO; 392 return -ENXIO;
393 } 393 }
394 394
395 #ifdef CONFIG_X86 395 #ifdef CONFIG_X86
396 static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo) 396 static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
397 { 397 {
398 /* I simplified this code as we used to miss the signatures in 398 /* I simplified this code as we used to miss the signatures in
399 * a lot of case. It's now closer to XFree, we just don't check 399 * a lot of case. It's now closer to XFree, we just don't check
400 * for signatures at all... Something better will have to be done 400 * for signatures at all... Something better will have to be done
401 * if we end up having conflicts 401 * if we end up having conflicts
402 */ 402 */
403 u32 segstart; 403 u32 segstart;
404 void __iomem *rom_base = NULL; 404 void __iomem *rom_base = NULL;
405 405
406 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { 406 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
407 rom_base = ioremap(segstart, 0x10000); 407 rom_base = ioremap(segstart, 0x10000);
408 if (rom_base == NULL) 408 if (rom_base == NULL)
409 return -ENOMEM; 409 return -ENOMEM;
410 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) 410 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
411 break; 411 break;
412 iounmap(rom_base); 412 iounmap(rom_base);
413 rom_base = NULL; 413 rom_base = NULL;
414 } 414 }
415 if (rom_base == NULL) 415 if (rom_base == NULL)
416 return -ENXIO; 416 return -ENXIO;
417 417
418 /* Locate the flat panel infos, do some sanity checking !!! */ 418 /* Locate the flat panel infos, do some sanity checking !!! */
419 rinfo->bios_seg = rom_base; 419 rinfo->bios_seg = rom_base;
420 rinfo->fp_bios_start = BIOS_IN16(0x48); 420 rinfo->fp_bios_start = BIOS_IN16(0x48);
421 421
422 return 0; 422 return 0;
423 } 423 }
424 #endif 424 #endif
425 425
426 #ifdef CONFIG_PPC_OF 426 #ifdef CONFIG_PPC_OF
427 /* 427 /*
428 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device 428 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
429 * tree. Hopefully, ATI OF driver is kind enough to fill these 429 * tree. Hopefully, ATI OF driver is kind enough to fill these
430 */ 430 */
431 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo) 431 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
432 { 432 {
433 struct device_node *dp = rinfo->of_node; 433 struct device_node *dp = rinfo->of_node;
434 u32 *val; 434 u32 *val;
435 435
436 if (dp == NULL) 436 if (dp == NULL)
437 return -ENODEV; 437 return -ENODEV;
438 val = (u32 *) get_property(dp, "ATY,RefCLK", NULL); 438 val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);
439 if (!val || !*val) { 439 if (!val || !*val) {
440 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n"); 440 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
441 return -EINVAL; 441 return -EINVAL;
442 } 442 }
443 443
444 rinfo->pll.ref_clk = (*val) / 10; 444 rinfo->pll.ref_clk = (*val) / 10;
445 445
446 val = (u32 *) get_property(dp, "ATY,SCLK", NULL); 446 val = (u32 *) get_property(dp, "ATY,SCLK", NULL);
447 if (val && *val) 447 if (val && *val)
448 rinfo->pll.sclk = (*val) / 10; 448 rinfo->pll.sclk = (*val) / 10;
449 449
450 val = (u32 *) get_property(dp, "ATY,MCLK", NULL); 450 val = (u32 *) get_property(dp, "ATY,MCLK", NULL);
451 if (val && *val) 451 if (val && *val)
452 rinfo->pll.mclk = (*val) / 10; 452 rinfo->pll.mclk = (*val) / 10;
453 453
454 return 0; 454 return 0;
455 } 455 }
456 #endif /* CONFIG_PPC_OF */ 456 #endif /* CONFIG_PPC_OF */
457 457
458 /* 458 /*
459 * Read PLL infos from chip registers 459 * Read PLL infos from chip registers
460 */ 460 */
461 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo) 461 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
462 { 462 {
463 unsigned char ppll_div_sel; 463 unsigned char ppll_div_sel;
464 unsigned Ns, Nm, M; 464 unsigned Ns, Nm, M;
465 unsigned sclk, mclk, tmp, ref_div; 465 unsigned sclk, mclk, tmp, ref_div;
466 int hTotal, vTotal, num, denom, m, n; 466 int hTotal, vTotal, num, denom, m, n;
467 unsigned long long hz, vclk; 467 unsigned long long hz, vclk;
468 long xtal; 468 long xtal;
469 struct timeval start_tv, stop_tv; 469 struct timeval start_tv, stop_tv;
470 long total_secs, total_usecs; 470 long total_secs, total_usecs;
471 int i; 471 int i;
472 472
473 /* Ugh, we cut interrupts, bad bad bad, but we want some precision 473 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
474 * here, so... --BenH 474 * here, so... --BenH
475 */ 475 */
476 476
477 /* Flush PCI buffers ? */ 477 /* Flush PCI buffers ? */
478 tmp = INREG16(DEVICE_ID); 478 tmp = INREG16(DEVICE_ID);
479 479
480 local_irq_disable(); 480 local_irq_disable();
481 481
482 for(i=0; i<1000000; i++) 482 for(i=0; i<1000000; i++)
483 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) 483 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
484 break; 484 break;
485 485
486 do_gettimeofday(&start_tv); 486 do_gettimeofday(&start_tv);
487 487
488 for(i=0; i<1000000; i++) 488 for(i=0; i<1000000; i++)
489 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0) 489 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
490 break; 490 break;
491 491
492 for(i=0; i<1000000; i++) 492 for(i=0; i<1000000; i++)
493 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) 493 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
494 break; 494 break;
495 495
496 do_gettimeofday(&stop_tv); 496 do_gettimeofday(&stop_tv);
497 497
498 local_irq_enable(); 498 local_irq_enable();
499 499
500 total_secs = stop_tv.tv_sec - start_tv.tv_sec; 500 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
501 if (total_secs > 10) 501 if (total_secs > 10)
502 return -1; 502 return -1;
503 total_usecs = stop_tv.tv_usec - start_tv.tv_usec; 503 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
504 total_usecs += total_secs * 1000000; 504 total_usecs += total_secs * 1000000;
505 if (total_usecs < 0) 505 if (total_usecs < 0)
506 total_usecs = -total_usecs; 506 total_usecs = -total_usecs;
507 hz = 1000000/total_usecs; 507 hz = 1000000/total_usecs;
508 508
509 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8; 509 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
510 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1); 510 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
511 vclk = (long long)hTotal * (long long)vTotal * hz; 511 vclk = (long long)hTotal * (long long)vTotal * hz;
512 512
513 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) { 513 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
514 case 0: 514 case 0:
515 default: 515 default:
516 num = 1; 516 num = 1;
517 denom = 1; 517 denom = 1;
518 break; 518 break;
519 case 1: 519 case 1:
520 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff); 520 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
521 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); 521 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
522 num = 2*n; 522 num = 2*n;
523 denom = 2*m; 523 denom = 2*m;
524 break; 524 break;
525 case 2: 525 case 2:
526 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff); 526 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
527 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); 527 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
528 num = 2*n; 528 num = 2*n;
529 denom = 2*m; 529 denom = 2*m;
530 break; 530 break;
531 } 531 }
532 532
533 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3; 533 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
534 radeon_pll_errata_after_index(rinfo); 534 radeon_pll_errata_after_index(rinfo);
535 535
536 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff); 536 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
537 m = (INPLL(PPLL_REF_DIV) & 0x3ff); 537 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
538 538
539 num *= n; 539 num *= n;
540 denom *= m; 540 denom *= m;
541 541
542 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { 542 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
543 case 1: 543 case 1:
544 denom *= 2; 544 denom *= 2;
545 break; 545 break;
546 case 2: 546 case 2:
547 denom *= 4; 547 denom *= 4;
548 break; 548 break;
549 case 3: 549 case 3:
550 denom *= 8; 550 denom *= 8;
551 break; 551 break;
552 case 4: 552 case 4:
553 denom *= 3; 553 denom *= 3;
554 break; 554 break;
555 case 6: 555 case 6:
556 denom *= 6; 556 denom *= 6;
557 break; 557 break;
558 case 7: 558 case 7:
559 denom *= 12; 559 denom *= 12;
560 break; 560 break;
561 } 561 }
562 562
563 vclk *= denom; 563 vclk *= denom;
564 do_div(vclk, 1000 * num); 564 do_div(vclk, 1000 * num);
565 xtal = vclk; 565 xtal = vclk;
566 566
567 if ((xtal > 26900) && (xtal < 27100)) 567 if ((xtal > 26900) && (xtal < 27100))
568 xtal = 2700; 568 xtal = 2700;
569 else if ((xtal > 14200) && (xtal < 14400)) 569 else if ((xtal > 14200) && (xtal < 14400))
570 xtal = 1432; 570 xtal = 1432;
571 else if ((xtal > 29400) && (xtal < 29600)) 571 else if ((xtal > 29400) && (xtal < 29600))
572 xtal = 2950; 572 xtal = 2950;
573 else { 573 else {
574 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal); 574 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
575 return -1; 575 return -1;
576 } 576 }
577 577
578 tmp = INPLL(M_SPLL_REF_FB_DIV); 578 tmp = INPLL(M_SPLL_REF_FB_DIV);
579 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; 579 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
580 580
581 Ns = (tmp & 0xff0000) >> 16; 581 Ns = (tmp & 0xff0000) >> 16;
582 Nm = (tmp & 0xff00) >> 8; 582 Nm = (tmp & 0xff00) >> 8;
583 M = (tmp & 0xff); 583 M = (tmp & 0xff);
584 sclk = round_div((2 * Ns * xtal), (2 * M)); 584 sclk = round_div((2 * Ns * xtal), (2 * M));
585 mclk = round_div((2 * Nm * xtal), (2 * M)); 585 mclk = round_div((2 * Nm * xtal), (2 * M));
586 586
587 /* we're done, hopefully these are sane values */ 587 /* we're done, hopefully these are sane values */
588 rinfo->pll.ref_clk = xtal; 588 rinfo->pll.ref_clk = xtal;
589 rinfo->pll.ref_div = ref_div; 589 rinfo->pll.ref_div = ref_div;
590 rinfo->pll.sclk = sclk; 590 rinfo->pll.sclk = sclk;
591 rinfo->pll.mclk = mclk; 591 rinfo->pll.mclk = mclk;
592 592
593 return 0; 593 return 0;
594 } 594 }
595 595
596 /* 596 /*
597 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...) 597 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
598 */ 598 */
599 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo) 599 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
600 { 600 {
601 /* 601 /*
602 * In the case nothing works, these are defaults; they are mostly 602 * In the case nothing works, these are defaults; they are mostly
603 * incomplete, however. It does provide ppll_max and _min values 603 * incomplete, however. It does provide ppll_max and _min values
604 * even for most other methods, however. 604 * even for most other methods, however.
605 */ 605 */
606 switch (rinfo->chipset) { 606 switch (rinfo->chipset) {
607 case PCI_DEVICE_ID_ATI_RADEON_QW: 607 case PCI_DEVICE_ID_ATI_RADEON_QW:
608 case PCI_DEVICE_ID_ATI_RADEON_QX: 608 case PCI_DEVICE_ID_ATI_RADEON_QX:
609 rinfo->pll.ppll_max = 35000; 609 rinfo->pll.ppll_max = 35000;
610 rinfo->pll.ppll_min = 12000; 610 rinfo->pll.ppll_min = 12000;
611 rinfo->pll.mclk = 23000; 611 rinfo->pll.mclk = 23000;
612 rinfo->pll.sclk = 23000; 612 rinfo->pll.sclk = 23000;
613 rinfo->pll.ref_clk = 2700; 613 rinfo->pll.ref_clk = 2700;
614 break; 614 break;
615 case PCI_DEVICE_ID_ATI_RADEON_QL: 615 case PCI_DEVICE_ID_ATI_RADEON_QL:
616 case PCI_DEVICE_ID_ATI_RADEON_QN: 616 case PCI_DEVICE_ID_ATI_RADEON_QN:
617 case PCI_DEVICE_ID_ATI_RADEON_QO: 617 case PCI_DEVICE_ID_ATI_RADEON_QO:
618 case PCI_DEVICE_ID_ATI_RADEON_Ql: 618 case PCI_DEVICE_ID_ATI_RADEON_Ql:
619 case PCI_DEVICE_ID_ATI_RADEON_BB: 619 case PCI_DEVICE_ID_ATI_RADEON_BB:
620 rinfo->pll.ppll_max = 35000; 620 rinfo->pll.ppll_max = 35000;
621 rinfo->pll.ppll_min = 12000; 621 rinfo->pll.ppll_min = 12000;
622 rinfo->pll.mclk = 27500; 622 rinfo->pll.mclk = 27500;
623 rinfo->pll.sclk = 27500; 623 rinfo->pll.sclk = 27500;
624 rinfo->pll.ref_clk = 2700; 624 rinfo->pll.ref_clk = 2700;
625 break; 625 break;
626 case PCI_DEVICE_ID_ATI_RADEON_Id: 626 case PCI_DEVICE_ID_ATI_RADEON_Id:
627 case PCI_DEVICE_ID_ATI_RADEON_Ie: 627 case PCI_DEVICE_ID_ATI_RADEON_Ie:
628 case PCI_DEVICE_ID_ATI_RADEON_If: 628 case PCI_DEVICE_ID_ATI_RADEON_If:
629 case PCI_DEVICE_ID_ATI_RADEON_Ig: 629 case PCI_DEVICE_ID_ATI_RADEON_Ig:
630 rinfo->pll.ppll_max = 35000; 630 rinfo->pll.ppll_max = 35000;
631 rinfo->pll.ppll_min = 12000; 631 rinfo->pll.ppll_min = 12000;
632 rinfo->pll.mclk = 25000; 632 rinfo->pll.mclk = 25000;
633 rinfo->pll.sclk = 25000; 633 rinfo->pll.sclk = 25000;
634 rinfo->pll.ref_clk = 2700; 634 rinfo->pll.ref_clk = 2700;
635 break; 635 break;
636 case PCI_DEVICE_ID_ATI_RADEON_ND: 636 case PCI_DEVICE_ID_ATI_RADEON_ND:
637 case PCI_DEVICE_ID_ATI_RADEON_NE: 637 case PCI_DEVICE_ID_ATI_RADEON_NE:
638 case PCI_DEVICE_ID_ATI_RADEON_NF: 638 case PCI_DEVICE_ID_ATI_RADEON_NF:
639 case PCI_DEVICE_ID_ATI_RADEON_NG: 639 case PCI_DEVICE_ID_ATI_RADEON_NG:
640 rinfo->pll.ppll_max = 40000; 640 rinfo->pll.ppll_max = 40000;
641 rinfo->pll.ppll_min = 20000; 641 rinfo->pll.ppll_min = 20000;
642 rinfo->pll.mclk = 27000; 642 rinfo->pll.mclk = 27000;
643 rinfo->pll.sclk = 27000; 643 rinfo->pll.sclk = 27000;
644 rinfo->pll.ref_clk = 2700; 644 rinfo->pll.ref_clk = 2700;
645 break; 645 break;
646 case PCI_DEVICE_ID_ATI_RADEON_QD: 646 case PCI_DEVICE_ID_ATI_RADEON_QD:
647 case PCI_DEVICE_ID_ATI_RADEON_QE: 647 case PCI_DEVICE_ID_ATI_RADEON_QE:
648 case PCI_DEVICE_ID_ATI_RADEON_QF: 648 case PCI_DEVICE_ID_ATI_RADEON_QF:
649 case PCI_DEVICE_ID_ATI_RADEON_QG: 649 case PCI_DEVICE_ID_ATI_RADEON_QG:
650 default: 650 default:
651 rinfo->pll.ppll_max = 35000; 651 rinfo->pll.ppll_max = 35000;
652 rinfo->pll.ppll_min = 12000; 652 rinfo->pll.ppll_min = 12000;
653 rinfo->pll.mclk = 16600; 653 rinfo->pll.mclk = 16600;
654 rinfo->pll.sclk = 16600; 654 rinfo->pll.sclk = 16600;
655 rinfo->pll.ref_clk = 2700; 655 rinfo->pll.ref_clk = 2700;
656 break; 656 break;
657 } 657 }
658 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; 658 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
659 659
660 660
661 #ifdef CONFIG_PPC_OF 661 #ifdef CONFIG_PPC_OF
662 /* 662 /*
663 * Retrieve PLL infos from Open Firmware first 663 * Retrieve PLL infos from Open Firmware first
664 */ 664 */
665 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) { 665 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
666 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n"); 666 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
667 goto found; 667 goto found;
668 } 668 }
669 #endif /* CONFIG_PPC_OF */ 669 #endif /* CONFIG_PPC_OF */
670 670
671 /* 671 /*
672 * Check out if we have an X86 which gave us some PLL informations 672 * Check out if we have an X86 which gave us some PLL informations
673 * and if yes, retrieve them 673 * and if yes, retrieve them
674 */ 674 */
675 if (!force_measure_pll && rinfo->bios_seg) { 675 if (!force_measure_pll && rinfo->bios_seg) {
676 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); 676 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
677 677
678 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); 678 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
679 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a); 679 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
680 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); 680 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
681 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); 681 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
682 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); 682 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
683 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); 683 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
684 684
685 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n"); 685 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
686 goto found; 686 goto found;
687 } 687 }
688 688
689 /* 689 /*
690 * We didn't get PLL parameters from either OF or BIOS, we try to 690 * We didn't get PLL parameters from either OF or BIOS, we try to
691 * probe them 691 * probe them
692 */ 692 */
693 if (radeon_probe_pll_params(rinfo) == 0) { 693 if (radeon_probe_pll_params(rinfo) == 0) {
694 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n"); 694 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
695 goto found; 695 goto found;
696 } 696 }
697 697
698 /* 698 /*
699 * Fall back to already-set defaults... 699 * Fall back to already-set defaults...
700 */ 700 */
701 printk(KERN_INFO "radeonfb: Used default PLL infos\n"); 701 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
702 702
703 found: 703 found:
704 /* 704 /*
705 * Some methods fail to retrieve SCLK and MCLK values, we apply default 705 * Some methods fail to retrieve SCLK and MCLK values, we apply default
706 * settings in this case (200Mhz). If that really happne often, we could 706 * settings in this case (200Mhz). If that really happne often, we could
707 * fetch from registers instead... 707 * fetch from registers instead...
708 */ 708 */
709 if (rinfo->pll.mclk == 0) 709 if (rinfo->pll.mclk == 0)
710 rinfo->pll.mclk = 20000; 710 rinfo->pll.mclk = 20000;
711 if (rinfo->pll.sclk == 0) 711 if (rinfo->pll.sclk == 0)
712 rinfo->pll.sclk = 20000; 712 rinfo->pll.sclk = 20000;
713 713
714 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n", 714 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
715 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100, 715 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
716 rinfo->pll.ref_div, 716 rinfo->pll.ref_div,
717 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100, 717 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
718 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100); 718 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
719 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max); 719 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
720 } 720 }
721 721
722 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info) 722 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
723 { 723 {
724 struct radeonfb_info *rinfo = info->par; 724 struct radeonfb_info *rinfo = info->par;
725 struct fb_var_screeninfo v; 725 struct fb_var_screeninfo v;
726 int nom, den; 726 int nom, den;
727 unsigned int pitch; 727 unsigned int pitch;
728 728
729 if (radeon_match_mode(rinfo, &v, var)) 729 if (radeon_match_mode(rinfo, &v, var))
730 return -EINVAL; 730 return -EINVAL;
731 731
732 switch (v.bits_per_pixel) { 732 switch (v.bits_per_pixel) {
733 case 0 ... 8: 733 case 0 ... 8:
734 v.bits_per_pixel = 8; 734 v.bits_per_pixel = 8;
735 break; 735 break;
736 case 9 ... 16: 736 case 9 ... 16:
737 v.bits_per_pixel = 16; 737 v.bits_per_pixel = 16;
738 break; 738 break;
739 case 17 ... 24: 739 case 17 ... 24:
740 #if 0 /* Doesn't seem to work */ 740 #if 0 /* Doesn't seem to work */
741 v.bits_per_pixel = 24; 741 v.bits_per_pixel = 24;
742 break; 742 break;
743 #endif 743 #endif
744 return -EINVAL; 744 return -EINVAL;
745 case 25 ... 32: 745 case 25 ... 32:
746 v.bits_per_pixel = 32; 746 v.bits_per_pixel = 32;
747 break; 747 break;
748 default: 748 default:
749 return -EINVAL; 749 return -EINVAL;
750 } 750 }
751 751
752 switch (var_to_depth(&v)) { 752 switch (var_to_depth(&v)) {
753 case 8: 753 case 8:
754 nom = den = 1; 754 nom = den = 1;
755 v.red.offset = v.green.offset = v.blue.offset = 0; 755 v.red.offset = v.green.offset = v.blue.offset = 0;
756 v.red.length = v.green.length = v.blue.length = 8; 756 v.red.length = v.green.length = v.blue.length = 8;
757 v.transp.offset = v.transp.length = 0; 757 v.transp.offset = v.transp.length = 0;
758 break; 758 break;
759 case 15: 759 case 15:
760 nom = 2; 760 nom = 2;
761 den = 1; 761 den = 1;
762 v.red.offset = 10; 762 v.red.offset = 10;
763 v.green.offset = 5; 763 v.green.offset = 5;
764 v.blue.offset = 0; 764 v.blue.offset = 0;
765 v.red.length = v.green.length = v.blue.length = 5; 765 v.red.length = v.green.length = v.blue.length = 5;
766 v.transp.offset = v.transp.length = 0; 766 v.transp.offset = v.transp.length = 0;
767 break; 767 break;
768 case 16: 768 case 16:
769 nom = 2; 769 nom = 2;
770 den = 1; 770 den = 1;
771 v.red.offset = 11; 771 v.red.offset = 11;
772 v.green.offset = 5; 772 v.green.offset = 5;
773 v.blue.offset = 0; 773 v.blue.offset = 0;
774 v.red.length = 5; 774 v.red.length = 5;
775 v.green.length = 6; 775 v.green.length = 6;
776 v.blue.length = 5; 776 v.blue.length = 5;
777 v.transp.offset = v.transp.length = 0; 777 v.transp.offset = v.transp.length = 0;
778 break; 778 break;
779 case 24: 779 case 24:
780 nom = 4; 780 nom = 4;
781 den = 1; 781 den = 1;
782 v.red.offset = 16; 782 v.red.offset = 16;
783 v.green.offset = 8; 783 v.green.offset = 8;
784 v.blue.offset = 0; 784 v.blue.offset = 0;
785 v.red.length = v.blue.length = v.green.length = 8; 785 v.red.length = v.blue.length = v.green.length = 8;
786 v.transp.offset = v.transp.length = 0; 786 v.transp.offset = v.transp.length = 0;
787 break; 787 break;
788 case 32: 788 case 32:
789 nom = 4; 789 nom = 4;
790 den = 1; 790 den = 1;
791 v.red.offset = 16; 791 v.red.offset = 16;
792 v.green.offset = 8; 792 v.green.offset = 8;
793 v.blue.offset = 0; 793 v.blue.offset = 0;
794 v.red.length = v.blue.length = v.green.length = 8; 794 v.red.length = v.blue.length = v.green.length = 8;
795 v.transp.offset = 24; 795 v.transp.offset = 24;
796 v.transp.length = 8; 796 v.transp.length = 8;
797 break; 797 break;
798 default: 798 default:
799 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n", 799 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
800 var->xres, var->yres, var->bits_per_pixel); 800 var->xres, var->yres, var->bits_per_pixel);
801 return -EINVAL; 801 return -EINVAL;
802 } 802 }
803 803
804 if (v.yres_virtual < v.yres) 804 if (v.yres_virtual < v.yres)
805 v.yres_virtual = v.yres; 805 v.yres_virtual = v.yres;
806 if (v.xres_virtual < v.xres) 806 if (v.xres_virtual < v.xres)
807 v.xres_virtual = v.xres; 807 v.xres_virtual = v.xres;
808 808
809 809
810 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree 810 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
811 * with some panels, though I don't quite like this solution 811 * with some panels, though I don't quite like this solution
812 */ 812 */
813 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) { 813 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
814 v.xres_virtual = v.xres_virtual & ~7ul; 814 v.xres_virtual = v.xres_virtual & ~7ul;
815 } else { 815 } else {
816 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f) 816 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
817 & ~(0x3f)) >> 6; 817 & ~(0x3f)) >> 6;
818 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8); 818 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
819 } 819 }
820 820
821 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram) 821 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
822 return -EINVAL; 822 return -EINVAL;
823 823
824 if (v.xres_virtual < v.xres) 824 if (v.xres_virtual < v.xres)
825 v.xres = v.xres_virtual; 825 v.xres = v.xres_virtual;
826 826
827 if (v.xoffset < 0) 827 if (v.xoffset < 0)
828 v.xoffset = 0; 828 v.xoffset = 0;
829 if (v.yoffset < 0) 829 if (v.yoffset < 0)
830 v.yoffset = 0; 830 v.yoffset = 0;
831 831
832 if (v.xoffset > v.xres_virtual - v.xres) 832 if (v.xoffset > v.xres_virtual - v.xres)
833 v.xoffset = v.xres_virtual - v.xres - 1; 833 v.xoffset = v.xres_virtual - v.xres - 1;
834 834
835 if (v.yoffset > v.yres_virtual - v.yres) 835 if (v.yoffset > v.yres_virtual - v.yres)
836 v.yoffset = v.yres_virtual - v.yres - 1; 836 v.yoffset = v.yres_virtual - v.yres - 1;
837 837
838 v.red.msb_right = v.green.msb_right = v.blue.msb_right = 838 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
839 v.transp.offset = v.transp.length = 839 v.transp.offset = v.transp.length =
840 v.transp.msb_right = 0; 840 v.transp.msb_right = 0;
841 841
842 memcpy(var, &v, sizeof(v)); 842 memcpy(var, &v, sizeof(v));
843 843
844 return 0; 844 return 0;
845 } 845 }
846 846
847 847
848 static int radeonfb_pan_display (struct fb_var_screeninfo *var, 848 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
849 struct fb_info *info) 849 struct fb_info *info)
850 { 850 {
851 struct radeonfb_info *rinfo = info->par; 851 struct radeonfb_info *rinfo = info->par;
852 852
853 if ((var->xoffset + var->xres > var->xres_virtual) 853 if ((var->xoffset + var->xres > var->xres_virtual)
854 || (var->yoffset + var->yres > var->yres_virtual)) 854 || (var->yoffset + var->yres > var->yres_virtual))
855 return -EINVAL; 855 return -EINVAL;
856 856
857 if (rinfo->asleep) 857 if (rinfo->asleep)
858 return 0; 858 return 0;
859 859
860 radeon_fifo_wait(2); 860 radeon_fifo_wait(2);
861 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset) 861 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
862 * var->bits_per_pixel / 8) & ~7); 862 * var->bits_per_pixel / 8) & ~7);
863 return 0; 863 return 0;
864 } 864 }
865 865
866 866
867 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd, 867 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
868 unsigned long arg) 868 unsigned long arg)
869 { 869 {
870 struct radeonfb_info *rinfo = info->par; 870 struct radeonfb_info *rinfo = info->par;
871 unsigned int tmp; 871 unsigned int tmp;
872 u32 value = 0; 872 u32 value = 0;
873 int rc; 873 int rc;
874 874
875 switch (cmd) { 875 switch (cmd) {
876 /* 876 /*
877 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's 877 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
878 * and do something better using 2nd CRTC instead of just hackish 878 * and do something better using 2nd CRTC instead of just hackish
879 * routing to second output 879 * routing to second output
880 */ 880 */
881 case FBIO_RADEON_SET_MIRROR: 881 case FBIO_RADEON_SET_MIRROR:
882 if (!rinfo->is_mobility) 882 if (!rinfo->is_mobility)
883 return -EINVAL; 883 return -EINVAL;
884 884
885 rc = get_user(value, (__u32 __user *)arg); 885 rc = get_user(value, (__u32 __user *)arg);
886 886
887 if (rc) 887 if (rc)
888 return rc; 888 return rc;
889 889
890 radeon_fifo_wait(2); 890 radeon_fifo_wait(2);
891 if (value & 0x01) { 891 if (value & 0x01) {
892 tmp = INREG(LVDS_GEN_CNTL); 892 tmp = INREG(LVDS_GEN_CNTL);
893 893
894 tmp |= (LVDS_ON | LVDS_BLON); 894 tmp |= (LVDS_ON | LVDS_BLON);
895 } else { 895 } else {
896 tmp = INREG(LVDS_GEN_CNTL); 896 tmp = INREG(LVDS_GEN_CNTL);
897 897
898 tmp &= ~(LVDS_ON | LVDS_BLON); 898 tmp &= ~(LVDS_ON | LVDS_BLON);
899 } 899 }
900 900
901 OUTREG(LVDS_GEN_CNTL, tmp); 901 OUTREG(LVDS_GEN_CNTL, tmp);
902 902
903 if (value & 0x02) { 903 if (value & 0x02) {
904 tmp = INREG(CRTC_EXT_CNTL); 904 tmp = INREG(CRTC_EXT_CNTL);
905 tmp |= CRTC_CRT_ON; 905 tmp |= CRTC_CRT_ON;
906 906
907 mirror = 1; 907 mirror = 1;
908 } else { 908 } else {
909 tmp = INREG(CRTC_EXT_CNTL); 909 tmp = INREG(CRTC_EXT_CNTL);
910 tmp &= ~CRTC_CRT_ON; 910 tmp &= ~CRTC_CRT_ON;
911 911
912 mirror = 0; 912 mirror = 0;
913 } 913 }
914 914
915 OUTREG(CRTC_EXT_CNTL, tmp); 915 OUTREG(CRTC_EXT_CNTL, tmp);
916 916
917 return 0; 917 return 0;
918 case FBIO_RADEON_GET_MIRROR: 918 case FBIO_RADEON_GET_MIRROR:
919 if (!rinfo->is_mobility) 919 if (!rinfo->is_mobility)
920 return -EINVAL; 920 return -EINVAL;
921 921
922 tmp = INREG(LVDS_GEN_CNTL); 922 tmp = INREG(LVDS_GEN_CNTL);
923 if ((LVDS_ON | LVDS_BLON) & tmp) 923 if ((LVDS_ON | LVDS_BLON) & tmp)
924 value |= 0x01; 924 value |= 0x01;
925 925
926 tmp = INREG(CRTC_EXT_CNTL); 926 tmp = INREG(CRTC_EXT_CNTL);
927 if (CRTC_CRT_ON & tmp) 927 if (CRTC_CRT_ON & tmp)
928 value |= 0x02; 928 value |= 0x02;
929 929
930 return put_user(value, (__u32 __user *)arg); 930 return put_user(value, (__u32 __user *)arg);
931 default: 931 default:
932 return -EINVAL; 932 return -EINVAL;
933 } 933 }
934 934
935 return -EINVAL; 935 return -EINVAL;
936 } 936 }
937 937
938 938
939 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch) 939 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
940 { 940 {
941 u32 val; 941 u32 val;
942 u32 tmp_pix_clks; 942 u32 tmp_pix_clks;
943 int unblank = 0; 943 int unblank = 0;
944 944
945 if (rinfo->lock_blank) 945 if (rinfo->lock_blank)
946 return 0; 946 return 0;
947 947
948 radeon_engine_idle(); 948 radeon_engine_idle();
949 949
950 val = INREG(CRTC_EXT_CNTL); 950 val = INREG(CRTC_EXT_CNTL);
951 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | 951 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
952 CRTC_VSYNC_DIS); 952 CRTC_VSYNC_DIS);
953 switch (blank) { 953 switch (blank) {
954 case FB_BLANK_VSYNC_SUSPEND: 954 case FB_BLANK_VSYNC_SUSPEND:
955 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS); 955 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
956 break; 956 break;
957 case FB_BLANK_HSYNC_SUSPEND: 957 case FB_BLANK_HSYNC_SUSPEND:
958 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS); 958 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
959 break; 959 break;
960 case FB_BLANK_POWERDOWN: 960 case FB_BLANK_POWERDOWN:
961 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | 961 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
962 CRTC_HSYNC_DIS); 962 CRTC_HSYNC_DIS);
963 break; 963 break;
964 case FB_BLANK_NORMAL: 964 case FB_BLANK_NORMAL:
965 val |= CRTC_DISPLAY_DIS; 965 val |= CRTC_DISPLAY_DIS;
966 break; 966 break;
967 case FB_BLANK_UNBLANK: 967 case FB_BLANK_UNBLANK:
968 default: 968 default:
969 unblank = 1; 969 unblank = 1;
970 } 970 }
971 OUTREG(CRTC_EXT_CNTL, val); 971 OUTREG(CRTC_EXT_CNTL, val);
972 972
973 973
974 switch (rinfo->mon1_type) { 974 switch (rinfo->mon1_type) {
975 case MT_DFP: 975 case MT_DFP:
976 if (unblank) 976 if (unblank)
977 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN), 977 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
978 ~(FP_FPON | FP_TMDS_EN)); 978 ~(FP_FPON | FP_TMDS_EN));
979 else { 979 else {
980 if (mode_switch || blank == FB_BLANK_NORMAL) 980 if (mode_switch || blank == FB_BLANK_NORMAL)
981 break; 981 break;
982 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN)); 982 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
983 } 983 }
984 break; 984 break;
985 case MT_LCD: 985 case MT_LCD:
986 del_timer_sync(&rinfo->lvds_timer); 986 del_timer_sync(&rinfo->lvds_timer);
987 val = INREG(LVDS_GEN_CNTL); 987 val = INREG(LVDS_GEN_CNTL);
988 if (unblank) { 988 if (unblank) {
989 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON 989 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
990 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl 990 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
991 & (LVDS_DIGON | LVDS_BL_MOD_EN)); 991 & (LVDS_DIGON | LVDS_BL_MOD_EN));
992 if ((val ^ target_val) == LVDS_DISPLAY_DIS) 992 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
993 OUTREG(LVDS_GEN_CNTL, target_val); 993 OUTREG(LVDS_GEN_CNTL, target_val);
994 else if ((val ^ target_val) != 0) { 994 else if ((val ^ target_val) != 0) {
995 OUTREG(LVDS_GEN_CNTL, target_val 995 OUTREG(LVDS_GEN_CNTL, target_val
996 & ~(LVDS_ON | LVDS_BL_MOD_EN)); 996 & ~(LVDS_ON | LVDS_BL_MOD_EN));
997 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; 997 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
998 rinfo->init_state.lvds_gen_cntl |= 998 rinfo->init_state.lvds_gen_cntl |=
999 target_val & LVDS_STATE_MASK; 999 target_val & LVDS_STATE_MASK;
1000 if (mode_switch) { 1000 if (mode_switch) {
1001 radeon_msleep(rinfo->panel_info.pwr_delay); 1001 radeon_msleep(rinfo->panel_info.pwr_delay);
1002 OUTREG(LVDS_GEN_CNTL, target_val); 1002 OUTREG(LVDS_GEN_CNTL, target_val);
1003 } 1003 }
1004 else { 1004 else {
1005 rinfo->pending_lvds_gen_cntl = target_val; 1005 rinfo->pending_lvds_gen_cntl = target_val;
1006 mod_timer(&rinfo->lvds_timer, 1006 mod_timer(&rinfo->lvds_timer,
1007 jiffies + 1007 jiffies +
1008 msecs_to_jiffies(rinfo->panel_info.pwr_delay)); 1008 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1009 } 1009 }
1010 } 1010 }
1011 } else { 1011 } else {
1012 val |= LVDS_DISPLAY_DIS; 1012 val |= LVDS_DISPLAY_DIS;
1013 OUTREG(LVDS_GEN_CNTL, val); 1013 OUTREG(LVDS_GEN_CNTL, val);
1014 1014
1015 /* We don't do a full switch-off on a simple mode switch */ 1015 /* We don't do a full switch-off on a simple mode switch */
1016 if (mode_switch || blank == FB_BLANK_NORMAL) 1016 if (mode_switch || blank == FB_BLANK_NORMAL)
1017 break; 1017 break;
1018 1018
1019 /* Asic bug, when turning off LVDS_ON, we have to make sure 1019 /* Asic bug, when turning off LVDS_ON, we have to make sure
1020 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off 1020 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1021 */ 1021 */
1022 tmp_pix_clks = INPLL(PIXCLKS_CNTL); 1022 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1023 if (rinfo->is_mobility || rinfo->is_IGP) 1023 if (rinfo->is_mobility || rinfo->is_IGP)
1024 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb); 1024 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1025 val &= ~(LVDS_BL_MOD_EN); 1025 val &= ~(LVDS_BL_MOD_EN);
1026 OUTREG(LVDS_GEN_CNTL, val); 1026 OUTREG(LVDS_GEN_CNTL, val);
1027 udelay(100); 1027 udelay(100);
1028 val &= ~(LVDS_ON | LVDS_EN); 1028 val &= ~(LVDS_ON | LVDS_EN);
1029 OUTREG(LVDS_GEN_CNTL, val); 1029 OUTREG(LVDS_GEN_CNTL, val);
1030 val &= ~LVDS_DIGON; 1030 val &= ~LVDS_DIGON;
1031 rinfo->pending_lvds_gen_cntl = val; 1031 rinfo->pending_lvds_gen_cntl = val;
1032 mod_timer(&rinfo->lvds_timer, 1032 mod_timer(&rinfo->lvds_timer,
1033 jiffies + 1033 jiffies +
1034 msecs_to_jiffies(rinfo->panel_info.pwr_delay)); 1034 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1035 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; 1035 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1036 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK; 1036 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1037 if (rinfo->is_mobility || rinfo->is_IGP) 1037 if (rinfo->is_mobility || rinfo->is_IGP)
1038 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks); 1038 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1039 } 1039 }
1040 break; 1040 break;
1041 case MT_CRT: 1041 case MT_CRT:
1042 // todo: powerdown DAC 1042 // todo: powerdown DAC
1043 default: 1043 default:
1044 break; 1044 break;
1045 } 1045 }
1046 1046
1047 /* let fbcon do a soft blank for us */ 1047 /* let fbcon do a soft blank for us */
1048 return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0; 1048 return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0;
1049 } 1049 }
1050 1050
1051 static int radeonfb_blank (int blank, struct fb_info *info) 1051 static int radeonfb_blank (int blank, struct fb_info *info)
1052 { 1052 {
1053 struct radeonfb_info *rinfo = info->par; 1053 struct radeonfb_info *rinfo = info->par;
1054 1054
1055 if (rinfo->asleep) 1055 if (rinfo->asleep)
1056 return 0; 1056 return 0;
1057 1057
1058 return radeon_screen_blank(rinfo, blank, 0); 1058 return radeon_screen_blank(rinfo, blank, 0);
1059 } 1059 }
1060 1060
1061 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green, 1061 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1062 unsigned blue, unsigned transp, 1062 unsigned blue, unsigned transp,
1063 struct radeonfb_info *rinfo) 1063 struct radeonfb_info *rinfo)
1064 { 1064 {
1065 u32 pindex; 1065 u32 pindex;
1066 unsigned int i; 1066 unsigned int i;
1067 1067
1068 1068
1069 if (regno > 255) 1069 if (regno > 255)
1070 return 1; 1070 return -EINVAL;
1071 1071
1072 red >>= 8; 1072 red >>= 8;
1073 green >>= 8; 1073 green >>= 8;
1074 blue >>= 8; 1074 blue >>= 8;
1075 rinfo->palette[regno].red = red; 1075 rinfo->palette[regno].red = red;
1076 rinfo->palette[regno].green = green; 1076 rinfo->palette[regno].green = green;
1077 rinfo->palette[regno].blue = blue; 1077 rinfo->palette[regno].blue = blue;
1078 1078
1079 /* default */ 1079 /* default */
1080 pindex = regno; 1080 pindex = regno;
1081 1081
1082 if (!rinfo->asleep) { 1082 if (!rinfo->asleep) {
1083 radeon_fifo_wait(9); 1083 radeon_fifo_wait(9);
1084 1084
1085 if (rinfo->bpp == 16) { 1085 if (rinfo->bpp == 16) {
1086 pindex = regno * 8; 1086 pindex = regno * 8;
1087 1087
1088 if (rinfo->depth == 16 && regno > 63) 1088 if (rinfo->depth == 16 && regno > 63)
1089 return 1; 1089 return -EINVAL;
1090 if (rinfo->depth == 15 && regno > 31) 1090 if (rinfo->depth == 15 && regno > 31)
1091 return 1; 1091 return -EINVAL;
1092 1092
1093 /* For 565, the green component is mixed one order 1093 /* For 565, the green component is mixed one order
1094 * below 1094 * below
1095 */ 1095 */
1096 if (rinfo->depth == 16) { 1096 if (rinfo->depth == 16) {
1097 OUTREG(PALETTE_INDEX, pindex>>1); 1097 OUTREG(PALETTE_INDEX, pindex>>1);
1098 OUTREG(PALETTE_DATA, 1098 OUTREG(PALETTE_DATA,
1099 (rinfo->palette[regno>>1].red << 16) | 1099 (rinfo->palette[regno>>1].red << 16) |
1100 (green << 8) | 1100 (green << 8) |
1101 (rinfo->palette[regno>>1].blue)); 1101 (rinfo->palette[regno>>1].blue));
1102 green = rinfo->palette[regno<<1].green; 1102 green = rinfo->palette[regno<<1].green;
1103 } 1103 }
1104 } 1104 }
1105 1105
1106 if (rinfo->depth != 16 || regno < 32) { 1106 if (rinfo->depth != 16 || regno < 32) {
1107 OUTREG(PALETTE_INDEX, pindex); 1107 OUTREG(PALETTE_INDEX, pindex);
1108 OUTREG(PALETTE_DATA, (red << 16) | 1108 OUTREG(PALETTE_DATA, (red << 16) |
1109 (green << 8) | blue); 1109 (green << 8) | blue);
1110 } 1110 }
1111 } 1111 }
1112 if (regno < 16) { 1112 if (regno < 16) {
1113 u32 *pal = rinfo->info->pseudo_palette; 1113 u32 *pal = rinfo->info->pseudo_palette;
1114 switch (rinfo->depth) { 1114 switch (rinfo->depth) {
1115 case 15: 1115 case 15:
1116 pal[regno] = (regno << 10) | (regno << 5) | regno; 1116 pal[regno] = (regno << 10) | (regno << 5) | regno;
1117 break; 1117 break;
1118 case 16: 1118 case 16:
1119 pal[regno] = (regno << 11) | (regno << 5) | regno; 1119 pal[regno] = (regno << 11) | (regno << 5) | regno;
1120 break; 1120 break;
1121 case 24: 1121 case 24:
1122 pal[regno] = (regno << 16) | (regno << 8) | regno; 1122 pal[regno] = (regno << 16) | (regno << 8) | regno;
1123 break; 1123 break;
1124 case 32: 1124 case 32:
1125 i = (regno << 8) | regno; 1125 i = (regno << 8) | regno;
1126 pal[regno] = (i << 16) | i; 1126 pal[regno] = (i << 16) | i;
1127 break; 1127 break;
1128 } 1128 }
1129 } 1129 }
1130 return 0; 1130 return 0;
1131 } 1131 }
1132 1132
1133 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green, 1133 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1134 unsigned blue, unsigned transp, 1134 unsigned blue, unsigned transp,
1135 struct fb_info *info) 1135 struct fb_info *info)
1136 { 1136 {
1137 struct radeonfb_info *rinfo = info->par; 1137 struct radeonfb_info *rinfo = info->par;
1138 u32 dac_cntl2, vclk_cntl = 0; 1138 u32 dac_cntl2, vclk_cntl = 0;
1139 int rc; 1139 int rc;
1140 1140
1141 if (!rinfo->asleep) { 1141 if (!rinfo->asleep) {
1142 if (rinfo->is_mobility) { 1142 if (rinfo->is_mobility) {
1143 vclk_cntl = INPLL(VCLK_ECP_CNTL); 1143 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1144 OUTPLL(VCLK_ECP_CNTL, 1144 OUTPLL(VCLK_ECP_CNTL,
1145 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb); 1145 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1146 } 1146 }
1147 1147
1148 /* Make sure we are on first palette */ 1148 /* Make sure we are on first palette */
1149 if (rinfo->has_CRTC2) { 1149 if (rinfo->has_CRTC2) {
1150 dac_cntl2 = INREG(DAC_CNTL2); 1150 dac_cntl2 = INREG(DAC_CNTL2);
1151 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL; 1151 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1152 OUTREG(DAC_CNTL2, dac_cntl2); 1152 OUTREG(DAC_CNTL2, dac_cntl2);
1153 } 1153 }
1154 } 1154 }
1155 1155
1156 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo); 1156 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1157 1157
1158 if (!rinfo->asleep && rinfo->is_mobility) 1158 if (!rinfo->asleep && rinfo->is_mobility)
1159 OUTPLL(VCLK_ECP_CNTL, vclk_cntl); 1159 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1160 1160
1161 return rc; 1161 return rc;
1162 } 1162 }
1163 1163
1164 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info) 1164 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1165 { 1165 {
1166 struct radeonfb_info *rinfo = info->par; 1166 struct radeonfb_info *rinfo = info->par;
1167 u16 *red, *green, *blue, *transp; 1167 u16 *red, *green, *blue, *transp;
1168 u32 dac_cntl2, vclk_cntl = 0; 1168 u32 dac_cntl2, vclk_cntl = 0;
1169 int i, start, rc = 0; 1169 int i, start, rc = 0;
1170 1170
1171 if (!rinfo->asleep) { 1171 if (!rinfo->asleep) {
1172 if (rinfo->is_mobility) { 1172 if (rinfo->is_mobility) {
1173 vclk_cntl = INPLL(VCLK_ECP_CNTL); 1173 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1174 OUTPLL(VCLK_ECP_CNTL, 1174 OUTPLL(VCLK_ECP_CNTL,
1175 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb); 1175 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1176 } 1176 }
1177 1177
1178 /* Make sure we are on first palette */ 1178 /* Make sure we are on first palette */
1179 if (rinfo->has_CRTC2) { 1179 if (rinfo->has_CRTC2) {
1180 dac_cntl2 = INREG(DAC_CNTL2); 1180 dac_cntl2 = INREG(DAC_CNTL2);
1181 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL; 1181 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1182 OUTREG(DAC_CNTL2, dac_cntl2); 1182 OUTREG(DAC_CNTL2, dac_cntl2);
1183 } 1183 }
1184 } 1184 }
1185 1185
1186 red = cmap->red; 1186 red = cmap->red;
1187 green = cmap->green; 1187 green = cmap->green;
1188 blue = cmap->blue; 1188 blue = cmap->blue;
1189 transp = cmap->transp; 1189 transp = cmap->transp;
1190 start = cmap->start; 1190 start = cmap->start;
1191 1191
1192 for (i = 0; i < cmap->len; i++) { 1192 for (i = 0; i < cmap->len; i++) {
1193 u_int hred, hgreen, hblue, htransp = 0xffff; 1193 u_int hred, hgreen, hblue, htransp = 0xffff;
1194 1194
1195 hred = *red++; 1195 hred = *red++;
1196 hgreen = *green++; 1196 hgreen = *green++;
1197 hblue = *blue++; 1197 hblue = *blue++;
1198 if (transp) 1198 if (transp)
1199 htransp = *transp++; 1199 htransp = *transp++;
1200 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp, 1200 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1201 rinfo); 1201 rinfo);
1202 if (rc) 1202 if (rc)
1203 break; 1203 break;
1204 } 1204 }
1205 1205
1206 if (!rinfo->asleep && rinfo->is_mobility) 1206 if (!rinfo->asleep && rinfo->is_mobility)
1207 OUTPLL(VCLK_ECP_CNTL, vclk_cntl); 1207 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1208 1208
1209 return rc; 1209 return rc;
1210 } 1210 }
1211 1211
1212 static void radeon_save_state (struct radeonfb_info *rinfo, 1212 static void radeon_save_state (struct radeonfb_info *rinfo,
1213 struct radeon_regs *save) 1213 struct radeon_regs *save)
1214 { 1214 {
1215 /* CRTC regs */ 1215 /* CRTC regs */
1216 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); 1216 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1217 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); 1217 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1218 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); 1218 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1219 save->dac_cntl = INREG(DAC_CNTL); 1219 save->dac_cntl = INREG(DAC_CNTL);
1220 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); 1220 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1221 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID); 1221 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1222 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP); 1222 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1223 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID); 1223 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1224 save->crtc_pitch = INREG(CRTC_PITCH); 1224 save->crtc_pitch = INREG(CRTC_PITCH);
1225 save->surface_cntl = INREG(SURFACE_CNTL); 1225 save->surface_cntl = INREG(SURFACE_CNTL);
1226 1226
1227 /* FP regs */ 1227 /* FP regs */
1228 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP); 1228 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1229 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP); 1229 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1230 save->fp_gen_cntl = INREG(FP_GEN_CNTL); 1230 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1231 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID); 1231 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1232 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH); 1232 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1233 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID); 1233 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1234 save->fp_vert_stretch = INREG(FP_VERT_STRETCH); 1234 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1235 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); 1235 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1236 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); 1236 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1237 save->tmds_crc = INREG(TMDS_CRC); 1237 save->tmds_crc = INREG(TMDS_CRC);
1238 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); 1238 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1239 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL); 1239 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1240 1240
1241 /* PLL regs */ 1241 /* PLL regs */
1242 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; 1242 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1243 radeon_pll_errata_after_index(rinfo); 1243 radeon_pll_errata_after_index(rinfo);
1244 save->ppll_div_3 = INPLL(PPLL_DIV_3); 1244 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1245 save->ppll_ref_div = INPLL(PPLL_REF_DIV); 1245 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1246 } 1246 }
1247 1247
1248 1248
1249 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) 1249 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1250 { 1250 {
1251 int i; 1251 int i;
1252 1252
1253 radeon_fifo_wait(20); 1253 radeon_fifo_wait(20);
1254 1254
1255 /* Workaround from XFree */ 1255 /* Workaround from XFree */
1256 if (rinfo->is_mobility) { 1256 if (rinfo->is_mobility) {
1257 /* A temporal workaround for the occational blanking on certain laptop 1257 /* A temporal workaround for the occational blanking on certain laptop
1258 * panels. This appears to related to the PLL divider registers 1258 * panels. This appears to related to the PLL divider registers
1259 * (fail to lock?). It occurs even when all dividers are the same 1259 * (fail to lock?). It occurs even when all dividers are the same
1260 * with their old settings. In this case we really don't need to 1260 * with their old settings. In this case we really don't need to
1261 * fiddle with PLL registers. By doing this we can avoid the blanking 1261 * fiddle with PLL registers. By doing this we can avoid the blanking
1262 * problem with some panels. 1262 * problem with some panels.
1263 */ 1263 */
1264 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && 1264 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1265 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & 1265 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1266 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { 1266 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1267 /* We still have to force a switch to selected PPLL div thanks to 1267 /* We still have to force a switch to selected PPLL div thanks to
1268 * an XFree86 driver bug which will switch it away in some cases 1268 * an XFree86 driver bug which will switch it away in some cases
1269 * even when using UseFDev */ 1269 * even when using UseFDev */
1270 OUTREGP(CLOCK_CNTL_INDEX, 1270 OUTREGP(CLOCK_CNTL_INDEX,
1271 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 1271 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1272 ~PPLL_DIV_SEL_MASK); 1272 ~PPLL_DIV_SEL_MASK);
1273 radeon_pll_errata_after_index(rinfo); 1273 radeon_pll_errata_after_index(rinfo);
1274 radeon_pll_errata_after_data(rinfo); 1274 radeon_pll_errata_after_data(rinfo);
1275 return; 1275 return;
1276 } 1276 }
1277 } 1277 }
1278 1278
1279 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ 1279 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1280 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); 1280 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1281 1281
1282 /* Reset PPLL & enable atomic update */ 1282 /* Reset PPLL & enable atomic update */
1283 OUTPLLP(PPLL_CNTL, 1283 OUTPLLP(PPLL_CNTL,
1284 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, 1284 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1285 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 1285 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1286 1286
1287 /* Switch to selected PPLL divider */ 1287 /* Switch to selected PPLL divider */
1288 OUTREGP(CLOCK_CNTL_INDEX, 1288 OUTREGP(CLOCK_CNTL_INDEX,
1289 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 1289 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1290 ~PPLL_DIV_SEL_MASK); 1290 ~PPLL_DIV_SEL_MASK);
1291 radeon_pll_errata_after_index(rinfo); 1291 radeon_pll_errata_after_index(rinfo);
1292 radeon_pll_errata_after_data(rinfo); 1292 radeon_pll_errata_after_data(rinfo);
1293 1293
1294 /* Set PPLL ref. div */ 1294 /* Set PPLL ref. div */
1295 if (rinfo->family == CHIP_FAMILY_R300 || 1295 if (rinfo->family == CHIP_FAMILY_R300 ||
1296 rinfo->family == CHIP_FAMILY_RS300 || 1296 rinfo->family == CHIP_FAMILY_RS300 ||
1297 rinfo->family == CHIP_FAMILY_R350 || 1297 rinfo->family == CHIP_FAMILY_R350 ||
1298 rinfo->family == CHIP_FAMILY_RV350) { 1298 rinfo->family == CHIP_FAMILY_RV350) {
1299 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 1299 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1300 /* When restoring console mode, use saved PPLL_REF_DIV 1300 /* When restoring console mode, use saved PPLL_REF_DIV
1301 * setting. 1301 * setting.
1302 */ 1302 */
1303 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); 1303 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1304 } else { 1304 } else {
1305 /* R300 uses ref_div_acc field as real ref divider */ 1305 /* R300 uses ref_div_acc field as real ref divider */
1306 OUTPLLP(PPLL_REF_DIV, 1306 OUTPLLP(PPLL_REF_DIV,
1307 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 1307 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1308 ~R300_PPLL_REF_DIV_ACC_MASK); 1308 ~R300_PPLL_REF_DIV_ACC_MASK);
1309 } 1309 }
1310 } else 1310 } else
1311 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); 1311 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1312 1312
1313 /* Set PPLL divider 3 & post divider*/ 1313 /* Set PPLL divider 3 & post divider*/
1314 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); 1314 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1315 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); 1315 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1316 1316
1317 /* Write update */ 1317 /* Write update */
1318 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) 1318 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1319 ; 1319 ;
1320 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); 1320 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1321 1321
1322 /* Wait read update complete */ 1322 /* Wait read update complete */
1323 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 1323 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1324 the cause yet, but this workaround will mask the problem for now. 1324 the cause yet, but this workaround will mask the problem for now.
1325 Other chips usually will pass at the very first test, so the 1325 Other chips usually will pass at the very first test, so the
1326 workaround shouldn't have any effect on them. */ 1326 workaround shouldn't have any effect on them. */
1327 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) 1327 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1328 ; 1328 ;
1329 1329
1330 OUTPLL(HTOTAL_CNTL, 0); 1330 OUTPLL(HTOTAL_CNTL, 0);
1331 1331
1332 /* Clear reset & atomic update */ 1332 /* Clear reset & atomic update */
1333 OUTPLLP(PPLL_CNTL, 0, 1333 OUTPLLP(PPLL_CNTL, 0,
1334 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 1334 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1335 1335
1336 /* We may want some locking ... oh well */ 1336 /* We may want some locking ... oh well */
1337 radeon_msleep(5); 1337 radeon_msleep(5);
1338 1338
1339 /* Switch back VCLK source to PPLL */ 1339 /* Switch back VCLK source to PPLL */
1340 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); 1340 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1341 } 1341 }
1342 1342
1343 /* 1343 /*
1344 * Timer function for delayed LVDS panel power up/down 1344 * Timer function for delayed LVDS panel power up/down
1345 */ 1345 */
1346 static void radeon_lvds_timer_func(unsigned long data) 1346 static void radeon_lvds_timer_func(unsigned long data)
1347 { 1347 {
1348 struct radeonfb_info *rinfo = (struct radeonfb_info *)data; 1348 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1349 1349
1350 radeon_engine_idle(); 1350 radeon_engine_idle();
1351 1351
1352 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); 1352 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1353 } 1353 }
1354 1354
1355 /* 1355 /*
1356 * Apply a video mode. This will apply the whole register set, including 1356 * Apply a video mode. This will apply the whole register set, including
1357 * the PLL registers, to the card 1357 * the PLL registers, to the card
1358 */ 1358 */
1359 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, 1359 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1360 int regs_only) 1360 int regs_only)
1361 { 1361 {
1362 int i; 1362 int i;
1363 int primary_mon = PRIMARY_MONITOR(rinfo); 1363 int primary_mon = PRIMARY_MONITOR(rinfo);
1364 1364
1365 if (nomodeset) 1365 if (nomodeset)
1366 return; 1366 return;
1367 1367
1368 if (!regs_only) 1368 if (!regs_only)
1369 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); 1369 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1370 1370
1371 radeon_fifo_wait(31); 1371 radeon_fifo_wait(31);
1372 for (i=0; i<10; i++) 1372 for (i=0; i<10; i++)
1373 OUTREG(common_regs[i].reg, common_regs[i].val); 1373 OUTREG(common_regs[i].reg, common_regs[i].val);
1374 1374
1375 /* Apply surface registers */ 1375 /* Apply surface registers */
1376 for (i=0; i<8; i++) { 1376 for (i=0; i<8; i++) {
1377 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]); 1377 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1378 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]); 1378 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1379 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]); 1379 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1380 } 1380 }
1381 1381
1382 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); 1382 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1383 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 1383 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1384 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 1384 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1385 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl); 1385 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1386 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); 1386 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1387 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); 1387 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1388 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); 1388 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1389 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); 1389 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1390 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); 1390 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1391 OUTREG(CRTC_OFFSET, 0); 1391 OUTREG(CRTC_OFFSET, 0);
1392 OUTREG(CRTC_OFFSET_CNTL, 0); 1392 OUTREG(CRTC_OFFSET_CNTL, 0);
1393 OUTREG(CRTC_PITCH, mode->crtc_pitch); 1393 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1394 OUTREG(SURFACE_CNTL, mode->surface_cntl); 1394 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1395 1395
1396 radeon_write_pll_regs(rinfo, mode); 1396 radeon_write_pll_regs(rinfo, mode);
1397 1397
1398 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1398 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1399 radeon_fifo_wait(10); 1399 radeon_fifo_wait(10);
1400 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); 1400 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1401 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); 1401 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1402 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); 1402 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1403 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid); 1403 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1404 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch); 1404 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1405 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); 1405 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1406 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); 1406 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1407 OUTREG(TMDS_CRC, mode->tmds_crc); 1407 OUTREG(TMDS_CRC, mode->tmds_crc);
1408 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); 1408 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1409 } 1409 }
1410 1410
1411 if (!regs_only) 1411 if (!regs_only)
1412 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); 1412 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1413 1413
1414 radeon_fifo_wait(2); 1414 radeon_fifo_wait(2);
1415 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); 1415 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1416 1416
1417 return; 1417 return;
1418 } 1418 }
1419 1419
1420 /* 1420 /*
1421 * Calculate the PLL values for a given mode 1421 * Calculate the PLL values for a given mode
1422 */ 1422 */
1423 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs, 1423 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1424 unsigned long freq) 1424 unsigned long freq)
1425 { 1425 {
1426 const struct { 1426 const struct {
1427 int divider; 1427 int divider;
1428 int bitvalue; 1428 int bitvalue;
1429 } *post_div, 1429 } *post_div,
1430 post_divs[] = { 1430 post_divs[] = {
1431 { 1, 0 }, 1431 { 1, 0 },
1432 { 2, 1 }, 1432 { 2, 1 },
1433 { 4, 2 }, 1433 { 4, 2 },
1434 { 8, 3 }, 1434 { 8, 3 },
1435 { 3, 4 }, 1435 { 3, 4 },
1436 { 16, 5 }, 1436 { 16, 5 },
1437 { 6, 6 }, 1437 { 6, 6 },
1438 { 12, 7 }, 1438 { 12, 7 },
1439 { 0, 0 }, 1439 { 0, 0 },
1440 }; 1440 };
1441 int fb_div, pll_output_freq = 0; 1441 int fb_div, pll_output_freq = 0;
1442 int uses_dvo = 0; 1442 int uses_dvo = 0;
1443 1443
1444 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm 1444 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1445 * not sure which model starts having FP2_GEN_CNTL, I assume anything more 1445 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1446 * recent than an r(v)100... 1446 * recent than an r(v)100...
1447 */ 1447 */
1448 #if 1 1448 #if 1
1449 /* XXX I had reports of flicker happening with the cinema display 1449 /* XXX I had reports of flicker happening with the cinema display
1450 * on TMDS1 that seem to be fixed if I also forbit odd dividers in 1450 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1451 * this case. This could just be a bandwidth calculation issue, I 1451 * this case. This could just be a bandwidth calculation issue, I
1452 * haven't implemented the bandwidth code yet, but in the meantime, 1452 * haven't implemented the bandwidth code yet, but in the meantime,
1453 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects, 1453 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1454 * I haven't seen a case were were absolutely needed an odd PLL 1454 * I haven't seen a case were were absolutely needed an odd PLL
1455 * divider. I'll find a better fix once I have more infos on the 1455 * divider. I'll find a better fix once I have more infos on the
1456 * real cause of the problem. 1456 * real cause of the problem.
1457 */ 1457 */
1458 while (rinfo->has_CRTC2) { 1458 while (rinfo->has_CRTC2) {
1459 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL); 1459 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1460 u32 disp_output_cntl; 1460 u32 disp_output_cntl;
1461 int source; 1461 int source;
1462 1462
1463 /* FP2 path not enabled */ 1463 /* FP2 path not enabled */
1464 if ((fp2_gen_cntl & FP2_ON) == 0) 1464 if ((fp2_gen_cntl & FP2_ON) == 0)
1465 break; 1465 break;
1466 /* Not all chip revs have the same format for this register, 1466 /* Not all chip revs have the same format for this register,
1467 * extract the source selection 1467 * extract the source selection
1468 */ 1468 */
1469 if (rinfo->family == CHIP_FAMILY_R200 || 1469 if (rinfo->family == CHIP_FAMILY_R200 ||
1470 rinfo->family == CHIP_FAMILY_R300 || 1470 rinfo->family == CHIP_FAMILY_R300 ||
1471 rinfo->family == CHIP_FAMILY_R350 || 1471 rinfo->family == CHIP_FAMILY_R350 ||
1472 rinfo->family == CHIP_FAMILY_RV350) { 1472 rinfo->family == CHIP_FAMILY_RV350) {
1473 source = (fp2_gen_cntl >> 10) & 0x3; 1473 source = (fp2_gen_cntl >> 10) & 0x3;
1474 /* sourced from transform unit, check for transform unit 1474 /* sourced from transform unit, check for transform unit
1475 * own source 1475 * own source
1476 */ 1476 */
1477 if (source == 3) { 1477 if (source == 3) {
1478 disp_output_cntl = INREG(DISP_OUTPUT_CNTL); 1478 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1479 source = (disp_output_cntl >> 12) & 0x3; 1479 source = (disp_output_cntl >> 12) & 0x3;
1480 } 1480 }
1481 } else 1481 } else
1482 source = (fp2_gen_cntl >> 13) & 0x1; 1482 source = (fp2_gen_cntl >> 13) & 0x1;
1483 /* sourced from CRTC2 -> exit */ 1483 /* sourced from CRTC2 -> exit */
1484 if (source == 1) 1484 if (source == 1)
1485 break; 1485 break;
1486 1486
1487 /* so we end up on CRTC1, let's set uses_dvo to 1 now */ 1487 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1488 uses_dvo = 1; 1488 uses_dvo = 1;
1489 break; 1489 break;
1490 } 1490 }
1491 #else 1491 #else
1492 uses_dvo = 1; 1492 uses_dvo = 1;
1493 #endif 1493 #endif
1494 if (freq > rinfo->pll.ppll_max) 1494 if (freq > rinfo->pll.ppll_max)
1495 freq = rinfo->pll.ppll_max; 1495 freq = rinfo->pll.ppll_max;
1496 if (freq*12 < rinfo->pll.ppll_min) 1496 if (freq*12 < rinfo->pll.ppll_min)
1497 freq = rinfo->pll.ppll_min / 12; 1497 freq = rinfo->pll.ppll_min / 12;
1498 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n", 1498 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1499 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max); 1499 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1500 1500
1501 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 1501 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1502 pll_output_freq = post_div->divider * freq; 1502 pll_output_freq = post_div->divider * freq;
1503 /* If we output to the DVO port (external TMDS), we don't allow an 1503 /* If we output to the DVO port (external TMDS), we don't allow an
1504 * odd PLL divider as those aren't supported on this path 1504 * odd PLL divider as those aren't supported on this path
1505 */ 1505 */
1506 if (uses_dvo && (post_div->divider & 1)) 1506 if (uses_dvo && (post_div->divider & 1))
1507 continue; 1507 continue;
1508 if (pll_output_freq >= rinfo->pll.ppll_min && 1508 if (pll_output_freq >= rinfo->pll.ppll_min &&
1509 pll_output_freq <= rinfo->pll.ppll_max) 1509 pll_output_freq <= rinfo->pll.ppll_max)
1510 break; 1510 break;
1511 } 1511 }
1512 1512
1513 /* If we fall through the bottom, try the "default value" 1513 /* If we fall through the bottom, try the "default value"
1514 given by the terminal post_div->bitvalue */ 1514 given by the terminal post_div->bitvalue */
1515 if ( !post_div->divider ) { 1515 if ( !post_div->divider ) {
1516 post_div = &post_divs[post_div->bitvalue]; 1516 post_div = &post_divs[post_div->bitvalue];
1517 pll_output_freq = post_div->divider * freq; 1517 pll_output_freq = post_div->divider * freq;
1518 } 1518 }
1519 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n", 1519 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1520 rinfo->pll.ref_div, rinfo->pll.ref_clk, 1520 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1521 pll_output_freq); 1521 pll_output_freq);
1522 1522
1523 /* If we fall through the bottom, try the "default value" 1523 /* If we fall through the bottom, try the "default value"
1524 given by the terminal post_div->bitvalue */ 1524 given by the terminal post_div->bitvalue */
1525 if ( !post_div->divider ) { 1525 if ( !post_div->divider ) {
1526 post_div = &post_divs[post_div->bitvalue]; 1526 post_div = &post_divs[post_div->bitvalue];
1527 pll_output_freq = post_div->divider * freq; 1527 pll_output_freq = post_div->divider * freq;
1528 } 1528 }
1529 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n", 1529 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1530 rinfo->pll.ref_div, rinfo->pll.ref_clk, 1530 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1531 pll_output_freq); 1531 pll_output_freq);
1532 1532
1533 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, 1533 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1534 rinfo->pll.ref_clk); 1534 rinfo->pll.ref_clk);
1535 regs->ppll_ref_div = rinfo->pll.ref_div; 1535 regs->ppll_ref_div = rinfo->pll.ref_div;
1536 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); 1536 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1537 1537
1538 RTRACE("post div = 0x%x\n", post_div->bitvalue); 1538 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1539 RTRACE("fb_div = 0x%x\n", fb_div); 1539 RTRACE("fb_div = 0x%x\n", fb_div);
1540 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3); 1540 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1541 } 1541 }
1542 1542
1543 static int radeonfb_set_par(struct fb_info *info) 1543 static int radeonfb_set_par(struct fb_info *info)
1544 { 1544 {
1545 struct radeonfb_info *rinfo = info->par; 1545 struct radeonfb_info *rinfo = info->par;
1546 struct fb_var_screeninfo *mode = &info->var; 1546 struct fb_var_screeninfo *mode = &info->var;
1547 struct radeon_regs *newmode; 1547 struct radeon_regs *newmode;
1548 int hTotal, vTotal, hSyncStart, hSyncEnd, 1548 int hTotal, vTotal, hSyncStart, hSyncEnd,
1549 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync; 1549 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1550 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5}; 1550 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1551 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5}; 1551 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1552 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock; 1552 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1553 int i, freq; 1553 int i, freq;
1554 int format = 0; 1554 int format = 0;
1555 int nopllcalc = 0; 1555 int nopllcalc = 0;
1556 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid; 1556 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1557 int primary_mon = PRIMARY_MONITOR(rinfo); 1557 int primary_mon = PRIMARY_MONITOR(rinfo);
1558 int depth = var_to_depth(mode); 1558 int depth = var_to_depth(mode);
1559 int use_rmx = 0; 1559 int use_rmx = 0;
1560 1560
1561 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL); 1561 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1562 if (!newmode) 1562 if (!newmode)
1563 return -ENOMEM; 1563 return -ENOMEM;
1564 1564
1565 /* We always want engine to be idle on a mode switch, even 1565 /* We always want engine to be idle on a mode switch, even
1566 * if we won't actually change the mode 1566 * if we won't actually change the mode
1567 */ 1567 */
1568 radeon_engine_idle(); 1568 radeon_engine_idle();
1569 1569
1570 hSyncStart = mode->xres + mode->right_margin; 1570 hSyncStart = mode->xres + mode->right_margin;
1571 hSyncEnd = hSyncStart + mode->hsync_len; 1571 hSyncEnd = hSyncStart + mode->hsync_len;
1572 hTotal = hSyncEnd + mode->left_margin; 1572 hTotal = hSyncEnd + mode->left_margin;
1573 1573
1574 vSyncStart = mode->yres + mode->lower_margin; 1574 vSyncStart = mode->yres + mode->lower_margin;
1575 vSyncEnd = vSyncStart + mode->vsync_len; 1575 vSyncEnd = vSyncStart + mode->vsync_len;
1576 vTotal = vSyncEnd + mode->upper_margin; 1576 vTotal = vSyncEnd + mode->upper_margin;
1577 pixClock = mode->pixclock; 1577 pixClock = mode->pixclock;
1578 1578
1579 sync = mode->sync; 1579 sync = mode->sync;
1580 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 1580 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1581 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 1581 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1582 1582
1583 if (primary_mon == MT_DFP || primary_mon == MT_LCD) { 1583 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1584 if (rinfo->panel_info.xres < mode->xres) 1584 if (rinfo->panel_info.xres < mode->xres)
1585 mode->xres = rinfo->panel_info.xres; 1585 mode->xres = rinfo->panel_info.xres;
1586 if (rinfo->panel_info.yres < mode->yres) 1586 if (rinfo->panel_info.yres < mode->yres)
1587 mode->yres = rinfo->panel_info.yres; 1587 mode->yres = rinfo->panel_info.yres;
1588 1588
1589 hTotal = mode->xres + rinfo->panel_info.hblank; 1589 hTotal = mode->xres + rinfo->panel_info.hblank;
1590 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus; 1590 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1591 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width; 1591 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1592 1592
1593 vTotal = mode->yres + rinfo->panel_info.vblank; 1593 vTotal = mode->yres + rinfo->panel_info.vblank;
1594 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus; 1594 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1595 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width; 1595 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1596 1596
1597 h_sync_pol = !rinfo->panel_info.hAct_high; 1597 h_sync_pol = !rinfo->panel_info.hAct_high;
1598 v_sync_pol = !rinfo->panel_info.vAct_high; 1598 v_sync_pol = !rinfo->panel_info.vAct_high;
1599 1599
1600 pixClock = 100000000 / rinfo->panel_info.clock; 1600 pixClock = 100000000 / rinfo->panel_info.clock;
1601 1601
1602 if (rinfo->panel_info.use_bios_dividers) { 1602 if (rinfo->panel_info.use_bios_dividers) {
1603 nopllcalc = 1; 1603 nopllcalc = 1;
1604 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider | 1604 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1605 (rinfo->panel_info.post_divider << 16); 1605 (rinfo->panel_info.post_divider << 16);
1606 newmode->ppll_ref_div = rinfo->panel_info.ref_divider; 1606 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1607 } 1607 }
1608 } 1608 }
1609 dotClock = 1000000000 / pixClock; 1609 dotClock = 1000000000 / pixClock;
1610 freq = dotClock / 10; /* x100 */ 1610 freq = dotClock / 10; /* x100 */
1611 1611
1612 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n", 1612 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1613 hSyncStart, hSyncEnd, hTotal); 1613 hSyncStart, hSyncEnd, hTotal);
1614 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n", 1614 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1615 vSyncStart, vSyncEnd, vTotal); 1615 vSyncStart, vSyncEnd, vTotal);
1616 1616
1617 hsync_wid = (hSyncEnd - hSyncStart) / 8; 1617 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1618 vsync_wid = vSyncEnd - vSyncStart; 1618 vsync_wid = vSyncEnd - vSyncStart;
1619 if (hsync_wid == 0) 1619 if (hsync_wid == 0)
1620 hsync_wid = 1; 1620 hsync_wid = 1;
1621 else if (hsync_wid > 0x3f) /* max */ 1621 else if (hsync_wid > 0x3f) /* max */
1622 hsync_wid = 0x3f; 1622 hsync_wid = 0x3f;
1623 1623
1624 if (vsync_wid == 0) 1624 if (vsync_wid == 0)
1625 vsync_wid = 1; 1625 vsync_wid = 1;
1626 else if (vsync_wid > 0x1f) /* max */ 1626 else if (vsync_wid > 0x1f) /* max */
1627 vsync_wid = 0x1f; 1627 vsync_wid = 0x1f;
1628 1628
1629 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 1629 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1630 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 1630 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1631 1631
1632 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; 1632 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1633 1633
1634 format = radeon_get_dstbpp(depth); 1634 format = radeon_get_dstbpp(depth);
1635 bytpp = mode->bits_per_pixel >> 3; 1635 bytpp = mode->bits_per_pixel >> 3;
1636 1636
1637 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) 1637 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1638 hsync_fudge = hsync_fudge_fp[format-1]; 1638 hsync_fudge = hsync_fudge_fp[format-1];
1639 else 1639 else
1640 hsync_fudge = hsync_adj_tab[format-1]; 1640 hsync_fudge = hsync_adj_tab[format-1];
1641 1641
1642 hsync_start = hSyncStart - 8 + hsync_fudge; 1642 hsync_start = hSyncStart - 8 + hsync_fudge;
1643 1643
1644 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | 1644 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1645 (format << 8); 1645 (format << 8);
1646 1646
1647 /* Clear auto-center etc... */ 1647 /* Clear auto-center etc... */
1648 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl; 1648 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1649 newmode->crtc_more_cntl &= 0xfffffff0; 1649 newmode->crtc_more_cntl &= 0xfffffff0;
1650 1650
1651 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1651 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1652 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN; 1652 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1653 if (mirror) 1653 if (mirror)
1654 newmode->crtc_ext_cntl |= CRTC_CRT_ON; 1654 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1655 1655
1656 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN | 1656 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1657 CRTC_INTERLACE_EN); 1657 CRTC_INTERLACE_EN);
1658 } else { 1658 } else {
1659 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | 1659 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1660 CRTC_CRT_ON; 1660 CRTC_CRT_ON;
1661 } 1661 }
1662 1662
1663 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN | 1663 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1664 DAC_8BIT_EN; 1664 DAC_8BIT_EN;
1665 1665
1666 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) | 1666 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1667 (((mode->xres / 8) - 1) << 16)); 1667 (((mode->xres / 8) - 1) << 16));
1668 1668
1669 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) | 1669 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1670 (hsync_wid << 16) | (h_sync_pol << 23)); 1670 (hsync_wid << 16) | (h_sync_pol << 23));
1671 1671
1672 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | 1672 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1673 ((mode->yres - 1) << 16); 1673 ((mode->yres - 1) << 16);
1674 1674
1675 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) | 1675 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1676 (vsync_wid << 16) | (v_sync_pol << 23)); 1676 (vsync_wid << 16) | (v_sync_pol << 23));
1677 1677
1678 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { 1678 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1679 /* We first calculate the engine pitch */ 1679 /* We first calculate the engine pitch */
1680 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f) 1680 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1681 & ~(0x3f)) >> 6; 1681 & ~(0x3f)) >> 6;
1682 1682
1683 /* Then, re-multiply it to get the CRTC pitch */ 1683 /* Then, re-multiply it to get the CRTC pitch */
1684 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8); 1684 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1685 } else 1685 } else
1686 newmode->crtc_pitch = (mode->xres_virtual >> 3); 1686 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1687 1687
1688 newmode->crtc_pitch |= (newmode->crtc_pitch << 16); 1688 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1689 1689
1690 /* 1690 /*
1691 * It looks like recent chips have a problem with SURFACE_CNTL, 1691 * It looks like recent chips have a problem with SURFACE_CNTL,
1692 * setting SURF_TRANSLATION_DIS completely disables the 1692 * setting SURF_TRANSLATION_DIS completely disables the
1693 * swapper as well, so we leave it unset now. 1693 * swapper as well, so we leave it unset now.
1694 */ 1694 */
1695 newmode->surface_cntl = 0; 1695 newmode->surface_cntl = 0;
1696 1696
1697 #if defined(__BIG_ENDIAN) 1697 #if defined(__BIG_ENDIAN)
1698 1698
1699 /* Setup swapping on both apertures, though we currently 1699 /* Setup swapping on both apertures, though we currently
1700 * only use aperture 0, enabling swapper on aperture 1 1700 * only use aperture 0, enabling swapper on aperture 1
1701 * won't harm 1701 * won't harm
1702 */ 1702 */
1703 switch (mode->bits_per_pixel) { 1703 switch (mode->bits_per_pixel) {
1704 case 16: 1704 case 16:
1705 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP; 1705 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1706 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP; 1706 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1707 break; 1707 break;
1708 case 24: 1708 case 24:
1709 case 32: 1709 case 32:
1710 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP; 1710 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1711 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP; 1711 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1712 break; 1712 break;
1713 } 1713 }
1714 #endif 1714 #endif
1715 1715
1716 /* Clear surface registers */ 1716 /* Clear surface registers */
1717 for (i=0; i<8; i++) { 1717 for (i=0; i<8; i++) {
1718 newmode->surf_lower_bound[i] = 0; 1718 newmode->surf_lower_bound[i] = 0;
1719 newmode->surf_upper_bound[i] = 0x1f; 1719 newmode->surf_upper_bound[i] = 0x1f;
1720 newmode->surf_info[i] = 0; 1720 newmode->surf_info[i] = 0;
1721 } 1721 }
1722 1722
1723 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n", 1723 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1724 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid); 1724 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1725 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n", 1725 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1726 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid); 1726 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1727 1727
1728 rinfo->bpp = mode->bits_per_pixel; 1728 rinfo->bpp = mode->bits_per_pixel;
1729 rinfo->depth = depth; 1729 rinfo->depth = depth;
1730 1730
1731 RTRACE("pixclock = %lu\n", (unsigned long)pixClock); 1731 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1732 RTRACE("freq = %lu\n", (unsigned long)freq); 1732 RTRACE("freq = %lu\n", (unsigned long)freq);
1733 1733
1734 /* We use PPLL_DIV_3 */ 1734 /* We use PPLL_DIV_3 */
1735 newmode->clk_cntl_index = 0x300; 1735 newmode->clk_cntl_index = 0x300;
1736 1736
1737 /* Calculate PPLL value if necessary */ 1737 /* Calculate PPLL value if necessary */
1738 if (!nopllcalc) 1738 if (!nopllcalc)
1739 radeon_calc_pll_regs(rinfo, newmode, freq); 1739 radeon_calc_pll_regs(rinfo, newmode, freq);
1740 1740
1741 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl; 1741 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1742 1742
1743 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1743 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1744 unsigned int hRatio, vRatio; 1744 unsigned int hRatio, vRatio;
1745 1745
1746 if (mode->xres > rinfo->panel_info.xres) 1746 if (mode->xres > rinfo->panel_info.xres)
1747 mode->xres = rinfo->panel_info.xres; 1747 mode->xres = rinfo->panel_info.xres;
1748 if (mode->yres > rinfo->panel_info.yres) 1748 if (mode->yres > rinfo->panel_info.yres)
1749 mode->yres = rinfo->panel_info.yres; 1749 mode->yres = rinfo->panel_info.yres;
1750 1750
1751 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1) 1751 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1752 << HORZ_PANEL_SHIFT); 1752 << HORZ_PANEL_SHIFT);
1753 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1) 1753 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1754 << VERT_PANEL_SHIFT); 1754 << VERT_PANEL_SHIFT);
1755 1755
1756 if (mode->xres != rinfo->panel_info.xres) { 1756 if (mode->xres != rinfo->panel_info.xres) {
1757 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX, 1757 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1758 rinfo->panel_info.xres); 1758 rinfo->panel_info.xres);
1759 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) | 1759 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1760 (newmode->fp_horz_stretch & 1760 (newmode->fp_horz_stretch &
1761 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH | 1761 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1762 HORZ_AUTO_RATIO_INC))); 1762 HORZ_AUTO_RATIO_INC)));
1763 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND | 1763 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1764 HORZ_STRETCH_ENABLE); 1764 HORZ_STRETCH_ENABLE);
1765 use_rmx = 1; 1765 use_rmx = 1;
1766 } 1766 }
1767 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO; 1767 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1768 1768
1769 if (mode->yres != rinfo->panel_info.yres) { 1769 if (mode->yres != rinfo->panel_info.yres) {
1770 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX, 1770 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1771 rinfo->panel_info.yres); 1771 rinfo->panel_info.yres);
1772 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) | 1772 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1773 (newmode->fp_vert_stretch & 1773 (newmode->fp_vert_stretch &
1774 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED))); 1774 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1775 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND | 1775 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1776 VERT_STRETCH_ENABLE); 1776 VERT_STRETCH_ENABLE);
1777 use_rmx = 1; 1777 use_rmx = 1;
1778 } 1778 }
1779 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN; 1779 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1780 1780
1781 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32) 1781 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1782 ~(FP_SEL_CRTC2 | 1782 ~(FP_SEL_CRTC2 |
1783 FP_RMX_HVSYNC_CONTROL_EN | 1783 FP_RMX_HVSYNC_CONTROL_EN |
1784 FP_DFP_SYNC_SEL | 1784 FP_DFP_SYNC_SEL |
1785 FP_CRT_SYNC_SEL | 1785 FP_CRT_SYNC_SEL |
1786 FP_CRTC_LOCK_8DOT | 1786 FP_CRTC_LOCK_8DOT |
1787 FP_USE_SHADOW_EN | 1787 FP_USE_SHADOW_EN |
1788 FP_CRTC_USE_SHADOW_VEND | 1788 FP_CRTC_USE_SHADOW_VEND |
1789 FP_CRT_SYNC_ALT)); 1789 FP_CRT_SYNC_ALT));
1790 1790
1791 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR | 1791 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1792 FP_CRTC_DONT_SHADOW_HEND | 1792 FP_CRTC_DONT_SHADOW_HEND |
1793 FP_PANEL_FORMAT); 1793 FP_PANEL_FORMAT);
1794 1794
1795 if (IS_R300_VARIANT(rinfo) || 1795 if (IS_R300_VARIANT(rinfo) ||
1796 (rinfo->family == CHIP_FAMILY_R200)) { 1796 (rinfo->family == CHIP_FAMILY_R200)) {
1797 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 1797 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1798 if (use_rmx) 1798 if (use_rmx)
1799 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; 1799 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1800 else 1800 else
1801 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; 1801 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1802 } else 1802 } else
1803 newmode->fp_gen_cntl |= FP_SEL_CRTC1; 1803 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1804 1804
1805 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl; 1805 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1806 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl; 1806 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1807 newmode->tmds_crc = rinfo->init_state.tmds_crc; 1807 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1808 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl; 1808 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1809 1809
1810 if (primary_mon == MT_LCD) { 1810 if (primary_mon == MT_LCD) {
1811 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON); 1811 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1812 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN); 1812 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1813 } else { 1813 } else {
1814 /* DFP */ 1814 /* DFP */
1815 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); 1815 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1816 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST); 1816 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1817 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */ 1817 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1818 if (IS_R300_VARIANT(rinfo) || 1818 if (IS_R300_VARIANT(rinfo) ||
1819 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2) 1819 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1820 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN; 1820 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1821 else 1821 else
1822 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN; 1822 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1823 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON; 1823 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1824 } 1824 }
1825 1825
1826 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) | 1826 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1827 (((mode->xres / 8) - 1) << 16)); 1827 (((mode->xres / 8) - 1) << 16));
1828 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) | 1828 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1829 ((mode->yres - 1) << 16); 1829 ((mode->yres - 1) << 16);
1830 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) | 1830 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1831 (hsync_wid << 16) | (h_sync_pol << 23)); 1831 (hsync_wid << 16) | (h_sync_pol << 23));
1832 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) | 1832 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1833 (vsync_wid << 16) | (v_sync_pol << 23)); 1833 (vsync_wid << 16) | (v_sync_pol << 23));
1834 } 1834 }
1835 1835
1836 /* do it! */ 1836 /* do it! */
1837 if (!rinfo->asleep) { 1837 if (!rinfo->asleep) {
1838 memcpy(&rinfo->state, newmode, sizeof(*newmode)); 1838 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1839 radeon_write_mode (rinfo, newmode, 0); 1839 radeon_write_mode (rinfo, newmode, 0);
1840 /* (re)initialize the engine */ 1840 /* (re)initialize the engine */
1841 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) 1841 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1842 radeonfb_engine_init (rinfo); 1842 radeonfb_engine_init (rinfo);
1843 } 1843 }
1844 /* Update fix */ 1844 /* Update fix */
1845 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) 1845 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1846 info->fix.line_length = rinfo->pitch*64; 1846 info->fix.line_length = rinfo->pitch*64;
1847 else 1847 else
1848 info->fix.line_length = mode->xres_virtual 1848 info->fix.line_length = mode->xres_virtual
1849 * ((mode->bits_per_pixel + 1) / 8); 1849 * ((mode->bits_per_pixel + 1) / 8);
1850 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR 1850 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1851 : FB_VISUAL_DIRECTCOLOR; 1851 : FB_VISUAL_DIRECTCOLOR;
1852 1852
1853 #ifdef CONFIG_BOOTX_TEXT 1853 #ifdef CONFIG_BOOTX_TEXT
1854 /* Update debug text engine */ 1854 /* Update debug text engine */
1855 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres, 1855 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1856 rinfo->depth, info->fix.line_length); 1856 rinfo->depth, info->fix.line_length);
1857 #endif 1857 #endif
1858 1858
1859 kfree(newmode); 1859 kfree(newmode);
1860 return 0; 1860 return 0;
1861 } 1861 }
1862 1862
1863 1863
1864 static struct fb_ops radeonfb_ops = { 1864 static struct fb_ops radeonfb_ops = {
1865 .owner = THIS_MODULE, 1865 .owner = THIS_MODULE,
1866 .fb_check_var = radeonfb_check_var, 1866 .fb_check_var = radeonfb_check_var,
1867 .fb_set_par = radeonfb_set_par, 1867 .fb_set_par = radeonfb_set_par,
1868 .fb_setcolreg = radeonfb_setcolreg, 1868 .fb_setcolreg = radeonfb_setcolreg,
1869 .fb_setcmap = radeonfb_setcmap, 1869 .fb_setcmap = radeonfb_setcmap,
1870 .fb_pan_display = radeonfb_pan_display, 1870 .fb_pan_display = radeonfb_pan_display,
1871 .fb_blank = radeonfb_blank, 1871 .fb_blank = radeonfb_blank,
1872 .fb_ioctl = radeonfb_ioctl, 1872 .fb_ioctl = radeonfb_ioctl,
1873 .fb_sync = radeonfb_sync, 1873 .fb_sync = radeonfb_sync,
1874 .fb_fillrect = radeonfb_fillrect, 1874 .fb_fillrect = radeonfb_fillrect,
1875 .fb_copyarea = radeonfb_copyarea, 1875 .fb_copyarea = radeonfb_copyarea,
1876 .fb_imageblit = radeonfb_imageblit, 1876 .fb_imageblit = radeonfb_imageblit,
1877 }; 1877 };
1878 1878
1879 1879
1880 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo) 1880 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1881 { 1881 {
1882 struct fb_info *info = rinfo->info; 1882 struct fb_info *info = rinfo->info;
1883 1883
1884 info->par = rinfo; 1884 info->par = rinfo;
1885 info->pseudo_palette = rinfo->pseudo_palette; 1885 info->pseudo_palette = rinfo->pseudo_palette;
1886 info->flags = FBINFO_DEFAULT 1886 info->flags = FBINFO_DEFAULT
1887 | FBINFO_HWACCEL_COPYAREA 1887 | FBINFO_HWACCEL_COPYAREA
1888 | FBINFO_HWACCEL_FILLRECT 1888 | FBINFO_HWACCEL_FILLRECT
1889 | FBINFO_HWACCEL_XPAN 1889 | FBINFO_HWACCEL_XPAN
1890 | FBINFO_HWACCEL_YPAN; 1890 | FBINFO_HWACCEL_YPAN;
1891 info->fbops = &radeonfb_ops; 1891 info->fbops = &radeonfb_ops;
1892 info->screen_base = rinfo->fb_base; 1892 info->screen_base = rinfo->fb_base;
1893 info->screen_size = rinfo->mapped_vram; 1893 info->screen_size = rinfo->mapped_vram;
1894 /* Fill fix common fields */ 1894 /* Fill fix common fields */
1895 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); 1895 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1896 info->fix.smem_start = rinfo->fb_base_phys; 1896 info->fix.smem_start = rinfo->fb_base_phys;
1897 info->fix.smem_len = rinfo->video_ram; 1897 info->fix.smem_len = rinfo->video_ram;
1898 info->fix.type = FB_TYPE_PACKED_PIXELS; 1898 info->fix.type = FB_TYPE_PACKED_PIXELS;
1899 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 1899 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1900 info->fix.xpanstep = 8; 1900 info->fix.xpanstep = 8;
1901 info->fix.ypanstep = 1; 1901 info->fix.ypanstep = 1;
1902 info->fix.ywrapstep = 0; 1902 info->fix.ywrapstep = 0;
1903 info->fix.type_aux = 0; 1903 info->fix.type_aux = 0;
1904 info->fix.mmio_start = rinfo->mmio_base_phys; 1904 info->fix.mmio_start = rinfo->mmio_base_phys;
1905 info->fix.mmio_len = RADEON_REGSIZE; 1905 info->fix.mmio_len = RADEON_REGSIZE;
1906 info->fix.accel = FB_ACCEL_ATI_RADEON; 1906 info->fix.accel = FB_ACCEL_ATI_RADEON;
1907 1907
1908 fb_alloc_cmap(&info->cmap, 256, 0); 1908 fb_alloc_cmap(&info->cmap, 256, 0);
1909 1909
1910 if (noaccel) 1910 if (noaccel)
1911 info->flags |= FBINFO_HWACCEL_DISABLED; 1911 info->flags |= FBINFO_HWACCEL_DISABLED;
1912 1912
1913 return 0; 1913 return 0;
1914 } 1914 }
1915 1915
1916 1916
1917 #ifdef CONFIG_PMAC_BACKLIGHT 1917 #ifdef CONFIG_PMAC_BACKLIGHT
1918 1918
1919 /* TODO: Dbl check these tables, we don't go up to full ON backlight 1919 /* TODO: Dbl check these tables, we don't go up to full ON backlight
1920 * in these, possibly because we noticed MacOS doesn't, but I'd prefer 1920 * in these, possibly because we noticed MacOS doesn't, but I'd prefer
1921 * having some more official numbers from ATI 1921 * having some more official numbers from ATI
1922 */ 1922 */
1923 static int backlight_conv_m6[] = { 1923 static int backlight_conv_m6[] = {
1924 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e, 1924 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
1925 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24 1925 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
1926 }; 1926 };
1927 static int backlight_conv_m7[] = { 1927 static int backlight_conv_m7[] = {
1928 0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81, 1928 0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
1929 0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9 1929 0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
1930 }; 1930 };
1931 1931
1932 #define BACKLIGHT_LVDS_OFF 1932 #define BACKLIGHT_LVDS_OFF
1933 #undef BACKLIGHT_DAC_OFF 1933 #undef BACKLIGHT_DAC_OFF
1934 1934
1935 /* We turn off the LCD completely instead of just dimming the backlight. 1935 /* We turn off the LCD completely instead of just dimming the backlight.
1936 * This provides some greater power saving and the display is useless 1936 * This provides some greater power saving and the display is useless
1937 * without backlight anyway. 1937 * without backlight anyway.
1938 */ 1938 */
1939 static int radeon_set_backlight_enable(int on, int level, void *data) 1939 static int radeon_set_backlight_enable(int on, int level, void *data)
1940 { 1940 {
1941 struct radeonfb_info *rinfo = (struct radeonfb_info *)data; 1941 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1942 u32 lvds_gen_cntl, tmpPixclksCntl; 1942 u32 lvds_gen_cntl, tmpPixclksCntl;
1943 int* conv_table; 1943 int* conv_table;
1944 1944
1945 if (rinfo->mon1_type != MT_LCD) 1945 if (rinfo->mon1_type != MT_LCD)
1946 return 0; 1946 return 0;
1947 1947
1948 /* Pardon me for that hack... maybe some day we can figure 1948 /* Pardon me for that hack... maybe some day we can figure
1949 * out in what direction backlight should work on a given 1949 * out in what direction backlight should work on a given
1950 * panel ? 1950 * panel ?
1951 */ 1951 */
1952 if ((rinfo->family == CHIP_FAMILY_RV200 || 1952 if ((rinfo->family == CHIP_FAMILY_RV200 ||
1953 rinfo->family == CHIP_FAMILY_RV250 || 1953 rinfo->family == CHIP_FAMILY_RV250 ||
1954 rinfo->family == CHIP_FAMILY_RV280 || 1954 rinfo->family == CHIP_FAMILY_RV280 ||
1955 rinfo->family == CHIP_FAMILY_RV350) && 1955 rinfo->family == CHIP_FAMILY_RV350) &&
1956 !machine_is_compatible("PowerBook4,3") && 1956 !machine_is_compatible("PowerBook4,3") &&
1957 !machine_is_compatible("PowerBook6,3") && 1957 !machine_is_compatible("PowerBook6,3") &&
1958 !machine_is_compatible("PowerBook6,5")) 1958 !machine_is_compatible("PowerBook6,5"))
1959 conv_table = backlight_conv_m7; 1959 conv_table = backlight_conv_m7;
1960 else 1960 else
1961 conv_table = backlight_conv_m6; 1961 conv_table = backlight_conv_m6;
1962 1962
1963 del_timer_sync(&rinfo->lvds_timer); 1963 del_timer_sync(&rinfo->lvds_timer);
1964 radeon_engine_idle(); 1964 radeon_engine_idle();
1965 1965
1966 lvds_gen_cntl = INREG(LVDS_GEN_CNTL); 1966 lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1967 if (on && (level > BACKLIGHT_OFF)) { 1967 if (on && (level > BACKLIGHT_OFF)) {
1968 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS; 1968 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
1969 if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) { 1969 if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) {
1970 lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON); 1970 lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON);
1971 lvds_gen_cntl |= LVDS_BLON | LVDS_EN; 1971 lvds_gen_cntl |= LVDS_BLON | LVDS_EN;
1972 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl); 1972 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1973 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK; 1973 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1974 lvds_gen_cntl |= (conv_table[level] << 1974 lvds_gen_cntl |= (conv_table[level] <<
1975 LVDS_BL_MOD_LEVEL_SHIFT); 1975 LVDS_BL_MOD_LEVEL_SHIFT);
1976 lvds_gen_cntl |= LVDS_ON; 1976 lvds_gen_cntl |= LVDS_ON;
1977 lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN); 1977 lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN);
1978 rinfo->pending_lvds_gen_cntl = lvds_gen_cntl; 1978 rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
1979 mod_timer(&rinfo->lvds_timer, 1979 mod_timer(&rinfo->lvds_timer,
1980 jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay)); 1980 jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1981 } else { 1981 } else {
1982 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK; 1982 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1983 lvds_gen_cntl |= (conv_table[level] << 1983 lvds_gen_cntl |= (conv_table[level] <<
1984 LVDS_BL_MOD_LEVEL_SHIFT); 1984 LVDS_BL_MOD_LEVEL_SHIFT);
1985 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl); 1985 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1986 } 1986 }
1987 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; 1987 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1988 rinfo->init_state.lvds_gen_cntl |= rinfo->pending_lvds_gen_cntl 1988 rinfo->init_state.lvds_gen_cntl |= rinfo->pending_lvds_gen_cntl
1989 & LVDS_STATE_MASK; 1989 & LVDS_STATE_MASK;
1990 } else { 1990 } else {
1991 /* Asic bug, when turning off LVDS_ON, we have to make sure 1991 /* Asic bug, when turning off LVDS_ON, we have to make sure
1992 RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off 1992 RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1993 */ 1993 */
1994 tmpPixclksCntl = INPLL(PIXCLKS_CNTL); 1994 tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
1995 if (rinfo->is_mobility || rinfo->is_IGP) 1995 if (rinfo->is_mobility || rinfo->is_IGP)
1996 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb); 1996 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1997 lvds_gen_cntl &= ~(LVDS_BL_MOD_LEVEL_MASK | LVDS_BL_MOD_EN); 1997 lvds_gen_cntl &= ~(LVDS_BL_MOD_LEVEL_MASK | LVDS_BL_MOD_EN);
1998 lvds_gen_cntl |= (conv_table[0] << 1998 lvds_gen_cntl |= (conv_table[0] <<
1999 LVDS_BL_MOD_LEVEL_SHIFT); 1999 LVDS_BL_MOD_LEVEL_SHIFT);
2000 lvds_gen_cntl |= LVDS_DISPLAY_DIS; 2000 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
2001 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl); 2001 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2002 udelay(100); 2002 udelay(100);
2003 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN); 2003 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN);
2004 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl); 2004 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2005 lvds_gen_cntl &= ~(LVDS_DIGON); 2005 lvds_gen_cntl &= ~(LVDS_DIGON);
2006 rinfo->pending_lvds_gen_cntl = lvds_gen_cntl; 2006 rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
2007 mod_timer(&rinfo->lvds_timer, 2007 mod_timer(&rinfo->lvds_timer,
2008 jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay)); 2008 jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
2009 if (rinfo->is_mobility || rinfo->is_IGP) 2009 if (rinfo->is_mobility || rinfo->is_IGP)
2010 OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl); 2010 OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
2011 } 2011 }
2012 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; 2012 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
2013 rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK); 2013 rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
2014 2014
2015 return 0; 2015 return 0;
2016 } 2016 }
2017 2017
2018 2018
2019 static int radeon_set_backlight_level(int level, void *data) 2019 static int radeon_set_backlight_level(int level, void *data)
2020 { 2020 {
2021 return radeon_set_backlight_enable(1, level, data); 2021 return radeon_set_backlight_enable(1, level, data);
2022 } 2022 }
2023 #endif /* CONFIG_PMAC_BACKLIGHT */ 2023 #endif /* CONFIG_PMAC_BACKLIGHT */
2024 2024
2025 2025
2026 /* 2026 /*
2027 * This reconfigure the card's internal memory map. In theory, we'd like 2027 * This reconfigure the card's internal memory map. In theory, we'd like
2028 * to setup the card's memory at the same address as it's PCI bus address, 2028 * to setup the card's memory at the same address as it's PCI bus address,
2029 * and the AGP aperture right after that so that system RAM on 32 bits 2029 * and the AGP aperture right after that so that system RAM on 32 bits
2030 * machines at least, is directly accessible. However, doing so would 2030 * machines at least, is directly accessible. However, doing so would
2031 * conflict with the current XFree drivers... 2031 * conflict with the current XFree drivers...
2032 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree 2032 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
2033 * on the proper way to set this up and duplicate this here. In the meantime, 2033 * on the proper way to set this up and duplicate this here. In the meantime,
2034 * I put the card's memory at 0 in card space and AGP at some random high 2034 * I put the card's memory at 0 in card space and AGP at some random high
2035 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway 2035 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
2036 */ 2036 */
2037 #ifdef CONFIG_PPC_OF 2037 #ifdef CONFIG_PPC_OF
2038 #undef SET_MC_FB_FROM_APERTURE 2038 #undef SET_MC_FB_FROM_APERTURE
2039 static void fixup_memory_mappings(struct radeonfb_info *rinfo) 2039 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
2040 { 2040 {
2041 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0; 2041 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
2042 u32 save_crtc_ext_cntl; 2042 u32 save_crtc_ext_cntl;
2043 u32 aper_base, aper_size; 2043 u32 aper_base, aper_size;
2044 u32 agp_base; 2044 u32 agp_base;
2045 2045
2046 /* First, we disable display to avoid interfering */ 2046 /* First, we disable display to avoid interfering */
2047 if (rinfo->has_CRTC2) { 2047 if (rinfo->has_CRTC2) {
2048 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL); 2048 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
2049 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B); 2049 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
2050 } 2050 }
2051 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL); 2051 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
2052 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL); 2052 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
2053 2053
2054 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS); 2054 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
2055 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B); 2055 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
2056 mdelay(100); 2056 mdelay(100);
2057 2057
2058 aper_base = INREG(CONFIG_APER_0_BASE); 2058 aper_base = INREG(CONFIG_APER_0_BASE);
2059 aper_size = INREG(CONFIG_APER_SIZE); 2059 aper_size = INREG(CONFIG_APER_SIZE);
2060 2060
2061 #ifdef SET_MC_FB_FROM_APERTURE 2061 #ifdef SET_MC_FB_FROM_APERTURE
2062 /* Set framebuffer to be at the same address as set in PCI BAR */ 2062 /* Set framebuffer to be at the same address as set in PCI BAR */
2063 OUTREG(MC_FB_LOCATION, 2063 OUTREG(MC_FB_LOCATION,
2064 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16)); 2064 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
2065 rinfo->fb_local_base = aper_base; 2065 rinfo->fb_local_base = aper_base;
2066 #else 2066 #else
2067 OUTREG(MC_FB_LOCATION, 0x7fff0000); 2067 OUTREG(MC_FB_LOCATION, 0x7fff0000);
2068 rinfo->fb_local_base = 0; 2068 rinfo->fb_local_base = 0;
2069 #endif 2069 #endif
2070 agp_base = aper_base + aper_size; 2070 agp_base = aper_base + aper_size;
2071 if (agp_base & 0xf0000000) 2071 if (agp_base & 0xf0000000)
2072 agp_base = (aper_base | 0x0fffffff) + 1; 2072 agp_base = (aper_base | 0x0fffffff) + 1;
2073 2073
2074 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This 2074 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
2075 * assumes the FB isn't mapped to 0xf0000000 or above, but this is 2075 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
2076 * always the case on PPCs afaik. 2076 * always the case on PPCs afaik.
2077 */ 2077 */
2078 #ifdef SET_MC_FB_FROM_APERTURE 2078 #ifdef SET_MC_FB_FROM_APERTURE
2079 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16)); 2079 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
2080 #else 2080 #else
2081 OUTREG(MC_AGP_LOCATION, 0xffffe000); 2081 OUTREG(MC_AGP_LOCATION, 0xffffe000);
2082 #endif 2082 #endif
2083 2083
2084 /* Fixup the display base addresses & engine offsets while we 2084 /* Fixup the display base addresses & engine offsets while we
2085 * are at it as well 2085 * are at it as well
2086 */ 2086 */
2087 #ifdef SET_MC_FB_FROM_APERTURE 2087 #ifdef SET_MC_FB_FROM_APERTURE
2088 OUTREG(DISPLAY_BASE_ADDR, aper_base); 2088 OUTREG(DISPLAY_BASE_ADDR, aper_base);
2089 if (rinfo->has_CRTC2) 2089 if (rinfo->has_CRTC2)
2090 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base); 2090 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
2091 OUTREG(OV0_BASE_ADDR, aper_base); 2091 OUTREG(OV0_BASE_ADDR, aper_base);
2092 #else 2092 #else
2093 OUTREG(DISPLAY_BASE_ADDR, 0); 2093 OUTREG(DISPLAY_BASE_ADDR, 0);
2094 if (rinfo->has_CRTC2) 2094 if (rinfo->has_CRTC2)
2095 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0); 2095 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
2096 OUTREG(OV0_BASE_ADDR, 0); 2096 OUTREG(OV0_BASE_ADDR, 0);
2097 #endif 2097 #endif
2098 mdelay(100); 2098 mdelay(100);
2099 2099
2100 /* Restore display settings */ 2100 /* Restore display settings */
2101 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl); 2101 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
2102 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl); 2102 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
2103 if (rinfo->has_CRTC2) 2103 if (rinfo->has_CRTC2)
2104 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl); 2104 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
2105 2105
2106 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n", 2106 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
2107 aper_base, 2107 aper_base,
2108 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16), 2108 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2109 0xffff0000 | (agp_base >> 16)); 2109 0xffff0000 | (agp_base >> 16));
2110 } 2110 }
2111 #endif /* CONFIG_PPC_OF */ 2111 #endif /* CONFIG_PPC_OF */
2112 2112
2113 2113
2114 static void radeon_identify_vram(struct radeonfb_info *rinfo) 2114 static void radeon_identify_vram(struct radeonfb_info *rinfo)
2115 { 2115 {
2116 u32 tmp; 2116 u32 tmp;
2117 2117
2118 /* framebuffer size */ 2118 /* framebuffer size */
2119 if ((rinfo->family == CHIP_FAMILY_RS100) || 2119 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2120 (rinfo->family == CHIP_FAMILY_RS200) || 2120 (rinfo->family == CHIP_FAMILY_RS200) ||
2121 (rinfo->family == CHIP_FAMILY_RS300)) { 2121 (rinfo->family == CHIP_FAMILY_RS300)) {
2122 u32 tom = INREG(NB_TOM); 2122 u32 tom = INREG(NB_TOM);
2123 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); 2123 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2124 2124
2125 radeon_fifo_wait(6); 2125 radeon_fifo_wait(6);
2126 OUTREG(MC_FB_LOCATION, tom); 2126 OUTREG(MC_FB_LOCATION, tom);
2127 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2127 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2128 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2128 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2129 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); 2129 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2130 2130
2131 /* This is supposed to fix the crtc2 noise problem. */ 2131 /* This is supposed to fix the crtc2 noise problem. */
2132 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); 2132 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2133 2133
2134 if ((rinfo->family == CHIP_FAMILY_RS100) || 2134 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2135 (rinfo->family == CHIP_FAMILY_RS200)) { 2135 (rinfo->family == CHIP_FAMILY_RS200)) {
2136 /* This is to workaround the asic bug for RMX, some versions 2136 /* This is to workaround the asic bug for RMX, some versions
2137 of BIOS dosen't have this register initialized correctly. 2137 of BIOS dosen't have this register initialized correctly.
2138 */ 2138 */
2139 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, 2139 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2140 ~CRTC_H_CUTOFF_ACTIVE_EN); 2140 ~CRTC_H_CUTOFF_ACTIVE_EN);
2141 } 2141 }
2142 } else { 2142 } else {
2143 tmp = INREG(CONFIG_MEMSIZE); 2143 tmp = INREG(CONFIG_MEMSIZE);
2144 } 2144 }
2145 2145
2146 /* mem size is bits [28:0], mask off the rest */ 2146 /* mem size is bits [28:0], mask off the rest */
2147 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; 2147 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2148 2148
2149 /* 2149 /*
2150 * Hack to get around some busted production M6's 2150 * Hack to get around some busted production M6's
2151 * reporting no ram 2151 * reporting no ram
2152 */ 2152 */
2153 if (rinfo->video_ram == 0) { 2153 if (rinfo->video_ram == 0) {
2154 switch (rinfo->pdev->device) { 2154 switch (rinfo->pdev->device) {
2155 case PCI_CHIP_RADEON_LY: 2155 case PCI_CHIP_RADEON_LY:
2156 case PCI_CHIP_RADEON_LZ: 2156 case PCI_CHIP_RADEON_LZ:
2157 rinfo->video_ram = 8192 * 1024; 2157 rinfo->video_ram = 8192 * 1024;
2158 break; 2158 break;
2159 default: 2159 default:
2160 break; 2160 break;
2161 } 2161 }
2162 } 2162 }
2163 2163
2164 2164
2165 /* 2165 /*
2166 * Now try to identify VRAM type 2166 * Now try to identify VRAM type
2167 */ 2167 */
2168 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) || 2168 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2169 (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) 2169 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2170 rinfo->vram_ddr = 1; 2170 rinfo->vram_ddr = 1;
2171 else 2171 else
2172 rinfo->vram_ddr = 0; 2172 rinfo->vram_ddr = 0;
2173 2173
2174 tmp = INREG(MEM_CNTL); 2174 tmp = INREG(MEM_CNTL);
2175 if (IS_R300_VARIANT(rinfo)) { 2175 if (IS_R300_VARIANT(rinfo)) {
2176 tmp &= R300_MEM_NUM_CHANNELS_MASK; 2176 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2177 switch (tmp) { 2177 switch (tmp) {
2178 case 0: rinfo->vram_width = 64; break; 2178 case 0: rinfo->vram_width = 64; break;
2179 case 1: rinfo->vram_width = 128; break; 2179 case 1: rinfo->vram_width = 128; break;
2180 case 2: rinfo->vram_width = 256; break; 2180 case 2: rinfo->vram_width = 256; break;
2181 default: rinfo->vram_width = 128; break; 2181 default: rinfo->vram_width = 128; break;
2182 } 2182 }
2183 } else if ((rinfo->family == CHIP_FAMILY_RV100) || 2183 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2184 (rinfo->family == CHIP_FAMILY_RS100) || 2184 (rinfo->family == CHIP_FAMILY_RS100) ||
2185 (rinfo->family == CHIP_FAMILY_RS200)){ 2185 (rinfo->family == CHIP_FAMILY_RS200)){
2186 if (tmp & RV100_MEM_HALF_MODE) 2186 if (tmp & RV100_MEM_HALF_MODE)
2187 rinfo->vram_width = 32; 2187 rinfo->vram_width = 32;
2188 else 2188 else
2189 rinfo->vram_width = 64; 2189 rinfo->vram_width = 64;
2190 } else { 2190 } else {
2191 if (tmp & MEM_NUM_CHANNELS_MASK) 2191 if (tmp & MEM_NUM_CHANNELS_MASK)
2192 rinfo->vram_width = 128; 2192 rinfo->vram_width = 128;
2193 else 2193 else
2194 rinfo->vram_width = 64; 2194 rinfo->vram_width = 64;
2195 } 2195 }
2196 2196
2197 /* This may not be correct, as some cards can have half of channel disabled 2197 /* This may not be correct, as some cards can have half of channel disabled
2198 * ToDo: identify these cases 2198 * ToDo: identify these cases
2199 */ 2199 */
2200 2200
2201 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n", 2201 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2202 pci_name(rinfo->pdev), 2202 pci_name(rinfo->pdev),
2203 rinfo->video_ram / 1024, 2203 rinfo->video_ram / 1024,
2204 rinfo->vram_ddr ? "DDR" : "SDRAM", 2204 rinfo->vram_ddr ? "DDR" : "SDRAM",
2205 rinfo->vram_width); 2205 rinfo->vram_width);
2206 } 2206 }
2207 2207
2208 /* 2208 /*
2209 * Sysfs 2209 * Sysfs
2210 */ 2210 */
2211 2211
2212 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid) 2212 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2213 { 2213 {
2214 if (off > EDID_LENGTH) 2214 if (off > EDID_LENGTH)
2215 return 0; 2215 return 0;
2216 2216
2217 if (off + count > EDID_LENGTH) 2217 if (off + count > EDID_LENGTH)
2218 count = EDID_LENGTH - off; 2218 count = EDID_LENGTH - off;
2219 2219
2220 memcpy(buf, edid + off, count); 2220 memcpy(buf, edid + off, count);
2221 2221
2222 return count; 2222 return count;
2223 } 2223 }
2224 2224
2225 2225
2226 static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count) 2226 static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
2227 { 2227 {
2228 struct device *dev = container_of(kobj, struct device, kobj); 2228 struct device *dev = container_of(kobj, struct device, kobj);
2229 struct pci_dev *pdev = to_pci_dev(dev); 2229 struct pci_dev *pdev = to_pci_dev(dev);
2230 struct fb_info *info = pci_get_drvdata(pdev); 2230 struct fb_info *info = pci_get_drvdata(pdev);
2231 struct radeonfb_info *rinfo = info->par; 2231 struct radeonfb_info *rinfo = info->par;
2232 2232
2233 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID); 2233 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2234 } 2234 }
2235 2235
2236 2236
2237 static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count) 2237 static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
2238 { 2238 {
2239 struct device *dev = container_of(kobj, struct device, kobj); 2239 struct device *dev = container_of(kobj, struct device, kobj);
2240 struct pci_dev *pdev = to_pci_dev(dev); 2240 struct pci_dev *pdev = to_pci_dev(dev);
2241 struct fb_info *info = pci_get_drvdata(pdev); 2241 struct fb_info *info = pci_get_drvdata(pdev);
2242 struct radeonfb_info *rinfo = info->par; 2242 struct radeonfb_info *rinfo = info->par;
2243 2243
2244 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID); 2244 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2245 } 2245 }
2246 2246
2247 static struct bin_attribute edid1_attr = { 2247 static struct bin_attribute edid1_attr = {
2248 .attr = { 2248 .attr = {
2249 .name = "edid1", 2249 .name = "edid1",
2250 .owner = THIS_MODULE, 2250 .owner = THIS_MODULE,
2251 .mode = 0444, 2251 .mode = 0444,
2252 }, 2252 },
2253 .size = EDID_LENGTH, 2253 .size = EDID_LENGTH,
2254 .read = radeon_show_edid1, 2254 .read = radeon_show_edid1,
2255 }; 2255 };
2256 2256
2257 static struct bin_attribute edid2_attr = { 2257 static struct bin_attribute edid2_attr = {
2258 .attr = { 2258 .attr = {
2259 .name = "edid2", 2259 .name = "edid2",
2260 .owner = THIS_MODULE, 2260 .owner = THIS_MODULE,
2261 .mode = 0444, 2261 .mode = 0444,
2262 }, 2262 },
2263 .size = EDID_LENGTH, 2263 .size = EDID_LENGTH,
2264 .read = radeon_show_edid2, 2264 .read = radeon_show_edid2,
2265 }; 2265 };
2266 2266
2267 2267
2268 static int radeonfb_pci_register (struct pci_dev *pdev, 2268 static int radeonfb_pci_register (struct pci_dev *pdev,
2269 const struct pci_device_id *ent) 2269 const struct pci_device_id *ent)
2270 { 2270 {
2271 struct fb_info *info; 2271 struct fb_info *info;
2272 struct radeonfb_info *rinfo; 2272 struct radeonfb_info *rinfo;
2273 int ret; 2273 int ret;
2274 2274
2275 RTRACE("radeonfb_pci_register BEGIN\n"); 2275 RTRACE("radeonfb_pci_register BEGIN\n");
2276 2276
2277 /* Enable device in PCI config */ 2277 /* Enable device in PCI config */
2278 ret = pci_enable_device(pdev); 2278 ret = pci_enable_device(pdev);
2279 if (ret < 0) { 2279 if (ret < 0) {
2280 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n", 2280 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2281 pci_name(pdev)); 2281 pci_name(pdev));
2282 goto err_out; 2282 goto err_out;
2283 } 2283 }
2284 2284
2285 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev); 2285 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2286 if (!info) { 2286 if (!info) {
2287 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n", 2287 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2288 pci_name(pdev)); 2288 pci_name(pdev));
2289 ret = -ENOMEM; 2289 ret = -ENOMEM;
2290 goto err_disable; 2290 goto err_disable;
2291 } 2291 }
2292 rinfo = info->par; 2292 rinfo = info->par;
2293 rinfo->info = info; 2293 rinfo->info = info;
2294 rinfo->pdev = pdev; 2294 rinfo->pdev = pdev;
2295 2295
2296 spin_lock_init(&rinfo->reg_lock); 2296 spin_lock_init(&rinfo->reg_lock);
2297 init_timer(&rinfo->lvds_timer); 2297 init_timer(&rinfo->lvds_timer);
2298 rinfo->lvds_timer.function = radeon_lvds_timer_func; 2298 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2299 rinfo->lvds_timer.data = (unsigned long)rinfo; 2299 rinfo->lvds_timer.data = (unsigned long)rinfo;
2300 2300
2301 strcpy(rinfo->name, "ATI Radeon XX "); 2301 strcpy(rinfo->name, "ATI Radeon XX ");
2302 rinfo->name[11] = ent->device >> 8; 2302 rinfo->name[11] = ent->device >> 8;
2303 rinfo->name[12] = ent->device & 0xFF; 2303 rinfo->name[12] = ent->device & 0xFF;
2304 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK; 2304 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2305 rinfo->chipset = pdev->device; 2305 rinfo->chipset = pdev->device;
2306 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0; 2306 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2307 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0; 2307 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2308 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0; 2308 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2309 2309
2310 /* Set base addrs */ 2310 /* Set base addrs */
2311 rinfo->fb_base_phys = pci_resource_start (pdev, 0); 2311 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2312 rinfo->mmio_base_phys = pci_resource_start (pdev, 2); 2312 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2313 2313
2314 /* request the mem regions */ 2314 /* request the mem regions */
2315 ret = pci_request_region(pdev, 0, "radeonfb framebuffer"); 2315 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2316 if (ret < 0) { 2316 if (ret < 0) {
2317 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n", 2317 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2318 pci_name(rinfo->pdev)); 2318 pci_name(rinfo->pdev));
2319 goto err_release_fb; 2319 goto err_release_fb;
2320 } 2320 }
2321 2321
2322 ret = pci_request_region(pdev, 2, "radeonfb mmio"); 2322 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2323 if (ret < 0) { 2323 if (ret < 0) {
2324 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n", 2324 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2325 pci_name(rinfo->pdev)); 2325 pci_name(rinfo->pdev));
2326 goto err_release_pci0; 2326 goto err_release_pci0;
2327 } 2327 }
2328 2328
2329 /* map the regions */ 2329 /* map the regions */
2330 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE); 2330 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2331 if (!rinfo->mmio_base) { 2331 if (!rinfo->mmio_base) {
2332 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n", 2332 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2333 pci_name(rinfo->pdev)); 2333 pci_name(rinfo->pdev));
2334 ret = -EIO; 2334 ret = -EIO;
2335 goto err_release_pci2; 2335 goto err_release_pci2;
2336 } 2336 }
2337 2337
2338 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; 2338 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2339 2339
2340 /* 2340 /*
2341 * Check for errata 2341 * Check for errata
2342 */ 2342 */
2343 rinfo->errata = 0; 2343 rinfo->errata = 0;
2344 if (rinfo->family == CHIP_FAMILY_R300 && 2344 if (rinfo->family == CHIP_FAMILY_R300 &&
2345 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) 2345 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2346 == CFG_ATI_REV_A11) 2346 == CFG_ATI_REV_A11)
2347 rinfo->errata |= CHIP_ERRATA_R300_CG; 2347 rinfo->errata |= CHIP_ERRATA_R300_CG;
2348 2348
2349 if (rinfo->family == CHIP_FAMILY_RV200 || 2349 if (rinfo->family == CHIP_FAMILY_RV200 ||
2350 rinfo->family == CHIP_FAMILY_RS200) 2350 rinfo->family == CHIP_FAMILY_RS200)
2351 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2351 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2352 2352
2353 if (rinfo->family == CHIP_FAMILY_RV100 || 2353 if (rinfo->family == CHIP_FAMILY_RV100 ||
2354 rinfo->family == CHIP_FAMILY_RS100 || 2354 rinfo->family == CHIP_FAMILY_RS100 ||
2355 rinfo->family == CHIP_FAMILY_RS200) 2355 rinfo->family == CHIP_FAMILY_RS200)
2356 rinfo->errata |= CHIP_ERRATA_PLL_DELAY; 2356 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2357 2357
2358 #ifdef CONFIG_PPC_OF 2358 #ifdef CONFIG_PPC_OF
2359 /* On PPC, we obtain the OF device-node pointer to the firmware 2359 /* On PPC, we obtain the OF device-node pointer to the firmware
2360 * data for this chip 2360 * data for this chip
2361 */ 2361 */
2362 rinfo->of_node = pci_device_to_OF_node(pdev); 2362 rinfo->of_node = pci_device_to_OF_node(pdev);
2363 if (rinfo->of_node == NULL) 2363 if (rinfo->of_node == NULL)
2364 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n", 2364 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2365 pci_name(rinfo->pdev)); 2365 pci_name(rinfo->pdev));
2366 2366
2367 /* On PPC, the firmware sets up a memory mapping that tends 2367 /* On PPC, the firmware sets up a memory mapping that tends
2368 * to cause lockups when enabling the engine. We reconfigure 2368 * to cause lockups when enabling the engine. We reconfigure
2369 * the card internal memory mappings properly 2369 * the card internal memory mappings properly
2370 */ 2370 */
2371 fixup_memory_mappings(rinfo); 2371 fixup_memory_mappings(rinfo);
2372 #endif /* CONFIG_PPC_OF */ 2372 #endif /* CONFIG_PPC_OF */
2373 2373
2374 /* Get VRAM size and type */ 2374 /* Get VRAM size and type */
2375 radeon_identify_vram(rinfo); 2375 radeon_identify_vram(rinfo);
2376 2376
2377 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram); 2377 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2378 2378
2379 do { 2379 do {
2380 rinfo->fb_base = ioremap (rinfo->fb_base_phys, 2380 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2381 rinfo->mapped_vram); 2381 rinfo->mapped_vram);
2382 } while ( rinfo->fb_base == 0 && 2382 } while ( rinfo->fb_base == 0 &&
2383 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) ); 2383 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2384 2384
2385 if (rinfo->fb_base == NULL) { 2385 if (rinfo->fb_base == NULL) {
2386 printk (KERN_ERR "radeonfb (%s): cannot map FB\n", 2386 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2387 pci_name(rinfo->pdev)); 2387 pci_name(rinfo->pdev));
2388 ret = -EIO; 2388 ret = -EIO;
2389 goto err_unmap_rom; 2389 goto err_unmap_rom;
2390 } 2390 }
2391 2391
2392 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev), 2392 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2393 rinfo->mapped_vram/1024); 2393 rinfo->mapped_vram/1024);
2394 2394
2395 /* 2395 /*
2396 * Map the BIOS ROM if any and retrieve PLL parameters from 2396 * Map the BIOS ROM if any and retrieve PLL parameters from
2397 * the BIOS. We skip that on mobility chips as the real panel 2397 * the BIOS. We skip that on mobility chips as the real panel
2398 * values we need aren't in the ROM but in the BIOS image in 2398 * values we need aren't in the ROM but in the BIOS image in
2399 * memory. This is definitely not the best meacnism though, 2399 * memory. This is definitely not the best meacnism though,
2400 * we really need the arch code to tell us which is the "primary" 2400 * we really need the arch code to tell us which is the "primary"
2401 * video adapter to use the memory image (or better, the arch 2401 * video adapter to use the memory image (or better, the arch
2402 * should provide us a copy of the BIOS image to shield us from 2402 * should provide us a copy of the BIOS image to shield us from
2403 * archs who would store that elsewhere and/or could initialize 2403 * archs who would store that elsewhere and/or could initialize
2404 * more than one adapter during boot). 2404 * more than one adapter during boot).
2405 */ 2405 */
2406 if (!rinfo->is_mobility) 2406 if (!rinfo->is_mobility)
2407 radeon_map_ROM(rinfo, pdev); 2407 radeon_map_ROM(rinfo, pdev);
2408 2408
2409 /* 2409 /*
2410 * On x86, the primary display on laptop may have it's BIOS 2410 * On x86, the primary display on laptop may have it's BIOS
2411 * ROM elsewhere, try to locate it at the legacy memory hole. 2411 * ROM elsewhere, try to locate it at the legacy memory hole.
2412 * We probably need to make sure this is the primary display, 2412 * We probably need to make sure this is the primary display,
2413 * but that is difficult without some arch support. 2413 * but that is difficult without some arch support.
2414 */ 2414 */
2415 #ifdef CONFIG_X86 2415 #ifdef CONFIG_X86
2416 if (rinfo->bios_seg == NULL) 2416 if (rinfo->bios_seg == NULL)
2417 radeon_find_mem_vbios(rinfo); 2417 radeon_find_mem_vbios(rinfo);
2418 #endif 2418 #endif
2419 2419
2420 /* If both above failed, try the BIOS ROM again for mobility 2420 /* If both above failed, try the BIOS ROM again for mobility
2421 * chips 2421 * chips
2422 */ 2422 */
2423 if (rinfo->bios_seg == NULL && rinfo->is_mobility) 2423 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2424 radeon_map_ROM(rinfo, pdev); 2424 radeon_map_ROM(rinfo, pdev);
2425 2425
2426 /* Get informations about the board's PLL */ 2426 /* Get informations about the board's PLL */
2427 radeon_get_pllinfo(rinfo); 2427 radeon_get_pllinfo(rinfo);
2428 2428
2429 #ifdef CONFIG_FB_RADEON_I2C 2429 #ifdef CONFIG_FB_RADEON_I2C
2430 /* Register I2C bus */ 2430 /* Register I2C bus */
2431 radeon_create_i2c_busses(rinfo); 2431 radeon_create_i2c_busses(rinfo);
2432 #endif 2432 #endif
2433 2433
2434 /* set all the vital stuff */ 2434 /* set all the vital stuff */
2435 radeon_set_fbinfo (rinfo); 2435 radeon_set_fbinfo (rinfo);
2436 2436
2437 /* Probe screen types */ 2437 /* Probe screen types */
2438 radeon_probe_screens(rinfo, monitor_layout, ignore_edid); 2438 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2439 2439
2440 /* Build mode list, check out panel native model */ 2440 /* Build mode list, check out panel native model */
2441 radeon_check_modes(rinfo, mode_option); 2441 radeon_check_modes(rinfo, mode_option);
2442 2442
2443 /* Register some sysfs stuff (should be done better) */ 2443 /* Register some sysfs stuff (should be done better) */
2444 if (rinfo->mon1_EDID) 2444 if (rinfo->mon1_EDID)
2445 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr); 2445 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2446 if (rinfo->mon2_EDID) 2446 if (rinfo->mon2_EDID)
2447 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr); 2447 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2448 2448
2449 /* save current mode regs before we switch into the new one 2449 /* save current mode regs before we switch into the new one
2450 * so we can restore this upon __exit 2450 * so we can restore this upon __exit
2451 */ 2451 */
2452 radeon_save_state (rinfo, &rinfo->init_state); 2452 radeon_save_state (rinfo, &rinfo->init_state);
2453 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs)); 2453 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2454 2454
2455 /* Setup Power Management capabilities */ 2455 /* Setup Power Management capabilities */
2456 if (default_dynclk < -1) { 2456 if (default_dynclk < -1) {
2457 /* -2 is special: means ON on mobility chips and do not 2457 /* -2 is special: means ON on mobility chips and do not
2458 * change on others 2458 * change on others
2459 */ 2459 */
2460 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1); 2460 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1);
2461 } else 2461 } else
2462 radeonfb_pm_init(rinfo, default_dynclk); 2462 radeonfb_pm_init(rinfo, default_dynclk);
2463 2463
2464 pci_set_drvdata(pdev, info); 2464 pci_set_drvdata(pdev, info);
2465 2465
2466 /* Register with fbdev layer */ 2466 /* Register with fbdev layer */
2467 ret = register_framebuffer(info); 2467 ret = register_framebuffer(info);
2468 if (ret < 0) { 2468 if (ret < 0) {
2469 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n", 2469 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2470 pci_name(rinfo->pdev)); 2470 pci_name(rinfo->pdev));
2471 goto err_unmap_fb; 2471 goto err_unmap_fb;
2472 } 2472 }
2473 2473
2474 #ifdef CONFIG_MTRR 2474 #ifdef CONFIG_MTRR
2475 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys, 2475 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2476 rinfo->video_ram, 2476 rinfo->video_ram,
2477 MTRR_TYPE_WRCOMB, 1); 2477 MTRR_TYPE_WRCOMB, 1);
2478 #endif 2478 #endif
2479 2479
2480 #ifdef CONFIG_PMAC_BACKLIGHT 2480 #ifdef CONFIG_PMAC_BACKLIGHT
2481 if (rinfo->mon1_type == MT_LCD) { 2481 if (rinfo->mon1_type == MT_LCD) {
2482 register_backlight_controller(&radeon_backlight_controller, 2482 register_backlight_controller(&radeon_backlight_controller,
2483 rinfo, "ati"); 2483 rinfo, "ati");
2484 register_backlight_controller(&radeon_backlight_controller, 2484 register_backlight_controller(&radeon_backlight_controller,
2485 rinfo, "mnca"); 2485 rinfo, "mnca");
2486 } 2486 }
2487 #endif 2487 #endif
2488 2488
2489 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name); 2489 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2490 2490
2491 if (rinfo->bios_seg) 2491 if (rinfo->bios_seg)
2492 radeon_unmap_ROM(rinfo, pdev); 2492 radeon_unmap_ROM(rinfo, pdev);
2493 RTRACE("radeonfb_pci_register END\n"); 2493 RTRACE("radeonfb_pci_register END\n");
2494 2494
2495 return 0; 2495 return 0;
2496 err_unmap_fb: 2496 err_unmap_fb:
2497 iounmap(rinfo->fb_base); 2497 iounmap(rinfo->fb_base);
2498 err_unmap_rom: 2498 err_unmap_rom:
2499 kfree(rinfo->mon1_EDID); 2499 kfree(rinfo->mon1_EDID);
2500 kfree(rinfo->mon2_EDID); 2500 kfree(rinfo->mon2_EDID);
2501 if (rinfo->mon1_modedb) 2501 if (rinfo->mon1_modedb)
2502 fb_destroy_modedb(rinfo->mon1_modedb); 2502 fb_destroy_modedb(rinfo->mon1_modedb);
2503 fb_dealloc_cmap(&info->cmap); 2503 fb_dealloc_cmap(&info->cmap);
2504 #ifdef CONFIG_FB_RADEON_I2C 2504 #ifdef CONFIG_FB_RADEON_I2C
2505 radeon_delete_i2c_busses(rinfo); 2505 radeon_delete_i2c_busses(rinfo);
2506 #endif 2506 #endif
2507 if (rinfo->bios_seg) 2507 if (rinfo->bios_seg)
2508 radeon_unmap_ROM(rinfo, pdev); 2508 radeon_unmap_ROM(rinfo, pdev);
2509 iounmap(rinfo->mmio_base); 2509 iounmap(rinfo->mmio_base);
2510 err_release_pci2: 2510 err_release_pci2:
2511 pci_release_region(pdev, 2); 2511 pci_release_region(pdev, 2);
2512 err_release_pci0: 2512 err_release_pci0:
2513 pci_release_region(pdev, 0); 2513 pci_release_region(pdev, 0);
2514 err_release_fb: 2514 err_release_fb:
2515 framebuffer_release(info); 2515 framebuffer_release(info);
2516 err_disable: 2516 err_disable:
2517 pci_disable_device(pdev); 2517 pci_disable_device(pdev);
2518 err_out: 2518 err_out:
2519 return ret; 2519 return ret;
2520 } 2520 }
2521 2521
2522 2522
2523 2523
2524 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev) 2524 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2525 { 2525 {
2526 struct fb_info *info = pci_get_drvdata(pdev); 2526 struct fb_info *info = pci_get_drvdata(pdev);
2527 struct radeonfb_info *rinfo = info->par; 2527 struct radeonfb_info *rinfo = info->par;
2528 2528
2529 if (!rinfo) 2529 if (!rinfo)
2530 return; 2530 return;
2531 2531
2532 radeonfb_pm_exit(rinfo); 2532 radeonfb_pm_exit(rinfo);
2533 2533
2534 if (rinfo->mon1_EDID) 2534 if (rinfo->mon1_EDID)
2535 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr); 2535 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2536 if (rinfo->mon2_EDID) 2536 if (rinfo->mon2_EDID)
2537 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr); 2537 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2538 2538
2539 #if 0 2539 #if 0
2540 /* restore original state 2540 /* restore original state
2541 * 2541 *
2542 * Doesn't quite work yet, I suspect if we come from a legacy 2542 * Doesn't quite work yet, I suspect if we come from a legacy
2543 * VGA mode (or worse, text mode), we need to do some VGA black 2543 * VGA mode (or worse, text mode), we need to do some VGA black
2544 * magic here that I know nothing about. --BenH 2544 * magic here that I know nothing about. --BenH
2545 */ 2545 */
2546 radeon_write_mode (rinfo, &rinfo->init_state, 1); 2546 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2547 #endif 2547 #endif
2548 2548
2549 del_timer_sync(&rinfo->lvds_timer); 2549 del_timer_sync(&rinfo->lvds_timer);
2550 2550
2551 #ifdef CONFIG_MTRR 2551 #ifdef CONFIG_MTRR
2552 if (rinfo->mtrr_hdl >= 0) 2552 if (rinfo->mtrr_hdl >= 0)
2553 mtrr_del(rinfo->mtrr_hdl, 0, 0); 2553 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2554 #endif 2554 #endif
2555 2555
2556 unregister_framebuffer(info); 2556 unregister_framebuffer(info);
2557 2557
2558 iounmap(rinfo->mmio_base); 2558 iounmap(rinfo->mmio_base);
2559 iounmap(rinfo->fb_base); 2559 iounmap(rinfo->fb_base);
2560 2560
2561 pci_release_region(pdev, 2); 2561 pci_release_region(pdev, 2);
2562 pci_release_region(pdev, 0); 2562 pci_release_region(pdev, 0);
2563 2563
2564 kfree(rinfo->mon1_EDID); 2564 kfree(rinfo->mon1_EDID);
2565 kfree(rinfo->mon2_EDID); 2565 kfree(rinfo->mon2_EDID);
2566 if (rinfo->mon1_modedb) 2566 if (rinfo->mon1_modedb)
2567 fb_destroy_modedb(rinfo->mon1_modedb); 2567 fb_destroy_modedb(rinfo->mon1_modedb);
2568 #ifdef CONFIG_FB_RADEON_I2C 2568 #ifdef CONFIG_FB_RADEON_I2C
2569 radeon_delete_i2c_busses(rinfo); 2569 radeon_delete_i2c_busses(rinfo);
2570 #endif 2570 #endif
2571 fb_dealloc_cmap(&info->cmap); 2571 fb_dealloc_cmap(&info->cmap);
2572 framebuffer_release(info); 2572 framebuffer_release(info);
2573 pci_disable_device(pdev); 2573 pci_disable_device(pdev);
2574 } 2574 }
2575 2575
2576 2576
2577 static struct pci_driver radeonfb_driver = { 2577 static struct pci_driver radeonfb_driver = {
2578 .name = "radeonfb", 2578 .name = "radeonfb",
2579 .id_table = radeonfb_pci_table, 2579 .id_table = radeonfb_pci_table,
2580 .probe = radeonfb_pci_register, 2580 .probe = radeonfb_pci_register,
2581 .remove = __devexit_p(radeonfb_pci_unregister), 2581 .remove = __devexit_p(radeonfb_pci_unregister),
2582 #ifdef CONFIG_PM 2582 #ifdef CONFIG_PM
2583 .suspend = radeonfb_pci_suspend, 2583 .suspend = radeonfb_pci_suspend,
2584 .resume = radeonfb_pci_resume, 2584 .resume = radeonfb_pci_resume,
2585 #endif /* CONFIG_PM */ 2585 #endif /* CONFIG_PM */
2586 }; 2586 };
2587 2587
2588 #ifndef MODULE 2588 #ifndef MODULE
2589 static int __init radeonfb_setup (char *options) 2589 static int __init radeonfb_setup (char *options)
2590 { 2590 {
2591 char *this_opt; 2591 char *this_opt;
2592 2592
2593 if (!options || !*options) 2593 if (!options || !*options)
2594 return 0; 2594 return 0;
2595 2595
2596 while ((this_opt = strsep (&options, ",")) != NULL) { 2596 while ((this_opt = strsep (&options, ",")) != NULL) {
2597 if (!*this_opt) 2597 if (!*this_opt)
2598 continue; 2598 continue;
2599 2599
2600 if (!strncmp(this_opt, "noaccel", 7)) { 2600 if (!strncmp(this_opt, "noaccel", 7)) {
2601 noaccel = 1; 2601 noaccel = 1;
2602 } else if (!strncmp(this_opt, "mirror", 6)) { 2602 } else if (!strncmp(this_opt, "mirror", 6)) {
2603 mirror = 1; 2603 mirror = 1;
2604 } else if (!strncmp(this_opt, "force_dfp", 9)) { 2604 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2605 force_dfp = 1; 2605 force_dfp = 1;
2606 } else if (!strncmp(this_opt, "panel_yres:", 11)) { 2606 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2607 panel_yres = simple_strtoul((this_opt+11), NULL, 0); 2607 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2608 #ifdef CONFIG_MTRR 2608 #ifdef CONFIG_MTRR
2609 } else if (!strncmp(this_opt, "nomtrr", 6)) { 2609 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2610 nomtrr = 1; 2610 nomtrr = 1;
2611 #endif 2611 #endif
2612 } else if (!strncmp(this_opt, "nomodeset", 9)) { 2612 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2613 nomodeset = 1; 2613 nomodeset = 1;
2614 } else if (!strncmp(this_opt, "force_measure_pll", 17)) { 2614 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2615 force_measure_pll = 1; 2615 force_measure_pll = 1;
2616 } else if (!strncmp(this_opt, "ignore_edid", 11)) { 2616 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2617 ignore_edid = 1; 2617 ignore_edid = 1;
2618 } else 2618 } else
2619 mode_option = this_opt; 2619 mode_option = this_opt;
2620 } 2620 }
2621 return 0; 2621 return 0;
2622 } 2622 }
2623 #endif /* MODULE */ 2623 #endif /* MODULE */
2624 2624
2625 static int __init radeonfb_init (void) 2625 static int __init radeonfb_init (void)
2626 { 2626 {
2627 #ifndef MODULE 2627 #ifndef MODULE
2628 char *option = NULL; 2628 char *option = NULL;
2629 2629
2630 if (fb_get_options("radeonfb", &option)) 2630 if (fb_get_options("radeonfb", &option))
2631 return -ENODEV; 2631 return -ENODEV;
2632 radeonfb_setup(option); 2632 radeonfb_setup(option);
2633 #endif 2633 #endif
2634 return pci_register_driver (&radeonfb_driver); 2634 return pci_register_driver (&radeonfb_driver);
2635 } 2635 }
2636 2636
2637 2637
2638 static void __exit radeonfb_exit (void) 2638 static void __exit radeonfb_exit (void)
2639 { 2639 {
2640 pci_unregister_driver (&radeonfb_driver); 2640 pci_unregister_driver (&radeonfb_driver);
2641 } 2641 }
2642 2642
2643 module_init(radeonfb_init); 2643 module_init(radeonfb_init);
2644 module_exit(radeonfb_exit); 2644 module_exit(radeonfb_exit);
2645 2645
2646 MODULE_AUTHOR("Ani Joshi"); 2646 MODULE_AUTHOR("Ani Joshi");
2647 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset"); 2647 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2648 MODULE_LICENSE("GPL"); 2648 MODULE_LICENSE("GPL");
2649 module_param(noaccel, bool, 0); 2649 module_param(noaccel, bool, 0);
2650 module_param(default_dynclk, int, 0); 2650 module_param(default_dynclk, int, 0);
2651 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on"); 2651 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2652 MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); 2652 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2653 module_param(nomodeset, bool, 0); 2653 module_param(nomodeset, bool, 0);
2654 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode"); 2654 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2655 module_param(mirror, bool, 0); 2655 module_param(mirror, bool, 0);
2656 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors"); 2656 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2657 module_param(force_dfp, bool, 0); 2657 module_param(force_dfp, bool, 0);
2658 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp"); 2658 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2659 module_param(ignore_edid, bool, 0); 2659 module_param(ignore_edid, bool, 0);
2660 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe"); 2660 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2661 module_param(monitor_layout, charp, 0); 2661 module_param(monitor_layout, charp, 0);
2662 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)"); 2662 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2663 module_param(force_measure_pll, bool, 0); 2663 module_param(force_measure_pll, bool, 0);
2664 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)"); 2664 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2665 #ifdef CONFIG_MTRR 2665 #ifdef CONFIG_MTRR
2666 module_param(nomtrr, bool, 0); 2666 module_param(nomtrr, bool, 0);
2667 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers"); 2667 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2668 #endif 2668 #endif
2669 module_param(panel_yres, int, 0); 2669 module_param(panel_yres, int, 0);
2670 MODULE_PARM_DESC(panel_yres, "int: set panel yres"); 2670 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2671 module_param(mode_option, charp, 0); 2671 module_param(mode_option, charp, 0);
2672 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); 2672 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2673 2673
drivers/video/fbcmap.c
1 /* 1 /*
2 * linux/drivers/video/fbcmap.c -- Colormap handling for frame buffer devices 2 * linux/drivers/video/fbcmap.c -- Colormap handling for frame buffer devices
3 * 3 *
4 * Created 15 Jun 1997 by Geert Uytterhoeven 4 * Created 15 Jun 1997 by Geert Uytterhoeven
5 * 5 *
6 * 2001 - Documented with DocBook 6 * 2001 - Documented with DocBook
7 * - Brad Douglas <brad@neruo.com> 7 * - Brad Douglas <brad@neruo.com>
8 * 8 *
9 * This file is subject to the terms and conditions of the GNU General Public 9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for 10 * License. See the file COPYING in the main directory of this archive for
11 * more details. 11 * more details.
12 */ 12 */
13 13
14 #include <linux/string.h> 14 #include <linux/string.h>
15 #include <linux/module.h> 15 #include <linux/module.h>
16 #include <linux/tty.h> 16 #include <linux/tty.h>
17 #include <linux/fb.h> 17 #include <linux/fb.h>
18 #include <linux/slab.h> 18 #include <linux/slab.h>
19 19
20 #include <asm/uaccess.h> 20 #include <asm/uaccess.h>
21 21
22 static u16 red2[] = { 22 static u16 red2[] = {
23 0x0000, 0xaaaa 23 0x0000, 0xaaaa
24 }; 24 };
25 static u16 green2[] = { 25 static u16 green2[] = {
26 0x0000, 0xaaaa 26 0x0000, 0xaaaa
27 }; 27 };
28 static u16 blue2[] = { 28 static u16 blue2[] = {
29 0x0000, 0xaaaa 29 0x0000, 0xaaaa
30 }; 30 };
31 31
32 static u16 red4[] = { 32 static u16 red4[] = {
33 0x0000, 0xaaaa, 0x5555, 0xffff 33 0x0000, 0xaaaa, 0x5555, 0xffff
34 }; 34 };
35 static u16 green4[] = { 35 static u16 green4[] = {
36 0x0000, 0xaaaa, 0x5555, 0xffff 36 0x0000, 0xaaaa, 0x5555, 0xffff
37 }; 37 };
38 static u16 blue4[] = { 38 static u16 blue4[] = {
39 0x0000, 0xaaaa, 0x5555, 0xffff 39 0x0000, 0xaaaa, 0x5555, 0xffff
40 }; 40 };
41 41
42 static u16 red8[] = { 42 static u16 red8[] = {
43 0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa 43 0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa
44 }; 44 };
45 static u16 green8[] = { 45 static u16 green8[] = {
46 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa 46 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa
47 }; 47 };
48 static u16 blue8[] = { 48 static u16 blue8[] = {
49 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa 49 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa
50 }; 50 };
51 51
52 static u16 red16[] = { 52 static u16 red16[] = {
53 0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 53 0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
54 0x5555, 0x5555, 0x5555, 0x5555, 0xffff, 0xffff, 0xffff, 0xffff 54 0x5555, 0x5555, 0x5555, 0x5555, 0xffff, 0xffff, 0xffff, 0xffff
55 }; 55 };
56 static u16 green16[] = { 56 static u16 green16[] = {
57 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa, 57 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa,
58 0x5555, 0x5555, 0xffff, 0xffff, 0x5555, 0x5555, 0xffff, 0xffff 58 0x5555, 0x5555, 0xffff, 0xffff, 0x5555, 0x5555, 0xffff, 0xffff
59 }; 59 };
60 static u16 blue16[] = { 60 static u16 blue16[] = {
61 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 61 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa,
62 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff 62 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff
63 }; 63 };
64 64
65 static struct fb_cmap default_2_colors = { 65 static struct fb_cmap default_2_colors = {
66 0, 2, red2, green2, blue2, NULL 66 0, 2, red2, green2, blue2, NULL
67 }; 67 };
68 static struct fb_cmap default_8_colors = { 68 static struct fb_cmap default_8_colors = {
69 0, 8, red8, green8, blue8, NULL 69 0, 8, red8, green8, blue8, NULL
70 }; 70 };
71 static struct fb_cmap default_4_colors = { 71 static struct fb_cmap default_4_colors = {
72 0, 4, red4, green4, blue4, NULL 72 0, 4, red4, green4, blue4, NULL
73 }; 73 };
74 static struct fb_cmap default_16_colors = { 74 static struct fb_cmap default_16_colors = {
75 0, 16, red16, green16, blue16, NULL 75 0, 16, red16, green16, blue16, NULL
76 }; 76 };
77 77
78 78
79 /** 79 /**
80 * fb_alloc_cmap - allocate a colormap 80 * fb_alloc_cmap - allocate a colormap
81 * @cmap: frame buffer colormap structure 81 * @cmap: frame buffer colormap structure
82 * @len: length of @cmap 82 * @len: length of @cmap
83 * @transp: boolean, 1 if there is transparency, 0 otherwise 83 * @transp: boolean, 1 if there is transparency, 0 otherwise
84 * 84 *
85 * Allocates memory for a colormap @cmap. @len is the 85 * Allocates memory for a colormap @cmap. @len is the
86 * number of entries in the palette. 86 * number of entries in the palette.
87 * 87 *
88 * Returns -1 errno on error, or zero on success. 88 * Returns negative errno on error, or zero on success.
89 * 89 *
90 */ 90 */
91 91
92 int fb_alloc_cmap(struct fb_cmap *cmap, int len, int transp) 92 int fb_alloc_cmap(struct fb_cmap *cmap, int len, int transp)
93 { 93 {
94 int size = len*sizeof(u16); 94 int size = len*sizeof(u16);
95 95
96 if (cmap->len != len) { 96 if (cmap->len != len) {
97 fb_dealloc_cmap(cmap); 97 fb_dealloc_cmap(cmap);
98 if (!len) 98 if (!len)
99 return 0; 99 return 0;
100 if (!(cmap->red = kmalloc(size, GFP_ATOMIC))) 100 if (!(cmap->red = kmalloc(size, GFP_ATOMIC)))
101 goto fail; 101 goto fail;
102 if (!(cmap->green = kmalloc(size, GFP_ATOMIC))) 102 if (!(cmap->green = kmalloc(size, GFP_ATOMIC)))
103 goto fail; 103 goto fail;
104 if (!(cmap->blue = kmalloc(size, GFP_ATOMIC))) 104 if (!(cmap->blue = kmalloc(size, GFP_ATOMIC)))
105 goto fail; 105 goto fail;
106 if (transp) { 106 if (transp) {
107 if (!(cmap->transp = kmalloc(size, GFP_ATOMIC))) 107 if (!(cmap->transp = kmalloc(size, GFP_ATOMIC)))
108 goto fail; 108 goto fail;
109 } else 109 } else
110 cmap->transp = NULL; 110 cmap->transp = NULL;
111 } 111 }
112 cmap->start = 0; 112 cmap->start = 0;
113 cmap->len = len; 113 cmap->len = len;
114 fb_copy_cmap(fb_default_cmap(len), cmap); 114 fb_copy_cmap(fb_default_cmap(len), cmap);
115 return 0; 115 return 0;
116 116
117 fail: 117 fail:
118 fb_dealloc_cmap(cmap); 118 fb_dealloc_cmap(cmap);
119 return -1; 119 return -ENOMEM;
120 } 120 }
121 121
122 /** 122 /**
123 * fb_dealloc_cmap - deallocate a colormap 123 * fb_dealloc_cmap - deallocate a colormap
124 * @cmap: frame buffer colormap structure 124 * @cmap: frame buffer colormap structure
125 * 125 *
126 * Deallocates a colormap that was previously allocated with 126 * Deallocates a colormap that was previously allocated with
127 * fb_alloc_cmap(). 127 * fb_alloc_cmap().
128 * 128 *
129 */ 129 */
130 130
131 void fb_dealloc_cmap(struct fb_cmap *cmap) 131 void fb_dealloc_cmap(struct fb_cmap *cmap)
132 { 132 {
133 kfree(cmap->red); 133 kfree(cmap->red);
134 kfree(cmap->green); 134 kfree(cmap->green);
135 kfree(cmap->blue); 135 kfree(cmap->blue);
136 kfree(cmap->transp); 136 kfree(cmap->transp);
137 137
138 cmap->red = cmap->green = cmap->blue = cmap->transp = NULL; 138 cmap->red = cmap->green = cmap->blue = cmap->transp = NULL;
139 cmap->len = 0; 139 cmap->len = 0;
140 } 140 }
141 141
142 /** 142 /**
143 * fb_copy_cmap - copy a colormap 143 * fb_copy_cmap - copy a colormap
144 * @from: frame buffer colormap structure 144 * @from: frame buffer colormap structure
145 * @to: frame buffer colormap structure 145 * @to: frame buffer colormap structure
146 * 146 *
147 * Copy contents of colormap from @from to @to. 147 * Copy contents of colormap from @from to @to.
148 */ 148 */
149 149
150 int fb_copy_cmap(struct fb_cmap *from, struct fb_cmap *to) 150 int fb_copy_cmap(struct fb_cmap *from, struct fb_cmap *to)
151 { 151 {
152 int tooff = 0, fromoff = 0; 152 int tooff = 0, fromoff = 0;
153 int size; 153 int size;
154 154
155 if (to->start > from->start) 155 if (to->start > from->start)
156 fromoff = to->start - from->start; 156 fromoff = to->start - from->start;
157 else 157 else
158 tooff = from->start - to->start; 158 tooff = from->start - to->start;
159 size = to->len - tooff; 159 size = to->len - tooff;
160 if (size > (int) (from->len - fromoff)) 160 if (size > (int) (from->len - fromoff))
161 size = from->len - fromoff; 161 size = from->len - fromoff;
162 if (size <= 0) 162 if (size <= 0)
163 return -EINVAL; 163 return -EINVAL;
164 size *= sizeof(u16); 164 size *= sizeof(u16);
165 165
166 memcpy(to->red+tooff, from->red+fromoff, size); 166 memcpy(to->red+tooff, from->red+fromoff, size);
167 memcpy(to->green+tooff, from->green+fromoff, size); 167 memcpy(to->green+tooff, from->green+fromoff, size);
168 memcpy(to->blue+tooff, from->blue+fromoff, size); 168 memcpy(to->blue+tooff, from->blue+fromoff, size);
169 if (from->transp && to->transp) 169 if (from->transp && to->transp)
170 memcpy(to->transp+tooff, from->transp+fromoff, size); 170 memcpy(to->transp+tooff, from->transp+fromoff, size);
171 return 0; 171 return 0;
172 } 172 }
173 173
174 int fb_cmap_to_user(struct fb_cmap *from, struct fb_cmap_user *to) 174 int fb_cmap_to_user(struct fb_cmap *from, struct fb_cmap_user *to)
175 { 175 {
176 int tooff = 0, fromoff = 0; 176 int tooff = 0, fromoff = 0;
177 int size; 177 int size;
178 178
179 if (to->start > from->start) 179 if (to->start > from->start)
180 fromoff = to->start - from->start; 180 fromoff = to->start - from->start;
181 else 181 else
182 tooff = from->start - to->start; 182 tooff = from->start - to->start;
183 size = to->len - tooff; 183 size = to->len - tooff;
184 if (size > (int) (from->len - fromoff)) 184 if (size > (int) (from->len - fromoff))
185 size = from->len - fromoff; 185 size = from->len - fromoff;
186 if (size <= 0) 186 if (size <= 0)
187 return -EINVAL; 187 return -EINVAL;
188 size *= sizeof(u16); 188 size *= sizeof(u16);
189 189
190 if (copy_to_user(to->red+tooff, from->red+fromoff, size)) 190 if (copy_to_user(to->red+tooff, from->red+fromoff, size))
191 return -EFAULT; 191 return -EFAULT;
192 if (copy_to_user(to->green+tooff, from->green+fromoff, size)) 192 if (copy_to_user(to->green+tooff, from->green+fromoff, size))
193 return -EFAULT; 193 return -EFAULT;
194 if (copy_to_user(to->blue+tooff, from->blue+fromoff, size)) 194 if (copy_to_user(to->blue+tooff, from->blue+fromoff, size))
195 return -EFAULT; 195 return -EFAULT;
196 if (from->transp && to->transp) 196 if (from->transp && to->transp)
197 if (copy_to_user(to->transp+tooff, from->transp+fromoff, size)) 197 if (copy_to_user(to->transp+tooff, from->transp+fromoff, size))
198 return -EFAULT; 198 return -EFAULT;
199 return 0; 199 return 0;
200 } 200 }
201 201
202 /** 202 /**
203 * fb_set_cmap - set the colormap 203 * fb_set_cmap - set the colormap
204 * @cmap: frame buffer colormap structure 204 * @cmap: frame buffer colormap structure
205 * @info: frame buffer info structure 205 * @info: frame buffer info structure
206 * 206 *
207 * Sets the colormap @cmap for a screen of device @info. 207 * Sets the colormap @cmap for a screen of device @info.
208 * 208 *
209 * Returns negative errno on error, or zero on success. 209 * Returns negative errno on error, or zero on success.
210 * 210 *
211 */ 211 */
212 212
213 int fb_set_cmap(struct fb_cmap *cmap, struct fb_info *info) 213 int fb_set_cmap(struct fb_cmap *cmap, struct fb_info *info)
214 { 214 {
215 int i, start, rc = 0; 215 int i, start, rc = 0;
216 u16 *red, *green, *blue, *transp; 216 u16 *red, *green, *blue, *transp;
217 u_int hred, hgreen, hblue, htransp = 0xffff; 217 u_int hred, hgreen, hblue, htransp = 0xffff;
218 218
219 red = cmap->red; 219 red = cmap->red;
220 green = cmap->green; 220 green = cmap->green;
221 blue = cmap->blue; 221 blue = cmap->blue;
222 transp = cmap->transp; 222 transp = cmap->transp;
223 start = cmap->start; 223 start = cmap->start;
224 224
225 if (start < 0 || (!info->fbops->fb_setcolreg && 225 if (start < 0 || (!info->fbops->fb_setcolreg &&
226 !info->fbops->fb_setcmap)) 226 !info->fbops->fb_setcmap))
227 return -EINVAL; 227 return -EINVAL;
228 if (info->fbops->fb_setcmap) { 228 if (info->fbops->fb_setcmap) {
229 rc = info->fbops->fb_setcmap(cmap, info); 229 rc = info->fbops->fb_setcmap(cmap, info);
230 } else { 230 } else {
231 for (i = 0; i < cmap->len; i++) { 231 for (i = 0; i < cmap->len; i++) {
232 hred = *red++; 232 hred = *red++;
233 hgreen = *green++; 233 hgreen = *green++;
234 hblue = *blue++; 234 hblue = *blue++;
235 if (transp) 235 if (transp)
236 htransp = *transp++; 236 htransp = *transp++;
237 if (info->fbops->fb_setcolreg(start++, 237 if (info->fbops->fb_setcolreg(start++,
238 hred, hgreen, hblue, 238 hred, hgreen, hblue,
239 htransp, info)) 239 htransp, info))
240 break; 240 break;
241 } 241 }
242 } 242 }
243 if (rc == 0) 243 if (rc == 0)
244 fb_copy_cmap(cmap, &info->cmap); 244 fb_copy_cmap(cmap, &info->cmap);
245 245
246 return rc; 246 return rc;
247 } 247 }
248 248
249 int fb_set_user_cmap(struct fb_cmap_user *cmap, struct fb_info *info) 249 int fb_set_user_cmap(struct fb_cmap_user *cmap, struct fb_info *info)
250 { 250 {
251 int rc, size = cmap->len * sizeof(u16); 251 int rc, size = cmap->len * sizeof(u16);
252 struct fb_cmap umap; 252 struct fb_cmap umap;
253 253
254 if (cmap->start < 0 || (!info->fbops->fb_setcolreg && 254 if (cmap->start < 0 || (!info->fbops->fb_setcolreg &&
255 !info->fbops->fb_setcmap)) 255 !info->fbops->fb_setcmap))
256 return -EINVAL; 256 return -EINVAL;
257 257
258 memset(&umap, 0, sizeof(struct fb_cmap)); 258 memset(&umap, 0, sizeof(struct fb_cmap));
259 rc = fb_alloc_cmap(&umap, cmap->len, cmap->transp != NULL); 259 rc = fb_alloc_cmap(&umap, cmap->len, cmap->transp != NULL);
260 if (rc) 260 if (rc)
261 return rc; 261 return rc;
262 if (copy_from_user(umap.red, cmap->red, size) || 262 if (copy_from_user(umap.red, cmap->red, size) ||
263 copy_from_user(umap.green, cmap->green, size) || 263 copy_from_user(umap.green, cmap->green, size) ||
264 copy_from_user(umap.blue, cmap->blue, size) || 264 copy_from_user(umap.blue, cmap->blue, size) ||
265 (cmap->transp && copy_from_user(umap.transp, cmap->transp, size))) { 265 (cmap->transp && copy_from_user(umap.transp, cmap->transp, size))) {
266 fb_dealloc_cmap(&umap); 266 fb_dealloc_cmap(&umap);
267 return -EFAULT; 267 return -EFAULT;
268 } 268 }
269 umap.start = cmap->start; 269 umap.start = cmap->start;
270 rc = fb_set_cmap(&umap, info); 270 rc = fb_set_cmap(&umap, info);
271 fb_dealloc_cmap(&umap); 271 fb_dealloc_cmap(&umap);
272 return rc; 272 return rc;
273 } 273 }
274 274
275 /** 275 /**
276 * fb_default_cmap - get default colormap 276 * fb_default_cmap - get default colormap
277 * @len: size of palette for a depth 277 * @len: size of palette for a depth
278 * 278 *
279 * Gets the default colormap for a specific screen depth. @len 279 * Gets the default colormap for a specific screen depth. @len
280 * is the size of the palette for a particular screen depth. 280 * is the size of the palette for a particular screen depth.
281 * 281 *
282 * Returns pointer to a frame buffer colormap structure. 282 * Returns pointer to a frame buffer colormap structure.
283 * 283 *
284 */ 284 */
285 285
286 struct fb_cmap *fb_default_cmap(int len) 286 struct fb_cmap *fb_default_cmap(int len)
287 { 287 {
288 if (len <= 2) 288 if (len <= 2)
289 return &default_2_colors; 289 return &default_2_colors;
290 if (len <= 4) 290 if (len <= 4)
291 return &default_4_colors; 291 return &default_4_colors;
292 if (len <= 8) 292 if (len <= 8)
293 return &default_8_colors; 293 return &default_8_colors;
294 return &default_16_colors; 294 return &default_16_colors;
295 } 295 }
296 296
297 297
298 /** 298 /**
299 * fb_invert_cmaps - invert all defaults colormaps 299 * fb_invert_cmaps - invert all defaults colormaps
300 * 300 *
301 * Invert all default colormaps. 301 * Invert all default colormaps.
302 * 302 *
303 */ 303 */
304 304
305 void fb_invert_cmaps(void) 305 void fb_invert_cmaps(void)
306 { 306 {
307 u_int i; 307 u_int i;
308 308
309 for (i = 0; i < 2; i++) { 309 for (i = 0; i < 2; i++) {
310 red2[i] = ~red2[i]; 310 red2[i] = ~red2[i];
311 green2[i] = ~green2[i]; 311 green2[i] = ~green2[i];
312 blue2[i] = ~blue2[i]; 312 blue2[i] = ~blue2[i];
313 } 313 }
314 for (i = 0; i < 4; i++) { 314 for (i = 0; i < 4; i++) {
315 red4[i] = ~red4[i]; 315 red4[i] = ~red4[i];
316 green4[i] = ~green4[i]; 316 green4[i] = ~green4[i];
317 blue4[i] = ~blue4[i]; 317 blue4[i] = ~blue4[i];
318 } 318 }
319 for (i = 0; i < 8; i++) { 319 for (i = 0; i < 8; i++) {
320 red8[i] = ~red8[i]; 320 red8[i] = ~red8[i];
321 green8[i] = ~green8[i]; 321 green8[i] = ~green8[i];
322 blue8[i] = ~blue8[i]; 322 blue8[i] = ~blue8[i];
323 } 323 }
324 for (i = 0; i < 16; i++) { 324 for (i = 0; i < 16; i++) {
325 red16[i] = ~red16[i]; 325 red16[i] = ~red16[i];
326 green16[i] = ~green16[i]; 326 green16[i] = ~green16[i];
327 blue16[i] = ~blue16[i]; 327 blue16[i] = ~blue16[i];
328 } 328 }
329 } 329 }
330 330
331 331
332 /* 332 /*
333 * Visible symbols for modules 333 * Visible symbols for modules
334 */ 334 */
335 335
336 EXPORT_SYMBOL(fb_alloc_cmap); 336 EXPORT_SYMBOL(fb_alloc_cmap);
337 EXPORT_SYMBOL(fb_dealloc_cmap); 337 EXPORT_SYMBOL(fb_dealloc_cmap);
338 EXPORT_SYMBOL(fb_copy_cmap); 338 EXPORT_SYMBOL(fb_copy_cmap);
339 EXPORT_SYMBOL(fb_set_cmap); 339 EXPORT_SYMBOL(fb_set_cmap);
340 EXPORT_SYMBOL(fb_default_cmap); 340 EXPORT_SYMBOL(fb_default_cmap);
341 EXPORT_SYMBOL(fb_invert_cmaps); 341 EXPORT_SYMBOL(fb_invert_cmaps);
342 342
drivers/video/fbsysfs.c
1 /* 1 /*
2 * fbsysfs.c - framebuffer device class and attributes 2 * fbsysfs.c - framebuffer device class and attributes
3 * 3 *
4 * Copyright (c) 2004 James Simmons <jsimmons@infradead.org> 4 * Copyright (c) 2004 James Simmons <jsimmons@infradead.org>
5 * 5 *
6 * This program is free software you can redistribute it and/or 6 * This program is free software you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License 7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11 11
12 /* 12 /*
13 * Note: currently there's only stubs for framebuffer_alloc and 13 * Note: currently there's only stubs for framebuffer_alloc and
14 * framebuffer_release here. The reson for that is that until all drivers 14 * framebuffer_release here. The reson for that is that until all drivers
15 * are converted to use it a sysfsification will open OOPSable races. 15 * are converted to use it a sysfsification will open OOPSable races.
16 */ 16 */
17 17
18 #include <linux/kernel.h> 18 #include <linux/kernel.h>
19 #include <linux/fb.h> 19 #include <linux/fb.h>
20 #include <linux/console.h> 20 #include <linux/console.h>
21 21
22 /** 22 /**
23 * framebuffer_alloc - creates a new frame buffer info structure 23 * framebuffer_alloc - creates a new frame buffer info structure
24 * 24 *
25 * @size: size of driver private data, can be zero 25 * @size: size of driver private data, can be zero
26 * @dev: pointer to the device for this fb, this can be NULL 26 * @dev: pointer to the device for this fb, this can be NULL
27 * 27 *
28 * Creates a new frame buffer info structure. Also reserves @size bytes 28 * Creates a new frame buffer info structure. Also reserves @size bytes
29 * for driver private data (info->par). info->par (if any) will be 29 * for driver private data (info->par). info->par (if any) will be
30 * aligned to sizeof(long). 30 * aligned to sizeof(long).
31 * 31 *
32 * Returns the new structure, or NULL if an error occured. 32 * Returns the new structure, or NULL if an error occured.
33 * 33 *
34 */ 34 */
35 struct fb_info *framebuffer_alloc(size_t size, struct device *dev) 35 struct fb_info *framebuffer_alloc(size_t size, struct device *dev)
36 { 36 {
37 #define BYTES_PER_LONG (BITS_PER_LONG/8) 37 #define BYTES_PER_LONG (BITS_PER_LONG/8)
38 #define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG)) 38 #define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG))
39 int fb_info_size = sizeof(struct fb_info); 39 int fb_info_size = sizeof(struct fb_info);
40 struct fb_info *info; 40 struct fb_info *info;
41 char *p; 41 char *p;
42 42
43 if (size) 43 if (size)
44 fb_info_size += PADDING; 44 fb_info_size += PADDING;
45 45
46 p = kzalloc(fb_info_size + size, GFP_KERNEL); 46 p = kzalloc(fb_info_size + size, GFP_KERNEL);
47 47
48 if (!p) 48 if (!p)
49 return NULL; 49 return NULL;
50 50
51 info = (struct fb_info *) p; 51 info = (struct fb_info *) p;
52 52
53 if (size) 53 if (size)
54 info->par = p + fb_info_size; 54 info->par = p + fb_info_size;
55 55
56 info->device = dev; 56 info->device = dev;
57 57
58 return info; 58 return info;
59 #undef PADDING 59 #undef PADDING
60 #undef BYTES_PER_LONG 60 #undef BYTES_PER_LONG
61 } 61 }
62 EXPORT_SYMBOL(framebuffer_alloc); 62 EXPORT_SYMBOL(framebuffer_alloc);
63 63
64 /** 64 /**
65 * framebuffer_release - marks the structure available for freeing 65 * framebuffer_release - marks the structure available for freeing
66 * 66 *
67 * @info: frame buffer info structure 67 * @info: frame buffer info structure
68 * 68 *
69 * Drop the reference count of the class_device embedded in the 69 * Drop the reference count of the class_device embedded in the
70 * framebuffer info structure. 70 * framebuffer info structure.
71 * 71 *
72 */ 72 */
73 void framebuffer_release(struct fb_info *info) 73 void framebuffer_release(struct fb_info *info)
74 { 74 {
75 kfree(info); 75 kfree(info);
76 } 76 }
77 EXPORT_SYMBOL(framebuffer_release); 77 EXPORT_SYMBOL(framebuffer_release);
78 78
79 static int activate(struct fb_info *fb_info, struct fb_var_screeninfo *var) 79 static int activate(struct fb_info *fb_info, struct fb_var_screeninfo *var)
80 { 80 {
81 int err; 81 int err;
82 82
83 var->activate |= FB_ACTIVATE_FORCE; 83 var->activate |= FB_ACTIVATE_FORCE;
84 acquire_console_sem(); 84 acquire_console_sem();
85 fb_info->flags |= FBINFO_MISC_USEREVENT; 85 fb_info->flags |= FBINFO_MISC_USEREVENT;
86 err = fb_set_var(fb_info, var); 86 err = fb_set_var(fb_info, var);
87 fb_info->flags &= ~FBINFO_MISC_USEREVENT; 87 fb_info->flags &= ~FBINFO_MISC_USEREVENT;
88 release_console_sem(); 88 release_console_sem();
89 if (err) 89 if (err)
90 return err; 90 return err;
91 return 0; 91 return 0;
92 } 92 }
93 93
94 static int mode_string(char *buf, unsigned int offset, 94 static int mode_string(char *buf, unsigned int offset,
95 const struct fb_videomode *mode) 95 const struct fb_videomode *mode)
96 { 96 {
97 char m = 'U'; 97 char m = 'U';
98 if (mode->flag & FB_MODE_IS_DETAILED) 98 if (mode->flag & FB_MODE_IS_DETAILED)
99 m = 'D'; 99 m = 'D';
100 if (mode->flag & FB_MODE_IS_VESA) 100 if (mode->flag & FB_MODE_IS_VESA)
101 m = 'V'; 101 m = 'V';
102 if (mode->flag & FB_MODE_IS_STANDARD) 102 if (mode->flag & FB_MODE_IS_STANDARD)
103 m = 'S'; 103 m = 'S';
104 return snprintf(&buf[offset], PAGE_SIZE - offset, "%c:%dx%d-%d\n", m, mode->xres, mode->yres, mode->refresh); 104 return snprintf(&buf[offset], PAGE_SIZE - offset, "%c:%dx%d-%d\n", m, mode->xres, mode->yres, mode->refresh);
105 } 105 }
106 106
107 static ssize_t store_mode(struct class_device *class_device, const char * buf, 107 static ssize_t store_mode(struct class_device *class_device, const char * buf,
108 size_t count) 108 size_t count)
109 { 109 {
110 struct fb_info *fb_info = class_get_devdata(class_device); 110 struct fb_info *fb_info = class_get_devdata(class_device);
111 char mstr[100]; 111 char mstr[100];
112 struct fb_var_screeninfo var; 112 struct fb_var_screeninfo var;
113 struct fb_modelist *modelist; 113 struct fb_modelist *modelist;
114 struct fb_videomode *mode; 114 struct fb_videomode *mode;
115 struct list_head *pos; 115 struct list_head *pos;
116 size_t i; 116 size_t i;
117 int err; 117 int err;
118 118
119 memset(&var, 0, sizeof(var)); 119 memset(&var, 0, sizeof(var));
120 120
121 list_for_each(pos, &fb_info->modelist) { 121 list_for_each(pos, &fb_info->modelist) {
122 modelist = list_entry(pos, struct fb_modelist, list); 122 modelist = list_entry(pos, struct fb_modelist, list);
123 mode = &modelist->mode; 123 mode = &modelist->mode;
124 i = mode_string(mstr, 0, mode); 124 i = mode_string(mstr, 0, mode);
125 if (strncmp(mstr, buf, max(count, i)) == 0) { 125 if (strncmp(mstr, buf, max(count, i)) == 0) {
126 126
127 var = fb_info->var; 127 var = fb_info->var;
128 fb_videomode_to_var(&var, mode); 128 fb_videomode_to_var(&var, mode);
129 if ((err = activate(fb_info, &var))) 129 if ((err = activate(fb_info, &var)))
130 return err; 130 return err;
131 fb_info->mode = mode; 131 fb_info->mode = mode;
132 return count; 132 return count;
133 } 133 }
134 } 134 }
135 return -EINVAL; 135 return -EINVAL;
136 } 136 }
137 137
138 static ssize_t show_mode(struct class_device *class_device, char *buf) 138 static ssize_t show_mode(struct class_device *class_device, char *buf)
139 { 139 {
140 struct fb_info *fb_info = class_get_devdata(class_device); 140 struct fb_info *fb_info = class_get_devdata(class_device);
141 141
142 if (!fb_info->mode) 142 if (!fb_info->mode)
143 return 0; 143 return 0;
144 144
145 return mode_string(buf, 0, fb_info->mode); 145 return mode_string(buf, 0, fb_info->mode);
146 } 146 }
147 147
148 static ssize_t store_modes(struct class_device *class_device, const char * buf, 148 static ssize_t store_modes(struct class_device *class_device, const char * buf,
149 size_t count) 149 size_t count)
150 { 150 {
151 struct fb_info *fb_info = class_get_devdata(class_device); 151 struct fb_info *fb_info = class_get_devdata(class_device);
152 LIST_HEAD(old_list); 152 LIST_HEAD(old_list);
153 int i = count / sizeof(struct fb_videomode); 153 int i = count / sizeof(struct fb_videomode);
154 154
155 if (i * sizeof(struct fb_videomode) != count) 155 if (i * sizeof(struct fb_videomode) != count)
156 return -EINVAL; 156 return -EINVAL;
157 157
158 acquire_console_sem(); 158 acquire_console_sem();
159 list_splice(&fb_info->modelist, &old_list); 159 list_splice(&fb_info->modelist, &old_list);
160 fb_videomode_to_modelist((struct fb_videomode *)buf, i, 160 fb_videomode_to_modelist((struct fb_videomode *)buf, i,
161 &fb_info->modelist); 161 &fb_info->modelist);
162 if (fb_new_modelist(fb_info)) { 162 if (fb_new_modelist(fb_info)) {
163 fb_destroy_modelist(&fb_info->modelist); 163 fb_destroy_modelist(&fb_info->modelist);
164 list_splice(&old_list, &fb_info->modelist); 164 list_splice(&old_list, &fb_info->modelist);
165 } else 165 } else
166 fb_destroy_modelist(&old_list); 166 fb_destroy_modelist(&old_list);
167 167
168 release_console_sem(); 168 release_console_sem();
169 169
170 return 0; 170 return 0;
171 } 171 }
172 172
173 static ssize_t show_modes(struct class_device *class_device, char *buf) 173 static ssize_t show_modes(struct class_device *class_device, char *buf)
174 { 174 {
175 struct fb_info *fb_info = class_get_devdata(class_device); 175 struct fb_info *fb_info = class_get_devdata(class_device);
176 unsigned int i; 176 unsigned int i;
177 struct list_head *pos; 177 struct list_head *pos;
178 struct fb_modelist *modelist; 178 struct fb_modelist *modelist;
179 const struct fb_videomode *mode; 179 const struct fb_videomode *mode;
180 180
181 i = 0; 181 i = 0;
182 list_for_each(pos, &fb_info->modelist) { 182 list_for_each(pos, &fb_info->modelist) {
183 modelist = list_entry(pos, struct fb_modelist, list); 183 modelist = list_entry(pos, struct fb_modelist, list);
184 mode = &modelist->mode; 184 mode = &modelist->mode;
185 i += mode_string(buf, i, mode); 185 i += mode_string(buf, i, mode);
186 } 186 }
187 return i; 187 return i;
188 } 188 }
189 189
190 static ssize_t store_bpp(struct class_device *class_device, const char * buf, 190 static ssize_t store_bpp(struct class_device *class_device, const char * buf,
191 size_t count) 191 size_t count)
192 { 192 {
193 struct fb_info *fb_info = class_get_devdata(class_device); 193 struct fb_info *fb_info = class_get_devdata(class_device);
194 struct fb_var_screeninfo var; 194 struct fb_var_screeninfo var;
195 char ** last = NULL; 195 char ** last = NULL;
196 int err; 196 int err;
197 197
198 var = fb_info->var; 198 var = fb_info->var;
199 var.bits_per_pixel = simple_strtoul(buf, last, 0); 199 var.bits_per_pixel = simple_strtoul(buf, last, 0);
200 if ((err = activate(fb_info, &var))) 200 if ((err = activate(fb_info, &var)))
201 return err; 201 return err;
202 return count; 202 return count;
203 } 203 }
204 204
205 static ssize_t show_bpp(struct class_device *class_device, char *buf) 205 static ssize_t show_bpp(struct class_device *class_device, char *buf)
206 { 206 {
207 struct fb_info *fb_info = class_get_devdata(class_device); 207 struct fb_info *fb_info = class_get_devdata(class_device);
208 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->var.bits_per_pixel); 208 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->var.bits_per_pixel);
209 } 209 }
210 210
211 static ssize_t store_rotate(struct class_device *class_device, const char *buf, 211 static ssize_t store_rotate(struct class_device *class_device, const char *buf,
212 size_t count) 212 size_t count)
213 { 213 {
214 struct fb_info *fb_info = class_get_devdata(class_device); 214 struct fb_info *fb_info = class_get_devdata(class_device);
215 struct fb_var_screeninfo var; 215 struct fb_var_screeninfo var;
216 char **last = NULL; 216 char **last = NULL;
217 int err; 217 int err;
218 218
219 var = fb_info->var; 219 var = fb_info->var;
220 var.rotate = simple_strtoul(buf, last, 0); 220 var.rotate = simple_strtoul(buf, last, 0);
221 221
222 if ((err = activate(fb_info, &var))) 222 if ((err = activate(fb_info, &var)))
223 return err; 223 return err;
224 224
225 return count; 225 return count;
226 } 226 }
227 227
228 228
229 static ssize_t show_rotate(struct class_device *class_device, char *buf) 229 static ssize_t show_rotate(struct class_device *class_device, char *buf)
230 { 230 {
231 struct fb_info *fb_info = class_get_devdata(class_device); 231 struct fb_info *fb_info = class_get_devdata(class_device);
232 232
233 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->var.rotate); 233 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->var.rotate);
234 } 234 }
235 235
236 static ssize_t store_con_rotate(struct class_device *class_device, 236 static ssize_t store_con_rotate(struct class_device *class_device,
237 const char *buf, size_t count) 237 const char *buf, size_t count)
238 { 238 {
239 struct fb_info *fb_info = class_get_devdata(class_device); 239 struct fb_info *fb_info = class_get_devdata(class_device);
240 int rotate; 240 int rotate;
241 char **last = NULL; 241 char **last = NULL;
242 242
243 acquire_console_sem(); 243 acquire_console_sem();
244 rotate = simple_strtoul(buf, last, 0); 244 rotate = simple_strtoul(buf, last, 0);
245 fb_con_duit(fb_info, FB_EVENT_SET_CON_ROTATE, &rotate); 245 fb_con_duit(fb_info, FB_EVENT_SET_CON_ROTATE, &rotate);
246 release_console_sem(); 246 release_console_sem();
247 return count; 247 return count;
248 } 248 }
249 249
250 static ssize_t store_con_rotate_all(struct class_device *class_device, 250 static ssize_t store_con_rotate_all(struct class_device *class_device,
251 const char *buf, size_t count) 251 const char *buf, size_t count)
252 { 252 {
253 struct fb_info *fb_info = class_get_devdata(class_device); 253 struct fb_info *fb_info = class_get_devdata(class_device);
254 int rotate; 254 int rotate;
255 char **last = NULL; 255 char **last = NULL;
256 256
257 acquire_console_sem(); 257 acquire_console_sem();
258 rotate = simple_strtoul(buf, last, 0); 258 rotate = simple_strtoul(buf, last, 0);
259 fb_con_duit(fb_info, FB_EVENT_SET_CON_ROTATE_ALL, &rotate); 259 fb_con_duit(fb_info, FB_EVENT_SET_CON_ROTATE_ALL, &rotate);
260 release_console_sem(); 260 release_console_sem();
261 return count; 261 return count;
262 } 262 }
263 263
264 static ssize_t show_con_rotate(struct class_device *class_device, char *buf) 264 static ssize_t show_con_rotate(struct class_device *class_device, char *buf)
265 { 265 {
266 struct fb_info *fb_info = class_get_devdata(class_device); 266 struct fb_info *fb_info = class_get_devdata(class_device);
267 int rotate; 267 int rotate;
268 268
269 acquire_console_sem(); 269 acquire_console_sem();
270 rotate = fb_con_duit(fb_info, FB_EVENT_GET_CON_ROTATE, NULL); 270 rotate = fb_con_duit(fb_info, FB_EVENT_GET_CON_ROTATE, NULL);
271 release_console_sem(); 271 release_console_sem();
272 return snprintf(buf, PAGE_SIZE, "%d\n", rotate); 272 return snprintf(buf, PAGE_SIZE, "%d\n", rotate);
273 } 273 }
274 274
275 static ssize_t store_virtual(struct class_device *class_device, 275 static ssize_t store_virtual(struct class_device *class_device,
276 const char * buf, size_t count) 276 const char * buf, size_t count)
277 { 277 {
278 struct fb_info *fb_info = class_get_devdata(class_device); 278 struct fb_info *fb_info = class_get_devdata(class_device);
279 struct fb_var_screeninfo var; 279 struct fb_var_screeninfo var;
280 char *last = NULL; 280 char *last = NULL;
281 int err; 281 int err;
282 282
283 var = fb_info->var; 283 var = fb_info->var;
284 var.xres_virtual = simple_strtoul(buf, &last, 0); 284 var.xres_virtual = simple_strtoul(buf, &last, 0);
285 last++; 285 last++;
286 if (last - buf >= count) 286 if (last - buf >= count)
287 return -EINVAL; 287 return -EINVAL;
288 var.yres_virtual = simple_strtoul(last, &last, 0); 288 var.yres_virtual = simple_strtoul(last, &last, 0);
289 289
290 if ((err = activate(fb_info, &var))) 290 if ((err = activate(fb_info, &var)))
291 return err; 291 return err;
292 return count; 292 return count;
293 } 293 }
294 294
295 static ssize_t show_virtual(struct class_device *class_device, char *buf) 295 static ssize_t show_virtual(struct class_device *class_device, char *buf)
296 { 296 {
297 struct fb_info *fb_info = class_get_devdata(class_device); 297 struct fb_info *fb_info = class_get_devdata(class_device);
298 return snprintf(buf, PAGE_SIZE, "%d,%d\n", fb_info->var.xres_virtual, 298 return snprintf(buf, PAGE_SIZE, "%d,%d\n", fb_info->var.xres_virtual,
299 fb_info->var.yres_virtual); 299 fb_info->var.yres_virtual);
300 } 300 }
301 301
302 static ssize_t show_stride(struct class_device *class_device, char *buf) 302 static ssize_t show_stride(struct class_device *class_device, char *buf)
303 { 303 {
304 struct fb_info *fb_info = class_get_devdata(class_device); 304 struct fb_info *fb_info = class_get_devdata(class_device);
305 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->fix.line_length); 305 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->fix.line_length);
306 } 306 }
307 307
308 /* Format for cmap is "%02x%c%4x%4x%4x\n" */ 308 /* Format for cmap is "%02x%c%4x%4x%4x\n" */
309 /* %02x entry %c transp %4x red %4x blue %4x green \n */ 309 /* %02x entry %c transp %4x red %4x blue %4x green \n */
310 /* 256 rows at 16 chars equals 4096, the normal page size */ 310 /* 256 rows at 16 chars equals 4096, the normal page size */
311 /* the code will automatically adjust for different page sizes */ 311 /* the code will automatically adjust for different page sizes */
312 static ssize_t store_cmap(struct class_device *class_device, const char *buf, 312 static ssize_t store_cmap(struct class_device *class_device, const char *buf,
313 size_t count) 313 size_t count)
314 { 314 {
315 struct fb_info *fb_info = class_get_devdata(class_device); 315 struct fb_info *fb_info = class_get_devdata(class_device);
316 int rc, i, start, length, transp = 0; 316 int rc, i, start, length, transp = 0;
317 317
318 if ((count > PAGE_SIZE) || ((count % 16) != 0)) 318 if ((count > PAGE_SIZE) || ((count % 16) != 0))
319 return -EINVAL; 319 return -EINVAL;
320 320
321 if (!fb_info->fbops->fb_setcolreg && !fb_info->fbops->fb_setcmap) 321 if (!fb_info->fbops->fb_setcolreg && !fb_info->fbops->fb_setcmap)
322 return -EINVAL; 322 return -EINVAL;
323 323
324 sscanf(buf, "%02x", &start); 324 sscanf(buf, "%02x", &start);
325 length = count / 16; 325 length = count / 16;
326 326
327 for (i = 0; i < length; i++) 327 for (i = 0; i < length; i++)
328 if (buf[i * 16 + 2] != ' ') 328 if (buf[i * 16 + 2] != ' ')
329 transp = 1; 329 transp = 1;
330 330
331 /* If we can batch, do it */ 331 /* If we can batch, do it */
332 if (fb_info->fbops->fb_setcmap && length > 1) { 332 if (fb_info->fbops->fb_setcmap && length > 1) {
333 struct fb_cmap umap; 333 struct fb_cmap umap;
334 334
335 memset(&umap, 0, sizeof(umap)); 335 memset(&umap, 0, sizeof(umap));
336 if ((rc = fb_alloc_cmap(&umap, length, transp))) 336 if ((rc = fb_alloc_cmap(&umap, length, transp)))
337 return rc; 337 return rc;
338 338
339 umap.start = start; 339 umap.start = start;
340 for (i = 0; i < length; i++) { 340 for (i = 0; i < length; i++) {
341 sscanf(&buf[i * 16 + 3], "%4hx", &umap.red[i]); 341 sscanf(&buf[i * 16 + 3], "%4hx", &umap.red[i]);
342 sscanf(&buf[i * 16 + 7], "%4hx", &umap.blue[i]); 342 sscanf(&buf[i * 16 + 7], "%4hx", &umap.blue[i]);
343 sscanf(&buf[i * 16 + 11], "%4hx", &umap.green[i]); 343 sscanf(&buf[i * 16 + 11], "%4hx", &umap.green[i]);
344 if (transp) 344 if (transp)
345 umap.transp[i] = (buf[i * 16 + 2] != ' '); 345 umap.transp[i] = (buf[i * 16 + 2] != ' ');
346 } 346 }
347 rc = fb_info->fbops->fb_setcmap(&umap, fb_info); 347 rc = fb_info->fbops->fb_setcmap(&umap, fb_info);
348 fb_copy_cmap(&umap, &fb_info->cmap); 348 fb_copy_cmap(&umap, &fb_info->cmap);
349 fb_dealloc_cmap(&umap); 349 fb_dealloc_cmap(&umap);
350 350
351 return rc; 351 return rc ?: count;
352 } 352 }
353 for (i = 0; i < length; i++) { 353 for (i = 0; i < length; i++) {
354 u16 red, blue, green, tsp; 354 u16 red, blue, green, tsp;
355 355
356 sscanf(&buf[i * 16 + 3], "%4hx", &red); 356 sscanf(&buf[i * 16 + 3], "%4hx", &red);
357 sscanf(&buf[i * 16 + 7], "%4hx", &blue); 357 sscanf(&buf[i * 16 + 7], "%4hx", &blue);
358 sscanf(&buf[i * 16 + 11], "%4hx", &green); 358 sscanf(&buf[i * 16 + 11], "%4hx", &green);
359 tsp = (buf[i * 16 + 2] != ' '); 359 tsp = (buf[i * 16 + 2] != ' ');
360 if ((rc = fb_info->fbops->fb_setcolreg(start++, 360 if ((rc = fb_info->fbops->fb_setcolreg(start++,
361 red, green, blue, tsp, fb_info))) 361 red, green, blue, tsp, fb_info)))
362 return rc; 362 return rc;
363 363
364 fb_info->cmap.red[i] = red; 364 fb_info->cmap.red[i] = red;
365 fb_info->cmap.blue[i] = blue; 365 fb_info->cmap.blue[i] = blue;
366 fb_info->cmap.green[i] = green; 366 fb_info->cmap.green[i] = green;
367 if (transp) 367 if (transp)
368 fb_info->cmap.transp[i] = tsp; 368 fb_info->cmap.transp[i] = tsp;
369 } 369 }
370 return 0; 370 return count;
371 } 371 }
372 372
373 static ssize_t show_cmap(struct class_device *class_device, char *buf) 373 static ssize_t show_cmap(struct class_device *class_device, char *buf)
374 { 374 {
375 struct fb_info *fb_info = class_get_devdata(class_device); 375 struct fb_info *fb_info = class_get_devdata(class_device);
376 unsigned int i; 376 unsigned int i;
377 377
378 if (!fb_info->cmap.red || !fb_info->cmap.blue || 378 if (!fb_info->cmap.red || !fb_info->cmap.blue ||
379 !fb_info->cmap.green) 379 !fb_info->cmap.green)
380 return -EINVAL; 380 return -EINVAL;
381 381
382 if (fb_info->cmap.len > PAGE_SIZE / 16) 382 if (fb_info->cmap.len > PAGE_SIZE / 16)
383 return -EINVAL; 383 return -EINVAL;
384 384
385 /* don't mess with the format, the buffer is PAGE_SIZE */ 385 /* don't mess with the format, the buffer is PAGE_SIZE */
386 /* 256 entries at 16 chars per line equals 4096 = PAGE_SIZE */ 386 /* 256 entries at 16 chars per line equals 4096 = PAGE_SIZE */
387 for (i = 0; i < fb_info->cmap.len; i++) { 387 for (i = 0; i < fb_info->cmap.len; i++) {
388 snprintf(&buf[ i * 16], PAGE_SIZE - i * 16, "%02x%c%4x%4x%4x\n", i + fb_info->cmap.start, 388 snprintf(&buf[ i * 16], PAGE_SIZE - i * 16, "%02x%c%4x%4x%4x\n", i + fb_info->cmap.start,
389 ((fb_info->cmap.transp && fb_info->cmap.transp[i]) ? '*' : ' '), 389 ((fb_info->cmap.transp && fb_info->cmap.transp[i]) ? '*' : ' '),
390 fb_info->cmap.red[i], fb_info->cmap.blue[i], 390 fb_info->cmap.red[i], fb_info->cmap.blue[i],
391 fb_info->cmap.green[i]); 391 fb_info->cmap.green[i]);
392 } 392 }
393 return 16 * fb_info->cmap.len; 393 return 16 * fb_info->cmap.len;
394 } 394 }
395 395
396 static ssize_t store_blank(struct class_device *class_device, const char * buf, 396 static ssize_t store_blank(struct class_device *class_device, const char * buf,
397 size_t count) 397 size_t count)
398 { 398 {
399 struct fb_info *fb_info = class_get_devdata(class_device); 399 struct fb_info *fb_info = class_get_devdata(class_device);
400 char *last = NULL; 400 char *last = NULL;
401 int err; 401 int err;
402 402
403 acquire_console_sem(); 403 acquire_console_sem();
404 fb_info->flags |= FBINFO_MISC_USEREVENT; 404 fb_info->flags |= FBINFO_MISC_USEREVENT;
405 err = fb_blank(fb_info, simple_strtoul(buf, &last, 0)); 405 err = fb_blank(fb_info, simple_strtoul(buf, &last, 0));
406 fb_info->flags &= ~FBINFO_MISC_USEREVENT; 406 fb_info->flags &= ~FBINFO_MISC_USEREVENT;
407 release_console_sem(); 407 release_console_sem();
408 if (err < 0) 408 if (err < 0)
409 return err; 409 return err;
410 return count; 410 return count;
411 } 411 }
412 412
413 static ssize_t show_blank(struct class_device *class_device, char *buf) 413 static ssize_t show_blank(struct class_device *class_device, char *buf)
414 { 414 {
415 // struct fb_info *fb_info = class_get_devdata(class_device); 415 // struct fb_info *fb_info = class_get_devdata(class_device);
416 return 0; 416 return 0;
417 } 417 }
418 418
419 static ssize_t store_console(struct class_device *class_device, 419 static ssize_t store_console(struct class_device *class_device,
420 const char * buf, size_t count) 420 const char * buf, size_t count)
421 { 421 {
422 // struct fb_info *fb_info = class_get_devdata(class_device); 422 // struct fb_info *fb_info = class_get_devdata(class_device);
423 return 0; 423 return 0;
424 } 424 }
425 425
426 static ssize_t show_console(struct class_device *class_device, char *buf) 426 static ssize_t show_console(struct class_device *class_device, char *buf)
427 { 427 {
428 // struct fb_info *fb_info = class_get_devdata(class_device); 428 // struct fb_info *fb_info = class_get_devdata(class_device);
429 return 0; 429 return 0;
430 } 430 }
431 431
432 static ssize_t store_cursor(struct class_device *class_device, 432 static ssize_t store_cursor(struct class_device *class_device,
433 const char * buf, size_t count) 433 const char * buf, size_t count)
434 { 434 {
435 // struct fb_info *fb_info = class_get_devdata(class_device); 435 // struct fb_info *fb_info = class_get_devdata(class_device);
436 return 0; 436 return 0;
437 } 437 }
438 438
439 static ssize_t show_cursor(struct class_device *class_device, char *buf) 439 static ssize_t show_cursor(struct class_device *class_device, char *buf)
440 { 440 {
441 // struct fb_info *fb_info = class_get_devdata(class_device); 441 // struct fb_info *fb_info = class_get_devdata(class_device);
442 return 0; 442 return 0;
443 } 443 }
444 444
445 static ssize_t store_pan(struct class_device *class_device, const char * buf, 445 static ssize_t store_pan(struct class_device *class_device, const char * buf,
446 size_t count) 446 size_t count)
447 { 447 {
448 struct fb_info *fb_info = class_get_devdata(class_device); 448 struct fb_info *fb_info = class_get_devdata(class_device);
449 struct fb_var_screeninfo var; 449 struct fb_var_screeninfo var;
450 char *last = NULL; 450 char *last = NULL;
451 int err; 451 int err;
452 452
453 var = fb_info->var; 453 var = fb_info->var;
454 var.xoffset = simple_strtoul(buf, &last, 0); 454 var.xoffset = simple_strtoul(buf, &last, 0);
455 last++; 455 last++;
456 if (last - buf >= count) 456 if (last - buf >= count)
457 return -EINVAL; 457 return -EINVAL;
458 var.yoffset = simple_strtoul(last, &last, 0); 458 var.yoffset = simple_strtoul(last, &last, 0);
459 459
460 acquire_console_sem(); 460 acquire_console_sem();
461 err = fb_pan_display(fb_info, &var); 461 err = fb_pan_display(fb_info, &var);
462 release_console_sem(); 462 release_console_sem();
463 463
464 if (err < 0) 464 if (err < 0)
465 return err; 465 return err;
466 return count; 466 return count;
467 } 467 }
468 468
469 static ssize_t show_pan(struct class_device *class_device, char *buf) 469 static ssize_t show_pan(struct class_device *class_device, char *buf)
470 { 470 {
471 struct fb_info *fb_info = class_get_devdata(class_device); 471 struct fb_info *fb_info = class_get_devdata(class_device);
472 return snprintf(buf, PAGE_SIZE, "%d,%d\n", fb_info->var.xoffset, 472 return snprintf(buf, PAGE_SIZE, "%d,%d\n", fb_info->var.xoffset,
473 fb_info->var.xoffset); 473 fb_info->var.xoffset);
474 } 474 }
475 475
476 static ssize_t show_name(struct class_device *class_device, char *buf) 476 static ssize_t show_name(struct class_device *class_device, char *buf)
477 { 477 {
478 struct fb_info *fb_info = class_get_devdata(class_device); 478 struct fb_info *fb_info = class_get_devdata(class_device);
479 479
480 return snprintf(buf, PAGE_SIZE, "%s\n", fb_info->fix.id); 480 return snprintf(buf, PAGE_SIZE, "%s\n", fb_info->fix.id);
481 } 481 }
482 482
483 static ssize_t store_fbstate(struct class_device *class_device, 483 static ssize_t store_fbstate(struct class_device *class_device,
484 const char *buf, size_t count) 484 const char *buf, size_t count)
485 { 485 {
486 struct fb_info *fb_info = class_get_devdata(class_device); 486 struct fb_info *fb_info = class_get_devdata(class_device);
487 u32 state; 487 u32 state;
488 char *last = NULL; 488 char *last = NULL;
489 489
490 state = simple_strtoul(buf, &last, 0); 490 state = simple_strtoul(buf, &last, 0);
491 491
492 acquire_console_sem(); 492 acquire_console_sem();
493 fb_set_suspend(fb_info, (int)state); 493 fb_set_suspend(fb_info, (int)state);
494 release_console_sem(); 494 release_console_sem();
495 495
496 return count; 496 return count;
497 } 497 }
498 498
499 static ssize_t show_fbstate(struct class_device *class_device, char *buf) 499 static ssize_t show_fbstate(struct class_device *class_device, char *buf)
500 { 500 {
501 struct fb_info *fb_info = class_get_devdata(class_device); 501 struct fb_info *fb_info = class_get_devdata(class_device);
502 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->state); 502 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->state);
503 } 503 }
504 504
505 static struct class_device_attribute class_device_attrs[] = { 505 static struct class_device_attribute class_device_attrs[] = {
506 __ATTR(bits_per_pixel, S_IRUGO|S_IWUSR, show_bpp, store_bpp), 506 __ATTR(bits_per_pixel, S_IRUGO|S_IWUSR, show_bpp, store_bpp),
507 __ATTR(blank, S_IRUGO|S_IWUSR, show_blank, store_blank), 507 __ATTR(blank, S_IRUGO|S_IWUSR, show_blank, store_blank),
508 __ATTR(color_map, S_IRUGO|S_IWUSR, show_cmap, store_cmap), 508 __ATTR(color_map, S_IRUGO|S_IWUSR, show_cmap, store_cmap),
509 __ATTR(console, S_IRUGO|S_IWUSR, show_console, store_console), 509 __ATTR(console, S_IRUGO|S_IWUSR, show_console, store_console),
510 __ATTR(cursor, S_IRUGO|S_IWUSR, show_cursor, store_cursor), 510 __ATTR(cursor, S_IRUGO|S_IWUSR, show_cursor, store_cursor),
511 __ATTR(mode, S_IRUGO|S_IWUSR, show_mode, store_mode), 511 __ATTR(mode, S_IRUGO|S_IWUSR, show_mode, store_mode),
512 __ATTR(modes, S_IRUGO|S_IWUSR, show_modes, store_modes), 512 __ATTR(modes, S_IRUGO|S_IWUSR, show_modes, store_modes),
513 __ATTR(pan, S_IRUGO|S_IWUSR, show_pan, store_pan), 513 __ATTR(pan, S_IRUGO|S_IWUSR, show_pan, store_pan),
514 __ATTR(virtual_size, S_IRUGO|S_IWUSR, show_virtual, store_virtual), 514 __ATTR(virtual_size, S_IRUGO|S_IWUSR, show_virtual, store_virtual),
515 __ATTR(name, S_IRUGO, show_name, NULL), 515 __ATTR(name, S_IRUGO, show_name, NULL),
516 __ATTR(stride, S_IRUGO, show_stride, NULL), 516 __ATTR(stride, S_IRUGO, show_stride, NULL),
517 __ATTR(rotate, S_IRUGO|S_IWUSR, show_rotate, store_rotate), 517 __ATTR(rotate, S_IRUGO|S_IWUSR, show_rotate, store_rotate),
518 __ATTR(con_rotate, S_IRUGO|S_IWUSR, show_con_rotate, store_con_rotate), 518 __ATTR(con_rotate, S_IRUGO|S_IWUSR, show_con_rotate, store_con_rotate),
519 __ATTR(con_rotate_all, S_IWUSR, NULL, store_con_rotate_all), 519 __ATTR(con_rotate_all, S_IWUSR, NULL, store_con_rotate_all),
520 __ATTR(state, S_IRUGO|S_IWUSR, show_fbstate, store_fbstate), 520 __ATTR(state, S_IRUGO|S_IWUSR, show_fbstate, store_fbstate),
521 }; 521 };
522 522
523 int fb_init_class_device(struct fb_info *fb_info) 523 int fb_init_class_device(struct fb_info *fb_info)
524 { 524 {
525 unsigned int i; 525 unsigned int i;
526 class_set_devdata(fb_info->class_device, fb_info); 526 class_set_devdata(fb_info->class_device, fb_info);
527 527
528 for (i = 0; i < ARRAY_SIZE(class_device_attrs); i++) 528 for (i = 0; i < ARRAY_SIZE(class_device_attrs); i++)
529 class_device_create_file(fb_info->class_device, 529 class_device_create_file(fb_info->class_device,
530 &class_device_attrs[i]); 530 &class_device_attrs[i]);
531 return 0; 531 return 0;
532 } 532 }
533 533
534 void fb_cleanup_class_device(struct fb_info *fb_info) 534 void fb_cleanup_class_device(struct fb_info *fb_info)
535 { 535 {
536 unsigned int i; 536 unsigned int i;
537 537
538 for (i = 0; i < ARRAY_SIZE(class_device_attrs); i++) 538 for (i = 0; i < ARRAY_SIZE(class_device_attrs); i++)
539 class_device_remove_file(fb_info->class_device, 539 class_device_remove_file(fb_info->class_device,
540 &class_device_attrs[i]); 540 &class_device_attrs[i]);
541 } 541 }
542 542
543 543
544 544