Doug / smarc-fsl-linux-kernel

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/*

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/*

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* drivers/video/aty/radeon_base.c

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* drivers/video/aty/radeon_base.c

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*

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*

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* framebuffer driver for ATI Radeon chipset video boards

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* framebuffer driver for ATI Radeon chipset video boards

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*

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*

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*

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*

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* i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>

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* i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>

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*

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*

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* Special thanks to ATI DevRel team for their hardware donations.

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* Special thanks to ATI DevRel team for their hardware donations.

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*

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*

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* ...Insert GPL boilerplate here...

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* ...Insert GPL boilerplate here...

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*

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*

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* Significant portions of this driver apdated from XFree86 Radeon

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* Significant portions of this driver apdated from XFree86 Radeon

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* driver which has the following copyright notice:

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* driver which has the following copyright notice:

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*

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*

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* VA Linux Systems Inc., Fremont, California.

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* VA Linux Systems Inc., Fremont, California.

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*

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*

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*

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*

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* Permission is hereby granted, free of charge, to any person obtaining

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* Permission is hereby granted, free of charge, to any person obtaining

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* a copy of this software and associated documentation files (the

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* a copy of this software and associated documentation files (the

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* "Software"), to deal in the Software without restriction, including

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* "Software"), to deal in the Software without restriction, including

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* without limitation on the rights to use, copy, modify, merge,

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* without limitation on the rights to use, copy, modify, merge,

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* publish, distribute, sublicense, and/or sell copies of the Software,

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* publish, distribute, sublicense, and/or sell copies of the Software,

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* and to permit persons to whom the Software is furnished to do so,

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* and to permit persons to whom the Software is furnished to do so,

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* subject to the following conditions:

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* subject to the following conditions:

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*

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*

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* The above copyright notice and this permission notice (including the

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* The above copyright notice and this permission notice (including the

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* next paragraph) shall be included in all copies or substantial

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* next paragraph) shall be included in all copies or substantial

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* portions of the Software.

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* portions of the Software.

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*

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*

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

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* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR

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* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR

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* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

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* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

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* DEALINGS IN THE SOFTWARE.

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* DEALINGS IN THE SOFTWARE.

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*

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*

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* XFree86 driver authors:

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* XFree86 driver authors:

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*

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*

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* Kevin E. Martin <martin@xfree86.org>

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* Kevin E. Martin <martin@xfree86.org>

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* Rickard E. Faith <faith@valinux.com>

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* Rickard E. Faith <faith@valinux.com>

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* Alan Hourihane <alanh@fairlite.demon.co.uk>

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* Alan Hourihane <alanh@fairlite.demon.co.uk>

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*

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*

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*/

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*/

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#define RADEON_VERSION "0.2.0"

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#define RADEON_VERSION "0.2.0"

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#include <linux/config.h>

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#include <linux/config.h>

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/moduleparam.h>

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#include <linux/moduleparam.h>

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/errno.h>

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#include <linux/errno.h>

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#include <linux/string.h>

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#include <linux/string.h>

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#include <linux/mm.h>

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#include <linux/mm.h>

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#include <linux/tty.h>

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#include <linux/tty.h>

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#include <linux/slab.h>

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#include <linux/slab.h>

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#include <linux/delay.h>

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#include <linux/delay.h>

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#include <linux/time.h>

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#include <linux/time.h>

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#include <linux/fb.h>

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#include <linux/fb.h>

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#include <linux/ioport.h>

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#include <linux/ioport.h>

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#include <linux/init.h>

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#include <linux/init.h>

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#include <linux/pci.h>

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#include <linux/pci.h>

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#include <linux/vmalloc.h>

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#include <linux/vmalloc.h>

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#include <linux/device.h>

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#include <linux/device.h>

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#include <linux/i2c.h>

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#include <asm/io.h>

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#include <asm/io.h>

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#include <asm/uaccess.h>

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#include <asm/uaccess.h>

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#ifdef CONFIG_PPC_OF

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#ifdef CONFIG_PPC_OF

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#include <asm/pci-bridge.h>

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#include <asm/pci-bridge.h>

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#include "../macmodes.h"

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#include "../macmodes.h"

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#ifdef CONFIG_PMAC_BACKLIGHT

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#ifdef CONFIG_PMAC_BACKLIGHT

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#include <asm/backlight.h>

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#include <asm/backlight.h>

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#endif

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#endif

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#ifdef CONFIG_BOOTX_TEXT

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#ifdef CONFIG_BOOTX_TEXT

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#include <asm/btext.h>

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#include <asm/btext.h>

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#endif

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#endif

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#endif /* CONFIG_PPC_OF */

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#endif /* CONFIG_PPC_OF */

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#ifdef CONFIG_MTRR

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#ifdef CONFIG_MTRR

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#include <asm/mtrr.h>

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#include <asm/mtrr.h>

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#endif

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#endif

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#include <video/radeon.h>

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#include <video/radeon.h>

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#include <linux/radeonfb.h>

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#include <linux/radeonfb.h>

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#include "../edid.h" // MOVE THAT TO include/video

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#include "../edid.h" // MOVE THAT TO include/video

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#include "ati_ids.h"

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#include "ati_ids.h"

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#include "radeonfb.h"

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#include "radeonfb.h"

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#define MAX_MAPPED_VRAM (2048*2048*4)

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#define MAX_MAPPED_VRAM (2048*2048*4)

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#define MIN_MAPPED_VRAM (1024*768*1)

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#define MIN_MAPPED_VRAM (1024*768*1)

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#define CHIP_DEF(id, family, flags) \

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#define CHIP_DEF(id, family, flags) \

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{ PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }

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{ PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }

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static struct pci_device_id radeonfb_pci_table[] = {

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static struct pci_device_id radeonfb_pci_table[] = {

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/* Mobility M6 */

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/* Mobility M6 */

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CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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/* Radeon VE/7000 */

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/* Radeon VE/7000 */

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CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),

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/* Radeon IGP320M (U1) */

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/* Radeon IGP320M (U1) */

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CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),

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/* Radeon IGP320 (A3) */

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/* Radeon IGP320 (A3) */

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CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),

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CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),

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/* IGP330M/340M/350M (U2) */

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/* IGP330M/340M/350M (U2) */

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CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),

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/* IGP330/340/350 (A4) */

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/* IGP330/340/350 (A4) */

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CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),

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CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),

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/* Mobility 7000 IGP */

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/* Mobility 7000 IGP */

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CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),

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/* 7000 IGP (A4+) */

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/* 7000 IGP (A4+) */

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CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),

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CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),

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/* 8500 AIW */

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/* 8500 AIW */

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CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),

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/* 8700/8800 */

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/* 8700/8800 */

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CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),

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/* 8500 */

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/* 8500 */

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CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),

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/* 9100 */

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/* 9100 */

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CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),

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/* Mobility M7 */

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/* Mobility M7 */

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CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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/* 7500 */

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/* 7500 */

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CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),

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/* Mobility M9 */

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/* Mobility M9 */

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CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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/* 9000/Pro */

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/* 9000/Pro */

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CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),

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/* Mobility 9100 IGP (U3) */

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/* Mobility 9100 IGP (U3) */

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CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),

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/* 9100 IGP (A5) */

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/* 9100 IGP (A5) */

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CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),

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CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),

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CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),

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CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),

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/* Mobility 9200 (M9+) */

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/* Mobility 9200 (M9+) */

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CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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/* 9200 */

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/* 9200 */

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CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),

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/* 9500 */

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/* 9500 */

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CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),

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/* 9600TX / FireGL Z1 */

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/* 9600TX / FireGL Z1 */

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CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),

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/* 9700/9500/Pro/FireGL X1 */

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/* 9700/9500/Pro/FireGL X1 */

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CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),

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/* Mobility M10/M11 */

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/* Mobility M10/M11 */

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CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

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/* 9600/FireGL T2 */

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/* 9600/FireGL T2 */

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CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),

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/* 9800/Pro/FileGL X2 */

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/* 9800/Pro/FileGL X2 */

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CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),

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CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),

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/* Newer stuff */

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/* Newer stuff */

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CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),

199

CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),

201

CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),

200

CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),

202

CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

201

CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

203

CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

202

CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

204

CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),

203

CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),

205

CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),

204

CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),

206

CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),

205

CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),

207

CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),

206

CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),

208

CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

207

CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

209

CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

208

CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

210

CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),

209

CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),

211

CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),

210

CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),

212

CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),

211

CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),

213

CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),

212

CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),

214

CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),

213

CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),

215

CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),

214

CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),

216

CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

215

CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),

217

CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),

216

CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),

218

CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),

217

CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),

219

CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),

218

CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),

220

CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),

219

CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),

221

CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),

220

CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),

222

CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),

221

CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),

223

CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),

222

CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),

224

CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),

223

CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),

225

CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),

224

CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),

226

/* Original Radeon/7200 */

225

/* Original Radeon/7200 */

227

CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),

226

CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),

228

CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),

227

CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),

229

CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),

228

CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),

230

CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),

229

CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),

231

{ 0, }

230

{ 0, }

232

};

231

};

233

MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);

232

MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);

234

233

235

234

236

typedef struct {

235

typedef struct {

237

u16 reg;

236

u16 reg;

238

u32 val;

237

u32 val;

239

} reg_val;

238

} reg_val;

240

239

241

240

242

/* these common regs are cleared before mode setting so they do not

241

/* these common regs are cleared before mode setting so they do not

243

* interfere with anything

242

* interfere with anything

244

*/

243

*/

245

static reg_val common_regs[] = {

244

static reg_val common_regs[] = {

246

{ OVR_CLR, 0 },

245

{ OVR_CLR, 0 },

247

{ OVR_WID_LEFT_RIGHT, 0 },

246

{ OVR_WID_LEFT_RIGHT, 0 },

248

{ OVR_WID_TOP_BOTTOM, 0 },

247

{ OVR_WID_TOP_BOTTOM, 0 },

249

{ OV0_SCALE_CNTL, 0 },

248

{ OV0_SCALE_CNTL, 0 },

250

{ SUBPIC_CNTL, 0 },

249

{ SUBPIC_CNTL, 0 },

251

{ VIPH_CONTROL, 0 },

250

{ VIPH_CONTROL, 0 },

252

{ I2C_CNTL_1, 0 },

251

{ I2C_CNTL_1, 0 },

253

{ GEN_INT_CNTL, 0 },

252

{ GEN_INT_CNTL, 0 },

254

{ CAP0_TRIG_CNTL, 0 },

253

{ CAP0_TRIG_CNTL, 0 },

255

{ CAP1_TRIG_CNTL, 0 },

254

{ CAP1_TRIG_CNTL, 0 },

256

};

255

};

257

256

258

/*

257

/*

259

* globals

258

* globals

260

*/

259

*/

261

260

262

static char *mode_option;

261

static char *mode_option;

263

static char *monitor_layout;

262

static char *monitor_layout;

264

static int noaccel = 0;

263

static int noaccel = 0;

265

static int default_dynclk = -2;

264

static int default_dynclk = -2;

266

static int nomodeset = 0;

265

static int nomodeset = 0;

267

static int ignore_edid = 0;

266

static int ignore_edid = 0;

268

static int mirror = 0;

267

static int mirror = 0;

269

static int panel_yres = 0;

268

static int panel_yres = 0;

270

static int force_dfp = 0;

269

static int force_dfp = 0;

271

static int force_measure_pll = 0;

270

static int force_measure_pll = 0;

272

#ifdef CONFIG_MTRR

271

#ifdef CONFIG_MTRR

273

static int nomtrr = 0;

272

static int nomtrr = 0;

274

#endif

273

#endif

275

274

276

/*

275

/*

277

* prototypes

276

* prototypes

278

*/

277

*/

279

278

280

279

281

#ifdef CONFIG_PPC_OF

280

#ifdef CONFIG_PPC_OF

282

281

283

#ifdef CONFIG_PMAC_BACKLIGHT

282

#ifdef CONFIG_PMAC_BACKLIGHT

284

static int radeon_set_backlight_enable(int on, int level, void *data);

283

static int radeon_set_backlight_enable(int on, int level, void *data);

285

static int radeon_set_backlight_level(int level, void *data);

284

static int radeon_set_backlight_level(int level, void *data);

286

static struct backlight_controller radeon_backlight_controller = {

285

static struct backlight_controller radeon_backlight_controller = {

287

radeon_set_backlight_enable,

286

radeon_set_backlight_enable,

288

radeon_set_backlight_level

287

radeon_set_backlight_level

289

};

288

};

290

#endif /* CONFIG_PMAC_BACKLIGHT */

289

#endif /* CONFIG_PMAC_BACKLIGHT */

291

290

292

#endif /* CONFIG_PPC_OF */

291

#endif /* CONFIG_PPC_OF */

293

292

294

static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)

293

static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)

295

{

294

{

296

if (!rinfo->bios_seg)

295

if (!rinfo->bios_seg)

297

return;

296

return;

298

pci_unmap_rom(dev, rinfo->bios_seg);

297

pci_unmap_rom(dev, rinfo->bios_seg);

299

}

298

}

300

299

301

static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)

300

static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)

302

{

301

{

303

void __iomem *rom;

302

void __iomem *rom;

304

u16 dptr;

303

u16 dptr;

305

u8 rom_type;

304

u8 rom_type;

306

size_t rom_size;

305

size_t rom_size;

307

306

308

/* If this is a primary card, there is a shadow copy of the

307

/* If this is a primary card, there is a shadow copy of the

309

* ROM somewhere in the first meg. We will just ignore the copy

308

* ROM somewhere in the first meg. We will just ignore the copy

310

* and use the ROM directly.

309

* and use the ROM directly.

311

*/

310

*/

312

311

313

/* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */

312

/* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */

314

unsigned int temp;

313

unsigned int temp;

315

temp = INREG(MPP_TB_CONFIG);

314

temp = INREG(MPP_TB_CONFIG);

316

temp &= 0x00ffffffu;

315

temp &= 0x00ffffffu;

317

temp |= 0x04 << 24;

316

temp |= 0x04 << 24;

318

OUTREG(MPP_TB_CONFIG, temp);

317

OUTREG(MPP_TB_CONFIG, temp);

319

temp = INREG(MPP_TB_CONFIG);

318

temp = INREG(MPP_TB_CONFIG);

320

319

321

rom = pci_map_rom(dev, &rom_size);

320

rom = pci_map_rom(dev, &rom_size);

322

if (!rom) {

321

if (!rom) {

323

printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",

322

printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",

324

pci_name(rinfo->pdev));

323

pci_name(rinfo->pdev));

325

return -ENOMEM;

324

return -ENOMEM;

326

}

325

}

327

326

328

rinfo->bios_seg = rom;

327

rinfo->bios_seg = rom;

329

328

330

/* Very simple test to make sure it appeared */

329

/* Very simple test to make sure it appeared */

331

if (BIOS_IN16(0) != 0xaa55) {

330

if (BIOS_IN16(0) != 0xaa55) {

332

printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "

331

printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "

333

"should be 0xaa55\n",

332

"should be 0xaa55\n",

334

pci_name(rinfo->pdev), BIOS_IN16(0));

333

pci_name(rinfo->pdev), BIOS_IN16(0));

335

goto failed;

334

goto failed;

336

}

335

}

337

/* Look for the PCI data to check the ROM type */

336

/* Look for the PCI data to check the ROM type */

338

dptr = BIOS_IN16(0x18);

337

dptr = BIOS_IN16(0x18);

339

338

340

/* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM

339

/* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM

341

* for now, until I've verified this works everywhere. The goal here is more

340

* for now, until I've verified this works everywhere. The goal here is more

342

* to phase out Open Firmware images.

341

* to phase out Open Firmware images.

343

*

342

*

344

* Currently, we only look at the first PCI data, we could iteratre and deal with

343

* Currently, we only look at the first PCI data, we could iteratre and deal with

345

* them all, and we should use fb_bios_start relative to start of image and not

344

* them all, and we should use fb_bios_start relative to start of image and not

346

* relative start of ROM, but so far, I never found a dual-image ATI card

345

* relative start of ROM, but so far, I never found a dual-image ATI card

347

*

346

*

348

* typedef struct {

347

* typedef struct {

349

* u32 signature; + 0x00

348

* u32 signature; + 0x00

350

* u16 vendor; + 0x04

349

* u16 vendor; + 0x04

351

* u16 device; + 0x06

350

* u16 device; + 0x06

352

* u16 reserved_1; + 0x08

351

* u16 reserved_1; + 0x08

353

* u16 dlen; + 0x0a

352

* u16 dlen; + 0x0a

354

* u8 drevision; + 0x0c

353

* u8 drevision; + 0x0c

355

* u8 class_hi; + 0x0d

354

* u8 class_hi; + 0x0d

356

* u16 class_lo; + 0x0e

355

* u16 class_lo; + 0x0e

357

* u16 ilen; + 0x10

356

* u16 ilen; + 0x10

358

* u16 irevision; + 0x12

357

* u16 irevision; + 0x12

359

* u8 type; + 0x14

358

* u8 type; + 0x14

360

* u8 indicator; + 0x15

359

* u8 indicator; + 0x15

361

* u16 reserved_2; + 0x16

360

* u16 reserved_2; + 0x16

362

* } pci_data_t;

361

* } pci_data_t;

363

*/

362

*/

364

if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {

363

if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {

365

printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"

364

printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"

366

"incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));

365

"incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));

367

goto anyway;

366

goto anyway;

368

}

367

}

369

rom_type = BIOS_IN8(dptr + 0x14);

368

rom_type = BIOS_IN8(dptr + 0x14);

370

switch(rom_type) {

369

switch(rom_type) {

371

case 0:

370

case 0:

372

printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");

371

printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");

373

break;

372

break;

374

case 1:

373

case 1:

375

printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");

374

printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");

376

goto failed;

375

goto failed;

377

case 2:

376

case 2:

378

printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");

377

printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");

379

goto failed;

378

goto failed;

380

default:

379

default:

381

printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);

380

printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);

382

goto failed;

381

goto failed;

383

}

382

}

384

anyway:

383

anyway:

385

/* Locate the flat panel infos, do some sanity checking !!! */

384

/* Locate the flat panel infos, do some sanity checking !!! */

386

rinfo->fp_bios_start = BIOS_IN16(0x48);

385

rinfo->fp_bios_start = BIOS_IN16(0x48);

387

return 0;

386

return 0;

388

387

389

failed:

388

failed:

390

rinfo->bios_seg = NULL;

389

rinfo->bios_seg = NULL;

391

radeon_unmap_ROM(rinfo, dev);

390

radeon_unmap_ROM(rinfo, dev);

392

return -ENXIO;

391

return -ENXIO;

393

}

392

}

394

393

395

#ifdef CONFIG_X86

394

#ifdef CONFIG_X86

396

static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)

395

static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)

397

{

396

{

398

/* I simplified this code as we used to miss the signatures in

397

/* I simplified this code as we used to miss the signatures in

399

* a lot of case. It's now closer to XFree, we just don't check

398

* a lot of case. It's now closer to XFree, we just don't check

400

* for signatures at all... Something better will have to be done

399

* for signatures at all... Something better will have to be done

401

* if we end up having conflicts

400

* if we end up having conflicts

402

*/

401

*/

403

u32 segstart;

402

u32 segstart;

404

void __iomem *rom_base = NULL;

403

void __iomem *rom_base = NULL;

405

404

406

for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {

405

for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {

407

rom_base = ioremap(segstart, 0x10000);

406

rom_base = ioremap(segstart, 0x10000);

408

if (rom_base == NULL)

407

if (rom_base == NULL)

409

return -ENOMEM;

408

return -ENOMEM;

410

if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)

409

if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)

411

break;

410

break;

412

iounmap(rom_base);

411

iounmap(rom_base);

413

rom_base = NULL;

412

rom_base = NULL;

414

}

413

}

415

if (rom_base == NULL)

414

if (rom_base == NULL)

416

return -ENXIO;

415

return -ENXIO;

417

416

418

/* Locate the flat panel infos, do some sanity checking !!! */

417

/* Locate the flat panel infos, do some sanity checking !!! */

419

rinfo->bios_seg = rom_base;

418

rinfo->bios_seg = rom_base;

420

rinfo->fp_bios_start = BIOS_IN16(0x48);

419

rinfo->fp_bios_start = BIOS_IN16(0x48);

421

420

422

return 0;

421

return 0;

423

}

422

}

424

#endif

423

#endif

425

424

426

#ifdef CONFIG_PPC_OF

425

#ifdef CONFIG_PPC_OF

427

/*

426

/*

428

* Read XTAL (ref clock), SCLK and MCLK from Open Firmware device

427

* Read XTAL (ref clock), SCLK and MCLK from Open Firmware device

429

* tree. Hopefully, ATI OF driver is kind enough to fill these

428

* tree. Hopefully, ATI OF driver is kind enough to fill these

430

*/

429

*/

431

static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)

430

static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)

432

{

431

{

433

struct device_node *dp = rinfo->of_node;

432

struct device_node *dp = rinfo->of_node;

434

u32 *val;

433

u32 *val;

435

434

436

if (dp == NULL)

435

if (dp == NULL)

437

return -ENODEV;

436

return -ENODEV;

438

val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);

437

val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);

439

if (!val || !*val) {

438

if (!val || !*val) {

440

printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");

439

printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");

441

return -EINVAL;

440

return -EINVAL;

442

}

441

}

443

442

444

rinfo->pll.ref_clk = (*val) / 10;

443

rinfo->pll.ref_clk = (*val) / 10;

445

444

446

val = (u32 *) get_property(dp, "ATY,SCLK", NULL);

445

val = (u32 *) get_property(dp, "ATY,SCLK", NULL);

447

if (val && *val)

446

if (val && *val)

448

rinfo->pll.sclk = (*val) / 10;

447

rinfo->pll.sclk = (*val) / 10;

449

448

450

val = (u32 *) get_property(dp, "ATY,MCLK", NULL);

449

val = (u32 *) get_property(dp, "ATY,MCLK", NULL);

451

if (val && *val)

450

if (val && *val)

452

rinfo->pll.mclk = (*val) / 10;

451

rinfo->pll.mclk = (*val) / 10;

453

452

454

return 0;

453

return 0;

455

}

454

}

456

#endif /* CONFIG_PPC_OF */

455

#endif /* CONFIG_PPC_OF */

457

456

458

/*

457

/*

459

* Read PLL infos from chip registers

458

* Read PLL infos from chip registers

460

*/

459

*/

461

static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)

460

static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)

462

{

461

{

463

unsigned char ppll_div_sel;

462

unsigned char ppll_div_sel;

464

unsigned Ns, Nm, M;

463

unsigned Ns, Nm, M;

465

unsigned sclk, mclk, tmp, ref_div;

464

unsigned sclk, mclk, tmp, ref_div;

466

int hTotal, vTotal, num, denom, m, n;

465

int hTotal, vTotal, num, denom, m, n;

467

unsigned long long hz, vclk;

466

unsigned long long hz, vclk;

468

long xtal;

467

long xtal;

469

struct timeval start_tv, stop_tv;

468

struct timeval start_tv, stop_tv;

470

long total_secs, total_usecs;

469

long total_secs, total_usecs;

471

int i;

470

int i;

472

471

473

/* Ugh, we cut interrupts, bad bad bad, but we want some precision

472

/* Ugh, we cut interrupts, bad bad bad, but we want some precision

474

* here, so... --BenH

473

* here, so... --BenH

475

*/

474

*/

476

475

477

/* Flush PCI buffers ? */

476

/* Flush PCI buffers ? */

478

tmp = INREG16(DEVICE_ID);

477

tmp = INREG16(DEVICE_ID);

479

478

480

local_irq_disable();

479

local_irq_disable();

481

480

482

for(i=0; i<1000000; i++)

481

for(i=0; i<1000000; i++)

483

if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)

482

if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)

484

break;

483

break;

485

484

486

do_gettimeofday(&start_tv);

485

do_gettimeofday(&start_tv);

487

486

488

for(i=0; i<1000000; i++)

487

for(i=0; i<1000000; i++)

489

if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)

488

if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)

490

break;

489

break;

491

490

492

for(i=0; i<1000000; i++)

491

for(i=0; i<1000000; i++)

493

if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)

492

if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)

494

break;

493

break;

495

494

496

do_gettimeofday(&stop_tv);

495

do_gettimeofday(&stop_tv);

497

496

498

local_irq_enable();

497

local_irq_enable();

499

498

500

total_secs = stop_tv.tv_sec - start_tv.tv_sec;

499

total_secs = stop_tv.tv_sec - start_tv.tv_sec;

501

if (total_secs > 10)

500

if (total_secs > 10)

502

return -1;

501

return -1;

503

total_usecs = stop_tv.tv_usec - start_tv.tv_usec;

502

total_usecs = stop_tv.tv_usec - start_tv.tv_usec;

504

total_usecs += total_secs * 1000000;

503

total_usecs += total_secs * 1000000;

505

if (total_usecs < 0)

504

if (total_usecs < 0)

506

total_usecs = -total_usecs;

505

total_usecs = -total_usecs;

507

hz = 1000000/total_usecs;

506

hz = 1000000/total_usecs;

508

507

509

hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;

508

hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;

510

vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);

509

vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);

511

vclk = (long long)hTotal * (long long)vTotal * hz;

510

vclk = (long long)hTotal * (long long)vTotal * hz;

512

511

513

switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {

512

switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {

514

case 0:

513

case 0:

515

default:

514

default:

516

num = 1;

515

num = 1;

517

denom = 1;

516

denom = 1;

518

break;

517

break;

519

case 1:

518

case 1:

520

n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);

519

n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);

521

m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);

520

m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);

522

num = 2*n;

521

num = 2*n;

523

denom = 2*m;

522

denom = 2*m;

524

break;

523

break;

525

case 2:

524

case 2:

526

n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);

525

n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);

527

m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);

526

m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);

528

num = 2*n;

527

num = 2*n;

529

denom = 2*m;

528

denom = 2*m;

530

break;

529

break;

531

}

530

}

532

531

533

ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;

532

ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;

534

radeon_pll_errata_after_index(rinfo);

533

radeon_pll_errata_after_index(rinfo);

535

534

536

n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);

535

n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);

537

m = (INPLL(PPLL_REF_DIV) & 0x3ff);

536

m = (INPLL(PPLL_REF_DIV) & 0x3ff);

538

537

539

num *= n;

538

num *= n;

540

denom *= m;

539

denom *= m;

541

540

542

switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {

541

switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {

543

case 1:

542

case 1:

544

denom *= 2;

543

denom *= 2;

545

break;

544

break;

546

case 2:

545

case 2:

547

denom *= 4;

546

denom *= 4;

548

break;

547

break;

549

case 3:

548

case 3:

550

denom *= 8;

549

denom *= 8;

551

break;

550

break;

552

case 4:

551

case 4:

553

denom *= 3;

552

denom *= 3;

554

break;

553

break;

555

case 6:

554

case 6:

556

denom *= 6;

555

denom *= 6;

557

break;

556

break;

558

case 7:

557

case 7:

559

denom *= 12;

558

denom *= 12;

560

break;

559

break;

561

}

560

}

562

561

563

vclk *= denom;

562

vclk *= denom;

564

do_div(vclk, 1000 * num);

563

do_div(vclk, 1000 * num);

565

xtal = vclk;

564

xtal = vclk;

566

565

567

if ((xtal > 26900) && (xtal < 27100))

566

if ((xtal > 26900) && (xtal < 27100))

568

xtal = 2700;

567

xtal = 2700;

569

else if ((xtal > 14200) && (xtal < 14400))

568

else if ((xtal > 14200) && (xtal < 14400))

570

xtal = 1432;

569

xtal = 1432;

571

else if ((xtal > 29400) && (xtal < 29600))

570

else if ((xtal > 29400) && (xtal < 29600))

572

xtal = 2950;

571

xtal = 2950;

573

else {

572

else {

574

printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);

573

printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);

575

return -1;

574

return -1;

576

}

575

}

577

576

578

tmp = INPLL(M_SPLL_REF_FB_DIV);

577

tmp = INPLL(M_SPLL_REF_FB_DIV);

579

ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;

578

ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;

580

579

581

Ns = (tmp & 0xff0000) >> 16;

580

Ns = (tmp & 0xff0000) >> 16;

582

Nm = (tmp & 0xff00) >> 8;

581

Nm = (tmp & 0xff00) >> 8;

583

M = (tmp & 0xff);

582

M = (tmp & 0xff);

584

sclk = round_div((2 * Ns * xtal), (2 * M));

583

sclk = round_div((2 * Ns * xtal), (2 * M));

585

mclk = round_div((2 * Nm * xtal), (2 * M));

584

mclk = round_div((2 * Nm * xtal), (2 * M));

586

585

587

/* we're done, hopefully these are sane values */

586

/* we're done, hopefully these are sane values */

588

rinfo->pll.ref_clk = xtal;

587

rinfo->pll.ref_clk = xtal;

589

rinfo->pll.ref_div = ref_div;

588

rinfo->pll.ref_div = ref_div;

590

rinfo->pll.sclk = sclk;

589

rinfo->pll.sclk = sclk;

591

rinfo->pll.mclk = mclk;

590

rinfo->pll.mclk = mclk;

592

591

593

return 0;

592

return 0;

594

}

593

}

595

594

596

/*

595

/*

597

* Retreive PLL infos by different means (BIOS, Open Firmware, register probing...)

596

* Retreive PLL infos by different means (BIOS, Open Firmware, register probing...)

598

*/

597

*/

599

static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)

598

static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)

600

{

599

{

601

/*

600

/*

602

* In the case nothing works, these are defaults; they are mostly

601

* In the case nothing works, these are defaults; they are mostly

603

* incomplete, however. It does provide ppll_max and _min values

602

* incomplete, however. It does provide ppll_max and _min values

604

* even for most other methods, however.

603

* even for most other methods, however.

605

*/

604

*/

606

switch (rinfo->chipset) {

605

switch (rinfo->chipset) {

607

case PCI_DEVICE_ID_ATI_RADEON_QW:

606

case PCI_DEVICE_ID_ATI_RADEON_QW:

608

case PCI_DEVICE_ID_ATI_RADEON_QX:

607

case PCI_DEVICE_ID_ATI_RADEON_QX:

609

rinfo->pll.ppll_max = 35000;

608

rinfo->pll.ppll_max = 35000;

610

rinfo->pll.ppll_min = 12000;

609

rinfo->pll.ppll_min = 12000;

611

rinfo->pll.mclk = 23000;

610

rinfo->pll.mclk = 23000;

612

rinfo->pll.sclk = 23000;

611

rinfo->pll.sclk = 23000;

613

rinfo->pll.ref_clk = 2700;

612

rinfo->pll.ref_clk = 2700;

614

break;

613

break;

615

case PCI_DEVICE_ID_ATI_RADEON_QL:

614

case PCI_DEVICE_ID_ATI_RADEON_QL:

616

case PCI_DEVICE_ID_ATI_RADEON_QN:

615

case PCI_DEVICE_ID_ATI_RADEON_QN:

617

case PCI_DEVICE_ID_ATI_RADEON_QO:

616

case PCI_DEVICE_ID_ATI_RADEON_QO:

618

case PCI_DEVICE_ID_ATI_RADEON_Ql:

617

case PCI_DEVICE_ID_ATI_RADEON_Ql:

619

case PCI_DEVICE_ID_ATI_RADEON_BB:

618

case PCI_DEVICE_ID_ATI_RADEON_BB:

620

rinfo->pll.ppll_max = 35000;

619

rinfo->pll.ppll_max = 35000;

621

rinfo->pll.ppll_min = 12000;

620

rinfo->pll.ppll_min = 12000;

622

rinfo->pll.mclk = 27500;

621

rinfo->pll.mclk = 27500;

623

rinfo->pll.sclk = 27500;

622

rinfo->pll.sclk = 27500;

624

rinfo->pll.ref_clk = 2700;

623

rinfo->pll.ref_clk = 2700;

625

break;

624

break;

626

case PCI_DEVICE_ID_ATI_RADEON_Id:

625

case PCI_DEVICE_ID_ATI_RADEON_Id:

627

case PCI_DEVICE_ID_ATI_RADEON_Ie:

626

case PCI_DEVICE_ID_ATI_RADEON_Ie:

628

case PCI_DEVICE_ID_ATI_RADEON_If:

627

case PCI_DEVICE_ID_ATI_RADEON_If:

629

case PCI_DEVICE_ID_ATI_RADEON_Ig:

628

case PCI_DEVICE_ID_ATI_RADEON_Ig:

630

rinfo->pll.ppll_max = 35000;

629

rinfo->pll.ppll_max = 35000;

631

rinfo->pll.ppll_min = 12000;

630

rinfo->pll.ppll_min = 12000;

632

rinfo->pll.mclk = 25000;

631

rinfo->pll.mclk = 25000;

633

rinfo->pll.sclk = 25000;

632

rinfo->pll.sclk = 25000;

634

rinfo->pll.ref_clk = 2700;

633

rinfo->pll.ref_clk = 2700;

635

break;

634

break;

636

case PCI_DEVICE_ID_ATI_RADEON_ND:

635

case PCI_DEVICE_ID_ATI_RADEON_ND:

637

case PCI_DEVICE_ID_ATI_RADEON_NE:

636

case PCI_DEVICE_ID_ATI_RADEON_NE:

638

case PCI_DEVICE_ID_ATI_RADEON_NF:

637

case PCI_DEVICE_ID_ATI_RADEON_NF:

639

case PCI_DEVICE_ID_ATI_RADEON_NG:

638

case PCI_DEVICE_ID_ATI_RADEON_NG:

640

rinfo->pll.ppll_max = 40000;

639

rinfo->pll.ppll_max = 40000;

641

rinfo->pll.ppll_min = 20000;

640

rinfo->pll.ppll_min = 20000;

642

rinfo->pll.mclk = 27000;

641

rinfo->pll.mclk = 27000;

643

rinfo->pll.sclk = 27000;

642

rinfo->pll.sclk = 27000;

644

rinfo->pll.ref_clk = 2700;

643

rinfo->pll.ref_clk = 2700;

645

break;

644

break;

646

case PCI_DEVICE_ID_ATI_RADEON_QD:

645

case PCI_DEVICE_ID_ATI_RADEON_QD:

647

case PCI_DEVICE_ID_ATI_RADEON_QE:

646

case PCI_DEVICE_ID_ATI_RADEON_QE:

648

case PCI_DEVICE_ID_ATI_RADEON_QF:

647

case PCI_DEVICE_ID_ATI_RADEON_QF:

649

case PCI_DEVICE_ID_ATI_RADEON_QG:

648

case PCI_DEVICE_ID_ATI_RADEON_QG:

650

default:

649

default:

651

rinfo->pll.ppll_max = 35000;

650

rinfo->pll.ppll_max = 35000;

652

rinfo->pll.ppll_min = 12000;

651

rinfo->pll.ppll_min = 12000;

653

rinfo->pll.mclk = 16600;

652

rinfo->pll.mclk = 16600;

654

rinfo->pll.sclk = 16600;

653

rinfo->pll.sclk = 16600;

655

rinfo->pll.ref_clk = 2700;

654

rinfo->pll.ref_clk = 2700;

656

break;

655

break;

657

}

656

}

658

rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;

657

rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;

659

658

660

659

661

#ifdef CONFIG_PPC_OF

660

#ifdef CONFIG_PPC_OF

662

/*

661

/*

663

* Retreive PLL infos from Open Firmware first

662

* Retreive PLL infos from Open Firmware first

664

*/

663

*/

665

if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {

664

if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {

666

printk(KERN_INFO "radeonfb: Retreived PLL infos from Open Firmware\n");

665

printk(KERN_INFO "radeonfb: Retreived PLL infos from Open Firmware\n");

667

goto found;

666

goto found;

668

}

667

}

669

#endif /* CONFIG_PPC_OF */

668

#endif /* CONFIG_PPC_OF */

670

669

671

/*

670

/*

672

* Check out if we have an X86 which gave us some PLL informations

671

* Check out if we have an X86 which gave us some PLL informations

673

* and if yes, retreive them

672

* and if yes, retreive them

674

*/

673

*/

675

if (!force_measure_pll && rinfo->bios_seg) {

674

if (!force_measure_pll && rinfo->bios_seg) {

676

u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);

675

u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);

677

676

678

rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);

677

rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);

679

rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);

678

rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);

680

rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);

679

rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);

681

rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);

680

rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);

682

rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);

681

rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);

683

rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);

682

rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);

684

683

685

printk(KERN_INFO "radeonfb: Retreived PLL infos from BIOS\n");

684

printk(KERN_INFO "radeonfb: Retreived PLL infos from BIOS\n");

686

goto found;

685

goto found;

687

}

686

}

688

687

689

/*

688

/*

690

* We didn't get PLL parameters from either OF or BIOS, we try to

689

* We didn't get PLL parameters from either OF or BIOS, we try to

691

* probe them

690

* probe them

692

*/

691

*/

693

if (radeon_probe_pll_params(rinfo) == 0) {

692

if (radeon_probe_pll_params(rinfo) == 0) {

694

printk(KERN_INFO "radeonfb: Retreived PLL infos from registers\n");

693

printk(KERN_INFO "radeonfb: Retreived PLL infos from registers\n");

695

goto found;

694

goto found;

696

}

695

}

697

696

698

/*

697

/*

699

* Fall back to already-set defaults...

698

* Fall back to already-set defaults...

700

*/

699

*/

701

printk(KERN_INFO "radeonfb: Used default PLL infos\n");

700

printk(KERN_INFO "radeonfb: Used default PLL infos\n");

702

701

703

found:

702

found:

704

/*

703

/*

705

* Some methods fail to retreive SCLK and MCLK values, we apply default

704

* Some methods fail to retreive SCLK and MCLK values, we apply default

706

* settings in this case (200Mhz). If that really happne often, we could

705

* settings in this case (200Mhz). If that really happne often, we could

707

* fetch from registers instead...

706

* fetch from registers instead...

708

*/

707

*/

709

if (rinfo->pll.mclk == 0)

708

if (rinfo->pll.mclk == 0)

710

rinfo->pll.mclk = 20000;

709

rinfo->pll.mclk = 20000;

711

if (rinfo->pll.sclk == 0)

710

if (rinfo->pll.sclk == 0)

712

rinfo->pll.sclk = 20000;

711

rinfo->pll.sclk = 20000;

713

712

714

printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",

713

printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",

715

rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,

714

rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,

716

rinfo->pll.ref_div,

715

rinfo->pll.ref_div,

717

rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,

716

rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,

718

rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);

717

rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);

719

printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);

718

printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);

720

}

719

}

721

720

722

static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)

721

static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)

723

{

722

{

724

struct radeonfb_info *rinfo = info->par;

723

struct radeonfb_info *rinfo = info->par;

725

struct fb_var_screeninfo v;

724

struct fb_var_screeninfo v;

726

int nom, den;

725

int nom, den;

727

unsigned int pitch;

726

unsigned int pitch;

728

727

729

if (radeon_match_mode(rinfo, &v, var))

728

if (radeon_match_mode(rinfo, &v, var))

730

return -EINVAL;

729

return -EINVAL;

731

730

732

switch (v.bits_per_pixel) {

731

switch (v.bits_per_pixel) {

733

case 0 ... 8:

732

case 0 ... 8:

734

v.bits_per_pixel = 8;

733

v.bits_per_pixel = 8;

735

break;

734

break;

736

case 9 ... 16:

735

case 9 ... 16:

737

v.bits_per_pixel = 16;

736

v.bits_per_pixel = 16;

738

break;

737

break;

739

case 17 ... 24:

738

case 17 ... 24:

740

#if 0 /* Doesn't seem to work */

739

#if 0 /* Doesn't seem to work */

741

v.bits_per_pixel = 24;

740

v.bits_per_pixel = 24;

742

break;

741

break;

743

#endif

742

#endif

744

return -EINVAL;

743

return -EINVAL;

745

case 25 ... 32:

744

case 25 ... 32:

746

v.bits_per_pixel = 32;

745

v.bits_per_pixel = 32;

747

break;

746

break;

748

default:

747

default:

749

return -EINVAL;

748

return -EINVAL;

750

}

749

}

751

750

752

switch (var_to_depth(&v)) {

751

switch (var_to_depth(&v)) {

753

case 8:

752

case 8:

754

nom = den = 1;

753

nom = den = 1;

755

v.red.offset = v.green.offset = v.blue.offset = 0;

754

v.red.offset = v.green.offset = v.blue.offset = 0;

756

v.red.length = v.green.length = v.blue.length = 8;

755

v.red.length = v.green.length = v.blue.length = 8;

757

v.transp.offset = v.transp.length = 0;

756

v.transp.offset = v.transp.length = 0;

758

break;

757

break;

759

case 15:

758

case 15:

760

nom = 2;

759

nom = 2;

761

den = 1;

760

den = 1;

762

v.red.offset = 10;

761

v.red.offset = 10;

763

v.green.offset = 5;

762

v.green.offset = 5;

764

v.blue.offset = 0;

763

v.blue.offset = 0;

765

v.red.length = v.green.length = v.blue.length = 5;

764

v.red.length = v.green.length = v.blue.length = 5;

766

v.transp.offset = v.transp.length = 0;

765

v.transp.offset = v.transp.length = 0;

767

break;

766

break;

768

case 16:

767

case 16:

769

nom = 2;

768

nom = 2;

770

den = 1;

769

den = 1;

771

v.red.offset = 11;

770

v.red.offset = 11;

772

v.green.offset = 5;

771

v.green.offset = 5;

773

v.blue.offset = 0;

772

v.blue.offset = 0;

774

v.red.length = 5;

773

v.red.length = 5;

775

v.green.length = 6;

774

v.green.length = 6;

776

v.blue.length = 5;

775

v.blue.length = 5;

777

v.transp.offset = v.transp.length = 0;

776

v.transp.offset = v.transp.length = 0;

778

break;

777

break;

779

case 24:

778

case 24:

780

nom = 4;

779

nom = 4;

781

den = 1;

780

den = 1;

782

v.red.offset = 16;

781

v.red.offset = 16;

783

v.green.offset = 8;

782

v.green.offset = 8;

784

v.blue.offset = 0;

783

v.blue.offset = 0;

785

v.red.length = v.blue.length = v.green.length = 8;

784

v.red.length = v.blue.length = v.green.length = 8;

786

v.transp.offset = v.transp.length = 0;

785

v.transp.offset = v.transp.length = 0;

787

break;

786

break;

788

case 32:

787

case 32:

789

nom = 4;

788

nom = 4;

790

den = 1;

789

den = 1;

791

v.red.offset = 16;

790

v.red.offset = 16;

792

v.green.offset = 8;

791

v.green.offset = 8;

793

v.blue.offset = 0;

792

v.blue.offset = 0;

794

v.red.length = v.blue.length = v.green.length = 8;

793

v.red.length = v.blue.length = v.green.length = 8;

795

v.transp.offset = 24;

794

v.transp.offset = 24;

796

v.transp.length = 8;

795

v.transp.length = 8;

797

break;

796

break;

798

default:

797

default:

799

printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",

798

printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",

800

var->xres, var->yres, var->bits_per_pixel);

799

var->xres, var->yres, var->bits_per_pixel);

801

return -EINVAL;

800

return -EINVAL;

802

}

801

}

803

802

804

if (v.yres_virtual < v.yres)

803

if (v.yres_virtual < v.yres)

805

v.yres_virtual = v.yres;

804

v.yres_virtual = v.yres;

806

if (v.xres_virtual < v.xres)

805

if (v.xres_virtual < v.xres)

807

v.xres_virtual = v.xres;

806

v.xres_virtual = v.xres;

808

807

809

808

810

/* XXX I'm adjusting xres_virtual to the pitch, that may help XFree

809

/* XXX I'm adjusting xres_virtual to the pitch, that may help XFree

811

* with some panels, though I don't quite like this solution

810

* with some panels, though I don't quite like this solution

812

*/

811

*/

813

if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {

812

if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {

814

v.xres_virtual = v.xres_virtual & ~7ul;

813

v.xres_virtual = v.xres_virtual & ~7ul;

815

} else {

814

} else {

816

pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)

815

pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)

817

& ~(0x3f)) >> 6;

816

& ~(0x3f)) >> 6;

818

v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);

817

v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);

819

}

818

}

820

819

821

if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)

820

if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)

822

return -EINVAL;

821

return -EINVAL;

823

822

824

if (v.xres_virtual < v.xres)

823

if (v.xres_virtual < v.xres)

825

v.xres = v.xres_virtual;

824

v.xres = v.xres_virtual;

826

825

827

if (v.xoffset < 0)

826

if (v.xoffset < 0)

828

v.xoffset = 0;

827

v.xoffset = 0;

829

if (v.yoffset < 0)

828

if (v.yoffset < 0)

830

v.yoffset = 0;

829

v.yoffset = 0;

831

830

832

if (v.xoffset > v.xres_virtual - v.xres)

831

if (v.xoffset > v.xres_virtual - v.xres)

833

v.xoffset = v.xres_virtual - v.xres - 1;

832

v.xoffset = v.xres_virtual - v.xres - 1;

834

833

835

if (v.yoffset > v.yres_virtual - v.yres)

834

if (v.yoffset > v.yres_virtual - v.yres)

836

v.yoffset = v.yres_virtual - v.yres - 1;

835

v.yoffset = v.yres_virtual - v.yres - 1;

837

836

838

v.red.msb_right = v.green.msb_right = v.blue.msb_right =

837

v.red.msb_right = v.green.msb_right = v.blue.msb_right =

839

v.transp.offset = v.transp.length =

838

v.transp.offset = v.transp.length =

840

v.transp.msb_right = 0;

839

v.transp.msb_right = 0;

841

840

842

memcpy(var, &v, sizeof(v));

841

memcpy(var, &v, sizeof(v));

843

842

844

return 0;

843

return 0;

845

}

844

}

846

845

847

846

848

static int radeonfb_pan_display (struct fb_var_screeninfo *var,

847

static int radeonfb_pan_display (struct fb_var_screeninfo *var,

849

struct fb_info *info)

848

struct fb_info *info)

850

{

849

{

851

struct radeonfb_info *rinfo = info->par;

850

struct radeonfb_info *rinfo = info->par;

852

851

853

if ((var->xoffset + var->xres > var->xres_virtual)

852

if ((var->xoffset + var->xres > var->xres_virtual)

854

|| (var->yoffset + var->yres > var->yres_virtual))

853

|| (var->yoffset + var->yres > var->yres_virtual))

855

return -EINVAL;

854

return -EINVAL;

856

855

857

if (rinfo->asleep)

856

if (rinfo->asleep)

858

return 0;

857

return 0;

859

858

860

radeon_fifo_wait(2);

859

radeon_fifo_wait(2);

861

OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)

860

OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)

862

* var->bits_per_pixel / 8) & ~7);

861

* var->bits_per_pixel / 8) & ~7);

863

return 0;

862

return 0;

864

}

863

}

865

864

866

865

867

static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,

866

static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,

868

unsigned long arg, struct fb_info *info)

867

unsigned long arg, struct fb_info *info)

869

{

868

{

870

struct radeonfb_info *rinfo = info->par;

869

struct radeonfb_info *rinfo = info->par;

871

unsigned int tmp;

870

unsigned int tmp;

872

u32 value = 0;

871

u32 value = 0;

873

int rc;

872

int rc;

874

873

875

switch (cmd) {

874

switch (cmd) {

876

/*

875

/*

877

* TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's

876

* TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's

878

* and do something better using 2nd CRTC instead of just hackish

877

* and do something better using 2nd CRTC instead of just hackish

879

* routing to second output

878

* routing to second output

880

*/

879

*/

881

case FBIO_RADEON_SET_MIRROR:

880

case FBIO_RADEON_SET_MIRROR:

882

if (!rinfo->is_mobility)

881

if (!rinfo->is_mobility)

883

return -EINVAL;

882

return -EINVAL;

884

883

885

rc = get_user(value, (__u32 __user *)arg);

884

rc = get_user(value, (__u32 __user *)arg);

886

885

887

if (rc)

886

if (rc)

888

return rc;

887

return rc;

889

888

890

radeon_fifo_wait(2);

889

radeon_fifo_wait(2);

891

if (value & 0x01) {

890

if (value & 0x01) {

892

tmp = INREG(LVDS_GEN_CNTL);

891

tmp = INREG(LVDS_GEN_CNTL);

893

892

894

tmp |= (LVDS_ON | LVDS_BLON);

893

tmp |= (LVDS_ON | LVDS_BLON);

895

} else {

894

} else {

896

tmp = INREG(LVDS_GEN_CNTL);

895

tmp = INREG(LVDS_GEN_CNTL);

897

896

898

tmp &= ~(LVDS_ON | LVDS_BLON);

897

tmp &= ~(LVDS_ON | LVDS_BLON);

899

}

898

}

900

899

901

OUTREG(LVDS_GEN_CNTL, tmp);

900

OUTREG(LVDS_GEN_CNTL, tmp);

902

901

903

if (value & 0x02) {

902

if (value & 0x02) {

904

tmp = INREG(CRTC_EXT_CNTL);

903

tmp = INREG(CRTC_EXT_CNTL);

905

tmp |= CRTC_CRT_ON;

904

tmp |= CRTC_CRT_ON;

906

905

907

mirror = 1;

906

mirror = 1;

908

} else {

907

} else {

909

tmp = INREG(CRTC_EXT_CNTL);

908

tmp = INREG(CRTC_EXT_CNTL);

910

tmp &= ~CRTC_CRT_ON;

909

tmp &= ~CRTC_CRT_ON;

911

910

912

mirror = 0;

911

mirror = 0;

913

}

912

}

914

913

915

OUTREG(CRTC_EXT_CNTL, tmp);

914

OUTREG(CRTC_EXT_CNTL, tmp);

916

915

917

return 0;

916

return 0;

918

case FBIO_RADEON_GET_MIRROR:

917

case FBIO_RADEON_GET_MIRROR:

919

if (!rinfo->is_mobility)

918

if (!rinfo->is_mobility)

920

return -EINVAL;

919

return -EINVAL;

921

920

922

tmp = INREG(LVDS_GEN_CNTL);

921

tmp = INREG(LVDS_GEN_CNTL);

923

if ((LVDS_ON | LVDS_BLON) & tmp)

922

if ((LVDS_ON | LVDS_BLON) & tmp)

924

value |= 0x01;

923

value |= 0x01;

925

924

926

tmp = INREG(CRTC_EXT_CNTL);

925

tmp = INREG(CRTC_EXT_CNTL);

927

if (CRTC_CRT_ON & tmp)

926

if (CRTC_CRT_ON & tmp)

928

value |= 0x02;

927

value |= 0x02;

929

928

930

return put_user(value, (__u32 __user *)arg);

929

return put_user(value, (__u32 __user *)arg);

931

default:

930

default:

932

return -EINVAL;

931

return -EINVAL;

933

}

932

}

934

933

935

return -EINVAL;

934

return -EINVAL;

936

}

935

}

937

936

938

937

939

int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)

938

int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)

940

{

939

{

941

u32 val;

940

u32 val;

942

u32 tmp_pix_clks;

941

u32 tmp_pix_clks;

943

int unblank = 0;

942

int unblank = 0;

944

943

945

if (rinfo->lock_blank)

944

if (rinfo->lock_blank)

946

return 0;

945

return 0;

947

946

948

radeon_engine_idle();

947

radeon_engine_idle();

949

948

950

val = INREG(CRTC_EXT_CNTL);

949

val = INREG(CRTC_EXT_CNTL);

951

val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |

950

val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |

952

CRTC_VSYNC_DIS);

951

CRTC_VSYNC_DIS);

953

switch (blank) {

952

switch (blank) {

954

case FB_BLANK_VSYNC_SUSPEND:

953

case FB_BLANK_VSYNC_SUSPEND:

955

val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);

954

val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);

956

break;

955

break;

957

case FB_BLANK_HSYNC_SUSPEND:

956

case FB_BLANK_HSYNC_SUSPEND:

958

val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);

957

val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);

959

break;

958

break;

960

case FB_BLANK_POWERDOWN:

959

case FB_BLANK_POWERDOWN:

961

val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |

960

val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |

962

CRTC_HSYNC_DIS);

961

CRTC_HSYNC_DIS);

963

break;

962

break;

964

case FB_BLANK_NORMAL:

963

case FB_BLANK_NORMAL:

965

val |= CRTC_DISPLAY_DIS;

964

val |= CRTC_DISPLAY_DIS;

966

break;

965

break;

967

case FB_BLANK_UNBLANK:

966

case FB_BLANK_UNBLANK:

968

default:

967

default:

969

unblank = 1;

968

unblank = 1;

970

}

969

}

971

OUTREG(CRTC_EXT_CNTL, val);

970

OUTREG(CRTC_EXT_CNTL, val);

972

971

973

972

974

switch (rinfo->mon1_type) {

973

switch (rinfo->mon1_type) {

975

case MT_DFP:

974

case MT_DFP:

976

if (unblank)

975

if (unblank)

977

OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),

976

OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),

978

~(FP_FPON | FP_TMDS_EN));

977

~(FP_FPON | FP_TMDS_EN));

979

else {

978

else {

980

if (mode_switch || blank == FB_BLANK_NORMAL)

979

if (mode_switch || blank == FB_BLANK_NORMAL)

981

break;

980

break;

982

OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));

981

OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));

983

}

982

}

984

break;

983

break;

985

case MT_LCD:

984

case MT_LCD:

986

del_timer_sync(&rinfo->lvds_timer);

985

del_timer_sync(&rinfo->lvds_timer);

987

val = INREG(LVDS_GEN_CNTL);

986

val = INREG(LVDS_GEN_CNTL);

988

if (unblank) {

987

if (unblank) {

989

u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON

988

u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON

990

| LVDS_EN | (rinfo->init_state.lvds_gen_cntl

989

| LVDS_EN | (rinfo->init_state.lvds_gen_cntl

991

& (LVDS_DIGON | LVDS_BL_MOD_EN));

990

& (LVDS_DIGON | LVDS_BL_MOD_EN));

992

if ((val ^ target_val) == LVDS_DISPLAY_DIS)

991

if ((val ^ target_val) == LVDS_DISPLAY_DIS)

993

OUTREG(LVDS_GEN_CNTL, target_val);

992

OUTREG(LVDS_GEN_CNTL, target_val);

994

else if ((val ^ target_val) != 0) {

993

else if ((val ^ target_val) != 0) {

995

OUTREG(LVDS_GEN_CNTL, target_val

994

OUTREG(LVDS_GEN_CNTL, target_val

996

& ~(LVDS_ON | LVDS_BL_MOD_EN));

995

& ~(LVDS_ON | LVDS_BL_MOD_EN));

997

rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;

996

rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;

998

rinfo->init_state.lvds_gen_cntl |=

997

rinfo->init_state.lvds_gen_cntl |=

999

target_val & LVDS_STATE_MASK;

998

target_val & LVDS_STATE_MASK;

1000

if (mode_switch) {

999

if (mode_switch) {

1001

radeon_msleep(rinfo->panel_info.pwr_delay);

1000

radeon_msleep(rinfo->panel_info.pwr_delay);

1002

OUTREG(LVDS_GEN_CNTL, target_val);

1001

OUTREG(LVDS_GEN_CNTL, target_val);

1003

}

1002

}

1004

else {

1003

else {

1005

rinfo->pending_lvds_gen_cntl = target_val;

1004

rinfo->pending_lvds_gen_cntl = target_val;

1006

mod_timer(&rinfo->lvds_timer,

1005

mod_timer(&rinfo->lvds_timer,

1007

jiffies +

1006

jiffies +

1008

msecs_to_jiffies(rinfo->panel_info.pwr_delay));

1007

msecs_to_jiffies(rinfo->panel_info.pwr_delay));

1009

}

1008

}

1010

}

1009

}

1011

} else {

1010

} else {

1012

val |= LVDS_DISPLAY_DIS;

1011

val |= LVDS_DISPLAY_DIS;

1013

OUTREG(LVDS_GEN_CNTL, val);

1012

OUTREG(LVDS_GEN_CNTL, val);

1014

1013

1015

/* We don't do a full switch-off on a simple mode switch */

1014

/* We don't do a full switch-off on a simple mode switch */

1016

if (mode_switch || blank == FB_BLANK_NORMAL)

1015

if (mode_switch || blank == FB_BLANK_NORMAL)

1017

break;

1016

break;

1018

1017

1019

/* Asic bug, when turning off LVDS_ON, we have to make sure

1018

/* Asic bug, when turning off LVDS_ON, we have to make sure

1020

* RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off

1019

* RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off

1021

*/

1020

*/

1022

tmp_pix_clks = INPLL(PIXCLKS_CNTL);

1021

tmp_pix_clks = INPLL(PIXCLKS_CNTL);

1023

if (rinfo->is_mobility || rinfo->is_IGP)

1022

if (rinfo->is_mobility || rinfo->is_IGP)

1024

OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);

1023

OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);

1025

val &= ~(LVDS_BL_MOD_EN);

1024

val &= ~(LVDS_BL_MOD_EN);

1026

OUTREG(LVDS_GEN_CNTL, val);

1025

OUTREG(LVDS_GEN_CNTL, val);

1027

udelay(100);

1026

udelay(100);

1028

val &= ~(LVDS_ON | LVDS_EN);

1027

val &= ~(LVDS_ON | LVDS_EN);

1029

OUTREG(LVDS_GEN_CNTL, val);

1028

OUTREG(LVDS_GEN_CNTL, val);

1030

val &= ~LVDS_DIGON;

1029

val &= ~LVDS_DIGON;

1031

rinfo->pending_lvds_gen_cntl = val;

1030

rinfo->pending_lvds_gen_cntl = val;

1032

mod_timer(&rinfo->lvds_timer,

1031

mod_timer(&rinfo->lvds_timer,

1033

jiffies +

1032

jiffies +

1034

msecs_to_jiffies(rinfo->panel_info.pwr_delay));

1033

msecs_to_jiffies(rinfo->panel_info.pwr_delay));

1035

rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;

1034

rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;

1036

rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;

1035

rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;

1037

if (rinfo->is_mobility || rinfo->is_IGP)

1036

if (rinfo->is_mobility || rinfo->is_IGP)

1038

OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);

1037

OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);

1039

}

1038

}

1040

break;

1039

break;

1041

case MT_CRT:

1040

case MT_CRT:

1042

// todo: powerdown DAC

1041

// todo: powerdown DAC

1043

default:

1042

default:

1044

break;

1043

break;

1045

}

1044

}

1046

1045

1047

/* let fbcon do a soft blank for us */

1046

/* let fbcon do a soft blank for us */

1048

return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0;

1047

return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0;

1049

}

1048

}

1050

1049

1051

static int radeonfb_blank (int blank, struct fb_info *info)

1050

static int radeonfb_blank (int blank, struct fb_info *info)

1052

{

1051

{

1053

struct radeonfb_info *rinfo = info->par;

1052

struct radeonfb_info *rinfo = info->par;

1054

1053

1055

if (rinfo->asleep)

1054

if (rinfo->asleep)

1056

return 0;

1055

return 0;

1057

1056

1058

return radeon_screen_blank(rinfo, blank, 0);

1057

return radeon_screen_blank(rinfo, blank, 0);

1059

}

1058

}

1060

1059

1061

static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,

1060

static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,

1062

unsigned blue, unsigned transp,

1061

unsigned blue, unsigned transp,

1063

struct radeonfb_info *rinfo)

1062

struct radeonfb_info *rinfo)

1064

{

1063

{

1065

u32 pindex;

1064

u32 pindex;

1066

unsigned int i;

1065

unsigned int i;

1067

1066

1068

1067

1069

if (regno > 255)

1068

if (regno > 255)

1070

return 1;

1069

return 1;

1071

1070

1072

red >>= 8;

1071

red >>= 8;

1073

green >>= 8;

1072

green >>= 8;

1074

blue >>= 8;

1073

blue >>= 8;

1075

rinfo->palette[regno].red = red;

1074

rinfo->palette[regno].red = red;

1076

rinfo->palette[regno].green = green;

1075

rinfo->palette[regno].green = green;

1077

rinfo->palette[regno].blue = blue;

1076

rinfo->palette[regno].blue = blue;

1078

1077

1079

/* default */

1078

/* default */

1080

pindex = regno;

1079

pindex = regno;

1081

1080

1082

if (!rinfo->asleep) {

1081

if (!rinfo->asleep) {

1083

radeon_fifo_wait(9);

1082

radeon_fifo_wait(9);

1084

1083

1085

if (rinfo->bpp == 16) {

1084

if (rinfo->bpp == 16) {

1086

pindex = regno * 8;

1085

pindex = regno * 8;

1087

1086

1088

if (rinfo->depth == 16 && regno > 63)

1087

if (rinfo->depth == 16 && regno > 63)

1089

return 1;

1088

return 1;

1090

if (rinfo->depth == 15 && regno > 31)

1089

if (rinfo->depth == 15 && regno > 31)

1091

return 1;

1090

return 1;

1092

1091

1093

/* For 565, the green component is mixed one order

1092

/* For 565, the green component is mixed one order

1094

* below

1093

* below

1095

*/

1094

*/

1096

if (rinfo->depth == 16) {

1095

if (rinfo->depth == 16) {

1097

OUTREG(PALETTE_INDEX, pindex>>1);

1096

OUTREG(PALETTE_INDEX, pindex>>1);

1098

OUTREG(PALETTE_DATA,

1097

OUTREG(PALETTE_DATA,

1099

(rinfo->palette[regno>>1].red << 16) |

1098

(rinfo->palette[regno>>1].red << 16) |

1100

(green << 8) |

1099

(green << 8) |

1101

(rinfo->palette[regno>>1].blue));

1100

(rinfo->palette[regno>>1].blue));

1102

green = rinfo->palette[regno<<1].green;

1101

green = rinfo->palette[regno<<1].green;

1103

}

1102

}

1104

}

1103

}

1105

1104

1106

if (rinfo->depth != 16 || regno < 32) {

1105

if (rinfo->depth != 16 || regno < 32) {

1107

OUTREG(PALETTE_INDEX, pindex);

1106

OUTREG(PALETTE_INDEX, pindex);

1108

OUTREG(PALETTE_DATA, (red << 16) |

1107

OUTREG(PALETTE_DATA, (red << 16) |

1109

(green << 8) | blue);

1108

(green << 8) | blue);

1110

}

1109

}

1111

}

1110

}

1112

if (regno < 16) {

1111

if (regno < 16) {

1113

u32 *pal = rinfo->info->pseudo_palette;

1112

u32 *pal = rinfo->info->pseudo_palette;

1114

switch (rinfo->depth) {

1113

switch (rinfo->depth) {

1115

case 15:

1114

case 15:

1116

pal[regno] = (regno << 10) | (regno << 5) | regno;

1115

pal[regno] = (regno << 10) | (regno << 5) | regno;

1117

break;

1116

break;

1118

case 16:

1117

case 16:

1119

pal[regno] = (regno << 11) | (regno << 5) | regno;

1118

pal[regno] = (regno << 11) | (regno << 5) | regno;

1120

break;

1119

break;

1121

case 24:

1120

case 24:

1122

pal[regno] = (regno << 16) | (regno << 8) | regno;

1121

pal[regno] = (regno << 16) | (regno << 8) | regno;

1123

break;

1122

break;

1124

case 32:

1123

case 32:

1125

i = (regno << 8) | regno;

1124

i = (regno << 8) | regno;

1126

pal[regno] = (i << 16) | i;

1125

pal[regno] = (i << 16) | i;

1127

break;

1126

break;

1128

}

1127

}

1129

}

1128

}

1130

return 0;

1129

return 0;

1131

}

1130

}

1132

1131

1133

static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,

1132

static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,

1134

unsigned blue, unsigned transp,

1133

unsigned blue, unsigned transp,

1135

struct fb_info *info)

1134

struct fb_info *info)

1136

{

1135

{

1137

struct radeonfb_info *rinfo = info->par;

1136

struct radeonfb_info *rinfo = info->par;

1138

u32 dac_cntl2, vclk_cntl = 0;

1137

u32 dac_cntl2, vclk_cntl = 0;

1139

int rc;

1138

int rc;

1140

1139

1141

if (!rinfo->asleep) {

1140

if (!rinfo->asleep) {

1142

if (rinfo->is_mobility) {

1141

if (rinfo->is_mobility) {

1143

vclk_cntl = INPLL(VCLK_ECP_CNTL);

1142

vclk_cntl = INPLL(VCLK_ECP_CNTL);

1144

OUTPLL(VCLK_ECP_CNTL,

1143

OUTPLL(VCLK_ECP_CNTL,

1145

vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);

1144

vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);

1146

}

1145

}

1147

1146

1148

/* Make sure we are on first palette */

1147

/* Make sure we are on first palette */

1149

if (rinfo->has_CRTC2) {

1148

if (rinfo->has_CRTC2) {

1150

dac_cntl2 = INREG(DAC_CNTL2);

1149

dac_cntl2 = INREG(DAC_CNTL2);

1151

dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;

1150

dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;

1152

OUTREG(DAC_CNTL2, dac_cntl2);

1151

OUTREG(DAC_CNTL2, dac_cntl2);

1153

}

1152

}

1154

}

1153

}

1155

1154

1156

rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);

1155

rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);

1157

1156

1158

if (!rinfo->asleep && rinfo->is_mobility)

1157

if (!rinfo->asleep && rinfo->is_mobility)

1159

OUTPLL(VCLK_ECP_CNTL, vclk_cntl);

1158

OUTPLL(VCLK_ECP_CNTL, vclk_cntl);

1160

1159

1161

return rc;

1160

return rc;

1162

}

1161

}

1163

1162

1164

static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)

1163

static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)

1165

{

1164

{

1166

struct radeonfb_info *rinfo = info->par;

1165

struct radeonfb_info *rinfo = info->par;

1167

u16 *red, *green, *blue, *transp;

1166

u16 *red, *green, *blue, *transp;

1168

u32 dac_cntl2, vclk_cntl = 0;

1167

u32 dac_cntl2, vclk_cntl = 0;

1169

int i, start, rc = 0;

1168

int i, start, rc = 0;

1170

1169

1171

if (!rinfo->asleep) {

1170

if (!rinfo->asleep) {

1172

if (rinfo->is_mobility) {

1171

if (rinfo->is_mobility) {

1173

vclk_cntl = INPLL(VCLK_ECP_CNTL);

1172

vclk_cntl = INPLL(VCLK_ECP_CNTL);

1174

OUTPLL(VCLK_ECP_CNTL,

1173

OUTPLL(VCLK_ECP_CNTL,

1175

vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);

1174

vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);

1176

}

1175

}

1177

1176

1178

/* Make sure we are on first palette */

1177

/* Make sure we are on first palette */

1179

if (rinfo->has_CRTC2) {

1178

if (rinfo->has_CRTC2) {

1180

dac_cntl2 = INREG(DAC_CNTL2);

1179

dac_cntl2 = INREG(DAC_CNTL2);

1181

dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;

1180

dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;

1182

OUTREG(DAC_CNTL2, dac_cntl2);

1181

OUTREG(DAC_CNTL2, dac_cntl2);

1183

}

1182

}

1184

}

1183

}

1185

1184

1186

red = cmap->red;

1185

red = cmap->red;

1187

green = cmap->green;

1186

green = cmap->green;

1188

blue = cmap->blue;

1187

blue = cmap->blue;

1189

transp = cmap->transp;

1188

transp = cmap->transp;

1190

start = cmap->start;

1189

start = cmap->start;

1191

1190

1192

for (i = 0; i < cmap->len; i++) {

1191

for (i = 0; i < cmap->len; i++) {

1193

u_int hred, hgreen, hblue, htransp = 0xffff;

1192

u_int hred, hgreen, hblue, htransp = 0xffff;

1194

1193

1195

hred = *red++;

1194

hred = *red++;

1196

hgreen = *green++;

1195

hgreen = *green++;

1197

hblue = *blue++;

1196

hblue = *blue++;

1198

if (transp)

1197

if (transp)

1199

htransp = *transp++;

1198

htransp = *transp++;

1200

rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,

1199

rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,

1201

rinfo);

1200

rinfo);

1202

if (rc)

1201

if (rc)

1203

break;

1202

break;

1204

}

1203

}

1205

1204

1206

if (!rinfo->asleep && rinfo->is_mobility)

1205

if (!rinfo->asleep && rinfo->is_mobility)

1207

OUTPLL(VCLK_ECP_CNTL, vclk_cntl);

1206

OUTPLL(VCLK_ECP_CNTL, vclk_cntl);

1208

1207

1209

return rc;

1208

return rc;

1210

}

1209

}

1211

1210

1212

static void radeon_save_state (struct radeonfb_info *rinfo,

1211

static void radeon_save_state (struct radeonfb_info *rinfo,

1213

struct radeon_regs *save)

1212

struct radeon_regs *save)

1214

{

1213

{

1215

/* CRTC regs */

1214

/* CRTC regs */

1216

save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);

1215

save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);

1217

save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);

1216

save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);

1218

save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);

1217

save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);

1219

save->dac_cntl = INREG(DAC_CNTL);

1218

save->dac_cntl = INREG(DAC_CNTL);

1220

save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);

1219

save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);

1221

save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);

1220

save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);

1222

save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);

1221

save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);

1223

save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);

1222

save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);

1224

save->crtc_pitch = INREG(CRTC_PITCH);

1223

save->crtc_pitch = INREG(CRTC_PITCH);

1225

save->surface_cntl = INREG(SURFACE_CNTL);

1224

save->surface_cntl = INREG(SURFACE_CNTL);

1226

1225

1227

/* FP regs */

1226

/* FP regs */

1228

save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);

1227

save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);

1229

save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);

1228

save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);

1230

save->fp_gen_cntl = INREG(FP_GEN_CNTL);

1229

save->fp_gen_cntl = INREG(FP_GEN_CNTL);

1231

save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);

1230

save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);

1232

save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);

1231

save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);

1233

save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);

1232

save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);

1234

save->fp_vert_stretch = INREG(FP_VERT_STRETCH);

1233

save->fp_vert_stretch = INREG(FP_VERT_STRETCH);

1235

save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);

1234

save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);

1236

save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);

1235

save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);

1237

save->tmds_crc = INREG(TMDS_CRC);

1236

save->tmds_crc = INREG(TMDS_CRC);

1238

save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);

1237

save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);

1239

save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);

1238

save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);

1240

1239

1241

/* PLL regs */

1240

/* PLL regs */

1242

save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;

1241

save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;

1243

radeon_pll_errata_after_index(rinfo);

1242

radeon_pll_errata_after_index(rinfo);

1244

save->ppll_div_3 = INPLL(PPLL_DIV_3);

1243

save->ppll_div_3 = INPLL(PPLL_DIV_3);

1245

save->ppll_ref_div = INPLL(PPLL_REF_DIV);

1244

save->ppll_ref_div = INPLL(PPLL_REF_DIV);

1246

}

1245

}

1247

1246

1248

1247

1249

static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)

1248

static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)

1250

{

1249

{

1251

int i;

1250

int i;

1252

1251

1253

radeon_fifo_wait(20);

1252

radeon_fifo_wait(20);

1254

1253

1255

/* Workaround from XFree */

1254

/* Workaround from XFree */

1256

if (rinfo->is_mobility) {

1255

if (rinfo->is_mobility) {

1257

/* A temporal workaround for the occational blanking on certain laptop

1256

/* A temporal workaround for the occational blanking on certain laptop

1258

* panels. This appears to related to the PLL divider registers

1257

* panels. This appears to related to the PLL divider registers

1259

* (fail to lock?). It occurs even when all dividers are the same

1258

* (fail to lock?). It occurs even when all dividers are the same

1260

* with their old settings. In this case we really don't need to

1259

* with their old settings. In this case we really don't need to

1261

* fiddle with PLL registers. By doing this we can avoid the blanking

1260

* fiddle with PLL registers. By doing this we can avoid the blanking

1262

* problem with some panels.

1261

* problem with some panels.

1263

*/

1262

*/

1264

if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&

1263

if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&

1265

(mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &

1264

(mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &

1266

(PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {

1265

(PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {

1267

/* We still have to force a switch to selected PPLL div thanks to

1266

/* We still have to force a switch to selected PPLL div thanks to

1268

* an XFree86 driver bug which will switch it away in some cases

1267

* an XFree86 driver bug which will switch it away in some cases

1269

* even when using UseFDev */

1268

* even when using UseFDev */

1270

OUTREGP(CLOCK_CNTL_INDEX,

1269

OUTREGP(CLOCK_CNTL_INDEX,

1271

mode->clk_cntl_index & PPLL_DIV_SEL_MASK,

1270

mode->clk_cntl_index & PPLL_DIV_SEL_MASK,

1272

~PPLL_DIV_SEL_MASK);

1271

~PPLL_DIV_SEL_MASK);

1273

radeon_pll_errata_after_index(rinfo);

1272

radeon_pll_errata_after_index(rinfo);

1274

radeon_pll_errata_after_data(rinfo);

1273

radeon_pll_errata_after_data(rinfo);

1275

return;

1274

return;

1276

}

1275

}

1277

}

1276

}

1278

1277

1279

/* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/

1278

/* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/

1280

OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);

1279

OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);

1281

1280

1282

/* Reset PPLL & enable atomic update */

1281

/* Reset PPLL & enable atomic update */

1283

OUTPLLP(PPLL_CNTL,

1282

OUTPLLP(PPLL_CNTL,

1284

PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,

1283

PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,

1285

~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));

1284

~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));

1286

1285

1287

/* Switch to selected PPLL divider */

1286

/* Switch to selected PPLL divider */

1288

OUTREGP(CLOCK_CNTL_INDEX,

1287

OUTREGP(CLOCK_CNTL_INDEX,

1289

mode->clk_cntl_index & PPLL_DIV_SEL_MASK,

1288

mode->clk_cntl_index & PPLL_DIV_SEL_MASK,

1290

~PPLL_DIV_SEL_MASK);

1289

~PPLL_DIV_SEL_MASK);

1291

radeon_pll_errata_after_index(rinfo);

1290

radeon_pll_errata_after_index(rinfo);

1292

radeon_pll_errata_after_data(rinfo);

1291

radeon_pll_errata_after_data(rinfo);

1293

1292

1294

/* Set PPLL ref. div */

1293

/* Set PPLL ref. div */

1295

if (rinfo->family == CHIP_FAMILY_R300 ||

1294

if (rinfo->family == CHIP_FAMILY_R300 ||

1296

rinfo->family == CHIP_FAMILY_RS300 ||

1295

rinfo->family == CHIP_FAMILY_RS300 ||

1297

rinfo->family == CHIP_FAMILY_R350 ||

1296

rinfo->family == CHIP_FAMILY_R350 ||

1298

rinfo->family == CHIP_FAMILY_RV350) {

1297

rinfo->family == CHIP_FAMILY_RV350) {

1299

if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {

1298

if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {

1300

/* When restoring console mode, use saved PPLL_REF_DIV

1299

/* When restoring console mode, use saved PPLL_REF_DIV

1301

* setting.

1300

* setting.

1302

*/

1301

*/

1303

OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);

1302

OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);

1304

} else {

1303

} else {

1305

/* R300 uses ref_div_acc field as real ref divider */

1304

/* R300 uses ref_div_acc field as real ref divider */

1306

OUTPLLP(PPLL_REF_DIV,

1305

OUTPLLP(PPLL_REF_DIV,

1307

(mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),

1306

(mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),

1308

~R300_PPLL_REF_DIV_ACC_MASK);

1307

~R300_PPLL_REF_DIV_ACC_MASK);

1309

}

1308

}

1310

} else

1309

} else

1311

OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);

1310

OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);

1312

1311

1313

/* Set PPLL divider 3 & post divider*/

1312

/* Set PPLL divider 3 & post divider*/

1314

OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);

1313

OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);

1315

OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);

1314

OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);

1316

1315

1317

/* Write update */

1316

/* Write update */

1318

while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)

1317

while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)

1319

;

1318

;

1320

OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);

1319

OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);

1321

1320

1322

/* Wait read update complete */

1321

/* Wait read update complete */

1323

/* FIXME: Certain revisions of R300 can't recover here. Not sure of

1322

/* FIXME: Certain revisions of R300 can't recover here. Not sure of

1324

the cause yet, but this workaround will mask the problem for now.

1323

the cause yet, but this workaround will mask the problem for now.

1325

Other chips usually will pass at the very first test, so the

1324

Other chips usually will pass at the very first test, so the

1326

workaround shouldn't have any effect on them. */

1325

workaround shouldn't have any effect on them. */

1327

for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)

1326

for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)

1328

;

1327

;

1329

1328

1330

OUTPLL(HTOTAL_CNTL, 0);

1329

OUTPLL(HTOTAL_CNTL, 0);

1331

1330

1332

/* Clear reset & atomic update */

1331

/* Clear reset & atomic update */

1333

OUTPLLP(PPLL_CNTL, 0,

1332

OUTPLLP(PPLL_CNTL, 0,

1334

~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));

1333

~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));

1335

1334

1336

/* We may want some locking ... oh well */

1335

/* We may want some locking ... oh well */

1337

radeon_msleep(5);

1336

radeon_msleep(5);

1338

1337

1339

/* Switch back VCLK source to PPLL */

1338

/* Switch back VCLK source to PPLL */

1340

OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);

1339

OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);

1341

}

1340

}

1342

1341

1343

/*

1342

/*

1344

* Timer function for delayed LVDS panel power up/down

1343

* Timer function for delayed LVDS panel power up/down

1345

*/

1344

*/

1346

static void radeon_lvds_timer_func(unsigned long data)

1345

static void radeon_lvds_timer_func(unsigned long data)

1347

{

1346

{

1348

struct radeonfb_info *rinfo = (struct radeonfb_info *)data;

1347

struct radeonfb_info *rinfo = (struct radeonfb_info *)data;

1349

1348

1350

radeon_engine_idle();

1349

radeon_engine_idle();

1351

1350

1352

OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);

1351

OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);

1353

}

1352

}

1354

1353

1355

/*

1354

/*

1356

* Apply a video mode. This will apply the whole register set, including

1355

* Apply a video mode. This will apply the whole register set, including

1357

* the PLL registers, to the card

1356

* the PLL registers, to the card

1358

*/

1357

*/

1359

void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,

1358

void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,

1360

int regs_only)

1359

int regs_only)

1361

{

1360

{

1362

int i;

1361

int i;

1363

int primary_mon = PRIMARY_MONITOR(rinfo);

1362

int primary_mon = PRIMARY_MONITOR(rinfo);

1364

1363

1365

if (nomodeset)

1364

if (nomodeset)

1366

return;

1365

return;

1367

1366

1368

if (!regs_only)

1367

if (!regs_only)

1369

radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);

1368

radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);

1370

1369

1371

radeon_fifo_wait(31);

1370

radeon_fifo_wait(31);

1372

for (i=0; i<10; i++)

1371

for (i=0; i<10; i++)

1373

OUTREG(common_regs[i].reg, common_regs[i].val);

1372

OUTREG(common_regs[i].reg, common_regs[i].val);

1374

1373

1375

/* Apply surface registers */

1374

/* Apply surface registers */

1376

for (i=0; i<8; i++) {

1375

for (i=0; i<8; i++) {

1377

OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);

1376

OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);

1378

OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);

1377

OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);

1379

OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);

1378

OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);

1380

}

1379

}

1381

1380

1382

OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);

1381

OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);

1383

OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,

1382

OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,

1384

~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));

1383

~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));

1385

OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);

1384

OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);

1386

OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);

1385

OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);

1387

OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);

1386

OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);

1388

OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);

1387

OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);

1389

OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);

1388

OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);

1390

OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);

1389

OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);

1391

OUTREG(CRTC_OFFSET, 0);

1390

OUTREG(CRTC_OFFSET, 0);

1392

OUTREG(CRTC_OFFSET_CNTL, 0);

1391

OUTREG(CRTC_OFFSET_CNTL, 0);

1393

OUTREG(CRTC_PITCH, mode->crtc_pitch);

1392

OUTREG(CRTC_PITCH, mode->crtc_pitch);

1394

OUTREG(SURFACE_CNTL, mode->surface_cntl);

1393

OUTREG(SURFACE_CNTL, mode->surface_cntl);

1395

1394

1396

radeon_write_pll_regs(rinfo, mode);

1395

radeon_write_pll_regs(rinfo, mode);

1397

1396

1398

if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {

1397

if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {

1399

radeon_fifo_wait(10);

1398

radeon_fifo_wait(10);

1400

OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);

1399

OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);

1401

OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);

1400

OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);

1402

OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);

1401

OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);

1403

OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);

1402

OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);

1404

OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);

1403

OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);

1405

OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);

1404

OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);

1406

OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);

1405

OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);

1407

OUTREG(TMDS_CRC, mode->tmds_crc);

1406

OUTREG(TMDS_CRC, mode->tmds_crc);

1408

OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);

1407

OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);

1409

}

1408

}

1410

1409

1411

if (!regs_only)

1410

if (!regs_only)

1412

radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);

1411

radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);

1413

1412

1414

radeon_fifo_wait(2);

1413

radeon_fifo_wait(2);

1415

OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);

1414

OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);

1416

1415

1417

return;

1416

return;

1418

}

1417

}

1419

1418

1420

/*

1419

/*

1421

* Calculate the PLL values for a given mode

1420

* Calculate the PLL values for a given mode

1422

*/

1421

*/

1423

static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,

1422

static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,

1424

unsigned long freq)

1423

unsigned long freq)

1425

{

1424

{

1426

const struct {

1425

const struct {

1427

int divider;

1426

int divider;

1428

int bitvalue;

1427

int bitvalue;

1429

} *post_div,

1428

} *post_div,

1430

post_divs[] = {

1429

post_divs[] = {

1431

{ 1, 0 },

1430

{ 1, 0 },

1432

{ 2, 1 },

1431

{ 2, 1 },

1433

{ 4, 2 },

1432

{ 4, 2 },

1434

{ 8, 3 },

1433

{ 8, 3 },

1435

{ 3, 4 },

1434

{ 3, 4 },

1436

{ 16, 5 },

1435

{ 16, 5 },

1437

{ 6, 6 },

1436

{ 6, 6 },

1438

{ 12, 7 },

1437

{ 12, 7 },

1439

{ 0, 0 },

1438

{ 0, 0 },

1440

};

1439

};

1441

int fb_div, pll_output_freq = 0;

1440

int fb_div, pll_output_freq = 0;

1442

int uses_dvo = 0;

1441

int uses_dvo = 0;

1443

1442

1444

/* Check if the DVO port is enabled and sourced from the primary CRTC. I'm

1443

/* Check if the DVO port is enabled and sourced from the primary CRTC. I'm

1445

* not sure which model starts having FP2_GEN_CNTL, I assume anything more

1444

* not sure which model starts having FP2_GEN_CNTL, I assume anything more

1446

* recent than an r(v)100...

1445

* recent than an r(v)100...

1447

*/

1446

*/

1448

#if 1

1447

#if 1

1449

/* XXX I had reports of flicker happening with the cinema display

1448

/* XXX I had reports of flicker happening with the cinema display

1450

* on TMDS1 that seem to be fixed if I also forbit odd dividers in

1449

* on TMDS1 that seem to be fixed if I also forbit odd dividers in

1451

* this case. This could just be a bandwidth calculation issue, I

1450

* this case. This could just be a bandwidth calculation issue, I

1452

* haven't implemented the bandwidth code yet, but in the meantime,

1451

* haven't implemented the bandwidth code yet, but in the meantime,

1453

* forcing uses_dvo to 1 fixes it and shouln't have bad side effects,

1452

* forcing uses_dvo to 1 fixes it and shouln't have bad side effects,

1454

* I haven't seen a case were were absolutely needed an odd PLL

1453

* I haven't seen a case were were absolutely needed an odd PLL

1455

* divider. I'll find a better fix once I have more infos on the

1454

* divider. I'll find a better fix once I have more infos on the

1456

* real cause of the problem.

1455

* real cause of the problem.

1457

*/

1456

*/

1458

while (rinfo->has_CRTC2) {

1457

while (rinfo->has_CRTC2) {

1459

u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);

1458

u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);

1460

u32 disp_output_cntl;

1459

u32 disp_output_cntl;

1461

int source;

1460

int source;

1462

1461

1463

/* FP2 path not enabled */

1462

/* FP2 path not enabled */

1464

if ((fp2_gen_cntl & FP2_ON) == 0)

1463

if ((fp2_gen_cntl & FP2_ON) == 0)

1465

break;

1464

break;

1466

/* Not all chip revs have the same format for this register,

1465

/* Not all chip revs have the same format for this register,

1467

* extract the source selection

1466

* extract the source selection

1468

*/

1467

*/

1469

if (rinfo->family == CHIP_FAMILY_R200 ||

1468

if (rinfo->family == CHIP_FAMILY_R200 ||

1470

rinfo->family == CHIP_FAMILY_R300 ||

1469

rinfo->family == CHIP_FAMILY_R300 ||

1471

rinfo->family == CHIP_FAMILY_R350 ||

1470

rinfo->family == CHIP_FAMILY_R350 ||

1472

rinfo->family == CHIP_FAMILY_RV350) {

1471

rinfo->family == CHIP_FAMILY_RV350) {

1473

source = (fp2_gen_cntl >> 10) & 0x3;

1472

source = (fp2_gen_cntl >> 10) & 0x3;

1474

/* sourced from transform unit, check for transform unit

1473

/* sourced from transform unit, check for transform unit

1475

* own source

1474

* own source

1476

*/

1475

*/

1477

if (source == 3) {

1476

if (source == 3) {

1478

disp_output_cntl = INREG(DISP_OUTPUT_CNTL);

1477

disp_output_cntl = INREG(DISP_OUTPUT_CNTL);

1479

source = (disp_output_cntl >> 12) & 0x3;

1478

source = (disp_output_cntl >> 12) & 0x3;

1480

}

1479

}

1481

} else

1480

} else

1482

source = (fp2_gen_cntl >> 13) & 0x1;

1481

source = (fp2_gen_cntl >> 13) & 0x1;

1483

/* sourced from CRTC2 -> exit */

1482

/* sourced from CRTC2 -> exit */

1484

if (source == 1)

1483

if (source == 1)

1485

break;

1484

break;

1486

1485

1487

/* so we end up on CRTC1, let's set uses_dvo to 1 now */

1486

/* so we end up on CRTC1, let's set uses_dvo to 1 now */

1488

uses_dvo = 1;

1487

uses_dvo = 1;

1489

break;

1488

break;

1490

}

1489

}

1491

#else

1490

#else

1492

uses_dvo = 1;

1491

uses_dvo = 1;

1493

#endif

1492

#endif

1494

if (freq > rinfo->pll.ppll_max)

1493

if (freq > rinfo->pll.ppll_max)

1495

freq = rinfo->pll.ppll_max;

1494

freq = rinfo->pll.ppll_max;

1496

if (freq*12 < rinfo->pll.ppll_min)

1495

if (freq*12 < rinfo->pll.ppll_min)

1497

freq = rinfo->pll.ppll_min / 12;

1496

freq = rinfo->pll.ppll_min / 12;

1498

RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",

1497

RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",

1499

freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);

1498

freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);

1500

1499

1501

for (post_div = &post_divs[0]; post_div->divider; ++post_div) {

1500

for (post_div = &post_divs[0]; post_div->divider; ++post_div) {

1502

pll_output_freq = post_div->divider * freq;

1501

pll_output_freq = post_div->divider * freq;

1503

/* If we output to the DVO port (external TMDS), we don't allow an

1502

/* If we output to the DVO port (external TMDS), we don't allow an

1504

* odd PLL divider as those aren't supported on this path

1503

* odd PLL divider as those aren't supported on this path

1505

*/

1504

*/

1506

if (uses_dvo && (post_div->divider & 1))

1505

if (uses_dvo && (post_div->divider & 1))

1507

continue;

1506

continue;

1508

if (pll_output_freq >= rinfo->pll.ppll_min &&

1507

if (pll_output_freq >= rinfo->pll.ppll_min &&

1509

pll_output_freq <= rinfo->pll.ppll_max)

1508

pll_output_freq <= rinfo->pll.ppll_max)

1510

break;

1509

break;

1511

}

1510

}

1512

1511

1513

/* If we fall through the bottom, try the "default value"

1512

/* If we fall through the bottom, try the "default value"

1514

given by the terminal post_div->bitvalue */

1513

given by the terminal post_div->bitvalue */

1515

if ( !post_div->divider ) {

1514

if ( !post_div->divider ) {

1516

post_div = &post_divs[post_div->bitvalue];

1515

post_div = &post_divs[post_div->bitvalue];

1517

pll_output_freq = post_div->divider * freq;

1516

pll_output_freq = post_div->divider * freq;

1518

}

1517

}

1519

RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",

1518

RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",

1520

rinfo->pll.ref_div, rinfo->pll.ref_clk,

1519

rinfo->pll.ref_div, rinfo->pll.ref_clk,

1521

pll_output_freq);

1520

pll_output_freq);

1522

1521

1523

/* If we fall through the bottom, try the "default value"

1522

/* If we fall through the bottom, try the "default value"

1524

given by the terminal post_div->bitvalue */

1523

given by the terminal post_div->bitvalue */

1525

if ( !post_div->divider ) {

1524

if ( !post_div->divider ) {

1526

post_div = &post_divs[post_div->bitvalue];

1525

post_div = &post_divs[post_div->bitvalue];

1527

pll_output_freq = post_div->divider * freq;

1526

pll_output_freq = post_div->divider * freq;

1528

}

1527

}

1529

RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",

1528

RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",

1530

rinfo->pll.ref_div, rinfo->pll.ref_clk,

1529

rinfo->pll.ref_div, rinfo->pll.ref_clk,

1531

pll_output_freq);

1530

pll_output_freq);

1532

1531

1533

fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,

1532

fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,

1534

rinfo->pll.ref_clk);

1533

rinfo->pll.ref_clk);

1535

regs->ppll_ref_div = rinfo->pll.ref_div;

1534

regs->ppll_ref_div = rinfo->pll.ref_div;

1536

regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);

1535

regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);

1537

1536

1538

RTRACE("post div = 0x%x\n", post_div->bitvalue);

1537

RTRACE("post div = 0x%x\n", post_div->bitvalue);

1539

RTRACE("fb_div = 0x%x\n", fb_div);

1538

RTRACE("fb_div = 0x%x\n", fb_div);

1540

RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);

1539

RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);

1541

}

1540

}

1542

1541

1543

static int radeonfb_set_par(struct fb_info *info)

1542

static int radeonfb_set_par(struct fb_info *info)

1544

{

1543

{

1545

struct radeonfb_info *rinfo = info->par;

1544

struct radeonfb_info *rinfo = info->par;

1546

struct fb_var_screeninfo *mode = &info->var;

1545

struct fb_var_screeninfo *mode = &info->var;

1547

struct radeon_regs *newmode;

1546

struct radeon_regs *newmode;

1548

int hTotal, vTotal, hSyncStart, hSyncEnd,

1547

int hTotal, vTotal, hSyncStart, hSyncEnd,

1549

hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;

1548

hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;

1550

u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};

1549

u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};

1551

u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};

1550

u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};

1552

u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;

1551

u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;

1553

int i, freq;

1552

int i, freq;

1554

int format = 0;

1553

int format = 0;

1555

int nopllcalc = 0;

1554

int nopllcalc = 0;

1556

int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;

1555

int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;

1557

int primary_mon = PRIMARY_MONITOR(rinfo);

1556

int primary_mon = PRIMARY_MONITOR(rinfo);

1558

int depth = var_to_depth(mode);

1557

int depth = var_to_depth(mode);

1559

int use_rmx = 0;

1558

int use_rmx = 0;

1560

1559

1561

newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);

1560

newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);

1562

if (!newmode)

1561

if (!newmode)

1563

return -ENOMEM;

1562

return -ENOMEM;

1564

1563

1565

/* We always want engine to be idle on a mode switch, even

1564

/* We always want engine to be idle on a mode switch, even

1566

* if we won't actually change the mode

1565

* if we won't actually change the mode

1567

*/

1566

*/

1568

radeon_engine_idle();

1567

radeon_engine_idle();

1569

1568

1570

hSyncStart = mode->xres + mode->right_margin;

1569

hSyncStart = mode->xres + mode->right_margin;

1571

hSyncEnd = hSyncStart + mode->hsync_len;

1570

hSyncEnd = hSyncStart + mode->hsync_len;

1572

hTotal = hSyncEnd + mode->left_margin;

1571

hTotal = hSyncEnd + mode->left_margin;

1573

1572

1574

vSyncStart = mode->yres + mode->lower_margin;

1573

vSyncStart = mode->yres + mode->lower_margin;

1575

vSyncEnd = vSyncStart + mode->vsync_len;

1574

vSyncEnd = vSyncStart + mode->vsync_len;

1576

vTotal = vSyncEnd + mode->upper_margin;

1575

vTotal = vSyncEnd + mode->upper_margin;

1577

pixClock = mode->pixclock;

1576

pixClock = mode->pixclock;

1578

1577

1579

sync = mode->sync;

1578

sync = mode->sync;

1580

h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;

1579

h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;

1581

v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;

1580

v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;

1582

1581

1583

if (primary_mon == MT_DFP || primary_mon == MT_LCD) {

1582

if (primary_mon == MT_DFP || primary_mon == MT_LCD) {

1584

if (rinfo->panel_info.xres < mode->xres)

1583

if (rinfo->panel_info.xres < mode->xres)

1585

mode->xres = rinfo->panel_info.xres;

1584

mode->xres = rinfo->panel_info.xres;

1586

if (rinfo->panel_info.yres < mode->yres)

1585

if (rinfo->panel_info.yres < mode->yres)

1587

mode->yres = rinfo->panel_info.yres;

1586

mode->yres = rinfo->panel_info.yres;

1588

1587

1589

hTotal = mode->xres + rinfo->panel_info.hblank;

1588

hTotal = mode->xres + rinfo->panel_info.hblank;

1590

hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;

1589

hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;

1591

hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;

1590

hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;

1592

1591

1593

vTotal = mode->yres + rinfo->panel_info.vblank;

1592

vTotal = mode->yres + rinfo->panel_info.vblank;

1594

vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;

1593

vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;

1595

vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;

1594

vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;

1596

1595

1597

h_sync_pol = !rinfo->panel_info.hAct_high;

1596

h_sync_pol = !rinfo->panel_info.hAct_high;

1598

v_sync_pol = !rinfo->panel_info.vAct_high;

1597

v_sync_pol = !rinfo->panel_info.vAct_high;

1599

1598

1600

pixClock = 100000000 / rinfo->panel_info.clock;

1599

pixClock = 100000000 / rinfo->panel_info.clock;

1601

1600

1602

if (rinfo->panel_info.use_bios_dividers) {

1601

if (rinfo->panel_info.use_bios_dividers) {

1603

nopllcalc = 1;

1602

nopllcalc = 1;

1604

newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |

1603

newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |

1605

(rinfo->panel_info.post_divider << 16);

1604

(rinfo->panel_info.post_divider << 16);

1606

newmode->ppll_ref_div = rinfo->panel_info.ref_divider;

1605

newmode->ppll_ref_div = rinfo->panel_info.ref_divider;

1607

}

1606

}

1608

}

1607

}

1609

dotClock = 1000000000 / pixClock;

1608

dotClock = 1000000000 / pixClock;

1610

freq = dotClock / 10; /* x100 */

1609

freq = dotClock / 10; /* x100 */

1611

1610

1612

RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",

1611

RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",

1613

hSyncStart, hSyncEnd, hTotal);

1612

hSyncStart, hSyncEnd, hTotal);

1614

RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",

1613

RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",

1615

vSyncStart, vSyncEnd, vTotal);

1614

vSyncStart, vSyncEnd, vTotal);

1616

1615

1617

hsync_wid = (hSyncEnd - hSyncStart) / 8;

1616

hsync_wid = (hSyncEnd - hSyncStart) / 8;

1618

vsync_wid = vSyncEnd - vSyncStart;

1617

vsync_wid = vSyncEnd - vSyncStart;

1619

if (hsync_wid == 0)

1618

if (hsync_wid == 0)

1620

hsync_wid = 1;

1619

hsync_wid = 1;

1621

else if (hsync_wid > 0x3f) /* max */

1620

else if (hsync_wid > 0x3f) /* max */

1622

hsync_wid = 0x3f;

1621

hsync_wid = 0x3f;

1623

1622

1624

if (vsync_wid == 0)

1623

if (vsync_wid == 0)

1625

vsync_wid = 1;

1624

vsync_wid = 1;

1626

else if (vsync_wid > 0x1f) /* max */

1625

else if (vsync_wid > 0x1f) /* max */

1627

vsync_wid = 0x1f;

1626

vsync_wid = 0x1f;

1628

1627

1629

hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;

1628

hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;

1630

vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;

1629

vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;

1631

1630

1632

cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;

1631

cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;

1633

1632

1634

format = radeon_get_dstbpp(depth);

1633

format = radeon_get_dstbpp(depth);

1635

bytpp = mode->bits_per_pixel >> 3;

1634

bytpp = mode->bits_per_pixel >> 3;

1636

1635

1637

if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))

1636

if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))

1638

hsync_fudge = hsync_fudge_fp[format-1];

1637

hsync_fudge = hsync_fudge_fp[format-1];

1639

else

1638

else

1640

hsync_fudge = hsync_adj_tab[format-1];

1639

hsync_fudge = hsync_adj_tab[format-1];

1641

1640

1642

hsync_start = hSyncStart - 8 + hsync_fudge;

1641

hsync_start = hSyncStart - 8 + hsync_fudge;

1643

1642

1644

newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |

1643

newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |

1645

(format << 8);

1644

(format << 8);

1646

1645

1647

/* Clear auto-center etc... */

1646

/* Clear auto-center etc... */

1648

newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;

1647

newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;

1649

newmode->crtc_more_cntl &= 0xfffffff0;

1648

newmode->crtc_more_cntl &= 0xfffffff0;

1650

1649

1651

if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {

1650

if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {

1652

newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;

1651

newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;

1653

if (mirror)

1652

if (mirror)

1654

newmode->crtc_ext_cntl |= CRTC_CRT_ON;

1653

newmode->crtc_ext_cntl |= CRTC_CRT_ON;

1655

1654

1656

newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |

1655

newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |

1657

CRTC_INTERLACE_EN);

1656

CRTC_INTERLACE_EN);

1658

} else {

1657

} else {

1659

newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |

1658

newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |

1660

CRTC_CRT_ON;

1659

CRTC_CRT_ON;

1661

}

1660

}

1662

1661

1663

newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |

1662

newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |

1664

DAC_8BIT_EN;

1663

DAC_8BIT_EN;

1665

1664

1666

newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |

1665

newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |

1667

(((mode->xres / 8) - 1) << 16));

1666

(((mode->xres / 8) - 1) << 16));

1668

1667

1669

newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |

1668

newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |

1670

(hsync_wid << 16) | (h_sync_pol << 23));

1669

(hsync_wid << 16) | (h_sync_pol << 23));

1671

1670

1672

newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |

1671

newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |

1673

((mode->yres - 1) << 16);

1672

((mode->yres - 1) << 16);

1674

1673

1675

newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |

1674

newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |

1676

(vsync_wid << 16) | (v_sync_pol << 23));

1675

(vsync_wid << 16) | (v_sync_pol << 23));

1677

1676

1678

if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {

1677

if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {

1679

/* We first calculate the engine pitch */

1678

/* We first calculate the engine pitch */

1680

rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)

1679

rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)

1681

& ~(0x3f)) >> 6;

1680

& ~(0x3f)) >> 6;

1682

1681

1683

/* Then, re-multiply it to get the CRTC pitch */

1682

/* Then, re-multiply it to get the CRTC pitch */

1684

newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);

1683

newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);

1685

} else

1684

} else

1686

newmode->crtc_pitch = (mode->xres_virtual >> 3);

1685

newmode->crtc_pitch = (mode->xres_virtual >> 3);

1687

1686

1688

newmode->crtc_pitch |= (newmode->crtc_pitch << 16);

1687

newmode->crtc_pitch |= (newmode->crtc_pitch << 16);

1689

1688

1690

/*

1689

/*

1691

* It looks like recent chips have a problem with SURFACE_CNTL,

1690

* It looks like recent chips have a problem with SURFACE_CNTL,

1692

* setting SURF_TRANSLATION_DIS completely disables the

1691

* setting SURF_TRANSLATION_DIS completely disables the

1693

* swapper as well, so we leave it unset now.

1692

* swapper as well, so we leave it unset now.

1694

*/

1693

*/

1695

newmode->surface_cntl = 0;

1694

newmode->surface_cntl = 0;

1696

1695

1697

#if defined(__BIG_ENDIAN)

1696

#if defined(__BIG_ENDIAN)

1698

1697

1699

/* Setup swapping on both apertures, though we currently

1698

/* Setup swapping on both apertures, though we currently

1700

* only use aperture 0, enabling swapper on aperture 1

1699

* only use aperture 0, enabling swapper on aperture 1

1701

* won't harm

1700

* won't harm

1702

*/

1701

*/

1703

switch (mode->bits_per_pixel) {

1702

switch (mode->bits_per_pixel) {

1704

case 16:

1703

case 16:

1705

newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;

1704

newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;

1706

newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;

1705

newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;

1707

break;

1706

break;

1708

case 24:

1707

case 24:

1709

case 32:

1708

case 32:

1710

newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;

1709

newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;

1711

newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;

1710

newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;

1712

break;

1711

break;

1713

}

1712

}

1714

#endif

1713

#endif

1715

1714

1716

/* Clear surface registers */

1715

/* Clear surface registers */

1717

for (i=0; i<8; i++) {

1716

for (i=0; i<8; i++) {

1718

newmode->surf_lower_bound[i] = 0;

1717

newmode->surf_lower_bound[i] = 0;

1719

newmode->surf_upper_bound[i] = 0x1f;

1718

newmode->surf_upper_bound[i] = 0x1f;

1720

newmode->surf_info[i] = 0;

1719

newmode->surf_info[i] = 0;

1721

}

1720

}

1722

1721

1723

RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",

1722

RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",

1724

newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);

1723

newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);

1725

RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",

1724

RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",

1726

newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);

1725

newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);

1727

1726

1728

rinfo->bpp = mode->bits_per_pixel;

1727

rinfo->bpp = mode->bits_per_pixel;

1729

rinfo->depth = depth;

1728

rinfo->depth = depth;

1730

1729

1731

RTRACE("pixclock = %lu\n", (unsigned long)pixClock);

1730

RTRACE("pixclock = %lu\n", (unsigned long)pixClock);

1732

RTRACE("freq = %lu\n", (unsigned long)freq);

1731

RTRACE("freq = %lu\n", (unsigned long)freq);

1733

1732

1734

/* We use PPLL_DIV_3 */

1733

/* We use PPLL_DIV_3 */

1735

newmode->clk_cntl_index = 0x300;

1734

newmode->clk_cntl_index = 0x300;

1736

1735

1737

/* Calculate PPLL value if necessary */

1736

/* Calculate PPLL value if necessary */

1738

if (!nopllcalc)

1737

if (!nopllcalc)

1739

radeon_calc_pll_regs(rinfo, newmode, freq);

1738

radeon_calc_pll_regs(rinfo, newmode, freq);

1740

1739

1741

newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;

1740

newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;

1742

1741

1743

if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {

1742

if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {

1744

unsigned int hRatio, vRatio;

1743

unsigned int hRatio, vRatio;

1745

1744

1746

if (mode->xres > rinfo->panel_info.xres)

1745

if (mode->xres > rinfo->panel_info.xres)

1747

mode->xres = rinfo->panel_info.xres;

1746

mode->xres = rinfo->panel_info.xres;

1748

if (mode->yres > rinfo->panel_info.yres)

1747

if (mode->yres > rinfo->panel_info.yres)

1749

mode->yres = rinfo->panel_info.yres;

1748

mode->yres = rinfo->panel_info.yres;

1750

1749

1751

newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)

1750

newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)

1752

<< HORZ_PANEL_SHIFT);

1751

<< HORZ_PANEL_SHIFT);

1753

newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)

1752

newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)

1754

<< VERT_PANEL_SHIFT);

1753

<< VERT_PANEL_SHIFT);

1755

1754

1756

if (mode->xres != rinfo->panel_info.xres) {

1755

if (mode->xres != rinfo->panel_info.xres) {

1757

hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,

1756

hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,

1758

rinfo->panel_info.xres);

1757

rinfo->panel_info.xres);

1759

newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |

1758

newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |

1760

(newmode->fp_horz_stretch &

1759

(newmode->fp_horz_stretch &

1761

(HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |

1760

(HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |

1762

HORZ_AUTO_RATIO_INC)));

1761

HORZ_AUTO_RATIO_INC)));

1763

newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |

1762

newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |

1764

HORZ_STRETCH_ENABLE);

1763

HORZ_STRETCH_ENABLE);

1765

use_rmx = 1;

1764

use_rmx = 1;

1766

}

1765

}

1767

newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;

1766

newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;

1768

1767

1769

if (mode->yres != rinfo->panel_info.yres) {

1768

if (mode->yres != rinfo->panel_info.yres) {

1770

vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,

1769

vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,

1771

rinfo->panel_info.yres);

1770

rinfo->panel_info.yres);

1772

newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |

1771

newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |

1773

(newmode->fp_vert_stretch &

1772

(newmode->fp_vert_stretch &

1774

(VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));

1773

(VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));

1775

newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |

1774

newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |

1776

VERT_STRETCH_ENABLE);

1775

VERT_STRETCH_ENABLE);

1777

use_rmx = 1;

1776

use_rmx = 1;

1778

}

1777

}

1779

newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;

1778

newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;

1780

1779

1781

newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)

1780

newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)

1782

~(FP_SEL_CRTC2 |

1781

~(FP_SEL_CRTC2 |

1783

FP_RMX_HVSYNC_CONTROL_EN |

1782

FP_RMX_HVSYNC_CONTROL_EN |

1784

FP_DFP_SYNC_SEL |

1783

FP_DFP_SYNC_SEL |

1785

FP_CRT_SYNC_SEL |

1784

FP_CRT_SYNC_SEL |

1786

FP_CRTC_LOCK_8DOT |

1785

FP_CRTC_LOCK_8DOT |

1787

FP_USE_SHADOW_EN |

1786

FP_USE_SHADOW_EN |

1788

FP_CRTC_USE_SHADOW_VEND |

1787

FP_CRTC_USE_SHADOW_VEND |

1789

FP_CRT_SYNC_ALT));

1788

FP_CRT_SYNC_ALT));

1790

1789

1791

newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |

1790

newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |

1792

FP_CRTC_DONT_SHADOW_HEND |

1791

FP_CRTC_DONT_SHADOW_HEND |

1793

FP_PANEL_FORMAT);

1792

FP_PANEL_FORMAT);

1794

1793

1795

if (IS_R300_VARIANT(rinfo) ||

1794

if (IS_R300_VARIANT(rinfo) ||

1796

(rinfo->family == CHIP_FAMILY_R200)) {

1795

(rinfo->family == CHIP_FAMILY_R200)) {

1797

newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;

1796

newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;

1798

if (use_rmx)

1797

if (use_rmx)

1799

newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;

1798

newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;

1800

else

1799

else

1801

newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;

1800

newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;

1802

} else

1801

} else

1803

newmode->fp_gen_cntl |= FP_SEL_CRTC1;

1802

newmode->fp_gen_cntl |= FP_SEL_CRTC1;

1804

1803

1805

newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;

1804

newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;

1806

newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;

1805

newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;

1807

newmode->tmds_crc = rinfo->init_state.tmds_crc;

1806

newmode->tmds_crc = rinfo->init_state.tmds_crc;

1808

newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;

1807

newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;

1809

1808

1810

if (primary_mon == MT_LCD) {

1809

if (primary_mon == MT_LCD) {

1811

newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);

1810

newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);

1812

newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);

1811

newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);

1813

} else {

1812

} else {

1814

/* DFP */

1813

/* DFP */

1815

newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);

1814

newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);

1816

newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);

1815

newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);

1817

/* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */

1816

/* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */

1818

if (IS_R300_VARIANT(rinfo) ||

1817

if (IS_R300_VARIANT(rinfo) ||

1819

(rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)

1818

(rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)

1820

newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;

1819

newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;

1821

else

1820

else

1822

newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;

1821

newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;

1823

newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;

1822

newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;

1824

}

1823

}

1825

1824

1826

newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |

1825

newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |

1827

(((mode->xres / 8) - 1) << 16));

1826

(((mode->xres / 8) - 1) << 16));

1828

newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |

1827

newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |

1829

((mode->yres - 1) << 16);

1828

((mode->yres - 1) << 16);

1830

newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |

1829

newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |

1831

(hsync_wid << 16) | (h_sync_pol << 23));

1830

(hsync_wid << 16) | (h_sync_pol << 23));

1832

newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |

1831

newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |

1833

(vsync_wid << 16) | (v_sync_pol << 23));

1832

(vsync_wid << 16) | (v_sync_pol << 23));

1834

}

1833

}

1835

1834

1836

/* do it! */

1835

/* do it! */

1837

if (!rinfo->asleep) {

1836

if (!rinfo->asleep) {

1838

memcpy(&rinfo->state, newmode, sizeof(*newmode));

1837

memcpy(&rinfo->state, newmode, sizeof(*newmode));

1839

radeon_write_mode (rinfo, newmode, 0);

1838

radeon_write_mode (rinfo, newmode, 0);

1840

/* (re)initialize the engine */

1839

/* (re)initialize the engine */

1841

if (!(info->flags & FBINFO_HWACCEL_DISABLED))

1840

if (!(info->flags & FBINFO_HWACCEL_DISABLED))

1842

radeonfb_engine_init (rinfo);

1841

radeonfb_engine_init (rinfo);

1843

}

1842

}

1844

/* Update fix */

1843

/* Update fix */

1845

if (!(info->flags & FBINFO_HWACCEL_DISABLED))

1844

if (!(info->flags & FBINFO_HWACCEL_DISABLED))

1846

info->fix.line_length = rinfo->pitch*64;

1845

info->fix.line_length = rinfo->pitch*64;

1847

else

1846

else

1848

info->fix.line_length = mode->xres_virtual

1847

info->fix.line_length = mode->xres_virtual

1849

* ((mode->bits_per_pixel + 1) / 8);

1848

* ((mode->bits_per_pixel + 1) / 8);

1850

info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR

1849

info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR

1851

: FB_VISUAL_DIRECTCOLOR;

1850

: FB_VISUAL_DIRECTCOLOR;

1852

1851

1853

#ifdef CONFIG_BOOTX_TEXT

1852

#ifdef CONFIG_BOOTX_TEXT

1854

/* Update debug text engine */

1853

/* Update debug text engine */

1855

btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,

1854

btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,

1856

rinfo->depth, info->fix.line_length);

1855

rinfo->depth, info->fix.line_length);

1857

#endif

1856

#endif

1858

1857

1859

kfree(newmode);

1858

kfree(newmode);

1860

return 0;

1859

return 0;

1861

}

1860

}

1862

1861

1863

1862

1864

static struct fb_ops radeonfb_ops = {

1863

static struct fb_ops radeonfb_ops = {

1865

.owner = THIS_MODULE,

1864

.owner = THIS_MODULE,

1866

.fb_check_var = radeonfb_check_var,

1865

.fb_check_var = radeonfb_check_var,

1867

.fb_set_par = radeonfb_set_par,

1866

.fb_set_par = radeonfb_set_par,

1868

.fb_setcolreg = radeonfb_setcolreg,

1867

.fb_setcolreg = radeonfb_setcolreg,

1869

.fb_setcmap = radeonfb_setcmap,

1868

.fb_setcmap = radeonfb_setcmap,

1870

.fb_pan_display = radeonfb_pan_display,

1869

.fb_pan_display = radeonfb_pan_display,

1871

.fb_blank = radeonfb_blank,

1870

.fb_blank = radeonfb_blank,

1872

.fb_ioctl = radeonfb_ioctl,

1871

.fb_ioctl = radeonfb_ioctl,

1873

.fb_sync = radeonfb_sync,

1872

.fb_sync = radeonfb_sync,

1874

.fb_fillrect = radeonfb_fillrect,

1873

.fb_fillrect = radeonfb_fillrect,

1875

.fb_copyarea = radeonfb_copyarea,

1874

.fb_copyarea = radeonfb_copyarea,

1876

.fb_imageblit = radeonfb_imageblit,

1875

.fb_imageblit = radeonfb_imageblit,

1877

.fb_cursor = soft_cursor,

1876

.fb_cursor = soft_cursor,

1878

};

1877

};

1879

1878

1880

1879

1881

static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)

1880

static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)

1882

{

1881

{

1883

struct fb_info *info = rinfo->info;

1882

struct fb_info *info = rinfo->info;

1884

1883

1885

info->par = rinfo;

1884

info->par = rinfo;

1886

info->pseudo_palette = rinfo->pseudo_palette;

1885

info->pseudo_palette = rinfo->pseudo_palette;

1887

info->flags = FBINFO_DEFAULT

1886

info->flags = FBINFO_DEFAULT

1888

| FBINFO_HWACCEL_COPYAREA

1887

| FBINFO_HWACCEL_COPYAREA

1889

| FBINFO_HWACCEL_FILLRECT

1888

| FBINFO_HWACCEL_FILLRECT

1890

| FBINFO_HWACCEL_XPAN

1889

| FBINFO_HWACCEL_XPAN

1891

| FBINFO_HWACCEL_YPAN;

1890

| FBINFO_HWACCEL_YPAN;

1892

info->fbops = &radeonfb_ops;

1891

info->fbops = &radeonfb_ops;

1893

info->screen_base = rinfo->fb_base;

1892

info->screen_base = rinfo->fb_base;

1894

info->screen_size = rinfo->mapped_vram;

1893

info->screen_size = rinfo->mapped_vram;

1895

/* Fill fix common fields */

1894

/* Fill fix common fields */

1896

strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));

1895

strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));

1897

info->fix.smem_start = rinfo->fb_base_phys;

1896

info->fix.smem_start = rinfo->fb_base_phys;

1898

info->fix.smem_len = rinfo->video_ram;

1897

info->fix.smem_len = rinfo->video_ram;

1899

info->fix.type = FB_TYPE_PACKED_PIXELS;

1898

info->fix.type = FB_TYPE_PACKED_PIXELS;

1900

info->fix.visual = FB_VISUAL_PSEUDOCOLOR;

1899

info->fix.visual = FB_VISUAL_PSEUDOCOLOR;

1901

info->fix.xpanstep = 8;

1900

info->fix.xpanstep = 8;

1902

info->fix.ypanstep = 1;

1901

info->fix.ypanstep = 1;

1903

info->fix.ywrapstep = 0;

1902

info->fix.ywrapstep = 0;

1904

info->fix.type_aux = 0;

1903

info->fix.type_aux = 0;

1905

info->fix.mmio_start = rinfo->mmio_base_phys;

1904

info->fix.mmio_start = rinfo->mmio_base_phys;

1906

info->fix.mmio_len = RADEON_REGSIZE;

1905

info->fix.mmio_len = RADEON_REGSIZE;

1907

info->fix.accel = FB_ACCEL_ATI_RADEON;

1906

info->fix.accel = FB_ACCEL_ATI_RADEON;

1908

1907

1909

fb_alloc_cmap(&info->cmap, 256, 0);

1908

fb_alloc_cmap(&info->cmap, 256, 0);

1910

1909

1911

if (noaccel)

1910

if (noaccel)

1912

info->flags |= FBINFO_HWACCEL_DISABLED;

1911

info->flags |= FBINFO_HWACCEL_DISABLED;

1913

1912

1914

return 0;

1913

return 0;

1915

}

1914

}

1916

1915

1917

1916

1918

#ifdef CONFIG_PMAC_BACKLIGHT

1917

#ifdef CONFIG_PMAC_BACKLIGHT

1919

1918

1920

/* TODO: Dbl check these tables, we don't go up to full ON backlight

1919

/* TODO: Dbl check these tables, we don't go up to full ON backlight

1921

* in these, possibly because we noticed MacOS doesn't, but I'd prefer

1920

* in these, possibly because we noticed MacOS doesn't, but I'd prefer

1922

* having some more official numbers from ATI

1921

* having some more official numbers from ATI

1923

*/

1922

*/

1924

static int backlight_conv_m6[] = {

1923

static int backlight_conv_m6[] = {

1925

0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,

1924

0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,

1926

0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24

1925

0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24

1927

};

1926

};

1928

static int backlight_conv_m7[] = {

1927

static int backlight_conv_m7[] = {

1929

0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,

1928

0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,

1930

0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9

1929

0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9

1931

};

1930

};

1932

1931

1933

#define BACKLIGHT_LVDS_OFF

1932

#define BACKLIGHT_LVDS_OFF

1934

#undef BACKLIGHT_DAC_OFF

1933

#undef BACKLIGHT_DAC_OFF

1935

1934

1936

/* We turn off the LCD completely instead of just dimming the backlight.

1935

/* We turn off the LCD completely instead of just dimming the backlight.

1937

* This provides some greater power saving and the display is useless

1936

* This provides some greater power saving and the display is useless

1938

* without backlight anyway.

1937

* without backlight anyway.

1939

*/

1938

*/

1940

static int radeon_set_backlight_enable(int on, int level, void *data)

1939

static int radeon_set_backlight_enable(int on, int level, void *data)

1941

{

1940

{

1942

struct radeonfb_info *rinfo = (struct radeonfb_info *)data;

1941

struct radeonfb_info *rinfo = (struct radeonfb_info *)data;

1943

u32 lvds_gen_cntl, tmpPixclksCntl;

1942

u32 lvds_gen_cntl, tmpPixclksCntl;

1944

int* conv_table;

1943

int* conv_table;

1945

1944

1946

if (rinfo->mon1_type != MT_LCD)

1945

if (rinfo->mon1_type != MT_LCD)

1947

return 0;

1946

return 0;

1948

1947

1949

/* Pardon me for that hack... maybe some day we can figure

1948

/* Pardon me for that hack... maybe some day we can figure

1950

* out in what direction backlight should work on a given

1949

* out in what direction backlight should work on a given

1951

* panel ?

1950

* panel ?

1952

*/

1951

*/

1953

if ((rinfo->family == CHIP_FAMILY_RV200 ||

1952

if ((rinfo->family == CHIP_FAMILY_RV200 ||

1954

rinfo->family == CHIP_FAMILY_RV250 ||

1953

rinfo->family == CHIP_FAMILY_RV250 ||

1955

rinfo->family == CHIP_FAMILY_RV280 ||

1954

rinfo->family == CHIP_FAMILY_RV280 ||

1956

rinfo->family == CHIP_FAMILY_RV350) &&

1955

rinfo->family == CHIP_FAMILY_RV350) &&

1957

!machine_is_compatible("PowerBook4,3") &&

1956

!machine_is_compatible("PowerBook4,3") &&

1958

!machine_is_compatible("PowerBook6,3") &&

1957

!machine_is_compatible("PowerBook6,3") &&

1959

!machine_is_compatible("PowerBook6,5"))

1958

!machine_is_compatible("PowerBook6,5"))

1960

conv_table = backlight_conv_m7;

1959

conv_table = backlight_conv_m7;

1961

else

1960

else

1962

conv_table = backlight_conv_m6;

1961

conv_table = backlight_conv_m6;

1963

1962

1964

del_timer_sync(&rinfo->lvds_timer);

1963

del_timer_sync(&rinfo->lvds_timer);

1965

radeon_engine_idle();

1964

radeon_engine_idle();

1966

1965

1967

lvds_gen_cntl = INREG(LVDS_GEN_CNTL);

1966

lvds_gen_cntl = INREG(LVDS_GEN_CNTL);

1968

if (on && (level > BACKLIGHT_OFF)) {

1967

if (on && (level > BACKLIGHT_OFF)) {

1969

lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;

1968

lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;

1970

if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) {

1969

if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) {

1971

lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON);

1970

lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON);

1972

lvds_gen_cntl |= LVDS_BLON | LVDS_EN;

1971

lvds_gen_cntl |= LVDS_BLON | LVDS_EN;

1973

OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);

1972

OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);

1974

lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;

1973

lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;

1975

lvds_gen_cntl |= (conv_table[level] <<

1974

lvds_gen_cntl |= (conv_table[level] <<

1976

LVDS_BL_MOD_LEVEL_SHIFT);

1975

LVDS_BL_MOD_LEVEL_SHIFT);

1977

lvds_gen_cntl |= LVDS_ON;

1976

lvds_gen_cntl |= LVDS_ON;

1978

lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN);

1977

lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN);

1979

rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;

1978

rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;

1980

mod_timer(&rinfo->lvds_timer,

1979

mod_timer(&rinfo->lvds_timer,

1981

jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));

1980

jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));

1982

} else {

1981

} else {

1983

lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;

1982

lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;

1984

lvds_gen_cntl |= (conv_table[level] <<

1983

lvds_gen_cntl |= (conv_table[level] <<

1985

LVDS_BL_MOD_LEVEL_SHIFT);

1984

LVDS_BL_MOD_LEVEL_SHIFT);

1986

OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);

1985

OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);

1987

}

1986

}

1988

rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;

1987

rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;

1989

rinfo->init_state.lvds_gen_cntl |= rinfo->pending_lvds_gen_cntl

1988

rinfo->init_state.lvds_gen_cntl |= rinfo->pending_lvds_gen_cntl

1990

& LVDS_STATE_MASK;

1989

& LVDS_STATE_MASK;

1991

} else {

1990

} else {

1992

/* Asic bug, when turning off LVDS_ON, we have to make sure

1991

/* Asic bug, when turning off LVDS_ON, we have to make sure

1993

RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off

1992

RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off

1994

*/

1993

*/

1995

tmpPixclksCntl = INPLL(PIXCLKS_CNTL);

1994

tmpPixclksCntl = INPLL(PIXCLKS_CNTL);

1996

if (rinfo->is_mobility || rinfo->is_IGP)

1995

if (rinfo->is_mobility || rinfo->is_IGP)

1997

OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);

1996

OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);

1998

lvds_gen_cntl &= ~(LVDS_BL_MOD_LEVEL_MASK | LVDS_BL_MOD_EN);

1997

lvds_gen_cntl &= ~(LVDS_BL_MOD_LEVEL_MASK | LVDS_BL_MOD_EN);

1999

lvds_gen_cntl |= (conv_table[0] <<

1998

lvds_gen_cntl |= (conv_table[0] <<

2000

LVDS_BL_MOD_LEVEL_SHIFT);

1999

LVDS_BL_MOD_LEVEL_SHIFT);

2001

lvds_gen_cntl |= LVDS_DISPLAY_DIS;

2000

lvds_gen_cntl |= LVDS_DISPLAY_DIS;

2002

OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);

2001

OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);

2003

udelay(100);

2002

udelay(100);

2004

lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN);

2003

lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN);

2005

OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);

2004

OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);

2006

lvds_gen_cntl &= ~(LVDS_DIGON);

2005

lvds_gen_cntl &= ~(LVDS_DIGON);

2007

rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;

2006

rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;

2008

mod_timer(&rinfo->lvds_timer,

2007

mod_timer(&rinfo->lvds_timer,

2009

jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));

2008

jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));

2010

if (rinfo->is_mobility || rinfo->is_IGP)

2009

if (rinfo->is_mobility || rinfo->is_IGP)

2011

OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);

2010

OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);

2012

}

2011

}

2013

rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;

2012

rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;

2014

rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);

2013

rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);

2015

2014

2016

return 0;

2015

return 0;

2017

}

2016

}

2018

2017

2019

2018

2020

static int radeon_set_backlight_level(int level, void *data)

2019

static int radeon_set_backlight_level(int level, void *data)

2021

{

2020

{

2022

return radeon_set_backlight_enable(1, level, data);

2021

return radeon_set_backlight_enable(1, level, data);

2023

}

2022

}

2024

#endif /* CONFIG_PMAC_BACKLIGHT */

2023

#endif /* CONFIG_PMAC_BACKLIGHT */

2025

2024

2026

2025

2027

/*

2026

/*

2028

* This reconfigure the card's internal memory map. In theory, we'd like

2027

* This reconfigure the card's internal memory map. In theory, we'd like

2029

* to setup the card's memory at the same address as it's PCI bus address,

2028

* to setup the card's memory at the same address as it's PCI bus address,

2030

* and the AGP aperture right after that so that system RAM on 32 bits

2029

* and the AGP aperture right after that so that system RAM on 32 bits

2031

* machines at least, is directly accessible. However, doing so would

2030

* machines at least, is directly accessible. However, doing so would

2032

* conflict with the current XFree drivers...

2031

* conflict with the current XFree drivers...

2033

* Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree

2032

* Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree

2034

* on the proper way to set this up and duplicate this here. In the meantime,

2033

* on the proper way to set this up and duplicate this here. In the meantime,

2035

* I put the card's memory at 0 in card space and AGP at some random high

2034

* I put the card's memory at 0 in card space and AGP at some random high

2036

* local (0xe0000000 for now) that will be changed by XFree/DRI anyway

2035

* local (0xe0000000 for now) that will be changed by XFree/DRI anyway

2037

*/

2036

*/

2038

#ifdef CONFIG_PPC_OF

2037

#ifdef CONFIG_PPC_OF

2039

#undef SET_MC_FB_FROM_APERTURE

2038

#undef SET_MC_FB_FROM_APERTURE

2040

static void fixup_memory_mappings(struct radeonfb_info *rinfo)

2039

static void fixup_memory_mappings(struct radeonfb_info *rinfo)

2041

{

2040

{

2042

u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;

2041

u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;

2043

u32 save_crtc_ext_cntl;

2042

u32 save_crtc_ext_cntl;

2044

u32 aper_base, aper_size;

2043

u32 aper_base, aper_size;

2045

u32 agp_base;

2044

u32 agp_base;

2046

2045

2047

/* First, we disable display to avoid interfering */

2046

/* First, we disable display to avoid interfering */

2048

if (rinfo->has_CRTC2) {

2047

if (rinfo->has_CRTC2) {

2049

save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);

2048

save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);

2050

OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);

2049

OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);

2051

}

2050

}

2052

save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);

2051

save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);

2053

save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);

2052

save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);

2054

2053

2055

OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);

2054

OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);

2056

OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);

2055

OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);

2057

mdelay(100);

2056

mdelay(100);

2058

2057

2059

aper_base = INREG(CONFIG_APER_0_BASE);

2058

aper_base = INREG(CONFIG_APER_0_BASE);

2060

aper_size = INREG(CONFIG_APER_SIZE);

2059

aper_size = INREG(CONFIG_APER_SIZE);

2061

2060

2062

#ifdef SET_MC_FB_FROM_APERTURE

2061

#ifdef SET_MC_FB_FROM_APERTURE

2063

/* Set framebuffer to be at the same address as set in PCI BAR */

2062

/* Set framebuffer to be at the same address as set in PCI BAR */

2064

OUTREG(MC_FB_LOCATION,

2063

OUTREG(MC_FB_LOCATION,

2065

((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));

2064

((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));

2066

rinfo->fb_local_base = aper_base;

2065

rinfo->fb_local_base = aper_base;

2067

#else

2066

#else

2068

OUTREG(MC_FB_LOCATION, 0x7fff0000);

2067

OUTREG(MC_FB_LOCATION, 0x7fff0000);

2069

rinfo->fb_local_base = 0;

2068

rinfo->fb_local_base = 0;

2070

#endif

2069

#endif

2071

agp_base = aper_base + aper_size;

2070

agp_base = aper_base + aper_size;

2072

if (agp_base & 0xf0000000)

2071

if (agp_base & 0xf0000000)

2073

agp_base = (aper_base | 0x0fffffff) + 1;

2072

agp_base = (aper_base | 0x0fffffff) + 1;

2074

2073

2075

/* Set AGP to be just after the framebuffer on a 256Mb boundary. This

2074

/* Set AGP to be just after the framebuffer on a 256Mb boundary. This

2076

* assumes the FB isn't mapped to 0xf0000000 or above, but this is

2075

* assumes the FB isn't mapped to 0xf0000000 or above, but this is

2077

* always the case on PPCs afaik.

2076

* always the case on PPCs afaik.

2078

*/

2077

*/

2079

#ifdef SET_MC_FB_FROM_APERTURE

2078

#ifdef SET_MC_FB_FROM_APERTURE

2080

OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));

2079

OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));

2081

#else

2080

#else

2082

OUTREG(MC_AGP_LOCATION, 0xffffe000);

2081

OUTREG(MC_AGP_LOCATION, 0xffffe000);

2083

#endif

2082

#endif

2084

2083

2085

/* Fixup the display base addresses & engine offsets while we

2084

/* Fixup the display base addresses & engine offsets while we

2086

* are at it as well

2085

* are at it as well

2087

*/

2086

*/

2088

#ifdef SET_MC_FB_FROM_APERTURE

2087

#ifdef SET_MC_FB_FROM_APERTURE

2089

OUTREG(DISPLAY_BASE_ADDR, aper_base);

2088

OUTREG(DISPLAY_BASE_ADDR, aper_base);

2090

if (rinfo->has_CRTC2)

2089

if (rinfo->has_CRTC2)

2091

OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);

2090

OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);

2092

OUTREG(OV0_BASE_ADDR, aper_base);

2091

OUTREG(OV0_BASE_ADDR, aper_base);

2093

#else

2092

#else

2094

OUTREG(DISPLAY_BASE_ADDR, 0);

2093

OUTREG(DISPLAY_BASE_ADDR, 0);

2095

if (rinfo->has_CRTC2)

2094

if (rinfo->has_CRTC2)

2096

OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);

2095

OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);

2097

OUTREG(OV0_BASE_ADDR, 0);

2096

OUTREG(OV0_BASE_ADDR, 0);

2098

#endif

2097

#endif

2099

mdelay(100);

2098

mdelay(100);

2100

2099

2101

/* Restore display settings */

2100

/* Restore display settings */

2102

OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);

2101

OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);

2103

OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);

2102

OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);

2104

if (rinfo->has_CRTC2)

2103

if (rinfo->has_CRTC2)

2105

OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);

2104

OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);

2106

2105

2107

RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",

2106

RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",

2108

aper_base,

2107

aper_base,

2109

((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),

2108

((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),

2110

0xffff0000 | (agp_base >> 16));

2109

0xffff0000 | (agp_base >> 16));

2111

}

2110

}

2112

#endif /* CONFIG_PPC_OF */

2111

#endif /* CONFIG_PPC_OF */

2113

2112

2114

2113

2115

static void radeon_identify_vram(struct radeonfb_info *rinfo)

2114

static void radeon_identify_vram(struct radeonfb_info *rinfo)

2116

{

2115

{

2117

u32 tmp;

2116

u32 tmp;

2118

2117

2119

/* framebuffer size */

2118

/* framebuffer size */

2120

if ((rinfo->family == CHIP_FAMILY_RS100) ||

2119

if ((rinfo->family == CHIP_FAMILY_RS100) ||

2121

(rinfo->family == CHIP_FAMILY_RS200) ||

2120

(rinfo->family == CHIP_FAMILY_RS200) ||

2122

(rinfo->family == CHIP_FAMILY_RS300)) {

2121

(rinfo->family == CHIP_FAMILY_RS300)) {

2123

u32 tom = INREG(NB_TOM);

2122

u32 tom = INREG(NB_TOM);

2124

tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);

2123

tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);

2125

2124

2126

radeon_fifo_wait(6);

2125

radeon_fifo_wait(6);

2127

OUTREG(MC_FB_LOCATION, tom);

2126

OUTREG(MC_FB_LOCATION, tom);

2128

OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);

2127

OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);

2129

OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);

2128

OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);

2130

OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);

2129

OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);

2131

2130

2132

/* This is supposed to fix the crtc2 noise problem. */

2131

/* This is supposed to fix the crtc2 noise problem. */

2133

OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);

2132

OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);

2134

2133

2135

if ((rinfo->family == CHIP_FAMILY_RS100) ||

2134

if ((rinfo->family == CHIP_FAMILY_RS100) ||

2136

(rinfo->family == CHIP_FAMILY_RS200)) {

2135

(rinfo->family == CHIP_FAMILY_RS200)) {

2137

/* This is to workaround the asic bug for RMX, some versions

2136

/* This is to workaround the asic bug for RMX, some versions

2138

of BIOS dosen't have this register initialized correctly.

2137

of BIOS dosen't have this register initialized correctly.

2139

*/

2138

*/

2140

OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,

2139

OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,

2141

~CRTC_H_CUTOFF_ACTIVE_EN);

2140

~CRTC_H_CUTOFF_ACTIVE_EN);

2142

}

2141

}

2143

} else {

2142

} else {

2144

tmp = INREG(CONFIG_MEMSIZE);

2143

tmp = INREG(CONFIG_MEMSIZE);

2145

}

2144

}

2146

2145

2147

/* mem size is bits [28:0], mask off the rest */

2146

/* mem size is bits [28:0], mask off the rest */

2148

rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;

2147

rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;

2149

2148

2150

/*

2149

/*

2151

* Hack to get around some busted production M6's

2150

* Hack to get around some busted production M6's

2152

* reporting no ram

2151

* reporting no ram

2153

*/

2152

*/

2154

if (rinfo->video_ram == 0) {

2153

if (rinfo->video_ram == 0) {

2155

switch (rinfo->pdev->device) {

2154

switch (rinfo->pdev->device) {

2156

case PCI_CHIP_RADEON_LY:

2155

case PCI_CHIP_RADEON_LY:

2157

case PCI_CHIP_RADEON_LZ:

2156

case PCI_CHIP_RADEON_LZ:

2158

rinfo->video_ram = 8192 * 1024;

2157

rinfo->video_ram = 8192 * 1024;

2159

break;

2158

break;

2160

default:

2159

default:

2161

break;

2160

break;

2162

}

2161

}

2163

}

2162

}

2164

2163

2165

2164

2166

/*

2165

/*

2167

* Now try to identify VRAM type

2166

* Now try to identify VRAM type

2168

*/

2167

*/

2169

if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||

2168

if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||

2170

(INREG(MEM_SDRAM_MODE_REG) & (1<<30)))

2169

(INREG(MEM_SDRAM_MODE_REG) & (1<<30)))

2171

rinfo->vram_ddr = 1;

2170

rinfo->vram_ddr = 1;

2172

else

2171

else

2173

rinfo->vram_ddr = 0;

2172

rinfo->vram_ddr = 0;

2174

2173

2175

tmp = INREG(MEM_CNTL);

2174

tmp = INREG(MEM_CNTL);

2176

if (IS_R300_VARIANT(rinfo)) {

2175

if (IS_R300_VARIANT(rinfo)) {

2177

tmp &= R300_MEM_NUM_CHANNELS_MASK;

2176

tmp &= R300_MEM_NUM_CHANNELS_MASK;

2178

switch (tmp) {

2177

switch (tmp) {

2179

case 0: rinfo->vram_width = 64; break;

2178

case 0: rinfo->vram_width = 64; break;

2180

case 1: rinfo->vram_width = 128; break;

2179

case 1: rinfo->vram_width = 128; break;

2181

case 2: rinfo->vram_width = 256; break;

2180

case 2: rinfo->vram_width = 256; break;

2182

default: rinfo->vram_width = 128; break;

2181

default: rinfo->vram_width = 128; break;

2183

}

2182

}

2184

} else if ((rinfo->family == CHIP_FAMILY_RV100) ||

2183

} else if ((rinfo->family == CHIP_FAMILY_RV100) ||

2185

(rinfo->family == CHIP_FAMILY_RS100) ||

2184

(rinfo->family == CHIP_FAMILY_RS100) ||

2186

(rinfo->family == CHIP_FAMILY_RS200)){

2185

(rinfo->family == CHIP_FAMILY_RS200)){

2187

if (tmp & RV100_MEM_HALF_MODE)

2186

if (tmp & RV100_MEM_HALF_MODE)

2188

rinfo->vram_width = 32;

2187

rinfo->vram_width = 32;

2189

else

2188

else

2190

rinfo->vram_width = 64;

2189

rinfo->vram_width = 64;

2191

} else {

2190

} else {

2192

if (tmp & MEM_NUM_CHANNELS_MASK)

2191

if (tmp & MEM_NUM_CHANNELS_MASK)

2193

rinfo->vram_width = 128;

2192

rinfo->vram_width = 128;

2194

else

2193

else

2195

rinfo->vram_width = 64;

2194

rinfo->vram_width = 64;

2196

}

2195

}

2197

2196

2198

/* This may not be correct, as some cards can have half of channel disabled

2197

/* This may not be correct, as some cards can have half of channel disabled

2199

* ToDo: identify these cases

2198

* ToDo: identify these cases

2200

*/

2199

*/

2201

2200

2202

RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",

2201

RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",

2203

pci_name(rinfo->pdev),

2202

pci_name(rinfo->pdev),

2204

rinfo->video_ram / 1024,

2203

rinfo->video_ram / 1024,

2205

rinfo->vram_ddr ? "DDR" : "SDRAM",

2204

rinfo->vram_ddr ? "DDR" : "SDRAM",

2206

rinfo->vram_width);

2205

rinfo->vram_width);

2207

}

2206

}

2208

2207

2209

/*

2208

/*

2210

* Sysfs

2209

* Sysfs

2211

*/

2210

*/

2212

2211

2213

static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)

2212

static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)

2214

{

2213

{

2215

if (off > EDID_LENGTH)

2214

if (off > EDID_LENGTH)

2216

return 0;

2215

return 0;

2217

2216

2218

if (off + count > EDID_LENGTH)

2217

if (off + count > EDID_LENGTH)

2219

count = EDID_LENGTH - off;

2218

count = EDID_LENGTH - off;

2220

2219

2221

memcpy(buf, edid + off, count);

2220

memcpy(buf, edid + off, count);

2222

2221

2223

return count;

2222

return count;

2224

}

2223

}

2225

2224

2226

2225

2227

static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)

2226

static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)

2228

{

2227

{

2229

struct device *dev = container_of(kobj, struct device, kobj);

2228

struct device *dev = container_of(kobj, struct device, kobj);

2230

struct pci_dev *pdev = to_pci_dev(dev);

2229

struct pci_dev *pdev = to_pci_dev(dev);

2231

struct fb_info *info = pci_get_drvdata(pdev);

2230

struct fb_info *info = pci_get_drvdata(pdev);

2232

struct radeonfb_info *rinfo = info->par;

2231

struct radeonfb_info *rinfo = info->par;

2233

2232

2234

return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);

2233

return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);

2235

}

2234

}

2236

2235

2237

2236

2238

static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)

2237

static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)

2239

{

2238

{

2240

struct device *dev = container_of(kobj, struct device, kobj);

2239

struct device *dev = container_of(kobj, struct device, kobj);

2241

struct pci_dev *pdev = to_pci_dev(dev);

2240

struct pci_dev *pdev = to_pci_dev(dev);

2242

struct fb_info *info = pci_get_drvdata(pdev);

2241

struct fb_info *info = pci_get_drvdata(pdev);

2243

struct radeonfb_info *rinfo = info->par;

2242

struct radeonfb_info *rinfo = info->par;

2244

2243

2245

return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);

2244

return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);

2246

}

2245

}

2247

2246

2248

static struct bin_attribute edid1_attr = {

2247

static struct bin_attribute edid1_attr = {

2249

.attr = {

2248

.attr = {

2250

.name = "edid1",

2249

.name = "edid1",

2251

.owner = THIS_MODULE,

2250

.owner = THIS_MODULE,

2252

.mode = 0444,

2251

.mode = 0444,

2253

},

2252

},

2254

.size = EDID_LENGTH,

2253

.size = EDID_LENGTH,

2255

.read = radeon_show_edid1,

2254

.read = radeon_show_edid1,

2256

};

2255

};

2257

2256

2258

static struct bin_attribute edid2_attr = {

2257

static struct bin_attribute edid2_attr = {

2259

.attr = {

2258

.attr = {

2260

.name = "edid2",

2259

.name = "edid2",

2261

.owner = THIS_MODULE,

2260

.owner = THIS_MODULE,

2262

.mode = 0444,

2261

.mode = 0444,

2263

},

2262

},

2264

.size = EDID_LENGTH,

2263

.size = EDID_LENGTH,

2265

.read = radeon_show_edid2,

2264

.read = radeon_show_edid2,

2266

};

2265

};

2267

2266

2268

2267

2269

static int radeonfb_pci_register (struct pci_dev *pdev,

2268

static int radeonfb_pci_register (struct pci_dev *pdev,

2270

const struct pci_device_id *ent)

2269

const struct pci_device_id *ent)

2271

{

2270

{

2272

struct fb_info *info;

2271

struct fb_info *info;

2273

struct radeonfb_info *rinfo;

2272

struct radeonfb_info *rinfo;

2274

int ret;

2273

int ret;

2275

2274

2276

RTRACE("radeonfb_pci_register BEGIN\n");

2275

RTRACE("radeonfb_pci_register BEGIN\n");

2277

2276

2278

/* Enable device in PCI config */

2277

/* Enable device in PCI config */

2279

ret = pci_enable_device(pdev);

2278

ret = pci_enable_device(pdev);

2280

if (ret < 0) {

2279

if (ret < 0) {

2281

printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",

2280

printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",

2282

pci_name(pdev));

2281

pci_name(pdev));

2283

goto err_out;

2282

goto err_out;

2284

}

2283

}

2285

2284

2286

info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);

2285

info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);

2287

if (!info) {

2286

if (!info) {

2288

printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",

2287

printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",

2289

pci_name(pdev));

2288

pci_name(pdev));

2290

ret = -ENOMEM;

2289

ret = -ENOMEM;

2291

goto err_disable;

2290

goto err_disable;

2292

}

2291

}

2293

rinfo = info->par;

2292

rinfo = info->par;

2294

rinfo->info = info;

2293

rinfo->info = info;

2295

rinfo->pdev = pdev;

2294

rinfo->pdev = pdev;

2296

2295

2297

spin_lock_init(&rinfo->reg_lock);

2296

spin_lock_init(&rinfo->reg_lock);

2298

init_timer(&rinfo->lvds_timer);

2297

init_timer(&rinfo->lvds_timer);

2299

rinfo->lvds_timer.function = radeon_lvds_timer_func;

2298

rinfo->lvds_timer.function = radeon_lvds_timer_func;

2300

rinfo->lvds_timer.data = (unsigned long)rinfo;

2299

rinfo->lvds_timer.data = (unsigned long)rinfo;

2301

2300

2302

strcpy(rinfo->name, "ATI Radeon XX ");

2301

strcpy(rinfo->name, "ATI Radeon XX ");

2303

rinfo->name[11] = ent->device >> 8;

2302

rinfo->name[11] = ent->device >> 8;

2304

rinfo->name[12] = ent->device & 0xFF;

2303

rinfo->name[12] = ent->device & 0xFF;

2305

rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;

2304

rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;

2306

rinfo->chipset = pdev->device;

2305

rinfo->chipset = pdev->device;

2307

rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;

2306

rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;

2308

rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;

2307

rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;

2309

rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;

2308

rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;

2310

2309

2311

/* Set base addrs */

2310

/* Set base addrs */

2312

rinfo->fb_base_phys = pci_resource_start (pdev, 0);

2311

rinfo->fb_base_phys = pci_resource_start (pdev, 0);

2313

rinfo->mmio_base_phys = pci_resource_start (pdev, 2);

2312

rinfo->mmio_base_phys = pci_resource_start (pdev, 2);

2314

2313

2315

/* request the mem regions */

2314

/* request the mem regions */

2316

ret = pci_request_region(pdev, 0, "radeonfb framebuffer");

2315

ret = pci_request_region(pdev, 0, "radeonfb framebuffer");

2317

if (ret < 0) {

2316

if (ret < 0) {

2318

printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",

2317

printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",

2319

pci_name(rinfo->pdev));

2318

pci_name(rinfo->pdev));

2320

goto err_release_fb;

2319

goto err_release_fb;

2321

}

2320

}

2322

2321

2323

ret = pci_request_region(pdev, 2, "radeonfb mmio");

2322

ret = pci_request_region(pdev, 2, "radeonfb mmio");

2324

if (ret < 0) {

2323

if (ret < 0) {

2325

printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",

2324

printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",

2326

pci_name(rinfo->pdev));

2325

pci_name(rinfo->pdev));

2327

goto err_release_pci0;

2326

goto err_release_pci0;

2328

}

2327

}

2329

2328

2330

/* map the regions */

2329

/* map the regions */

2331

rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);

2330

rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);

2332

if (!rinfo->mmio_base) {

2331

if (!rinfo->mmio_base) {

2333

printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",

2332

printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",

2334

pci_name(rinfo->pdev));

2333

pci_name(rinfo->pdev));

2335

ret = -EIO;

2334

ret = -EIO;

2336

goto err_release_pci2;

2335

goto err_release_pci2;

2337

}

2336

}

2338

2337

2339

rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;

2338

rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;

2340

2339

2341

/*

2340

/*

2342

* Check for errata

2341

* Check for errata

2343

*/

2342

*/

2344

rinfo->errata = 0;

2343

rinfo->errata = 0;

2345

if (rinfo->family == CHIP_FAMILY_R300 &&

2344

if (rinfo->family == CHIP_FAMILY_R300 &&

2346

(INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)

2345

(INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)

2347

== CFG_ATI_REV_A11)

2346

== CFG_ATI_REV_A11)

2348

rinfo->errata |= CHIP_ERRATA_R300_CG;

2347

rinfo->errata |= CHIP_ERRATA_R300_CG;

2349

2348

2350

if (rinfo->family == CHIP_FAMILY_RV200 ||

2349

if (rinfo->family == CHIP_FAMILY_RV200 ||

2351

rinfo->family == CHIP_FAMILY_RS200)

2350

rinfo->family == CHIP_FAMILY_RS200)

2352

rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;

2351

rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;

2353

2352

2354

if (rinfo->family == CHIP_FAMILY_RV100 ||

2353

if (rinfo->family == CHIP_FAMILY_RV100 ||

2355

rinfo->family == CHIP_FAMILY_RS100 ||

2354

rinfo->family == CHIP_FAMILY_RS100 ||

2356

rinfo->family == CHIP_FAMILY_RS200)

2355

rinfo->family == CHIP_FAMILY_RS200)

2357

rinfo->errata |= CHIP_ERRATA_PLL_DELAY;

2356

rinfo->errata |= CHIP_ERRATA_PLL_DELAY;

2358

2357

2359

#ifdef CONFIG_PPC_OF

2358

#ifdef CONFIG_PPC_OF

2360

/* On PPC, we obtain the OF device-node pointer to the firmware

2359

/* On PPC, we obtain the OF device-node pointer to the firmware

2361

* data for this chip

2360

* data for this chip

2362

*/

2361

*/

2363

rinfo->of_node = pci_device_to_OF_node(pdev);

2362

rinfo->of_node = pci_device_to_OF_node(pdev);

2364

if (rinfo->of_node == NULL)

2363

if (rinfo->of_node == NULL)

2365

printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",

2364

printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",

2366

pci_name(rinfo->pdev));

2365

pci_name(rinfo->pdev));

2367

2366

2368

/* On PPC, the firmware sets up a memory mapping that tends

2367

/* On PPC, the firmware sets up a memory mapping that tends

2369

* to cause lockups when enabling the engine. We reconfigure

2368

* to cause lockups when enabling the engine. We reconfigure

2370

* the card internal memory mappings properly

2369

* the card internal memory mappings properly

2371

*/

2370

*/

2372

fixup_memory_mappings(rinfo);

2371

fixup_memory_mappings(rinfo);

2373

#endif /* CONFIG_PPC_OF */

2372

#endif /* CONFIG_PPC_OF */

2374

2373

2375

/* Get VRAM size and type */

2374

/* Get VRAM size and type */

2376

radeon_identify_vram(rinfo);

2375

radeon_identify_vram(rinfo);

2377

2376

2378

rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);

2377

rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);

2379

2378

2380

do {

2379

do {

2381

rinfo->fb_base = ioremap (rinfo->fb_base_phys,

2380

rinfo->fb_base = ioremap (rinfo->fb_base_phys,

2382

rinfo->mapped_vram);

2381

rinfo->mapped_vram);

2383

} while ( rinfo->fb_base == 0 &&

2382

} while ( rinfo->fb_base == 0 &&

2384

((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );

2383

((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );

2385

2384

2386

if (rinfo->fb_base == NULL) {

2385

if (rinfo->fb_base == NULL) {

2387

printk (KERN_ERR "radeonfb (%s): cannot map FB\n",

2386

printk (KERN_ERR "radeonfb (%s): cannot map FB\n",

2388

pci_name(rinfo->pdev));

2387

pci_name(rinfo->pdev));

2389

ret = -EIO;

2388

ret = -EIO;

2390

goto err_unmap_rom;

2389

goto err_unmap_rom;

2391

}

2390

}

2392

2391

2393

RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),

2392

RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),

2394

rinfo->mapped_vram/1024);

2393

rinfo->mapped_vram/1024);

2395

2394

2396

/*

2395

/*

2397

* Map the BIOS ROM if any and retreive PLL parameters from

2396

* Map the BIOS ROM if any and retreive PLL parameters from

2398

* the BIOS. We skip that on mobility chips as the real panel

2397

* the BIOS. We skip that on mobility chips as the real panel

2399

* values we need aren't in the ROM but in the BIOS image in

2398

* values we need aren't in the ROM but in the BIOS image in

2400

* memory. This is definitely not the best meacnism though,

2399

* memory. This is definitely not the best meacnism though,

2401

* we really need the arch code to tell us which is the "primary"

2400

* we really need the arch code to tell us which is the "primary"

2402

* video adapter to use the memory image (or better, the arch

2401

* video adapter to use the memory image (or better, the arch

2403

* should provide us a copy of the BIOS image to shield us from

2402

* should provide us a copy of the BIOS image to shield us from

2404

* archs who would store that elsewhere and/or could initialize

2403

* archs who would store that elsewhere and/or could initialize

2405

* more than one adapter during boot).

2404

* more than one adapter during boot).

2406

*/

2405

*/

2407

if (!rinfo->is_mobility)

2406

if (!rinfo->is_mobility)

2408

radeon_map_ROM(rinfo, pdev);

2407

radeon_map_ROM(rinfo, pdev);

2409

2408

2410

/*

2409

/*

2411

* On x86, the primary display on laptop may have it's BIOS

2410

* On x86, the primary display on laptop may have it's BIOS

2412

* ROM elsewhere, try to locate it at the legacy memory hole.

2411

* ROM elsewhere, try to locate it at the legacy memory hole.

2413

* We probably need to make sure this is the primary display,

2412

* We probably need to make sure this is the primary display,

2414

* but that is difficult without some arch support.

2413

* but that is difficult without some arch support.

2415

*/

2414

*/

2416

#ifdef CONFIG_X86

2415

#ifdef CONFIG_X86

2417

if (rinfo->bios_seg == NULL)

2416

if (rinfo->bios_seg == NULL)

2418

radeon_find_mem_vbios(rinfo);

2417

radeon_find_mem_vbios(rinfo);

2419

#endif

2418

#endif

2420

2419

2421

/* If both above failed, try the BIOS ROM again for mobility

2420

/* If both above failed, try the BIOS ROM again for mobility

2422

* chips

2421

* chips

2423

*/

2422

*/

2424

if (rinfo->bios_seg == NULL && rinfo->is_mobility)

2423

if (rinfo->bios_seg == NULL && rinfo->is_mobility)

2425

radeon_map_ROM(rinfo, pdev);

2424

radeon_map_ROM(rinfo, pdev);

2426

2425

2427

/* Get informations about the board's PLL */

2426

/* Get informations about the board's PLL */

2428

radeon_get_pllinfo(rinfo);

2427

radeon_get_pllinfo(rinfo);

2429

2428

2430

#ifdef CONFIG_FB_RADEON_I2C

2429

#ifdef CONFIG_FB_RADEON_I2C

2431

/* Register I2C bus */

2430

/* Register I2C bus */

2432

radeon_create_i2c_busses(rinfo);

2431

radeon_create_i2c_busses(rinfo);

2433

#endif

2432

#endif

2434

2433

2435

/* set all the vital stuff */

2434

/* set all the vital stuff */

2436

radeon_set_fbinfo (rinfo);

2435

radeon_set_fbinfo (rinfo);

2437

2436

2438

/* Probe screen types */

2437

/* Probe screen types */

2439

radeon_probe_screens(rinfo, monitor_layout, ignore_edid);

2438

radeon_probe_screens(rinfo, monitor_layout, ignore_edid);

2440

2439

2441

/* Build mode list, check out panel native model */

2440

/* Build mode list, check out panel native model */

2442

radeon_check_modes(rinfo, mode_option);

2441

radeon_check_modes(rinfo, mode_option);

2443

2442

2444

/* Register some sysfs stuff (should be done better) */

2443

/* Register some sysfs stuff (should be done better) */

2445

if (rinfo->mon1_EDID)

2444

if (rinfo->mon1_EDID)

2446

sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);

2445

sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);

2447

if (rinfo->mon2_EDID)

2446

if (rinfo->mon2_EDID)

2448

sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);

2447

sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);

2449

2448

2450

/* save current mode regs before we switch into the new one

2449

/* save current mode regs before we switch into the new one

2451

* so we can restore this upon __exit

2450

* so we can restore this upon __exit

2452

*/

2451

*/

2453

radeon_save_state (rinfo, &rinfo->init_state);

2452

radeon_save_state (rinfo, &rinfo->init_state);

2454

memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));

2453

memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));

2455

2454

2456

/* Setup Power Management capabilities */

2455

/* Setup Power Management capabilities */

2457

if (default_dynclk < -1) {

2456

if (default_dynclk < -1) {

2458

/* -2 is special: means ON on mobility chips and do not

2457

/* -2 is special: means ON on mobility chips and do not

2459

* change on others

2458

* change on others

2460

*/

2459

*/

2461

radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1);

2460

radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1);

2462

} else

2461

} else

2463

radeonfb_pm_init(rinfo, default_dynclk);

2462

radeonfb_pm_init(rinfo, default_dynclk);

2464

2463

2465

pci_set_drvdata(pdev, info);

2464

pci_set_drvdata(pdev, info);

2466

2465

2467

/* Register with fbdev layer */

2466

/* Register with fbdev layer */

2468

ret = register_framebuffer(info);

2467

ret = register_framebuffer(info);

2469

if (ret < 0) {

2468

if (ret < 0) {

2470

printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",

2469

printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",

2471

pci_name(rinfo->pdev));

2470

pci_name(rinfo->pdev));

2472

goto err_unmap_fb;

2471

goto err_unmap_fb;

2473

}

2472

}

2474

2473

2475

#ifdef CONFIG_MTRR

2474

#ifdef CONFIG_MTRR

2476

rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,

2475

rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,

2477

rinfo->video_ram,

2476

rinfo->video_ram,

2478

MTRR_TYPE_WRCOMB, 1);

2477

MTRR_TYPE_WRCOMB, 1);

2479

#endif

2478

#endif

2480

2479

2481

#ifdef CONFIG_PMAC_BACKLIGHT

2480

#ifdef CONFIG_PMAC_BACKLIGHT

2482

if (rinfo->mon1_type == MT_LCD) {

2481

if (rinfo->mon1_type == MT_LCD) {

2483

register_backlight_controller(&radeon_backlight_controller,

2482

register_backlight_controller(&radeon_backlight_controller,

2484

rinfo, "ati");

2483

rinfo, "ati");

2485

register_backlight_controller(&radeon_backlight_controller,

2484

register_backlight_controller(&radeon_backlight_controller,

2486

rinfo, "mnca");

2485

rinfo, "mnca");

2487

}

2486

}

2488

#endif

2487

#endif

2489

2488

2490

printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);

2489

printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);

2491

2490

2492

if (rinfo->bios_seg)

2491

if (rinfo->bios_seg)

2493

radeon_unmap_ROM(rinfo, pdev);

2492

radeon_unmap_ROM(rinfo, pdev);

2494

RTRACE("radeonfb_pci_register END\n");

2493

RTRACE("radeonfb_pci_register END\n");

2495

2494

2496

return 0;

2495

return 0;

2497

err_unmap_fb:

2496

err_unmap_fb:

2498

iounmap(rinfo->fb_base);

2497

iounmap(rinfo->fb_base);

2499

err_unmap_rom:

2498

err_unmap_rom:

2500

kfree(rinfo->mon1_EDID);

2499

kfree(rinfo->mon1_EDID);

2501

kfree(rinfo->mon2_EDID);

2500

kfree(rinfo->mon2_EDID);

2502

if (rinfo->mon1_modedb)

2501

if (rinfo->mon1_modedb)

2503

fb_destroy_modedb(rinfo->mon1_modedb);

2502

fb_destroy_modedb(rinfo->mon1_modedb);

2504

fb_dealloc_cmap(&info->cmap);

2503

fb_dealloc_cmap(&info->cmap);

2505

#ifdef CONFIG_FB_RADEON_I2C

2504

#ifdef CONFIG_FB_RADEON_I2C

2506

radeon_delete_i2c_busses(rinfo);

2505

radeon_delete_i2c_busses(rinfo);

2507

#endif

2506

#endif

2508

if (rinfo->bios_seg)

2507

if (rinfo->bios_seg)

2509

radeon_unmap_ROM(rinfo, pdev);

2508

radeon_unmap_ROM(rinfo, pdev);

2510

iounmap(rinfo->mmio_base);

2509

iounmap(rinfo->mmio_base);

2511

err_release_pci2:

2510

err_release_pci2:

2512

pci_release_region(pdev, 2);

2511

pci_release_region(pdev, 2);

2513

err_release_pci0:

2512

err_release_pci0:

2514

pci_release_region(pdev, 0);

2513

pci_release_region(pdev, 0);

2515

err_release_fb:

2514

err_release_fb:

2516

framebuffer_release(info);

2515

framebuffer_release(info);

2517

err_disable:

2516

err_disable:

2518

pci_disable_device(pdev);

2517

pci_disable_device(pdev);

2519

err_out:

2518

err_out:

2520

return ret;

2519

return ret;

2521

}

2520

}

2522

2521

2523

2522

2524

2523

2525

static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)

2524

static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)

2526

{

2525

{

2527

struct fb_info *info = pci_get_drvdata(pdev);

2526

struct fb_info *info = pci_get_drvdata(pdev);

2528

struct radeonfb_info *rinfo = info->par;

2527

struct radeonfb_info *rinfo = info->par;

2529

2528

2530

if (!rinfo)

2529

if (!rinfo)

2531

return;

2530

return;

2532

2531

2533

radeonfb_pm_exit(rinfo);

2532

radeonfb_pm_exit(rinfo);

2534

2533

2535

if (rinfo->mon1_EDID)

2534

if (rinfo->mon1_EDID)

2536

sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);

2535

sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);

2537

if (rinfo->mon2_EDID)

2536

if (rinfo->mon2_EDID)

2538

sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);

2537

sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);

2539

2538

2540

#if 0

2539

#if 0

2541

/* restore original state

2540

/* restore original state

2542

*

2541

*

2543

* Doesn't quite work yet, I suspect if we come from a legacy

2542

* Doesn't quite work yet, I suspect if we come from a legacy

2544

* VGA mode (or worse, text mode), we need to do some VGA black

2543

* VGA mode (or worse, text mode), we need to do some VGA black

2545

* magic here that I know nothing about. --BenH

2544

* magic here that I know nothing about. --BenH

2546

*/

2545

*/

2547

radeon_write_mode (rinfo, &rinfo->init_state, 1);

2546

radeon_write_mode (rinfo, &rinfo->init_state, 1);

2548

#endif

2547

#endif

2549

2548

2550

del_timer_sync(&rinfo->lvds_timer);

2549

del_timer_sync(&rinfo->lvds_timer);

2551

2550

2552

#ifdef CONFIG_MTRR

2551

#ifdef CONFIG_MTRR

2553

if (rinfo->mtrr_hdl >= 0)

2552

if (rinfo->mtrr_hdl >= 0)

2554

mtrr_del(rinfo->mtrr_hdl, 0, 0);

2553

mtrr_del(rinfo->mtrr_hdl, 0, 0);

2555

#endif

2554

#endif

2556

2555

2557

unregister_framebuffer(info);

2556

unregister_framebuffer(info);

2558

2557

2559

iounmap(rinfo->mmio_base);

2558

iounmap(rinfo->mmio_base);

2560

iounmap(rinfo->fb_base);

2559

iounmap(rinfo->fb_base);

2561

2560

2562

pci_release_region(pdev, 2);

2561

pci_release_region(pdev, 2);

2563

pci_release_region(pdev, 0);

2562

pci_release_region(pdev, 0);

2564

2563

2565

kfree(rinfo->mon1_EDID);

2564

kfree(rinfo->mon1_EDID);

2566

kfree(rinfo->mon2_EDID);

2565

kfree(rinfo->mon2_EDID);

2567

if (rinfo->mon1_modedb)

2566

if (rinfo->mon1_modedb)

2568

fb_destroy_modedb(rinfo->mon1_modedb);

2567

fb_destroy_modedb(rinfo->mon1_modedb);

2569

#ifdef CONFIG_FB_RADEON_I2C

2568

#ifdef CONFIG_FB_RADEON_I2C

2570

radeon_delete_i2c_busses(rinfo);

2569

radeon_delete_i2c_busses(rinfo);

2571

#endif

2570

#endif

2572

fb_dealloc_cmap(&info->cmap);

2571

fb_dealloc_cmap(&info->cmap);

2573

framebuffer_release(info);

2572

framebuffer_release(info);

2574

pci_disable_device(pdev);

2573

pci_disable_device(pdev);

2575

}

2574

}

2576

2575

2577

2576

2578

static struct pci_driver radeonfb_driver = {

2577

static struct pci_driver radeonfb_driver = {

2579

.name = "radeonfb",

2578

.name = "radeonfb",

2580

.id_table = radeonfb_pci_table,

2579

.id_table = radeonfb_pci_table,

2581

.probe = radeonfb_pci_register,

2580

.probe = radeonfb_pci_register,

2582

.remove = __devexit_p(radeonfb_pci_unregister),

2581

.remove = __devexit_p(radeonfb_pci_unregister),

2583

#ifdef CONFIG_PM

2582

#ifdef CONFIG_PM

2584

.suspend = radeonfb_pci_suspend,

2583

.suspend = radeonfb_pci_suspend,

2585

.resume = radeonfb_pci_resume,

2584

.resume = radeonfb_pci_resume,

2586

#endif /* CONFIG_PM */

2585

#endif /* CONFIG_PM */

2587

};

2586

};

2588

2587

2589

#ifndef MODULE

2588

#ifndef MODULE

2590

static int __init radeonfb_setup (char *options)

2589

static int __init radeonfb_setup (char *options)

2591

{

2590

{

2592

char *this_opt;

2591

char *this_opt;

2593

2592

2594

if (!options || !*options)

2593

if (!options || !*options)

2595

return 0;

2594

return 0;

2596

2595

2597

while ((this_opt = strsep (&options, ",")) != NULL) {

2596

while ((this_opt = strsep (&options, ",")) != NULL) {

2598

if (!*this_opt)

2597

if (!*this_opt)

2599

continue;

2598

continue;

2600

2599

2601

if (!strncmp(this_opt, "noaccel", 7)) {

2600

if (!strncmp(this_opt, "noaccel", 7)) {

2602

noaccel = 1;

2601

noaccel = 1;

2603

} else if (!strncmp(this_opt, "mirror", 6)) {

2602

} else if (!strncmp(this_opt, "mirror", 6)) {

2604

mirror = 1;

2603

mirror = 1;

2605

} else if (!strncmp(this_opt, "force_dfp", 9)) {

2604

} else if (!strncmp(this_opt, "force_dfp", 9)) {

2606

force_dfp = 1;

2605

force_dfp = 1;

2607

} else if (!strncmp(this_opt, "panel_yres:", 11)) {

2606

} else if (!strncmp(this_opt, "panel_yres:", 11)) {

2608

panel_yres = simple_strtoul((this_opt+11), NULL, 0);

2607

panel_yres = simple_strtoul((this_opt+11), NULL, 0);

2609

#ifdef CONFIG_MTRR

2608

#ifdef CONFIG_MTRR

2610

} else if (!strncmp(this_opt, "nomtrr", 6)) {

2609

} else if (!strncmp(this_opt, "nomtrr", 6)) {

2611

nomtrr = 1;

2610

nomtrr = 1;

2612

#endif

2611

#endif

2613

} else if (!strncmp(this_opt, "nomodeset", 9)) {

2612

} else if (!strncmp(this_opt, "nomodeset", 9)) {

2614

nomodeset = 1;

2613

nomodeset = 1;

2615

} else if (!strncmp(this_opt, "force_measure_pll", 17)) {

2614

} else if (!strncmp(this_opt, "force_measure_pll", 17)) {

2616

force_measure_pll = 1;

2615

force_measure_pll = 1;

2617

} else if (!strncmp(this_opt, "ignore_edid", 11)) {

2616

} else if (!strncmp(this_opt, "ignore_edid", 11)) {

2618

ignore_edid = 1;

2617

ignore_edid = 1;

2619

} else

2618

} else

2620

mode_option = this_opt;

2619

mode_option = this_opt;

2621

}

2620

}

2622

return 0;

2621

return 0;

2623

}

2622

}

2624

#endif /* MODULE */

2623

#endif /* MODULE */

2625

2624

2626

static int __init radeonfb_init (void)

2625

static int __init radeonfb_init (void)

2627

{

2626

{

2628

#ifndef MODULE

2627

#ifndef MODULE

2629

char *option = NULL;

2628

char *option = NULL;

2630

2629

2631

if (fb_get_options("radeonfb", &option))

2630

if (fb_get_options("radeonfb", &option))

2632

return -ENODEV;

2631

return -ENODEV;

2633

radeonfb_setup(option);

2632

radeonfb_setup(option);

2634

#endif

2633

#endif

2635

return pci_register_driver (&radeonfb_driver);

2634

return pci_register_driver (&radeonfb_driver);

2636

}

2635

}

2637

2636

2638

2637

2639

static void __exit radeonfb_exit (void)

2638

static void __exit radeonfb_exit (void)

2640

{

2639

{

2641

pci_unregister_driver (&radeonfb_driver);

2640

pci_unregister_driver (&radeonfb_driver);

2642

}

2641

}

2643

2642

2644

module_init(radeonfb_init);

2643

module_init(radeonfb_init);

2645

module_exit(radeonfb_exit);

2644

module_exit(radeonfb_exit);

2646

2645

2647

MODULE_AUTHOR("Ani Joshi");

2646

MODULE_AUTHOR("Ani Joshi");

2648

MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");

2647

MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");

2649

MODULE_LICENSE("GPL");

2648

MODULE_LICENSE("GPL");

2650

module_param(noaccel, bool, 0);

2649

module_param(noaccel, bool, 0);

2651

module_param(default_dynclk, int, 0);

2650

module_param(default_dynclk, int, 0);

2652

MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");

2651

MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");

2653

MODULE_PARM_DESC(noaccel, "bool: disable acceleration");

2652

MODULE_PARM_DESC(noaccel, "bool: disable acceleration");

2654

module_param(nomodeset, bool, 0);

2653

module_param(nomodeset, bool, 0);

2655

MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");

2654

MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");

2656

module_param(mirror, bool, 0);

2655

module_param(mirror, bool, 0);

2657

MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");

2656

MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");

2658

module_param(force_dfp, bool, 0);

2657

module_param(force_dfp, bool, 0);

2659

MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");

2658

MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");

2660

module_param(ignore_edid, bool, 0);

2659

module_param(ignore_edid, bool, 0);

2661

MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");

2660

MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");

2662

module_param(monitor_layout, charp, 0);

2661

module_param(monitor_layout, charp, 0);

2663

MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");

2662

MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");

2664

module_param(force_measure_pll, bool, 0);

2663

module_param(force_measure_pll, bool, 0);

2665

MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");

2664

MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");

2666

#ifdef CONFIG_MTRR

2665

#ifdef CONFIG_MTRR

2667

module_param(nomtrr, bool, 0);

2666

module_param(nomtrr, bool, 0);

2668

MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");

2667

MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");

2669

#endif

2668

#endif

2670

module_param(panel_yres, int, 0);

2669

module_param(panel_yres, int, 0);

2671

MODULE_PARM_DESC(panel_yres, "int: set panel yres");

2670

MODULE_PARM_DESC(panel_yres, "int: set panel yres");

2672

module_param(mode_option, charp, 0);

2671

module_param(mode_option, charp, 0);

2673

MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");

2672

MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");

2674

2673

GITLAB

[PATCH] radeonfb: prevent spurious recompilations

 /*
  *	drivers/video/aty/radeon_base.c
  *
  *	framebuffer driver for ATI Radeon chipset video boards
  *
  *	Copyright 2003	Ben. Herrenschmidt <benh@kernel.crashing.org>
  *	Copyright 2000	Ani Joshi <ajoshi@kernel.crashing.org>
  *
  *	i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
  *
  *	Special thanks to ATI DevRel team for their hardware donations.
  *
  *	...Insert GPL boilerplate here...
  *
  *	Significant portions of this driver apdated from XFree86 Radeon
  *	driver which has the following copyright notice:
  *
  *	Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  *                     VA Linux Systems Inc., Fremont, California.
  *
  *	All Rights Reserved.
  *
  *	Permission is hereby granted, free of charge, to any person obtaining
  *	a copy of this software and associated documentation files (the
  *	"Software"), to deal in the Software without restriction, including
  *	without limitation on the rights to use, copy, modify, merge,
  *	publish, distribute, sublicense, and/or sell copies of the Software,
  *	and to permit persons to whom the Software is furnished to do so,
  *	subject to the following conditions:
  *
  *	The above copyright notice and this permission notice (including the
  *	next paragraph) shall be included in all copies or substantial
  *	portions of the Software.
  *
  *	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  * 	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  *	MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  *	NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
  *	THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  *	WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  *	OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  *	DEALINGS IN THE SOFTWARE.
  *
  *	XFree86 driver authors:
  *
  *	   Kevin E. Martin <martin@xfree86.org>
  *	   Rickard E. Faith <faith@valinux.com>
  *	   Alan Hourihane <alanh@fairlite.demon.co.uk>
  *
  */
 #define RADEON_VERSION	"0.2.0"
 #include <linux/config.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/tty.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/time.h>
 #include <linux/fb.h>
 #include <linux/ioport.h>
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/vmalloc.h>
 #include <linux/device.h>
-#include <linux/i2c.h>
 #include <asm/io.h>
 #include <asm/uaccess.h>
 #ifdef CONFIG_PPC_OF
 #include <asm/pci-bridge.h>
 #include "../macmodes.h"
 #ifdef CONFIG_PMAC_BACKLIGHT
 #include <asm/backlight.h>
 #endif
 #ifdef CONFIG_BOOTX_TEXT
 #include <asm/btext.h>
 #endif
 #endif /* CONFIG_PPC_OF */
 #ifdef CONFIG_MTRR
 #include <asm/mtrr.h>
 #endif
 #include <video/radeon.h>
 #include <linux/radeonfb.h>
 #include "../edid.h" // MOVE THAT TO include/video
 #include "ati_ids.h"
 #include "radeonfb.h"
 #define MAX_MAPPED_VRAM	(2048*2048*4)
 #define MIN_MAPPED_VRAM	(1024*768*1)
 #define CHIP_DEF(id, family, flags)					\
 	{ PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
 static struct pci_device_id radeonfb_pci_table[] = {
 	/* Mobility M6 */
 	CHIP_DEF(PCI_CHIP_RADEON_LY, 	RV100,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RADEON_LZ,	RV100,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	/* Radeon VE/7000 */
 	CHIP_DEF(PCI_CHIP_RV100_QY, 	RV100,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV100_QZ, 	RV100,	CHIP_HAS_CRTC2),
 	/* Radeon IGP320M (U1) */
 	CHIP_DEF(PCI_CHIP_RS100_4336,	RS100,	CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 	/* Radeon IGP320 (A3) */
 	CHIP_DEF(PCI_CHIP_RS100_4136,	RS100,	CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 	/* IGP330M/340M/350M (U2) */
 	CHIP_DEF(PCI_CHIP_RS200_4337,	RS200,	CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 	/* IGP330/340/350 (A4) */
 	CHIP_DEF(PCI_CHIP_RS200_4137,	RS200,	CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 	/* Mobility 7000 IGP */
 	CHIP_DEF(PCI_CHIP_RS250_4437,	RS200,	CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 	/* 7000 IGP (A4+) */
 	CHIP_DEF(PCI_CHIP_RS250_4237,	RS200,	CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 	/* 8500 AIW */
 	CHIP_DEF(PCI_CHIP_R200_BB,	R200,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R200_BC,	R200,	CHIP_HAS_CRTC2),
 	/* 8700/8800 */
 	CHIP_DEF(PCI_CHIP_R200_QH,	R200,	CHIP_HAS_CRTC2),
 	/* 8500 */
 	CHIP_DEF(PCI_CHIP_R200_QL,	R200,	CHIP_HAS_CRTC2),
 	/* 9100 */
 	CHIP_DEF(PCI_CHIP_R200_QM,	R200,	CHIP_HAS_CRTC2),
 	/* Mobility M7 */
 	CHIP_DEF(PCI_CHIP_RADEON_LW,	RV200,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RADEON_LX,	RV200,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	/* 7500 */
 	CHIP_DEF(PCI_CHIP_RV200_QW,	RV200,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV200_QX,	RV200,	CHIP_HAS_CRTC2),
 	/* Mobility M9 */
 	CHIP_DEF(PCI_CHIP_RV250_Ld,	RV250,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RV250_Le,	RV250,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RV250_Lf,	RV250,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RV250_Lg,	RV250,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	/* 9000/Pro */
 	CHIP_DEF(PCI_CHIP_RV250_If,	RV250,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV250_Ig,	RV250,	CHIP_HAS_CRTC2),
 	/* Mobility 9100 IGP (U3) */
 	CHIP_DEF(PCI_CHIP_RS300_5835,	RS300,	CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RS350_7835,	RS300,	CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 	/* 9100 IGP (A5) */
 	CHIP_DEF(PCI_CHIP_RS300_5834,	RS300,	CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 	CHIP_DEF(PCI_CHIP_RS350_7834,	RS300,	CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 	/* Mobility 9200 (M9+) */
 	CHIP_DEF(PCI_CHIP_RV280_5C61,	RV280,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RV280_5C63,	RV280,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	/* 9200 */
 	CHIP_DEF(PCI_CHIP_RV280_5960,	RV280,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV280_5961,	RV280,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV280_5962,	RV280,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV280_5964,	RV280,	CHIP_HAS_CRTC2),
 	/* 9500 */
 	CHIP_DEF(PCI_CHIP_R300_AD,	R300,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R300_AE,	R300,	CHIP_HAS_CRTC2),
 	/* 9600TX / FireGL Z1 */
 	CHIP_DEF(PCI_CHIP_R300_AF,	R300,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R300_AG,	R300,	CHIP_HAS_CRTC2),
 	/* 9700/9500/Pro/FireGL X1 */
 	CHIP_DEF(PCI_CHIP_R300_ND,	R300,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R300_NE,	R300,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R300_NF,	R300,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R300_NG,	R300,	CHIP_HAS_CRTC2),
 	/* Mobility M10/M11 */
 	CHIP_DEF(PCI_CHIP_RV350_NP,	RV350,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RV350_NQ,	RV350,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RV350_NR,	RV350,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RV350_NS,	RV350,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RV350_NT,	RV350,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RV350_NV,	RV350,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	/* 9600/FireGL T2 */
 	CHIP_DEF(PCI_CHIP_RV350_AP,	RV350,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV350_AQ,	RV350,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV360_AR,	RV350,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV350_AS,	RV350,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV350_AT,	RV350,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV350_AV,	RV350,	CHIP_HAS_CRTC2),
 	/* 9800/Pro/FileGL X2 */
 	CHIP_DEF(PCI_CHIP_R350_AH,	R350,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R350_AI,	R350,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R350_AJ,	R350,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R350_AK,	R350,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R350_NH,	R350,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R350_NI,	R350,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R360_NJ,	R350,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R350_NK,	R350,	CHIP_HAS_CRTC2),
 	/* Newer stuff */
 	CHIP_DEF(PCI_CHIP_RV380_3E50,	RV380,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV380_3E54,	RV380,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV380_3150,	RV380,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RV380_3154,	RV380,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RV370_5B60,	RV380,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV370_5B62,	RV380,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV370_5B64,	RV380,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV370_5B65,	RV380,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_RV370_5460,	RV380,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_RV370_5464,	RV380,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_R420_JH,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R420_JI,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R420_JJ,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R420_JK,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R420_JL,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R420_JM,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R420_JN,	R420,	CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 	CHIP_DEF(PCI_CHIP_R420_JP,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R423_UH,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R423_UI,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R423_UJ,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R423_UK,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R423_UQ,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R423_UR,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R423_UT,	R420,	CHIP_HAS_CRTC2),
 	CHIP_DEF(PCI_CHIP_R423_5D57,	R420,	CHIP_HAS_CRTC2),
 	/* Original Radeon/7200 */
 	CHIP_DEF(PCI_CHIP_RADEON_QD,	RADEON,	0),
 	CHIP_DEF(PCI_CHIP_RADEON_QE,	RADEON,	0),
 	CHIP_DEF(PCI_CHIP_RADEON_QF,	RADEON,	0),
 	CHIP_DEF(PCI_CHIP_RADEON_QG,	RADEON,	0),
 	{ 0, }
 };
 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
 typedef struct {
 	u16 reg;
 	u32 val;
 } reg_val;
 /* these common regs are cleared before mode setting so they do not
  * interfere with anything
  */
 static reg_val common_regs[] = {
 	{ OVR_CLR, 0 },
 	{ OVR_WID_LEFT_RIGHT, 0 },
 	{ OVR_WID_TOP_BOTTOM, 0 },
 	{ OV0_SCALE_CNTL, 0 },
 	{ SUBPIC_CNTL, 0 },
 	{ VIPH_CONTROL, 0 },
 	{ I2C_CNTL_1, 0 },
 	{ GEN_INT_CNTL, 0 },
 	{ CAP0_TRIG_CNTL, 0 },
 	{ CAP1_TRIG_CNTL, 0 },
 };
 /*
  * globals
  */
 static char *mode_option;
 static char *monitor_layout;
 static int noaccel = 0;
 static int default_dynclk = -2;
 static int nomodeset = 0;
 static int ignore_edid = 0;
 static int mirror = 0;
 static int panel_yres = 0;
 static int force_dfp = 0;
 static int force_measure_pll = 0;
 #ifdef CONFIG_MTRR
 static int nomtrr = 0;
 #endif
 /*
  * prototypes
  */
 #ifdef CONFIG_PPC_OF
 #ifdef CONFIG_PMAC_BACKLIGHT
 static int radeon_set_backlight_enable(int on, int level, void *data);
 static int radeon_set_backlight_level(int level, void *data);
 static struct backlight_controller radeon_backlight_controller = {
 	radeon_set_backlight_enable,
 	radeon_set_backlight_level
 };
 #endif /* CONFIG_PMAC_BACKLIGHT */
 #endif /* CONFIG_PPC_OF */
 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
 {
 	if (!rinfo->bios_seg)
 		return;
 	pci_unmap_rom(dev, rinfo->bios_seg);
 }
 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
 {
 	void __iomem *rom;
 	u16 dptr;
 	u8 rom_type;
 	size_t rom_size;
 	/* If this is a primary card, there is a shadow copy of the
 	 * ROM somewhere in the first meg. We will just ignore the copy
 	 * and use the ROM directly.
 	 */
     	/* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
     	unsigned int temp;
 	temp = INREG(MPP_TB_CONFIG);
 	temp &= 0x00ffffffu;
 	temp |= 0x04 << 24;
 	OUTREG(MPP_TB_CONFIG, temp);
 	temp = INREG(MPP_TB_CONFIG);
 	rom = pci_map_rom(dev, &rom_size);
 	if (!rom) {
 		printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
 		       pci_name(rinfo->pdev));
 		return -ENOMEM;
 	}
 	rinfo->bios_seg = rom;
 	/* Very simple test to make sure it appeared */
 	if (BIOS_IN16(0) != 0xaa55) {
 		printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
 			"should be 0xaa55\n",
 			pci_name(rinfo->pdev), BIOS_IN16(0));
 		goto failed;
 	}
 	/* Look for the PCI data to check the ROM type */
 	dptr = BIOS_IN16(0x18);
 	/* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
 	 * for now, until I've verified this works everywhere. The goal here is more
 	 * to phase out Open Firmware images.
 	 *
 	 * Currently, we only look at the first PCI data, we could iteratre and deal with
 	 * them all, and we should use fb_bios_start relative to start of image and not
 	 * relative start of ROM, but so far, I never found a dual-image ATI card
 	 *
 	 * typedef struct {
 	 * 	u32	signature;	+ 0x00
 	 * 	u16	vendor;		+ 0x04
 	 * 	u16	device;		+ 0x06
 	 * 	u16	reserved_1;	+ 0x08
 	 * 	u16	dlen;		+ 0x0a
 	 * 	u8	drevision;	+ 0x0c
 	 * 	u8	class_hi;	+ 0x0d
 	 * 	u16	class_lo;	+ 0x0e
 	 * 	u16	ilen;		+ 0x10
 	 * 	u16	irevision;	+ 0x12
 	 * 	u8	type;		+ 0x14
 	 * 	u8	indicator;	+ 0x15
 	 * 	u16	reserved_2;	+ 0x16
 	 * } pci_data_t;
 	 */
 	if (BIOS_IN32(dptr) !=  (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
 		printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
 		       "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
 		goto anyway;
 	}
 	rom_type = BIOS_IN8(dptr + 0x14);
 	switch(rom_type) {
 	case 0:
 		printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
 		break;
 	case 1:
 		printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
 		goto failed;
 	case 2:
 		printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
 		goto failed;
 	default:
 		printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
 		goto failed;
 	}
  anyway:
 	/* Locate the flat panel infos, do some sanity checking !!! */
 	rinfo->fp_bios_start = BIOS_IN16(0x48);
 	return 0;
  failed:
 	rinfo->bios_seg = NULL;
 	radeon_unmap_ROM(rinfo, dev);
 	return -ENXIO;
 }
 #ifdef CONFIG_X86
 static int  __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
 {
 	/* I simplified this code as we used to miss the signatures in
 	 * a lot of case. It's now closer to XFree, we just don't check
 	 * for signatures at all... Something better will have to be done
 	 * if we end up having conflicts
 	 */
         u32  segstart;
 	void __iomem *rom_base = NULL;
         for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
                 rom_base = ioremap(segstart, 0x10000);
 		if (rom_base == NULL)
 			return -ENOMEM;
                 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
 	                break;
                 iounmap(rom_base);
 		rom_base = NULL;
         }
 	if (rom_base == NULL)
 		return -ENXIO;
 	/* Locate the flat panel infos, do some sanity checking !!! */
 	rinfo->bios_seg = rom_base;
 	rinfo->fp_bios_start = BIOS_IN16(0x48);
 	return 0;
 }
 #endif
 #ifdef CONFIG_PPC_OF
 /*
  * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
  * tree. Hopefully, ATI OF driver is kind enough to fill these
  */
 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
 {
 	struct device_node *dp = rinfo->of_node;
 	u32 *val;
 	if (dp == NULL)
 		return -ENODEV;
 	val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);
 	if (!val || !*val) {
 		printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
 		return -EINVAL;
 	}
 	rinfo->pll.ref_clk = (*val) / 10;
 	val = (u32 *) get_property(dp, "ATY,SCLK", NULL);
 	if (val && *val)
 		rinfo->pll.sclk = (*val) / 10;
 	val = (u32 *) get_property(dp, "ATY,MCLK", NULL);
 	if (val && *val)
 		rinfo->pll.mclk = (*val) / 10;
        	return 0;
 }
 #endif /* CONFIG_PPC_OF */
 /*
  * Read PLL infos from chip registers
  */
 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
 {
 	unsigned char ppll_div_sel;
 	unsigned Ns, Nm, M;
 	unsigned sclk, mclk, tmp, ref_div;
 	int hTotal, vTotal, num, denom, m, n;
 	unsigned long long hz, vclk;
 	long xtal;
 	struct timeval start_tv, stop_tv;
 	long total_secs, total_usecs;
 	int i;
 	/* Ugh, we cut interrupts, bad bad bad, but we want some precision
 	 * here, so... --BenH
 	 */
 	/* Flush PCI buffers ? */
 	tmp = INREG16(DEVICE_ID);
 	local_irq_disable();
 	for(i=0; i<1000000; i++)
 		if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
 			break;
 	do_gettimeofday(&start_tv);
 	for(i=0; i<1000000; i++)
 		if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
 			break;
 	for(i=0; i<1000000; i++)
 		if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
 			break;
 	do_gettimeofday(&stop_tv);
 	local_irq_enable();
 	total_secs = stop_tv.tv_sec - start_tv.tv_sec;
 	if (total_secs > 10)
 		return -1;
 	total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
 	total_usecs += total_secs * 1000000;
 	if (total_usecs < 0)
 		total_usecs = -total_usecs;
 	hz = 1000000/total_usecs;
 	hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
 	vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
 	vclk = (long long)hTotal * (long long)vTotal * hz;
 	switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
 	case 0:
 	default:
 		num = 1;
 		denom = 1;
 		break;
 	case 1:
 		n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
 		m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
 		num = 2*n;
 		denom = 2*m;
 		break;
 	case 2:
 		n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
 		m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
 		num = 2*n;
 		denom = 2*m;
         break;
 	}
 	ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
 	radeon_pll_errata_after_index(rinfo);
 	n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
 	m = (INPLL(PPLL_REF_DIV) & 0x3ff);
 	num *= n;
 	denom *= m;
 	switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
 	case 1:
 		denom *= 2;
 		break;
 	case 2:
 		denom *= 4;
 		break;
 	case 3:
 		denom *= 8;
 		break;
 	case 4:
 		denom *= 3;
 		break;
 	case 6:
 		denom *= 6;
 		break;
 	case 7:
 		denom *= 12;
 		break;
 	}
 	vclk *= denom;
 	do_div(vclk, 1000 * num);
 	xtal = vclk;
 	if ((xtal > 26900) && (xtal < 27100))
 		xtal = 2700;
 	else if ((xtal > 14200) && (xtal < 14400))
 		xtal = 1432;
 	else if ((xtal > 29400) && (xtal < 29600))
 		xtal = 2950;
 	else {
 		printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
 		return -1;
 	}
 	tmp = INPLL(M_SPLL_REF_FB_DIV);
 	ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 	Ns = (tmp & 0xff0000) >> 16;
 	Nm = (tmp & 0xff00) >> 8;
 	M = (tmp & 0xff);
 	sclk = round_div((2 * Ns * xtal), (2 * M));
 	mclk = round_div((2 * Nm * xtal), (2 * M));
 	/* we're done, hopefully these are sane values */
 	rinfo->pll.ref_clk = xtal;
 	rinfo->pll.ref_div = ref_div;
 	rinfo->pll.sclk = sclk;
 	rinfo->pll.mclk = mclk;
 	return 0;
 }
 /*
  * Retreive PLL infos by different means (BIOS, Open Firmware, register probing...)
  */
 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
 {
 	/*
 	 * In the case nothing works, these are defaults; they are mostly
 	 * incomplete, however.  It does provide ppll_max and _min values
 	 * even for most other methods, however.
 	 */
 	switch (rinfo->chipset) {
 	case PCI_DEVICE_ID_ATI_RADEON_QW:
 	case PCI_DEVICE_ID_ATI_RADEON_QX:
 		rinfo->pll.ppll_max = 35000;
 		rinfo->pll.ppll_min = 12000;
 		rinfo->pll.mclk = 23000;
 		rinfo->pll.sclk = 23000;
 		rinfo->pll.ref_clk = 2700;
 		break;
 	case PCI_DEVICE_ID_ATI_RADEON_QL:
 	case PCI_DEVICE_ID_ATI_RADEON_QN:
 	case PCI_DEVICE_ID_ATI_RADEON_QO:
 	case PCI_DEVICE_ID_ATI_RADEON_Ql:
 	case PCI_DEVICE_ID_ATI_RADEON_BB:
 		rinfo->pll.ppll_max = 35000;
 		rinfo->pll.ppll_min = 12000;
 		rinfo->pll.mclk = 27500;
 		rinfo->pll.sclk = 27500;
 		rinfo->pll.ref_clk = 2700;
 		break;
 	case PCI_DEVICE_ID_ATI_RADEON_Id:
 	case PCI_DEVICE_ID_ATI_RADEON_Ie:
 	case PCI_DEVICE_ID_ATI_RADEON_If:
 	case PCI_DEVICE_ID_ATI_RADEON_Ig:
 		rinfo->pll.ppll_max = 35000;
 		rinfo->pll.ppll_min = 12000;
 		rinfo->pll.mclk = 25000;
 		rinfo->pll.sclk = 25000;
 		rinfo->pll.ref_clk = 2700;
 		break;
 	case PCI_DEVICE_ID_ATI_RADEON_ND:
 	case PCI_DEVICE_ID_ATI_RADEON_NE:
 	case PCI_DEVICE_ID_ATI_RADEON_NF:
 	case PCI_DEVICE_ID_ATI_RADEON_NG:
 		rinfo->pll.ppll_max = 40000;
 		rinfo->pll.ppll_min = 20000;
 		rinfo->pll.mclk = 27000;
 		rinfo->pll.sclk = 27000;
 		rinfo->pll.ref_clk = 2700;
 		break;
 	case PCI_DEVICE_ID_ATI_RADEON_QD:
 	case PCI_DEVICE_ID_ATI_RADEON_QE:
 	case PCI_DEVICE_ID_ATI_RADEON_QF:
 	case PCI_DEVICE_ID_ATI_RADEON_QG:
 	default:
 		rinfo->pll.ppll_max = 35000;
 		rinfo->pll.ppll_min = 12000;
 		rinfo->pll.mclk = 16600;
 		rinfo->pll.sclk = 16600;
 		rinfo->pll.ref_clk = 2700;
 		break;
 	}
 	rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
 #ifdef CONFIG_PPC_OF
 	/*
 	 * Retreive PLL infos from Open Firmware first
 	 */
        	if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
        		printk(KERN_INFO "radeonfb: Retreived PLL infos from Open Firmware\n");
 		goto found;
 	}
 #endif /* CONFIG_PPC_OF */
 	/*
 	 * Check out if we have an X86 which gave us some PLL informations
 	 * and if yes, retreive them
 	 */
 	if (!force_measure_pll && rinfo->bios_seg) {
 		u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
 		rinfo->pll.sclk		= BIOS_IN16(pll_info_block + 0x08);
 		rinfo->pll.mclk		= BIOS_IN16(pll_info_block + 0x0a);
 		rinfo->pll.ref_clk	= BIOS_IN16(pll_info_block + 0x0e);
 		rinfo->pll.ref_div	= BIOS_IN16(pll_info_block + 0x10);
 		rinfo->pll.ppll_min	= BIOS_IN32(pll_info_block + 0x12);
 		rinfo->pll.ppll_max	= BIOS_IN32(pll_info_block + 0x16);
 		printk(KERN_INFO "radeonfb: Retreived PLL infos from BIOS\n");
 		goto found;
 	}
 	/*
 	 * We didn't get PLL parameters from either OF or BIOS, we try to
 	 * probe them
 	 */
 	if (radeon_probe_pll_params(rinfo) == 0) {
 		printk(KERN_INFO "radeonfb: Retreived PLL infos from registers\n");
 		goto found;
 	}
 	/*
 	 * Fall back to already-set defaults...
 	 */
        	printk(KERN_INFO "radeonfb: Used default PLL infos\n");
 found:
 	/*
 	 * Some methods fail to retreive SCLK and MCLK values, we apply default
 	 * settings in this case (200Mhz). If that really happne often, we could
 	 * fetch from registers instead...
 	 */
 	if (rinfo->pll.mclk == 0)
 		rinfo->pll.mclk = 20000;
 	if (rinfo->pll.sclk == 0)
 		rinfo->pll.sclk = 20000;
 	printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
 	       rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
 	       rinfo->pll.ref_div,
 	       rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
 	       rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
 	printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
 }
 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
 {
 	struct radeonfb_info *rinfo = info->par;
         struct fb_var_screeninfo v;
         int nom, den;
 	unsigned int pitch;
 	if (radeon_match_mode(rinfo, &v, var))
 		return -EINVAL;
         switch (v.bits_per_pixel) {
 		case 0 ... 8:
 			v.bits_per_pixel = 8;
 			break;
 		case 9 ... 16:
 			v.bits_per_pixel = 16;
 			break;
 		case 17 ... 24:
 #if 0 /* Doesn't seem to work */
 			v.bits_per_pixel = 24;
 			break;
 #endif
 			return -EINVAL;
 		case 25 ... 32:
 			v.bits_per_pixel = 32;
 			break;
 		default:
 			return -EINVAL;
 	}
 	switch (var_to_depth(&v)) {
                 case 8:
                         nom = den = 1;
                         v.red.offset = v.green.offset = v.blue.offset = 0;
                         v.red.length = v.green.length = v.blue.length = 8;
                         v.transp.offset = v.transp.length = 0;
                         break;
 		case 15:
 			nom = 2;
 			den = 1;
 			v.red.offset = 10;
 			v.green.offset = 5;
 			v.blue.offset = 0;
 			v.red.length = v.green.length = v.blue.length = 5;
 			v.transp.offset = v.transp.length = 0;
 			break;
                 case 16:
                         nom = 2;
                         den = 1;
                         v.red.offset = 11;
                         v.green.offset = 5;
                         v.blue.offset = 0;
                         v.red.length = 5;
                         v.green.length = 6;
                         v.blue.length = 5;
                         v.transp.offset = v.transp.length = 0;
                         break;
                 case 24:
                         nom = 4;
                         den = 1;
                         v.red.offset = 16;
                         v.green.offset = 8;
                         v.blue.offset = 0;
                         v.red.length = v.blue.length = v.green.length = 8;
                         v.transp.offset = v.transp.length = 0;
                         break;
                 case 32:
                         nom = 4;
                         den = 1;
                         v.red.offset = 16;
                         v.green.offset = 8;
                         v.blue.offset = 0;
                         v.red.length = v.blue.length = v.green.length = 8;
                         v.transp.offset = 24;
                         v.transp.length = 8;
                         break;
                 default:
                         printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
                                 var->xres, var->yres, var->bits_per_pixel);
                         return -EINVAL;
         }
 	if (v.yres_virtual < v.yres)
 		v.yres_virtual = v.yres;
 	if (v.xres_virtual < v.xres)
 		v.xres_virtual = v.xres;
 	/* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
 	 * with some panels, though I don't quite like this solution
 	 */
   	if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
 		v.xres_virtual = v.xres_virtual & ~7ul;
 	} else {
 		pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
  				& ~(0x3f)) >> 6;
 		v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
 	}
 	if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
 		return -EINVAL;
 	if (v.xres_virtual < v.xres)
 		v.xres = v.xres_virtual;
 	if (v.xoffset < 0)
                 v.xoffset = 0;
         if (v.yoffset < 0)
                 v.yoffset = 0;
         if (v.xoffset > v.xres_virtual - v.xres)
                 v.xoffset = v.xres_virtual - v.xres - 1;
         if (v.yoffset > v.yres_virtual - v.yres)
                 v.yoffset = v.yres_virtual - v.yres - 1;
         v.red.msb_right = v.green.msb_right = v.blue.msb_right =
                           v.transp.offset = v.transp.length =
                           v.transp.msb_right = 0;
         memcpy(var, &v, sizeof(v));
         return 0;
 }
 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
                                  struct fb_info *info)
 {
         struct radeonfb_info *rinfo = info->par;
         if ((var->xoffset + var->xres > var->xres_virtual)
 	    || (var->yoffset + var->yres > var->yres_virtual))
                return -EINVAL;
         if (rinfo->asleep)
         	return 0;
 	radeon_fifo_wait(2);
         OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
 			     * var->bits_per_pixel / 8) & ~7);
         return 0;
 }
 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
                            unsigned long arg, struct fb_info *info)
 {
         struct radeonfb_info *rinfo = info->par;
 	unsigned int tmp;
 	u32 value = 0;
 	int rc;
 	switch (cmd) {
 		/*
 		 * TODO:  set mirror accordingly for non-Mobility chipsets with 2 CRTC's
 		 *        and do something better using 2nd CRTC instead of just hackish
 		 *        routing to second output
 		 */
 		case FBIO_RADEON_SET_MIRROR:
 			if (!rinfo->is_mobility)
 				return -EINVAL;
 			rc = get_user(value, (__u32 __user *)arg);
 			if (rc)
 				return rc;
 			radeon_fifo_wait(2);
 			if (value & 0x01) {
 				tmp = INREG(LVDS_GEN_CNTL);
 				tmp |= (LVDS_ON | LVDS_BLON);
 			} else {
 				tmp = INREG(LVDS_GEN_CNTL);
 				tmp &= ~(LVDS_ON | LVDS_BLON);
 			}
 			OUTREG(LVDS_GEN_CNTL, tmp);
 			if (value & 0x02) {
 				tmp = INREG(CRTC_EXT_CNTL);
 				tmp |= CRTC_CRT_ON;
 				mirror = 1;
 			} else {
 				tmp = INREG(CRTC_EXT_CNTL);
 				tmp &= ~CRTC_CRT_ON;
 				mirror = 0;
 			}
 			OUTREG(CRTC_EXT_CNTL, tmp);
 			return 0;
 		case FBIO_RADEON_GET_MIRROR:
 			if (!rinfo->is_mobility)
 				return -EINVAL;
 			tmp = INREG(LVDS_GEN_CNTL);
 			if ((LVDS_ON | LVDS_BLON) & tmp)
 				value |= 0x01;
 			tmp = INREG(CRTC_EXT_CNTL);
 			if (CRTC_CRT_ON & tmp)
 				value |= 0x02;
 			return put_user(value, (__u32 __user *)arg);
 		default:
 			return -EINVAL;
 	}
 	return -EINVAL;
 }
 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
 {
         u32 val;
 	u32 tmp_pix_clks;
 	int unblank = 0;
 	if (rinfo->lock_blank)
 		return 0;
 	radeon_engine_idle();
 	val = INREG(CRTC_EXT_CNTL);
         val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
                  CRTC_VSYNC_DIS);
         switch (blank) {
 	case FB_BLANK_VSYNC_SUSPEND:
 		val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
 		break;
 	case FB_BLANK_HSYNC_SUSPEND:
 		val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
 		break;
 	case FB_BLANK_POWERDOWN:
 		val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
 			CRTC_HSYNC_DIS);
 		break;
 	case FB_BLANK_NORMAL:
 		val |= CRTC_DISPLAY_DIS;
 		break;
 	case FB_BLANK_UNBLANK:
 	default:
 		unblank = 1;
         }
 	OUTREG(CRTC_EXT_CNTL, val);
 	switch (rinfo->mon1_type) {
 	case MT_DFP:
 		if (unblank)
 			OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
 				~(FP_FPON | FP_TMDS_EN));
 		else {
 			if (mode_switch || blank == FB_BLANK_NORMAL)
 				break;
 			OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
 		}
 		break;
 	case MT_LCD:
 		del_timer_sync(&rinfo->lvds_timer);
 		val = INREG(LVDS_GEN_CNTL);
 		if (unblank) {
 			u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
 				| LVDS_EN | (rinfo->init_state.lvds_gen_cntl
 					     & (LVDS_DIGON | LVDS_BL_MOD_EN));
 			if ((val ^ target_val) == LVDS_DISPLAY_DIS)
 				OUTREG(LVDS_GEN_CNTL, target_val);
 			else if ((val ^ target_val) != 0) {
 				OUTREG(LVDS_GEN_CNTL, target_val
 				       & ~(LVDS_ON | LVDS_BL_MOD_EN));
 				rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
 				rinfo->init_state.lvds_gen_cntl |=
 					target_val & LVDS_STATE_MASK;
 				if (mode_switch) {
 					radeon_msleep(rinfo->panel_info.pwr_delay);
 					OUTREG(LVDS_GEN_CNTL, target_val);
 				}
 				else {
 					rinfo->pending_lvds_gen_cntl = target_val;
 					mod_timer(&rinfo->lvds_timer,
 					   jiffies +
 					   msecs_to_jiffies(rinfo->panel_info.pwr_delay));
 				}
 			}
 		} else {
 			val |= LVDS_DISPLAY_DIS;
 			OUTREG(LVDS_GEN_CNTL, val);
 			/* We don't do a full switch-off on a simple mode switch */
 			if (mode_switch || blank == FB_BLANK_NORMAL)
 				break;
 			/* Asic bug, when turning off LVDS_ON, we have to make sure
 			 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
 			 */
 			tmp_pix_clks = INPLL(PIXCLKS_CNTL);
 			if (rinfo->is_mobility || rinfo->is_IGP)
 				OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
 			val &= ~(LVDS_BL_MOD_EN);
 			OUTREG(LVDS_GEN_CNTL, val);
 			udelay(100);
 			val &= ~(LVDS_ON | LVDS_EN);
 			OUTREG(LVDS_GEN_CNTL, val);
 			val &= ~LVDS_DIGON;
 			rinfo->pending_lvds_gen_cntl = val;
 			mod_timer(&rinfo->lvds_timer,
 				  jiffies +
 				  msecs_to_jiffies(rinfo->panel_info.pwr_delay));
 			rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
 			rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
 			if (rinfo->is_mobility || rinfo->is_IGP)
 				OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
 		}
 		break;
 	case MT_CRT:
 		// todo: powerdown DAC
 	default:
 		break;
 	}
 	/* let fbcon do a soft blank for us */
 	return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0;
 }
 static int radeonfb_blank (int blank, struct fb_info *info)
 {
         struct radeonfb_info *rinfo = info->par;
 	if (rinfo->asleep)
 		return 0;
 	return radeon_screen_blank(rinfo, blank, 0);
 }
 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
                              unsigned blue, unsigned transp,
 			     struct radeonfb_info *rinfo)
 {
 	u32 pindex;
 	unsigned int i;
 	if (regno > 255)
 		return 1;
 	red >>= 8;
 	green >>= 8;
 	blue >>= 8;
 	rinfo->palette[regno].red = red;
 	rinfo->palette[regno].green = green;
 	rinfo->palette[regno].blue = blue;
         /* default */
         pindex = regno;
         if (!rinfo->asleep) {
 		radeon_fifo_wait(9);
 		if (rinfo->bpp == 16) {
 			pindex = regno * 8;
 			if (rinfo->depth == 16 && regno > 63)
 				return 1;
 			if (rinfo->depth == 15 && regno > 31)
 				return 1;
 			/* For 565, the green component is mixed one order
 			 * below
 			 */
 			if (rinfo->depth == 16) {
 		                OUTREG(PALETTE_INDEX, pindex>>1);
 	       	         	OUTREG(PALETTE_DATA,
 				       (rinfo->palette[regno>>1].red << 16) |
 	                        	(green << 8) |
 				       (rinfo->palette[regno>>1].blue));
 	                	green = rinfo->palette[regno<<1].green;
 	        	}
 		}
 		if (rinfo->depth != 16 || regno < 32) {
 			OUTREG(PALETTE_INDEX, pindex);
 			OUTREG(PALETTE_DATA, (red << 16) |
 			       (green << 8) | blue);
 		}
 	}
  	if (regno < 16) {
 		u32 *pal = rinfo->info->pseudo_palette;
         	switch (rinfo->depth) {
 		case 15:
 			pal[regno] = (regno << 10) | (regno << 5) | regno;
 			break;
 		case 16:
 			pal[regno] = (regno << 11) | (regno << 5) | regno;
 			break;
 		case 24:
 			pal[regno] = (regno << 16) | (regno << 8) | regno;
 			break;
 		case 32:
 			i = (regno << 8) | regno;
 			pal[regno] = (i << 16) | i;
 			break;
 		}
         }
 	return 0;
 }
 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
 			       unsigned blue, unsigned transp,
 			       struct fb_info *info)
 {
         struct radeonfb_info *rinfo = info->par;
 	u32 dac_cntl2, vclk_cntl = 0;
 	int rc;
         if (!rinfo->asleep) {
 		if (rinfo->is_mobility) {
 			vclk_cntl = INPLL(VCLK_ECP_CNTL);
 			OUTPLL(VCLK_ECP_CNTL,
 			       vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
 		}
 		/* Make sure we are on first palette */
 		if (rinfo->has_CRTC2) {
 			dac_cntl2 = INREG(DAC_CNTL2);
 			dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
 			OUTREG(DAC_CNTL2, dac_cntl2);
 		}
 	}
 	rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
 	if (!rinfo->asleep && rinfo->is_mobility)
 		OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
 	return rc;
 }
 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
 {
         struct radeonfb_info *rinfo = info->par;
 	u16 *red, *green, *blue, *transp;
 	u32 dac_cntl2, vclk_cntl = 0;
 	int i, start, rc = 0;
         if (!rinfo->asleep) {
 		if (rinfo->is_mobility) {
 			vclk_cntl = INPLL(VCLK_ECP_CNTL);
 			OUTPLL(VCLK_ECP_CNTL,
 			       vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
 		}
 		/* Make sure we are on first palette */
 		if (rinfo->has_CRTC2) {
 			dac_cntl2 = INREG(DAC_CNTL2);
 			dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
 			OUTREG(DAC_CNTL2, dac_cntl2);
 		}
 	}
 	red = cmap->red;
 	green = cmap->green;
 	blue = cmap->blue;
 	transp = cmap->transp;
 	start = cmap->start;
 	for (i = 0; i < cmap->len; i++) {
 		u_int hred, hgreen, hblue, htransp = 0xffff;
 		hred = *red++;
 		hgreen = *green++;
 		hblue = *blue++;
 		if (transp)
 			htransp = *transp++;
 		rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
 				       rinfo);
 		if (rc)
 			break;
 	}
 	if (!rinfo->asleep && rinfo->is_mobility)
 		OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
 	return rc;
 }
 static void radeon_save_state (struct radeonfb_info *rinfo,
 			       struct radeon_regs *save)
 {
 	/* CRTC regs */
 	save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
 	save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
 	save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
 	save->dac_cntl = INREG(DAC_CNTL);
         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
 	save->crtc_pitch = INREG(CRTC_PITCH);
 	save->surface_cntl = INREG(SURFACE_CNTL);
 	/* FP regs */
 	save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
 	save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
 	save->fp_gen_cntl = INREG(FP_GEN_CNTL);
 	save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
 	save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
 	save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
 	save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
 	save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
 	save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
 	save->tmds_crc = INREG(TMDS_CRC);
 	save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
 	save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
 	/* PLL regs */
 	save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
 	radeon_pll_errata_after_index(rinfo);
 	save->ppll_div_3 = INPLL(PPLL_DIV_3);
 	save->ppll_ref_div = INPLL(PPLL_REF_DIV);
 }
 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
 {
 	int i;
 	radeon_fifo_wait(20);
 	/* Workaround from XFree */
 	if (rinfo->is_mobility) {
 	        /* A temporal workaround for the occational blanking on certain laptop
 		 * panels. This appears to related to the PLL divider registers
 		 * (fail to lock?). It occurs even when all dividers are the same
 		 * with their old settings. In this case we really don't need to
 		 * fiddle with PLL registers. By doing this we can avoid the blanking
 		 * problem with some panels.
 	         */
 		if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
 		    (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
 					  (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
 			/* We still have to force a switch to selected PPLL div thanks to
 			 * an XFree86 driver bug which will switch it away in some cases
 			 * even when using UseFDev */
 			OUTREGP(CLOCK_CNTL_INDEX,
 				mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
 				~PPLL_DIV_SEL_MASK);
 			radeon_pll_errata_after_index(rinfo);
 			radeon_pll_errata_after_data(rinfo);
             		return;
 		}
 	}
 	/* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
 	OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
 	/* Reset PPLL & enable atomic update */
 	OUTPLLP(PPLL_CNTL,
 		PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
 		~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
 	/* Switch to selected PPLL divider */
 	OUTREGP(CLOCK_CNTL_INDEX,
 		mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
 		~PPLL_DIV_SEL_MASK);
 	radeon_pll_errata_after_index(rinfo);
 	radeon_pll_errata_after_data(rinfo);
 	/* Set PPLL ref. div */
 	if (rinfo->family == CHIP_FAMILY_R300 ||
 	    rinfo->family == CHIP_FAMILY_RS300 ||
 	    rinfo->family == CHIP_FAMILY_R350 ||
 	    rinfo->family == CHIP_FAMILY_RV350) {
 		if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 			/* When restoring console mode, use saved PPLL_REF_DIV
 			 * setting.
 			 */
 			OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
 		} else {
 			/* R300 uses ref_div_acc field as real ref divider */
 			OUTPLLP(PPLL_REF_DIV,
 				(mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 				~R300_PPLL_REF_DIV_ACC_MASK);
 		}
 	} else
 		OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
 	/* Set PPLL divider 3 & post divider*/
 	OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
 	OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
 	/* Write update */
 	while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
 		;
 	OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
 	/* Wait read update complete */
 	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 	   the cause yet, but this workaround will mask the problem for now.
 	   Other chips usually will pass at the very first test, so the
 	   workaround shouldn't have any effect on them. */
 	for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
 		;
 	OUTPLL(HTOTAL_CNTL, 0);
 	/* Clear reset & atomic update */
 	OUTPLLP(PPLL_CNTL, 0,
 		~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
 	/* We may want some locking ... oh well */
        	radeon_msleep(5);
 	/* Switch back VCLK source to PPLL */
 	OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
 }
 /*
  * Timer function for delayed LVDS panel power up/down
  */
 static void radeon_lvds_timer_func(unsigned long data)
 {
 	struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
 	radeon_engine_idle();
 	OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
 }
 /*
  * Apply a video mode. This will apply the whole register set, including
  * the PLL registers, to the card
  */
 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
 			int regs_only)
 {
 	int i;
 	int primary_mon = PRIMARY_MONITOR(rinfo);
 	if (nomodeset)
 		return;
 	if (!regs_only)
 		radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
 	radeon_fifo_wait(31);
 	for (i=0; i<10; i++)
 		OUTREG(common_regs[i].reg, common_regs[i].val);
 	/* Apply surface registers */
 	for (i=0; i<8; i++) {
 		OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
 		OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
 		OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
 	}
 	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
 	OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
 		~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
 	OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
 	OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
 	OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
 	OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
 	OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
 	OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
 	OUTREG(CRTC_OFFSET, 0);
 	OUTREG(CRTC_OFFSET_CNTL, 0);
 	OUTREG(CRTC_PITCH, mode->crtc_pitch);
 	OUTREG(SURFACE_CNTL, mode->surface_cntl);
 	radeon_write_pll_regs(rinfo, mode);
 	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
 		radeon_fifo_wait(10);
 		OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
 		OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
 		OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
 		OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
 		OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
 		OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
 		OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
 		OUTREG(TMDS_CRC, mode->tmds_crc);
 		OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
 	}
 	if (!regs_only)
 		radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
 	radeon_fifo_wait(2);
 	OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
 	return;
 }
 /*
  * Calculate the PLL values for a given mode
  */
 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
 				 unsigned long freq)
 {
 	const struct {
 		int divider;
 		int bitvalue;
 	} *post_div,
 	  post_divs[] = {
 		{ 1,  0 },
 		{ 2,  1 },
 		{ 4,  2 },
 		{ 8,  3 },
 		{ 3,  4 },
 		{ 16, 5 },
 		{ 6,  6 },
 		{ 12, 7 },
 		{ 0,  0 },
 	};
 	int fb_div, pll_output_freq = 0;
 	int uses_dvo = 0;
 	/* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
 	 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
 	 * recent than an r(v)100...
 	 */
 #if 1
 	/* XXX I had reports of flicker happening with the cinema display
 	 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
 	 * this case. This could just be a bandwidth calculation issue, I
 	 * haven't implemented the bandwidth code yet, but in the meantime,
 	 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
 	 * I haven't seen a case were were absolutely needed an odd PLL
 	 * divider. I'll find a better fix once I have more infos on the
 	 * real cause of the problem.
 	 */
 	while (rinfo->has_CRTC2) {
 		u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
 		u32 disp_output_cntl;
 		int source;
 		/* FP2 path not enabled */
 		if ((fp2_gen_cntl & FP2_ON) == 0)
 			break;
 		/* Not all chip revs have the same format for this register,
 		 * extract the source selection
 		 */
 		if (rinfo->family == CHIP_FAMILY_R200 ||
 		    rinfo->family == CHIP_FAMILY_R300 ||
 		    rinfo->family == CHIP_FAMILY_R350 ||
 		    rinfo->family == CHIP_FAMILY_RV350) {
 			source = (fp2_gen_cntl >> 10) & 0x3;
 			/* sourced from transform unit, check for transform unit
 			 * own source
 			 */
 			if (source == 3) {
 				disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
 				source = (disp_output_cntl >> 12) & 0x3;
 			}
 		} else
 			source = (fp2_gen_cntl >> 13) & 0x1;
 		/* sourced from CRTC2 -> exit */
 		if (source == 1)
 			break;
 		/* so we end up on CRTC1, let's set uses_dvo to 1 now */
 		uses_dvo = 1;
 		break;
 	}
 #else
 	uses_dvo = 1;
 #endif
 	if (freq > rinfo->pll.ppll_max)
 		freq = rinfo->pll.ppll_max;
 	if (freq*12 < rinfo->pll.ppll_min)
 		freq = rinfo->pll.ppll_min / 12;
 	RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
 	       freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
 	for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 		pll_output_freq = post_div->divider * freq;
 		/* If we output to the DVO port (external TMDS), we don't allow an
 		 * odd PLL divider as those aren't supported on this path
 		 */
 		if (uses_dvo && (post_div->divider & 1))
 			continue;
 		if (pll_output_freq >= rinfo->pll.ppll_min  &&
 		    pll_output_freq <= rinfo->pll.ppll_max)
 			break;
 	}
 	/* If we fall through the bottom, try the "default value"
 	   given by the terminal post_div->bitvalue */
 	if ( !post_div->divider ) {
 		post_div = &post_divs[post_div->bitvalue];
 		pll_output_freq = post_div->divider * freq;
 	}
 	RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
 	       rinfo->pll.ref_div, rinfo->pll.ref_clk,
 	       pll_output_freq);
 	/* If we fall through the bottom, try the "default value"
 	   given by the terminal post_div->bitvalue */
 	if ( !post_div->divider ) {
 		post_div = &post_divs[post_div->bitvalue];
 		pll_output_freq = post_div->divider * freq;
 	}
 	RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
 	       rinfo->pll.ref_div, rinfo->pll.ref_clk,
 	       pll_output_freq);
 	fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
 				  rinfo->pll.ref_clk);
 	regs->ppll_ref_div = rinfo->pll.ref_div;
 	regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
 	RTRACE("post div = 0x%x\n", post_div->bitvalue);
 	RTRACE("fb_div = 0x%x\n", fb_div);
 	RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
 }
 static int radeonfb_set_par(struct fb_info *info)
 {
 	struct radeonfb_info *rinfo = info->par;
 	struct fb_var_screeninfo *mode = &info->var;
 	struct radeon_regs *newmode;
 	int hTotal, vTotal, hSyncStart, hSyncEnd,
 	    hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
 	u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
 	u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
 	u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
 	int i, freq;
 	int format = 0;
 	int nopllcalc = 0;
 	int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
 	int primary_mon = PRIMARY_MONITOR(rinfo);
 	int depth = var_to_depth(mode);
 	int use_rmx = 0;
 	newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
 	if (!newmode)
 		return -ENOMEM;
 	/* We always want engine to be idle on a mode switch, even
 	 * if we won't actually change the mode
 	 */
 	radeon_engine_idle();
 	hSyncStart = mode->xres + mode->right_margin;
 	hSyncEnd = hSyncStart + mode->hsync_len;
 	hTotal = hSyncEnd + mode->left_margin;
 	vSyncStart = mode->yres + mode->lower_margin;
 	vSyncEnd = vSyncStart + mode->vsync_len;
 	vTotal = vSyncEnd + mode->upper_margin;
 	pixClock = mode->pixclock;
 	sync = mode->sync;
 	h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 	v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 	if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
 		if (rinfo->panel_info.xres < mode->xres)
 			mode->xres = rinfo->panel_info.xres;
 		if (rinfo->panel_info.yres < mode->yres)
 			mode->yres = rinfo->panel_info.yres;
 		hTotal = mode->xres + rinfo->panel_info.hblank;
 		hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
 		hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
 		vTotal = mode->yres + rinfo->panel_info.vblank;
 		vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
 		vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
 		h_sync_pol = !rinfo->panel_info.hAct_high;
 		v_sync_pol = !rinfo->panel_info.vAct_high;
 		pixClock = 100000000 / rinfo->panel_info.clock;
 		if (rinfo->panel_info.use_bios_dividers) {
 			nopllcalc = 1;
 			newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
 				(rinfo->panel_info.post_divider << 16);
 			newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
 		}
 	}
 	dotClock = 1000000000 / pixClock;
 	freq = dotClock / 10; /* x100 */
 	RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
 		hSyncStart, hSyncEnd, hTotal);
 	RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
 		vSyncStart, vSyncEnd, vTotal);
 	hsync_wid = (hSyncEnd - hSyncStart) / 8;
 	vsync_wid = vSyncEnd - vSyncStart;
 	if (hsync_wid == 0)
 		hsync_wid = 1;
 	else if (hsync_wid > 0x3f)	/* max */
 		hsync_wid = 0x3f;
 	if (vsync_wid == 0)
 		vsync_wid = 1;
 	else if (vsync_wid > 0x1f)	/* max */
 		vsync_wid = 0x1f;
 	hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 	vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 	cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
 	format = radeon_get_dstbpp(depth);
 	bytpp = mode->bits_per_pixel >> 3;
 	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
 		hsync_fudge = hsync_fudge_fp[format-1];
 	else
 		hsync_fudge = hsync_adj_tab[format-1];
 	hsync_start = hSyncStart - 8 + hsync_fudge;
 	newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
 				(format << 8);
 	/* Clear auto-center etc... */
 	newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
 	newmode->crtc_more_cntl &= 0xfffffff0;
 	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
 		newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
 		if (mirror)
 			newmode->crtc_ext_cntl |= CRTC_CRT_ON;
 		newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
 					   CRTC_INTERLACE_EN);
 	} else {
 		newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
 					CRTC_CRT_ON;
 	}
 	newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
 			   DAC_8BIT_EN;
 	newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
 				     (((mode->xres / 8) - 1) << 16));
 	newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
 					(hsync_wid << 16) | (h_sync_pol << 23));
 	newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
 				    ((mode->yres - 1) << 16);
 	newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
 					 (vsync_wid << 16) | (v_sync_pol  << 23));
 	if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
 		/* We first calculate the engine pitch */
 		rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
  				& ~(0x3f)) >> 6;
 		/* Then, re-multiply it to get the CRTC pitch */
 		newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
 	} else
 		newmode->crtc_pitch = (mode->xres_virtual >> 3);
 	newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
 	/*
 	 * It looks like recent chips have a problem with SURFACE_CNTL,
 	 * setting SURF_TRANSLATION_DIS completely disables the
 	 * swapper as well, so we leave it unset now.
 	 */
 	newmode->surface_cntl = 0;
 #if defined(__BIG_ENDIAN)
 	/* Setup swapping on both apertures, though we currently
 	 * only use aperture 0, enabling swapper on aperture 1
 	 * won't harm
 	 */
 	switch (mode->bits_per_pixel) {
 		case 16:
 			newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
 			newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
 			break;
 		case 24:
 		case 32:
 			newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
 			newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
 			break;
 	}
 #endif
 	/* Clear surface registers */
 	for (i=0; i<8; i++) {
 		newmode->surf_lower_bound[i] = 0;
 		newmode->surf_upper_bound[i] = 0x1f;
 		newmode->surf_info[i] = 0;
 	}
 	RTRACE("h_total_disp = 0x%x\t   hsync_strt_wid = 0x%x\n",
 		newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
 	RTRACE("v_total_disp = 0x%x\t   vsync_strt_wid = 0x%x\n",
 		newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
 	rinfo->bpp = mode->bits_per_pixel;
 	rinfo->depth = depth;
 	RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
 	RTRACE("freq = %lu\n", (unsigned long)freq);
 	/* We use PPLL_DIV_3 */
 	newmode->clk_cntl_index = 0x300;
 	/* Calculate PPLL value if necessary */
 	if (!nopllcalc)
 		radeon_calc_pll_regs(rinfo, newmode, freq);
 	newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
 	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
 		unsigned int hRatio, vRatio;
 		if (mode->xres > rinfo->panel_info.xres)
 			mode->xres = rinfo->panel_info.xres;
 		if (mode->yres > rinfo->panel_info.yres)
 			mode->yres = rinfo->panel_info.yres;
 		newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
 					   << HORZ_PANEL_SHIFT);
 		newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
 					   << VERT_PANEL_SHIFT);
 		if (mode->xres != rinfo->panel_info.xres) {
 			hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
 					   rinfo->panel_info.xres);
 			newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
 						   (newmode->fp_horz_stretch &
 						    (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
 						     HORZ_AUTO_RATIO_INC)));
 			newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
 						    HORZ_STRETCH_ENABLE);
 			use_rmx = 1;
 		}
 		newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
 		if (mode->yres != rinfo->panel_info.yres) {
 			vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
 					   rinfo->panel_info.yres);
 			newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
 						   (newmode->fp_vert_stretch &
 						   (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
 			newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
 						    VERT_STRETCH_ENABLE);
 			use_rmx = 1;
 		}
 		newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
 		newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
 				       ~(FP_SEL_CRTC2 |
 					 FP_RMX_HVSYNC_CONTROL_EN |
 					 FP_DFP_SYNC_SEL |
 					 FP_CRT_SYNC_SEL |
 					 FP_CRTC_LOCK_8DOT |
 					 FP_USE_SHADOW_EN |
 					 FP_CRTC_USE_SHADOW_VEND |
 					 FP_CRT_SYNC_ALT));
 		newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
 					FP_CRTC_DONT_SHADOW_HEND |
 					FP_PANEL_FORMAT);
 		if (IS_R300_VARIANT(rinfo) ||
 		    (rinfo->family == CHIP_FAMILY_R200)) {
 			newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 			if (use_rmx)
 				newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 			else
 				newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 		} else
 			newmode->fp_gen_cntl |= FP_SEL_CRTC1;
 		newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
 		newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
 		newmode->tmds_crc = rinfo->init_state.tmds_crc;
 		newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
 		if (primary_mon == MT_LCD) {
 			newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
 			newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
 		} else {
 			/* DFP */
 			newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
 			newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
 			/* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
 			if (IS_R300_VARIANT(rinfo) ||
 			    (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
 				newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
 			else
 				newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
 			newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
 		}
 		newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
 				(((mode->xres / 8) - 1) << 16));
 		newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
 				((mode->yres - 1) << 16);
 		newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
 				(hsync_wid << 16) | (h_sync_pol << 23));
 		newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
 				(vsync_wid << 16) | (v_sync_pol  << 23));
 	}
 	/* do it! */
 	if (!rinfo->asleep) {
 		memcpy(&rinfo->state, newmode, sizeof(*newmode));
 		radeon_write_mode (rinfo, newmode, 0);
 		/* (re)initialize the engine */
 		if (!(info->flags & FBINFO_HWACCEL_DISABLED))
 			radeonfb_engine_init (rinfo);
 	}
 	/* Update fix */
 	if (!(info->flags & FBINFO_HWACCEL_DISABLED))
         	info->fix.line_length = rinfo->pitch*64;
         else
 		info->fix.line_length = mode->xres_virtual
 			* ((mode->bits_per_pixel + 1) / 8);
         info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
 		: FB_VISUAL_DIRECTCOLOR;
 #ifdef CONFIG_BOOTX_TEXT
 	/* Update debug text engine */
 	btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
 			     rinfo->depth, info->fix.line_length);
 #endif
 	kfree(newmode);
 	return 0;
 }
 static struct fb_ops radeonfb_ops = {
 	.owner			= THIS_MODULE,
 	.fb_check_var		= radeonfb_check_var,
 	.fb_set_par		= radeonfb_set_par,
 	.fb_setcolreg		= radeonfb_setcolreg,
 	.fb_setcmap		= radeonfb_setcmap,
 	.fb_pan_display 	= radeonfb_pan_display,
 	.fb_blank		= radeonfb_blank,
 	.fb_ioctl		= radeonfb_ioctl,
 	.fb_sync		= radeonfb_sync,
 	.fb_fillrect		= radeonfb_fillrect,
 	.fb_copyarea		= radeonfb_copyarea,
 	.fb_imageblit		= radeonfb_imageblit,
 	.fb_cursor		= soft_cursor,
 };
 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
 {
 	struct fb_info *info = rinfo->info;
 	info->par = rinfo;
 	info->pseudo_palette = rinfo->pseudo_palette;
 	info->flags = FBINFO_DEFAULT
 		    | FBINFO_HWACCEL_COPYAREA
 		    | FBINFO_HWACCEL_FILLRECT
 		    | FBINFO_HWACCEL_XPAN
 		    | FBINFO_HWACCEL_YPAN;
 	info->fbops = &radeonfb_ops;
 	info->screen_base = rinfo->fb_base;
 	info->screen_size = rinfo->mapped_vram;
 	/* Fill fix common fields */
 	strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
         info->fix.smem_start = rinfo->fb_base_phys;
         info->fix.smem_len = rinfo->video_ram;
         info->fix.type = FB_TYPE_PACKED_PIXELS;
         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
         info->fix.xpanstep = 8;
         info->fix.ypanstep = 1;
         info->fix.ywrapstep = 0;
         info->fix.type_aux = 0;
         info->fix.mmio_start = rinfo->mmio_base_phys;
         info->fix.mmio_len = RADEON_REGSIZE;
 	info->fix.accel = FB_ACCEL_ATI_RADEON;
 	fb_alloc_cmap(&info->cmap, 256, 0);
 	if (noaccel)
 		info->flags |= FBINFO_HWACCEL_DISABLED;
         return 0;
 }
 #ifdef CONFIG_PMAC_BACKLIGHT
 /* TODO: Dbl check these tables, we don't go up to full ON backlight
  * in these, possibly because we noticed MacOS doesn't, but I'd prefer
  * having some more official numbers from ATI
  */
 static int backlight_conv_m6[] = {
 	0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
 	0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
 };
 static int backlight_conv_m7[] = {
 	0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
 	0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
 };
 #define BACKLIGHT_LVDS_OFF
 #undef BACKLIGHT_DAC_OFF
 /* We turn off the LCD completely instead of just dimming the backlight.
  * This provides some greater power saving and the display is useless
  * without backlight anyway.
  */
 static int radeon_set_backlight_enable(int on, int level, void *data)
 {
 	struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
 	u32 lvds_gen_cntl, tmpPixclksCntl;
 	int* conv_table;
 	if (rinfo->mon1_type != MT_LCD)
 		return 0;
 	/* Pardon me for that hack... maybe some day we can figure
 	 * out in what direction backlight should work on a given
 	 * panel ?
 	 */
 	if ((rinfo->family == CHIP_FAMILY_RV200 ||
 	     rinfo->family == CHIP_FAMILY_RV250 ||
 	     rinfo->family == CHIP_FAMILY_RV280 ||
 	     rinfo->family == CHIP_FAMILY_RV350) &&
 	    !machine_is_compatible("PowerBook4,3") &&
 	    !machine_is_compatible("PowerBook6,3") &&
 	    !machine_is_compatible("PowerBook6,5"))
 		conv_table = backlight_conv_m7;
 	else
 		conv_table = backlight_conv_m6;
 	del_timer_sync(&rinfo->lvds_timer);
 	radeon_engine_idle();
 	lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
 	if (on && (level > BACKLIGHT_OFF)) {
 		lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
 		if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) {
 			lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON);
 			lvds_gen_cntl |= LVDS_BLON | LVDS_EN;
 			OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
 			lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
 			lvds_gen_cntl |= (conv_table[level] <<
 					  LVDS_BL_MOD_LEVEL_SHIFT);
 			lvds_gen_cntl |= LVDS_ON;
 			lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN);
 			rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
 			mod_timer(&rinfo->lvds_timer,
 				  jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
 		} else {
 			lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
 			lvds_gen_cntl |= (conv_table[level] <<
 					  LVDS_BL_MOD_LEVEL_SHIFT);
 			OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
 		}
 		rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
 		rinfo->init_state.lvds_gen_cntl |= rinfo->pending_lvds_gen_cntl
 			& LVDS_STATE_MASK;
 	} else {
 		/* Asic bug, when turning off LVDS_ON, we have to make sure
 		   RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
 		*/
 		tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
 		if (rinfo->is_mobility || rinfo->is_IGP)
 			OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
 		lvds_gen_cntl &= ~(LVDS_BL_MOD_LEVEL_MASK | LVDS_BL_MOD_EN);
 		lvds_gen_cntl |= (conv_table[0] <<
 				  LVDS_BL_MOD_LEVEL_SHIFT);
 		lvds_gen_cntl |= LVDS_DISPLAY_DIS;
 		OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
 		udelay(100);
 		lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN);
 		OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
 		lvds_gen_cntl &= ~(LVDS_DIGON);
 		rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
 		mod_timer(&rinfo->lvds_timer,
 			  jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
 		if (rinfo->is_mobility || rinfo->is_IGP)
 			OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
 	}
 	rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
 	rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
 	return 0;
 }
 static int radeon_set_backlight_level(int level, void *data)
 {
 	return radeon_set_backlight_enable(1, level, data);
 }
 #endif /* CONFIG_PMAC_BACKLIGHT */
 /*
  * This reconfigure the card's internal memory map. In theory, we'd like
  * to setup the card's memory at the same address as it's PCI bus address,
  * and the AGP aperture right after that so that system RAM on 32 bits
  * machines at least, is directly accessible. However, doing so would
  * conflict with the current XFree drivers...
  * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
  * on the proper way to set this up and duplicate this here. In the meantime,
  * I put the card's memory at 0 in card space and AGP at some random high
  * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
  */
 #ifdef CONFIG_PPC_OF
 #undef SET_MC_FB_FROM_APERTURE
 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
 {
 	u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
 	u32 save_crtc_ext_cntl;
 	u32 aper_base, aper_size;
 	u32 agp_base;
 	/* First, we disable display to avoid interfering */
 	if (rinfo->has_CRTC2) {
 		save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
 		OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
 	}
 	save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
 	save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
 	OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
 	OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
 	mdelay(100);
 	aper_base = INREG(CONFIG_APER_0_BASE);
 	aper_size = INREG(CONFIG_APER_SIZE);
 #ifdef SET_MC_FB_FROM_APERTURE
 	/* Set framebuffer to be at the same address as set in PCI BAR */
 	OUTREG(MC_FB_LOCATION,
 		((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
 	rinfo->fb_local_base = aper_base;
 #else
 	OUTREG(MC_FB_LOCATION, 0x7fff0000);
 	rinfo->fb_local_base = 0;
 #endif
 	agp_base = aper_base + aper_size;
 	if (agp_base & 0xf0000000)
 		agp_base = (aper_base | 0x0fffffff) + 1;
 	/* Set AGP to be just after the framebuffer on a 256Mb boundary. This
 	 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
 	 * always the case on PPCs afaik.
 	 */
 #ifdef SET_MC_FB_FROM_APERTURE
 	OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
 #else
 	OUTREG(MC_AGP_LOCATION, 0xffffe000);
 #endif
 	/* Fixup the display base addresses & engine offsets while we
 	 * are at it as well
 	 */
 #ifdef SET_MC_FB_FROM_APERTURE
 	OUTREG(DISPLAY_BASE_ADDR, aper_base);
 	if (rinfo->has_CRTC2)
 		OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
 	OUTREG(OV0_BASE_ADDR, aper_base);
 #else
 	OUTREG(DISPLAY_BASE_ADDR, 0);
 	if (rinfo->has_CRTC2)
 		OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
 	OUTREG(OV0_BASE_ADDR, 0);
 #endif
 	mdelay(100);
 	/* Restore display settings */
 	OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
 	OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
 	if (rinfo->has_CRTC2)
 		OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
 	RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
 		aper_base,
 		((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
 		0xffff0000 | (agp_base >> 16));
 }
 #endif /* CONFIG_PPC_OF */
 static void radeon_identify_vram(struct radeonfb_info *rinfo)
 {
 	u32 tmp;
 	/* framebuffer size */
         if ((rinfo->family == CHIP_FAMILY_RS100) ||
             (rinfo->family == CHIP_FAMILY_RS200) ||
             (rinfo->family == CHIP_FAMILY_RS300)) {
           u32 tom = INREG(NB_TOM);
           tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
  		radeon_fifo_wait(6);
           OUTREG(MC_FB_LOCATION, tom);
           OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
           OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
           OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
           /* This is supposed to fix the crtc2 noise problem. */
           OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
           if ((rinfo->family == CHIP_FAMILY_RS100) ||
               (rinfo->family == CHIP_FAMILY_RS200)) {
              /* This is to workaround the asic bug for RMX, some versions
                 of BIOS dosen't have this register initialized correctly.
              */
              OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
                      ~CRTC_H_CUTOFF_ACTIVE_EN);
           }
         } else {
           tmp = INREG(CONFIG_MEMSIZE);
         }
 	/* mem size is bits [28:0], mask off the rest */
 	rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
 	/*
 	 * Hack to get around some busted production M6's
 	 * reporting no ram
 	 */
 	if (rinfo->video_ram == 0) {
 		switch (rinfo->pdev->device) {
 	       	case PCI_CHIP_RADEON_LY:
 		case PCI_CHIP_RADEON_LZ:
 	       		rinfo->video_ram = 8192 * 1024;
 	       		break;
 	       	default:
 	       		break;
 		}
 	}
 	/*
 	 * Now try to identify VRAM type
 	 */
 	if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
 	    (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
 		rinfo->vram_ddr = 1;
 	else
 		rinfo->vram_ddr = 0;
 	tmp = INREG(MEM_CNTL);
 	if (IS_R300_VARIANT(rinfo)) {
 		tmp &=  R300_MEM_NUM_CHANNELS_MASK;
 		switch (tmp) {
 		case 0:  rinfo->vram_width = 64; break;
 		case 1:  rinfo->vram_width = 128; break;
 		case 2:  rinfo->vram_width = 256; break;
 		default: rinfo->vram_width = 128; break;
 		}
 	} else if ((rinfo->family == CHIP_FAMILY_RV100) ||
 		   (rinfo->family == CHIP_FAMILY_RS100) ||
 		   (rinfo->family == CHIP_FAMILY_RS200)){
 		if (tmp & RV100_MEM_HALF_MODE)
 			rinfo->vram_width = 32;
 		else
 			rinfo->vram_width = 64;
 	} else {
 		if (tmp & MEM_NUM_CHANNELS_MASK)
 			rinfo->vram_width = 128;
 		else
 			rinfo->vram_width = 64;
 	}
 	/* This may not be correct, as some cards can have half of channel disabled
 	 * ToDo: identify these cases
 	 */
 	RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
 	       pci_name(rinfo->pdev),
 	       rinfo->video_ram / 1024,
 	       rinfo->vram_ddr ? "DDR" : "SDRAM",
 	       rinfo->vram_width);
 }
 /*
  * Sysfs
  */
 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
 {
 	if (off > EDID_LENGTH)
 		return 0;
 	if (off + count > EDID_LENGTH)
 		count = EDID_LENGTH - off;
 	memcpy(buf, edid + off, count);
 	return count;
 }
 static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
 {
 	struct device *dev = container_of(kobj, struct device, kobj);
 	struct pci_dev *pdev = to_pci_dev(dev);
         struct fb_info *info = pci_get_drvdata(pdev);
         struct radeonfb_info *rinfo = info->par;
 	return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
 }
 static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
 {
 	struct device *dev = container_of(kobj, struct device, kobj);
 	struct pci_dev *pdev = to_pci_dev(dev);
         struct fb_info *info = pci_get_drvdata(pdev);
         struct radeonfb_info *rinfo = info->par;
 	return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
 }
 static struct bin_attribute edid1_attr = {
 	.attr   = {
 		.name	= "edid1",
 		.owner	= THIS_MODULE,
 		.mode	= 0444,
 	},
 	.size	= EDID_LENGTH,
 	.read	= radeon_show_edid1,
 };
 static struct bin_attribute edid2_attr = {
 	.attr   = {
 		.name	= "edid2",
 		.owner	= THIS_MODULE,
 		.mode	= 0444,
 	},
 	.size	= EDID_LENGTH,
 	.read	= radeon_show_edid2,
 };
 static int radeonfb_pci_register (struct pci_dev *pdev,
 				  const struct pci_device_id *ent)
 {
 	struct fb_info *info;
 	struct radeonfb_info *rinfo;
 	int ret;
 	RTRACE("radeonfb_pci_register BEGIN\n");
 	/* Enable device in PCI config */
 	ret = pci_enable_device(pdev);
 	if (ret < 0) {
 		printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
 		       pci_name(pdev));
 		goto err_out;
 	}
 	info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
 	if (!info) {
 		printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
 			pci_name(pdev));
 		ret = -ENOMEM;
 		goto err_disable;
 	}
 	rinfo = info->par;
 	rinfo->info = info;
 	rinfo->pdev = pdev;
 	spin_lock_init(&rinfo->reg_lock);
 	init_timer(&rinfo->lvds_timer);
 	rinfo->lvds_timer.function = radeon_lvds_timer_func;
 	rinfo->lvds_timer.data = (unsigned long)rinfo;
 	strcpy(rinfo->name, "ATI Radeon XX ");
 	rinfo->name[11] = ent->device >> 8;
 	rinfo->name[12] = ent->device & 0xFF;
 	rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
 	rinfo->chipset = pdev->device;
 	rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
 	rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
 	rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
 	/* Set base addrs */
 	rinfo->fb_base_phys = pci_resource_start (pdev, 0);
 	rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
 	/* request the mem regions */
 	ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
 	if (ret < 0) {
 		printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
 			pci_name(rinfo->pdev));
 		goto err_release_fb;
 	}
 	ret = pci_request_region(pdev, 2, "radeonfb mmio");
 	if (ret < 0) {
 		printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
 			pci_name(rinfo->pdev));
 		goto err_release_pci0;
 	}
 	/* map the regions */
 	rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
 	if (!rinfo->mmio_base) {
 		printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
 		       pci_name(rinfo->pdev));
 		ret = -EIO;
 		goto err_release_pci2;
 	}
 	rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
 	/*
 	 * Check for errata
 	 */
 	rinfo->errata = 0;
 	if (rinfo->family == CHIP_FAMILY_R300 &&
 	    (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
 	    == CFG_ATI_REV_A11)
 		rinfo->errata |= CHIP_ERRATA_R300_CG;
 	if (rinfo->family == CHIP_FAMILY_RV200 ||
 	    rinfo->family == CHIP_FAMILY_RS200)
 		rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
 	if (rinfo->family == CHIP_FAMILY_RV100 ||
 	    rinfo->family == CHIP_FAMILY_RS100 ||
 	    rinfo->family == CHIP_FAMILY_RS200)
 		rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
 #ifdef CONFIG_PPC_OF
 	/* On PPC, we obtain the OF device-node pointer to the firmware
 	 * data for this chip
 	 */
 	rinfo->of_node = pci_device_to_OF_node(pdev);
 	if (rinfo->of_node == NULL)
 		printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
 		       pci_name(rinfo->pdev));
 	/* On PPC, the firmware sets up a memory mapping that tends
 	 * to cause lockups when enabling the engine. We reconfigure
 	 * the card internal memory mappings properly
 	 */
 	fixup_memory_mappings(rinfo);
 #endif /* CONFIG_PPC_OF */
 	/* Get VRAM size and type */
 	radeon_identify_vram(rinfo);
 	rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
 	do {
 		rinfo->fb_base = ioremap (rinfo->fb_base_phys,
 					  rinfo->mapped_vram);
 	} while (   rinfo->fb_base == 0 &&
 		  ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
 	if (rinfo->fb_base == NULL) {
 		printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
 			pci_name(rinfo->pdev));
 		ret = -EIO;
 		goto err_unmap_rom;
 	}
 	RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
 	       rinfo->mapped_vram/1024);
 	/*
 	 * Map the BIOS ROM if any and retreive PLL parameters from
 	 * the BIOS. We skip that on mobility chips as the real panel
 	 * values we need aren't in the ROM but in the BIOS image in
 	 * memory. This is definitely not the best meacnism though,
 	 * we really need the arch code to tell us which is the "primary"
 	 * video adapter to use the memory image (or better, the arch
 	 * should provide us a copy of the BIOS image to shield us from
 	 * archs who would store that elsewhere and/or could initialize
 	 * more than one adapter during boot).
 	 */
 	if (!rinfo->is_mobility)
 		radeon_map_ROM(rinfo, pdev);
 	/*
 	 * On x86, the primary display on laptop may have it's BIOS
 	 * ROM elsewhere, try to locate it at the legacy memory hole.
 	 * We probably need to make sure this is the primary display,
 	 * but that is difficult without some arch support.
 	 */
 #ifdef CONFIG_X86
 	if (rinfo->bios_seg == NULL)
 		radeon_find_mem_vbios(rinfo);
 #endif
 	/* If both above failed, try the BIOS ROM again for mobility
 	 * chips
 	 */
 	if (rinfo->bios_seg == NULL && rinfo->is_mobility)
 		radeon_map_ROM(rinfo, pdev);
 	/* Get informations about the board's PLL */
 	radeon_get_pllinfo(rinfo);
 #ifdef CONFIG_FB_RADEON_I2C
 	/* Register I2C bus */
 	radeon_create_i2c_busses(rinfo);
 #endif
 	/* set all the vital stuff */
 	radeon_set_fbinfo (rinfo);
 	/* Probe screen types */
 	radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
 	/* Build mode list, check out panel native model */
 	radeon_check_modes(rinfo, mode_option);
 	/* Register some sysfs stuff (should be done better) */
 	if (rinfo->mon1_EDID)
 		sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
 	if (rinfo->mon2_EDID)
 		sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
 	/* save current mode regs before we switch into the new one
 	 * so we can restore this upon __exit
 	 */
 	radeon_save_state (rinfo, &rinfo->init_state);
 	memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
 	/* Setup Power Management capabilities */
 	if (default_dynclk < -1) {
 		/* -2 is special: means  ON on mobility chips and do not
 		 * change on others
 		 */
 		radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1);
 	} else
 		radeonfb_pm_init(rinfo, default_dynclk);
 	pci_set_drvdata(pdev, info);
 	/* Register with fbdev layer */
 	ret = register_framebuffer(info);
 	if (ret < 0) {
 		printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
 			pci_name(rinfo->pdev));
 		goto err_unmap_fb;
 	}
 #ifdef CONFIG_MTRR
 	rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
 						 rinfo->video_ram,
 						 MTRR_TYPE_WRCOMB, 1);
 #endif
 #ifdef CONFIG_PMAC_BACKLIGHT
 	if (rinfo->mon1_type == MT_LCD) {
 		register_backlight_controller(&radeon_backlight_controller,
 					      rinfo, "ati");
 		register_backlight_controller(&radeon_backlight_controller,
 					      rinfo, "mnca");
 	}
 #endif
 	printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
 	if (rinfo->bios_seg)
 		radeon_unmap_ROM(rinfo, pdev);
 	RTRACE("radeonfb_pci_register END\n");
 	return 0;
 err_unmap_fb:
 	iounmap(rinfo->fb_base);
 err_unmap_rom:
 	kfree(rinfo->mon1_EDID);
 	kfree(rinfo->mon2_EDID);
 	if (rinfo->mon1_modedb)
 		fb_destroy_modedb(rinfo->mon1_modedb);
 	fb_dealloc_cmap(&info->cmap);
 #ifdef CONFIG_FB_RADEON_I2C
 	radeon_delete_i2c_busses(rinfo);
 #endif
 	if (rinfo->bios_seg)
 		radeon_unmap_ROM(rinfo, pdev);
 	iounmap(rinfo->mmio_base);
 err_release_pci2:
 	pci_release_region(pdev, 2);
 err_release_pci0:
 	pci_release_region(pdev, 0);
 err_release_fb:
         framebuffer_release(info);
 err_disable:
 	pci_disable_device(pdev);
 err_out:
 	return ret;
 }
 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
 {
         struct fb_info *info = pci_get_drvdata(pdev);
         struct radeonfb_info *rinfo = info->par;
         if (!rinfo)
                 return;
 	radeonfb_pm_exit(rinfo);
 	if (rinfo->mon1_EDID)
 		sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
 	if (rinfo->mon2_EDID)
 		sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
 #if 0
 	/* restore original state
 	 *
 	 * Doesn't quite work yet, I suspect if we come from a legacy
 	 * VGA mode (or worse, text mode), we need to do some VGA black
 	 * magic here that I know nothing about. --BenH
 	 */
         radeon_write_mode (rinfo, &rinfo->init_state, 1);
  #endif
 	del_timer_sync(&rinfo->lvds_timer);
 #ifdef CONFIG_MTRR
 	if (rinfo->mtrr_hdl >= 0)
 		mtrr_del(rinfo->mtrr_hdl, 0, 0);
 #endif
         unregister_framebuffer(info);
         iounmap(rinfo->mmio_base);
         iounmap(rinfo->fb_base);
 	pci_release_region(pdev, 2);
 	pci_release_region(pdev, 0);
 	kfree(rinfo->mon1_EDID);
 	kfree(rinfo->mon2_EDID);
 	if (rinfo->mon1_modedb)
 		fb_destroy_modedb(rinfo->mon1_modedb);
 #ifdef CONFIG_FB_RADEON_I2C
 	radeon_delete_i2c_busses(rinfo);
 #endif
 	fb_dealloc_cmap(&info->cmap);
         framebuffer_release(info);
 	pci_disable_device(pdev);
 }
 static struct pci_driver radeonfb_driver = {
 	.name		= "radeonfb",
 	.id_table	= radeonfb_pci_table,
 	.probe		= radeonfb_pci_register,
 	.remove		= __devexit_p(radeonfb_pci_unregister),
 #ifdef CONFIG_PM
 	.suspend       	= radeonfb_pci_suspend,
 	.resume		= radeonfb_pci_resume,
 #endif /* CONFIG_PM */
 };
 #ifndef MODULE
 static int __init radeonfb_setup (char *options)
 {
 	char *this_opt;
 	if (!options || !*options)
 		return 0;
 	while ((this_opt = strsep (&options, ",")) != NULL) {
 		if (!*this_opt)
 			continue;
 		if (!strncmp(this_opt, "noaccel", 7)) {
 			noaccel = 1;
 		} else if (!strncmp(this_opt, "mirror", 6)) {
 			mirror = 1;
 		} else if (!strncmp(this_opt, "force_dfp", 9)) {
 			force_dfp = 1;
 		} else if (!strncmp(this_opt, "panel_yres:", 11)) {
 			panel_yres = simple_strtoul((this_opt+11), NULL, 0);
 #ifdef CONFIG_MTRR
 		} else if (!strncmp(this_opt, "nomtrr", 6)) {
 			nomtrr = 1;
 #endif
 		} else if (!strncmp(this_opt, "nomodeset", 9)) {
 			nomodeset = 1;
 		} else if (!strncmp(this_opt, "force_measure_pll", 17)) {
 			force_measure_pll = 1;
 		} else if (!strncmp(this_opt, "ignore_edid", 11)) {
 			ignore_edid = 1;
 		} else
 			mode_option = this_opt;
 	}
 	return 0;
 }
 #endif  /*  MODULE  */
 static int __init radeonfb_init (void)
 {
 #ifndef MODULE
 	char *option = NULL;
 	if (fb_get_options("radeonfb", &option))
 		return -ENODEV;
 	radeonfb_setup(option);
 #endif
 	return pci_register_driver (&radeonfb_driver);
 }
 static void __exit radeonfb_exit (void)
 {
 	pci_unregister_driver (&radeonfb_driver);
 }
 module_init(radeonfb_init);
 module_exit(radeonfb_exit);
 MODULE_AUTHOR("Ani Joshi");
 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
 MODULE_LICENSE("GPL");
 module_param(noaccel, bool, 0);
 module_param(default_dynclk, int, 0);
 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
 module_param(nomodeset, bool, 0);
 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
 module_param(mirror, bool, 0);
 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
 module_param(force_dfp, bool, 0);
 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
 module_param(ignore_edid, bool, 0);
 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
 module_param(monitor_layout, charp, 0);
 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
 module_param(force_measure_pll, bool, 0);
 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
 #ifdef CONFIG_MTRR
 module_param(nomtrr, bool, 0);
 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
 #endif
 module_param(panel_yres, int, 0);
 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
 module_param(mode_option, charp, 0);
 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");

 #ifndef __RADEONFB_H__
 #define __RADEONFB_H__
 #include <linux/config.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/delay.h>
 #include <linux/pci.h>
 #include <linux/fb.h>
+#ifdef CONFIG_FB_RADEON_I2C
 #include <linux/i2c.h>
-#include <linux/i2c-id.h>
 #include <linux/i2c-algo-bit.h>
+#endif
 #include <asm/io.h>
 #ifdef CONFIG_PPC_OF
 #include <asm/prom.h>
 #endif
 #include <video/radeon.h>
 /***************************************************************
  * Most of the definitions here are adapted right from XFree86 *
  ***************************************************************/
 /*
  * Chip families. Must fit in the low 16 bits of a long word
  */
 enum radeon_family {
 	CHIP_FAMILY_UNKNOW,
 	CHIP_FAMILY_LEGACY,
 	CHIP_FAMILY_RADEON,
 	CHIP_FAMILY_RV100,
 	CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
 	CHIP_FAMILY_RV200,
 	CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
 				 RS250 (IGP 7000) */
 	CHIP_FAMILY_R200,
 	CHIP_FAMILY_RV250,
 	CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
 	CHIP_FAMILY_RV280,
 	CHIP_FAMILY_R300,
 	CHIP_FAMILY_R350,
 	CHIP_FAMILY_RV350,
 	CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
 	CHIP_FAMILY_R420,     /* R420/R423/M18 */
 	CHIP_FAMILY_LAST,
 };
 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
 				 ((rinfo)->family == CHIP_FAMILY_RV200)  || \
 				 ((rinfo)->family == CHIP_FAMILY_RS100)  || \
 				 ((rinfo)->family == CHIP_FAMILY_RS200)  || \
 				 ((rinfo)->family == CHIP_FAMILY_RV250)  || \
 				 ((rinfo)->family == CHIP_FAMILY_RV280)  || \
 				 ((rinfo)->family == CHIP_FAMILY_RS300))
 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
 				((rinfo)->family == CHIP_FAMILY_RV350) || \
 				((rinfo)->family == CHIP_FAMILY_R350)  || \
 				((rinfo)->family == CHIP_FAMILY_RV380) || \
 				((rinfo)->family == CHIP_FAMILY_R420))
 /*
  * Chip flags
  */
 enum radeon_chip_flags {
 	CHIP_FAMILY_MASK	= 0x0000ffffUL,
 	CHIP_FLAGS_MASK		= 0xffff0000UL,
 	CHIP_IS_MOBILITY	= 0x00010000UL,
 	CHIP_IS_IGP		= 0x00020000UL,
 	CHIP_HAS_CRTC2		= 0x00040000UL,
 };
 /*
  * Errata workarounds
  */
 enum radeon_errata {
 	CHIP_ERRATA_R300_CG		= 0x00000001,
 	CHIP_ERRATA_PLL_DUMMYREADS	= 0x00000002,
 	CHIP_ERRATA_PLL_DELAY		= 0x00000004,
 };
 /*
  * Monitor types
  */
 enum radeon_montype {
 	MT_NONE = 0,
 	MT_CRT,		/* CRT */
 	MT_LCD,		/* LCD */
 	MT_DFP,		/* DVI */
 	MT_CTV,		/* composite TV */
 	MT_STV		/* S-Video out */
 };
 /*
  * DDC i2c ports
  */
 enum ddc_type {
 	ddc_none,
 	ddc_monid,
 	ddc_dvi,
 	ddc_vga,
 	ddc_crt2,
 };
 /*
  * Connector types
  */
 enum conn_type {
 	conn_none,
 	conn_proprietary,
 	conn_crt,
 	conn_DVI_I,
 	conn_DVI_D,
 };
 /*
  * PLL infos
  */
 struct pll_info {
 	int ppll_max;
 	int ppll_min;
 	int sclk, mclk;
 	int ref_div;
 	int ref_clk;
 };
 /*
  * This structure contains the various registers manipulated by this
  * driver for setting or restoring a mode. It's mostly copied from
  * XFree's RADEONSaveRec structure. A few chip settings might still be
  * tweaked without beeing reflected or saved in these registers though
  */
 struct radeon_regs {
 	/* Common registers */
 	u32		ovr_clr;
 	u32		ovr_wid_left_right;
 	u32		ovr_wid_top_bottom;
 	u32		ov0_scale_cntl;
 	u32		mpp_tb_config;
 	u32		mpp_gp_config;
 	u32		subpic_cntl;
 	u32		viph_control;
 	u32		i2c_cntl_1;
 	u32		gen_int_cntl;
 	u32		cap0_trig_cntl;
 	u32		cap1_trig_cntl;
 	u32		bus_cntl;
 	u32		surface_cntl;
 	u32		bios_5_scratch;
 	/* Other registers to save for VT switches or driver load/unload */
 	u32		dp_datatype;
 	u32		rbbm_soft_reset;
 	u32		clock_cntl_index;
 	u32		amcgpio_en_reg;
 	u32		amcgpio_mask;
 	/* Surface/tiling registers */
 	u32		surf_lower_bound[8];
 	u32		surf_upper_bound[8];
 	u32		surf_info[8];
 	/* CRTC registers */
 	u32		crtc_gen_cntl;
 	u32		crtc_ext_cntl;
 	u32		dac_cntl;
 	u32		crtc_h_total_disp;
 	u32		crtc_h_sync_strt_wid;
 	u32		crtc_v_total_disp;
 	u32		crtc_v_sync_strt_wid;
 	u32		crtc_offset;
 	u32		crtc_offset_cntl;
 	u32		crtc_pitch;
 	u32		disp_merge_cntl;
 	u32		grph_buffer_cntl;
 	u32		crtc_more_cntl;
 	/* CRTC2 registers */
 	u32		crtc2_gen_cntl;
 	u32		dac2_cntl;
 	u32		disp_output_cntl;
 	u32		disp_hw_debug;
 	u32		disp2_merge_cntl;
 	u32		grph2_buffer_cntl;
 	u32		crtc2_h_total_disp;
 	u32		crtc2_h_sync_strt_wid;
 	u32		crtc2_v_total_disp;
 	u32		crtc2_v_sync_strt_wid;
 	u32		crtc2_offset;
 	u32		crtc2_offset_cntl;
 	u32		crtc2_pitch;
 	/* Flat panel regs */
 	u32 		fp_crtc_h_total_disp;
 	u32		fp_crtc_v_total_disp;
 	u32		fp_gen_cntl;
 	u32		fp2_gen_cntl;
 	u32		fp_h_sync_strt_wid;
 	u32		fp2_h_sync_strt_wid;
 	u32		fp_horz_stretch;
 	u32		fp_panel_cntl;
 	u32		fp_v_sync_strt_wid;
 	u32		fp2_v_sync_strt_wid;
 	u32		fp_vert_stretch;
 	u32		lvds_gen_cntl;
 	u32		lvds_pll_cntl;
 	u32		tmds_crc;
 	u32		tmds_transmitter_cntl;
 	/* Computed values for PLL */
 	u32		dot_clock_freq;
 	int		feedback_div;
 	int		post_div;
 	/* PLL registers */
 	u32		ppll_div_3;
 	u32		ppll_ref_div;
 	u32		vclk_ecp_cntl;
 	u32		clk_cntl_index;
 	/* Computed values for PLL2 */
 	u32		dot_clock_freq_2;
 	int		feedback_div_2;
 	int		post_div_2;
 	/* PLL2 registers */
 	u32		p2pll_ref_div;
 	u32		p2pll_div_0;
 	u32		htotal_cntl2;
        	/* Palette */
 	int		palette_valid;
 };
 struct panel_info {
 	int xres, yres;
 	int valid;
 	int clock;
 	int hOver_plus, hSync_width, hblank;
 	int vOver_plus, vSync_width, vblank;
 	int hAct_high, vAct_high, interlaced;
 	int pwr_delay;
 	int use_bios_dividers;
 	int ref_divider;
 	int post_divider;
 	int fbk_divider;
 };
 struct radeonfb_info;
 #ifdef CONFIG_FB_RADEON_I2C
 struct radeon_i2c_chan {
 	struct radeonfb_info		*rinfo;
 	u32		 		ddc_reg;
 	struct i2c_adapter		adapter;
 	struct i2c_algo_bit_data	algo;
 };
 #endif
 enum radeon_pm_mode {
 	radeon_pm_none	= 0,		/* Nothing supported */
 	radeon_pm_d2	= 0x00000001,	/* Can do D2 state */
 	radeon_pm_off	= 0x00000002,	/* Can resume from D3 cold */
 };
 struct radeonfb_info {
 	struct fb_info		*info;
 	struct radeon_regs 	state;
 	struct radeon_regs	init_state;
 	char			name[DEVICE_NAME_SIZE];
 	unsigned long		mmio_base_phys;
 	unsigned long		fb_base_phys;
 	void __iomem		*mmio_base;
 	void __iomem		*fb_base;
 	unsigned long		fb_local_base;
 	struct pci_dev		*pdev;
 #ifdef CONFIG_PPC_OF
 	struct device_node	*of_node;
 #endif
 	void __iomem		*bios_seg;
 	int			fp_bios_start;
 	u32			pseudo_palette[17];
 	struct { u8 red, green, blue, pad; }
 				palette[256];
 	int			chipset;
 	u8			family;
 	u8			rev;
 	unsigned int		errata;
 	unsigned long		video_ram;
 	unsigned long		mapped_vram;
 	int			vram_width;
 	int			vram_ddr;
 	int			pitch, bpp, depth;
 	int			has_CRTC2;
 	int			is_mobility;
 	int			is_IGP;
 	int			reversed_DAC;
 	int			reversed_TMDS;
 	struct panel_info	panel_info;
 	int			mon1_type;
 	u8			*mon1_EDID;
 	struct fb_videomode	*mon1_modedb;
 	int			mon1_dbsize;
 	int			mon2_type;
 	u8		        *mon2_EDID;
 	u32			dp_gui_master_cntl;
 	struct pll_info		pll;
 	int			mtrr_hdl;
 	int			pm_reg;
 	u32			save_regs[100];
 	int			asleep;
 	int			lock_blank;
 	int			dynclk;
 	int			no_schedule;
 	enum radeon_pm_mode	pm_mode;
 	void			(*reinit_func)(struct radeonfb_info *rinfo);
 	/* Lock on register access */
 	spinlock_t		reg_lock;
 	/* Timer used for delayed LVDS operations */
 	struct timer_list	lvds_timer;
 	u32			pending_lvds_gen_cntl;
 #ifdef CONFIG_FB_RADEON_I2C
 	struct radeon_i2c_chan 	i2c[4];
 #endif
 	u32			cfg_save[64];
 };
 #define PRIMARY_MONITOR(rinfo)	(rinfo->mon1_type)
 /*
  * Debugging stuffs
  */
 #ifdef CONFIG_FB_RADEON_DEBUG
 #define DEBUG		1
 #else
 #define DEBUG		0
 #endif
 #if DEBUG
 #define RTRACE		printk
 #else
 #define RTRACE		if(0) printk
 #endif
 /*
  * IO macros
  */
 /* Note about this function: we have some rare cases where we must not schedule,
  * this typically happen with our special "wake up early" hook which allows us to
  * wake up the graphic chip (and thus get the console back) before everything else
  * on some machines that support that mecanism. At this point, interrupts are off
  * and scheduling is not permitted
  */
 static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
 {
 	if (rinfo->no_schedule || oops_in_progress)
 		mdelay(ms);
 	else
 		msleep(ms);
 }
 #define INREG8(addr)		readb((rinfo->mmio_base)+addr)
 #define OUTREG8(addr,val)	writeb(val, (rinfo->mmio_base)+addr)
 #define INREG16(addr)		readw((rinfo->mmio_base)+addr)
 #define OUTREG16(addr,val)	writew(val, (rinfo->mmio_base)+addr)
 #define INREG(addr)		readl((rinfo->mmio_base)+addr)
 #define OUTREG(addr,val)	writel(val, (rinfo->mmio_base)+addr)
 static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
 		       u32 val, u32 mask)
 {
 	unsigned long flags;
 	unsigned int tmp;
 	spin_lock_irqsave(&rinfo->reg_lock, flags);
 	tmp = INREG(addr);
 	tmp &= (mask);
 	tmp |= (val);
 	OUTREG(addr, tmp);
 	spin_unlock_irqrestore(&rinfo->reg_lock, flags);
 }
 #define OUTREGP(addr,val,mask)	_OUTREGP(rinfo, addr, val,mask)
 /*
  * Note about PLL register accesses:
  *
  * I have removed the spinlock on them on purpose. The driver now
  * expects that it will only manipulate the PLL registers in normal
  * task environment, where radeon_msleep() will be called, protected
  * by a semaphore (currently the console semaphore) so that no conflict
  * will happen on the PLL register index.
  *
  * With the latest changes to the VT layer, this is guaranteed for all
  * calls except the actual drawing/blits which aren't supposed to use
  * the PLL registers anyway
  *
  * This is very important for the workarounds to work properly. The only
  * possible exception to this rule is the call to unblank(), which may
  * be done at irq time if an oops is in progress.
  */
 static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
 {
 	if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
 		return;
 	(void)INREG(CLOCK_CNTL_DATA);
 	(void)INREG(CRTC_GEN_CNTL);
 }
 static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
 {
 	if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
 		/* we can't deal with posted writes here ... */
 		_radeon_msleep(rinfo, 5);
 	}
 	if (rinfo->errata & CHIP_ERRATA_R300_CG) {
 		u32 save, tmp;
 		save = INREG(CLOCK_CNTL_INDEX);
 		tmp = save & ~(0x3f | PLL_WR_EN);
 		OUTREG(CLOCK_CNTL_INDEX, tmp);
 		tmp = INREG(CLOCK_CNTL_DATA);
 		OUTREG(CLOCK_CNTL_INDEX, save);
 	}
 }
 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
 {
 	u32 data;
 	OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
 	radeon_pll_errata_after_index(rinfo);
 	data = INREG(CLOCK_CNTL_DATA);
 	radeon_pll_errata_after_data(rinfo);
 	return data;
 }
 static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
 			    u32 val)
 {
 	OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
 	radeon_pll_errata_after_index(rinfo);
 	OUTREG(CLOCK_CNTL_DATA, val);
 	radeon_pll_errata_after_data(rinfo);
 }
 static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
 			     u32 val, u32 mask)
 {
 	unsigned int tmp;
 	tmp  = __INPLL(rinfo, index);
 	tmp &= (mask);
 	tmp |= (val);
 	__OUTPLL(rinfo, index, tmp);
 }
 #define INPLL(addr)			__INPLL(rinfo, addr)
 #define OUTPLL(index, val)		__OUTPLL(rinfo, index, val)
 #define OUTPLLP(index, val, mask)	__OUTPLLP(rinfo, index, val, mask)
 #define BIOS_IN8(v)  	(readb(rinfo->bios_seg + (v)))
 #define BIOS_IN16(v) 	(readb(rinfo->bios_seg + (v)) | \
 			  (readb(rinfo->bios_seg + (v) + 1) << 8))
 #define BIOS_IN32(v) 	(readb(rinfo->bios_seg + (v)) | \
 			  (readb(rinfo->bios_seg + (v) + 1) << 8) | \
 			  (readb(rinfo->bios_seg + (v) + 2) << 16) | \
 			  (readb(rinfo->bios_seg + (v) + 3) << 24))
 /*
  * Inline utilities
  */
 static inline int round_div(int num, int den)
 {
         return (num + (den / 2)) / den;
 }
 static inline int var_to_depth(const struct fb_var_screeninfo *var)
 {
 	if (var->bits_per_pixel != 16)
 		return var->bits_per_pixel;
 	return (var->green.length == 5) ? 15 : 16;
 }
 static inline u32 radeon_get_dstbpp(u16 depth)
 {
 	switch (depth) {
        	case 8:
        		return DST_8BPP;
        	case 15:
        		return DST_15BPP;
        	case 16:
        		return DST_16BPP;
        	case 32:
        		return DST_32BPP;
        	default:
        		return 0;
 	}
 }
 /*
  * 2D Engine helper routines
  */
 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
 {
 	int i;
 	/* initiate flush */
 	OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
 	        ~RB2D_DC_FLUSH_ALL);
 	for (i=0; i < 2000000; i++) {
 		if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
 			return;
 		udelay(1);
 	}
 	printk(KERN_ERR "radeonfb: Flush Timeout !\n");
 }
 static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
 {
 	int i;
 	for (i=0; i<2000000; i++) {
 		if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
 			return;
 		udelay(1);
 	}
 	printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
 }
 static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
 {
 	int i;
 	/* ensure FIFO is empty before waiting for idle */
 	_radeon_fifo_wait (rinfo, 64);
 	for (i=0; i<2000000; i++) {
 		if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
 			radeon_engine_flush (rinfo);
 			return;
 		}
 		udelay(1);
 	}
 	printk(KERN_ERR "radeonfb: Idle Timeout !\n");
 }
 #define radeon_engine_idle()		_radeon_engine_idle(rinfo)
 #define radeon_fifo_wait(entries)	_radeon_fifo_wait(rinfo,entries)
 #define radeon_msleep(ms)		_radeon_msleep(rinfo,ms)
 /* I2C Functions */
 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
 /* PM Functions */
 extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
 extern int radeonfb_pci_resume(struct pci_dev *pdev);
 extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk);
 extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
 /* Monitor probe functions */
 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
 				 const char *monitor_layout, int ignore_edid);
 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
 extern int radeon_match_mode(struct radeonfb_info *rinfo,
 			     struct fb_var_screeninfo *dest,
 			     const struct fb_var_screeninfo *src);
 /* Accel functions */
 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
 extern int radeonfb_sync(struct fb_info *info);
 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
 /* Other functions */
 extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
 extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
 			       int reg_only);
 #endif /* __RADEONFB_H__ */