Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit e9c515589df7731591d15e506ba6d69713faae41

Authored by Rob Herring
1 parent 44430ec068
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

ARM: spear: use common irqchip_init function 

Convert spear DT irq initialization over to use common irqchip_init
function.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Rajeev Kumar <rajeev-dlh.kumar@st.com>

Showing 7 changed files with 13 additions and 33 deletions Inline Diff

arch/arm/mach-spear3xx/include/mach/generic.h
Diff comments   View file @ e9c5155
1 /* 1 /*
2 * arch/arm/mach-spear3xx/generic.h 2 * arch/arm/mach-spear3xx/generic.h
3 * 3 *
4 * SPEAr3XX machine family generic header file 4 * SPEAr3XX machine family generic header file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.linux@gmail.com> 7 * Viresh Kumar<viresh.linux@gmail.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14 #ifndef __MACH_GENERIC_H 14 #ifndef __MACH_GENERIC_H
15 #define __MACH_GENERIC_H 15 #define __MACH_GENERIC_H
16 16
17 #include <linux/amba/pl08x.h> 17 #include <linux/amba/pl08x.h>
18 #include <linux/init.h> 18 #include <linux/init.h>
19 #include <linux/platform_device.h> 19 #include <linux/platform_device.h>
20 #include <linux/amba/bus.h> 20 #include <linux/amba/bus.h>
21 #include <asm/mach/time.h> 21 #include <asm/mach/time.h>
22 #include <asm/mach/map.h> 22 #include <asm/mach/map.h>
23 23
24 /* Add spear3xx family device structure declarations here */ 24 /* Add spear3xx family device structure declarations here */
25 extern struct sys_timer spear3xx_timer; 25 extern struct sys_timer spear3xx_timer;
26 extern struct pl022_ssp_controller pl022_plat_data; 26 extern struct pl022_ssp_controller pl022_plat_data;
27 extern struct pl08x_platform_data pl080_plat_data; 27 extern struct pl08x_platform_data pl080_plat_data;
28 28
29 /* Add spear3xx family function declarations here */ 29 /* Add spear3xx family function declarations here */
30 void __init spear_setup_of_timer(void); 30 void __init spear_setup_of_timer(void);
31 void __init spear3xx_clk_init(void); 31 void __init spear3xx_clk_init(void);
32 void __init spear3xx_map_io(void); 32 void __init spear3xx_map_io(void);
33 void __init spear3xx_dt_init_irq(void);
34 33
35 void spear_restart(char, const char *); 34 void spear_restart(char, const char *);
36 35
37 #endif /* __MACH_GENERIC_H */ 36 #endif /* __MACH_GENERIC_H */
38 37
arch/arm/mach-spear3xx/spear300.c
Diff comments   View file @ e9c5155
1 /* 1 /*
2 * arch/arm/mach-spear3xx/spear300.c 2 * arch/arm/mach-spear3xx/spear300.c
3 * 3 *
4 * SPEAr300 machine source file 4 * SPEAr300 machine source file
5 * 5 *
6 * Copyright (C) 2009-2012 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com> 7 * Viresh Kumar <viresh.linux@gmail.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14 #define pr_fmt(fmt) "SPEAr300: " fmt 14 #define pr_fmt(fmt) "SPEAr300: " fmt
15 15
16 #include <linux/amba/pl08x.h> 16 #include <linux/amba/pl08x.h>
17 #include <linux/irqchip.h>
17 #include <linux/of_platform.h> 18 #include <linux/of_platform.h>
18 #include <asm/mach/arch.h> 19 #include <asm/mach/arch.h>
19 #include <mach/generic.h> 20 #include <mach/generic.h>
20 #include <mach/spear.h> 21 #include <mach/spear.h>
21 22
22 /* DMAC platform data's slave info */ 23 /* DMAC platform data's slave info */
23 struct pl08x_channel_data spear300_dma_info[] = { 24 struct pl08x_channel_data spear300_dma_info[] = {
24 { 25 {
25 .bus_id = "uart0_rx", 26 .bus_id = "uart0_rx",
26 .min_signal = 2, 27 .min_signal = 2,
27 .max_signal = 2, 28 .max_signal = 2,
28 .muxval = 0, 29 .muxval = 0,
29 .periph_buses = PL08X_AHB1, 30 .periph_buses = PL08X_AHB1,
30 }, { 31 }, {
31 .bus_id = "uart0_tx", 32 .bus_id = "uart0_tx",
32 .min_signal = 3, 33 .min_signal = 3,
33 .max_signal = 3, 34 .max_signal = 3,
34 .muxval = 0, 35 .muxval = 0,
35 .periph_buses = PL08X_AHB1, 36 .periph_buses = PL08X_AHB1,
36 }, { 37 }, {
37 .bus_id = "ssp0_rx", 38 .bus_id = "ssp0_rx",
38 .min_signal = 8, 39 .min_signal = 8,
39 .max_signal = 8, 40 .max_signal = 8,
40 .muxval = 0, 41 .muxval = 0,
41 .periph_buses = PL08X_AHB1, 42 .periph_buses = PL08X_AHB1,
42 }, { 43 }, {
43 .bus_id = "ssp0_tx", 44 .bus_id = "ssp0_tx",
44 .min_signal = 9, 45 .min_signal = 9,
45 .max_signal = 9, 46 .max_signal = 9,
46 .muxval = 0, 47 .muxval = 0,
47 .periph_buses = PL08X_AHB1, 48 .periph_buses = PL08X_AHB1,
48 }, { 49 }, {
49 .bus_id = "i2c_rx", 50 .bus_id = "i2c_rx",
50 .min_signal = 10, 51 .min_signal = 10,
51 .max_signal = 10, 52 .max_signal = 10,
52 .muxval = 0, 53 .muxval = 0,
53 .periph_buses = PL08X_AHB1, 54 .periph_buses = PL08X_AHB1,
54 }, { 55 }, {
55 .bus_id = "i2c_tx", 56 .bus_id = "i2c_tx",
56 .min_signal = 11, 57 .min_signal = 11,
57 .max_signal = 11, 58 .max_signal = 11,
58 .muxval = 0, 59 .muxval = 0,
59 .periph_buses = PL08X_AHB1, 60 .periph_buses = PL08X_AHB1,
60 }, { 61 }, {
61 .bus_id = "irda", 62 .bus_id = "irda",
62 .min_signal = 12, 63 .min_signal = 12,
63 .max_signal = 12, 64 .max_signal = 12,
64 .muxval = 0, 65 .muxval = 0,
65 .periph_buses = PL08X_AHB1, 66 .periph_buses = PL08X_AHB1,
66 }, { 67 }, {
67 .bus_id = "adc", 68 .bus_id = "adc",
68 .min_signal = 13, 69 .min_signal = 13,
69 .max_signal = 13, 70 .max_signal = 13,
70 .muxval = 0, 71 .muxval = 0,
71 .periph_buses = PL08X_AHB1, 72 .periph_buses = PL08X_AHB1,
72 }, { 73 }, {
73 .bus_id = "to_jpeg", 74 .bus_id = "to_jpeg",
74 .min_signal = 14, 75 .min_signal = 14,
75 .max_signal = 14, 76 .max_signal = 14,
76 .muxval = 0, 77 .muxval = 0,
77 .periph_buses = PL08X_AHB1, 78 .periph_buses = PL08X_AHB1,
78 }, { 79 }, {
79 .bus_id = "from_jpeg", 80 .bus_id = "from_jpeg",
80 .min_signal = 15, 81 .min_signal = 15,
81 .max_signal = 15, 82 .max_signal = 15,
82 .muxval = 0, 83 .muxval = 0,
83 .periph_buses = PL08X_AHB1, 84 .periph_buses = PL08X_AHB1,
84 }, { 85 }, {
85 .bus_id = "ras0_rx", 86 .bus_id = "ras0_rx",
86 .min_signal = 0, 87 .min_signal = 0,
87 .max_signal = 0, 88 .max_signal = 0,
88 .muxval = 1, 89 .muxval = 1,
89 .periph_buses = PL08X_AHB1, 90 .periph_buses = PL08X_AHB1,
90 }, { 91 }, {
91 .bus_id = "ras0_tx", 92 .bus_id = "ras0_tx",
92 .min_signal = 1, 93 .min_signal = 1,
93 .max_signal = 1, 94 .max_signal = 1,
94 .muxval = 1, 95 .muxval = 1,
95 .periph_buses = PL08X_AHB1, 96 .periph_buses = PL08X_AHB1,
96 }, { 97 }, {
97 .bus_id = "ras1_rx", 98 .bus_id = "ras1_rx",
98 .min_signal = 2, 99 .min_signal = 2,
99 .max_signal = 2, 100 .max_signal = 2,
100 .muxval = 1, 101 .muxval = 1,
101 .periph_buses = PL08X_AHB1, 102 .periph_buses = PL08X_AHB1,
102 }, { 103 }, {
103 .bus_id = "ras1_tx", 104 .bus_id = "ras1_tx",
104 .min_signal = 3, 105 .min_signal = 3,
105 .max_signal = 3, 106 .max_signal = 3,
106 .muxval = 1, 107 .muxval = 1,
107 .periph_buses = PL08X_AHB1, 108 .periph_buses = PL08X_AHB1,
108 }, { 109 }, {
109 .bus_id = "ras2_rx", 110 .bus_id = "ras2_rx",
110 .min_signal = 4, 111 .min_signal = 4,
111 .max_signal = 4, 112 .max_signal = 4,
112 .muxval = 1, 113 .muxval = 1,
113 .periph_buses = PL08X_AHB1, 114 .periph_buses = PL08X_AHB1,
114 }, { 115 }, {
115 .bus_id = "ras2_tx", 116 .bus_id = "ras2_tx",
116 .min_signal = 5, 117 .min_signal = 5,
117 .max_signal = 5, 118 .max_signal = 5,
118 .muxval = 1, 119 .muxval = 1,
119 .periph_buses = PL08X_AHB1, 120 .periph_buses = PL08X_AHB1,
120 }, { 121 }, {
121 .bus_id = "ras3_rx", 122 .bus_id = "ras3_rx",
122 .min_signal = 6, 123 .min_signal = 6,
123 .max_signal = 6, 124 .max_signal = 6,
124 .muxval = 1, 125 .muxval = 1,
125 .periph_buses = PL08X_AHB1, 126 .periph_buses = PL08X_AHB1,
126 }, { 127 }, {
127 .bus_id = "ras3_tx", 128 .bus_id = "ras3_tx",
128 .min_signal = 7, 129 .min_signal = 7,
129 .max_signal = 7, 130 .max_signal = 7,
130 .muxval = 1, 131 .muxval = 1,
131 .periph_buses = PL08X_AHB1, 132 .periph_buses = PL08X_AHB1,
132 }, { 133 }, {
133 .bus_id = "ras4_rx", 134 .bus_id = "ras4_rx",
134 .min_signal = 8, 135 .min_signal = 8,
135 .max_signal = 8, 136 .max_signal = 8,
136 .muxval = 1, 137 .muxval = 1,
137 .periph_buses = PL08X_AHB1, 138 .periph_buses = PL08X_AHB1,
138 }, { 139 }, {
139 .bus_id = "ras4_tx", 140 .bus_id = "ras4_tx",
140 .min_signal = 9, 141 .min_signal = 9,
141 .max_signal = 9, 142 .max_signal = 9,
142 .muxval = 1, 143 .muxval = 1,
143 .periph_buses = PL08X_AHB1, 144 .periph_buses = PL08X_AHB1,
144 }, { 145 }, {
145 .bus_id = "ras5_rx", 146 .bus_id = "ras5_rx",
146 .min_signal = 10, 147 .min_signal = 10,
147 .max_signal = 10, 148 .max_signal = 10,
148 .muxval = 1, 149 .muxval = 1,
149 .periph_buses = PL08X_AHB1, 150 .periph_buses = PL08X_AHB1,
150 }, { 151 }, {
151 .bus_id = "ras5_tx", 152 .bus_id = "ras5_tx",
152 .min_signal = 11, 153 .min_signal = 11,
153 .max_signal = 11, 154 .max_signal = 11,
154 .muxval = 1, 155 .muxval = 1,
155 .periph_buses = PL08X_AHB1, 156 .periph_buses = PL08X_AHB1,
156 }, { 157 }, {
157 .bus_id = "ras6_rx", 158 .bus_id = "ras6_rx",
158 .min_signal = 12, 159 .min_signal = 12,
159 .max_signal = 12, 160 .max_signal = 12,
160 .muxval = 1, 161 .muxval = 1,
161 .periph_buses = PL08X_AHB1, 162 .periph_buses = PL08X_AHB1,
162 }, { 163 }, {
163 .bus_id = "ras6_tx", 164 .bus_id = "ras6_tx",
164 .min_signal = 13, 165 .min_signal = 13,
165 .max_signal = 13, 166 .max_signal = 13,
166 .muxval = 1, 167 .muxval = 1,
167 .periph_buses = PL08X_AHB1, 168 .periph_buses = PL08X_AHB1,
168 }, { 169 }, {
169 .bus_id = "ras7_rx", 170 .bus_id = "ras7_rx",
170 .min_signal = 14, 171 .min_signal = 14,
171 .max_signal = 14, 172 .max_signal = 14,
172 .muxval = 1, 173 .muxval = 1,
173 .periph_buses = PL08X_AHB1, 174 .periph_buses = PL08X_AHB1,
174 }, { 175 }, {
175 .bus_id = "ras7_tx", 176 .bus_id = "ras7_tx",
176 .min_signal = 15, 177 .min_signal = 15,
177 .max_signal = 15, 178 .max_signal = 15,
178 .muxval = 1, 179 .muxval = 1,
179 .periph_buses = PL08X_AHB1, 180 .periph_buses = PL08X_AHB1,
180 }, 181 },
181 }; 182 };
182 183
183 /* Add SPEAr300 auxdata to pass platform data */ 184 /* Add SPEAr300 auxdata to pass platform data */
184 static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = { 185 static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
185 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, 186 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
186 &pl022_plat_data), 187 &pl022_plat_data),
187 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, 188 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
188 &pl080_plat_data), 189 &pl080_plat_data),
189 {} 190 {}
190 }; 191 };
191 192
192 static void __init spear300_dt_init(void) 193 static void __init spear300_dt_init(void)
193 { 194 {
194 pl080_plat_data.slave_channels = spear300_dma_info; 195 pl080_plat_data.slave_channels = spear300_dma_info;
195 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); 196 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
196 197
197 of_platform_populate(NULL, of_default_bus_match_table, 198 of_platform_populate(NULL, of_default_bus_match_table,
198 spear300_auxdata_lookup, NULL); 199 spear300_auxdata_lookup, NULL);
199 } 200 }
200 201
201 static const char * const spear300_dt_board_compat[] = { 202 static const char * const spear300_dt_board_compat[] = {
202 "st,spear300", 203 "st,spear300",
203 "st,spear300-evb", 204 "st,spear300-evb",
204 NULL, 205 NULL,
205 }; 206 };
206 207
207 static void __init spear300_map_io(void) 208 static void __init spear300_map_io(void)
208 { 209 {
209 spear3xx_map_io(); 210 spear3xx_map_io();
210 } 211 }
211 212
212 DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") 213 DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
213 .map_io = spear300_map_io, 214 .map_io = spear300_map_io,
214 .init_irq = spear3xx_dt_init_irq, 215 .init_irq = irqchip_init,
215 .timer = &spear3xx_timer, 216 .timer = &spear3xx_timer,
216 .init_machine = spear300_dt_init, 217 .init_machine = spear300_dt_init,
217 .restart = spear_restart, 218 .restart = spear_restart,
218 .dt_compat = spear300_dt_board_compat, 219 .dt_compat = spear300_dt_board_compat,
219 MACHINE_END 220 MACHINE_END
220 221
arch/arm/mach-spear3xx/spear310.c
Diff comments   View file @ e9c5155
1 /* 1 /*
2 * arch/arm/mach-spear3xx/spear310.c 2 * arch/arm/mach-spear3xx/spear310.c
3 * 3 *
4 * SPEAr310 machine source file 4 * SPEAr310 machine source file
5 * 5 *
6 * Copyright (C) 2009-2012 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com> 7 * Viresh Kumar <viresh.linux@gmail.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14 #define pr_fmt(fmt) "SPEAr310: " fmt 14 #define pr_fmt(fmt) "SPEAr310: " fmt
15 15
16 #include <linux/amba/pl08x.h> 16 #include <linux/amba/pl08x.h>
17 #include <linux/amba/serial.h> 17 #include <linux/amba/serial.h>
18 #include <linux/irqchip.h>
18 #include <linux/of_platform.h> 19 #include <linux/of_platform.h>
19 #include <asm/mach/arch.h> 20 #include <asm/mach/arch.h>
20 #include <mach/generic.h> 21 #include <mach/generic.h>
21 #include <mach/spear.h> 22 #include <mach/spear.h>
22 23
23 #define SPEAR310_UART1_BASE UL(0xB2000000) 24 #define SPEAR310_UART1_BASE UL(0xB2000000)
24 #define SPEAR310_UART2_BASE UL(0xB2080000) 25 #define SPEAR310_UART2_BASE UL(0xB2080000)
25 #define SPEAR310_UART3_BASE UL(0xB2100000) 26 #define SPEAR310_UART3_BASE UL(0xB2100000)
26 #define SPEAR310_UART4_BASE UL(0xB2180000) 27 #define SPEAR310_UART4_BASE UL(0xB2180000)
27 #define SPEAR310_UART5_BASE UL(0xB2200000) 28 #define SPEAR310_UART5_BASE UL(0xB2200000)
28 29
29 /* DMAC platform data's slave info */ 30 /* DMAC platform data's slave info */
30 struct pl08x_channel_data spear310_dma_info[] = { 31 struct pl08x_channel_data spear310_dma_info[] = {
31 { 32 {
32 .bus_id = "uart0_rx", 33 .bus_id = "uart0_rx",
33 .min_signal = 2, 34 .min_signal = 2,
34 .max_signal = 2, 35 .max_signal = 2,
35 .muxval = 0, 36 .muxval = 0,
36 .periph_buses = PL08X_AHB1, 37 .periph_buses = PL08X_AHB1,
37 }, { 38 }, {
38 .bus_id = "uart0_tx", 39 .bus_id = "uart0_tx",
39 .min_signal = 3, 40 .min_signal = 3,
40 .max_signal = 3, 41 .max_signal = 3,
41 .muxval = 0, 42 .muxval = 0,
42 .periph_buses = PL08X_AHB1, 43 .periph_buses = PL08X_AHB1,
43 }, { 44 }, {
44 .bus_id = "ssp0_rx", 45 .bus_id = "ssp0_rx",
45 .min_signal = 8, 46 .min_signal = 8,
46 .max_signal = 8, 47 .max_signal = 8,
47 .muxval = 0, 48 .muxval = 0,
48 .periph_buses = PL08X_AHB1, 49 .periph_buses = PL08X_AHB1,
49 }, { 50 }, {
50 .bus_id = "ssp0_tx", 51 .bus_id = "ssp0_tx",
51 .min_signal = 9, 52 .min_signal = 9,
52 .max_signal = 9, 53 .max_signal = 9,
53 .muxval = 0, 54 .muxval = 0,
54 .periph_buses = PL08X_AHB1, 55 .periph_buses = PL08X_AHB1,
55 }, { 56 }, {
56 .bus_id = "i2c_rx", 57 .bus_id = "i2c_rx",
57 .min_signal = 10, 58 .min_signal = 10,
58 .max_signal = 10, 59 .max_signal = 10,
59 .muxval = 0, 60 .muxval = 0,
60 .periph_buses = PL08X_AHB1, 61 .periph_buses = PL08X_AHB1,
61 }, { 62 }, {
62 .bus_id = "i2c_tx", 63 .bus_id = "i2c_tx",
63 .min_signal = 11, 64 .min_signal = 11,
64 .max_signal = 11, 65 .max_signal = 11,
65 .muxval = 0, 66 .muxval = 0,
66 .periph_buses = PL08X_AHB1, 67 .periph_buses = PL08X_AHB1,
67 }, { 68 }, {
68 .bus_id = "irda", 69 .bus_id = "irda",
69 .min_signal = 12, 70 .min_signal = 12,
70 .max_signal = 12, 71 .max_signal = 12,
71 .muxval = 0, 72 .muxval = 0,
72 .periph_buses = PL08X_AHB1, 73 .periph_buses = PL08X_AHB1,
73 }, { 74 }, {
74 .bus_id = "adc", 75 .bus_id = "adc",
75 .min_signal = 13, 76 .min_signal = 13,
76 .max_signal = 13, 77 .max_signal = 13,
77 .muxval = 0, 78 .muxval = 0,
78 .periph_buses = PL08X_AHB1, 79 .periph_buses = PL08X_AHB1,
79 }, { 80 }, {
80 .bus_id = "to_jpeg", 81 .bus_id = "to_jpeg",
81 .min_signal = 14, 82 .min_signal = 14,
82 .max_signal = 14, 83 .max_signal = 14,
83 .muxval = 0, 84 .muxval = 0,
84 .periph_buses = PL08X_AHB1, 85 .periph_buses = PL08X_AHB1,
85 }, { 86 }, {
86 .bus_id = "from_jpeg", 87 .bus_id = "from_jpeg",
87 .min_signal = 15, 88 .min_signal = 15,
88 .max_signal = 15, 89 .max_signal = 15,
89 .muxval = 0, 90 .muxval = 0,
90 .periph_buses = PL08X_AHB1, 91 .periph_buses = PL08X_AHB1,
91 }, { 92 }, {
92 .bus_id = "uart1_rx", 93 .bus_id = "uart1_rx",
93 .min_signal = 0, 94 .min_signal = 0,
94 .max_signal = 0, 95 .max_signal = 0,
95 .muxval = 1, 96 .muxval = 1,
96 .periph_buses = PL08X_AHB1, 97 .periph_buses = PL08X_AHB1,
97 }, { 98 }, {
98 .bus_id = "uart1_tx", 99 .bus_id = "uart1_tx",
99 .min_signal = 1, 100 .min_signal = 1,
100 .max_signal = 1, 101 .max_signal = 1,
101 .muxval = 1, 102 .muxval = 1,
102 .periph_buses = PL08X_AHB1, 103 .periph_buses = PL08X_AHB1,
103 }, { 104 }, {
104 .bus_id = "uart2_rx", 105 .bus_id = "uart2_rx",
105 .min_signal = 2, 106 .min_signal = 2,
106 .max_signal = 2, 107 .max_signal = 2,
107 .muxval = 1, 108 .muxval = 1,
108 .periph_buses = PL08X_AHB1, 109 .periph_buses = PL08X_AHB1,
109 }, { 110 }, {
110 .bus_id = "uart2_tx", 111 .bus_id = "uart2_tx",
111 .min_signal = 3, 112 .min_signal = 3,
112 .max_signal = 3, 113 .max_signal = 3,
113 .muxval = 1, 114 .muxval = 1,
114 .periph_buses = PL08X_AHB1, 115 .periph_buses = PL08X_AHB1,
115 }, { 116 }, {
116 .bus_id = "uart3_rx", 117 .bus_id = "uart3_rx",
117 .min_signal = 4, 118 .min_signal = 4,
118 .max_signal = 4, 119 .max_signal = 4,
119 .muxval = 1, 120 .muxval = 1,
120 .periph_buses = PL08X_AHB1, 121 .periph_buses = PL08X_AHB1,
121 }, { 122 }, {
122 .bus_id = "uart3_tx", 123 .bus_id = "uart3_tx",
123 .min_signal = 5, 124 .min_signal = 5,
124 .max_signal = 5, 125 .max_signal = 5,
125 .muxval = 1, 126 .muxval = 1,
126 .periph_buses = PL08X_AHB1, 127 .periph_buses = PL08X_AHB1,
127 }, { 128 }, {
128 .bus_id = "uart4_rx", 129 .bus_id = "uart4_rx",
129 .min_signal = 6, 130 .min_signal = 6,
130 .max_signal = 6, 131 .max_signal = 6,
131 .muxval = 1, 132 .muxval = 1,
132 .periph_buses = PL08X_AHB1, 133 .periph_buses = PL08X_AHB1,
133 }, { 134 }, {
134 .bus_id = "uart4_tx", 135 .bus_id = "uart4_tx",
135 .min_signal = 7, 136 .min_signal = 7,
136 .max_signal = 7, 137 .max_signal = 7,
137 .muxval = 1, 138 .muxval = 1,
138 .periph_buses = PL08X_AHB1, 139 .periph_buses = PL08X_AHB1,
139 }, { 140 }, {
140 .bus_id = "uart5_rx", 141 .bus_id = "uart5_rx",
141 .min_signal = 8, 142 .min_signal = 8,
142 .max_signal = 8, 143 .max_signal = 8,
143 .muxval = 1, 144 .muxval = 1,
144 .periph_buses = PL08X_AHB1, 145 .periph_buses = PL08X_AHB1,
145 }, { 146 }, {
146 .bus_id = "uart5_tx", 147 .bus_id = "uart5_tx",
147 .min_signal = 9, 148 .min_signal = 9,
148 .max_signal = 9, 149 .max_signal = 9,
149 .muxval = 1, 150 .muxval = 1,
150 .periph_buses = PL08X_AHB1, 151 .periph_buses = PL08X_AHB1,
151 }, { 152 }, {
152 .bus_id = "ras5_rx", 153 .bus_id = "ras5_rx",
153 .min_signal = 10, 154 .min_signal = 10,
154 .max_signal = 10, 155 .max_signal = 10,
155 .muxval = 1, 156 .muxval = 1,
156 .periph_buses = PL08X_AHB1, 157 .periph_buses = PL08X_AHB1,
157 }, { 158 }, {
158 .bus_id = "ras5_tx", 159 .bus_id = "ras5_tx",
159 .min_signal = 11, 160 .min_signal = 11,
160 .max_signal = 11, 161 .max_signal = 11,
161 .muxval = 1, 162 .muxval = 1,
162 .periph_buses = PL08X_AHB1, 163 .periph_buses = PL08X_AHB1,
163 }, { 164 }, {
164 .bus_id = "ras6_rx", 165 .bus_id = "ras6_rx",
165 .min_signal = 12, 166 .min_signal = 12,
166 .max_signal = 12, 167 .max_signal = 12,
167 .muxval = 1, 168 .muxval = 1,
168 .periph_buses = PL08X_AHB1, 169 .periph_buses = PL08X_AHB1,
169 }, { 170 }, {
170 .bus_id = "ras6_tx", 171 .bus_id = "ras6_tx",
171 .min_signal = 13, 172 .min_signal = 13,
172 .max_signal = 13, 173 .max_signal = 13,
173 .muxval = 1, 174 .muxval = 1,
174 .periph_buses = PL08X_AHB1, 175 .periph_buses = PL08X_AHB1,
175 }, { 176 }, {
176 .bus_id = "ras7_rx", 177 .bus_id = "ras7_rx",
177 .min_signal = 14, 178 .min_signal = 14,
178 .max_signal = 14, 179 .max_signal = 14,
179 .muxval = 1, 180 .muxval = 1,
180 .periph_buses = PL08X_AHB1, 181 .periph_buses = PL08X_AHB1,
181 }, { 182 }, {
182 .bus_id = "ras7_tx", 183 .bus_id = "ras7_tx",
183 .min_signal = 15, 184 .min_signal = 15,
184 .max_signal = 15, 185 .max_signal = 15,
185 .muxval = 1, 186 .muxval = 1,
186 .periph_buses = PL08X_AHB1, 187 .periph_buses = PL08X_AHB1,
187 }, 188 },
188 }; 189 };
189 190
190 /* uart devices plat data */ 191 /* uart devices plat data */
191 static struct amba_pl011_data spear310_uart_data[] = { 192 static struct amba_pl011_data spear310_uart_data[] = {
192 { 193 {
193 .dma_filter = pl08x_filter_id, 194 .dma_filter = pl08x_filter_id,
194 .dma_tx_param = "uart1_tx", 195 .dma_tx_param = "uart1_tx",
195 .dma_rx_param = "uart1_rx", 196 .dma_rx_param = "uart1_rx",
196 }, { 197 }, {
197 .dma_filter = pl08x_filter_id, 198 .dma_filter = pl08x_filter_id,
198 .dma_tx_param = "uart2_tx", 199 .dma_tx_param = "uart2_tx",
199 .dma_rx_param = "uart2_rx", 200 .dma_rx_param = "uart2_rx",
200 }, { 201 }, {
201 .dma_filter = pl08x_filter_id, 202 .dma_filter = pl08x_filter_id,
202 .dma_tx_param = "uart3_tx", 203 .dma_tx_param = "uart3_tx",
203 .dma_rx_param = "uart3_rx", 204 .dma_rx_param = "uart3_rx",
204 }, { 205 }, {
205 .dma_filter = pl08x_filter_id, 206 .dma_filter = pl08x_filter_id,
206 .dma_tx_param = "uart4_tx", 207 .dma_tx_param = "uart4_tx",
207 .dma_rx_param = "uart4_rx", 208 .dma_rx_param = "uart4_rx",
208 }, { 209 }, {
209 .dma_filter = pl08x_filter_id, 210 .dma_filter = pl08x_filter_id,
210 .dma_tx_param = "uart5_tx", 211 .dma_tx_param = "uart5_tx",
211 .dma_rx_param = "uart5_rx", 212 .dma_rx_param = "uart5_rx",
212 }, 213 },
213 }; 214 };
214 215
215 /* Add SPEAr310 auxdata to pass platform data */ 216 /* Add SPEAr310 auxdata to pass platform data */
216 static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { 217 static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
217 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, 218 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
218 &pl022_plat_data), 219 &pl022_plat_data),
219 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, 220 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
220 &pl080_plat_data), 221 &pl080_plat_data),
221 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, 222 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
222 &spear310_uart_data[0]), 223 &spear310_uart_data[0]),
223 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL, 224 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
224 &spear310_uart_data[1]), 225 &spear310_uart_data[1]),
225 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL, 226 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
226 &spear310_uart_data[2]), 227 &spear310_uart_data[2]),
227 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL, 228 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
228 &spear310_uart_data[3]), 229 &spear310_uart_data[3]),
229 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL, 230 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
230 &spear310_uart_data[4]), 231 &spear310_uart_data[4]),
231 {} 232 {}
232 }; 233 };
233 234
234 static void __init spear310_dt_init(void) 235 static void __init spear310_dt_init(void)
235 { 236 {
236 pl080_plat_data.slave_channels = spear310_dma_info; 237 pl080_plat_data.slave_channels = spear310_dma_info;
237 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); 238 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
238 239
239 of_platform_populate(NULL, of_default_bus_match_table, 240 of_platform_populate(NULL, of_default_bus_match_table,
240 spear310_auxdata_lookup, NULL); 241 spear310_auxdata_lookup, NULL);
241 } 242 }
242 243
243 static const char * const spear310_dt_board_compat[] = { 244 static const char * const spear310_dt_board_compat[] = {
244 "st,spear310", 245 "st,spear310",
245 "st,spear310-evb", 246 "st,spear310-evb",
246 NULL, 247 NULL,
247 }; 248 };
248 249
249 static void __init spear310_map_io(void) 250 static void __init spear310_map_io(void)
250 { 251 {
251 spear3xx_map_io(); 252 spear3xx_map_io();
252 } 253 }
253 254
254 DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") 255 DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
255 .map_io = spear310_map_io, 256 .map_io = spear310_map_io,
256 .init_irq = spear3xx_dt_init_irq, 257 .init_irq = irqchip_init,
257 .timer = &spear3xx_timer, 258 .timer = &spear3xx_timer,
258 .init_machine = spear310_dt_init, 259 .init_machine = spear310_dt_init,
259 .restart = spear_restart, 260 .restart = spear_restart,
260 .dt_compat = spear310_dt_board_compat, 261 .dt_compat = spear310_dt_board_compat,
261 MACHINE_END 262 MACHINE_END
262 263
arch/arm/mach-spear3xx/spear320.c
Diff comments   View file @ e9c5155
1 /* 1 /*
2 * arch/arm/mach-spear3xx/spear320.c 2 * arch/arm/mach-spear3xx/spear320.c
3 * 3 *
4 * SPEAr320 machine source file 4 * SPEAr320 machine source file
5 * 5 *
6 * Copyright (C) 2009-2012 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com> 7 * Viresh Kumar <viresh.linux@gmail.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14 #define pr_fmt(fmt) "SPEAr320: " fmt 14 #define pr_fmt(fmt) "SPEAr320: " fmt
15 15
16 #include <linux/amba/pl022.h> 16 #include <linux/amba/pl022.h>
17 #include <linux/amba/pl08x.h> 17 #include <linux/amba/pl08x.h>
18 #include <linux/amba/serial.h> 18 #include <linux/amba/serial.h>
19 #include <linux/irqchip.h>
19 #include <linux/of_platform.h> 20 #include <linux/of_platform.h>
20 #include <asm/mach/arch.h> 21 #include <asm/mach/arch.h>
21 #include <mach/generic.h> 22 #include <mach/generic.h>
22 #include <mach/spear.h> 23 #include <mach/spear.h>
23 24
24 #define SPEAR320_UART1_BASE UL(0xA3000000) 25 #define SPEAR320_UART1_BASE UL(0xA3000000)
25 #define SPEAR320_UART2_BASE UL(0xA4000000) 26 #define SPEAR320_UART2_BASE UL(0xA4000000)
26 #define SPEAR320_SSP0_BASE UL(0xA5000000) 27 #define SPEAR320_SSP0_BASE UL(0xA5000000)
27 #define SPEAR320_SSP1_BASE UL(0xA6000000) 28 #define SPEAR320_SSP1_BASE UL(0xA6000000)
28 29
29 /* DMAC platform data's slave info */ 30 /* DMAC platform data's slave info */
30 struct pl08x_channel_data spear320_dma_info[] = { 31 struct pl08x_channel_data spear320_dma_info[] = {
31 { 32 {
32 .bus_id = "uart0_rx", 33 .bus_id = "uart0_rx",
33 .min_signal = 2, 34 .min_signal = 2,
34 .max_signal = 2, 35 .max_signal = 2,
35 .muxval = 0, 36 .muxval = 0,
36 .periph_buses = PL08X_AHB1, 37 .periph_buses = PL08X_AHB1,
37 }, { 38 }, {
38 .bus_id = "uart0_tx", 39 .bus_id = "uart0_tx",
39 .min_signal = 3, 40 .min_signal = 3,
40 .max_signal = 3, 41 .max_signal = 3,
41 .muxval = 0, 42 .muxval = 0,
42 .periph_buses = PL08X_AHB1, 43 .periph_buses = PL08X_AHB1,
43 }, { 44 }, {
44 .bus_id = "ssp0_rx", 45 .bus_id = "ssp0_rx",
45 .min_signal = 8, 46 .min_signal = 8,
46 .max_signal = 8, 47 .max_signal = 8,
47 .muxval = 0, 48 .muxval = 0,
48 .periph_buses = PL08X_AHB1, 49 .periph_buses = PL08X_AHB1,
49 }, { 50 }, {
50 .bus_id = "ssp0_tx", 51 .bus_id = "ssp0_tx",
51 .min_signal = 9, 52 .min_signal = 9,
52 .max_signal = 9, 53 .max_signal = 9,
53 .muxval = 0, 54 .muxval = 0,
54 .periph_buses = PL08X_AHB1, 55 .periph_buses = PL08X_AHB1,
55 }, { 56 }, {
56 .bus_id = "i2c0_rx", 57 .bus_id = "i2c0_rx",
57 .min_signal = 10, 58 .min_signal = 10,
58 .max_signal = 10, 59 .max_signal = 10,
59 .muxval = 0, 60 .muxval = 0,
60 .periph_buses = PL08X_AHB1, 61 .periph_buses = PL08X_AHB1,
61 }, { 62 }, {
62 .bus_id = "i2c0_tx", 63 .bus_id = "i2c0_tx",
63 .min_signal = 11, 64 .min_signal = 11,
64 .max_signal = 11, 65 .max_signal = 11,
65 .muxval = 0, 66 .muxval = 0,
66 .periph_buses = PL08X_AHB1, 67 .periph_buses = PL08X_AHB1,
67 }, { 68 }, {
68 .bus_id = "irda", 69 .bus_id = "irda",
69 .min_signal = 12, 70 .min_signal = 12,
70 .max_signal = 12, 71 .max_signal = 12,
71 .muxval = 0, 72 .muxval = 0,
72 .periph_buses = PL08X_AHB1, 73 .periph_buses = PL08X_AHB1,
73 }, { 74 }, {
74 .bus_id = "adc", 75 .bus_id = "adc",
75 .min_signal = 13, 76 .min_signal = 13,
76 .max_signal = 13, 77 .max_signal = 13,
77 .muxval = 0, 78 .muxval = 0,
78 .periph_buses = PL08X_AHB1, 79 .periph_buses = PL08X_AHB1,
79 }, { 80 }, {
80 .bus_id = "to_jpeg", 81 .bus_id = "to_jpeg",
81 .min_signal = 14, 82 .min_signal = 14,
82 .max_signal = 14, 83 .max_signal = 14,
83 .muxval = 0, 84 .muxval = 0,
84 .periph_buses = PL08X_AHB1, 85 .periph_buses = PL08X_AHB1,
85 }, { 86 }, {
86 .bus_id = "from_jpeg", 87 .bus_id = "from_jpeg",
87 .min_signal = 15, 88 .min_signal = 15,
88 .max_signal = 15, 89 .max_signal = 15,
89 .muxval = 0, 90 .muxval = 0,
90 .periph_buses = PL08X_AHB1, 91 .periph_buses = PL08X_AHB1,
91 }, { 92 }, {
92 .bus_id = "ssp1_rx", 93 .bus_id = "ssp1_rx",
93 .min_signal = 0, 94 .min_signal = 0,
94 .max_signal = 0, 95 .max_signal = 0,
95 .muxval = 1, 96 .muxval = 1,
96 .periph_buses = PL08X_AHB2, 97 .periph_buses = PL08X_AHB2,
97 }, { 98 }, {
98 .bus_id = "ssp1_tx", 99 .bus_id = "ssp1_tx",
99 .min_signal = 1, 100 .min_signal = 1,
100 .max_signal = 1, 101 .max_signal = 1,
101 .muxval = 1, 102 .muxval = 1,
102 .periph_buses = PL08X_AHB2, 103 .periph_buses = PL08X_AHB2,
103 }, { 104 }, {
104 .bus_id = "ssp2_rx", 105 .bus_id = "ssp2_rx",
105 .min_signal = 2, 106 .min_signal = 2,
106 .max_signal = 2, 107 .max_signal = 2,
107 .muxval = 1, 108 .muxval = 1,
108 .periph_buses = PL08X_AHB2, 109 .periph_buses = PL08X_AHB2,
109 }, { 110 }, {
110 .bus_id = "ssp2_tx", 111 .bus_id = "ssp2_tx",
111 .min_signal = 3, 112 .min_signal = 3,
112 .max_signal = 3, 113 .max_signal = 3,
113 .muxval = 1, 114 .muxval = 1,
114 .periph_buses = PL08X_AHB2, 115 .periph_buses = PL08X_AHB2,
115 }, { 116 }, {
116 .bus_id = "uart1_rx", 117 .bus_id = "uart1_rx",
117 .min_signal = 4, 118 .min_signal = 4,
118 .max_signal = 4, 119 .max_signal = 4,
119 .muxval = 1, 120 .muxval = 1,
120 .periph_buses = PL08X_AHB2, 121 .periph_buses = PL08X_AHB2,
121 }, { 122 }, {
122 .bus_id = "uart1_tx", 123 .bus_id = "uart1_tx",
123 .min_signal = 5, 124 .min_signal = 5,
124 .max_signal = 5, 125 .max_signal = 5,
125 .muxval = 1, 126 .muxval = 1,
126 .periph_buses = PL08X_AHB2, 127 .periph_buses = PL08X_AHB2,
127 }, { 128 }, {
128 .bus_id = "uart2_rx", 129 .bus_id = "uart2_rx",
129 .min_signal = 6, 130 .min_signal = 6,
130 .max_signal = 6, 131 .max_signal = 6,
131 .muxval = 1, 132 .muxval = 1,
132 .periph_buses = PL08X_AHB2, 133 .periph_buses = PL08X_AHB2,
133 }, { 134 }, {
134 .bus_id = "uart2_tx", 135 .bus_id = "uart2_tx",
135 .min_signal = 7, 136 .min_signal = 7,
136 .max_signal = 7, 137 .max_signal = 7,
137 .muxval = 1, 138 .muxval = 1,
138 .periph_buses = PL08X_AHB2, 139 .periph_buses = PL08X_AHB2,
139 }, { 140 }, {
140 .bus_id = "i2c1_rx", 141 .bus_id = "i2c1_rx",
141 .min_signal = 8, 142 .min_signal = 8,
142 .max_signal = 8, 143 .max_signal = 8,
143 .muxval = 1, 144 .muxval = 1,
144 .periph_buses = PL08X_AHB2, 145 .periph_buses = PL08X_AHB2,
145 }, { 146 }, {
146 .bus_id = "i2c1_tx", 147 .bus_id = "i2c1_tx",
147 .min_signal = 9, 148 .min_signal = 9,
148 .max_signal = 9, 149 .max_signal = 9,
149 .muxval = 1, 150 .muxval = 1,
150 .periph_buses = PL08X_AHB2, 151 .periph_buses = PL08X_AHB2,
151 }, { 152 }, {
152 .bus_id = "i2c2_rx", 153 .bus_id = "i2c2_rx",
153 .min_signal = 10, 154 .min_signal = 10,
154 .max_signal = 10, 155 .max_signal = 10,
155 .muxval = 1, 156 .muxval = 1,
156 .periph_buses = PL08X_AHB2, 157 .periph_buses = PL08X_AHB2,
157 }, { 158 }, {
158 .bus_id = "i2c2_tx", 159 .bus_id = "i2c2_tx",
159 .min_signal = 11, 160 .min_signal = 11,
160 .max_signal = 11, 161 .max_signal = 11,
161 .muxval = 1, 162 .muxval = 1,
162 .periph_buses = PL08X_AHB2, 163 .periph_buses = PL08X_AHB2,
163 }, { 164 }, {
164 .bus_id = "i2s_rx", 165 .bus_id = "i2s_rx",
165 .min_signal = 12, 166 .min_signal = 12,
166 .max_signal = 12, 167 .max_signal = 12,
167 .muxval = 1, 168 .muxval = 1,
168 .periph_buses = PL08X_AHB2, 169 .periph_buses = PL08X_AHB2,
169 }, { 170 }, {
170 .bus_id = "i2s_tx", 171 .bus_id = "i2s_tx",
171 .min_signal = 13, 172 .min_signal = 13,
172 .max_signal = 13, 173 .max_signal = 13,
173 .muxval = 1, 174 .muxval = 1,
174 .periph_buses = PL08X_AHB2, 175 .periph_buses = PL08X_AHB2,
175 }, { 176 }, {
176 .bus_id = "rs485_rx", 177 .bus_id = "rs485_rx",
177 .min_signal = 14, 178 .min_signal = 14,
178 .max_signal = 14, 179 .max_signal = 14,
179 .muxval = 1, 180 .muxval = 1,
180 .periph_buses = PL08X_AHB2, 181 .periph_buses = PL08X_AHB2,
181 }, { 182 }, {
182 .bus_id = "rs485_tx", 183 .bus_id = "rs485_tx",
183 .min_signal = 15, 184 .min_signal = 15,
184 .max_signal = 15, 185 .max_signal = 15,
185 .muxval = 1, 186 .muxval = 1,
186 .periph_buses = PL08X_AHB2, 187 .periph_buses = PL08X_AHB2,
187 }, 188 },
188 }; 189 };
189 190
190 static struct pl022_ssp_controller spear320_ssp_data[] = { 191 static struct pl022_ssp_controller spear320_ssp_data[] = {
191 { 192 {
192 .bus_id = 1, 193 .bus_id = 1,
193 .enable_dma = 1, 194 .enable_dma = 1,
194 .dma_filter = pl08x_filter_id, 195 .dma_filter = pl08x_filter_id,
195 .dma_tx_param = "ssp1_tx", 196 .dma_tx_param = "ssp1_tx",
196 .dma_rx_param = "ssp1_rx", 197 .dma_rx_param = "ssp1_rx",
197 .num_chipselect = 2, 198 .num_chipselect = 2,
198 }, { 199 }, {
199 .bus_id = 2, 200 .bus_id = 2,
200 .enable_dma = 1, 201 .enable_dma = 1,
201 .dma_filter = pl08x_filter_id, 202 .dma_filter = pl08x_filter_id,
202 .dma_tx_param = "ssp2_tx", 203 .dma_tx_param = "ssp2_tx",
203 .dma_rx_param = "ssp2_rx", 204 .dma_rx_param = "ssp2_rx",
204 .num_chipselect = 2, 205 .num_chipselect = 2,
205 } 206 }
206 }; 207 };
207 208
208 static struct amba_pl011_data spear320_uart_data[] = { 209 static struct amba_pl011_data spear320_uart_data[] = {
209 { 210 {
210 .dma_filter = pl08x_filter_id, 211 .dma_filter = pl08x_filter_id,
211 .dma_tx_param = "uart1_tx", 212 .dma_tx_param = "uart1_tx",
212 .dma_rx_param = "uart1_rx", 213 .dma_rx_param = "uart1_rx",
213 }, { 214 }, {
214 .dma_filter = pl08x_filter_id, 215 .dma_filter = pl08x_filter_id,
215 .dma_tx_param = "uart2_tx", 216 .dma_tx_param = "uart2_tx",
216 .dma_rx_param = "uart2_rx", 217 .dma_rx_param = "uart2_rx",
217 }, 218 },
218 }; 219 };
219 220
220 /* Add SPEAr310 auxdata to pass platform data */ 221 /* Add SPEAr310 auxdata to pass platform data */
221 static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { 222 static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
222 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, 223 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
223 &pl022_plat_data), 224 &pl022_plat_data),
224 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, 225 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
225 &pl080_plat_data), 226 &pl080_plat_data),
226 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL, 227 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
227 &spear320_ssp_data[0]), 228 &spear320_ssp_data[0]),
228 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL, 229 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
229 &spear320_ssp_data[1]), 230 &spear320_ssp_data[1]),
230 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL, 231 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
231 &spear320_uart_data[0]), 232 &spear320_uart_data[0]),
232 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL, 233 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
233 &spear320_uart_data[1]), 234 &spear320_uart_data[1]),
234 {} 235 {}
235 }; 236 };
236 237
237 static void __init spear320_dt_init(void) 238 static void __init spear320_dt_init(void)
238 { 239 {
239 pl080_plat_data.slave_channels = spear320_dma_info; 240 pl080_plat_data.slave_channels = spear320_dma_info;
240 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); 241 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
241 242
242 of_platform_populate(NULL, of_default_bus_match_table, 243 of_platform_populate(NULL, of_default_bus_match_table,
243 spear320_auxdata_lookup, NULL); 244 spear320_auxdata_lookup, NULL);
244 } 245 }
245 246
246 static const char * const spear320_dt_board_compat[] = { 247 static const char * const spear320_dt_board_compat[] = {
247 "st,spear320", 248 "st,spear320",
248 "st,spear320-evb", 249 "st,spear320-evb",
249 "st,spear320-hmi", 250 "st,spear320-hmi",
250 NULL, 251 NULL,
251 }; 252 };
252 253
253 struct map_desc spear320_io_desc[] __initdata = { 254 struct map_desc spear320_io_desc[] __initdata = {
254 { 255 {
255 .virtual = VA_SPEAR320_SOC_CONFIG_BASE, 256 .virtual = VA_SPEAR320_SOC_CONFIG_BASE,
256 .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE), 257 .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
257 .length = SZ_16M, 258 .length = SZ_16M,
258 .type = MT_DEVICE 259 .type = MT_DEVICE
259 }, 260 },
260 }; 261 };
261 262
262 static void __init spear320_map_io(void) 263 static void __init spear320_map_io(void)
263 { 264 {
264 iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc)); 265 iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
265 spear3xx_map_io(); 266 spear3xx_map_io();
266 } 267 }
267 268
268 DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") 269 DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
269 .map_io = spear320_map_io, 270 .map_io = spear320_map_io,
270 .init_irq = spear3xx_dt_init_irq, 271 .init_irq = irqchip_init,
271 .timer = &spear3xx_timer, 272 .timer = &spear3xx_timer,
272 .init_machine = spear320_dt_init, 273 .init_machine = spear320_dt_init,
273 .restart = spear_restart, 274 .restart = spear_restart,
274 .dt_compat = spear320_dt_board_compat, 275 .dt_compat = spear320_dt_board_compat,
275 MACHINE_END 276 MACHINE_END
276 277
arch/arm/mach-spear3xx/spear3xx.c
Diff comments   View file @ e9c5155
1 /* 1 /*
2 * arch/arm/mach-spear3xx/spear3xx.c 2 * arch/arm/mach-spear3xx/spear3xx.c
3 * 3 *
4 * SPEAr3XX machines common source file 4 * SPEAr3XX machines common source file
5 * 5 *
6 * Copyright (C) 2009-2012 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com> 7 * Viresh Kumar <viresh.linux@gmail.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14 #define pr_fmt(fmt) "SPEAr3xx: " fmt 14 #define pr_fmt(fmt) "SPEAr3xx: " fmt
15 15
16 #include <linux/amba/pl022.h> 16 #include <linux/amba/pl022.h>
17 #include <linux/amba/pl08x.h> 17 #include <linux/amba/pl08x.h>
18 #include <linux/irqchip/spear-shirq.h>
19 #include <linux/of_irq.h>
20 #include <linux/io.h> 18 #include <linux/io.h>
21 #include <asm/hardware/pl080.h> 19 #include <asm/hardware/pl080.h>
22 #include <asm/hardware/vic.h>
23 #include <plat/pl080.h> 20 #include <plat/pl080.h>
24 #include <mach/generic.h> 21 #include <mach/generic.h>
25 #include <mach/spear.h> 22 #include <mach/spear.h>
26 23
27 /* ssp device registration */ 24 /* ssp device registration */
28 struct pl022_ssp_controller pl022_plat_data = { 25 struct pl022_ssp_controller pl022_plat_data = {
29 .bus_id = 0, 26 .bus_id = 0,
30 .enable_dma = 1, 27 .enable_dma = 1,
31 .dma_filter = pl08x_filter_id, 28 .dma_filter = pl08x_filter_id,
32 .dma_tx_param = "ssp0_tx", 29 .dma_tx_param = "ssp0_tx",
33 .dma_rx_param = "ssp0_rx", 30 .dma_rx_param = "ssp0_rx",
34 /* 31 /*
35 * This is number of spi devices that can be connected to spi. There are 32 * This is number of spi devices that can be connected to spi. There are
36 * two type of chipselects on which slave devices can work. One is chip 33 * two type of chipselects on which slave devices can work. One is chip
37 * select provided by spi masters other is controlled through external 34 * select provided by spi masters other is controlled through external
38 * gpio's. We can't use chipselect provided from spi master (because as 35 * gpio's. We can't use chipselect provided from spi master (because as
39 * soon as FIFO becomes empty, CS is disabled and transfer ends). So 36 * soon as FIFO becomes empty, CS is disabled and transfer ends). So
40 * this number now depends on number of gpios available for spi. each 37 * this number now depends on number of gpios available for spi. each
41 * slave on each master requires a separate gpio pin. 38 * slave on each master requires a separate gpio pin.
42 */ 39 */
43 .num_chipselect = 2, 40 .num_chipselect = 2,
44 }; 41 };
45 42
46 /* dmac device registration */ 43 /* dmac device registration */
47 struct pl08x_platform_data pl080_plat_data = { 44 struct pl08x_platform_data pl080_plat_data = {
48 .memcpy_channel = { 45 .memcpy_channel = {
49 .bus_id = "memcpy", 46 .bus_id = "memcpy",
50 .cctl_memcpy = 47 .cctl_memcpy =
51 (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ 48 (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
52 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ 49 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
53 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ 50 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
54 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ 51 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
55 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ 52 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
56 PL080_CONTROL_PROT_SYS), 53 PL080_CONTROL_PROT_SYS),
57 }, 54 },
58 .lli_buses = PL08X_AHB1, 55 .lli_buses = PL08X_AHB1,
59 .mem_buses = PL08X_AHB1, 56 .mem_buses = PL08X_AHB1,
60 .get_signal = pl080_get_signal, 57 .get_signal = pl080_get_signal,
61 .put_signal = pl080_put_signal, 58 .put_signal = pl080_put_signal,
62 }; 59 };
63 60
64 /* 61 /*
65 * Following will create 16MB static virtual/physical mappings 62 * Following will create 16MB static virtual/physical mappings
66 * PHYSICAL VIRTUAL 63 * PHYSICAL VIRTUAL
67 * 0xD0000000 0xFD000000 64 * 0xD0000000 0xFD000000
68 * 0xFC000000 0xFC000000 65 * 0xFC000000 0xFC000000
69 */ 66 */
70 struct map_desc spear3xx_io_desc[] __initdata = { 67 struct map_desc spear3xx_io_desc[] __initdata = {
71 { 68 {
72 .virtual = VA_SPEAR3XX_ICM1_2_BASE, 69 .virtual = VA_SPEAR3XX_ICM1_2_BASE,
73 .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE), 70 .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
74 .length = SZ_16M, 71 .length = SZ_16M,
75 .type = MT_DEVICE 72 .type = MT_DEVICE
76 }, { 73 }, {
77 .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE, 74 .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
78 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE), 75 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
79 .length = SZ_16M, 76 .length = SZ_16M,
80 .type = MT_DEVICE 77 .type = MT_DEVICE
81 }, 78 },
82 }; 79 };
83 80
84 /* This will create static memory mapping for selected devices */ 81 /* This will create static memory mapping for selected devices */
85 void __init spear3xx_map_io(void) 82 void __init spear3xx_map_io(void)
86 { 83 {
87 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); 84 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
88 } 85 }
89 86
90 static void __init spear3xx_timer_init(void) 87 static void __init spear3xx_timer_init(void)
91 { 88 {
92 char pclk_name[] = "pll3_clk"; 89 char pclk_name[] = "pll3_clk";
93 struct clk *gpt_clk, *pclk; 90 struct clk *gpt_clk, *pclk;
94 91
95 spear3xx_clk_init(); 92 spear3xx_clk_init();
96 93
97 /* get the system timer clock */ 94 /* get the system timer clock */
98 gpt_clk = clk_get_sys("gpt0", NULL); 95 gpt_clk = clk_get_sys("gpt0", NULL);
99 if (IS_ERR(gpt_clk)) { 96 if (IS_ERR(gpt_clk)) {
100 pr_err("%s:couldn't get clk for gpt\n", __func__); 97 pr_err("%s:couldn't get clk for gpt\n", __func__);
101 BUG(); 98 BUG();
102 } 99 }
103 100
104 /* get the suitable parent clock for timer*/ 101 /* get the suitable parent clock for timer*/
105 pclk = clk_get(NULL, pclk_name); 102 pclk = clk_get(NULL, pclk_name);
106 if (IS_ERR(pclk)) { 103 if (IS_ERR(pclk)) {
107 pr_err("%s:couldn't get %s as parent for gpt\n", 104 pr_err("%s:couldn't get %s as parent for gpt\n",
108 __func__, pclk_name); 105 __func__, pclk_name);
109 BUG(); 106 BUG();
110 } 107 }
111 108
112 clk_set_parent(gpt_clk, pclk); 109 clk_set_parent(gpt_clk, pclk);
113 clk_put(gpt_clk); 110 clk_put(gpt_clk);
114 clk_put(pclk); 111 clk_put(pclk);
115 112
116 spear_setup_of_timer(); 113 spear_setup_of_timer();
117 } 114 }
118 115
119 struct sys_timer spear3xx_timer = { 116 struct sys_timer spear3xx_timer = {
120 .init = spear3xx_timer_init, 117 .init = spear3xx_timer_init,
121 }; 118 };
122
123 static const struct of_device_id vic_of_match[] __initconst = {
124 { .compatible = "arm,pl190-vic", .data = vic_of_init, },
125 { .compatible = "st,spear300-shirq", .data = spear300_shirq_of_init, },
126 { .compatible = "st,spear310-shirq", .data = spear310_shirq_of_init, },
127 { .compatible = "st,spear320-shirq", .data = spear320_shirq_of_init, },
128 { /* Sentinel */ }
129 };
130
131 void __init spear3xx_dt_init_irq(void)
132 {
133 of_irq_init(vic_of_match);
134 }
135 119
arch/arm/mach-spear6xx/spear6xx.c
Diff comments   View file @ e9c5155
1 /* 1 /*
2 * arch/arm/mach-spear6xx/spear6xx.c 2 * arch/arm/mach-spear6xx/spear6xx.c
3 * 3 *
4 * SPEAr6XX machines common source file 4 * SPEAr6XX machines common source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009 ST Microelectronics
7 * Rajeev Kumar<rajeev-dlh.kumar@st.com> 7 * Rajeev Kumar<rajeev-dlh.kumar@st.com>
8 * 8 *
9 * Copyright 2012 Stefan Roese <sr@denx.de> 9 * Copyright 2012 Stefan Roese <sr@denx.de>
10 * 10 *
11 * This file is licensed under the terms of the GNU General Public 11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any 12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 */ 14 */
15 15
16 #include <linux/amba/pl08x.h> 16 #include <linux/amba/pl08x.h>
17 #include <linux/clk.h> 17 #include <linux/clk.h>
18 #include <linux/err.h> 18 #include <linux/err.h>
19 #include <linux/irqchip.h>
19 #include <linux/of.h> 20 #include <linux/of.h>
20 #include <linux/of_address.h> 21 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h> 22 #include <linux/of_platform.h>
23 #include <asm/hardware/pl080.h> 23 #include <asm/hardware/pl080.h>
24 #include <asm/hardware/vic.h>
25 #include <asm/mach/arch.h> 24 #include <asm/mach/arch.h>
26 #include <asm/mach/time.h> 25 #include <asm/mach/time.h>
27 #include <asm/mach/map.h> 26 #include <asm/mach/map.h>
28 #include <plat/pl080.h> 27 #include <plat/pl080.h>
29 #include <mach/generic.h> 28 #include <mach/generic.h>
30 #include <mach/spear.h> 29 #include <mach/spear.h>
31 30
32 /* dmac device registration */ 31 /* dmac device registration */
33 static struct pl08x_channel_data spear600_dma_info[] = { 32 static struct pl08x_channel_data spear600_dma_info[] = {
34 { 33 {
35 .bus_id = "ssp1_rx", 34 .bus_id = "ssp1_rx",
36 .min_signal = 0, 35 .min_signal = 0,
37 .max_signal = 0, 36 .max_signal = 0,
38 .muxval = 0, 37 .muxval = 0,
39 .periph_buses = PL08X_AHB1, 38 .periph_buses = PL08X_AHB1,
40 }, { 39 }, {
41 .bus_id = "ssp1_tx", 40 .bus_id = "ssp1_tx",
42 .min_signal = 1, 41 .min_signal = 1,
43 .max_signal = 1, 42 .max_signal = 1,
44 .muxval = 0, 43 .muxval = 0,
45 .periph_buses = PL08X_AHB1, 44 .periph_buses = PL08X_AHB1,
46 }, { 45 }, {
47 .bus_id = "uart0_rx", 46 .bus_id = "uart0_rx",
48 .min_signal = 2, 47 .min_signal = 2,
49 .max_signal = 2, 48 .max_signal = 2,
50 .muxval = 0, 49 .muxval = 0,
51 .periph_buses = PL08X_AHB1, 50 .periph_buses = PL08X_AHB1,
52 }, { 51 }, {
53 .bus_id = "uart0_tx", 52 .bus_id = "uart0_tx",
54 .min_signal = 3, 53 .min_signal = 3,
55 .max_signal = 3, 54 .max_signal = 3,
56 .muxval = 0, 55 .muxval = 0,
57 .periph_buses = PL08X_AHB1, 56 .periph_buses = PL08X_AHB1,
58 }, { 57 }, {
59 .bus_id = "uart1_rx", 58 .bus_id = "uart1_rx",
60 .min_signal = 4, 59 .min_signal = 4,
61 .max_signal = 4, 60 .max_signal = 4,
62 .muxval = 0, 61 .muxval = 0,
63 .periph_buses = PL08X_AHB1, 62 .periph_buses = PL08X_AHB1,
64 }, { 63 }, {
65 .bus_id = "uart1_tx", 64 .bus_id = "uart1_tx",
66 .min_signal = 5, 65 .min_signal = 5,
67 .max_signal = 5, 66 .max_signal = 5,
68 .muxval = 0, 67 .muxval = 0,
69 .periph_buses = PL08X_AHB1, 68 .periph_buses = PL08X_AHB1,
70 }, { 69 }, {
71 .bus_id = "ssp2_rx", 70 .bus_id = "ssp2_rx",
72 .min_signal = 6, 71 .min_signal = 6,
73 .max_signal = 6, 72 .max_signal = 6,
74 .muxval = 0, 73 .muxval = 0,
75 .periph_buses = PL08X_AHB2, 74 .periph_buses = PL08X_AHB2,
76 }, { 75 }, {
77 .bus_id = "ssp2_tx", 76 .bus_id = "ssp2_tx",
78 .min_signal = 7, 77 .min_signal = 7,
79 .max_signal = 7, 78 .max_signal = 7,
80 .muxval = 0, 79 .muxval = 0,
81 .periph_buses = PL08X_AHB2, 80 .periph_buses = PL08X_AHB2,
82 }, { 81 }, {
83 .bus_id = "ssp0_rx", 82 .bus_id = "ssp0_rx",
84 .min_signal = 8, 83 .min_signal = 8,
85 .max_signal = 8, 84 .max_signal = 8,
86 .muxval = 0, 85 .muxval = 0,
87 .periph_buses = PL08X_AHB1, 86 .periph_buses = PL08X_AHB1,
88 }, { 87 }, {
89 .bus_id = "ssp0_tx", 88 .bus_id = "ssp0_tx",
90 .min_signal = 9, 89 .min_signal = 9,
91 .max_signal = 9, 90 .max_signal = 9,
92 .muxval = 0, 91 .muxval = 0,
93 .periph_buses = PL08X_AHB1, 92 .periph_buses = PL08X_AHB1,
94 }, { 93 }, {
95 .bus_id = "i2c_rx", 94 .bus_id = "i2c_rx",
96 .min_signal = 10, 95 .min_signal = 10,
97 .max_signal = 10, 96 .max_signal = 10,
98 .muxval = 0, 97 .muxval = 0,
99 .periph_buses = PL08X_AHB1, 98 .periph_buses = PL08X_AHB1,
100 }, { 99 }, {
101 .bus_id = "i2c_tx", 100 .bus_id = "i2c_tx",
102 .min_signal = 11, 101 .min_signal = 11,
103 .max_signal = 11, 102 .max_signal = 11,
104 .muxval = 0, 103 .muxval = 0,
105 .periph_buses = PL08X_AHB1, 104 .periph_buses = PL08X_AHB1,
106 }, { 105 }, {
107 .bus_id = "irda", 106 .bus_id = "irda",
108 .min_signal = 12, 107 .min_signal = 12,
109 .max_signal = 12, 108 .max_signal = 12,
110 .muxval = 0, 109 .muxval = 0,
111 .periph_buses = PL08X_AHB1, 110 .periph_buses = PL08X_AHB1,
112 }, { 111 }, {
113 .bus_id = "adc", 112 .bus_id = "adc",
114 .min_signal = 13, 113 .min_signal = 13,
115 .max_signal = 13, 114 .max_signal = 13,
116 .muxval = 0, 115 .muxval = 0,
117 .periph_buses = PL08X_AHB2, 116 .periph_buses = PL08X_AHB2,
118 }, { 117 }, {
119 .bus_id = "to_jpeg", 118 .bus_id = "to_jpeg",
120 .min_signal = 14, 119 .min_signal = 14,
121 .max_signal = 14, 120 .max_signal = 14,
122 .muxval = 0, 121 .muxval = 0,
123 .periph_buses = PL08X_AHB1, 122 .periph_buses = PL08X_AHB1,
124 }, { 123 }, {
125 .bus_id = "from_jpeg", 124 .bus_id = "from_jpeg",
126 .min_signal = 15, 125 .min_signal = 15,
127 .max_signal = 15, 126 .max_signal = 15,
128 .muxval = 0, 127 .muxval = 0,
129 .periph_buses = PL08X_AHB1, 128 .periph_buses = PL08X_AHB1,
130 }, { 129 }, {
131 .bus_id = "ras0_rx", 130 .bus_id = "ras0_rx",
132 .min_signal = 0, 131 .min_signal = 0,
133 .max_signal = 0, 132 .max_signal = 0,
134 .muxval = 1, 133 .muxval = 1,
135 .periph_buses = PL08X_AHB1, 134 .periph_buses = PL08X_AHB1,
136 }, { 135 }, {
137 .bus_id = "ras0_tx", 136 .bus_id = "ras0_tx",
138 .min_signal = 1, 137 .min_signal = 1,
139 .max_signal = 1, 138 .max_signal = 1,
140 .muxval = 1, 139 .muxval = 1,
141 .periph_buses = PL08X_AHB1, 140 .periph_buses = PL08X_AHB1,
142 }, { 141 }, {
143 .bus_id = "ras1_rx", 142 .bus_id = "ras1_rx",
144 .min_signal = 2, 143 .min_signal = 2,
145 .max_signal = 2, 144 .max_signal = 2,
146 .muxval = 1, 145 .muxval = 1,
147 .periph_buses = PL08X_AHB1, 146 .periph_buses = PL08X_AHB1,
148 }, { 147 }, {
149 .bus_id = "ras1_tx", 148 .bus_id = "ras1_tx",
150 .min_signal = 3, 149 .min_signal = 3,
151 .max_signal = 3, 150 .max_signal = 3,
152 .muxval = 1, 151 .muxval = 1,
153 .periph_buses = PL08X_AHB1, 152 .periph_buses = PL08X_AHB1,
154 }, { 153 }, {
155 .bus_id = "ras2_rx", 154 .bus_id = "ras2_rx",
156 .min_signal = 4, 155 .min_signal = 4,
157 .max_signal = 4, 156 .max_signal = 4,
158 .muxval = 1, 157 .muxval = 1,
159 .periph_buses = PL08X_AHB1, 158 .periph_buses = PL08X_AHB1,
160 }, { 159 }, {
161 .bus_id = "ras2_tx", 160 .bus_id = "ras2_tx",
162 .min_signal = 5, 161 .min_signal = 5,
163 .max_signal = 5, 162 .max_signal = 5,
164 .muxval = 1, 163 .muxval = 1,
165 .periph_buses = PL08X_AHB1, 164 .periph_buses = PL08X_AHB1,
166 }, { 165 }, {
167 .bus_id = "ras3_rx", 166 .bus_id = "ras3_rx",
168 .min_signal = 6, 167 .min_signal = 6,
169 .max_signal = 6, 168 .max_signal = 6,
170 .muxval = 1, 169 .muxval = 1,
171 .periph_buses = PL08X_AHB1, 170 .periph_buses = PL08X_AHB1,
172 }, { 171 }, {
173 .bus_id = "ras3_tx", 172 .bus_id = "ras3_tx",
174 .min_signal = 7, 173 .min_signal = 7,
175 .max_signal = 7, 174 .max_signal = 7,
176 .muxval = 1, 175 .muxval = 1,
177 .periph_buses = PL08X_AHB1, 176 .periph_buses = PL08X_AHB1,
178 }, { 177 }, {
179 .bus_id = "ras4_rx", 178 .bus_id = "ras4_rx",
180 .min_signal = 8, 179 .min_signal = 8,
181 .max_signal = 8, 180 .max_signal = 8,
182 .muxval = 1, 181 .muxval = 1,
183 .periph_buses = PL08X_AHB1, 182 .periph_buses = PL08X_AHB1,
184 }, { 183 }, {
185 .bus_id = "ras4_tx", 184 .bus_id = "ras4_tx",
186 .min_signal = 9, 185 .min_signal = 9,
187 .max_signal = 9, 186 .max_signal = 9,
188 .muxval = 1, 187 .muxval = 1,
189 .periph_buses = PL08X_AHB1, 188 .periph_buses = PL08X_AHB1,
190 }, { 189 }, {
191 .bus_id = "ras5_rx", 190 .bus_id = "ras5_rx",
192 .min_signal = 10, 191 .min_signal = 10,
193 .max_signal = 10, 192 .max_signal = 10,
194 .muxval = 1, 193 .muxval = 1,
195 .periph_buses = PL08X_AHB1, 194 .periph_buses = PL08X_AHB1,
196 }, { 195 }, {
197 .bus_id = "ras5_tx", 196 .bus_id = "ras5_tx",
198 .min_signal = 11, 197 .min_signal = 11,
199 .max_signal = 11, 198 .max_signal = 11,
200 .muxval = 1, 199 .muxval = 1,
201 .periph_buses = PL08X_AHB1, 200 .periph_buses = PL08X_AHB1,
202 }, { 201 }, {
203 .bus_id = "ras6_rx", 202 .bus_id = "ras6_rx",
204 .min_signal = 12, 203 .min_signal = 12,
205 .max_signal = 12, 204 .max_signal = 12,
206 .muxval = 1, 205 .muxval = 1,
207 .periph_buses = PL08X_AHB1, 206 .periph_buses = PL08X_AHB1,
208 }, { 207 }, {
209 .bus_id = "ras6_tx", 208 .bus_id = "ras6_tx",
210 .min_signal = 13, 209 .min_signal = 13,
211 .max_signal = 13, 210 .max_signal = 13,
212 .muxval = 1, 211 .muxval = 1,
213 .periph_buses = PL08X_AHB1, 212 .periph_buses = PL08X_AHB1,
214 }, { 213 }, {
215 .bus_id = "ras7_rx", 214 .bus_id = "ras7_rx",
216 .min_signal = 14, 215 .min_signal = 14,
217 .max_signal = 14, 216 .max_signal = 14,
218 .muxval = 1, 217 .muxval = 1,
219 .periph_buses = PL08X_AHB1, 218 .periph_buses = PL08X_AHB1,
220 }, { 219 }, {
221 .bus_id = "ras7_tx", 220 .bus_id = "ras7_tx",
222 .min_signal = 15, 221 .min_signal = 15,
223 .max_signal = 15, 222 .max_signal = 15,
224 .muxval = 1, 223 .muxval = 1,
225 .periph_buses = PL08X_AHB1, 224 .periph_buses = PL08X_AHB1,
226 }, { 225 }, {
227 .bus_id = "ext0_rx", 226 .bus_id = "ext0_rx",
228 .min_signal = 0, 227 .min_signal = 0,
229 .max_signal = 0, 228 .max_signal = 0,
230 .muxval = 2, 229 .muxval = 2,
231 .periph_buses = PL08X_AHB2, 230 .periph_buses = PL08X_AHB2,
232 }, { 231 }, {
233 .bus_id = "ext0_tx", 232 .bus_id = "ext0_tx",
234 .min_signal = 1, 233 .min_signal = 1,
235 .max_signal = 1, 234 .max_signal = 1,
236 .muxval = 2, 235 .muxval = 2,
237 .periph_buses = PL08X_AHB2, 236 .periph_buses = PL08X_AHB2,
238 }, { 237 }, {
239 .bus_id = "ext1_rx", 238 .bus_id = "ext1_rx",
240 .min_signal = 2, 239 .min_signal = 2,
241 .max_signal = 2, 240 .max_signal = 2,
242 .muxval = 2, 241 .muxval = 2,
243 .periph_buses = PL08X_AHB2, 242 .periph_buses = PL08X_AHB2,
244 }, { 243 }, {
245 .bus_id = "ext1_tx", 244 .bus_id = "ext1_tx",
246 .min_signal = 3, 245 .min_signal = 3,
247 .max_signal = 3, 246 .max_signal = 3,
248 .muxval = 2, 247 .muxval = 2,
249 .periph_buses = PL08X_AHB2, 248 .periph_buses = PL08X_AHB2,
250 }, { 249 }, {
251 .bus_id = "ext2_rx", 250 .bus_id = "ext2_rx",
252 .min_signal = 4, 251 .min_signal = 4,
253 .max_signal = 4, 252 .max_signal = 4,
254 .muxval = 2, 253 .muxval = 2,
255 .periph_buses = PL08X_AHB2, 254 .periph_buses = PL08X_AHB2,
256 }, { 255 }, {
257 .bus_id = "ext2_tx", 256 .bus_id = "ext2_tx",
258 .min_signal = 5, 257 .min_signal = 5,
259 .max_signal = 5, 258 .max_signal = 5,
260 .muxval = 2, 259 .muxval = 2,
261 .periph_buses = PL08X_AHB2, 260 .periph_buses = PL08X_AHB2,
262 }, { 261 }, {
263 .bus_id = "ext3_rx", 262 .bus_id = "ext3_rx",
264 .min_signal = 6, 263 .min_signal = 6,
265 .max_signal = 6, 264 .max_signal = 6,
266 .muxval = 2, 265 .muxval = 2,
267 .periph_buses = PL08X_AHB2, 266 .periph_buses = PL08X_AHB2,
268 }, { 267 }, {
269 .bus_id = "ext3_tx", 268 .bus_id = "ext3_tx",
270 .min_signal = 7, 269 .min_signal = 7,
271 .max_signal = 7, 270 .max_signal = 7,
272 .muxval = 2, 271 .muxval = 2,
273 .periph_buses = PL08X_AHB2, 272 .periph_buses = PL08X_AHB2,
274 }, { 273 }, {
275 .bus_id = "ext4_rx", 274 .bus_id = "ext4_rx",
276 .min_signal = 8, 275 .min_signal = 8,
277 .max_signal = 8, 276 .max_signal = 8,
278 .muxval = 2, 277 .muxval = 2,
279 .periph_buses = PL08X_AHB2, 278 .periph_buses = PL08X_AHB2,
280 }, { 279 }, {
281 .bus_id = "ext4_tx", 280 .bus_id = "ext4_tx",
282 .min_signal = 9, 281 .min_signal = 9,
283 .max_signal = 9, 282 .max_signal = 9,
284 .muxval = 2, 283 .muxval = 2,
285 .periph_buses = PL08X_AHB2, 284 .periph_buses = PL08X_AHB2,
286 }, { 285 }, {
287 .bus_id = "ext5_rx", 286 .bus_id = "ext5_rx",
288 .min_signal = 10, 287 .min_signal = 10,
289 .max_signal = 10, 288 .max_signal = 10,
290 .muxval = 2, 289 .muxval = 2,
291 .periph_buses = PL08X_AHB2, 290 .periph_buses = PL08X_AHB2,
292 }, { 291 }, {
293 .bus_id = "ext5_tx", 292 .bus_id = "ext5_tx",
294 .min_signal = 11, 293 .min_signal = 11,
295 .max_signal = 11, 294 .max_signal = 11,
296 .muxval = 2, 295 .muxval = 2,
297 .periph_buses = PL08X_AHB2, 296 .periph_buses = PL08X_AHB2,
298 }, { 297 }, {
299 .bus_id = "ext6_rx", 298 .bus_id = "ext6_rx",
300 .min_signal = 12, 299 .min_signal = 12,
301 .max_signal = 12, 300 .max_signal = 12,
302 .muxval = 2, 301 .muxval = 2,
303 .periph_buses = PL08X_AHB2, 302 .periph_buses = PL08X_AHB2,
304 }, { 303 }, {
305 .bus_id = "ext6_tx", 304 .bus_id = "ext6_tx",
306 .min_signal = 13, 305 .min_signal = 13,
307 .max_signal = 13, 306 .max_signal = 13,
308 .muxval = 2, 307 .muxval = 2,
309 .periph_buses = PL08X_AHB2, 308 .periph_buses = PL08X_AHB2,
310 }, { 309 }, {
311 .bus_id = "ext7_rx", 310 .bus_id = "ext7_rx",
312 .min_signal = 14, 311 .min_signal = 14,
313 .max_signal = 14, 312 .max_signal = 14,
314 .muxval = 2, 313 .muxval = 2,
315 .periph_buses = PL08X_AHB2, 314 .periph_buses = PL08X_AHB2,
316 }, { 315 }, {
317 .bus_id = "ext7_tx", 316 .bus_id = "ext7_tx",
318 .min_signal = 15, 317 .min_signal = 15,
319 .max_signal = 15, 318 .max_signal = 15,
320 .muxval = 2, 319 .muxval = 2,
321 .periph_buses = PL08X_AHB2, 320 .periph_buses = PL08X_AHB2,
322 }, 321 },
323 }; 322 };
324 323
325 struct pl08x_platform_data pl080_plat_data = { 324 struct pl08x_platform_data pl080_plat_data = {
326 .memcpy_channel = { 325 .memcpy_channel = {
327 .bus_id = "memcpy", 326 .bus_id = "memcpy",
328 .cctl_memcpy = 327 .cctl_memcpy =
329 (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ 328 (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
330 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ 329 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
331 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ 330 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
332 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ 331 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
333 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ 332 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
334 PL080_CONTROL_PROT_SYS), 333 PL080_CONTROL_PROT_SYS),
335 }, 334 },
336 .lli_buses = PL08X_AHB1, 335 .lli_buses = PL08X_AHB1,
337 .mem_buses = PL08X_AHB1, 336 .mem_buses = PL08X_AHB1,
338 .get_signal = pl080_get_signal, 337 .get_signal = pl080_get_signal,
339 .put_signal = pl080_put_signal, 338 .put_signal = pl080_put_signal,
340 .slave_channels = spear600_dma_info, 339 .slave_channels = spear600_dma_info,
341 .num_slave_channels = ARRAY_SIZE(spear600_dma_info), 340 .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
342 }; 341 };
343 342
344 /* 343 /*
345 * Following will create 16MB static virtual/physical mappings 344 * Following will create 16MB static virtual/physical mappings
346 * PHYSICAL VIRTUAL 345 * PHYSICAL VIRTUAL
347 * 0xF0000000 0xF0000000 346 * 0xF0000000 0xF0000000
348 * 0xF1000000 0xF1000000 347 * 0xF1000000 0xF1000000
349 * 0xD0000000 0xFD000000 348 * 0xD0000000 0xFD000000
350 * 0xFC000000 0xFC000000 349 * 0xFC000000 0xFC000000
351 */ 350 */
352 struct map_desc spear6xx_io_desc[] __initdata = { 351 struct map_desc spear6xx_io_desc[] __initdata = {
353 { 352 {
354 .virtual = VA_SPEAR6XX_ML_CPU_BASE, 353 .virtual = VA_SPEAR6XX_ML_CPU_BASE,
355 .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE), 354 .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
356 .length = 2 * SZ_16M, 355 .length = 2 * SZ_16M,
357 .type = MT_DEVICE 356 .type = MT_DEVICE
358 }, { 357 }, {
359 .virtual = VA_SPEAR6XX_ICM1_BASE, 358 .virtual = VA_SPEAR6XX_ICM1_BASE,
360 .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE), 359 .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
361 .length = SZ_16M, 360 .length = SZ_16M,
362 .type = MT_DEVICE 361 .type = MT_DEVICE
363 }, { 362 }, {
364 .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE, 363 .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
365 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE), 364 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
366 .length = SZ_16M, 365 .length = SZ_16M,
367 .type = MT_DEVICE 366 .type = MT_DEVICE
368 }, 367 },
369 }; 368 };
370 369
371 /* This will create static memory mapping for selected devices */ 370 /* This will create static memory mapping for selected devices */
372 void __init spear6xx_map_io(void) 371 void __init spear6xx_map_io(void)
373 { 372 {
374 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); 373 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
375 } 374 }
376 375
377 static void __init spear6xx_timer_init(void) 376 static void __init spear6xx_timer_init(void)
378 { 377 {
379 char pclk_name[] = "pll3_clk"; 378 char pclk_name[] = "pll3_clk";
380 struct clk *gpt_clk, *pclk; 379 struct clk *gpt_clk, *pclk;
381 380
382 spear6xx_clk_init(); 381 spear6xx_clk_init();
383 382
384 /* get the system timer clock */ 383 /* get the system timer clock */
385 gpt_clk = clk_get_sys("gpt0", NULL); 384 gpt_clk = clk_get_sys("gpt0", NULL);
386 if (IS_ERR(gpt_clk)) { 385 if (IS_ERR(gpt_clk)) {
387 pr_err("%s:couldn't get clk for gpt\n", __func__); 386 pr_err("%s:couldn't get clk for gpt\n", __func__);
388 BUG(); 387 BUG();
389 } 388 }
390 389
391 /* get the suitable parent clock for timer*/ 390 /* get the suitable parent clock for timer*/
392 pclk = clk_get(NULL, pclk_name); 391 pclk = clk_get(NULL, pclk_name);
393 if (IS_ERR(pclk)) { 392 if (IS_ERR(pclk)) {
394 pr_err("%s:couldn't get %s as parent for gpt\n", 393 pr_err("%s:couldn't get %s as parent for gpt\n",
395 __func__, pclk_name); 394 __func__, pclk_name);
396 BUG(); 395 BUG();
397 } 396 }
398 397
399 clk_set_parent(gpt_clk, pclk); 398 clk_set_parent(gpt_clk, pclk);
400 clk_put(gpt_clk); 399 clk_put(gpt_clk);
401 clk_put(pclk); 400 clk_put(pclk);
402 401
403 spear_setup_of_timer(); 402 spear_setup_of_timer();
404 } 403 }
405 404
406 struct sys_timer spear6xx_timer = { 405 struct sys_timer spear6xx_timer = {
407 .init = spear6xx_timer_init, 406 .init = spear6xx_timer_init,
408 }; 407 };
409 408
410 /* Add auxdata to pass platform data */ 409 /* Add auxdata to pass platform data */
411 struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = { 410 struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
412 OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL, 411 OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
413 &pl080_plat_data), 412 &pl080_plat_data),
414 {} 413 {}
415 }; 414 };
416 415
417 static void __init spear600_dt_init(void) 416 static void __init spear600_dt_init(void)
418 { 417 {
419 of_platform_populate(NULL, of_default_bus_match_table, 418 of_platform_populate(NULL, of_default_bus_match_table,
420 spear6xx_auxdata_lookup, NULL); 419 spear6xx_auxdata_lookup, NULL);
421 } 420 }
422 421
423 static const char *spear600_dt_board_compat[] = { 422 static const char *spear600_dt_board_compat[] = {
424 "st,spear600", 423 "st,spear600",
425 NULL 424 NULL
426 }; 425 };
427 426
428 static const struct of_device_id vic_of_match[] __initconst = {
429 { .compatible = "arm,pl190-vic", .data = vic_of_init, },
430 { /* Sentinel */ }
431 };
432
433 static void __init spear6xx_dt_init_irq(void)
434 {
435 of_irq_init(vic_of_match);
436 }
437
438 DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)") 427 DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
439 .map_io = spear6xx_map_io, 428 .map_io = spear6xx_map_io,
440 .init_irq = spear6xx_dt_init_irq, 429 .init_irq = irqchip_init,
441 .timer = &spear6xx_timer, 430 .timer = &spear6xx_timer,
442 .init_machine = spear600_dt_init, 431 .init_machine = spear600_dt_init,
443 .restart = spear_restart, 432 .restart = spear_restart,
444 .dt_compat = spear600_dt_board_compat, 433 .dt_compat = spear600_dt_board_compat,
445 MACHINE_END 434 MACHINE_END
drivers/irqchip/spear-shirq.c
Diff comments   View file @ e9c5155
1 /* 1 /*
2 * SPEAr platform shared irq layer source file 2 * SPEAr platform shared irq layer source file
3 * 3 *
4 * Copyright (C) 2009-2012 ST Microelectronics 4 * Copyright (C) 2009-2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * Copyright (C) 2012 ST Microelectronics 7 * Copyright (C) 2012 ST Microelectronics
8 * Shiraz Hashim <shiraz.hashim@st.com> 8 * Shiraz Hashim <shiraz.hashim@st.com>
9 * 9 *
10 * This file is licensed under the terms of the GNU General Public 10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any 11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied. 12 * warranty of any kind, whether express or implied.
13 */ 13 */
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 15
16 #include <linux/err.h> 16 #include <linux/err.h>
17 #include <linux/export.h> 17 #include <linux/export.h>
18 #include <linux/interrupt.h> 18 #include <linux/interrupt.h>
19 #include <linux/io.h> 19 #include <linux/io.h>
20 #include <linux/irq.h> 20 #include <linux/irq.h>
21 #include <linux/irqdomain.h> 21 #include <linux/irqdomain.h>
22 #include <linux/irqchip/spear-shirq.h> 22 #include <linux/irqchip/spear-shirq.h>
23 #include <linux/of.h> 23 #include <linux/of.h>
24 #include <linux/of_address.h> 24 #include <linux/of_address.h>
25 #include <linux/of_irq.h> 25 #include <linux/of_irq.h>
26 #include <linux/spinlock.h> 26 #include <linux/spinlock.h>
27 27
28 #include "irqchip.h"
29
28 static DEFINE_SPINLOCK(lock); 30 static DEFINE_SPINLOCK(lock);
29 31
30 /* spear300 shared irq registers offsets and masks */ 32 /* spear300 shared irq registers offsets and masks */
31 #define SPEAR300_INT_ENB_MASK_REG 0x54 33 #define SPEAR300_INT_ENB_MASK_REG 0x54
32 #define SPEAR300_INT_STS_MASK_REG 0x58 34 #define SPEAR300_INT_STS_MASK_REG 0x58
33 35
34 static struct spear_shirq spear300_shirq_ras1 = { 36 static struct spear_shirq spear300_shirq_ras1 = {
35 .irq_nr = 9, 37 .irq_nr = 9,
36 .irq_bit_off = 0, 38 .irq_bit_off = 0,
37 .regs = { 39 .regs = {
38 .enb_reg = SPEAR300_INT_ENB_MASK_REG, 40 .enb_reg = SPEAR300_INT_ENB_MASK_REG,
39 .status_reg = SPEAR300_INT_STS_MASK_REG, 41 .status_reg = SPEAR300_INT_STS_MASK_REG,
40 .clear_reg = -1, 42 .clear_reg = -1,
41 }, 43 },
42 }; 44 };
43 45
44 static struct spear_shirq *spear300_shirq_blocks[] = { 46 static struct spear_shirq *spear300_shirq_blocks[] = {
45 &spear300_shirq_ras1, 47 &spear300_shirq_ras1,
46 }; 48 };
47 49
48 /* spear310 shared irq registers offsets and masks */ 50 /* spear310 shared irq registers offsets and masks */
49 #define SPEAR310_INT_STS_MASK_REG 0x04 51 #define SPEAR310_INT_STS_MASK_REG 0x04
50 52
51 static struct spear_shirq spear310_shirq_ras1 = { 53 static struct spear_shirq spear310_shirq_ras1 = {
52 .irq_nr = 8, 54 .irq_nr = 8,
53 .irq_bit_off = 0, 55 .irq_bit_off = 0,
54 .regs = { 56 .regs = {
55 .enb_reg = -1, 57 .enb_reg = -1,
56 .status_reg = SPEAR310_INT_STS_MASK_REG, 58 .status_reg = SPEAR310_INT_STS_MASK_REG,
57 .clear_reg = -1, 59 .clear_reg = -1,
58 }, 60 },
59 }; 61 };
60 62
61 static struct spear_shirq spear310_shirq_ras2 = { 63 static struct spear_shirq spear310_shirq_ras2 = {
62 .irq_nr = 5, 64 .irq_nr = 5,
63 .irq_bit_off = 8, 65 .irq_bit_off = 8,
64 .regs = { 66 .regs = {
65 .enb_reg = -1, 67 .enb_reg = -1,
66 .status_reg = SPEAR310_INT_STS_MASK_REG, 68 .status_reg = SPEAR310_INT_STS_MASK_REG,
67 .clear_reg = -1, 69 .clear_reg = -1,
68 }, 70 },
69 }; 71 };
70 72
71 static struct spear_shirq spear310_shirq_ras3 = { 73 static struct spear_shirq spear310_shirq_ras3 = {
72 .irq_nr = 1, 74 .irq_nr = 1,
73 .irq_bit_off = 13, 75 .irq_bit_off = 13,
74 .regs = { 76 .regs = {
75 .enb_reg = -1, 77 .enb_reg = -1,
76 .status_reg = SPEAR310_INT_STS_MASK_REG, 78 .status_reg = SPEAR310_INT_STS_MASK_REG,
77 .clear_reg = -1, 79 .clear_reg = -1,
78 }, 80 },
79 }; 81 };
80 82
81 static struct spear_shirq spear310_shirq_intrcomm_ras = { 83 static struct spear_shirq spear310_shirq_intrcomm_ras = {
82 .irq_nr = 3, 84 .irq_nr = 3,
83 .irq_bit_off = 14, 85 .irq_bit_off = 14,
84 .regs = { 86 .regs = {
85 .enb_reg = -1, 87 .enb_reg = -1,
86 .status_reg = SPEAR310_INT_STS_MASK_REG, 88 .status_reg = SPEAR310_INT_STS_MASK_REG,
87 .clear_reg = -1, 89 .clear_reg = -1,
88 }, 90 },
89 }; 91 };
90 92
91 static struct spear_shirq *spear310_shirq_blocks[] = { 93 static struct spear_shirq *spear310_shirq_blocks[] = {
92 &spear310_shirq_ras1, 94 &spear310_shirq_ras1,
93 &spear310_shirq_ras2, 95 &spear310_shirq_ras2,
94 &spear310_shirq_ras3, 96 &spear310_shirq_ras3,
95 &spear310_shirq_intrcomm_ras, 97 &spear310_shirq_intrcomm_ras,
96 }; 98 };
97 99
98 /* spear320 shared irq registers offsets and masks */ 100 /* spear320 shared irq registers offsets and masks */
99 #define SPEAR320_INT_STS_MASK_REG 0x04 101 #define SPEAR320_INT_STS_MASK_REG 0x04
100 #define SPEAR320_INT_CLR_MASK_REG 0x04 102 #define SPEAR320_INT_CLR_MASK_REG 0x04
101 #define SPEAR320_INT_ENB_MASK_REG 0x08 103 #define SPEAR320_INT_ENB_MASK_REG 0x08
102 104
103 static struct spear_shirq spear320_shirq_ras1 = { 105 static struct spear_shirq spear320_shirq_ras1 = {
104 .irq_nr = 3, 106 .irq_nr = 3,
105 .irq_bit_off = 7, 107 .irq_bit_off = 7,
106 .regs = { 108 .regs = {
107 .enb_reg = -1, 109 .enb_reg = -1,
108 .status_reg = SPEAR320_INT_STS_MASK_REG, 110 .status_reg = SPEAR320_INT_STS_MASK_REG,
109 .clear_reg = SPEAR320_INT_CLR_MASK_REG, 111 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
110 .reset_to_clear = 1, 112 .reset_to_clear = 1,
111 }, 113 },
112 }; 114 };
113 115
114 static struct spear_shirq spear320_shirq_ras2 = { 116 static struct spear_shirq spear320_shirq_ras2 = {
115 .irq_nr = 1, 117 .irq_nr = 1,
116 .irq_bit_off = 10, 118 .irq_bit_off = 10,
117 .regs = { 119 .regs = {
118 .enb_reg = -1, 120 .enb_reg = -1,
119 .status_reg = SPEAR320_INT_STS_MASK_REG, 121 .status_reg = SPEAR320_INT_STS_MASK_REG,
120 .clear_reg = SPEAR320_INT_CLR_MASK_REG, 122 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
121 .reset_to_clear = 1, 123 .reset_to_clear = 1,
122 }, 124 },
123 }; 125 };
124 126
125 static struct spear_shirq spear320_shirq_ras3 = { 127 static struct spear_shirq spear320_shirq_ras3 = {
126 .irq_nr = 3, 128 .irq_nr = 3,
127 .irq_bit_off = 0, 129 .irq_bit_off = 0,
128 .invalid_irq = 1, 130 .invalid_irq = 1,
129 .regs = { 131 .regs = {
130 .enb_reg = SPEAR320_INT_ENB_MASK_REG, 132 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
131 .reset_to_enb = 1, 133 .reset_to_enb = 1,
132 .status_reg = SPEAR320_INT_STS_MASK_REG, 134 .status_reg = SPEAR320_INT_STS_MASK_REG,
133 .clear_reg = SPEAR320_INT_CLR_MASK_REG, 135 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
134 .reset_to_clear = 1, 136 .reset_to_clear = 1,
135 }, 137 },
136 }; 138 };
137 139
138 static struct spear_shirq spear320_shirq_intrcomm_ras = { 140 static struct spear_shirq spear320_shirq_intrcomm_ras = {
139 .irq_nr = 11, 141 .irq_nr = 11,
140 .irq_bit_off = 11, 142 .irq_bit_off = 11,
141 .regs = { 143 .regs = {
142 .enb_reg = -1, 144 .enb_reg = -1,
143 .status_reg = SPEAR320_INT_STS_MASK_REG, 145 .status_reg = SPEAR320_INT_STS_MASK_REG,
144 .clear_reg = SPEAR320_INT_CLR_MASK_REG, 146 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
145 .reset_to_clear = 1, 147 .reset_to_clear = 1,
146 }, 148 },
147 }; 149 };
148 150
149 static struct spear_shirq *spear320_shirq_blocks[] = { 151 static struct spear_shirq *spear320_shirq_blocks[] = {
150 &spear320_shirq_ras3, 152 &spear320_shirq_ras3,
151 &spear320_shirq_ras1, 153 &spear320_shirq_ras1,
152 &spear320_shirq_ras2, 154 &spear320_shirq_ras2,
153 &spear320_shirq_intrcomm_ras, 155 &spear320_shirq_intrcomm_ras,
154 }; 156 };
155 157
156 static void shirq_irq_mask_unmask(struct irq_data *d, bool mask) 158 static void shirq_irq_mask_unmask(struct irq_data *d, bool mask)
157 { 159 {
158 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d); 160 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
159 u32 val, offset = d->irq - shirq->irq_base; 161 u32 val, offset = d->irq - shirq->irq_base;
160 unsigned long flags; 162 unsigned long flags;
161 163
162 if (shirq->regs.enb_reg == -1) 164 if (shirq->regs.enb_reg == -1)
163 return; 165 return;
164 166
165 spin_lock_irqsave(&lock, flags); 167 spin_lock_irqsave(&lock, flags);
166 val = readl(shirq->base + shirq->regs.enb_reg); 168 val = readl(shirq->base + shirq->regs.enb_reg);
167 169
168 if (mask ^ shirq->regs.reset_to_enb) 170 if (mask ^ shirq->regs.reset_to_enb)
169 val &= ~(0x1 << shirq->irq_bit_off << offset); 171 val &= ~(0x1 << shirq->irq_bit_off << offset);
170 else 172 else
171 val |= 0x1 << shirq->irq_bit_off << offset; 173 val |= 0x1 << shirq->irq_bit_off << offset;
172 174
173 writel(val, shirq->base + shirq->regs.enb_reg); 175 writel(val, shirq->base + shirq->regs.enb_reg);
174 spin_unlock_irqrestore(&lock, flags); 176 spin_unlock_irqrestore(&lock, flags);
175 177
176 } 178 }
177 179
178 static void shirq_irq_mask(struct irq_data *d) 180 static void shirq_irq_mask(struct irq_data *d)
179 { 181 {
180 shirq_irq_mask_unmask(d, 1); 182 shirq_irq_mask_unmask(d, 1);
181 } 183 }
182 184
183 static void shirq_irq_unmask(struct irq_data *d) 185 static void shirq_irq_unmask(struct irq_data *d)
184 { 186 {
185 shirq_irq_mask_unmask(d, 0); 187 shirq_irq_mask_unmask(d, 0);
186 } 188 }
187 189
188 static struct irq_chip shirq_chip = { 190 static struct irq_chip shirq_chip = {
189 .name = "spear-shirq", 191 .name = "spear-shirq",
190 .irq_ack = shirq_irq_mask, 192 .irq_ack = shirq_irq_mask,
191 .irq_mask = shirq_irq_mask, 193 .irq_mask = shirq_irq_mask,
192 .irq_unmask = shirq_irq_unmask, 194 .irq_unmask = shirq_irq_unmask,
193 }; 195 };
194 196
195 static void shirq_handler(unsigned irq, struct irq_desc *desc) 197 static void shirq_handler(unsigned irq, struct irq_desc *desc)
196 { 198 {
197 u32 i, j, val, mask, tmp; 199 u32 i, j, val, mask, tmp;
198 struct irq_chip *chip; 200 struct irq_chip *chip;
199 struct spear_shirq *shirq = irq_get_handler_data(irq); 201 struct spear_shirq *shirq = irq_get_handler_data(irq);
200 202
201 chip = irq_get_chip(irq); 203 chip = irq_get_chip(irq);
202 chip->irq_ack(&desc->irq_data); 204 chip->irq_ack(&desc->irq_data);
203 205
204 mask = ((0x1 << shirq->irq_nr) - 1) << shirq->irq_bit_off; 206 mask = ((0x1 << shirq->irq_nr) - 1) << shirq->irq_bit_off;
205 while ((val = readl(shirq->base + shirq->regs.status_reg) & 207 while ((val = readl(shirq->base + shirq->regs.status_reg) &
206 mask)) { 208 mask)) {
207 209
208 val >>= shirq->irq_bit_off; 210 val >>= shirq->irq_bit_off;
209 for (i = 0, j = 1; i < shirq->irq_nr; i++, j <<= 1) { 211 for (i = 0, j = 1; i < shirq->irq_nr; i++, j <<= 1) {
210 212
211 if (!(j & val)) 213 if (!(j & val))
212 continue; 214 continue;
213 215
214 generic_handle_irq(shirq->irq_base + i); 216 generic_handle_irq(shirq->irq_base + i);
215 217
216 /* clear interrupt */ 218 /* clear interrupt */
217 if (shirq->regs.clear_reg == -1) 219 if (shirq->regs.clear_reg == -1)
218 continue; 220 continue;
219 221
220 tmp = readl(shirq->base + shirq->regs.clear_reg); 222 tmp = readl(shirq->base + shirq->regs.clear_reg);
221 if (shirq->regs.reset_to_clear) 223 if (shirq->regs.reset_to_clear)
222 tmp &= ~(j << shirq->irq_bit_off); 224 tmp &= ~(j << shirq->irq_bit_off);
223 else 225 else
224 tmp |= (j << shirq->irq_bit_off); 226 tmp |= (j << shirq->irq_bit_off);
225 writel(tmp, shirq->base + shirq->regs.clear_reg); 227 writel(tmp, shirq->base + shirq->regs.clear_reg);
226 } 228 }
227 } 229 }
228 chip->irq_unmask(&desc->irq_data); 230 chip->irq_unmask(&desc->irq_data);
229 } 231 }
230 232
231 static void __init spear_shirq_register(struct spear_shirq *shirq) 233 static void __init spear_shirq_register(struct spear_shirq *shirq)
232 { 234 {
233 int i; 235 int i;
234 236
235 if (shirq->invalid_irq) 237 if (shirq->invalid_irq)
236 return; 238 return;
237 239
238 irq_set_chained_handler(shirq->irq, shirq_handler); 240 irq_set_chained_handler(shirq->irq, shirq_handler);
239 for (i = 0; i < shirq->irq_nr; i++) { 241 for (i = 0; i < shirq->irq_nr; i++) {
240 irq_set_chip_and_handler(shirq->irq_base + i, 242 irq_set_chip_and_handler(shirq->irq_base + i,
241 &shirq_chip, handle_simple_irq); 243 &shirq_chip, handle_simple_irq);
242 set_irq_flags(shirq->irq_base + i, IRQF_VALID); 244 set_irq_flags(shirq->irq_base + i, IRQF_VALID);
243 irq_set_chip_data(shirq->irq_base + i, shirq); 245 irq_set_chip_data(shirq->irq_base + i, shirq);
244 } 246 }
245 247
246 irq_set_handler_data(shirq->irq, shirq); 248 irq_set_handler_data(shirq->irq, shirq);
247 } 249 }
248 250
249 static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr, 251 static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
250 struct device_node *np) 252 struct device_node *np)
251 { 253 {
252 int i, irq_base, hwirq = 0, irq_nr = 0; 254 int i, irq_base, hwirq = 0, irq_nr = 0;
253 static struct irq_domain *shirq_domain; 255 static struct irq_domain *shirq_domain;
254 void __iomem *base; 256 void __iomem *base;
255 257
256 base = of_iomap(np, 0); 258 base = of_iomap(np, 0);
257 if (!base) { 259 if (!base) {
258 pr_err("%s: failed to map shirq registers\n", __func__); 260 pr_err("%s: failed to map shirq registers\n", __func__);
259 return -ENXIO; 261 return -ENXIO;
260 } 262 }
261 263
262 for (i = 0; i < block_nr; i++) 264 for (i = 0; i < block_nr; i++)
263 irq_nr += shirq_blocks[i]->irq_nr; 265 irq_nr += shirq_blocks[i]->irq_nr;
264 266
265 irq_base = irq_alloc_descs(-1, 0, irq_nr, 0); 267 irq_base = irq_alloc_descs(-1, 0, irq_nr, 0);
266 if (IS_ERR_VALUE(irq_base)) { 268 if (IS_ERR_VALUE(irq_base)) {
267 pr_err("%s: irq desc alloc failed\n", __func__); 269 pr_err("%s: irq desc alloc failed\n", __func__);
268 goto err_unmap; 270 goto err_unmap;
269 } 271 }
270 272
271 shirq_domain = irq_domain_add_legacy(np, irq_nr, irq_base, 0, 273 shirq_domain = irq_domain_add_legacy(np, irq_nr, irq_base, 0,
272 &irq_domain_simple_ops, NULL); 274 &irq_domain_simple_ops, NULL);
273 if (WARN_ON(!shirq_domain)) { 275 if (WARN_ON(!shirq_domain)) {
274 pr_warn("%s: irq domain init failed\n", __func__); 276 pr_warn("%s: irq domain init failed\n", __func__);
275 goto err_free_desc; 277 goto err_free_desc;
276 } 278 }
277 279
278 for (i = 0; i < block_nr; i++) { 280 for (i = 0; i < block_nr; i++) {
279 shirq_blocks[i]->base = base; 281 shirq_blocks[i]->base = base;
280 shirq_blocks[i]->irq_base = irq_find_mapping(shirq_domain, 282 shirq_blocks[i]->irq_base = irq_find_mapping(shirq_domain,
281 hwirq); 283 hwirq);
282 shirq_blocks[i]->irq = irq_of_parse_and_map(np, i); 284 shirq_blocks[i]->irq = irq_of_parse_and_map(np, i);
283 285
284 spear_shirq_register(shirq_blocks[i]); 286 spear_shirq_register(shirq_blocks[i]);
285 hwirq += shirq_blocks[i]->irq_nr; 287 hwirq += shirq_blocks[i]->irq_nr;
286 } 288 }
287 289
288 return 0; 290 return 0;
289 291
290 err_free_desc: 292 err_free_desc:
291 irq_free_descs(irq_base, irq_nr); 293 irq_free_descs(irq_base, irq_nr);
292 err_unmap: 294 err_unmap:
293 iounmap(base); 295 iounmap(base);
294 return -ENXIO; 296 return -ENXIO;
295 } 297 }
296 298
297 int __init spear300_shirq_of_init(struct device_node *np, 299 int __init spear300_shirq_of_init(struct device_node *np,
298 struct device_node *parent) 300 struct device_node *parent)
299 { 301 {
300 return shirq_init(spear300_shirq_blocks, 302 return shirq_init(spear300_shirq_blocks,
301 ARRAY_SIZE(spear300_shirq_blocks), np); 303 ARRAY_SIZE(spear300_shirq_blocks), np);
302 } 304 }
305 IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init);
303 306
304 int __init spear310_shirq_of_init(struct device_node *np, 307 int __init spear310_shirq_of_init(struct device_node *np,
305 struct device_node *parent) 308 struct device_node *parent)
306 { 309 {
307 return shirq_init(spear310_shirq_blocks, 310 return shirq_init(spear310_shirq_blocks,
308 ARRAY_SIZE(spear310_shirq_blocks), np); 311 ARRAY_SIZE(spear310_shirq_blocks), np);
309 } 312 }
313 IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init);
310 314
311 int __init spear320_shirq_of_init(struct device_node *np, 315 int __init spear320_shirq_of_init(struct device_node *np,
312 struct device_node *parent) 316 struct device_node *parent)
313 { 317 {
314 return shirq_init(spear320_shirq_blocks, 318 return shirq_init(spear320_shirq_blocks,
315 ARRAY_SIZE(spear320_shirq_blocks), np); 319 ARRAY_SIZE(spear320_shirq_blocks), np);
316 } 320 }
321 IRQCHIP_DECLARE(spear320_shirq, "st,spear320-shirq", spear320_shirq_of_init);
317 322