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Commit ecfe57b796d4ccec7ea53783ca18a0ad48ad880b

Authored by Rafał Miłecki
Committed by Artem Bityutskiy
1 parent d8b1e34e24
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

mtd: bcm47xxnflash: writing support 

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>

Showing 2 changed files with 79 additions and 3 deletions Inline Diff

drivers/mtd/nand/Kconfig
Diff comments   View file @ ecfe57b
1 config MTD_NAND_ECC 1 config MTD_NAND_ECC
2 tristate 2 tristate
3 3
4 config MTD_NAND_ECC_SMC 4 config MTD_NAND_ECC_SMC
5 bool "NAND ECC Smart Media byte order" 5 bool "NAND ECC Smart Media byte order"
6 depends on MTD_NAND_ECC 6 depends on MTD_NAND_ECC
7 default n 7 default n
8 help 8 help
9 Software ECC according to the Smart Media Specification. 9 Software ECC according to the Smart Media Specification.
10 The original Linux implementation had byte 0 and 1 swapped. 10 The original Linux implementation had byte 0 and 1 swapped.
11 11
12 12
13 menuconfig MTD_NAND 13 menuconfig MTD_NAND
14 tristate "NAND Device Support" 14 tristate "NAND Device Support"
15 depends on MTD 15 depends on MTD
16 select MTD_NAND_IDS 16 select MTD_NAND_IDS
17 select MTD_NAND_ECC 17 select MTD_NAND_ECC
18 help 18 help
19 This enables support for accessing all type of NAND flash 19 This enables support for accessing all type of NAND flash
20 devices. For further information see 20 devices. For further information see
21 <http://www.linux-mtd.infradead.org/doc/nand.html>. 21 <http://www.linux-mtd.infradead.org/doc/nand.html>.
22 22
23 if MTD_NAND 23 if MTD_NAND
24 24
25 config MTD_NAND_BCH 25 config MTD_NAND_BCH
26 tristate 26 tristate
27 select BCH 27 select BCH
28 depends on MTD_NAND_ECC_BCH 28 depends on MTD_NAND_ECC_BCH
29 default MTD_NAND 29 default MTD_NAND
30 30
31 config MTD_NAND_ECC_BCH 31 config MTD_NAND_ECC_BCH
32 bool "Support software BCH ECC" 32 bool "Support software BCH ECC"
33 default n 33 default n
34 help 34 help
35 This enables support for software BCH error correction. Binary BCH 35 This enables support for software BCH error correction. Binary BCH
36 codes are more powerful and cpu intensive than traditional Hamming 36 codes are more powerful and cpu intensive than traditional Hamming
37 ECC codes. They are used with NAND devices requiring more than 1 bit 37 ECC codes. They are used with NAND devices requiring more than 1 bit
38 of error correction. 38 of error correction.
39 39
40 config MTD_SM_COMMON 40 config MTD_SM_COMMON
41 tristate 41 tristate
42 default n 42 default n
43 43
44 config MTD_NAND_MUSEUM_IDS 44 config MTD_NAND_MUSEUM_IDS
45 bool "Enable chip ids for obsolete ancient NAND devices" 45 bool "Enable chip ids for obsolete ancient NAND devices"
46 default n 46 default n
47 help 47 help
48 Enable this option only when your board has first generation 48 Enable this option only when your board has first generation
49 NAND chips (page size 256 byte, erase size 4-8KiB). The IDs 49 NAND chips (page size 256 byte, erase size 4-8KiB). The IDs
50 of these chips were reused by later, larger chips. 50 of these chips were reused by later, larger chips.
51 51
52 config MTD_NAND_AUTCPU12 52 config MTD_NAND_AUTCPU12
53 tristate "SmartMediaCard on autronix autcpu12 board" 53 tristate "SmartMediaCard on autronix autcpu12 board"
54 depends on ARCH_AUTCPU12 54 depends on ARCH_AUTCPU12
55 help 55 help
56 This enables the driver for the autronix autcpu12 board to 56 This enables the driver for the autronix autcpu12 board to
57 access the SmartMediaCard. 57 access the SmartMediaCard.
58 58
59 config MTD_NAND_DENALI 59 config MTD_NAND_DENALI
60 tristate "Support Denali NAND controller" 60 tristate "Support Denali NAND controller"
61 help 61 help
62 Enable support for the Denali NAND controller. This should be 62 Enable support for the Denali NAND controller. This should be
63 combined with either the PCI or platform drivers to provide device 63 combined with either the PCI or platform drivers to provide device
64 registration. 64 registration.
65 65
66 config MTD_NAND_DENALI_PCI 66 config MTD_NAND_DENALI_PCI
67 tristate "Support Denali NAND controller on Intel Moorestown" 67 tristate "Support Denali NAND controller on Intel Moorestown"
68 depends on PCI && MTD_NAND_DENALI 68 depends on PCI && MTD_NAND_DENALI
69 help 69 help
70 Enable the driver for NAND flash on Intel Moorestown, using the 70 Enable the driver for NAND flash on Intel Moorestown, using the
71 Denali NAND controller core. 71 Denali NAND controller core.
72 72
73 config MTD_NAND_DENALI_DT 73 config MTD_NAND_DENALI_DT
74 tristate "Support Denali NAND controller as a DT device" 74 tristate "Support Denali NAND controller as a DT device"
75 depends on HAVE_CLK && MTD_NAND_DENALI 75 depends on HAVE_CLK && MTD_NAND_DENALI
76 help 76 help
77 Enable the driver for NAND flash on platforms using a Denali NAND 77 Enable the driver for NAND flash on platforms using a Denali NAND
78 controller as a DT device. 78 controller as a DT device.
79 79
80 config MTD_NAND_DENALI_SCRATCH_REG_ADDR 80 config MTD_NAND_DENALI_SCRATCH_REG_ADDR
81 hex "Denali NAND size scratch register address" 81 hex "Denali NAND size scratch register address"
82 default "0xFF108018" 82 default "0xFF108018"
83 depends on MTD_NAND_DENALI_PCI 83 depends on MTD_NAND_DENALI_PCI
84 help 84 help
85 Some platforms place the NAND chip size in a scratch register 85 Some platforms place the NAND chip size in a scratch register
86 because (some versions of) the driver aren't able to automatically 86 because (some versions of) the driver aren't able to automatically
87 determine the size of certain chips. Set the address of the 87 determine the size of certain chips. Set the address of the
88 scratch register here to enable this feature. On Intel Moorestown 88 scratch register here to enable this feature. On Intel Moorestown
89 boards, the scratch register is at 0xFF108018. 89 boards, the scratch register is at 0xFF108018.
90 90
91 config MTD_NAND_H1900 91 config MTD_NAND_H1900
92 tristate "iPAQ H1900 flash" 92 tristate "iPAQ H1900 flash"
93 depends on ARCH_PXA && BROKEN 93 depends on ARCH_PXA && BROKEN
94 help 94 help
95 This enables the driver for the iPAQ h1900 flash. 95 This enables the driver for the iPAQ h1900 flash.
96 96
97 config MTD_NAND_GPIO 97 config MTD_NAND_GPIO
98 tristate "GPIO NAND Flash driver" 98 tristate "GPIO NAND Flash driver"
99 depends on GENERIC_GPIO && ARM 99 depends on GENERIC_GPIO && ARM
100 help 100 help
101 This enables a GPIO based NAND flash driver. 101 This enables a GPIO based NAND flash driver.
102 102
103 config MTD_NAND_SPIA 103 config MTD_NAND_SPIA
104 tristate "NAND Flash device on SPIA board" 104 tristate "NAND Flash device on SPIA board"
105 depends on ARCH_P720T 105 depends on ARCH_P720T
106 help 106 help
107 If you had to ask, you don't have one. Say 'N'. 107 If you had to ask, you don't have one. Say 'N'.
108 108
109 config MTD_NAND_AMS_DELTA 109 config MTD_NAND_AMS_DELTA
110 tristate "NAND Flash device on Amstrad E3" 110 tristate "NAND Flash device on Amstrad E3"
111 depends on MACH_AMS_DELTA 111 depends on MACH_AMS_DELTA
112 default y 112 default y
113 help 113 help
114 Support for NAND flash on Amstrad E3 (Delta). 114 Support for NAND flash on Amstrad E3 (Delta).
115 115
116 config MTD_NAND_OMAP2 116 config MTD_NAND_OMAP2
117 tristate "NAND Flash device on OMAP2, OMAP3 and OMAP4" 117 tristate "NAND Flash device on OMAP2, OMAP3 and OMAP4"
118 depends on ARCH_OMAP2PLUS 118 depends on ARCH_OMAP2PLUS
119 help 119 help
120 Support for NAND flash on Texas Instruments OMAP2, OMAP3 and OMAP4 120 Support for NAND flash on Texas Instruments OMAP2, OMAP3 and OMAP4
121 platforms. 121 platforms.
122 122
123 config MTD_NAND_OMAP_BCH 123 config MTD_NAND_OMAP_BCH
124 depends on MTD_NAND && MTD_NAND_OMAP2 && ARCH_OMAP3 124 depends on MTD_NAND && MTD_NAND_OMAP2 && ARCH_OMAP3
125 bool "Enable support for hardware BCH error correction" 125 bool "Enable support for hardware BCH error correction"
126 default n 126 default n
127 select BCH 127 select BCH
128 select BCH_CONST_PARAMS 128 select BCH_CONST_PARAMS
129 help 129 help
130 Support for hardware BCH error correction. 130 Support for hardware BCH error correction.
131 131
132 choice 132 choice
133 prompt "BCH error correction capability" 133 prompt "BCH error correction capability"
134 depends on MTD_NAND_OMAP_BCH 134 depends on MTD_NAND_OMAP_BCH
135 135
136 config MTD_NAND_OMAP_BCH8 136 config MTD_NAND_OMAP_BCH8
137 bool "8 bits / 512 bytes (recommended)" 137 bool "8 bits / 512 bytes (recommended)"
138 help 138 help
139 Support correcting up to 8 bitflips per 512-byte block. 139 Support correcting up to 8 bitflips per 512-byte block.
140 This will use 13 bytes of spare area per 512 bytes of page data. 140 This will use 13 bytes of spare area per 512 bytes of page data.
141 This is the recommended mode, as 4-bit mode does not work 141 This is the recommended mode, as 4-bit mode does not work
142 on some OMAP3 revisions, due to a hardware bug. 142 on some OMAP3 revisions, due to a hardware bug.
143 143
144 config MTD_NAND_OMAP_BCH4 144 config MTD_NAND_OMAP_BCH4
145 bool "4 bits / 512 bytes" 145 bool "4 bits / 512 bytes"
146 help 146 help
147 Support correcting up to 4 bitflips per 512-byte block. 147 Support correcting up to 4 bitflips per 512-byte block.
148 This will use 7 bytes of spare area per 512 bytes of page data. 148 This will use 7 bytes of spare area per 512 bytes of page data.
149 Note that this mode does not work on some OMAP3 revisions, due to a 149 Note that this mode does not work on some OMAP3 revisions, due to a
150 hardware bug. Please check your OMAP datasheet before selecting this 150 hardware bug. Please check your OMAP datasheet before selecting this
151 mode. 151 mode.
152 152
153 endchoice 153 endchoice
154 154
155 if MTD_NAND_OMAP_BCH 155 if MTD_NAND_OMAP_BCH
156 config BCH_CONST_M 156 config BCH_CONST_M
157 default 13 157 default 13
158 config BCH_CONST_T 158 config BCH_CONST_T
159 default 4 if MTD_NAND_OMAP_BCH4 159 default 4 if MTD_NAND_OMAP_BCH4
160 default 8 if MTD_NAND_OMAP_BCH8 160 default 8 if MTD_NAND_OMAP_BCH8
161 endif 161 endif
162 162
163 config MTD_NAND_IDS 163 config MTD_NAND_IDS
164 tristate 164 tristate
165 165
166 config MTD_NAND_RICOH 166 config MTD_NAND_RICOH
167 tristate "Ricoh xD card reader" 167 tristate "Ricoh xD card reader"
168 default n 168 default n
169 depends on PCI 169 depends on PCI
170 select MTD_SM_COMMON 170 select MTD_SM_COMMON
171 help 171 help
172 Enable support for Ricoh R5C852 xD card reader 172 Enable support for Ricoh R5C852 xD card reader
173 You also need to enable ether 173 You also need to enable ether
174 NAND SSFDC (SmartMedia) read only translation layer' or new 174 NAND SSFDC (SmartMedia) read only translation layer' or new
175 expermental, readwrite 175 expermental, readwrite
176 'SmartMedia/xD new translation layer' 176 'SmartMedia/xD new translation layer'
177 177
178 config MTD_NAND_AU1550 178 config MTD_NAND_AU1550
179 tristate "Au1550/1200 NAND support" 179 tristate "Au1550/1200 NAND support"
180 depends on MIPS_ALCHEMY 180 depends on MIPS_ALCHEMY
181 help 181 help
182 This enables the driver for the NAND flash controller on the 182 This enables the driver for the NAND flash controller on the
183 AMD/Alchemy 1550 SOC. 183 AMD/Alchemy 1550 SOC.
184 184
185 config MTD_NAND_BF5XX 185 config MTD_NAND_BF5XX
186 tristate "Blackfin on-chip NAND Flash Controller driver" 186 tristate "Blackfin on-chip NAND Flash Controller driver"
187 depends on BF54x || BF52x 187 depends on BF54x || BF52x
188 help 188 help
189 This enables the Blackfin on-chip NAND flash controller 189 This enables the Blackfin on-chip NAND flash controller
190 190
191 No board specific support is done by this driver, each board 191 No board specific support is done by this driver, each board
192 must advertise a platform_device for the driver to attach. 192 must advertise a platform_device for the driver to attach.
193 193
194 This driver can also be built as a module. If so, the module 194 This driver can also be built as a module. If so, the module
195 will be called bf5xx-nand. 195 will be called bf5xx-nand.
196 196
197 config MTD_NAND_BF5XX_HWECC 197 config MTD_NAND_BF5XX_HWECC
198 bool "BF5XX NAND Hardware ECC" 198 bool "BF5XX NAND Hardware ECC"
199 default y 199 default y
200 depends on MTD_NAND_BF5XX 200 depends on MTD_NAND_BF5XX
201 help 201 help
202 Enable the use of the BF5XX's internal ECC generator when 202 Enable the use of the BF5XX's internal ECC generator when
203 using NAND. 203 using NAND.
204 204
205 config MTD_NAND_BF5XX_BOOTROM_ECC 205 config MTD_NAND_BF5XX_BOOTROM_ECC
206 bool "Use Blackfin BootROM ECC Layout" 206 bool "Use Blackfin BootROM ECC Layout"
207 default n 207 default n
208 depends on MTD_NAND_BF5XX_HWECC 208 depends on MTD_NAND_BF5XX_HWECC
209 help 209 help
210 If you wish to modify NAND pages and allow the Blackfin on-chip 210 If you wish to modify NAND pages and allow the Blackfin on-chip
211 BootROM to boot from them, say Y here. This is only necessary 211 BootROM to boot from them, say Y here. This is only necessary
212 if you are booting U-Boot out of NAND and you wish to update 212 if you are booting U-Boot out of NAND and you wish to update
213 U-Boot from Linux' userspace. Otherwise, you should say N here. 213 U-Boot from Linux' userspace. Otherwise, you should say N here.
214 214
215 If unsure, say N. 215 If unsure, say N.
216 216
217 config MTD_NAND_RTC_FROM4 217 config MTD_NAND_RTC_FROM4
218 tristate "Renesas Flash ROM 4-slot interface board (FROM_BOARD4)" 218 tristate "Renesas Flash ROM 4-slot interface board (FROM_BOARD4)"
219 depends on SH_SOLUTION_ENGINE 219 depends on SH_SOLUTION_ENGINE
220 select REED_SOLOMON 220 select REED_SOLOMON
221 select REED_SOLOMON_DEC8 221 select REED_SOLOMON_DEC8
222 select BITREVERSE 222 select BITREVERSE
223 help 223 help
224 This enables the driver for the Renesas Technology AG-AND 224 This enables the driver for the Renesas Technology AG-AND
225 flash interface board (FROM_BOARD4) 225 flash interface board (FROM_BOARD4)
226 226
227 config MTD_NAND_PPCHAMELEONEVB 227 config MTD_NAND_PPCHAMELEONEVB
228 tristate "NAND Flash device on PPChameleonEVB board" 228 tristate "NAND Flash device on PPChameleonEVB board"
229 depends on PPCHAMELEONEVB && BROKEN 229 depends on PPCHAMELEONEVB && BROKEN
230 help 230 help
231 This enables the NAND flash driver on the PPChameleon EVB Board. 231 This enables the NAND flash driver on the PPChameleon EVB Board.
232 232
233 config MTD_NAND_S3C2410 233 config MTD_NAND_S3C2410
234 tristate "NAND Flash support for Samsung S3C SoCs" 234 tristate "NAND Flash support for Samsung S3C SoCs"
235 depends on ARCH_S3C24XX || ARCH_S3C64XX 235 depends on ARCH_S3C24XX || ARCH_S3C64XX
236 help 236 help
237 This enables the NAND flash controller on the S3C24xx and S3C64xx 237 This enables the NAND flash controller on the S3C24xx and S3C64xx
238 SoCs 238 SoCs
239 239
240 No board specific support is done by this driver, each board 240 No board specific support is done by this driver, each board
241 must advertise a platform_device for the driver to attach. 241 must advertise a platform_device for the driver to attach.
242 242
243 config MTD_NAND_S3C2410_DEBUG 243 config MTD_NAND_S3C2410_DEBUG
244 bool "Samsung S3C NAND driver debug" 244 bool "Samsung S3C NAND driver debug"
245 depends on MTD_NAND_S3C2410 245 depends on MTD_NAND_S3C2410
246 help 246 help
247 Enable debugging of the S3C NAND driver 247 Enable debugging of the S3C NAND driver
248 248
249 config MTD_NAND_S3C2410_HWECC 249 config MTD_NAND_S3C2410_HWECC
250 bool "Samsung S3C NAND Hardware ECC" 250 bool "Samsung S3C NAND Hardware ECC"
251 depends on MTD_NAND_S3C2410 251 depends on MTD_NAND_S3C2410
252 help 252 help
253 Enable the use of the controller's internal ECC generator when 253 Enable the use of the controller's internal ECC generator when
254 using NAND. Early versions of the chips have had problems with 254 using NAND. Early versions of the chips have had problems with
255 incorrect ECC generation, and if using these, the default of 255 incorrect ECC generation, and if using these, the default of
256 software ECC is preferable. 256 software ECC is preferable.
257 257
258 config MTD_NAND_NDFC 258 config MTD_NAND_NDFC
259 tristate "NDFC NanD Flash Controller" 259 tristate "NDFC NanD Flash Controller"
260 depends on 4xx 260 depends on 4xx
261 select MTD_NAND_ECC_SMC 261 select MTD_NAND_ECC_SMC
262 help 262 help
263 NDFC Nand Flash Controllers are integrated in IBM/AMCC's 4xx SoCs 263 NDFC Nand Flash Controllers are integrated in IBM/AMCC's 4xx SoCs
264 264
265 config MTD_NAND_S3C2410_CLKSTOP 265 config MTD_NAND_S3C2410_CLKSTOP
266 bool "Samsung S3C NAND IDLE clock stop" 266 bool "Samsung S3C NAND IDLE clock stop"
267 depends on MTD_NAND_S3C2410 267 depends on MTD_NAND_S3C2410
268 default n 268 default n
269 help 269 help
270 Stop the clock to the NAND controller when there is no chip 270 Stop the clock to the NAND controller when there is no chip
271 selected to save power. This will mean there is a small delay 271 selected to save power. This will mean there is a small delay
272 when the is NAND chip selected or released, but will save 272 when the is NAND chip selected or released, but will save
273 approximately 5mA of power when there is nothing happening. 273 approximately 5mA of power when there is nothing happening.
274 274
275 config MTD_NAND_DISKONCHIP 275 config MTD_NAND_DISKONCHIP
276 tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)" 276 tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)"
277 depends on EXPERIMENTAL 277 depends on EXPERIMENTAL
278 depends on HAS_IOMEM 278 depends on HAS_IOMEM
279 select REED_SOLOMON 279 select REED_SOLOMON
280 select REED_SOLOMON_DEC16 280 select REED_SOLOMON_DEC16
281 help 281 help
282 This is a reimplementation of M-Systems DiskOnChip 2000, 282 This is a reimplementation of M-Systems DiskOnChip 2000,
283 Millennium and Millennium Plus as a standard NAND device driver, 283 Millennium and Millennium Plus as a standard NAND device driver,
284 as opposed to the earlier self-contained MTD device drivers. 284 as opposed to the earlier self-contained MTD device drivers.
285 This should enable, among other things, proper JFFS2 operation on 285 This should enable, among other things, proper JFFS2 operation on
286 these devices. 286 these devices.
287 287
288 config MTD_NAND_DISKONCHIP_PROBE_ADVANCED 288 config MTD_NAND_DISKONCHIP_PROBE_ADVANCED
289 bool "Advanced detection options for DiskOnChip" 289 bool "Advanced detection options for DiskOnChip"
290 depends on MTD_NAND_DISKONCHIP 290 depends on MTD_NAND_DISKONCHIP
291 help 291 help
292 This option allows you to specify nonstandard address at which to 292 This option allows you to specify nonstandard address at which to
293 probe for a DiskOnChip, or to change the detection options. You 293 probe for a DiskOnChip, or to change the detection options. You
294 are unlikely to need any of this unless you are using LinuxBIOS. 294 are unlikely to need any of this unless you are using LinuxBIOS.
295 Say 'N'. 295 Say 'N'.
296 296
297 config MTD_NAND_DISKONCHIP_PROBE_ADDRESS 297 config MTD_NAND_DISKONCHIP_PROBE_ADDRESS
298 hex "Physical address of DiskOnChip" if MTD_NAND_DISKONCHIP_PROBE_ADVANCED 298 hex "Physical address of DiskOnChip" if MTD_NAND_DISKONCHIP_PROBE_ADVANCED
299 depends on MTD_NAND_DISKONCHIP 299 depends on MTD_NAND_DISKONCHIP
300 default "0" 300 default "0"
301 ---help--- 301 ---help---
302 By default, the probe for DiskOnChip devices will look for a 302 By default, the probe for DiskOnChip devices will look for a
303 DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000. 303 DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000.
304 This option allows you to specify a single address at which to probe 304 This option allows you to specify a single address at which to probe
305 for the device, which is useful if you have other devices in that 305 for the device, which is useful if you have other devices in that
306 range which get upset when they are probed. 306 range which get upset when they are probed.
307 307
308 (Note that on PowerPC, the normal probe will only check at 308 (Note that on PowerPC, the normal probe will only check at
309 0xE4000000.) 309 0xE4000000.)
310 310
311 Normally, you should leave this set to zero, to allow the probe at 311 Normally, you should leave this set to zero, to allow the probe at
312 the normal addresses. 312 the normal addresses.
313 313
314 config MTD_NAND_DISKONCHIP_PROBE_HIGH 314 config MTD_NAND_DISKONCHIP_PROBE_HIGH
315 bool "Probe high addresses" 315 bool "Probe high addresses"
316 depends on MTD_NAND_DISKONCHIP_PROBE_ADVANCED 316 depends on MTD_NAND_DISKONCHIP_PROBE_ADVANCED
317 help 317 help
318 By default, the probe for DiskOnChip devices will look for a 318 By default, the probe for DiskOnChip devices will look for a
319 DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000. 319 DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000.
320 This option changes to make it probe between 0xFFFC8000 and 320 This option changes to make it probe between 0xFFFC8000 and
321 0xFFFEE000. Unless you are using LinuxBIOS, this is unlikely to be 321 0xFFFEE000. Unless you are using LinuxBIOS, this is unlikely to be
322 useful to you. Say 'N'. 322 useful to you. Say 'N'.
323 323
324 config MTD_NAND_DISKONCHIP_BBTWRITE 324 config MTD_NAND_DISKONCHIP_BBTWRITE
325 bool "Allow BBT writes on DiskOnChip Millennium and 2000TSOP" 325 bool "Allow BBT writes on DiskOnChip Millennium and 2000TSOP"
326 depends on MTD_NAND_DISKONCHIP 326 depends on MTD_NAND_DISKONCHIP
327 help 327 help
328 On DiskOnChip devices shipped with the INFTL filesystem (Millennium 328 On DiskOnChip devices shipped with the INFTL filesystem (Millennium
329 and 2000 TSOP/Alon), Linux reserves some space at the end of the 329 and 2000 TSOP/Alon), Linux reserves some space at the end of the
330 device for the Bad Block Table (BBT). If you have existing INFTL 330 device for the Bad Block Table (BBT). If you have existing INFTL
331 data on your device (created by non-Linux tools such as M-Systems' 331 data on your device (created by non-Linux tools such as M-Systems'
332 DOS drivers), your data might overlap the area Linux wants to use for 332 DOS drivers), your data might overlap the area Linux wants to use for
333 the BBT. If this is a concern for you, leave this option disabled and 333 the BBT. If this is a concern for you, leave this option disabled and
334 Linux will not write BBT data into this area. 334 Linux will not write BBT data into this area.
335 The downside of leaving this option disabled is that if bad blocks 335 The downside of leaving this option disabled is that if bad blocks
336 are detected by Linux, they will not be recorded in the BBT, which 336 are detected by Linux, they will not be recorded in the BBT, which
337 could cause future problems. 337 could cause future problems.
338 Once you enable this option, new filesystems (INFTL or others, created 338 Once you enable this option, new filesystems (INFTL or others, created
339 in Linux or other operating systems) will not use the reserved area. 339 in Linux or other operating systems) will not use the reserved area.
340 The only reason not to enable this option is to prevent damage to 340 The only reason not to enable this option is to prevent damage to
341 preexisting filesystems. 341 preexisting filesystems.
342 Even if you leave this disabled, you can enable BBT writes at module 342 Even if you leave this disabled, you can enable BBT writes at module
343 load time (assuming you build diskonchip as a module) with the module 343 load time (assuming you build diskonchip as a module) with the module
344 parameter "inftl_bbt_write=1". 344 parameter "inftl_bbt_write=1".
345 345
346 config MTD_NAND_DOCG4 346 config MTD_NAND_DOCG4
347 tristate "Support for DiskOnChip G4 (EXPERIMENTAL)" 347 tristate "Support for DiskOnChip G4 (EXPERIMENTAL)"
348 depends on EXPERIMENTAL && HAS_IOMEM 348 depends on EXPERIMENTAL && HAS_IOMEM
349 select BCH 349 select BCH
350 select BITREVERSE 350 select BITREVERSE
351 help 351 help
352 Support for diskonchip G4 nand flash, found in various smartphones and 352 Support for diskonchip G4 nand flash, found in various smartphones and
353 PDAs, among them the Palm Treo680, HTC Prophet and Wizard, Toshiba 353 PDAs, among them the Palm Treo680, HTC Prophet and Wizard, Toshiba
354 Portege G900, Asus P526, and O2 XDA Zinc. 354 Portege G900, Asus P526, and O2 XDA Zinc.
355 355
356 With this driver you will be able to use UBI and create a ubifs on the 356 With this driver you will be able to use UBI and create a ubifs on the
357 device, so you may wish to consider enabling UBI and UBIFS as well. 357 device, so you may wish to consider enabling UBI and UBIFS as well.
358 358
359 These devices ship with the Mys/Sandisk SAFTL formatting, for which 359 These devices ship with the Mys/Sandisk SAFTL formatting, for which
360 there is currently no mtd parser, so you may want to use command line 360 there is currently no mtd parser, so you may want to use command line
361 partitioning to segregate write-protected blocks. On the Treo680, the 361 partitioning to segregate write-protected blocks. On the Treo680, the
362 first five erase blocks (256KiB each) are write-protected, followed 362 first five erase blocks (256KiB each) are write-protected, followed
363 by the block containing the saftl partition table. This is probably 363 by the block containing the saftl partition table. This is probably
364 typical. 364 typical.
365 365
366 config MTD_NAND_SHARPSL 366 config MTD_NAND_SHARPSL
367 tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)" 367 tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)"
368 depends on ARCH_PXA 368 depends on ARCH_PXA
369 369
370 config MTD_NAND_CAFE 370 config MTD_NAND_CAFE
371 tristate "NAND support for OLPC CAFÉ chip" 371 tristate "NAND support for OLPC CAFÉ chip"
372 depends on PCI 372 depends on PCI
373 select REED_SOLOMON 373 select REED_SOLOMON
374 select REED_SOLOMON_DEC16 374 select REED_SOLOMON_DEC16
375 help 375 help
376 Use NAND flash attached to the CAFÉ chip designed for the OLPC 376 Use NAND flash attached to the CAFÉ chip designed for the OLPC
377 laptop. 377 laptop.
378 378
379 config MTD_NAND_CS553X 379 config MTD_NAND_CS553X
380 tristate "NAND support for CS5535/CS5536 (AMD Geode companion chip)" 380 tristate "NAND support for CS5535/CS5536 (AMD Geode companion chip)"
381 depends on X86_32 381 depends on X86_32
382 help 382 help
383 The CS553x companion chips for the AMD Geode processor 383 The CS553x companion chips for the AMD Geode processor
384 include NAND flash controllers with built-in hardware ECC 384 include NAND flash controllers with built-in hardware ECC
385 capabilities; enabling this option will allow you to use 385 capabilities; enabling this option will allow you to use
386 these. The driver will check the MSRs to verify that the 386 these. The driver will check the MSRs to verify that the
387 controller is enabled for NAND, and currently requires that 387 controller is enabled for NAND, and currently requires that
388 the controller be in MMIO mode. 388 the controller be in MMIO mode.
389 389
390 If you say "m", the module will be called cs553x_nand. 390 If you say "m", the module will be called cs553x_nand.
391 391
392 config MTD_NAND_ATMEL 392 config MTD_NAND_ATMEL
393 tristate "Support for NAND Flash / SmartMedia on AT91 and AVR32" 393 tristate "Support for NAND Flash / SmartMedia on AT91 and AVR32"
394 depends on ARCH_AT91 || AVR32 394 depends on ARCH_AT91 || AVR32
395 help 395 help
396 Enables support for NAND Flash / Smart Media Card interface 396 Enables support for NAND Flash / Smart Media Card interface
397 on Atmel AT91 and AVR32 processors. 397 on Atmel AT91 and AVR32 processors.
398 398
399 config MTD_NAND_PXA3xx 399 config MTD_NAND_PXA3xx
400 tristate "Support for NAND flash devices on PXA3xx" 400 tristate "Support for NAND flash devices on PXA3xx"
401 depends on PXA3xx || ARCH_MMP 401 depends on PXA3xx || ARCH_MMP
402 help 402 help
403 This enables the driver for the NAND flash device found on 403 This enables the driver for the NAND flash device found on
404 PXA3xx processors 404 PXA3xx processors
405 405
406 config MTD_NAND_SLC_LPC32XX 406 config MTD_NAND_SLC_LPC32XX
407 tristate "NXP LPC32xx SLC Controller" 407 tristate "NXP LPC32xx SLC Controller"
408 depends on ARCH_LPC32XX 408 depends on ARCH_LPC32XX
409 help 409 help
410 Enables support for NXP's LPC32XX SLC (i.e. for Single Level Cell 410 Enables support for NXP's LPC32XX SLC (i.e. for Single Level Cell
411 chips) NAND controller. This is the default for the PHYTEC 3250 411 chips) NAND controller. This is the default for the PHYTEC 3250
412 reference board which contains a NAND256R3A2CZA6 chip. 412 reference board which contains a NAND256R3A2CZA6 chip.
413 413
414 Please check the actual NAND chip connected and its support 414 Please check the actual NAND chip connected and its support
415 by the SLC NAND controller. 415 by the SLC NAND controller.
416 416
417 config MTD_NAND_MLC_LPC32XX 417 config MTD_NAND_MLC_LPC32XX
418 tristate "NXP LPC32xx MLC Controller" 418 tristate "NXP LPC32xx MLC Controller"
419 depends on ARCH_LPC32XX 419 depends on ARCH_LPC32XX
420 help 420 help
421 Uses the LPC32XX MLC (i.e. for Multi Level Cell chips) NAND 421 Uses the LPC32XX MLC (i.e. for Multi Level Cell chips) NAND
422 controller. This is the default for the WORK92105 controller 422 controller. This is the default for the WORK92105 controller
423 board. 423 board.
424 424
425 Please check the actual NAND chip connected and its support 425 Please check the actual NAND chip connected and its support
426 by the MLC NAND controller. 426 by the MLC NAND controller.
427 427
428 config MTD_NAND_CM_X270 428 config MTD_NAND_CM_X270
429 tristate "Support for NAND Flash on CM-X270 modules" 429 tristate "Support for NAND Flash on CM-X270 modules"
430 depends on MACH_ARMCORE 430 depends on MACH_ARMCORE
431 431
432 config MTD_NAND_PASEMI 432 config MTD_NAND_PASEMI
433 tristate "NAND support for PA Semi PWRficient" 433 tristate "NAND support for PA Semi PWRficient"
434 depends on PPC_PASEMI 434 depends on PPC_PASEMI
435 help 435 help
436 Enables support for NAND Flash interface on PA Semi PWRficient 436 Enables support for NAND Flash interface on PA Semi PWRficient
437 based boards 437 based boards
438 438
439 config MTD_NAND_TMIO 439 config MTD_NAND_TMIO
440 tristate "NAND Flash device on Toshiba Mobile IO Controller" 440 tristate "NAND Flash device on Toshiba Mobile IO Controller"
441 depends on MFD_TMIO 441 depends on MFD_TMIO
442 help 442 help
443 Support for NAND flash connected to a Toshiba Mobile IO 443 Support for NAND flash connected to a Toshiba Mobile IO
444 Controller in some PDAs, including the Sharp SL6000x. 444 Controller in some PDAs, including the Sharp SL6000x.
445 445
446 config MTD_NAND_NANDSIM 446 config MTD_NAND_NANDSIM
447 tristate "Support for NAND Flash Simulator" 447 tristate "Support for NAND Flash Simulator"
448 help 448 help
449 The simulator may simulate various NAND flash chips for the 449 The simulator may simulate various NAND flash chips for the
450 MTD nand layer. 450 MTD nand layer.
451 451
452 config MTD_NAND_GPMI_NAND 452 config MTD_NAND_GPMI_NAND
453 tristate "GPMI NAND Flash Controller driver" 453 tristate "GPMI NAND Flash Controller driver"
454 depends on MTD_NAND && MXS_DMA 454 depends on MTD_NAND && MXS_DMA
455 help 455 help
456 Enables NAND Flash support for IMX23, IMX28 or IMX6. 456 Enables NAND Flash support for IMX23, IMX28 or IMX6.
457 The GPMI controller is very powerful, with the help of BCH 457 The GPMI controller is very powerful, with the help of BCH
458 module, it can do the hardware ECC. The GPMI supports several 458 module, it can do the hardware ECC. The GPMI supports several
459 NAND flashs at the same time. The GPMI may conflicts with other 459 NAND flashs at the same time. The GPMI may conflicts with other
460 block, such as SD card. So pay attention to it when you enable 460 block, such as SD card. So pay attention to it when you enable
461 the GPMI. 461 the GPMI.
462 462
463 config MTD_NAND_BCM47XXNFLASH 463 config MTD_NAND_BCM47XXNFLASH
464 tristate "R/O support for NAND flash on BCMA bus" 464 tristate "Support for NAND flash on BCM4706 BCMA bus"
465 depends on BCMA_NFLASH 465 depends on BCMA_NFLASH
466 help 466 help
467 BCMA bus can have various flash memories attached, they are 467 BCMA bus can have various flash memories attached, they are
468 registered by bcma as platform devices. This enables driver for 468 registered by bcma as platform devices. This enables driver for
469 NAND flash memories. For now only read mode for BCM4706 is 469 NAND flash memories. For now only BCM4706 is supported.
470 implemented.
471 470
472 config MTD_NAND_PLATFORM 471 config MTD_NAND_PLATFORM
473 tristate "Support for generic platform NAND driver" 472 tristate "Support for generic platform NAND driver"
474 depends on HAS_IOMEM 473 depends on HAS_IOMEM
475 help 474 help
476 This implements a generic NAND driver for on-SOC platform 475 This implements a generic NAND driver for on-SOC platform
477 devices. You will need to provide platform-specific functions 476 devices. You will need to provide platform-specific functions
478 via platform_data. 477 via platform_data.
479 478
480 config MTD_ALAUDA 479 config MTD_ALAUDA
481 tristate "MTD driver for Olympus MAUSB-10 and Fujifilm DPC-R1" 480 tristate "MTD driver for Olympus MAUSB-10 and Fujifilm DPC-R1"
482 depends on USB 481 depends on USB
483 help 482 help
484 These two (and possibly other) Alauda-based cardreaders for 483 These two (and possibly other) Alauda-based cardreaders for
485 SmartMedia and xD allow raw flash access. 484 SmartMedia and xD allow raw flash access.
486 485
487 config MTD_NAND_ORION 486 config MTD_NAND_ORION
488 tristate "NAND Flash support for Marvell Orion SoC" 487 tristate "NAND Flash support for Marvell Orion SoC"
489 depends on PLAT_ORION 488 depends on PLAT_ORION
490 help 489 help
491 This enables the NAND flash controller on Orion machines. 490 This enables the NAND flash controller on Orion machines.
492 491
493 No board specific support is done by this driver, each board 492 No board specific support is done by this driver, each board
494 must advertise a platform_device for the driver to attach. 493 must advertise a platform_device for the driver to attach.
495 494
496 config MTD_NAND_FSL_ELBC 495 config MTD_NAND_FSL_ELBC
497 tristate "NAND support for Freescale eLBC controllers" 496 tristate "NAND support for Freescale eLBC controllers"
498 depends on PPC_OF 497 depends on PPC_OF
499 select FSL_LBC 498 select FSL_LBC
500 help 499 help
501 Various Freescale chips, including the 8313, include a NAND Flash 500 Various Freescale chips, including the 8313, include a NAND Flash
502 Controller Module with built-in hardware ECC capabilities. 501 Controller Module with built-in hardware ECC capabilities.
503 Enabling this option will enable you to use this to control 502 Enabling this option will enable you to use this to control
504 external NAND devices. 503 external NAND devices.
505 504
506 config MTD_NAND_FSL_IFC 505 config MTD_NAND_FSL_IFC
507 tristate "NAND support for Freescale IFC controller" 506 tristate "NAND support for Freescale IFC controller"
508 depends on MTD_NAND && FSL_SOC 507 depends on MTD_NAND && FSL_SOC
509 select FSL_IFC 508 select FSL_IFC
510 help 509 help
511 Various Freescale chips e.g P1010, include a NAND Flash machine 510 Various Freescale chips e.g P1010, include a NAND Flash machine
512 with built-in hardware ECC capabilities. 511 with built-in hardware ECC capabilities.
513 Enabling this option will enable you to use this to control 512 Enabling this option will enable you to use this to control
514 external NAND devices. 513 external NAND devices.
515 514
516 config MTD_NAND_FSL_UPM 515 config MTD_NAND_FSL_UPM
517 tristate "Support for NAND on Freescale UPM" 516 tristate "Support for NAND on Freescale UPM"
518 depends on PPC_83xx || PPC_85xx 517 depends on PPC_83xx || PPC_85xx
519 select FSL_LBC 518 select FSL_LBC
520 help 519 help
521 Enables support for NAND Flash chips wired onto Freescale PowerPC 520 Enables support for NAND Flash chips wired onto Freescale PowerPC
522 processor localbus with User-Programmable Machine support. 521 processor localbus with User-Programmable Machine support.
523 522
524 config MTD_NAND_MPC5121_NFC 523 config MTD_NAND_MPC5121_NFC
525 tristate "MPC5121 built-in NAND Flash Controller support" 524 tristate "MPC5121 built-in NAND Flash Controller support"
526 depends on PPC_MPC512x 525 depends on PPC_MPC512x
527 help 526 help
528 This enables the driver for the NAND flash controller on the 527 This enables the driver for the NAND flash controller on the
529 MPC5121 SoC. 528 MPC5121 SoC.
530 529
531 config MTD_NAND_MXC 530 config MTD_NAND_MXC
532 tristate "MXC NAND support" 531 tristate "MXC NAND support"
533 depends on ARCH_MXC 532 depends on ARCH_MXC
534 help 533 help
535 This enables the driver for the NAND flash controller on the 534 This enables the driver for the NAND flash controller on the
536 MXC processors. 535 MXC processors.
537 536
538 config MTD_NAND_SH_FLCTL 537 config MTD_NAND_SH_FLCTL
539 tristate "Support for NAND on Renesas SuperH FLCTL" 538 tristate "Support for NAND on Renesas SuperH FLCTL"
540 depends on SUPERH || ARCH_SHMOBILE 539 depends on SUPERH || ARCH_SHMOBILE
541 help 540 help
542 Several Renesas SuperH CPU has FLCTL. This option enables support 541 Several Renesas SuperH CPU has FLCTL. This option enables support
543 for NAND Flash using FLCTL. 542 for NAND Flash using FLCTL.
544 543
545 config MTD_NAND_DAVINCI 544 config MTD_NAND_DAVINCI
546 tristate "Support NAND on DaVinci SoC" 545 tristate "Support NAND on DaVinci SoC"
547 depends on ARCH_DAVINCI 546 depends on ARCH_DAVINCI
548 help 547 help
549 Enable the driver for NAND flash chips on Texas Instruments 548 Enable the driver for NAND flash chips on Texas Instruments
550 DaVinci processors. 549 DaVinci processors.
551 550
552 config MTD_NAND_TXX9NDFMC 551 config MTD_NAND_TXX9NDFMC
553 tristate "NAND Flash support for TXx9 SoC" 552 tristate "NAND Flash support for TXx9 SoC"
554 depends on SOC_TX4938 || SOC_TX4939 553 depends on SOC_TX4938 || SOC_TX4939
555 help 554 help
556 This enables the NAND flash controller on the TXx9 SoCs. 555 This enables the NAND flash controller on the TXx9 SoCs.
557 556
558 config MTD_NAND_SOCRATES 557 config MTD_NAND_SOCRATES
559 tristate "Support for NAND on Socrates board" 558 tristate "Support for NAND on Socrates board"
560 depends on SOCRATES 559 depends on SOCRATES
561 help 560 help
562 Enables support for NAND Flash chips wired onto Socrates board. 561 Enables support for NAND Flash chips wired onto Socrates board.
563 562
564 config MTD_NAND_NUC900 563 config MTD_NAND_NUC900
565 tristate "Support for NAND on Nuvoton NUC9xx/w90p910 evaluation boards." 564 tristate "Support for NAND on Nuvoton NUC9xx/w90p910 evaluation boards."
566 depends on ARCH_W90X900 565 depends on ARCH_W90X900
567 help 566 help
568 This enables the driver for the NAND Flash on evaluation board based 567 This enables the driver for the NAND Flash on evaluation board based
569 on w90p910 / NUC9xx. 568 on w90p910 / NUC9xx.
570 569
571 config MTD_NAND_JZ4740 570 config MTD_NAND_JZ4740
572 tristate "Support for JZ4740 SoC NAND controller" 571 tristate "Support for JZ4740 SoC NAND controller"
573 depends on MACH_JZ4740 572 depends on MACH_JZ4740
574 help 573 help
575 Enables support for NAND Flash on JZ4740 SoC based boards. 574 Enables support for NAND Flash on JZ4740 SoC based boards.
576 575
577 config MTD_NAND_FSMC 576 config MTD_NAND_FSMC
578 tristate "Support for NAND on ST Micros FSMC" 577 tristate "Support for NAND on ST Micros FSMC"
579 depends on PLAT_SPEAR || PLAT_NOMADIK || MACH_U300 578 depends on PLAT_SPEAR || PLAT_NOMADIK || MACH_U300
580 help 579 help
581 Enables support for NAND Flash chips on the ST Microelectronics 580 Enables support for NAND Flash chips on the ST Microelectronics
582 Flexible Static Memory Controller (FSMC) 581 Flexible Static Memory Controller (FSMC)
583 582
584 config MTD_NAND_XWAY 583 config MTD_NAND_XWAY
585 tristate "Support for NAND on Lantiq XWAY SoC" 584 tristate "Support for NAND on Lantiq XWAY SoC"
586 depends on LANTIQ && SOC_TYPE_XWAY 585 depends on LANTIQ && SOC_TYPE_XWAY
587 select MTD_NAND_PLATFORM 586 select MTD_NAND_PLATFORM
588 help 587 help
589 Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached 588 Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
590 to the External Bus Unit (EBU). 589 to the External Bus Unit (EBU).
591 590
592 endif # MTD_NAND 591 endif # MTD_NAND
593 592
drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
Diff comments   View file @ ecfe57b
1 /* 1 /*
2 * BCM47XX NAND flash driver 2 * BCM47XX NAND flash driver
3 * 3 *
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> 4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 * 9 *
10 */ 10 */
11 11
12 #include <linux/module.h> 12 #include <linux/module.h>
13 #include <linux/kernel.h> 13 #include <linux/kernel.h>
14 #include <linux/slab.h> 14 #include <linux/slab.h>
15 #include <linux/bcma/bcma.h> 15 #include <linux/bcma/bcma.h>
16 16
17 #include "bcm47xxnflash.h" 17 #include "bcm47xxnflash.h"
18 18
19 /* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has 19 /* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has
20 * shown 164 retries as maxiumum. */ 20 * shown 164 retries as maxiumum. */
21 #define NFLASH_READY_RETRIES 1000 21 #define NFLASH_READY_RETRIES 1000
22 22
23 #define NFLASH_SECTOR_SIZE 512 23 #define NFLASH_SECTOR_SIZE 512
24 24
25 #define NCTL_CMD0 0x00010000 25 #define NCTL_CMD0 0x00010000
26 #define NCTL_CMD1W 0x00080000 26 #define NCTL_CMD1W 0x00080000
27 #define NCTL_READ 0x00100000 27 #define NCTL_READ 0x00100000
28 #define NCTL_WRITE 0x00200000
28 #define NCTL_SPECADDR 0x01000000 29 #define NCTL_SPECADDR 0x01000000
29 #define NCTL_READY 0x04000000 30 #define NCTL_READY 0x04000000
30 #define NCTL_ERR 0x08000000 31 #define NCTL_ERR 0x08000000
31 #define NCTL_CSA 0x40000000 32 #define NCTL_CSA 0x40000000
32 #define NCTL_START 0x80000000 33 #define NCTL_START 0x80000000
33 34
34 /************************************************** 35 /**************************************************
35 * Various helpers 36 * Various helpers
36 **************************************************/ 37 **************************************************/
37 38
38 static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock) 39 static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
39 { 40 {
40 return ((ns * 1000 * clock) / 1000000) + 1; 41 return ((ns * 1000 * clock) / 1000000) + 1;
41 } 42 }
42 43
43 static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code) 44 static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
44 { 45 {
45 int i = 0; 46 int i = 0;
46 47
47 bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, NCTL_START | code); 48 bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, NCTL_START | code);
48 for (i = 0; i < NFLASH_READY_RETRIES; i++) { 49 for (i = 0; i < NFLASH_READY_RETRIES; i++) {
49 if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_START)) { 50 if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_START)) {
50 i = 0; 51 i = 0;
51 break; 52 break;
52 } 53 }
53 } 54 }
54 if (i) { 55 if (i) {
55 pr_err("NFLASH control command not ready!\n"); 56 pr_err("NFLASH control command not ready!\n");
56 return -EBUSY; 57 return -EBUSY;
57 } 58 }
58 return 0; 59 return 0;
59 } 60 }
60 61
61 static int bcm47xxnflash_ops_bcm4706_poll(struct bcma_drv_cc *cc) 62 static int bcm47xxnflash_ops_bcm4706_poll(struct bcma_drv_cc *cc)
62 { 63 {
63 int i; 64 int i;
64 65
65 for (i = 0; i < NFLASH_READY_RETRIES; i++) { 66 for (i = 0; i < NFLASH_READY_RETRIES; i++) {
66 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_READY) { 67 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_READY) {
67 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & 68 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) &
68 BCMA_CC_NFLASH_CTL_ERR) { 69 BCMA_CC_NFLASH_CTL_ERR) {
69 pr_err("Error on polling\n"); 70 pr_err("Error on polling\n");
70 return -EBUSY; 71 return -EBUSY;
71 } else { 72 } else {
72 return 0; 73 return 0;
73 } 74 }
74 } 75 }
75 } 76 }
76 77
77 pr_err("Polling timeout!\n"); 78 pr_err("Polling timeout!\n");
78 return -EBUSY; 79 return -EBUSY;
79 } 80 }
80 81
81 /************************************************** 82 /**************************************************
82 * R/W 83 * R/W
83 **************************************************/ 84 **************************************************/
84 85
85 static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf, 86 static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,
86 int len) 87 int len)
87 { 88 {
88 struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv; 89 struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
89 struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv; 90 struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
90 91
91 u32 ctlcode; 92 u32 ctlcode;
92 u32 *dest = (u32 *)buf; 93 u32 *dest = (u32 *)buf;
93 int i; 94 int i;
94 int toread; 95 int toread;
95 96
96 BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask); 97 BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
97 /* Don't validate column using nand_chip->page_shift, it may be bigger 98 /* Don't validate column using nand_chip->page_shift, it may be bigger
98 * when accessing OOB */ 99 * when accessing OOB */
99 100
100 while (len) { 101 while (len) {
101 /* We can read maximum of 0x200 bytes at once */ 102 /* We can read maximum of 0x200 bytes at once */
102 toread = min(len, 0x200); 103 toread = min(len, 0x200);
103 104
104 /* Set page and column */ 105 /* Set page and column */
105 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_COL_ADDR, 106 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_COL_ADDR,
106 b47n->curr_column); 107 b47n->curr_column);
107 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_ROW_ADDR, 108 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_ROW_ADDR,
108 b47n->curr_page_addr); 109 b47n->curr_page_addr);
109 110
110 /* Prepare to read */ 111 /* Prepare to read */
111 ctlcode = NCTL_CSA | NCTL_CMD1W | 0x00040000 | 0x00020000 | 112 ctlcode = NCTL_CSA | NCTL_CMD1W | 0x00040000 | 0x00020000 |
112 NCTL_CMD0; 113 NCTL_CMD0;
113 ctlcode |= NAND_CMD_READSTART << 8; 114 ctlcode |= NAND_CMD_READSTART << 8;
114 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) 115 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode))
115 return; 116 return;
116 if (bcm47xxnflash_ops_bcm4706_poll(b47n->cc)) 117 if (bcm47xxnflash_ops_bcm4706_poll(b47n->cc))
117 return; 118 return;
118 119
119 /* Eventually read some data :) */ 120 /* Eventually read some data :) */
120 for (i = 0; i < toread; i += 4, dest++) { 121 for (i = 0; i < toread; i += 4, dest++) {
121 ctlcode = NCTL_CSA | 0x30000000 | NCTL_READ; 122 ctlcode = NCTL_CSA | 0x30000000 | NCTL_READ;
122 if (i == toread - 4) /* Last read goes without that */ 123 if (i == toread - 4) /* Last read goes without that */
123 ctlcode &= ~NCTL_CSA; 124 ctlcode &= ~NCTL_CSA;
124 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, 125 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
125 ctlcode)) 126 ctlcode))
126 return; 127 return;
127 *dest = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA); 128 *dest = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA);
128 } 129 }
129 130
130 b47n->curr_column += toread; 131 b47n->curr_column += toread;
131 len -= toread; 132 len -= toread;
132 } 133 }
133 } 134 }
134 135
136 static void bcm47xxnflash_ops_bcm4706_write(struct mtd_info *mtd,
137 const uint8_t *buf, int len)
138 {
139 struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
140 struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
141 struct bcma_drv_cc *cc = b47n->cc;
142
143 u32 ctlcode;
144 const u32 *data = (u32 *)buf;
145 int i;
146
147 BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
148 /* Don't validate column using nand_chip->page_shift, it may be bigger
149 * when accessing OOB */
150
151 for (i = 0; i < len; i += 4, data++) {
152 bcma_cc_write32(cc, BCMA_CC_NFLASH_DATA, *data);
153
154 ctlcode = NCTL_CSA | 0x30000000 | NCTL_WRITE;
155 if (i == len - 4) /* Last read goes without that */
156 ctlcode &= ~NCTL_CSA;
157 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode)) {
158 pr_err("%s ctl_cmd didn't work!\n", __func__);
159 return;
160 }
161 }
162
163 b47n->curr_column += len;
164 }
165
135 /************************************************** 166 /**************************************************
136 * NAND chip ops 167 * NAND chip ops
137 **************************************************/ 168 **************************************************/
138 169
139 /* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */ 170 /* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */
140 static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd, 171 static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd,
141 int chip) 172 int chip)
142 { 173 {
143 return; 174 return;
144 } 175 }
145 176
146 /* 177 /*
147 * Default nand_command and nand_command_lp don't match BCM4706 hardware layout. 178 * Default nand_command and nand_command_lp don't match BCM4706 hardware layout.
148 * For example, reading chip id is performed in a non-standard way. 179 * For example, reading chip id is performed in a non-standard way.
149 * Setting column and page is also handled differently, we use a special 180 * Setting column and page is also handled differently, we use a special
150 * registers of ChipCommon core. Hacking cmd_ctrl to understand and convert 181 * registers of ChipCommon core. Hacking cmd_ctrl to understand and convert
151 * standard commands would be much more complicated. 182 * standard commands would be much more complicated.
152 */ 183 */
153 static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd, 184 static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
154 unsigned command, int column, 185 unsigned command, int column,
155 int page_addr) 186 int page_addr)
156 { 187 {
157 struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv; 188 struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
158 struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv; 189 struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
159 struct bcma_drv_cc *cc = b47n->cc; 190 struct bcma_drv_cc *cc = b47n->cc;
160 u32 ctlcode; 191 u32 ctlcode;
161 int i; 192 int i;
162 193
163 if (column != -1) 194 if (column != -1)
164 b47n->curr_column = column; 195 b47n->curr_column = column;
165 if (page_addr != -1) 196 if (page_addr != -1)
166 b47n->curr_page_addr = page_addr; 197 b47n->curr_page_addr = page_addr;
167 198
168 switch (command) { 199 switch (command) {
169 case NAND_CMD_RESET: 200 case NAND_CMD_RESET:
170 pr_warn("Chip reset not implemented yet\n"); 201 pr_warn("Chip reset not implemented yet\n");
171 break; 202 break;
172 case NAND_CMD_READID: 203 case NAND_CMD_READID:
173 ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0; 204 ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0;
174 ctlcode |= NAND_CMD_READID; 205 ctlcode |= NAND_CMD_READID;
175 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) { 206 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) {
176 pr_err("READID error\n"); 207 pr_err("READID error\n");
177 break; 208 break;
178 } 209 }
179 210
180 /* 211 /*
181 * Reading is specific, last one has to go without NCTL_CSA 212 * Reading is specific, last one has to go without NCTL_CSA
182 * bit. We don't know how many reads NAND subsystem is going 213 * bit. We don't know how many reads NAND subsystem is going
183 * to perform, so cache everything. 214 * to perform, so cache everything.
184 */ 215 */
185 for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) { 216 for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) {
186 ctlcode = NCTL_CSA | NCTL_READ; 217 ctlcode = NCTL_CSA | NCTL_READ;
187 if (i == ARRAY_SIZE(b47n->id_data) - 1) 218 if (i == ARRAY_SIZE(b47n->id_data) - 1)
188 ctlcode &= ~NCTL_CSA; 219 ctlcode &= ~NCTL_CSA;
189 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, 220 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
190 ctlcode)) { 221 ctlcode)) {
191 pr_err("READID error\n"); 222 pr_err("READID error\n");
192 break; 223 break;
193 } 224 }
194 b47n->id_data[i] = 225 b47n->id_data[i] =
195 bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA) 226 bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA)
196 & 0xFF; 227 & 0xFF;
197 } 228 }
198 229
199 break; 230 break;
200 case NAND_CMD_STATUS: 231 case NAND_CMD_STATUS:
201 ctlcode = NCTL_CSA | NCTL_CMD0 | NAND_CMD_STATUS; 232 ctlcode = NCTL_CSA | NCTL_CMD0 | NAND_CMD_STATUS;
202 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode)) 233 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
203 pr_err("STATUS command error\n"); 234 pr_err("STATUS command error\n");
204 break; 235 break;
205 case NAND_CMD_READ0: 236 case NAND_CMD_READ0:
206 break; 237 break;
207 case NAND_CMD_READOOB: 238 case NAND_CMD_READOOB:
208 if (page_addr != -1) 239 if (page_addr != -1)
209 b47n->curr_column += mtd->writesize; 240 b47n->curr_column += mtd->writesize;
210 break; 241 break;
242 case NAND_CMD_ERASE1:
243 bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR,
244 b47n->curr_page_addr);
245 ctlcode = 0x00040000 | NCTL_CMD1W | NCTL_CMD0 |
246 NAND_CMD_ERASE1 | (NAND_CMD_ERASE2 << 8);
247 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
248 pr_err("ERASE1 failed\n");
249 break;
250 case NAND_CMD_ERASE2:
251 break;
252 case NAND_CMD_SEQIN:
253 /* Set page and column */
254 bcma_cc_write32(cc, BCMA_CC_NFLASH_COL_ADDR,
255 b47n->curr_column);
256 bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR,
257 b47n->curr_page_addr);
258
259 /* Prepare to write */
260 ctlcode = 0x40000000 | 0x00040000 | 0x00020000 | 0x00010000;
261 ctlcode |= NAND_CMD_SEQIN;
262 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
263 pr_err("SEQIN failed\n");
264 break;
265 case NAND_CMD_PAGEPROG:
266 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, 0x00010000 |
267 NAND_CMD_PAGEPROG))
268 pr_err("PAGEPROG failed\n");
269 if (bcm47xxnflash_ops_bcm4706_poll(cc))
270 pr_err("PAGEPROG not ready\n");
271 break;
211 default: 272 default:
212 pr_err("Command 0x%X unsupported\n", command); 273 pr_err("Command 0x%X unsupported\n", command);
213 break; 274 break;
214 } 275 }
215 b47n->curr_command = command; 276 b47n->curr_command = command;
216 } 277 }
217 278
218 static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd) 279 static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
219 { 280 {
220 struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv; 281 struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
221 struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv; 282 struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
222 struct bcma_drv_cc *cc = b47n->cc; 283 struct bcma_drv_cc *cc = b47n->cc;
223 u32 tmp = 0; 284 u32 tmp = 0;
224 285
225 switch (b47n->curr_command) { 286 switch (b47n->curr_command) {
226 case NAND_CMD_READID: 287 case NAND_CMD_READID:
227 if (b47n->curr_column >= ARRAY_SIZE(b47n->id_data)) { 288 if (b47n->curr_column >= ARRAY_SIZE(b47n->id_data)) {
228 pr_err("Requested invalid id_data: %d\n", 289 pr_err("Requested invalid id_data: %d\n",
229 b47n->curr_column); 290 b47n->curr_column);
230 return 0; 291 return 0;
231 } 292 }
232 return b47n->id_data[b47n->curr_column++]; 293 return b47n->id_data[b47n->curr_column++];
233 case NAND_CMD_STATUS: 294 case NAND_CMD_STATUS:
234 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, NCTL_READ)) 295 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, NCTL_READ))
235 return 0; 296 return 0;
236 return bcma_cc_read32(cc, BCMA_CC_NFLASH_DATA) & 0xff; 297 return bcma_cc_read32(cc, BCMA_CC_NFLASH_DATA) & 0xff;
237 case NAND_CMD_READOOB: 298 case NAND_CMD_READOOB:
238 bcm47xxnflash_ops_bcm4706_read(mtd, (u8 *)&tmp, 4); 299 bcm47xxnflash_ops_bcm4706_read(mtd, (u8 *)&tmp, 4);
239 return tmp & 0xFF; 300 return tmp & 0xFF;
240 } 301 }
241 302
242 pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command); 303 pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command);
243 return 0; 304 return 0;
244 } 305 }
245 306
246 static void bcm47xxnflash_ops_bcm4706_read_buf(struct mtd_info *mtd, 307 static void bcm47xxnflash_ops_bcm4706_read_buf(struct mtd_info *mtd,
247 uint8_t *buf, int len) 308 uint8_t *buf, int len)
248 { 309 {
249 struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv; 310 struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
250 struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv; 311 struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
251 312
252 switch (b47n->curr_command) { 313 switch (b47n->curr_command) {
253 case NAND_CMD_READ0: 314 case NAND_CMD_READ0:
254 case NAND_CMD_READOOB: 315 case NAND_CMD_READOOB:
255 bcm47xxnflash_ops_bcm4706_read(mtd, buf, len); 316 bcm47xxnflash_ops_bcm4706_read(mtd, buf, len);
256 return; 317 return;
257 } 318 }
258 319
259 pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command); 320 pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command);
260 } 321 }
261 322
323 static void bcm47xxnflash_ops_bcm4706_write_buf(struct mtd_info *mtd,
324 const uint8_t *buf, int len)
325 {
326 struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
327 struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
328
329 switch (b47n->curr_command) {
330 case NAND_CMD_SEQIN:
331 bcm47xxnflash_ops_bcm4706_write(mtd, buf, len);
332 return;
333 }
334
335 pr_err("Invalid command for buf write: 0x%X\n", b47n->curr_command);
336 }
337
262 /************************************************** 338 /**************************************************
263 * Init 339 * Init
264 **************************************************/ 340 **************************************************/
265 341
266 int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n) 342 int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
267 { 343 {
268 int err; 344 int err;
269 u32 freq; 345 u32 freq;
270 u16 clock; 346 u16 clock;
271 u8 w0, w1, w2, w3, w4; 347 u8 w0, w1, w2, w3, w4;
272 348
273 unsigned long chipsize; /* MiB */ 349 unsigned long chipsize; /* MiB */
274 u8 tbits, col_bits, col_size, row_bits, row_bsize; 350 u8 tbits, col_bits, col_size, row_bits, row_bsize;
275 u32 val; 351 u32 val;
276 352
277 b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip; 353 b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
278 b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc; 354 b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
279 b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte; 355 b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
280 b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf; 356 b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
357 b47n->nand_chip.write_buf = bcm47xxnflash_ops_bcm4706_write_buf;
281 b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH; 358 b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
282 b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */ 359 b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
283 360
284 /* Enable NAND flash access */ 361 /* Enable NAND flash access */
285 bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG, 362 bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
286 BCMA_CC_4706_FLASHSCFG_NF1); 363 BCMA_CC_4706_FLASHSCFG_NF1);
287 364
288 /* Configure wait counters */ 365 /* Configure wait counters */
289 if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) { 366 if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) {
290 freq = 100000000; 367 freq = 100000000;
291 } else { 368 } else {
292 freq = bcma_chipco_pll_read(b47n->cc, 4); 369 freq = bcma_chipco_pll_read(b47n->cc, 4);
293 freq = (freq * 0xFFF) >> 3; 370 freq = (freq * 0xFFF) >> 3;
294 freq = (freq * 25000000) >> 3; 371 freq = (freq * 25000000) >> 3;
295 } 372 }
296 clock = freq / 1000000; 373 clock = freq / 1000000;
297 w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock); 374 w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock);
298 w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock); 375 w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock);
299 w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock); 376 w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
300 w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock); 377 w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
301 w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock); 378 w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock);
302 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0, 379 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0,
303 (w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0)); 380 (w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
304 381
305 /* Scan NAND */ 382 /* Scan NAND */
306 err = nand_scan(&b47n->mtd, 1); 383 err = nand_scan(&b47n->mtd, 1);
307 if (err) { 384 if (err) {
308 pr_err("Could not scan NAND flash: %d\n", err); 385 pr_err("Could not scan NAND flash: %d\n", err);
309 goto exit; 386 goto exit;
310 } 387 }
311 388
312 /* Configure FLASH */ 389 /* Configure FLASH */
313 chipsize = b47n->nand_chip.chipsize >> 20; 390 chipsize = b47n->nand_chip.chipsize >> 20;
314 tbits = ffs(chipsize); /* find first bit set */ 391 tbits = ffs(chipsize); /* find first bit set */
315 if (!tbits || tbits != fls(chipsize)) { 392 if (!tbits || tbits != fls(chipsize)) {
316 pr_err("Invalid flash size: 0x%lX\n", chipsize); 393 pr_err("Invalid flash size: 0x%lX\n", chipsize);
317 err = -ENOTSUPP; 394 err = -ENOTSUPP;
318 goto exit; 395 goto exit;
319 } 396 }
320 tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */ 397 tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
321 398
322 col_bits = b47n->nand_chip.page_shift + 1; 399 col_bits = b47n->nand_chip.page_shift + 1;
323 col_size = (col_bits + 7) / 8; 400 col_size = (col_bits + 7) / 8;
324 401
325 row_bits = tbits - col_bits + 1; 402 row_bits = tbits - col_bits + 1;
326 row_bsize = (row_bits + 7) / 8; 403 row_bsize = (row_bits + 7) / 8;
327 404
328 val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2; 405 val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2;
329 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val); 406 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
330 407
331 exit: 408 exit:
332 if (err) 409 if (err)
333 bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG, 410 bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
334 ~BCMA_CC_4706_FLASHSCFG_NF1); 411 ~BCMA_CC_4706_FLASHSCFG_NF1);
335 return err; 412 return err;
336 } 413 }
337 414