Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit f17c13ca52d5c5a6a164536244a6debb8cd17983

Authored by Kuninori Morimoto
Committed by Mark Brown
1 parent d7c5762bc7
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

ASoC: sh: fsi: modify selection method of I2S/PCM/SPDIF format 

Current format selection of FSI-codecs depended on platform information for FSI,
and chip default settings for codecs. It is not understandable/formal method.
This patch modify FSI and FSI-codecs to use snd_soc_dai_set_fmt.

But FSI can use I2S/PCM and SPDIF format today.
It can be selected to I2S/PCM by snd_soc_dai_set_fmt, but can not select SPDIF.
So, this patch change FSI platform information to have DAI/SPDIF mode.

If platform selects DAI mode (default),
FSI-codecs can select I2S/PCM by snd_soc_dai_set_fmt,
and if it is SPDIF mode, FSI become SPDIF format.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

Showing 9 changed files with 84 additions and 126 deletions Inline Diff

arch/arm/mach-shmobile/board-ag5evm.c
Diff comments   View file @ f17c13c
1 /* 1 /*
2 * arch/arm/mach-shmobile/board-ag5evm.c 2 * arch/arm/mach-shmobile/board-ag5evm.c
3 * 3 *
4 * Copyright (C) 2010 Takashi Yoshii <yoshii.takashi.zj@renesas.com> 4 * Copyright (C) 2010 Takashi Yoshii <yoshii.takashi.zj@renesas.com>
5 * Copyright (C) 2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * Copyright (C) 2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License. 9 * the Free Software Foundation; version 2 of the License.
10 * 10 *
11 * This program is distributed in the hope that it will be useful, 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 * 15 *
16 * You should have received a copy of the GNU General Public License 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 * 19 *
20 */ 20 */
21 21
22 #include <linux/kernel.h> 22 #include <linux/kernel.h>
23 #include <linux/init.h> 23 #include <linux/init.h>
24 #include <linux/interrupt.h> 24 #include <linux/interrupt.h>
25 #include <linux/irq.h> 25 #include <linux/irq.h>
26 #include <linux/platform_device.h> 26 #include <linux/platform_device.h>
27 #include <linux/delay.h> 27 #include <linux/delay.h>
28 #include <linux/io.h> 28 #include <linux/io.h>
29 #include <linux/dma-mapping.h> 29 #include <linux/dma-mapping.h>
30 #include <linux/serial_sci.h> 30 #include <linux/serial_sci.h>
31 #include <linux/smsc911x.h> 31 #include <linux/smsc911x.h>
32 #include <linux/gpio.h> 32 #include <linux/gpio.h>
33 #include <linux/input.h> 33 #include <linux/input.h>
34 #include <linux/input/sh_keysc.h> 34 #include <linux/input/sh_keysc.h>
35 #include <linux/mmc/host.h> 35 #include <linux/mmc/host.h>
36 #include <linux/mmc/sh_mmcif.h> 36 #include <linux/mmc/sh_mmcif.h>
37 37
38 #include <sound/sh_fsi.h> 38 #include <sound/sh_fsi.h>
39 39
40 #include <mach/hardware.h> 40 #include <mach/hardware.h>
41 #include <mach/sh73a0.h> 41 #include <mach/sh73a0.h>
42 #include <mach/common.h> 42 #include <mach/common.h>
43 #include <asm/mach-types.h> 43 #include <asm/mach-types.h>
44 #include <asm/mach/arch.h> 44 #include <asm/mach/arch.h>
45 #include <asm/mach/map.h> 45 #include <asm/mach/map.h>
46 #include <asm/mach/time.h> 46 #include <asm/mach/time.h>
47 #include <asm/hardware/gic.h> 47 #include <asm/hardware/gic.h>
48 #include <asm/hardware/cache-l2x0.h> 48 #include <asm/hardware/cache-l2x0.h>
49 #include <asm/traps.h> 49 #include <asm/traps.h>
50 50
51 static struct resource smsc9220_resources[] = { 51 static struct resource smsc9220_resources[] = {
52 [0] = { 52 [0] = {
53 .start = 0x14000000, 53 .start = 0x14000000,
54 .end = 0x14000000 + SZ_64K - 1, 54 .end = 0x14000000 + SZ_64K - 1,
55 .flags = IORESOURCE_MEM, 55 .flags = IORESOURCE_MEM,
56 }, 56 },
57 [1] = { 57 [1] = {
58 .start = gic_spi(33), /* PINT1 */ 58 .start = gic_spi(33), /* PINT1 */
59 .flags = IORESOURCE_IRQ, 59 .flags = IORESOURCE_IRQ,
60 }, 60 },
61 }; 61 };
62 62
63 static struct smsc911x_platform_config smsc9220_platdata = { 63 static struct smsc911x_platform_config smsc9220_platdata = {
64 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, 64 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
65 .phy_interface = PHY_INTERFACE_MODE_MII, 65 .phy_interface = PHY_INTERFACE_MODE_MII,
66 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 66 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
67 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 67 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
68 }; 68 };
69 69
70 static struct platform_device eth_device = { 70 static struct platform_device eth_device = {
71 .name = "smsc911x", 71 .name = "smsc911x",
72 .id = 0, 72 .id = 0,
73 .dev = { 73 .dev = {
74 .platform_data = &smsc9220_platdata, 74 .platform_data = &smsc9220_platdata,
75 }, 75 },
76 .resource = smsc9220_resources, 76 .resource = smsc9220_resources,
77 .num_resources = ARRAY_SIZE(smsc9220_resources), 77 .num_resources = ARRAY_SIZE(smsc9220_resources),
78 }; 78 };
79 79
80 static struct sh_keysc_info keysc_platdata = { 80 static struct sh_keysc_info keysc_platdata = {
81 .mode = SH_KEYSC_MODE_6, 81 .mode = SH_KEYSC_MODE_6,
82 .scan_timing = 3, 82 .scan_timing = 3,
83 .delay = 100, 83 .delay = 100,
84 .keycodes = { 84 .keycodes = {
85 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G, 85 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G,
86 KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N, 86 KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N,
87 KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U, 87 KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U,
88 KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP, 88 KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP,
89 KEY_SPACE, KEY_9, KEY_6, KEY_3, KEY_WAKEUP, KEY_RIGHT, \ 89 KEY_SPACE, KEY_9, KEY_6, KEY_3, KEY_WAKEUP, KEY_RIGHT, \
90 KEY_COFFEE, 90 KEY_COFFEE,
91 KEY_0, KEY_8, KEY_5, KEY_2, KEY_DOWN, KEY_ENTER, KEY_UP, 91 KEY_0, KEY_8, KEY_5, KEY_2, KEY_DOWN, KEY_ENTER, KEY_UP,
92 KEY_KPASTERISK, KEY_7, KEY_4, KEY_1, KEY_STOP, KEY_LEFT, \ 92 KEY_KPASTERISK, KEY_7, KEY_4, KEY_1, KEY_STOP, KEY_LEFT, \
93 KEY_COMPUTER, 93 KEY_COMPUTER,
94 }, 94 },
95 }; 95 };
96 96
97 static struct resource keysc_resources[] = { 97 static struct resource keysc_resources[] = {
98 [0] = { 98 [0] = {
99 .name = "KEYSC", 99 .name = "KEYSC",
100 .start = 0xe61b0000, 100 .start = 0xe61b0000,
101 .end = 0xe61b0098 - 1, 101 .end = 0xe61b0098 - 1,
102 .flags = IORESOURCE_MEM, 102 .flags = IORESOURCE_MEM,
103 }, 103 },
104 [1] = { 104 [1] = {
105 .start = gic_spi(71), 105 .start = gic_spi(71),
106 .flags = IORESOURCE_IRQ, 106 .flags = IORESOURCE_IRQ,
107 }, 107 },
108 }; 108 };
109 109
110 static struct platform_device keysc_device = { 110 static struct platform_device keysc_device = {
111 .name = "sh_keysc", 111 .name = "sh_keysc",
112 .id = 0, 112 .id = 0,
113 .num_resources = ARRAY_SIZE(keysc_resources), 113 .num_resources = ARRAY_SIZE(keysc_resources),
114 .resource = keysc_resources, 114 .resource = keysc_resources,
115 .dev = { 115 .dev = {
116 .platform_data = &keysc_platdata, 116 .platform_data = &keysc_platdata,
117 }, 117 },
118 }; 118 };
119 119
120 /* FSI A */ 120 /* FSI A */
121 static struct sh_fsi_platform_info fsi_info = {
122 .porta_flags = SH_FSI_OFMT(I2S) |
123 SH_FSI_IFMT(I2S),
124 };
125
126 static struct resource fsi_resources[] = { 121 static struct resource fsi_resources[] = {
127 [0] = { 122 [0] = {
128 .name = "FSI", 123 .name = "FSI",
129 .start = 0xEC230000, 124 .start = 0xEC230000,
130 .end = 0xEC230400 - 1, 125 .end = 0xEC230400 - 1,
131 .flags = IORESOURCE_MEM, 126 .flags = IORESOURCE_MEM,
132 }, 127 },
133 [1] = { 128 [1] = {
134 .start = gic_spi(146), 129 .start = gic_spi(146),
135 .flags = IORESOURCE_IRQ, 130 .flags = IORESOURCE_IRQ,
136 }, 131 },
137 }; 132 };
138 133
139 static struct platform_device fsi_device = { 134 static struct platform_device fsi_device = {
140 .name = "sh_fsi2", 135 .name = "sh_fsi2",
141 .id = -1, 136 .id = -1,
142 .num_resources = ARRAY_SIZE(fsi_resources), 137 .num_resources = ARRAY_SIZE(fsi_resources),
143 .resource = fsi_resources, 138 .resource = fsi_resources,
144 .dev = {
145 .platform_data = &fsi_info,
146 },
147 }; 139 };
148 140
149 static struct resource sh_mmcif_resources[] = { 141 static struct resource sh_mmcif_resources[] = {
150 [0] = { 142 [0] = {
151 .name = "MMCIF", 143 .name = "MMCIF",
152 .start = 0xe6bd0000, 144 .start = 0xe6bd0000,
153 .end = 0xe6bd00ff, 145 .end = 0xe6bd00ff,
154 .flags = IORESOURCE_MEM, 146 .flags = IORESOURCE_MEM,
155 }, 147 },
156 [1] = { 148 [1] = {
157 .start = gic_spi(141), 149 .start = gic_spi(141),
158 .flags = IORESOURCE_IRQ, 150 .flags = IORESOURCE_IRQ,
159 }, 151 },
160 [2] = { 152 [2] = {
161 .start = gic_spi(140), 153 .start = gic_spi(140),
162 .flags = IORESOURCE_IRQ, 154 .flags = IORESOURCE_IRQ,
163 }, 155 },
164 }; 156 };
165 157
166 static struct sh_mmcif_plat_data sh_mmcif_platdata = { 158 static struct sh_mmcif_plat_data sh_mmcif_platdata = {
167 .sup_pclk = 0, 159 .sup_pclk = 0,
168 .ocr = MMC_VDD_165_195, 160 .ocr = MMC_VDD_165_195,
169 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, 161 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
170 }; 162 };
171 163
172 static struct platform_device mmc_device = { 164 static struct platform_device mmc_device = {
173 .name = "sh_mmcif", 165 .name = "sh_mmcif",
174 .id = 0, 166 .id = 0,
175 .dev = { 167 .dev = {
176 .dma_mask = NULL, 168 .dma_mask = NULL,
177 .coherent_dma_mask = 0xffffffff, 169 .coherent_dma_mask = 0xffffffff,
178 .platform_data = &sh_mmcif_platdata, 170 .platform_data = &sh_mmcif_platdata,
179 }, 171 },
180 .num_resources = ARRAY_SIZE(sh_mmcif_resources), 172 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
181 .resource = sh_mmcif_resources, 173 .resource = sh_mmcif_resources,
182 }; 174 };
183 175
184 static struct platform_device *ag5evm_devices[] __initdata = { 176 static struct platform_device *ag5evm_devices[] __initdata = {
185 &eth_device, 177 &eth_device,
186 &keysc_device, 178 &keysc_device,
187 &fsi_device, 179 &fsi_device,
188 &mmc_device, 180 &mmc_device,
189 }; 181 };
190 182
191 static struct map_desc ag5evm_io_desc[] __initdata = { 183 static struct map_desc ag5evm_io_desc[] __initdata = {
192 /* create a 1:1 entity map for 0xe6xxxxxx 184 /* create a 1:1 entity map for 0xe6xxxxxx
193 * used by CPGA, INTC and PFC. 185 * used by CPGA, INTC and PFC.
194 */ 186 */
195 { 187 {
196 .virtual = 0xe6000000, 188 .virtual = 0xe6000000,
197 .pfn = __phys_to_pfn(0xe6000000), 189 .pfn = __phys_to_pfn(0xe6000000),
198 .length = 256 << 20, 190 .length = 256 << 20,
199 .type = MT_DEVICE_NONSHARED 191 .type = MT_DEVICE_NONSHARED
200 }, 192 },
201 }; 193 };
202 194
203 static void __init ag5evm_map_io(void) 195 static void __init ag5evm_map_io(void)
204 { 196 {
205 iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc)); 197 iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc));
206 198
207 /* setup early devices and console here as well */ 199 /* setup early devices and console here as well */
208 sh73a0_add_early_devices(); 200 sh73a0_add_early_devices();
209 shmobile_setup_console(); 201 shmobile_setup_console();
210 } 202 }
211 203
212 #define PINTC_ADDR 0xe6900000 204 #define PINTC_ADDR 0xe6900000
213 #define PINTER0A (PINTC_ADDR + 0xa0) 205 #define PINTER0A (PINTC_ADDR + 0xa0)
214 #define PINTCR0A (PINTC_ADDR + 0xb0) 206 #define PINTCR0A (PINTC_ADDR + 0xb0)
215 207
216 void __init ag5evm_init_irq(void) 208 void __init ag5evm_init_irq(void)
217 { 209 {
218 sh73a0_init_irq(); 210 sh73a0_init_irq();
219 211
220 /* setup PINT: enable PINTA2 as active low */ 212 /* setup PINT: enable PINTA2 as active low */
221 __raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A); 213 __raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A);
222 __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A); 214 __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A);
223 } 215 }
224 216
225 static void __init ag5evm_init(void) 217 static void __init ag5evm_init(void)
226 { 218 {
227 sh73a0_pinmux_init(); 219 sh73a0_pinmux_init();
228 220
229 /* enable SCIFA2 */ 221 /* enable SCIFA2 */
230 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); 222 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
231 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); 223 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
232 gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL); 224 gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
233 gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL); 225 gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
234 226
235 /* enable KEYSC */ 227 /* enable KEYSC */
236 gpio_request(GPIO_FN_KEYIN0_PU, NULL); 228 gpio_request(GPIO_FN_KEYIN0_PU, NULL);
237 gpio_request(GPIO_FN_KEYIN1_PU, NULL); 229 gpio_request(GPIO_FN_KEYIN1_PU, NULL);
238 gpio_request(GPIO_FN_KEYIN2_PU, NULL); 230 gpio_request(GPIO_FN_KEYIN2_PU, NULL);
239 gpio_request(GPIO_FN_KEYIN3_PU, NULL); 231 gpio_request(GPIO_FN_KEYIN3_PU, NULL);
240 gpio_request(GPIO_FN_KEYIN4_PU, NULL); 232 gpio_request(GPIO_FN_KEYIN4_PU, NULL);
241 gpio_request(GPIO_FN_KEYIN5_PU, NULL); 233 gpio_request(GPIO_FN_KEYIN5_PU, NULL);
242 gpio_request(GPIO_FN_KEYIN6_PU, NULL); 234 gpio_request(GPIO_FN_KEYIN6_PU, NULL);
243 gpio_request(GPIO_FN_KEYIN7_PU, NULL); 235 gpio_request(GPIO_FN_KEYIN7_PU, NULL);
244 gpio_request(GPIO_FN_KEYOUT0, NULL); 236 gpio_request(GPIO_FN_KEYOUT0, NULL);
245 gpio_request(GPIO_FN_KEYOUT1, NULL); 237 gpio_request(GPIO_FN_KEYOUT1, NULL);
246 gpio_request(GPIO_FN_KEYOUT2, NULL); 238 gpio_request(GPIO_FN_KEYOUT2, NULL);
247 gpio_request(GPIO_FN_KEYOUT3, NULL); 239 gpio_request(GPIO_FN_KEYOUT3, NULL);
248 gpio_request(GPIO_FN_KEYOUT4, NULL); 240 gpio_request(GPIO_FN_KEYOUT4, NULL);
249 gpio_request(GPIO_FN_KEYOUT5, NULL); 241 gpio_request(GPIO_FN_KEYOUT5, NULL);
250 gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL); 242 gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
251 gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL); 243 gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
252 gpio_request(GPIO_FN_KEYOUT8, NULL); 244 gpio_request(GPIO_FN_KEYOUT8, NULL);
253 gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL); 245 gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
254 246
255 /* enable I2C channel 2 and 3 */ 247 /* enable I2C channel 2 and 3 */
256 gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); 248 gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
257 gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); 249 gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
258 gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL); 250 gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
259 gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL); 251 gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
260 252
261 /* enable MMCIF */ 253 /* enable MMCIF */
262 gpio_request(GPIO_FN_MMCCLK0, NULL); 254 gpio_request(GPIO_FN_MMCCLK0, NULL);
263 gpio_request(GPIO_FN_MMCCMD0_PU, NULL); 255 gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
264 gpio_request(GPIO_FN_MMCD0_0, NULL); 256 gpio_request(GPIO_FN_MMCD0_0, NULL);
265 gpio_request(GPIO_FN_MMCD0_1, NULL); 257 gpio_request(GPIO_FN_MMCD0_1, NULL);
266 gpio_request(GPIO_FN_MMCD0_2, NULL); 258 gpio_request(GPIO_FN_MMCD0_2, NULL);
267 gpio_request(GPIO_FN_MMCD0_3, NULL); 259 gpio_request(GPIO_FN_MMCD0_3, NULL);
268 gpio_request(GPIO_FN_MMCD0_4, NULL); 260 gpio_request(GPIO_FN_MMCD0_4, NULL);
269 gpio_request(GPIO_FN_MMCD0_5, NULL); 261 gpio_request(GPIO_FN_MMCD0_5, NULL);
270 gpio_request(GPIO_FN_MMCD0_6, NULL); 262 gpio_request(GPIO_FN_MMCD0_6, NULL);
271 gpio_request(GPIO_FN_MMCD0_7, NULL); 263 gpio_request(GPIO_FN_MMCD0_7, NULL);
272 gpio_request(GPIO_PORT208, NULL); /* Reset */ 264 gpio_request(GPIO_PORT208, NULL); /* Reset */
273 gpio_direction_output(GPIO_PORT208, 1); 265 gpio_direction_output(GPIO_PORT208, 1);
274 266
275 /* enable SMSC911X */ 267 /* enable SMSC911X */
276 gpio_request(GPIO_PORT144, NULL); /* PINTA2 */ 268 gpio_request(GPIO_PORT144, NULL); /* PINTA2 */
277 gpio_direction_input(GPIO_PORT144); 269 gpio_direction_input(GPIO_PORT144);
278 gpio_request(GPIO_PORT145, NULL); /* RESET */ 270 gpio_request(GPIO_PORT145, NULL); /* RESET */
279 gpio_direction_output(GPIO_PORT145, 1); 271 gpio_direction_output(GPIO_PORT145, 1);
280 272
281 /* FSI A */ 273 /* FSI A */
282 gpio_request(GPIO_FN_FSIACK, NULL); 274 gpio_request(GPIO_FN_FSIACK, NULL);
283 gpio_request(GPIO_FN_FSIAILR, NULL); 275 gpio_request(GPIO_FN_FSIAILR, NULL);
284 gpio_request(GPIO_FN_FSIAIBT, NULL); 276 gpio_request(GPIO_FN_FSIAIBT, NULL);
285 gpio_request(GPIO_FN_FSIAISLD, NULL); 277 gpio_request(GPIO_FN_FSIAISLD, NULL);
286 gpio_request(GPIO_FN_FSIAOSLD, NULL); 278 gpio_request(GPIO_FN_FSIAOSLD, NULL);
287 279
288 #ifdef CONFIG_CACHE_L2X0 280 #ifdef CONFIG_CACHE_L2X0
289 /* Shared attribute override enable, 64K*8way */ 281 /* Shared attribute override enable, 64K*8way */
290 l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff); 282 l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
291 #endif 283 #endif
292 sh73a0_add_standard_devices(); 284 sh73a0_add_standard_devices();
293 platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices)); 285 platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));
294 } 286 }
295 287
296 static void __init ag5evm_timer_init(void) 288 static void __init ag5evm_timer_init(void)
297 { 289 {
298 sh73a0_clock_init(); 290 sh73a0_clock_init();
299 shmobile_timer.init(); 291 shmobile_timer.init();
300 return; 292 return;
301 } 293 }
302 294
303 struct sys_timer ag5evm_timer = { 295 struct sys_timer ag5evm_timer = {
304 .init = ag5evm_timer_init, 296 .init = ag5evm_timer_init,
305 }; 297 };
306 298
307 MACHINE_START(AG5EVM, "ag5evm") 299 MACHINE_START(AG5EVM, "ag5evm")
308 .map_io = ag5evm_map_io, 300 .map_io = ag5evm_map_io,
309 .init_irq = ag5evm_init_irq, 301 .init_irq = ag5evm_init_irq,
310 .handle_irq = shmobile_handle_irq_gic, 302 .handle_irq = shmobile_handle_irq_gic,
311 .init_machine = ag5evm_init, 303 .init_machine = ag5evm_init,
312 .timer = &ag5evm_timer, 304 .timer = &ag5evm_timer,
313 MACHINE_END 305 MACHINE_END
314 306
arch/arm/mach-shmobile/board-ap4evb.c
Diff comments   View file @ f17c13c
1 /* 1 /*
2 * AP4EVB board support 2 * AP4EVB board support
3 * 3 *
4 * Copyright (C) 2010 Magnus Damm 4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda 5 * Copyright (C) 2008 Yoshihiro Shimoda
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License. 9 * the Free Software Foundation; version 2 of the License.
10 * 10 *
11 * This program is distributed in the hope that it will be useful, 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 * 15 *
16 * You should have received a copy of the GNU General Public License 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 #include <linux/clk.h> 20 #include <linux/clk.h>
21 #include <linux/kernel.h> 21 #include <linux/kernel.h>
22 #include <linux/init.h> 22 #include <linux/init.h>
23 #include <linux/interrupt.h> 23 #include <linux/interrupt.h>
24 #include <linux/irq.h> 24 #include <linux/irq.h>
25 #include <linux/platform_device.h> 25 #include <linux/platform_device.h>
26 #include <linux/delay.h> 26 #include <linux/delay.h>
27 #include <linux/mfd/sh_mobile_sdhi.h> 27 #include <linux/mfd/sh_mobile_sdhi.h>
28 #include <linux/mfd/tmio.h> 28 #include <linux/mfd/tmio.h>
29 #include <linux/mmc/host.h> 29 #include <linux/mmc/host.h>
30 #include <linux/mtd/mtd.h> 30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/partitions.h> 31 #include <linux/mtd/partitions.h>
32 #include <linux/mtd/physmap.h> 32 #include <linux/mtd/physmap.h>
33 #include <linux/mmc/sh_mmcif.h> 33 #include <linux/mmc/sh_mmcif.h>
34 #include <linux/i2c.h> 34 #include <linux/i2c.h>
35 #include <linux/i2c/tsc2007.h> 35 #include <linux/i2c/tsc2007.h>
36 #include <linux/io.h> 36 #include <linux/io.h>
37 #include <linux/smsc911x.h> 37 #include <linux/smsc911x.h>
38 #include <linux/sh_intc.h> 38 #include <linux/sh_intc.h>
39 #include <linux/sh_clk.h> 39 #include <linux/sh_clk.h>
40 #include <linux/gpio.h> 40 #include <linux/gpio.h>
41 #include <linux/input.h> 41 #include <linux/input.h>
42 #include <linux/leds.h> 42 #include <linux/leds.h>
43 #include <linux/input/sh_keysc.h> 43 #include <linux/input/sh_keysc.h>
44 #include <linux/usb/r8a66597.h> 44 #include <linux/usb/r8a66597.h>
45 45
46 #include <media/sh_mobile_ceu.h> 46 #include <media/sh_mobile_ceu.h>
47 #include <media/sh_mobile_csi2.h> 47 #include <media/sh_mobile_csi2.h>
48 #include <media/soc_camera.h> 48 #include <media/soc_camera.h>
49 49
50 #include <sound/sh_fsi.h> 50 #include <sound/sh_fsi.h>
51 51
52 #include <video/sh_mobile_hdmi.h> 52 #include <video/sh_mobile_hdmi.h>
53 #include <video/sh_mobile_lcdc.h> 53 #include <video/sh_mobile_lcdc.h>
54 #include <video/sh_mipi_dsi.h> 54 #include <video/sh_mipi_dsi.h>
55 55
56 #include <mach/common.h> 56 #include <mach/common.h>
57 #include <mach/irqs.h> 57 #include <mach/irqs.h>
58 #include <mach/sh7372.h> 58 #include <mach/sh7372.h>
59 59
60 #include <asm/mach-types.h> 60 #include <asm/mach-types.h>
61 #include <asm/mach/arch.h> 61 #include <asm/mach/arch.h>
62 #include <asm/mach/map.h> 62 #include <asm/mach/map.h>
63 #include <asm/mach/time.h> 63 #include <asm/mach/time.h>
64 #include <asm/setup.h> 64 #include <asm/setup.h>
65 65
66 /* 66 /*
67 * Address Interface BusWidth note 67 * Address Interface BusWidth note
68 * ------------------------------------------------------------------ 68 * ------------------------------------------------------------------
69 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON 69 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON
70 * 0x0800_0000 user area - 70 * 0x0800_0000 user area -
71 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF 71 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF
72 * 0x1400_0000 Ether (LAN9220) 16bit 72 * 0x1400_0000 Ether (LAN9220) 16bit
73 * 0x1600_0000 user area - cannot use with NAND 73 * 0x1600_0000 user area - cannot use with NAND
74 * 0x1800_0000 user area - 74 * 0x1800_0000 user area -
75 * 0x1A00_0000 - 75 * 0x1A00_0000 -
76 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit 76 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit
77 */ 77 */
78 78
79 /* 79 /*
80 * NOR Flash ROM 80 * NOR Flash ROM
81 * 81 *
82 * SW1 | SW2 | SW7 | NOR Flash ROM 82 * SW1 | SW2 | SW7 | NOR Flash ROM
83 * bit1 | bit1 bit2 | bit1 | Memory allocation 83 * bit1 | bit1 bit2 | bit1 | Memory allocation
84 * ------+------------+------+------------------ 84 * ------+------------+------+------------------
85 * OFF | ON OFF | ON | Area 0 85 * OFF | ON OFF | ON | Area 0
86 * OFF | ON OFF | OFF | Area 4 86 * OFF | ON OFF | OFF | Area 4
87 */ 87 */
88 88
89 /* 89 /*
90 * NAND Flash ROM 90 * NAND Flash ROM
91 * 91 *
92 * SW1 | SW2 | SW7 | NAND Flash ROM 92 * SW1 | SW2 | SW7 | NAND Flash ROM
93 * bit1 | bit1 bit2 | bit2 | Memory allocation 93 * bit1 | bit1 bit2 | bit2 | Memory allocation
94 * ------+------------+------+------------------ 94 * ------+------------+------+------------------
95 * OFF | ON OFF | ON | FCE 0 95 * OFF | ON OFF | ON | FCE 0
96 * OFF | ON OFF | OFF | FCE 1 96 * OFF | ON OFF | OFF | FCE 1
97 */ 97 */
98 98
99 /* 99 /*
100 * SMSC 9220 100 * SMSC 9220
101 * 101 *
102 * SW1 SMSC 9220 102 * SW1 SMSC 9220
103 * ----------------------- 103 * -----------------------
104 * ON access disable 104 * ON access disable
105 * OFF access enable 105 * OFF access enable
106 */ 106 */
107 107
108 /* 108 /*
109 * LCD / IRQ / KEYSC / IrDA 109 * LCD / IRQ / KEYSC / IrDA
110 * 110 *
111 * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen) 111 * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen)
112 * LCD = 2nd LCDC (WVGA) 112 * LCD = 2nd LCDC (WVGA)
113 * 113 *
114 * | SW43 | 114 * | SW43 |
115 * SW3 | ON | OFF | 115 * SW3 | ON | OFF |
116 * -------------+-----------------------+---------------+ 116 * -------------+-----------------------+---------------+
117 * ON | KEY / IrDA | LCD | 117 * ON | KEY / IrDA | LCD |
118 * OFF | KEY / IrDA / IRQ | IRQ | 118 * OFF | KEY / IrDA / IRQ | IRQ |
119 * 119 *
120 * 120 *
121 * QHD / WVGA display 121 * QHD / WVGA display
122 * 122 *
123 * You can choice display type on menuconfig. 123 * You can choice display type on menuconfig.
124 * Then, check above dip-switch. 124 * Then, check above dip-switch.
125 */ 125 */
126 126
127 /* 127 /*
128 * USB 128 * USB
129 * 129 *
130 * J7 : 1-2 MAX3355E VBUS 130 * J7 : 1-2 MAX3355E VBUS
131 * 2-3 DC 5.0V 131 * 2-3 DC 5.0V
132 * 132 *
133 * S39: bit2: off 133 * S39: bit2: off
134 */ 134 */
135 135
136 /* 136 /*
137 * FSI/FSMI 137 * FSI/FSMI
138 * 138 *
139 * SW41 : ON : SH-Mobile AP4 Audio Mode 139 * SW41 : ON : SH-Mobile AP4 Audio Mode
140 * : OFF : Bluetooth Audio Mode 140 * : OFF : Bluetooth Audio Mode
141 */ 141 */
142 142
143 /* 143 /*
144 * MMC0/SDHI1 (CN7) 144 * MMC0/SDHI1 (CN7)
145 * 145 *
146 * J22 : select card voltage 146 * J22 : select card voltage
147 * 1-2 pin : 1.8v 147 * 1-2 pin : 1.8v
148 * 2-3 pin : 3.3v 148 * 2-3 pin : 3.3v
149 * 149 *
150 * SW1 | SW33 150 * SW1 | SW33
151 * | bit1 | bit2 | bit3 | bit4 151 * | bit1 | bit2 | bit3 | bit4
152 * ------------+------+------+------+------- 152 * ------------+------+------+------+-------
153 * MMC0 OFF | OFF | ON | ON | X 153 * MMC0 OFF | OFF | ON | ON | X
154 * SDHI1 OFF | ON | X | OFF | ON 154 * SDHI1 OFF | ON | X | OFF | ON
155 * 155 *
156 * voltage lebel 156 * voltage lebel
157 * CN7 : 1.8v 157 * CN7 : 1.8v
158 * CN12: 3.3v 158 * CN12: 3.3v
159 */ 159 */
160 160
161 /* MTD */ 161 /* MTD */
162 static struct mtd_partition nor_flash_partitions[] = { 162 static struct mtd_partition nor_flash_partitions[] = {
163 { 163 {
164 .name = "loader", 164 .name = "loader",
165 .offset = 0x00000000, 165 .offset = 0x00000000,
166 .size = 512 * 1024, 166 .size = 512 * 1024,
167 .mask_flags = MTD_WRITEABLE, 167 .mask_flags = MTD_WRITEABLE,
168 }, 168 },
169 { 169 {
170 .name = "bootenv", 170 .name = "bootenv",
171 .offset = MTDPART_OFS_APPEND, 171 .offset = MTDPART_OFS_APPEND,
172 .size = 512 * 1024, 172 .size = 512 * 1024,
173 .mask_flags = MTD_WRITEABLE, 173 .mask_flags = MTD_WRITEABLE,
174 }, 174 },
175 { 175 {
176 .name = "kernel_ro", 176 .name = "kernel_ro",
177 .offset = MTDPART_OFS_APPEND, 177 .offset = MTDPART_OFS_APPEND,
178 .size = 8 * 1024 * 1024, 178 .size = 8 * 1024 * 1024,
179 .mask_flags = MTD_WRITEABLE, 179 .mask_flags = MTD_WRITEABLE,
180 }, 180 },
181 { 181 {
182 .name = "kernel", 182 .name = "kernel",
183 .offset = MTDPART_OFS_APPEND, 183 .offset = MTDPART_OFS_APPEND,
184 .size = 8 * 1024 * 1024, 184 .size = 8 * 1024 * 1024,
185 }, 185 },
186 { 186 {
187 .name = "data", 187 .name = "data",
188 .offset = MTDPART_OFS_APPEND, 188 .offset = MTDPART_OFS_APPEND,
189 .size = MTDPART_SIZ_FULL, 189 .size = MTDPART_SIZ_FULL,
190 }, 190 },
191 }; 191 };
192 192
193 static struct physmap_flash_data nor_flash_data = { 193 static struct physmap_flash_data nor_flash_data = {
194 .width = 2, 194 .width = 2,
195 .parts = nor_flash_partitions, 195 .parts = nor_flash_partitions,
196 .nr_parts = ARRAY_SIZE(nor_flash_partitions), 196 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
197 }; 197 };
198 198
199 static struct resource nor_flash_resources[] = { 199 static struct resource nor_flash_resources[] = {
200 [0] = { 200 [0] = {
201 .start = 0x00000000, 201 .start = 0x00000000,
202 .end = 0x08000000 - 1, 202 .end = 0x08000000 - 1,
203 .flags = IORESOURCE_MEM, 203 .flags = IORESOURCE_MEM,
204 } 204 }
205 }; 205 };
206 206
207 static struct platform_device nor_flash_device = { 207 static struct platform_device nor_flash_device = {
208 .name = "physmap-flash", 208 .name = "physmap-flash",
209 .dev = { 209 .dev = {
210 .platform_data = &nor_flash_data, 210 .platform_data = &nor_flash_data,
211 }, 211 },
212 .num_resources = ARRAY_SIZE(nor_flash_resources), 212 .num_resources = ARRAY_SIZE(nor_flash_resources),
213 .resource = nor_flash_resources, 213 .resource = nor_flash_resources,
214 }; 214 };
215 215
216 /* SMSC 9220 */ 216 /* SMSC 9220 */
217 static struct resource smc911x_resources[] = { 217 static struct resource smc911x_resources[] = {
218 { 218 {
219 .start = 0x14000000, 219 .start = 0x14000000,
220 .end = 0x16000000 - 1, 220 .end = 0x16000000 - 1,
221 .flags = IORESOURCE_MEM, 221 .flags = IORESOURCE_MEM,
222 }, { 222 }, {
223 .start = evt2irq(0x02c0) /* IRQ6A */, 223 .start = evt2irq(0x02c0) /* IRQ6A */,
224 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 224 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
225 }, 225 },
226 }; 226 };
227 227
228 static struct smsc911x_platform_config smsc911x_info = { 228 static struct smsc911x_platform_config smsc911x_info = {
229 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS, 229 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
230 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 230 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
231 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 231 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
232 }; 232 };
233 233
234 static struct platform_device smc911x_device = { 234 static struct platform_device smc911x_device = {
235 .name = "smsc911x", 235 .name = "smsc911x",
236 .id = -1, 236 .id = -1,
237 .num_resources = ARRAY_SIZE(smc911x_resources), 237 .num_resources = ARRAY_SIZE(smc911x_resources),
238 .resource = smc911x_resources, 238 .resource = smc911x_resources,
239 .dev = { 239 .dev = {
240 .platform_data = &smsc911x_info, 240 .platform_data = &smsc911x_info,
241 }, 241 },
242 }; 242 };
243 243
244 /* 244 /*
245 * The card detect pin of the top SD/MMC slot (CN7) is active low and is 245 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
246 * connected to GPIO A22 of SH7372 (GPIO_PORT41). 246 * connected to GPIO A22 of SH7372 (GPIO_PORT41).
247 */ 247 */
248 static int slot_cn7_get_cd(struct platform_device *pdev) 248 static int slot_cn7_get_cd(struct platform_device *pdev)
249 { 249 {
250 return !gpio_get_value(GPIO_PORT41); 250 return !gpio_get_value(GPIO_PORT41);
251 } 251 }
252 252
253 /* SH_MMCIF */ 253 /* SH_MMCIF */
254 static struct resource sh_mmcif_resources[] = { 254 static struct resource sh_mmcif_resources[] = {
255 [0] = { 255 [0] = {
256 .name = "MMCIF", 256 .name = "MMCIF",
257 .start = 0xE6BD0000, 257 .start = 0xE6BD0000,
258 .end = 0xE6BD00FF, 258 .end = 0xE6BD00FF,
259 .flags = IORESOURCE_MEM, 259 .flags = IORESOURCE_MEM,
260 }, 260 },
261 [1] = { 261 [1] = {
262 /* MMC ERR */ 262 /* MMC ERR */
263 .start = evt2irq(0x1ac0), 263 .start = evt2irq(0x1ac0),
264 .flags = IORESOURCE_IRQ, 264 .flags = IORESOURCE_IRQ,
265 }, 265 },
266 [2] = { 266 [2] = {
267 /* MMC NOR */ 267 /* MMC NOR */
268 .start = evt2irq(0x1ae0), 268 .start = evt2irq(0x1ae0),
269 .flags = IORESOURCE_IRQ, 269 .flags = IORESOURCE_IRQ,
270 }, 270 },
271 }; 271 };
272 272
273 static struct sh_mmcif_dma sh_mmcif_dma = { 273 static struct sh_mmcif_dma sh_mmcif_dma = {
274 .chan_priv_rx = { 274 .chan_priv_rx = {
275 .slave_id = SHDMA_SLAVE_MMCIF_RX, 275 .slave_id = SHDMA_SLAVE_MMCIF_RX,
276 }, 276 },
277 .chan_priv_tx = { 277 .chan_priv_tx = {
278 .slave_id = SHDMA_SLAVE_MMCIF_TX, 278 .slave_id = SHDMA_SLAVE_MMCIF_TX,
279 }, 279 },
280 }; 280 };
281 281
282 static struct sh_mmcif_plat_data sh_mmcif_plat = { 282 static struct sh_mmcif_plat_data sh_mmcif_plat = {
283 .sup_pclk = 0, 283 .sup_pclk = 0,
284 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 284 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
285 .caps = MMC_CAP_4_BIT_DATA | 285 .caps = MMC_CAP_4_BIT_DATA |
286 MMC_CAP_8_BIT_DATA | 286 MMC_CAP_8_BIT_DATA |
287 MMC_CAP_NEEDS_POLL, 287 MMC_CAP_NEEDS_POLL,
288 .get_cd = slot_cn7_get_cd, 288 .get_cd = slot_cn7_get_cd,
289 .dma = &sh_mmcif_dma, 289 .dma = &sh_mmcif_dma,
290 }; 290 };
291 291
292 static struct platform_device sh_mmcif_device = { 292 static struct platform_device sh_mmcif_device = {
293 .name = "sh_mmcif", 293 .name = "sh_mmcif",
294 .id = 0, 294 .id = 0,
295 .dev = { 295 .dev = {
296 .dma_mask = NULL, 296 .dma_mask = NULL,
297 .coherent_dma_mask = 0xffffffff, 297 .coherent_dma_mask = 0xffffffff,
298 .platform_data = &sh_mmcif_plat, 298 .platform_data = &sh_mmcif_plat,
299 }, 299 },
300 .num_resources = ARRAY_SIZE(sh_mmcif_resources), 300 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
301 .resource = sh_mmcif_resources, 301 .resource = sh_mmcif_resources,
302 }; 302 };
303 303
304 /* SDHI0 */ 304 /* SDHI0 */
305 static struct sh_mobile_sdhi_info sdhi0_info = { 305 static struct sh_mobile_sdhi_info sdhi0_info = {
306 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 306 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
307 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 307 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
308 .tmio_caps = MMC_CAP_SDIO_IRQ, 308 .tmio_caps = MMC_CAP_SDIO_IRQ,
309 }; 309 };
310 310
311 static struct resource sdhi0_resources[] = { 311 static struct resource sdhi0_resources[] = {
312 [0] = { 312 [0] = {
313 .name = "SDHI0", 313 .name = "SDHI0",
314 .start = 0xe6850000, 314 .start = 0xe6850000,
315 .end = 0xe68501ff, 315 .end = 0xe68501ff,
316 .flags = IORESOURCE_MEM, 316 .flags = IORESOURCE_MEM,
317 }, 317 },
318 [1] = { 318 [1] = {
319 .start = evt2irq(0x0e00) /* SDHI0 */, 319 .start = evt2irq(0x0e00) /* SDHI0 */,
320 .flags = IORESOURCE_IRQ, 320 .flags = IORESOURCE_IRQ,
321 }, 321 },
322 }; 322 };
323 323
324 static struct platform_device sdhi0_device = { 324 static struct platform_device sdhi0_device = {
325 .name = "sh_mobile_sdhi", 325 .name = "sh_mobile_sdhi",
326 .num_resources = ARRAY_SIZE(sdhi0_resources), 326 .num_resources = ARRAY_SIZE(sdhi0_resources),
327 .resource = sdhi0_resources, 327 .resource = sdhi0_resources,
328 .id = 0, 328 .id = 0,
329 .dev = { 329 .dev = {
330 .platform_data = &sdhi0_info, 330 .platform_data = &sdhi0_info,
331 }, 331 },
332 }; 332 };
333 333
334 /* SDHI1 */ 334 /* SDHI1 */
335 static struct sh_mobile_sdhi_info sdhi1_info = { 335 static struct sh_mobile_sdhi_info sdhi1_info = {
336 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, 336 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
337 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, 337 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
338 .tmio_ocr_mask = MMC_VDD_165_195, 338 .tmio_ocr_mask = MMC_VDD_165_195,
339 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, 339 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
340 .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ, 340 .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
341 .get_cd = slot_cn7_get_cd, 341 .get_cd = slot_cn7_get_cd,
342 }; 342 };
343 343
344 static struct resource sdhi1_resources[] = { 344 static struct resource sdhi1_resources[] = {
345 [0] = { 345 [0] = {
346 .name = "SDHI1", 346 .name = "SDHI1",
347 .start = 0xe6860000, 347 .start = 0xe6860000,
348 .end = 0xe68601ff, 348 .end = 0xe68601ff,
349 .flags = IORESOURCE_MEM, 349 .flags = IORESOURCE_MEM,
350 }, 350 },
351 [1] = { 351 [1] = {
352 .start = evt2irq(0x0e80), 352 .start = evt2irq(0x0e80),
353 .flags = IORESOURCE_IRQ, 353 .flags = IORESOURCE_IRQ,
354 }, 354 },
355 }; 355 };
356 356
357 static struct platform_device sdhi1_device = { 357 static struct platform_device sdhi1_device = {
358 .name = "sh_mobile_sdhi", 358 .name = "sh_mobile_sdhi",
359 .num_resources = ARRAY_SIZE(sdhi1_resources), 359 .num_resources = ARRAY_SIZE(sdhi1_resources),
360 .resource = sdhi1_resources, 360 .resource = sdhi1_resources,
361 .id = 1, 361 .id = 1,
362 .dev = { 362 .dev = {
363 .platform_data = &sdhi1_info, 363 .platform_data = &sdhi1_info,
364 }, 364 },
365 }; 365 };
366 366
367 /* USB1 */ 367 /* USB1 */
368 static void usb1_host_port_power(int port, int power) 368 static void usb1_host_port_power(int port, int power)
369 { 369 {
370 if (!power) /* only power-on supported for now */ 370 if (!power) /* only power-on supported for now */
371 return; 371 return;
372 372
373 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */ 373 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
374 __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008); 374 __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
375 } 375 }
376 376
377 static struct r8a66597_platdata usb1_host_data = { 377 static struct r8a66597_platdata usb1_host_data = {
378 .on_chip = 1, 378 .on_chip = 1,
379 .port_power = usb1_host_port_power, 379 .port_power = usb1_host_port_power,
380 }; 380 };
381 381
382 static struct resource usb1_host_resources[] = { 382 static struct resource usb1_host_resources[] = {
383 [0] = { 383 [0] = {
384 .name = "USBHS", 384 .name = "USBHS",
385 .start = 0xE68B0000, 385 .start = 0xE68B0000,
386 .end = 0xE68B00E6 - 1, 386 .end = 0xE68B00E6 - 1,
387 .flags = IORESOURCE_MEM, 387 .flags = IORESOURCE_MEM,
388 }, 388 },
389 [1] = { 389 [1] = {
390 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */, 390 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
391 .flags = IORESOURCE_IRQ, 391 .flags = IORESOURCE_IRQ,
392 }, 392 },
393 }; 393 };
394 394
395 static struct platform_device usb1_host_device = { 395 static struct platform_device usb1_host_device = {
396 .name = "r8a66597_hcd", 396 .name = "r8a66597_hcd",
397 .id = 1, 397 .id = 1,
398 .dev = { 398 .dev = {
399 .dma_mask = NULL, /* not use dma */ 399 .dma_mask = NULL, /* not use dma */
400 .coherent_dma_mask = 0xffffffff, 400 .coherent_dma_mask = 0xffffffff,
401 .platform_data = &usb1_host_data, 401 .platform_data = &usb1_host_data,
402 }, 402 },
403 .num_resources = ARRAY_SIZE(usb1_host_resources), 403 .num_resources = ARRAY_SIZE(usb1_host_resources),
404 .resource = usb1_host_resources, 404 .resource = usb1_host_resources,
405 }; 405 };
406 406
407 const static struct fb_videomode ap4evb_lcdc_modes[] = { 407 const static struct fb_videomode ap4evb_lcdc_modes[] = {
408 { 408 {
409 #ifdef CONFIG_AP4EVB_QHD 409 #ifdef CONFIG_AP4EVB_QHD
410 .name = "R63302(QHD)", 410 .name = "R63302(QHD)",
411 .xres = 544, 411 .xres = 544,
412 .yres = 961, 412 .yres = 961,
413 .left_margin = 72, 413 .left_margin = 72,
414 .right_margin = 600, 414 .right_margin = 600,
415 .hsync_len = 16, 415 .hsync_len = 16,
416 .upper_margin = 8, 416 .upper_margin = 8,
417 .lower_margin = 8, 417 .lower_margin = 8,
418 .vsync_len = 2, 418 .vsync_len = 2,
419 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, 419 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
420 #else 420 #else
421 .name = "WVGA Panel", 421 .name = "WVGA Panel",
422 .xres = 800, 422 .xres = 800,
423 .yres = 480, 423 .yres = 480,
424 .left_margin = 220, 424 .left_margin = 220,
425 .right_margin = 110, 425 .right_margin = 110,
426 .hsync_len = 70, 426 .hsync_len = 70,
427 .upper_margin = 20, 427 .upper_margin = 20,
428 .lower_margin = 5, 428 .lower_margin = 5,
429 .vsync_len = 5, 429 .vsync_len = 5,
430 .sync = 0, 430 .sync = 0,
431 #endif 431 #endif
432 }, 432 },
433 }; 433 };
434 434
435 static struct sh_mobile_lcdc_info lcdc_info = { 435 static struct sh_mobile_lcdc_info lcdc_info = {
436 .ch[0] = { 436 .ch[0] = {
437 .chan = LCDC_CHAN_MAINLCD, 437 .chan = LCDC_CHAN_MAINLCD,
438 .bpp = 16, 438 .bpp = 16,
439 .lcd_cfg = ap4evb_lcdc_modes, 439 .lcd_cfg = ap4evb_lcdc_modes,
440 .num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes), 440 .num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
441 } 441 }
442 }; 442 };
443 443
444 static struct resource lcdc_resources[] = { 444 static struct resource lcdc_resources[] = {
445 [0] = { 445 [0] = {
446 .name = "LCDC", 446 .name = "LCDC",
447 .start = 0xfe940000, /* P4-only space */ 447 .start = 0xfe940000, /* P4-only space */
448 .end = 0xfe943fff, 448 .end = 0xfe943fff,
449 .flags = IORESOURCE_MEM, 449 .flags = IORESOURCE_MEM,
450 }, 450 },
451 [1] = { 451 [1] = {
452 .start = intcs_evt2irq(0x580), 452 .start = intcs_evt2irq(0x580),
453 .flags = IORESOURCE_IRQ, 453 .flags = IORESOURCE_IRQ,
454 }, 454 },
455 }; 455 };
456 456
457 static struct platform_device lcdc_device = { 457 static struct platform_device lcdc_device = {
458 .name = "sh_mobile_lcdc_fb", 458 .name = "sh_mobile_lcdc_fb",
459 .num_resources = ARRAY_SIZE(lcdc_resources), 459 .num_resources = ARRAY_SIZE(lcdc_resources),
460 .resource = lcdc_resources, 460 .resource = lcdc_resources,
461 .dev = { 461 .dev = {
462 .platform_data = &lcdc_info, 462 .platform_data = &lcdc_info,
463 .coherent_dma_mask = ~0, 463 .coherent_dma_mask = ~0,
464 }, 464 },
465 }; 465 };
466 466
467 /* 467 /*
468 * QHD display 468 * QHD display
469 */ 469 */
470 #ifdef CONFIG_AP4EVB_QHD 470 #ifdef CONFIG_AP4EVB_QHD
471 471
472 /* KEYSC (Needs SW43 set to ON) */ 472 /* KEYSC (Needs SW43 set to ON) */
473 static struct sh_keysc_info keysc_info = { 473 static struct sh_keysc_info keysc_info = {
474 .mode = SH_KEYSC_MODE_1, 474 .mode = SH_KEYSC_MODE_1,
475 .scan_timing = 3, 475 .scan_timing = 3,
476 .delay = 2500, 476 .delay = 2500,
477 .keycodes = { 477 .keycodes = {
478 KEY_0, KEY_1, KEY_2, KEY_3, KEY_4, 478 KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
479 KEY_5, KEY_6, KEY_7, KEY_8, KEY_9, 479 KEY_5, KEY_6, KEY_7, KEY_8, KEY_9,
480 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, 480 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
481 KEY_F, KEY_G, KEY_H, KEY_I, KEY_J, 481 KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
482 KEY_K, KEY_L, KEY_M, KEY_N, KEY_O, 482 KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
483 }, 483 },
484 }; 484 };
485 485
486 static struct resource keysc_resources[] = { 486 static struct resource keysc_resources[] = {
487 [0] = { 487 [0] = {
488 .name = "KEYSC", 488 .name = "KEYSC",
489 .start = 0xe61b0000, 489 .start = 0xe61b0000,
490 .end = 0xe61b0063, 490 .end = 0xe61b0063,
491 .flags = IORESOURCE_MEM, 491 .flags = IORESOURCE_MEM,
492 }, 492 },
493 [1] = { 493 [1] = {
494 .start = evt2irq(0x0be0), /* KEYSC_KEY */ 494 .start = evt2irq(0x0be0), /* KEYSC_KEY */
495 .flags = IORESOURCE_IRQ, 495 .flags = IORESOURCE_IRQ,
496 }, 496 },
497 }; 497 };
498 498
499 static struct platform_device keysc_device = { 499 static struct platform_device keysc_device = {
500 .name = "sh_keysc", 500 .name = "sh_keysc",
501 .id = 0, /* "keysc0" clock */ 501 .id = 0, /* "keysc0" clock */
502 .num_resources = ARRAY_SIZE(keysc_resources), 502 .num_resources = ARRAY_SIZE(keysc_resources),
503 .resource = keysc_resources, 503 .resource = keysc_resources,
504 .dev = { 504 .dev = {
505 .platform_data = &keysc_info, 505 .platform_data = &keysc_info,
506 }, 506 },
507 }; 507 };
508 508
509 /* MIPI-DSI */ 509 /* MIPI-DSI */
510 static struct resource mipidsi0_resources[] = { 510 static struct resource mipidsi0_resources[] = {
511 [0] = { 511 [0] = {
512 .start = 0xffc60000, 512 .start = 0xffc60000,
513 .end = 0xffc63073, 513 .end = 0xffc63073,
514 .flags = IORESOURCE_MEM, 514 .flags = IORESOURCE_MEM,
515 }, 515 },
516 [1] = { 516 [1] = {
517 .start = 0xffc68000, 517 .start = 0xffc68000,
518 .end = 0xffc680ef, 518 .end = 0xffc680ef,
519 .flags = IORESOURCE_MEM, 519 .flags = IORESOURCE_MEM,
520 }, 520 },
521 }; 521 };
522 522
523 static struct sh_mipi_dsi_info mipidsi0_info = { 523 static struct sh_mipi_dsi_info mipidsi0_info = {
524 .data_format = MIPI_RGB888, 524 .data_format = MIPI_RGB888,
525 .lcd_chan = &lcdc_info.ch[0], 525 .lcd_chan = &lcdc_info.ch[0],
526 .vsynw_offset = 17, 526 .vsynw_offset = 17,
527 }; 527 };
528 528
529 static struct platform_device mipidsi0_device = { 529 static struct platform_device mipidsi0_device = {
530 .name = "sh-mipi-dsi", 530 .name = "sh-mipi-dsi",
531 .num_resources = ARRAY_SIZE(mipidsi0_resources), 531 .num_resources = ARRAY_SIZE(mipidsi0_resources),
532 .resource = mipidsi0_resources, 532 .resource = mipidsi0_resources,
533 .id = 0, 533 .id = 0,
534 .dev = { 534 .dev = {
535 .platform_data = &mipidsi0_info, 535 .platform_data = &mipidsi0_info,
536 }, 536 },
537 }; 537 };
538 538
539 static struct platform_device *qhd_devices[] __initdata = { 539 static struct platform_device *qhd_devices[] __initdata = {
540 &mipidsi0_device, 540 &mipidsi0_device,
541 &keysc_device, 541 &keysc_device,
542 }; 542 };
543 #endif /* CONFIG_AP4EVB_QHD */ 543 #endif /* CONFIG_AP4EVB_QHD */
544 544
545 /* FSI */ 545 /* FSI */
546 #define IRQ_FSI evt2irq(0x1840) 546 #define IRQ_FSI evt2irq(0x1840)
547 static int __fsi_set_rate(struct clk *clk, long rate, int enable) 547 static int __fsi_set_rate(struct clk *clk, long rate, int enable)
548 { 548 {
549 int ret = 0; 549 int ret = 0;
550 550
551 if (rate <= 0) 551 if (rate <= 0)
552 return ret; 552 return ret;
553 553
554 if (enable) { 554 if (enable) {
555 ret = clk_set_rate(clk, rate); 555 ret = clk_set_rate(clk, rate);
556 if (0 == ret) 556 if (0 == ret)
557 ret = clk_enable(clk); 557 ret = clk_enable(clk);
558 } else { 558 } else {
559 clk_disable(clk); 559 clk_disable(clk);
560 } 560 }
561 561
562 return ret; 562 return ret;
563 } 563 }
564 564
565 static int __fsi_set_round_rate(struct clk *clk, long rate, int enable) 565 static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
566 { 566 {
567 return __fsi_set_rate(clk, clk_round_rate(clk, rate), enable); 567 return __fsi_set_rate(clk, clk_round_rate(clk, rate), enable);
568 } 568 }
569 569
570 static int fsi_ak4642_set_rate(struct device *dev, int rate, int enable) 570 static int fsi_ak4642_set_rate(struct device *dev, int rate, int enable)
571 { 571 {
572 struct clk *fsia_ick; 572 struct clk *fsia_ick;
573 struct clk *fsiack; 573 struct clk *fsiack;
574 int ret = -EIO; 574 int ret = -EIO;
575 575
576 fsia_ick = clk_get(dev, "icka"); 576 fsia_ick = clk_get(dev, "icka");
577 if (IS_ERR(fsia_ick)) 577 if (IS_ERR(fsia_ick))
578 return PTR_ERR(fsia_ick); 578 return PTR_ERR(fsia_ick);
579 579
580 /* 580 /*
581 * FSIACK is connected to AK4642, 581 * FSIACK is connected to AK4642,
582 * and use external clock pin from it. 582 * and use external clock pin from it.
583 * it is parent of fsia_ick now. 583 * it is parent of fsia_ick now.
584 */ 584 */
585 fsiack = clk_get_parent(fsia_ick); 585 fsiack = clk_get_parent(fsia_ick);
586 if (!fsiack) 586 if (!fsiack)
587 goto fsia_ick_out; 587 goto fsia_ick_out;
588 588
589 /* 589 /*
590 * we get 1/1 divided clock by setting same rate to fsiack and fsia_ick 590 * we get 1/1 divided clock by setting same rate to fsiack and fsia_ick
591 * 591 *
592 ** FIXME ** 592 ** FIXME **
593 * Because the freq_table of external clk (fsiack) are all 0, 593 * Because the freq_table of external clk (fsiack) are all 0,
594 * the return value of clk_round_rate became 0. 594 * the return value of clk_round_rate became 0.
595 * So, it use __fsi_set_rate here. 595 * So, it use __fsi_set_rate here.
596 */ 596 */
597 ret = __fsi_set_rate(fsiack, rate, enable); 597 ret = __fsi_set_rate(fsiack, rate, enable);
598 if (ret < 0) 598 if (ret < 0)
599 goto fsiack_out; 599 goto fsiack_out;
600 600
601 ret = __fsi_set_round_rate(fsia_ick, rate, enable); 601 ret = __fsi_set_round_rate(fsia_ick, rate, enable);
602 if ((ret < 0) && enable) 602 if ((ret < 0) && enable)
603 __fsi_set_round_rate(fsiack, rate, 0); /* disable FSI ACK */ 603 __fsi_set_round_rate(fsiack, rate, 0); /* disable FSI ACK */
604 604
605 fsiack_out: 605 fsiack_out:
606 clk_put(fsiack); 606 clk_put(fsiack);
607 607
608 fsia_ick_out: 608 fsia_ick_out:
609 clk_put(fsia_ick); 609 clk_put(fsia_ick);
610 610
611 return 0; 611 return 0;
612 } 612 }
613 613
614 static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable) 614 static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
615 { 615 {
616 struct clk *fsib_clk; 616 struct clk *fsib_clk;
617 struct clk *fdiv_clk = &sh7372_fsidivb_clk; 617 struct clk *fdiv_clk = &sh7372_fsidivb_clk;
618 long fsib_rate = 0; 618 long fsib_rate = 0;
619 long fdiv_rate = 0; 619 long fdiv_rate = 0;
620 int ackmd_bpfmd; 620 int ackmd_bpfmd;
621 int ret; 621 int ret;
622 622
623 switch (rate) { 623 switch (rate) {
624 case 44100: 624 case 44100:
625 fsib_rate = rate * 256; 625 fsib_rate = rate * 256;
626 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64; 626 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
627 break; 627 break;
628 case 48000: 628 case 48000:
629 fsib_rate = 85428000; /* around 48kHz x 256 x 7 */ 629 fsib_rate = 85428000; /* around 48kHz x 256 x 7 */
630 fdiv_rate = rate * 256; 630 fdiv_rate = rate * 256;
631 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64; 631 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
632 break; 632 break;
633 default: 633 default:
634 pr_err("unsupported rate in FSI2 port B\n"); 634 pr_err("unsupported rate in FSI2 port B\n");
635 return -EINVAL; 635 return -EINVAL;
636 } 636 }
637 637
638 /* FSI B setting */ 638 /* FSI B setting */
639 fsib_clk = clk_get(dev, "ickb"); 639 fsib_clk = clk_get(dev, "ickb");
640 if (IS_ERR(fsib_clk)) 640 if (IS_ERR(fsib_clk))
641 return -EIO; 641 return -EIO;
642 642
643 ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable); 643 ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
644 if (ret < 0) 644 if (ret < 0)
645 goto fsi_set_rate_end; 645 goto fsi_set_rate_end;
646 646
647 /* FSI DIV setting */ 647 /* FSI DIV setting */
648 ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable); 648 ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
649 if (ret < 0) { 649 if (ret < 0) {
650 /* disable FSI B */ 650 /* disable FSI B */
651 if (enable) 651 if (enable)
652 __fsi_set_round_rate(fsib_clk, fsib_rate, 0); 652 __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
653 goto fsi_set_rate_end; 653 goto fsi_set_rate_end;
654 } 654 }
655 655
656 ret = ackmd_bpfmd; 656 ret = ackmd_bpfmd;
657 657
658 fsi_set_rate_end: 658 fsi_set_rate_end:
659 clk_put(fsib_clk); 659 clk_put(fsib_clk);
660 return ret; 660 return ret;
661 } 661 }
662 662
663 static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable) 663 static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
664 { 664 {
665 int ret; 665 int ret;
666 666
667 if (is_porta) 667 if (is_porta)
668 ret = fsi_ak4642_set_rate(dev, rate, enable); 668 ret = fsi_ak4642_set_rate(dev, rate, enable);
669 else 669 else
670 ret = fsi_hdmi_set_rate(dev, rate, enable); 670 ret = fsi_hdmi_set_rate(dev, rate, enable);
671 671
672 return ret; 672 return ret;
673 } 673 }
674 674
675 static struct sh_fsi_platform_info fsi_info = { 675 static struct sh_fsi_platform_info fsi_info = {
676 .porta_flags = SH_FSI_BRS_INV | 676 .porta_flags = SH_FSI_BRS_INV,
677 SH_FSI_OFMT(PCM) |
678 SH_FSI_IFMT(PCM),
679 677
680 .portb_flags = SH_FSI_BRS_INV | 678 .portb_flags = SH_FSI_BRS_INV |
681 SH_FSI_BRM_INV | 679 SH_FSI_BRM_INV |
682 SH_FSI_LRS_INV | 680 SH_FSI_LRS_INV |
683 SH_FSI_OFMT(SPDIF), 681 SH_FSI_FMT_SPDIF,
684 .set_rate = fsi_set_rate, 682 .set_rate = fsi_set_rate,
685 }; 683 };
686 684
687 static struct resource fsi_resources[] = { 685 static struct resource fsi_resources[] = {
688 [0] = { 686 [0] = {
689 .name = "FSI", 687 .name = "FSI",
690 .start = 0xFE3C0000, 688 .start = 0xFE3C0000,
691 .end = 0xFE3C0400 - 1, 689 .end = 0xFE3C0400 - 1,
692 .flags = IORESOURCE_MEM, 690 .flags = IORESOURCE_MEM,
693 }, 691 },
694 [1] = { 692 [1] = {
695 .start = IRQ_FSI, 693 .start = IRQ_FSI,
696 .flags = IORESOURCE_IRQ, 694 .flags = IORESOURCE_IRQ,
697 }, 695 },
698 }; 696 };
699 697
700 static struct platform_device fsi_device = { 698 static struct platform_device fsi_device = {
701 .name = "sh_fsi2", 699 .name = "sh_fsi2",
702 .id = -1, 700 .id = -1,
703 .num_resources = ARRAY_SIZE(fsi_resources), 701 .num_resources = ARRAY_SIZE(fsi_resources),
704 .resource = fsi_resources, 702 .resource = fsi_resources,
705 .dev = { 703 .dev = {
706 .platform_data = &fsi_info, 704 .platform_data = &fsi_info,
707 }, 705 },
708 }; 706 };
709 707
710 static struct platform_device fsi_ak4643_device = { 708 static struct platform_device fsi_ak4643_device = {
711 .name = "sh_fsi2_a_ak4643", 709 .name = "sh_fsi2_a_ak4643",
712 }; 710 };
713 711
714 static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = { 712 static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
715 .clock_source = LCDC_CLK_EXTERNAL, 713 .clock_source = LCDC_CLK_EXTERNAL,
716 .ch[0] = { 714 .ch[0] = {
717 .chan = LCDC_CHAN_MAINLCD, 715 .chan = LCDC_CHAN_MAINLCD,
718 .bpp = 16, 716 .bpp = 16,
719 .interface_type = RGB24, 717 .interface_type = RGB24,
720 .clock_divider = 1, 718 .clock_divider = 1,
721 .flags = LCDC_FLAGS_DWPOL, 719 .flags = LCDC_FLAGS_DWPOL,
722 } 720 }
723 }; 721 };
724 722
725 static struct resource lcdc1_resources[] = { 723 static struct resource lcdc1_resources[] = {
726 [0] = { 724 [0] = {
727 .name = "LCDC1", 725 .name = "LCDC1",
728 .start = 0xfe944000, 726 .start = 0xfe944000,
729 .end = 0xfe947fff, 727 .end = 0xfe947fff,
730 .flags = IORESOURCE_MEM, 728 .flags = IORESOURCE_MEM,
731 }, 729 },
732 [1] = { 730 [1] = {
733 .start = intcs_evt2irq(0x1780), 731 .start = intcs_evt2irq(0x1780),
734 .flags = IORESOURCE_IRQ, 732 .flags = IORESOURCE_IRQ,
735 }, 733 },
736 }; 734 };
737 735
738 static struct platform_device lcdc1_device = { 736 static struct platform_device lcdc1_device = {
739 .name = "sh_mobile_lcdc_fb", 737 .name = "sh_mobile_lcdc_fb",
740 .num_resources = ARRAY_SIZE(lcdc1_resources), 738 .num_resources = ARRAY_SIZE(lcdc1_resources),
741 .resource = lcdc1_resources, 739 .resource = lcdc1_resources,
742 .id = 1, 740 .id = 1,
743 .dev = { 741 .dev = {
744 .platform_data = &sh_mobile_lcdc1_info, 742 .platform_data = &sh_mobile_lcdc1_info,
745 .coherent_dma_mask = ~0, 743 .coherent_dma_mask = ~0,
746 }, 744 },
747 }; 745 };
748 746
749 static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq, 747 static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
750 unsigned long *parent_freq); 748 unsigned long *parent_freq);
751 749
752 750
753 static struct sh_mobile_hdmi_info hdmi_info = { 751 static struct sh_mobile_hdmi_info hdmi_info = {
754 .lcd_chan = &sh_mobile_lcdc1_info.ch[0], 752 .lcd_chan = &sh_mobile_lcdc1_info.ch[0],
755 .lcd_dev = &lcdc1_device.dev, 753 .lcd_dev = &lcdc1_device.dev,
756 .flags = HDMI_SND_SRC_SPDIF, 754 .flags = HDMI_SND_SRC_SPDIF,
757 .clk_optimize_parent = ap4evb_clk_optimize, 755 .clk_optimize_parent = ap4evb_clk_optimize,
758 }; 756 };
759 757
760 static struct resource hdmi_resources[] = { 758 static struct resource hdmi_resources[] = {
761 [0] = { 759 [0] = {
762 .name = "HDMI", 760 .name = "HDMI",
763 .start = 0xe6be0000, 761 .start = 0xe6be0000,
764 .end = 0xe6be00ff, 762 .end = 0xe6be00ff,
765 .flags = IORESOURCE_MEM, 763 .flags = IORESOURCE_MEM,
766 }, 764 },
767 [1] = { 765 [1] = {
768 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */ 766 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
769 .start = evt2irq(0x17e0), 767 .start = evt2irq(0x17e0),
770 .flags = IORESOURCE_IRQ, 768 .flags = IORESOURCE_IRQ,
771 }, 769 },
772 }; 770 };
773 771
774 static struct platform_device hdmi_device = { 772 static struct platform_device hdmi_device = {
775 .name = "sh-mobile-hdmi", 773 .name = "sh-mobile-hdmi",
776 .num_resources = ARRAY_SIZE(hdmi_resources), 774 .num_resources = ARRAY_SIZE(hdmi_resources),
777 .resource = hdmi_resources, 775 .resource = hdmi_resources,
778 .id = -1, 776 .id = -1,
779 .dev = { 777 .dev = {
780 .platform_data = &hdmi_info, 778 .platform_data = &hdmi_info,
781 }, 779 },
782 }; 780 };
783 781
784 static struct platform_device fsi_hdmi_device = { 782 static struct platform_device fsi_hdmi_device = {
785 .name = "sh_fsi2_b_hdmi", 783 .name = "sh_fsi2_b_hdmi",
786 }; 784 };
787 785
788 static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq, 786 static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
789 unsigned long *parent_freq) 787 unsigned long *parent_freq)
790 { 788 {
791 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); 789 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
792 long error; 790 long error;
793 791
794 if (IS_ERR(hdmi_ick)) { 792 if (IS_ERR(hdmi_ick)) {
795 int ret = PTR_ERR(hdmi_ick); 793 int ret = PTR_ERR(hdmi_ick);
796 pr_err("Cannot get HDMI ICK: %d\n", ret); 794 pr_err("Cannot get HDMI ICK: %d\n", ret);
797 return ret; 795 return ret;
798 } 796 }
799 797
800 error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64); 798 error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
801 799
802 clk_put(hdmi_ick); 800 clk_put(hdmi_ick);
803 801
804 return error; 802 return error;
805 } 803 }
806 804
807 static struct gpio_led ap4evb_leds[] = { 805 static struct gpio_led ap4evb_leds[] = {
808 { 806 {
809 .name = "led4", 807 .name = "led4",
810 .gpio = GPIO_PORT185, 808 .gpio = GPIO_PORT185,
811 .default_state = LEDS_GPIO_DEFSTATE_ON, 809 .default_state = LEDS_GPIO_DEFSTATE_ON,
812 }, 810 },
813 { 811 {
814 .name = "led2", 812 .name = "led2",
815 .gpio = GPIO_PORT186, 813 .gpio = GPIO_PORT186,
816 .default_state = LEDS_GPIO_DEFSTATE_ON, 814 .default_state = LEDS_GPIO_DEFSTATE_ON,
817 }, 815 },
818 { 816 {
819 .name = "led3", 817 .name = "led3",
820 .gpio = GPIO_PORT187, 818 .gpio = GPIO_PORT187,
821 .default_state = LEDS_GPIO_DEFSTATE_ON, 819 .default_state = LEDS_GPIO_DEFSTATE_ON,
822 }, 820 },
823 { 821 {
824 .name = "led1", 822 .name = "led1",
825 .gpio = GPIO_PORT188, 823 .gpio = GPIO_PORT188,
826 .default_state = LEDS_GPIO_DEFSTATE_ON, 824 .default_state = LEDS_GPIO_DEFSTATE_ON,
827 } 825 }
828 }; 826 };
829 827
830 static struct gpio_led_platform_data ap4evb_leds_pdata = { 828 static struct gpio_led_platform_data ap4evb_leds_pdata = {
831 .num_leds = ARRAY_SIZE(ap4evb_leds), 829 .num_leds = ARRAY_SIZE(ap4evb_leds),
832 .leds = ap4evb_leds, 830 .leds = ap4evb_leds,
833 }; 831 };
834 832
835 static struct platform_device leds_device = { 833 static struct platform_device leds_device = {
836 .name = "leds-gpio", 834 .name = "leds-gpio",
837 .id = 0, 835 .id = 0,
838 .dev = { 836 .dev = {
839 .platform_data = &ap4evb_leds_pdata, 837 .platform_data = &ap4evb_leds_pdata,
840 }, 838 },
841 }; 839 };
842 840
843 static struct i2c_board_info imx074_info = { 841 static struct i2c_board_info imx074_info = {
844 I2C_BOARD_INFO("imx074", 0x1a), 842 I2C_BOARD_INFO("imx074", 0x1a),
845 }; 843 };
846 844
847 struct soc_camera_link imx074_link = { 845 struct soc_camera_link imx074_link = {
848 .bus_id = 0, 846 .bus_id = 0,
849 .board_info = &imx074_info, 847 .board_info = &imx074_info,
850 .i2c_adapter_id = 0, 848 .i2c_adapter_id = 0,
851 .module_name = "imx074", 849 .module_name = "imx074",
852 }; 850 };
853 851
854 static struct platform_device ap4evb_camera = { 852 static struct platform_device ap4evb_camera = {
855 .name = "soc-camera-pdrv", 853 .name = "soc-camera-pdrv",
856 .id = 0, 854 .id = 0,
857 .dev = { 855 .dev = {
858 .platform_data = &imx074_link, 856 .platform_data = &imx074_link,
859 }, 857 },
860 }; 858 };
861 859
862 static struct sh_csi2_client_config csi2_clients[] = { 860 static struct sh_csi2_client_config csi2_clients[] = {
863 { 861 {
864 .phy = SH_CSI2_PHY_MAIN, 862 .phy = SH_CSI2_PHY_MAIN,
865 .lanes = 3, 863 .lanes = 3,
866 .channel = 0, 864 .channel = 0,
867 .pdev = &ap4evb_camera, 865 .pdev = &ap4evb_camera,
868 }, 866 },
869 }; 867 };
870 868
871 static struct sh_csi2_pdata csi2_info = { 869 static struct sh_csi2_pdata csi2_info = {
872 .type = SH_CSI2C, 870 .type = SH_CSI2C,
873 .clients = csi2_clients, 871 .clients = csi2_clients,
874 .num_clients = ARRAY_SIZE(csi2_clients), 872 .num_clients = ARRAY_SIZE(csi2_clients),
875 .flags = SH_CSI2_ECC | SH_CSI2_CRC, 873 .flags = SH_CSI2_ECC | SH_CSI2_CRC,
876 }; 874 };
877 875
878 static struct resource csi2_resources[] = { 876 static struct resource csi2_resources[] = {
879 [0] = { 877 [0] = {
880 .name = "CSI2", 878 .name = "CSI2",
881 .start = 0xffc90000, 879 .start = 0xffc90000,
882 .end = 0xffc90fff, 880 .end = 0xffc90fff,
883 .flags = IORESOURCE_MEM, 881 .flags = IORESOURCE_MEM,
884 }, 882 },
885 [1] = { 883 [1] = {
886 .start = intcs_evt2irq(0x17a0), 884 .start = intcs_evt2irq(0x17a0),
887 .flags = IORESOURCE_IRQ, 885 .flags = IORESOURCE_IRQ,
888 }, 886 },
889 }; 887 };
890 888
891 static struct platform_device csi2_device = { 889 static struct platform_device csi2_device = {
892 .name = "sh-mobile-csi2", 890 .name = "sh-mobile-csi2",
893 .id = 0, 891 .id = 0,
894 .num_resources = ARRAY_SIZE(csi2_resources), 892 .num_resources = ARRAY_SIZE(csi2_resources),
895 .resource = csi2_resources, 893 .resource = csi2_resources,
896 .dev = { 894 .dev = {
897 .platform_data = &csi2_info, 895 .platform_data = &csi2_info,
898 }, 896 },
899 }; 897 };
900 898
901 static struct sh_mobile_ceu_info sh_mobile_ceu_info = { 899 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
902 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 900 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
903 .csi2_dev = &csi2_device.dev, 901 .csi2_dev = &csi2_device.dev,
904 }; 902 };
905 903
906 static struct resource ceu_resources[] = { 904 static struct resource ceu_resources[] = {
907 [0] = { 905 [0] = {
908 .name = "CEU", 906 .name = "CEU",
909 .start = 0xfe910000, 907 .start = 0xfe910000,
910 .end = 0xfe91009f, 908 .end = 0xfe91009f,
911 .flags = IORESOURCE_MEM, 909 .flags = IORESOURCE_MEM,
912 }, 910 },
913 [1] = { 911 [1] = {
914 .start = intcs_evt2irq(0x880), 912 .start = intcs_evt2irq(0x880),
915 .flags = IORESOURCE_IRQ, 913 .flags = IORESOURCE_IRQ,
916 }, 914 },
917 [2] = { 915 [2] = {
918 /* place holder for contiguous memory */ 916 /* place holder for contiguous memory */
919 }, 917 },
920 }; 918 };
921 919
922 static struct platform_device ceu_device = { 920 static struct platform_device ceu_device = {
923 .name = "sh_mobile_ceu", 921 .name = "sh_mobile_ceu",
924 .id = 0, /* "ceu0" clock */ 922 .id = 0, /* "ceu0" clock */
925 .num_resources = ARRAY_SIZE(ceu_resources), 923 .num_resources = ARRAY_SIZE(ceu_resources),
926 .resource = ceu_resources, 924 .resource = ceu_resources,
927 .dev = { 925 .dev = {
928 .platform_data = &sh_mobile_ceu_info, 926 .platform_data = &sh_mobile_ceu_info,
929 }, 927 },
930 }; 928 };
931 929
932 static struct platform_device *ap4evb_devices[] __initdata = { 930 static struct platform_device *ap4evb_devices[] __initdata = {
933 &leds_device, 931 &leds_device,
934 &nor_flash_device, 932 &nor_flash_device,
935 &smc911x_device, 933 &smc911x_device,
936 &sdhi0_device, 934 &sdhi0_device,
937 &sdhi1_device, 935 &sdhi1_device,
938 &usb1_host_device, 936 &usb1_host_device,
939 &fsi_device, 937 &fsi_device,
940 &fsi_ak4643_device, 938 &fsi_ak4643_device,
941 &fsi_hdmi_device, 939 &fsi_hdmi_device,
942 &sh_mmcif_device, 940 &sh_mmcif_device,
943 &lcdc1_device, 941 &lcdc1_device,
944 &lcdc_device, 942 &lcdc_device,
945 &hdmi_device, 943 &hdmi_device,
946 &csi2_device, 944 &csi2_device,
947 &ceu_device, 945 &ceu_device,
948 &ap4evb_camera, 946 &ap4evb_camera,
949 }; 947 };
950 948
951 static int __init hdmi_init_pm_clock(void) 949 static int __init hdmi_init_pm_clock(void)
952 { 950 {
953 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); 951 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
954 int ret; 952 int ret;
955 long rate; 953 long rate;
956 954
957 if (IS_ERR(hdmi_ick)) { 955 if (IS_ERR(hdmi_ick)) {
958 ret = PTR_ERR(hdmi_ick); 956 ret = PTR_ERR(hdmi_ick);
959 pr_err("Cannot get HDMI ICK: %d\n", ret); 957 pr_err("Cannot get HDMI ICK: %d\n", ret);
960 goto out; 958 goto out;
961 } 959 }
962 960
963 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk); 961 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
964 if (ret < 0) { 962 if (ret < 0) {
965 pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount); 963 pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
966 goto out; 964 goto out;
967 } 965 }
968 966
969 pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk)); 967 pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
970 968
971 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000); 969 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
972 if (rate < 0) { 970 if (rate < 0) {
973 pr_err("Cannot get suitable rate: %ld\n", rate); 971 pr_err("Cannot get suitable rate: %ld\n", rate);
974 ret = rate; 972 ret = rate;
975 goto out; 973 goto out;
976 } 974 }
977 975
978 ret = clk_set_rate(&sh7372_pllc2_clk, rate); 976 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
979 if (ret < 0) { 977 if (ret < 0) {
980 pr_err("Cannot set rate %ld: %d\n", rate, ret); 978 pr_err("Cannot set rate %ld: %d\n", rate, ret);
981 goto out; 979 goto out;
982 } 980 }
983 981
984 ret = clk_enable(&sh7372_pllc2_clk); 982 ret = clk_enable(&sh7372_pllc2_clk);
985 if (ret < 0) { 983 if (ret < 0) {
986 pr_err("Cannot enable pllc2 clock\n"); 984 pr_err("Cannot enable pllc2 clock\n");
987 goto out; 985 goto out;
988 } 986 }
989 pr_debug("PLLC2 set frequency %lu\n", rate); 987 pr_debug("PLLC2 set frequency %lu\n", rate);
990 988
991 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); 989 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
992 if (ret < 0) { 990 if (ret < 0) {
993 pr_err("Cannot set HDMI parent: %d\n", ret); 991 pr_err("Cannot set HDMI parent: %d\n", ret);
994 goto out; 992 goto out;
995 } 993 }
996 994
997 out: 995 out:
998 if (!IS_ERR(hdmi_ick)) 996 if (!IS_ERR(hdmi_ick))
999 clk_put(hdmi_ick); 997 clk_put(hdmi_ick);
1000 return ret; 998 return ret;
1001 } 999 }
1002 1000
1003 device_initcall(hdmi_init_pm_clock); 1001 device_initcall(hdmi_init_pm_clock);
1004 1002
1005 static int __init fsi_init_pm_clock(void) 1003 static int __init fsi_init_pm_clock(void)
1006 { 1004 {
1007 struct clk *fsia_ick; 1005 struct clk *fsia_ick;
1008 int ret; 1006 int ret;
1009 1007
1010 fsia_ick = clk_get(&fsi_device.dev, "icka"); 1008 fsia_ick = clk_get(&fsi_device.dev, "icka");
1011 if (IS_ERR(fsia_ick)) { 1009 if (IS_ERR(fsia_ick)) {
1012 ret = PTR_ERR(fsia_ick); 1010 ret = PTR_ERR(fsia_ick);
1013 pr_err("Cannot get FSI ICK: %d\n", ret); 1011 pr_err("Cannot get FSI ICK: %d\n", ret);
1014 return ret; 1012 return ret;
1015 } 1013 }
1016 1014
1017 ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk); 1015 ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk);
1018 if (ret < 0) 1016 if (ret < 0)
1019 pr_err("Cannot set FSI-A parent: %d\n", ret); 1017 pr_err("Cannot set FSI-A parent: %d\n", ret);
1020 1018
1021 clk_put(fsia_ick); 1019 clk_put(fsia_ick);
1022 1020
1023 return ret; 1021 return ret;
1024 } 1022 }
1025 device_initcall(fsi_init_pm_clock); 1023 device_initcall(fsi_init_pm_clock);
1026 1024
1027 /* 1025 /*
1028 * FIXME !! 1026 * FIXME !!
1029 * 1027 *
1030 * gpio_no_direction 1028 * gpio_no_direction
1031 * are quick_hack. 1029 * are quick_hack.
1032 * 1030 *
1033 * current gpio frame work doesn't have 1031 * current gpio frame work doesn't have
1034 * the method to control only pull up/down/free. 1032 * the method to control only pull up/down/free.
1035 * this function should be replaced by correct gpio function 1033 * this function should be replaced by correct gpio function
1036 */ 1034 */
1037 static void __init gpio_no_direction(u32 addr) 1035 static void __init gpio_no_direction(u32 addr)
1038 { 1036 {
1039 __raw_writeb(0x00, addr); 1037 __raw_writeb(0x00, addr);
1040 } 1038 }
1041 1039
1042 /* TouchScreen */ 1040 /* TouchScreen */
1043 #ifdef CONFIG_AP4EVB_QHD 1041 #ifdef CONFIG_AP4EVB_QHD
1044 # define GPIO_TSC_IRQ GPIO_FN_IRQ28_123 1042 # define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
1045 # define GPIO_TSC_PORT GPIO_PORT123 1043 # define GPIO_TSC_PORT GPIO_PORT123
1046 #else /* WVGA */ 1044 #else /* WVGA */
1047 # define GPIO_TSC_IRQ GPIO_FN_IRQ7_40 1045 # define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
1048 # define GPIO_TSC_PORT GPIO_PORT40 1046 # define GPIO_TSC_PORT GPIO_PORT40
1049 #endif 1047 #endif
1050 1048
1051 #define IRQ28 evt2irq(0x3380) /* IRQ28A */ 1049 #define IRQ28 evt2irq(0x3380) /* IRQ28A */
1052 #define IRQ7 evt2irq(0x02e0) /* IRQ7A */ 1050 #define IRQ7 evt2irq(0x02e0) /* IRQ7A */
1053 static int ts_get_pendown_state(void) 1051 static int ts_get_pendown_state(void)
1054 { 1052 {
1055 int val; 1053 int val;
1056 1054
1057 gpio_free(GPIO_TSC_IRQ); 1055 gpio_free(GPIO_TSC_IRQ);
1058 1056
1059 gpio_request(GPIO_TSC_PORT, NULL); 1057 gpio_request(GPIO_TSC_PORT, NULL);
1060 1058
1061 gpio_direction_input(GPIO_TSC_PORT); 1059 gpio_direction_input(GPIO_TSC_PORT);
1062 1060
1063 val = gpio_get_value(GPIO_TSC_PORT); 1061 val = gpio_get_value(GPIO_TSC_PORT);
1064 1062
1065 gpio_request(GPIO_TSC_IRQ, NULL); 1063 gpio_request(GPIO_TSC_IRQ, NULL);
1066 1064
1067 return !val; 1065 return !val;
1068 } 1066 }
1069 1067
1070 static int ts_init(void) 1068 static int ts_init(void)
1071 { 1069 {
1072 gpio_request(GPIO_TSC_IRQ, NULL); 1070 gpio_request(GPIO_TSC_IRQ, NULL);
1073 1071
1074 return 0; 1072 return 0;
1075 } 1073 }
1076 1074
1077 static struct tsc2007_platform_data tsc2007_info = { 1075 static struct tsc2007_platform_data tsc2007_info = {
1078 .model = 2007, 1076 .model = 2007,
1079 .x_plate_ohms = 180, 1077 .x_plate_ohms = 180,
1080 .get_pendown_state = ts_get_pendown_state, 1078 .get_pendown_state = ts_get_pendown_state,
1081 .init_platform_hw = ts_init, 1079 .init_platform_hw = ts_init,
1082 }; 1080 };
1083 1081
1084 static struct i2c_board_info tsc_device = { 1082 static struct i2c_board_info tsc_device = {
1085 I2C_BOARD_INFO("tsc2007", 0x48), 1083 I2C_BOARD_INFO("tsc2007", 0x48),
1086 .type = "tsc2007", 1084 .type = "tsc2007",
1087 .platform_data = &tsc2007_info, 1085 .platform_data = &tsc2007_info,
1088 /*.irq is selected on ap4evb_init */ 1086 /*.irq is selected on ap4evb_init */
1089 }; 1087 };
1090 1088
1091 /* I2C */ 1089 /* I2C */
1092 static struct i2c_board_info i2c0_devices[] = { 1090 static struct i2c_board_info i2c0_devices[] = {
1093 { 1091 {
1094 I2C_BOARD_INFO("ak4643", 0x13), 1092 I2C_BOARD_INFO("ak4643", 0x13),
1095 }, 1093 },
1096 }; 1094 };
1097 1095
1098 static struct i2c_board_info i2c1_devices[] = { 1096 static struct i2c_board_info i2c1_devices[] = {
1099 { 1097 {
1100 I2C_BOARD_INFO("r2025sd", 0x32), 1098 I2C_BOARD_INFO("r2025sd", 0x32),
1101 }, 1099 },
1102 }; 1100 };
1103 1101
1104 static struct map_desc ap4evb_io_desc[] __initdata = { 1102 static struct map_desc ap4evb_io_desc[] __initdata = {
1105 /* create a 1:1 entity map for 0xe6xxxxxx 1103 /* create a 1:1 entity map for 0xe6xxxxxx
1106 * used by CPGA, INTC and PFC. 1104 * used by CPGA, INTC and PFC.
1107 */ 1105 */
1108 { 1106 {
1109 .virtual = 0xe6000000, 1107 .virtual = 0xe6000000,
1110 .pfn = __phys_to_pfn(0xe6000000), 1108 .pfn = __phys_to_pfn(0xe6000000),
1111 .length = 256 << 20, 1109 .length = 256 << 20,
1112 .type = MT_DEVICE_NONSHARED 1110 .type = MT_DEVICE_NONSHARED
1113 }, 1111 },
1114 }; 1112 };
1115 1113
1116 static void __init ap4evb_map_io(void) 1114 static void __init ap4evb_map_io(void)
1117 { 1115 {
1118 iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc)); 1116 iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc));
1119 1117
1120 /* setup early devices and console here as well */ 1118 /* setup early devices and console here as well */
1121 sh7372_add_early_devices(); 1119 sh7372_add_early_devices();
1122 shmobile_setup_console(); 1120 shmobile_setup_console();
1123 } 1121 }
1124 1122
1125 #define GPIO_PORT9CR 0xE6051009 1123 #define GPIO_PORT9CR 0xE6051009
1126 #define GPIO_PORT10CR 0xE605100A 1124 #define GPIO_PORT10CR 0xE605100A
1127 #define USCCR1 0xE6058144 1125 #define USCCR1 0xE6058144
1128 static void __init ap4evb_init(void) 1126 static void __init ap4evb_init(void)
1129 { 1127 {
1130 u32 srcr4; 1128 u32 srcr4;
1131 struct clk *clk; 1129 struct clk *clk;
1132 1130
1133 sh7372_pinmux_init(); 1131 sh7372_pinmux_init();
1134 1132
1135 /* enable SCIFA0 */ 1133 /* enable SCIFA0 */
1136 gpio_request(GPIO_FN_SCIFA0_TXD, NULL); 1134 gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
1137 gpio_request(GPIO_FN_SCIFA0_RXD, NULL); 1135 gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
1138 1136
1139 /* enable SMSC911X */ 1137 /* enable SMSC911X */
1140 gpio_request(GPIO_FN_CS5A, NULL); 1138 gpio_request(GPIO_FN_CS5A, NULL);
1141 gpio_request(GPIO_FN_IRQ6_39, NULL); 1139 gpio_request(GPIO_FN_IRQ6_39, NULL);
1142 1140
1143 /* enable Debug switch (S6) */ 1141 /* enable Debug switch (S6) */
1144 gpio_request(GPIO_PORT32, NULL); 1142 gpio_request(GPIO_PORT32, NULL);
1145 gpio_request(GPIO_PORT33, NULL); 1143 gpio_request(GPIO_PORT33, NULL);
1146 gpio_request(GPIO_PORT34, NULL); 1144 gpio_request(GPIO_PORT34, NULL);
1147 gpio_request(GPIO_PORT35, NULL); 1145 gpio_request(GPIO_PORT35, NULL);
1148 gpio_direction_input(GPIO_PORT32); 1146 gpio_direction_input(GPIO_PORT32);
1149 gpio_direction_input(GPIO_PORT33); 1147 gpio_direction_input(GPIO_PORT33);
1150 gpio_direction_input(GPIO_PORT34); 1148 gpio_direction_input(GPIO_PORT34);
1151 gpio_direction_input(GPIO_PORT35); 1149 gpio_direction_input(GPIO_PORT35);
1152 gpio_export(GPIO_PORT32, 0); 1150 gpio_export(GPIO_PORT32, 0);
1153 gpio_export(GPIO_PORT33, 0); 1151 gpio_export(GPIO_PORT33, 0);
1154 gpio_export(GPIO_PORT34, 0); 1152 gpio_export(GPIO_PORT34, 0);
1155 gpio_export(GPIO_PORT35, 0); 1153 gpio_export(GPIO_PORT35, 0);
1156 1154
1157 /* SDHI0 */ 1155 /* SDHI0 */
1158 gpio_request(GPIO_FN_SDHICD0, NULL); 1156 gpio_request(GPIO_FN_SDHICD0, NULL);
1159 gpio_request(GPIO_FN_SDHIWP0, NULL); 1157 gpio_request(GPIO_FN_SDHIWP0, NULL);
1160 gpio_request(GPIO_FN_SDHICMD0, NULL); 1158 gpio_request(GPIO_FN_SDHICMD0, NULL);
1161 gpio_request(GPIO_FN_SDHICLK0, NULL); 1159 gpio_request(GPIO_FN_SDHICLK0, NULL);
1162 gpio_request(GPIO_FN_SDHID0_3, NULL); 1160 gpio_request(GPIO_FN_SDHID0_3, NULL);
1163 gpio_request(GPIO_FN_SDHID0_2, NULL); 1161 gpio_request(GPIO_FN_SDHID0_2, NULL);
1164 gpio_request(GPIO_FN_SDHID0_1, NULL); 1162 gpio_request(GPIO_FN_SDHID0_1, NULL);
1165 gpio_request(GPIO_FN_SDHID0_0, NULL); 1163 gpio_request(GPIO_FN_SDHID0_0, NULL);
1166 1164
1167 /* SDHI1 */ 1165 /* SDHI1 */
1168 gpio_request(GPIO_FN_SDHICMD1, NULL); 1166 gpio_request(GPIO_FN_SDHICMD1, NULL);
1169 gpio_request(GPIO_FN_SDHICLK1, NULL); 1167 gpio_request(GPIO_FN_SDHICLK1, NULL);
1170 gpio_request(GPIO_FN_SDHID1_3, NULL); 1168 gpio_request(GPIO_FN_SDHID1_3, NULL);
1171 gpio_request(GPIO_FN_SDHID1_2, NULL); 1169 gpio_request(GPIO_FN_SDHID1_2, NULL);
1172 gpio_request(GPIO_FN_SDHID1_1, NULL); 1170 gpio_request(GPIO_FN_SDHID1_1, NULL);
1173 gpio_request(GPIO_FN_SDHID1_0, NULL); 1171 gpio_request(GPIO_FN_SDHID1_0, NULL);
1174 1172
1175 /* MMCIF */ 1173 /* MMCIF */
1176 gpio_request(GPIO_FN_MMCD0_0, NULL); 1174 gpio_request(GPIO_FN_MMCD0_0, NULL);
1177 gpio_request(GPIO_FN_MMCD0_1, NULL); 1175 gpio_request(GPIO_FN_MMCD0_1, NULL);
1178 gpio_request(GPIO_FN_MMCD0_2, NULL); 1176 gpio_request(GPIO_FN_MMCD0_2, NULL);
1179 gpio_request(GPIO_FN_MMCD0_3, NULL); 1177 gpio_request(GPIO_FN_MMCD0_3, NULL);
1180 gpio_request(GPIO_FN_MMCD0_4, NULL); 1178 gpio_request(GPIO_FN_MMCD0_4, NULL);
1181 gpio_request(GPIO_FN_MMCD0_5, NULL); 1179 gpio_request(GPIO_FN_MMCD0_5, NULL);
1182 gpio_request(GPIO_FN_MMCD0_6, NULL); 1180 gpio_request(GPIO_FN_MMCD0_6, NULL);
1183 gpio_request(GPIO_FN_MMCD0_7, NULL); 1181 gpio_request(GPIO_FN_MMCD0_7, NULL);
1184 gpio_request(GPIO_FN_MMCCMD0, NULL); 1182 gpio_request(GPIO_FN_MMCCMD0, NULL);
1185 gpio_request(GPIO_FN_MMCCLK0, NULL); 1183 gpio_request(GPIO_FN_MMCCLK0, NULL);
1186 1184
1187 /* USB enable */ 1185 /* USB enable */
1188 gpio_request(GPIO_FN_VBUS0_1, NULL); 1186 gpio_request(GPIO_FN_VBUS0_1, NULL);
1189 gpio_request(GPIO_FN_IDIN_1_18, NULL); 1187 gpio_request(GPIO_FN_IDIN_1_18, NULL);
1190 gpio_request(GPIO_FN_PWEN_1_115, NULL); 1188 gpio_request(GPIO_FN_PWEN_1_115, NULL);
1191 gpio_request(GPIO_FN_OVCN_1_114, NULL); 1189 gpio_request(GPIO_FN_OVCN_1_114, NULL);
1192 gpio_request(GPIO_FN_EXTLP_1, NULL); 1190 gpio_request(GPIO_FN_EXTLP_1, NULL);
1193 gpio_request(GPIO_FN_OVCN2_1, NULL); 1191 gpio_request(GPIO_FN_OVCN2_1, NULL);
1194 1192
1195 /* setup USB phy */ 1193 /* setup USB phy */
1196 __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */ 1194 __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */
1197 1195
1198 /* enable FSI2 port A (ak4643) */ 1196 /* enable FSI2 port A (ak4643) */
1199 gpio_request(GPIO_FN_FSIAIBT, NULL); 1197 gpio_request(GPIO_FN_FSIAIBT, NULL);
1200 gpio_request(GPIO_FN_FSIAILR, NULL); 1198 gpio_request(GPIO_FN_FSIAILR, NULL);
1201 gpio_request(GPIO_FN_FSIAISLD, NULL); 1199 gpio_request(GPIO_FN_FSIAISLD, NULL);
1202 gpio_request(GPIO_FN_FSIAOSLD, NULL); 1200 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1203 gpio_request(GPIO_PORT161, NULL); 1201 gpio_request(GPIO_PORT161, NULL);
1204 gpio_direction_output(GPIO_PORT161, 0); /* slave */ 1202 gpio_direction_output(GPIO_PORT161, 0); /* slave */
1205 1203
1206 gpio_request(GPIO_PORT9, NULL); 1204 gpio_request(GPIO_PORT9, NULL);
1207 gpio_request(GPIO_PORT10, NULL); 1205 gpio_request(GPIO_PORT10, NULL);
1208 gpio_no_direction(GPIO_PORT9CR); /* FSIAOBT needs no direction */ 1206 gpio_no_direction(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1209 gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */ 1207 gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
1210 1208
1211 /* card detect pin for MMC slot (CN7) */ 1209 /* card detect pin for MMC slot (CN7) */
1212 gpio_request(GPIO_PORT41, NULL); 1210 gpio_request(GPIO_PORT41, NULL);
1213 gpio_direction_input(GPIO_PORT41); 1211 gpio_direction_input(GPIO_PORT41);
1214 1212
1215 /* setup FSI2 port B (HDMI) */ 1213 /* setup FSI2 port B (HDMI) */
1216 gpio_request(GPIO_FN_FSIBCK, NULL); 1214 gpio_request(GPIO_FN_FSIBCK, NULL);
1217 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ 1215 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
1218 1216
1219 /* set SPU2 clock to 119.6 MHz */ 1217 /* set SPU2 clock to 119.6 MHz */
1220 clk = clk_get(NULL, "spu_clk"); 1218 clk = clk_get(NULL, "spu_clk");
1221 if (!IS_ERR(clk)) { 1219 if (!IS_ERR(clk)) {
1222 clk_set_rate(clk, clk_round_rate(clk, 119600000)); 1220 clk_set_rate(clk, clk_round_rate(clk, 119600000));
1223 clk_put(clk); 1221 clk_put(clk);
1224 } 1222 }
1225 1223
1226 /* 1224 /*
1227 * set irq priority, to avoid sound chopping 1225 * set irq priority, to avoid sound chopping
1228 * when NFS rootfs is used 1226 * when NFS rootfs is used
1229 * FSI(3) > SMSC911X(2) 1227 * FSI(3) > SMSC911X(2)
1230 */ 1228 */
1231 intc_set_priority(IRQ_FSI, 3); 1229 intc_set_priority(IRQ_FSI, 3);
1232 1230
1233 i2c_register_board_info(0, i2c0_devices, 1231 i2c_register_board_info(0, i2c0_devices,
1234 ARRAY_SIZE(i2c0_devices)); 1232 ARRAY_SIZE(i2c0_devices));
1235 1233
1236 i2c_register_board_info(1, i2c1_devices, 1234 i2c_register_board_info(1, i2c1_devices,
1237 ARRAY_SIZE(i2c1_devices)); 1235 ARRAY_SIZE(i2c1_devices));
1238 1236
1239 #ifdef CONFIG_AP4EVB_QHD 1237 #ifdef CONFIG_AP4EVB_QHD
1240 1238
1241 /* 1239 /*
1242 * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and 1240 * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
1243 * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON. 1241 * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
1244 */ 1242 */
1245 1243
1246 /* enable KEYSC */ 1244 /* enable KEYSC */
1247 gpio_request(GPIO_FN_KEYOUT0, NULL); 1245 gpio_request(GPIO_FN_KEYOUT0, NULL);
1248 gpio_request(GPIO_FN_KEYOUT1, NULL); 1246 gpio_request(GPIO_FN_KEYOUT1, NULL);
1249 gpio_request(GPIO_FN_KEYOUT2, NULL); 1247 gpio_request(GPIO_FN_KEYOUT2, NULL);
1250 gpio_request(GPIO_FN_KEYOUT3, NULL); 1248 gpio_request(GPIO_FN_KEYOUT3, NULL);
1251 gpio_request(GPIO_FN_KEYOUT4, NULL); 1249 gpio_request(GPIO_FN_KEYOUT4, NULL);
1252 gpio_request(GPIO_FN_KEYIN0_136, NULL); 1250 gpio_request(GPIO_FN_KEYIN0_136, NULL);
1253 gpio_request(GPIO_FN_KEYIN1_135, NULL); 1251 gpio_request(GPIO_FN_KEYIN1_135, NULL);
1254 gpio_request(GPIO_FN_KEYIN2_134, NULL); 1252 gpio_request(GPIO_FN_KEYIN2_134, NULL);
1255 gpio_request(GPIO_FN_KEYIN3_133, NULL); 1253 gpio_request(GPIO_FN_KEYIN3_133, NULL);
1256 gpio_request(GPIO_FN_KEYIN4, NULL); 1254 gpio_request(GPIO_FN_KEYIN4, NULL);
1257 1255
1258 /* enable TouchScreen */ 1256 /* enable TouchScreen */
1259 set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); 1257 set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
1260 1258
1261 tsc_device.irq = IRQ28; 1259 tsc_device.irq = IRQ28;
1262 i2c_register_board_info(1, &tsc_device, 1); 1260 i2c_register_board_info(1, &tsc_device, 1);
1263 1261
1264 /* LCDC0 */ 1262 /* LCDC0 */
1265 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL; 1263 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
1266 lcdc_info.ch[0].interface_type = RGB24; 1264 lcdc_info.ch[0].interface_type = RGB24;
1267 lcdc_info.ch[0].clock_divider = 1; 1265 lcdc_info.ch[0].clock_divider = 1;
1268 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; 1266 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
1269 lcdc_info.ch[0].lcd_size_cfg.width = 44; 1267 lcdc_info.ch[0].lcd_size_cfg.width = 44;
1270 lcdc_info.ch[0].lcd_size_cfg.height = 79; 1268 lcdc_info.ch[0].lcd_size_cfg.height = 79;
1271 1269
1272 platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices)); 1270 platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
1273 1271
1274 #else 1272 #else
1275 /* 1273 /*
1276 * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and 1274 * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
1277 * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF. 1275 * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
1278 */ 1276 */
1279 1277
1280 gpio_request(GPIO_FN_LCDD17, NULL); 1278 gpio_request(GPIO_FN_LCDD17, NULL);
1281 gpio_request(GPIO_FN_LCDD16, NULL); 1279 gpio_request(GPIO_FN_LCDD16, NULL);
1282 gpio_request(GPIO_FN_LCDD15, NULL); 1280 gpio_request(GPIO_FN_LCDD15, NULL);
1283 gpio_request(GPIO_FN_LCDD14, NULL); 1281 gpio_request(GPIO_FN_LCDD14, NULL);
1284 gpio_request(GPIO_FN_LCDD13, NULL); 1282 gpio_request(GPIO_FN_LCDD13, NULL);
1285 gpio_request(GPIO_FN_LCDD12, NULL); 1283 gpio_request(GPIO_FN_LCDD12, NULL);
1286 gpio_request(GPIO_FN_LCDD11, NULL); 1284 gpio_request(GPIO_FN_LCDD11, NULL);
1287 gpio_request(GPIO_FN_LCDD10, NULL); 1285 gpio_request(GPIO_FN_LCDD10, NULL);
1288 gpio_request(GPIO_FN_LCDD9, NULL); 1286 gpio_request(GPIO_FN_LCDD9, NULL);
1289 gpio_request(GPIO_FN_LCDD8, NULL); 1287 gpio_request(GPIO_FN_LCDD8, NULL);
1290 gpio_request(GPIO_FN_LCDD7, NULL); 1288 gpio_request(GPIO_FN_LCDD7, NULL);
1291 gpio_request(GPIO_FN_LCDD6, NULL); 1289 gpio_request(GPIO_FN_LCDD6, NULL);
1292 gpio_request(GPIO_FN_LCDD5, NULL); 1290 gpio_request(GPIO_FN_LCDD5, NULL);
1293 gpio_request(GPIO_FN_LCDD4, NULL); 1291 gpio_request(GPIO_FN_LCDD4, NULL);
1294 gpio_request(GPIO_FN_LCDD3, NULL); 1292 gpio_request(GPIO_FN_LCDD3, NULL);
1295 gpio_request(GPIO_FN_LCDD2, NULL); 1293 gpio_request(GPIO_FN_LCDD2, NULL);
1296 gpio_request(GPIO_FN_LCDD1, NULL); 1294 gpio_request(GPIO_FN_LCDD1, NULL);
1297 gpio_request(GPIO_FN_LCDD0, NULL); 1295 gpio_request(GPIO_FN_LCDD0, NULL);
1298 gpio_request(GPIO_FN_LCDDISP, NULL); 1296 gpio_request(GPIO_FN_LCDDISP, NULL);
1299 gpio_request(GPIO_FN_LCDDCK, NULL); 1297 gpio_request(GPIO_FN_LCDDCK, NULL);
1300 1298
1301 gpio_request(GPIO_PORT189, NULL); /* backlight */ 1299 gpio_request(GPIO_PORT189, NULL); /* backlight */
1302 gpio_direction_output(GPIO_PORT189, 1); 1300 gpio_direction_output(GPIO_PORT189, 1);
1303 1301
1304 gpio_request(GPIO_PORT151, NULL); /* LCDDON */ 1302 gpio_request(GPIO_PORT151, NULL); /* LCDDON */
1305 gpio_direction_output(GPIO_PORT151, 1); 1303 gpio_direction_output(GPIO_PORT151, 1);
1306 1304
1307 lcdc_info.clock_source = LCDC_CLK_BUS; 1305 lcdc_info.clock_source = LCDC_CLK_BUS;
1308 lcdc_info.ch[0].interface_type = RGB18; 1306 lcdc_info.ch[0].interface_type = RGB18;
1309 lcdc_info.ch[0].clock_divider = 2; 1307 lcdc_info.ch[0].clock_divider = 2;
1310 lcdc_info.ch[0].flags = 0; 1308 lcdc_info.ch[0].flags = 0;
1311 lcdc_info.ch[0].lcd_size_cfg.width = 152; 1309 lcdc_info.ch[0].lcd_size_cfg.width = 152;
1312 lcdc_info.ch[0].lcd_size_cfg.height = 91; 1310 lcdc_info.ch[0].lcd_size_cfg.height = 91;
1313 1311
1314 /* enable TouchScreen */ 1312 /* enable TouchScreen */
1315 set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); 1313 set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
1316 1314
1317 tsc_device.irq = IRQ7; 1315 tsc_device.irq = IRQ7;
1318 i2c_register_board_info(0, &tsc_device, 1); 1316 i2c_register_board_info(0, &tsc_device, 1);
1319 #endif /* CONFIG_AP4EVB_QHD */ 1317 #endif /* CONFIG_AP4EVB_QHD */
1320 1318
1321 /* CEU */ 1319 /* CEU */
1322 1320
1323 /* 1321 /*
1324 * TODO: reserve memory for V4L2 DMA buffers, when a suitable API 1322 * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
1325 * becomes available 1323 * becomes available
1326 */ 1324 */
1327 1325
1328 /* MIPI-CSI stuff */ 1326 /* MIPI-CSI stuff */
1329 gpio_request(GPIO_FN_VIO_CKO, NULL); 1327 gpio_request(GPIO_FN_VIO_CKO, NULL);
1330 1328
1331 clk = clk_get(NULL, "vck1_clk"); 1329 clk = clk_get(NULL, "vck1_clk");
1332 if (!IS_ERR(clk)) { 1330 if (!IS_ERR(clk)) {
1333 clk_set_rate(clk, clk_round_rate(clk, 13000000)); 1331 clk_set_rate(clk, clk_round_rate(clk, 13000000));
1334 clk_enable(clk); 1332 clk_enable(clk);
1335 clk_put(clk); 1333 clk_put(clk);
1336 } 1334 }
1337 1335
1338 sh7372_add_standard_devices(); 1336 sh7372_add_standard_devices();
1339 1337
1340 /* HDMI */ 1338 /* HDMI */
1341 gpio_request(GPIO_FN_HDMI_HPD, NULL); 1339 gpio_request(GPIO_FN_HDMI_HPD, NULL);
1342 gpio_request(GPIO_FN_HDMI_CEC, NULL); 1340 gpio_request(GPIO_FN_HDMI_CEC, NULL);
1343 1341
1344 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ 1342 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
1345 #define SRCR4 0xe61580bc 1343 #define SRCR4 0xe61580bc
1346 srcr4 = __raw_readl(SRCR4); 1344 srcr4 = __raw_readl(SRCR4);
1347 __raw_writel(srcr4 | (1 << 13), SRCR4); 1345 __raw_writel(srcr4 | (1 << 13), SRCR4);
1348 udelay(50); 1346 udelay(50);
1349 __raw_writel(srcr4 & ~(1 << 13), SRCR4); 1347 __raw_writel(srcr4 & ~(1 << 13), SRCR4);
1350 1348
1351 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); 1349 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
1352 } 1350 }
1353 1351
1354 static void __init ap4evb_timer_init(void) 1352 static void __init ap4evb_timer_init(void)
1355 { 1353 {
1356 sh7372_clock_init(); 1354 sh7372_clock_init();
1357 shmobile_timer.init(); 1355 shmobile_timer.init();
1358 1356
1359 /* External clock source */ 1357 /* External clock source */
1360 clk_set_rate(&sh7372_dv_clki_clk, 27000000); 1358 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1361 } 1359 }
1362 1360
1363 static struct sys_timer ap4evb_timer = { 1361 static struct sys_timer ap4evb_timer = {
1364 .init = ap4evb_timer_init, 1362 .init = ap4evb_timer_init,
1365 }; 1363 };
1366 1364
1367 MACHINE_START(AP4EVB, "ap4evb") 1365 MACHINE_START(AP4EVB, "ap4evb")
1368 .map_io = ap4evb_map_io, 1366 .map_io = ap4evb_map_io,
1369 .init_irq = sh7372_init_irq, 1367 .init_irq = sh7372_init_irq,
1370 .handle_irq = shmobile_handle_irq_intc, 1368 .handle_irq = shmobile_handle_irq_intc,
1371 .init_machine = ap4evb_init, 1369 .init_machine = ap4evb_init,
1372 .timer = &ap4evb_timer, 1370 .timer = &ap4evb_timer,
1373 MACHINE_END 1371 MACHINE_END
1374 1372
arch/arm/mach-shmobile/board-mackerel.c
Diff comments   View file @ f17c13c
1 /* 1 /*
2 * mackerel board support 2 * mackerel board support
3 * 3 *
4 * Copyright (C) 2010 Renesas Solutions Corp. 4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * 6 *
7 * based on ap4evb 7 * based on ap4evb
8 * Copyright (C) 2010 Magnus Damm 8 * Copyright (C) 2010 Magnus Damm
9 * Copyright (C) 2008 Yoshihiro Shimoda 9 * Copyright (C) 2008 Yoshihiro Shimoda
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License. 13 * the Free Software Foundation; version 2 of the License.
14 * 14 *
15 * This program is distributed in the hope that it will be useful, 15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details. 18 * GNU General Public License for more details.
19 * 19 *
20 * You should have received a copy of the GNU General Public License 20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software 21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 */ 23 */
24 #include <linux/delay.h> 24 #include <linux/delay.h>
25 #include <linux/kernel.h> 25 #include <linux/kernel.h>
26 #include <linux/init.h> 26 #include <linux/init.h>
27 #include <linux/interrupt.h> 27 #include <linux/interrupt.h>
28 #include <linux/irq.h> 28 #include <linux/irq.h>
29 #include <linux/platform_device.h> 29 #include <linux/platform_device.h>
30 #include <linux/gpio.h> 30 #include <linux/gpio.h>
31 #include <linux/input.h> 31 #include <linux/input.h>
32 #include <linux/io.h> 32 #include <linux/io.h>
33 #include <linux/i2c.h> 33 #include <linux/i2c.h>
34 #include <linux/leds.h> 34 #include <linux/leds.h>
35 #include <linux/mfd/sh_mobile_sdhi.h> 35 #include <linux/mfd/sh_mobile_sdhi.h>
36 #include <linux/mfd/tmio.h> 36 #include <linux/mfd/tmio.h>
37 #include <linux/mmc/host.h> 37 #include <linux/mmc/host.h>
38 #include <linux/mmc/sh_mmcif.h> 38 #include <linux/mmc/sh_mmcif.h>
39 #include <linux/mtd/mtd.h> 39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/partitions.h> 40 #include <linux/mtd/partitions.h>
41 #include <linux/mtd/physmap.h> 41 #include <linux/mtd/physmap.h>
42 #include <linux/smsc911x.h> 42 #include <linux/smsc911x.h>
43 #include <linux/sh_intc.h> 43 #include <linux/sh_intc.h>
44 #include <linux/tca6416_keypad.h> 44 #include <linux/tca6416_keypad.h>
45 #include <linux/usb/r8a66597.h> 45 #include <linux/usb/r8a66597.h>
46 46
47 #include <video/sh_mobile_hdmi.h> 47 #include <video/sh_mobile_hdmi.h>
48 #include <video/sh_mobile_lcdc.h> 48 #include <video/sh_mobile_lcdc.h>
49 #include <media/sh_mobile_ceu.h> 49 #include <media/sh_mobile_ceu.h>
50 #include <media/soc_camera.h> 50 #include <media/soc_camera.h>
51 #include <media/soc_camera_platform.h> 51 #include <media/soc_camera_platform.h>
52 #include <sound/sh_fsi.h> 52 #include <sound/sh_fsi.h>
53 53
54 #include <mach/common.h> 54 #include <mach/common.h>
55 #include <mach/sh7372.h> 55 #include <mach/sh7372.h>
56 56
57 #include <asm/mach/arch.h> 57 #include <asm/mach/arch.h>
58 #include <asm/mach/time.h> 58 #include <asm/mach/time.h>
59 #include <asm/mach/map.h> 59 #include <asm/mach/map.h>
60 #include <asm/mach-types.h> 60 #include <asm/mach-types.h>
61 61
62 /* 62 /*
63 * Address Interface BusWidth note 63 * Address Interface BusWidth note
64 * ------------------------------------------------------------------ 64 * ------------------------------------------------------------------
65 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON 65 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON
66 * 0x0800_0000 user area - 66 * 0x0800_0000 user area -
67 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF 67 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF
68 * 0x1400_0000 Ether (LAN9220) 16bit 68 * 0x1400_0000 Ether (LAN9220) 16bit
69 * 0x1600_0000 user area - cannot use with NAND 69 * 0x1600_0000 user area - cannot use with NAND
70 * 0x1800_0000 user area - 70 * 0x1800_0000 user area -
71 * 0x1A00_0000 - 71 * 0x1A00_0000 -
72 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit 72 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit
73 */ 73 */
74 74
75 /* 75 /*
76 * CPU mode 76 * CPU mode
77 * 77 *
78 * SW4 | Boot Area| Master | Remarks 78 * SW4 | Boot Area| Master | Remarks
79 * 1 | 2 | 3 | 4 | 5 | 6 | 8 | | Processor| 79 * 1 | 2 | 3 | 4 | 5 | 6 | 8 | | Processor|
80 * ----+-----+-----+-----+-----+-----+-----+----------+----------+-------------- 80 * ----+-----+-----+-----+-----+-----+-----+----------+----------+--------------
81 * ON | ON | OFF | ON | ON | OFF | OFF | External | System | External ROM 81 * ON | ON | OFF | ON | ON | OFF | OFF | External | System | External ROM
82 * ON | ON | ON | ON | ON | OFF | OFF | External | System | ROM Debug 82 * ON | ON | ON | ON | ON | OFF | OFF | External | System | ROM Debug
83 * ON | ON | X | ON | OFF | OFF | OFF | Built-in | System | ROM Debug 83 * ON | ON | X | ON | OFF | OFF | OFF | Built-in | System | ROM Debug
84 * X | OFF | X | X | X | X | OFF | Built-in | System | MaskROM 84 * X | OFF | X | X | X | X | OFF | Built-in | System | MaskROM
85 * OFF | X | X | X | X | X | OFF | Built-in | System | MaskROM 85 * OFF | X | X | X | X | X | OFF | Built-in | System | MaskROM
86 * X | X | X | OFF | X | X | OFF | Built-in | System | MaskROM 86 * X | X | X | OFF | X | X | OFF | Built-in | System | MaskROM
87 * OFF | ON | OFF | X | X | OFF | ON | External | System | Standalone 87 * OFF | ON | OFF | X | X | OFF | ON | External | System | Standalone
88 * ON | OFF | OFF | X | X | OFF | ON | External | Realtime | Standalone 88 * ON | OFF | OFF | X | X | OFF | ON | External | Realtime | Standalone
89 */ 89 */
90 90
91 /* 91 /*
92 * NOR Flash ROM 92 * NOR Flash ROM
93 * 93 *
94 * SW1 | SW2 | SW7 | NOR Flash ROM 94 * SW1 | SW2 | SW7 | NOR Flash ROM
95 * bit1 | bit1 bit2 | bit1 | Memory allocation 95 * bit1 | bit1 bit2 | bit1 | Memory allocation
96 * ------+------------+------+------------------ 96 * ------+------------+------+------------------
97 * OFF | ON OFF | ON | Area 0 97 * OFF | ON OFF | ON | Area 0
98 * OFF | ON OFF | OFF | Area 4 98 * OFF | ON OFF | OFF | Area 4
99 */ 99 */
100 100
101 /* 101 /*
102 * SMSC 9220 102 * SMSC 9220
103 * 103 *
104 * SW1 SMSC 9220 104 * SW1 SMSC 9220
105 * ----------------------- 105 * -----------------------
106 * ON access disable 106 * ON access disable
107 * OFF access enable 107 * OFF access enable
108 */ 108 */
109 109
110 /* 110 /*
111 * NAND Flash ROM 111 * NAND Flash ROM
112 * 112 *
113 * SW1 | SW2 | SW7 | NAND Flash ROM 113 * SW1 | SW2 | SW7 | NAND Flash ROM
114 * bit1 | bit1 bit2 | bit2 | Memory allocation 114 * bit1 | bit1 bit2 | bit2 | Memory allocation
115 * ------+------------+------+------------------ 115 * ------+------------+------+------------------
116 * OFF | ON OFF | ON | FCE 0 116 * OFF | ON OFF | ON | FCE 0
117 * OFF | ON OFF | OFF | FCE 1 117 * OFF | ON OFF | OFF | FCE 1
118 */ 118 */
119 119
120 /* 120 /*
121 * External interrupt pin settings 121 * External interrupt pin settings
122 * 122 *
123 * IRQX | pin setting | device | level 123 * IRQX | pin setting | device | level
124 * ------+--------------------+--------------------+------- 124 * ------+--------------------+--------------------+-------
125 * IRQ0 | ICR1A.IRQ0SA=0010 | SDHI2 card detect | Low 125 * IRQ0 | ICR1A.IRQ0SA=0010 | SDHI2 card detect | Low
126 * IRQ6 | ICR1A.IRQ6SA=0011 | Ether(LAN9220) | High 126 * IRQ6 | ICR1A.IRQ6SA=0011 | Ether(LAN9220) | High
127 * IRQ7 | ICR1A.IRQ7SA=0010 | LCD Tuch Panel | Low 127 * IRQ7 | ICR1A.IRQ7SA=0010 | LCD Tuch Panel | Low
128 * IRQ8 | ICR2A.IRQ8SA=0010 | MMC/SD card detect | Low 128 * IRQ8 | ICR2A.IRQ8SA=0010 | MMC/SD card detect | Low
129 * IRQ9 | ICR2A.IRQ9SA=0010 | KEY(TCA6408) | Low 129 * IRQ9 | ICR2A.IRQ9SA=0010 | KEY(TCA6408) | Low
130 * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345) | High 130 * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345) | High
131 * IRQ22 | ICR4A.IRQ22SA=0011 | Sensor(AK8975) | High 131 * IRQ22 | ICR4A.IRQ22SA=0011 | Sensor(AK8975) | High
132 */ 132 */
133 133
134 /* 134 /*
135 * USB 135 * USB
136 * 136 *
137 * USB0 : CN22 : Function 137 * USB0 : CN22 : Function
138 * USB1 : CN31 : Function/Host *1 138 * USB1 : CN31 : Function/Host *1
139 * 139 *
140 * J30 (for CN31) *1 140 * J30 (for CN31) *1
141 * ----------+---------------+------------- 141 * ----------+---------------+-------------
142 * 1-2 short | VBUS 5V | Host 142 * 1-2 short | VBUS 5V | Host
143 * open | external VBUS | Function 143 * open | external VBUS | Function
144 * 144 *
145 * *1 145 * *1
146 * CN31 is used as Host in Linux. 146 * CN31 is used as Host in Linux.
147 */ 147 */
148 148
149 /* 149 /*
150 * SDHI0 (CN12) 150 * SDHI0 (CN12)
151 * 151 *
152 * SW56 : OFF 152 * SW56 : OFF
153 * 153 *
154 */ 154 */
155 155
156 /* MMC /SDHI1 (CN7) 156 /* MMC /SDHI1 (CN7)
157 * 157 *
158 * I/O voltage : 1.8v 158 * I/O voltage : 1.8v
159 * 159 *
160 * Power voltage : 1.8v or 3.3v 160 * Power voltage : 1.8v or 3.3v
161 * J22 : select power voltage *1 161 * J22 : select power voltage *1
162 * 1-2 pin : 1.8v 162 * 1-2 pin : 1.8v
163 * 2-3 pin : 3.3v 163 * 2-3 pin : 3.3v
164 * 164 *
165 * *1 165 * *1
166 * Please change J22 depends the card to be used. 166 * Please change J22 depends the card to be used.
167 * MMC's OCR field set to support either voltage for the card inserted. 167 * MMC's OCR field set to support either voltage for the card inserted.
168 * 168 *
169 * SW1 | SW33 169 * SW1 | SW33
170 * | bit1 | bit2 | bit3 | bit4 170 * | bit1 | bit2 | bit3 | bit4
171 * -------------+------+------+------+------- 171 * -------------+------+------+------+-------
172 * MMC0 OFF | OFF | ON | ON | X 172 * MMC0 OFF | OFF | ON | ON | X
173 * MMC1 ON | OFF | ON | X | ON 173 * MMC1 ON | OFF | ON | X | ON
174 * SDHI1 OFF | ON | X | OFF | ON 174 * SDHI1 OFF | ON | X | OFF | ON
175 * 175 *
176 */ 176 */
177 177
178 /* 178 /*
179 * SDHI2 (CN23) 179 * SDHI2 (CN23)
180 * 180 *
181 * microSD card sloct 181 * microSD card sloct
182 * 182 *
183 */ 183 */
184 184
185 /* 185 /*
186 * FIXME !! 186 * FIXME !!
187 * 187 *
188 * gpio_no_direction 188 * gpio_no_direction
189 * are quick_hack. 189 * are quick_hack.
190 * 190 *
191 * current gpio frame work doesn't have 191 * current gpio frame work doesn't have
192 * the method to control only pull up/down/free. 192 * the method to control only pull up/down/free.
193 * this function should be replaced by correct gpio function 193 * this function should be replaced by correct gpio function
194 */ 194 */
195 static void __init gpio_no_direction(u32 addr) 195 static void __init gpio_no_direction(u32 addr)
196 { 196 {
197 __raw_writeb(0x00, addr); 197 __raw_writeb(0x00, addr);
198 } 198 }
199 199
200 /* MTD */ 200 /* MTD */
201 static struct mtd_partition nor_flash_partitions[] = { 201 static struct mtd_partition nor_flash_partitions[] = {
202 { 202 {
203 .name = "loader", 203 .name = "loader",
204 .offset = 0x00000000, 204 .offset = 0x00000000,
205 .size = 512 * 1024, 205 .size = 512 * 1024,
206 .mask_flags = MTD_WRITEABLE, 206 .mask_flags = MTD_WRITEABLE,
207 }, 207 },
208 { 208 {
209 .name = "bootenv", 209 .name = "bootenv",
210 .offset = MTDPART_OFS_APPEND, 210 .offset = MTDPART_OFS_APPEND,
211 .size = 512 * 1024, 211 .size = 512 * 1024,
212 .mask_flags = MTD_WRITEABLE, 212 .mask_flags = MTD_WRITEABLE,
213 }, 213 },
214 { 214 {
215 .name = "kernel_ro", 215 .name = "kernel_ro",
216 .offset = MTDPART_OFS_APPEND, 216 .offset = MTDPART_OFS_APPEND,
217 .size = 8 * 1024 * 1024, 217 .size = 8 * 1024 * 1024,
218 .mask_flags = MTD_WRITEABLE, 218 .mask_flags = MTD_WRITEABLE,
219 }, 219 },
220 { 220 {
221 .name = "kernel", 221 .name = "kernel",
222 .offset = MTDPART_OFS_APPEND, 222 .offset = MTDPART_OFS_APPEND,
223 .size = 8 * 1024 * 1024, 223 .size = 8 * 1024 * 1024,
224 }, 224 },
225 { 225 {
226 .name = "data", 226 .name = "data",
227 .offset = MTDPART_OFS_APPEND, 227 .offset = MTDPART_OFS_APPEND,
228 .size = MTDPART_SIZ_FULL, 228 .size = MTDPART_SIZ_FULL,
229 }, 229 },
230 }; 230 };
231 231
232 static struct physmap_flash_data nor_flash_data = { 232 static struct physmap_flash_data nor_flash_data = {
233 .width = 2, 233 .width = 2,
234 .parts = nor_flash_partitions, 234 .parts = nor_flash_partitions,
235 .nr_parts = ARRAY_SIZE(nor_flash_partitions), 235 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
236 }; 236 };
237 237
238 static struct resource nor_flash_resources[] = { 238 static struct resource nor_flash_resources[] = {
239 [0] = { 239 [0] = {
240 .start = 0x00000000, 240 .start = 0x00000000,
241 .end = 0x08000000 - 1, 241 .end = 0x08000000 - 1,
242 .flags = IORESOURCE_MEM, 242 .flags = IORESOURCE_MEM,
243 } 243 }
244 }; 244 };
245 245
246 static struct platform_device nor_flash_device = { 246 static struct platform_device nor_flash_device = {
247 .name = "physmap-flash", 247 .name = "physmap-flash",
248 .dev = { 248 .dev = {
249 .platform_data = &nor_flash_data, 249 .platform_data = &nor_flash_data,
250 }, 250 },
251 .num_resources = ARRAY_SIZE(nor_flash_resources), 251 .num_resources = ARRAY_SIZE(nor_flash_resources),
252 .resource = nor_flash_resources, 252 .resource = nor_flash_resources,
253 }; 253 };
254 254
255 /* SMSC */ 255 /* SMSC */
256 static struct resource smc911x_resources[] = { 256 static struct resource smc911x_resources[] = {
257 { 257 {
258 .start = 0x14000000, 258 .start = 0x14000000,
259 .end = 0x16000000 - 1, 259 .end = 0x16000000 - 1,
260 .flags = IORESOURCE_MEM, 260 .flags = IORESOURCE_MEM,
261 }, { 261 }, {
262 .start = evt2irq(0x02c0) /* IRQ6A */, 262 .start = evt2irq(0x02c0) /* IRQ6A */,
263 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 263 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
264 }, 264 },
265 }; 265 };
266 266
267 static struct smsc911x_platform_config smsc911x_info = { 267 static struct smsc911x_platform_config smsc911x_info = {
268 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS, 268 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
269 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 269 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
270 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 270 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
271 }; 271 };
272 272
273 static struct platform_device smc911x_device = { 273 static struct platform_device smc911x_device = {
274 .name = "smsc911x", 274 .name = "smsc911x",
275 .id = -1, 275 .id = -1,
276 .num_resources = ARRAY_SIZE(smc911x_resources), 276 .num_resources = ARRAY_SIZE(smc911x_resources),
277 .resource = smc911x_resources, 277 .resource = smc911x_resources,
278 .dev = { 278 .dev = {
279 .platform_data = &smsc911x_info, 279 .platform_data = &smsc911x_info,
280 }, 280 },
281 }; 281 };
282 282
283 /* LCDC */ 283 /* LCDC */
284 static struct fb_videomode mackerel_lcdc_modes[] = { 284 static struct fb_videomode mackerel_lcdc_modes[] = {
285 { 285 {
286 .name = "WVGA Panel", 286 .name = "WVGA Panel",
287 .xres = 800, 287 .xres = 800,
288 .yres = 480, 288 .yres = 480,
289 .left_margin = 220, 289 .left_margin = 220,
290 .right_margin = 110, 290 .right_margin = 110,
291 .hsync_len = 70, 291 .hsync_len = 70,
292 .upper_margin = 20, 292 .upper_margin = 20,
293 .lower_margin = 5, 293 .lower_margin = 5,
294 .vsync_len = 5, 294 .vsync_len = 5,
295 .sync = 0, 295 .sync = 0,
296 }, 296 },
297 }; 297 };
298 298
299 static struct sh_mobile_lcdc_info lcdc_info = { 299 static struct sh_mobile_lcdc_info lcdc_info = {
300 .clock_source = LCDC_CLK_BUS, 300 .clock_source = LCDC_CLK_BUS,
301 .ch[0] = { 301 .ch[0] = {
302 .chan = LCDC_CHAN_MAINLCD, 302 .chan = LCDC_CHAN_MAINLCD,
303 .bpp = 16, 303 .bpp = 16,
304 .lcd_cfg = mackerel_lcdc_modes, 304 .lcd_cfg = mackerel_lcdc_modes,
305 .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes), 305 .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
306 .interface_type = RGB24, 306 .interface_type = RGB24,
307 .clock_divider = 2, 307 .clock_divider = 2,
308 .flags = 0, 308 .flags = 0,
309 .lcd_size_cfg.width = 152, 309 .lcd_size_cfg.width = 152,
310 .lcd_size_cfg.height = 91, 310 .lcd_size_cfg.height = 91,
311 } 311 }
312 }; 312 };
313 313
314 static struct resource lcdc_resources[] = { 314 static struct resource lcdc_resources[] = {
315 [0] = { 315 [0] = {
316 .name = "LCDC", 316 .name = "LCDC",
317 .start = 0xfe940000, 317 .start = 0xfe940000,
318 .end = 0xfe943fff, 318 .end = 0xfe943fff,
319 .flags = IORESOURCE_MEM, 319 .flags = IORESOURCE_MEM,
320 }, 320 },
321 [1] = { 321 [1] = {
322 .start = intcs_evt2irq(0x580), 322 .start = intcs_evt2irq(0x580),
323 .flags = IORESOURCE_IRQ, 323 .flags = IORESOURCE_IRQ,
324 }, 324 },
325 }; 325 };
326 326
327 static struct platform_device lcdc_device = { 327 static struct platform_device lcdc_device = {
328 .name = "sh_mobile_lcdc_fb", 328 .name = "sh_mobile_lcdc_fb",
329 .num_resources = ARRAY_SIZE(lcdc_resources), 329 .num_resources = ARRAY_SIZE(lcdc_resources),
330 .resource = lcdc_resources, 330 .resource = lcdc_resources,
331 .dev = { 331 .dev = {
332 .platform_data = &lcdc_info, 332 .platform_data = &lcdc_info,
333 .coherent_dma_mask = ~0, 333 .coherent_dma_mask = ~0,
334 }, 334 },
335 }; 335 };
336 336
337 /* HDMI */ 337 /* HDMI */
338 static struct sh_mobile_lcdc_info hdmi_lcdc_info = { 338 static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
339 .clock_source = LCDC_CLK_EXTERNAL, 339 .clock_source = LCDC_CLK_EXTERNAL,
340 .ch[0] = { 340 .ch[0] = {
341 .chan = LCDC_CHAN_MAINLCD, 341 .chan = LCDC_CHAN_MAINLCD,
342 .bpp = 16, 342 .bpp = 16,
343 .interface_type = RGB24, 343 .interface_type = RGB24,
344 .clock_divider = 1, 344 .clock_divider = 1,
345 .flags = LCDC_FLAGS_DWPOL, 345 .flags = LCDC_FLAGS_DWPOL,
346 } 346 }
347 }; 347 };
348 348
349 static struct resource hdmi_lcdc_resources[] = { 349 static struct resource hdmi_lcdc_resources[] = {
350 [0] = { 350 [0] = {
351 .name = "LCDC1", 351 .name = "LCDC1",
352 .start = 0xfe944000, 352 .start = 0xfe944000,
353 .end = 0xfe947fff, 353 .end = 0xfe947fff,
354 .flags = IORESOURCE_MEM, 354 .flags = IORESOURCE_MEM,
355 }, 355 },
356 [1] = { 356 [1] = {
357 .start = intcs_evt2irq(0x1780), 357 .start = intcs_evt2irq(0x1780),
358 .flags = IORESOURCE_IRQ, 358 .flags = IORESOURCE_IRQ,
359 }, 359 },
360 }; 360 };
361 361
362 static struct platform_device hdmi_lcdc_device = { 362 static struct platform_device hdmi_lcdc_device = {
363 .name = "sh_mobile_lcdc_fb", 363 .name = "sh_mobile_lcdc_fb",
364 .num_resources = ARRAY_SIZE(hdmi_lcdc_resources), 364 .num_resources = ARRAY_SIZE(hdmi_lcdc_resources),
365 .resource = hdmi_lcdc_resources, 365 .resource = hdmi_lcdc_resources,
366 .id = 1, 366 .id = 1,
367 .dev = { 367 .dev = {
368 .platform_data = &hdmi_lcdc_info, 368 .platform_data = &hdmi_lcdc_info,
369 .coherent_dma_mask = ~0, 369 .coherent_dma_mask = ~0,
370 }, 370 },
371 }; 371 };
372 372
373 static struct sh_mobile_hdmi_info hdmi_info = { 373 static struct sh_mobile_hdmi_info hdmi_info = {
374 .lcd_chan = &hdmi_lcdc_info.ch[0], 374 .lcd_chan = &hdmi_lcdc_info.ch[0],
375 .lcd_dev = &hdmi_lcdc_device.dev, 375 .lcd_dev = &hdmi_lcdc_device.dev,
376 .flags = HDMI_SND_SRC_SPDIF, 376 .flags = HDMI_SND_SRC_SPDIF,
377 }; 377 };
378 378
379 static struct resource hdmi_resources[] = { 379 static struct resource hdmi_resources[] = {
380 [0] = { 380 [0] = {
381 .name = "HDMI", 381 .name = "HDMI",
382 .start = 0xe6be0000, 382 .start = 0xe6be0000,
383 .end = 0xe6be00ff, 383 .end = 0xe6be00ff,
384 .flags = IORESOURCE_MEM, 384 .flags = IORESOURCE_MEM,
385 }, 385 },
386 [1] = { 386 [1] = {
387 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */ 387 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
388 .start = evt2irq(0x17e0), 388 .start = evt2irq(0x17e0),
389 .flags = IORESOURCE_IRQ, 389 .flags = IORESOURCE_IRQ,
390 }, 390 },
391 }; 391 };
392 392
393 static struct platform_device hdmi_device = { 393 static struct platform_device hdmi_device = {
394 .name = "sh-mobile-hdmi", 394 .name = "sh-mobile-hdmi",
395 .num_resources = ARRAY_SIZE(hdmi_resources), 395 .num_resources = ARRAY_SIZE(hdmi_resources),
396 .resource = hdmi_resources, 396 .resource = hdmi_resources,
397 .id = -1, 397 .id = -1,
398 .dev = { 398 .dev = {
399 .platform_data = &hdmi_info, 399 .platform_data = &hdmi_info,
400 }, 400 },
401 }; 401 };
402 402
403 static struct platform_device fsi_hdmi_device = { 403 static struct platform_device fsi_hdmi_device = {
404 .name = "sh_fsi2_b_hdmi", 404 .name = "sh_fsi2_b_hdmi",
405 }; 405 };
406 406
407 static int __init hdmi_init_pm_clock(void) 407 static int __init hdmi_init_pm_clock(void)
408 { 408 {
409 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); 409 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
410 int ret; 410 int ret;
411 long rate; 411 long rate;
412 412
413 if (IS_ERR(hdmi_ick)) { 413 if (IS_ERR(hdmi_ick)) {
414 ret = PTR_ERR(hdmi_ick); 414 ret = PTR_ERR(hdmi_ick);
415 pr_err("Cannot get HDMI ICK: %d\n", ret); 415 pr_err("Cannot get HDMI ICK: %d\n", ret);
416 goto out; 416 goto out;
417 } 417 }
418 418
419 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk); 419 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
420 if (ret < 0) { 420 if (ret < 0) {
421 pr_err("Cannot set PLLC2 parent: %d, %d users\n", 421 pr_err("Cannot set PLLC2 parent: %d, %d users\n",
422 ret, sh7372_pllc2_clk.usecount); 422 ret, sh7372_pllc2_clk.usecount);
423 goto out; 423 goto out;
424 } 424 }
425 425
426 pr_debug("PLLC2 initial frequency %lu\n", 426 pr_debug("PLLC2 initial frequency %lu\n",
427 clk_get_rate(&sh7372_pllc2_clk)); 427 clk_get_rate(&sh7372_pllc2_clk));
428 428
429 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000); 429 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
430 if (rate < 0) { 430 if (rate < 0) {
431 pr_err("Cannot get suitable rate: %ld\n", rate); 431 pr_err("Cannot get suitable rate: %ld\n", rate);
432 ret = rate; 432 ret = rate;
433 goto out; 433 goto out;
434 } 434 }
435 435
436 ret = clk_set_rate(&sh7372_pllc2_clk, rate); 436 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
437 if (ret < 0) { 437 if (ret < 0) {
438 pr_err("Cannot set rate %ld: %d\n", rate, ret); 438 pr_err("Cannot set rate %ld: %d\n", rate, ret);
439 goto out; 439 goto out;
440 } 440 }
441 441
442 ret = clk_enable(&sh7372_pllc2_clk); 442 ret = clk_enable(&sh7372_pllc2_clk);
443 if (ret < 0) { 443 if (ret < 0) {
444 pr_err("Cannot enable pllc2 clock\n"); 444 pr_err("Cannot enable pllc2 clock\n");
445 goto out; 445 goto out;
446 } 446 }
447 447
448 pr_debug("PLLC2 set frequency %lu\n", rate); 448 pr_debug("PLLC2 set frequency %lu\n", rate);
449 449
450 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); 450 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
451 if (ret < 0) { 451 if (ret < 0) {
452 pr_err("Cannot set HDMI parent: %d\n", ret); 452 pr_err("Cannot set HDMI parent: %d\n", ret);
453 goto out; 453 goto out;
454 } 454 }
455 455
456 out: 456 out:
457 if (!IS_ERR(hdmi_ick)) 457 if (!IS_ERR(hdmi_ick))
458 clk_put(hdmi_ick); 458 clk_put(hdmi_ick);
459 return ret; 459 return ret;
460 } 460 }
461 device_initcall(hdmi_init_pm_clock); 461 device_initcall(hdmi_init_pm_clock);
462 462
463 /* USB1 (Host) */ 463 /* USB1 (Host) */
464 static void usb1_host_port_power(int port, int power) 464 static void usb1_host_port_power(int port, int power)
465 { 465 {
466 if (!power) /* only power-on is supported for now */ 466 if (!power) /* only power-on is supported for now */
467 return; 467 return;
468 468
469 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */ 469 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
470 __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008); 470 __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
471 } 471 }
472 472
473 static struct r8a66597_platdata usb1_host_data = { 473 static struct r8a66597_platdata usb1_host_data = {
474 .on_chip = 1, 474 .on_chip = 1,
475 .port_power = usb1_host_port_power, 475 .port_power = usb1_host_port_power,
476 }; 476 };
477 477
478 static struct resource usb1_host_resources[] = { 478 static struct resource usb1_host_resources[] = {
479 [0] = { 479 [0] = {
480 .name = "USBHS", 480 .name = "USBHS",
481 .start = 0xE68B0000, 481 .start = 0xE68B0000,
482 .end = 0xE68B00E6 - 1, 482 .end = 0xE68B00E6 - 1,
483 .flags = IORESOURCE_MEM, 483 .flags = IORESOURCE_MEM,
484 }, 484 },
485 [1] = { 485 [1] = {
486 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */, 486 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
487 .flags = IORESOURCE_IRQ, 487 .flags = IORESOURCE_IRQ,
488 }, 488 },
489 }; 489 };
490 490
491 static struct platform_device usb1_host_device = { 491 static struct platform_device usb1_host_device = {
492 .name = "r8a66597_hcd", 492 .name = "r8a66597_hcd",
493 .id = 1, 493 .id = 1,
494 .dev = { 494 .dev = {
495 .dma_mask = NULL, /* not use dma */ 495 .dma_mask = NULL, /* not use dma */
496 .coherent_dma_mask = 0xffffffff, 496 .coherent_dma_mask = 0xffffffff,
497 .platform_data = &usb1_host_data, 497 .platform_data = &usb1_host_data,
498 }, 498 },
499 .num_resources = ARRAY_SIZE(usb1_host_resources), 499 .num_resources = ARRAY_SIZE(usb1_host_resources),
500 .resource = usb1_host_resources, 500 .resource = usb1_host_resources,
501 }; 501 };
502 502
503 /* LED */ 503 /* LED */
504 static struct gpio_led mackerel_leds[] = { 504 static struct gpio_led mackerel_leds[] = {
505 { 505 {
506 .name = "led0", 506 .name = "led0",
507 .gpio = GPIO_PORT0, 507 .gpio = GPIO_PORT0,
508 .default_state = LEDS_GPIO_DEFSTATE_ON, 508 .default_state = LEDS_GPIO_DEFSTATE_ON,
509 }, 509 },
510 { 510 {
511 .name = "led1", 511 .name = "led1",
512 .gpio = GPIO_PORT1, 512 .gpio = GPIO_PORT1,
513 .default_state = LEDS_GPIO_DEFSTATE_ON, 513 .default_state = LEDS_GPIO_DEFSTATE_ON,
514 }, 514 },
515 { 515 {
516 .name = "led2", 516 .name = "led2",
517 .gpio = GPIO_PORT2, 517 .gpio = GPIO_PORT2,
518 .default_state = LEDS_GPIO_DEFSTATE_ON, 518 .default_state = LEDS_GPIO_DEFSTATE_ON,
519 }, 519 },
520 { 520 {
521 .name = "led3", 521 .name = "led3",
522 .gpio = GPIO_PORT159, 522 .gpio = GPIO_PORT159,
523 .default_state = LEDS_GPIO_DEFSTATE_ON, 523 .default_state = LEDS_GPIO_DEFSTATE_ON,
524 } 524 }
525 }; 525 };
526 526
527 static struct gpio_led_platform_data mackerel_leds_pdata = { 527 static struct gpio_led_platform_data mackerel_leds_pdata = {
528 .leds = mackerel_leds, 528 .leds = mackerel_leds,
529 .num_leds = ARRAY_SIZE(mackerel_leds), 529 .num_leds = ARRAY_SIZE(mackerel_leds),
530 }; 530 };
531 531
532 static struct platform_device leds_device = { 532 static struct platform_device leds_device = {
533 .name = "leds-gpio", 533 .name = "leds-gpio",
534 .id = 0, 534 .id = 0,
535 .dev = { 535 .dev = {
536 .platform_data = &mackerel_leds_pdata, 536 .platform_data = &mackerel_leds_pdata,
537 }, 537 },
538 }; 538 };
539 539
540 /* FSI */ 540 /* FSI */
541 #define IRQ_FSI evt2irq(0x1840) 541 #define IRQ_FSI evt2irq(0x1840)
542 static int __fsi_set_round_rate(struct clk *clk, long rate, int enable) 542 static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
543 { 543 {
544 int ret; 544 int ret;
545 545
546 if (rate <= 0) 546 if (rate <= 0)
547 return 0; 547 return 0;
548 548
549 if (!enable) { 549 if (!enable) {
550 clk_disable(clk); 550 clk_disable(clk);
551 return 0; 551 return 0;
552 } 552 }
553 553
554 ret = clk_set_rate(clk, clk_round_rate(clk, rate)); 554 ret = clk_set_rate(clk, clk_round_rate(clk, rate));
555 if (ret < 0) 555 if (ret < 0)
556 return ret; 556 return ret;
557 557
558 return clk_enable(clk); 558 return clk_enable(clk);
559 } 559 }
560 560
561 static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable) 561 static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
562 { 562 {
563 struct clk *fsib_clk; 563 struct clk *fsib_clk;
564 struct clk *fdiv_clk = &sh7372_fsidivb_clk; 564 struct clk *fdiv_clk = &sh7372_fsidivb_clk;
565 long fsib_rate = 0; 565 long fsib_rate = 0;
566 long fdiv_rate = 0; 566 long fdiv_rate = 0;
567 int ackmd_bpfmd; 567 int ackmd_bpfmd;
568 int ret; 568 int ret;
569 569
570 /* FSIA is slave mode. nothing to do here */ 570 /* FSIA is slave mode. nothing to do here */
571 if (is_porta) 571 if (is_porta)
572 return 0; 572 return 0;
573 573
574 /* clock start */ 574 /* clock start */
575 switch (rate) { 575 switch (rate) {
576 case 44100: 576 case 44100:
577 fsib_rate = rate * 256; 577 fsib_rate = rate * 256;
578 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64; 578 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
579 break; 579 break;
580 case 48000: 580 case 48000:
581 fsib_rate = 85428000; /* around 48kHz x 256 x 7 */ 581 fsib_rate = 85428000; /* around 48kHz x 256 x 7 */
582 fdiv_rate = rate * 256; 582 fdiv_rate = rate * 256;
583 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64; 583 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
584 break; 584 break;
585 default: 585 default:
586 pr_err("unsupported rate in FSI2 port B\n"); 586 pr_err("unsupported rate in FSI2 port B\n");
587 return -EINVAL; 587 return -EINVAL;
588 } 588 }
589 589
590 /* FSI B setting */ 590 /* FSI B setting */
591 fsib_clk = clk_get(dev, "ickb"); 591 fsib_clk = clk_get(dev, "ickb");
592 if (IS_ERR(fsib_clk)) 592 if (IS_ERR(fsib_clk))
593 return -EIO; 593 return -EIO;
594 594
595 /* fsib */ 595 /* fsib */
596 ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable); 596 ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
597 if (ret < 0) 597 if (ret < 0)
598 goto fsi_set_rate_end; 598 goto fsi_set_rate_end;
599 599
600 /* FSI DIV */ 600 /* FSI DIV */
601 ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable); 601 ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
602 if (ret < 0) { 602 if (ret < 0) {
603 /* disable FSI B */ 603 /* disable FSI B */
604 if (enable) 604 if (enable)
605 __fsi_set_round_rate(fsib_clk, fsib_rate, 0); 605 __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
606 goto fsi_set_rate_end; 606 goto fsi_set_rate_end;
607 } 607 }
608 608
609 ret = ackmd_bpfmd; 609 ret = ackmd_bpfmd;
610 610
611 fsi_set_rate_end: 611 fsi_set_rate_end:
612 clk_put(fsib_clk); 612 clk_put(fsib_clk);
613 return ret; 613 return ret;
614 } 614 }
615 615
616 static struct sh_fsi_platform_info fsi_info = { 616 static struct sh_fsi_platform_info fsi_info = {
617 .porta_flags = SH_FSI_BRS_INV | 617 .porta_flags = SH_FSI_BRS_INV,
618 SH_FSI_OFMT(PCM) |
619 SH_FSI_IFMT(PCM),
620 618
621 .portb_flags = SH_FSI_BRS_INV | 619 .portb_flags = SH_FSI_BRS_INV |
622 SH_FSI_BRM_INV | 620 SH_FSI_BRM_INV |
623 SH_FSI_LRS_INV | 621 SH_FSI_LRS_INV |
624 SH_FSI_OFMT(SPDIF), 622 SH_FSI_FMT_SPDIF,
625 623
626 .set_rate = fsi_set_rate, 624 .set_rate = fsi_set_rate,
627 }; 625 };
628 626
629 static struct resource fsi_resources[] = { 627 static struct resource fsi_resources[] = {
630 [0] = { 628 [0] = {
631 .name = "FSI", 629 .name = "FSI",
632 .start = 0xFE3C0000, 630 .start = 0xFE3C0000,
633 .end = 0xFE3C0400 - 1, 631 .end = 0xFE3C0400 - 1,
634 .flags = IORESOURCE_MEM, 632 .flags = IORESOURCE_MEM,
635 }, 633 },
636 [1] = { 634 [1] = {
637 .start = IRQ_FSI, 635 .start = IRQ_FSI,
638 .flags = IORESOURCE_IRQ, 636 .flags = IORESOURCE_IRQ,
639 }, 637 },
640 }; 638 };
641 639
642 static struct platform_device fsi_device = { 640 static struct platform_device fsi_device = {
643 .name = "sh_fsi2", 641 .name = "sh_fsi2",
644 .id = -1, 642 .id = -1,
645 .num_resources = ARRAY_SIZE(fsi_resources), 643 .num_resources = ARRAY_SIZE(fsi_resources),
646 .resource = fsi_resources, 644 .resource = fsi_resources,
647 .dev = { 645 .dev = {
648 .platform_data = &fsi_info, 646 .platform_data = &fsi_info,
649 }, 647 },
650 }; 648 };
651 649
652 static struct platform_device fsi_ak4643_device = { 650 static struct platform_device fsi_ak4643_device = {
653 .name = "sh_fsi2_a_ak4643", 651 .name = "sh_fsi2_a_ak4643",
654 }; 652 };
655 653
656 /* 654 /*
657 * The card detect pin of the top SD/MMC slot (CN7) is active low and is 655 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
658 * connected to GPIO A22 of SH7372 (GPIO_PORT41). 656 * connected to GPIO A22 of SH7372 (GPIO_PORT41).
659 */ 657 */
660 static int slot_cn7_get_cd(struct platform_device *pdev) 658 static int slot_cn7_get_cd(struct platform_device *pdev)
661 { 659 {
662 return !gpio_get_value(GPIO_PORT41); 660 return !gpio_get_value(GPIO_PORT41);
663 } 661 }
664 662
665 /* SDHI0 */ 663 /* SDHI0 */
666 static struct sh_mobile_sdhi_info sdhi0_info = { 664 static struct sh_mobile_sdhi_info sdhi0_info = {
667 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 665 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
668 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 666 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
669 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, 667 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
670 }; 668 };
671 669
672 static struct resource sdhi0_resources[] = { 670 static struct resource sdhi0_resources[] = {
673 [0] = { 671 [0] = {
674 .name = "SDHI0", 672 .name = "SDHI0",
675 .start = 0xe6850000, 673 .start = 0xe6850000,
676 .end = 0xe68501ff, 674 .end = 0xe68501ff,
677 .flags = IORESOURCE_MEM, 675 .flags = IORESOURCE_MEM,
678 }, 676 },
679 [1] = { 677 [1] = {
680 .start = evt2irq(0x0e00) /* SDHI0 */, 678 .start = evt2irq(0x0e00) /* SDHI0 */,
681 .flags = IORESOURCE_IRQ, 679 .flags = IORESOURCE_IRQ,
682 }, 680 },
683 }; 681 };
684 682
685 static struct platform_device sdhi0_device = { 683 static struct platform_device sdhi0_device = {
686 .name = "sh_mobile_sdhi", 684 .name = "sh_mobile_sdhi",
687 .num_resources = ARRAY_SIZE(sdhi0_resources), 685 .num_resources = ARRAY_SIZE(sdhi0_resources),
688 .resource = sdhi0_resources, 686 .resource = sdhi0_resources,
689 .id = 0, 687 .id = 0,
690 .dev = { 688 .dev = {
691 .platform_data = &sdhi0_info, 689 .platform_data = &sdhi0_info,
692 }, 690 },
693 }; 691 };
694 692
695 #if !defined(CONFIG_MMC_SH_MMCIF) 693 #if !defined(CONFIG_MMC_SH_MMCIF)
696 /* SDHI1 */ 694 /* SDHI1 */
697 static struct sh_mobile_sdhi_info sdhi1_info = { 695 static struct sh_mobile_sdhi_info sdhi1_info = {
698 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, 696 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
699 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, 697 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
700 .tmio_ocr_mask = MMC_VDD_165_195, 698 .tmio_ocr_mask = MMC_VDD_165_195,
701 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, 699 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
702 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 700 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
703 MMC_CAP_NEEDS_POLL, 701 MMC_CAP_NEEDS_POLL,
704 .get_cd = slot_cn7_get_cd, 702 .get_cd = slot_cn7_get_cd,
705 }; 703 };
706 704
707 static struct resource sdhi1_resources[] = { 705 static struct resource sdhi1_resources[] = {
708 [0] = { 706 [0] = {
709 .name = "SDHI1", 707 .name = "SDHI1",
710 .start = 0xe6860000, 708 .start = 0xe6860000,
711 .end = 0xe68601ff, 709 .end = 0xe68601ff,
712 .flags = IORESOURCE_MEM, 710 .flags = IORESOURCE_MEM,
713 }, 711 },
714 [1] = { 712 [1] = {
715 .start = evt2irq(0x0e80), 713 .start = evt2irq(0x0e80),
716 .flags = IORESOURCE_IRQ, 714 .flags = IORESOURCE_IRQ,
717 }, 715 },
718 }; 716 };
719 717
720 static struct platform_device sdhi1_device = { 718 static struct platform_device sdhi1_device = {
721 .name = "sh_mobile_sdhi", 719 .name = "sh_mobile_sdhi",
722 .num_resources = ARRAY_SIZE(sdhi1_resources), 720 .num_resources = ARRAY_SIZE(sdhi1_resources),
723 .resource = sdhi1_resources, 721 .resource = sdhi1_resources,
724 .id = 1, 722 .id = 1,
725 .dev = { 723 .dev = {
726 .platform_data = &sdhi1_info, 724 .platform_data = &sdhi1_info,
727 }, 725 },
728 }; 726 };
729 #endif 727 #endif
730 728
731 /* 729 /*
732 * The card detect pin of the top SD/MMC slot (CN23) is active low and is 730 * The card detect pin of the top SD/MMC slot (CN23) is active low and is
733 * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162). 731 * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162).
734 */ 732 */
735 static int slot_cn23_get_cd(struct platform_device *pdev) 733 static int slot_cn23_get_cd(struct platform_device *pdev)
736 { 734 {
737 return !gpio_get_value(GPIO_PORT162); 735 return !gpio_get_value(GPIO_PORT162);
738 } 736 }
739 737
740 /* SDHI2 */ 738 /* SDHI2 */
741 static struct sh_mobile_sdhi_info sdhi2_info = { 739 static struct sh_mobile_sdhi_info sdhi2_info = {
742 .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX, 740 .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX,
743 .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX, 741 .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX,
744 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, 742 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
745 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 743 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
746 MMC_CAP_NEEDS_POLL, 744 MMC_CAP_NEEDS_POLL,
747 .get_cd = slot_cn23_get_cd, 745 .get_cd = slot_cn23_get_cd,
748 }; 746 };
749 747
750 static struct resource sdhi2_resources[] = { 748 static struct resource sdhi2_resources[] = {
751 [0] = { 749 [0] = {
752 .name = "SDHI2", 750 .name = "SDHI2",
753 .start = 0xe6870000, 751 .start = 0xe6870000,
754 .end = 0xe68701ff, 752 .end = 0xe68701ff,
755 .flags = IORESOURCE_MEM, 753 .flags = IORESOURCE_MEM,
756 }, 754 },
757 [1] = { 755 [1] = {
758 .start = evt2irq(0x1200), 756 .start = evt2irq(0x1200),
759 .flags = IORESOURCE_IRQ, 757 .flags = IORESOURCE_IRQ,
760 }, 758 },
761 }; 759 };
762 760
763 static struct platform_device sdhi2_device = { 761 static struct platform_device sdhi2_device = {
764 .name = "sh_mobile_sdhi", 762 .name = "sh_mobile_sdhi",
765 .num_resources = ARRAY_SIZE(sdhi2_resources), 763 .num_resources = ARRAY_SIZE(sdhi2_resources),
766 .resource = sdhi2_resources, 764 .resource = sdhi2_resources,
767 .id = 2, 765 .id = 2,
768 .dev = { 766 .dev = {
769 .platform_data = &sdhi2_info, 767 .platform_data = &sdhi2_info,
770 }, 768 },
771 }; 769 };
772 770
773 /* SH_MMCIF */ 771 /* SH_MMCIF */
774 static struct resource sh_mmcif_resources[] = { 772 static struct resource sh_mmcif_resources[] = {
775 [0] = { 773 [0] = {
776 .name = "MMCIF", 774 .name = "MMCIF",
777 .start = 0xE6BD0000, 775 .start = 0xE6BD0000,
778 .end = 0xE6BD00FF, 776 .end = 0xE6BD00FF,
779 .flags = IORESOURCE_MEM, 777 .flags = IORESOURCE_MEM,
780 }, 778 },
781 [1] = { 779 [1] = {
782 /* MMC ERR */ 780 /* MMC ERR */
783 .start = evt2irq(0x1ac0), 781 .start = evt2irq(0x1ac0),
784 .flags = IORESOURCE_IRQ, 782 .flags = IORESOURCE_IRQ,
785 }, 783 },
786 [2] = { 784 [2] = {
787 /* MMC NOR */ 785 /* MMC NOR */
788 .start = evt2irq(0x1ae0), 786 .start = evt2irq(0x1ae0),
789 .flags = IORESOURCE_IRQ, 787 .flags = IORESOURCE_IRQ,
790 }, 788 },
791 }; 789 };
792 790
793 static struct sh_mmcif_plat_data sh_mmcif_plat = { 791 static struct sh_mmcif_plat_data sh_mmcif_plat = {
794 .sup_pclk = 0, 792 .sup_pclk = 0,
795 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 793 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
796 .caps = MMC_CAP_4_BIT_DATA | 794 .caps = MMC_CAP_4_BIT_DATA |
797 MMC_CAP_8_BIT_DATA | 795 MMC_CAP_8_BIT_DATA |
798 MMC_CAP_NEEDS_POLL, 796 MMC_CAP_NEEDS_POLL,
799 .get_cd = slot_cn7_get_cd, 797 .get_cd = slot_cn7_get_cd,
800 }; 798 };
801 799
802 static struct platform_device sh_mmcif_device = { 800 static struct platform_device sh_mmcif_device = {
803 .name = "sh_mmcif", 801 .name = "sh_mmcif",
804 .id = 0, 802 .id = 0,
805 .dev = { 803 .dev = {
806 .dma_mask = NULL, 804 .dma_mask = NULL,
807 .coherent_dma_mask = 0xffffffff, 805 .coherent_dma_mask = 0xffffffff,
808 .platform_data = &sh_mmcif_plat, 806 .platform_data = &sh_mmcif_plat,
809 }, 807 },
810 .num_resources = ARRAY_SIZE(sh_mmcif_resources), 808 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
811 .resource = sh_mmcif_resources, 809 .resource = sh_mmcif_resources,
812 }; 810 };
813 811
814 812
815 static int mackerel_camera_add(struct soc_camera_link *icl, struct device *dev); 813 static int mackerel_camera_add(struct soc_camera_link *icl, struct device *dev);
816 static void mackerel_camera_del(struct soc_camera_link *icl); 814 static void mackerel_camera_del(struct soc_camera_link *icl);
817 815
818 static int camera_set_capture(struct soc_camera_platform_info *info, 816 static int camera_set_capture(struct soc_camera_platform_info *info,
819 int enable) 817 int enable)
820 { 818 {
821 return 0; /* camera sensor always enabled */ 819 return 0; /* camera sensor always enabled */
822 } 820 }
823 821
824 static struct soc_camera_platform_info camera_info = { 822 static struct soc_camera_platform_info camera_info = {
825 .format_name = "UYVY", 823 .format_name = "UYVY",
826 .format_depth = 16, 824 .format_depth = 16,
827 .format = { 825 .format = {
828 .code = V4L2_MBUS_FMT_UYVY8_2X8, 826 .code = V4L2_MBUS_FMT_UYVY8_2X8,
829 .colorspace = V4L2_COLORSPACE_SMPTE170M, 827 .colorspace = V4L2_COLORSPACE_SMPTE170M,
830 .field = V4L2_FIELD_NONE, 828 .field = V4L2_FIELD_NONE,
831 .width = 640, 829 .width = 640,
832 .height = 480, 830 .height = 480,
833 }, 831 },
834 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | 832 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
835 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 | 833 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 |
836 SOCAM_DATA_ACTIVE_HIGH, 834 SOCAM_DATA_ACTIVE_HIGH,
837 .set_capture = camera_set_capture, 835 .set_capture = camera_set_capture,
838 }; 836 };
839 837
840 static struct soc_camera_link camera_link = { 838 static struct soc_camera_link camera_link = {
841 .bus_id = 0, 839 .bus_id = 0,
842 .add_device = mackerel_camera_add, 840 .add_device = mackerel_camera_add,
843 .del_device = mackerel_camera_del, 841 .del_device = mackerel_camera_del,
844 .module_name = "soc_camera_platform", 842 .module_name = "soc_camera_platform",
845 .priv = &camera_info, 843 .priv = &camera_info,
846 }; 844 };
847 845
848 static void dummy_release(struct device *dev) 846 static void dummy_release(struct device *dev)
849 { 847 {
850 } 848 }
851 849
852 static struct platform_device camera_device = { 850 static struct platform_device camera_device = {
853 .name = "soc_camera_platform", 851 .name = "soc_camera_platform",
854 .dev = { 852 .dev = {
855 .platform_data = &camera_info, 853 .platform_data = &camera_info,
856 .release = dummy_release, 854 .release = dummy_release,
857 }, 855 },
858 }; 856 };
859 857
860 static int mackerel_camera_add(struct soc_camera_link *icl, 858 static int mackerel_camera_add(struct soc_camera_link *icl,
861 struct device *dev) 859 struct device *dev)
862 { 860 {
863 if (icl != &camera_link) 861 if (icl != &camera_link)
864 return -ENODEV; 862 return -ENODEV;
865 863
866 camera_info.dev = dev; 864 camera_info.dev = dev;
867 865
868 return platform_device_register(&camera_device); 866 return platform_device_register(&camera_device);
869 } 867 }
870 868
871 static void mackerel_camera_del(struct soc_camera_link *icl) 869 static void mackerel_camera_del(struct soc_camera_link *icl)
872 { 870 {
873 if (icl != &camera_link) 871 if (icl != &camera_link)
874 return; 872 return;
875 873
876 platform_device_unregister(&camera_device); 874 platform_device_unregister(&camera_device);
877 memset(&camera_device.dev.kobj, 0, 875 memset(&camera_device.dev.kobj, 0,
878 sizeof(camera_device.dev.kobj)); 876 sizeof(camera_device.dev.kobj));
879 } 877 }
880 878
881 static struct sh_mobile_ceu_info sh_mobile_ceu_info = { 879 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
882 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 880 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
883 }; 881 };
884 882
885 static struct resource ceu_resources[] = { 883 static struct resource ceu_resources[] = {
886 [0] = { 884 [0] = {
887 .name = "CEU", 885 .name = "CEU",
888 .start = 0xfe910000, 886 .start = 0xfe910000,
889 .end = 0xfe91009f, 887 .end = 0xfe91009f,
890 .flags = IORESOURCE_MEM, 888 .flags = IORESOURCE_MEM,
891 }, 889 },
892 [1] = { 890 [1] = {
893 .start = intcs_evt2irq(0x880), 891 .start = intcs_evt2irq(0x880),
894 .flags = IORESOURCE_IRQ, 892 .flags = IORESOURCE_IRQ,
895 }, 893 },
896 [2] = { 894 [2] = {
897 /* place holder for contiguous memory */ 895 /* place holder for contiguous memory */
898 }, 896 },
899 }; 897 };
900 898
901 static struct platform_device ceu_device = { 899 static struct platform_device ceu_device = {
902 .name = "sh_mobile_ceu", 900 .name = "sh_mobile_ceu",
903 .id = 0, /* "ceu0" clock */ 901 .id = 0, /* "ceu0" clock */
904 .num_resources = ARRAY_SIZE(ceu_resources), 902 .num_resources = ARRAY_SIZE(ceu_resources),
905 .resource = ceu_resources, 903 .resource = ceu_resources,
906 .dev = { 904 .dev = {
907 .platform_data = &sh_mobile_ceu_info, 905 .platform_data = &sh_mobile_ceu_info,
908 }, 906 },
909 }; 907 };
910 908
911 static struct platform_device mackerel_camera = { 909 static struct platform_device mackerel_camera = {
912 .name = "soc-camera-pdrv", 910 .name = "soc-camera-pdrv",
913 .id = 0, 911 .id = 0,
914 .dev = { 912 .dev = {
915 .platform_data = &camera_link, 913 .platform_data = &camera_link,
916 }, 914 },
917 }; 915 };
918 916
919 static struct platform_device *mackerel_devices[] __initdata = { 917 static struct platform_device *mackerel_devices[] __initdata = {
920 &nor_flash_device, 918 &nor_flash_device,
921 &smc911x_device, 919 &smc911x_device,
922 &lcdc_device, 920 &lcdc_device,
923 &usb1_host_device, 921 &usb1_host_device,
924 &leds_device, 922 &leds_device,
925 &fsi_device, 923 &fsi_device,
926 &fsi_ak4643_device, 924 &fsi_ak4643_device,
927 &fsi_hdmi_device, 925 &fsi_hdmi_device,
928 &sdhi0_device, 926 &sdhi0_device,
929 #if !defined(CONFIG_MMC_SH_MMCIF) 927 #if !defined(CONFIG_MMC_SH_MMCIF)
930 &sdhi1_device, 928 &sdhi1_device,
931 #endif 929 #endif
932 &sdhi2_device, 930 &sdhi2_device,
933 &sh_mmcif_device, 931 &sh_mmcif_device,
934 &ceu_device, 932 &ceu_device,
935 &mackerel_camera, 933 &mackerel_camera,
936 &hdmi_lcdc_device, 934 &hdmi_lcdc_device,
937 &hdmi_device, 935 &hdmi_device,
938 }; 936 };
939 937
940 /* Keypad Initialization */ 938 /* Keypad Initialization */
941 #define KEYPAD_BUTTON(ev_type, ev_code, act_low) \ 939 #define KEYPAD_BUTTON(ev_type, ev_code, act_low) \
942 { \ 940 { \
943 .type = ev_type, \ 941 .type = ev_type, \
944 .code = ev_code, \ 942 .code = ev_code, \
945 .active_low = act_low, \ 943 .active_low = act_low, \
946 } 944 }
947 945
948 #define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1) 946 #define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1)
949 947
950 static struct tca6416_button mackerel_gpio_keys[] = { 948 static struct tca6416_button mackerel_gpio_keys[] = {
951 KEYPAD_BUTTON_LOW(KEY_HOME), 949 KEYPAD_BUTTON_LOW(KEY_HOME),
952 KEYPAD_BUTTON_LOW(KEY_MENU), 950 KEYPAD_BUTTON_LOW(KEY_MENU),
953 KEYPAD_BUTTON_LOW(KEY_BACK), 951 KEYPAD_BUTTON_LOW(KEY_BACK),
954 KEYPAD_BUTTON_LOW(KEY_POWER), 952 KEYPAD_BUTTON_LOW(KEY_POWER),
955 }; 953 };
956 954
957 static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = { 955 static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = {
958 .buttons = mackerel_gpio_keys, 956 .buttons = mackerel_gpio_keys,
959 .nbuttons = ARRAY_SIZE(mackerel_gpio_keys), 957 .nbuttons = ARRAY_SIZE(mackerel_gpio_keys),
960 .rep = 1, 958 .rep = 1,
961 .use_polling = 0, 959 .use_polling = 0,
962 .pinmask = 0x000F, 960 .pinmask = 0x000F,
963 }; 961 };
964 962
965 /* I2C */ 963 /* I2C */
966 #define IRQ7 evt2irq(0x02e0) 964 #define IRQ7 evt2irq(0x02e0)
967 #define IRQ9 evt2irq(0x0320) 965 #define IRQ9 evt2irq(0x0320)
968 966
969 static struct i2c_board_info i2c0_devices[] = { 967 static struct i2c_board_info i2c0_devices[] = {
970 { 968 {
971 I2C_BOARD_INFO("ak4643", 0x13), 969 I2C_BOARD_INFO("ak4643", 0x13),
972 }, 970 },
973 /* Keypad */ 971 /* Keypad */
974 { 972 {
975 I2C_BOARD_INFO("tca6408-keys", 0x20), 973 I2C_BOARD_INFO("tca6408-keys", 0x20),
976 .platform_data = &mackerel_tca6416_keys_info, 974 .platform_data = &mackerel_tca6416_keys_info,
977 .irq = IRQ9, 975 .irq = IRQ9,
978 }, 976 },
979 /* Touchscreen */ 977 /* Touchscreen */
980 { 978 {
981 I2C_BOARD_INFO("st1232-ts", 0x55), 979 I2C_BOARD_INFO("st1232-ts", 0x55),
982 .irq = IRQ7, 980 .irq = IRQ7,
983 }, 981 },
984 }; 982 };
985 983
986 #define IRQ21 evt2irq(0x32a0) 984 #define IRQ21 evt2irq(0x32a0)
987 985
988 static struct i2c_board_info i2c1_devices[] = { 986 static struct i2c_board_info i2c1_devices[] = {
989 /* Accelerometer */ 987 /* Accelerometer */
990 { 988 {
991 I2C_BOARD_INFO("adxl34x", 0x53), 989 I2C_BOARD_INFO("adxl34x", 0x53),
992 .irq = IRQ21, 990 .irq = IRQ21,
993 }, 991 },
994 }; 992 };
995 993
996 static struct map_desc mackerel_io_desc[] __initdata = { 994 static struct map_desc mackerel_io_desc[] __initdata = {
997 /* create a 1:1 entity map for 0xe6xxxxxx 995 /* create a 1:1 entity map for 0xe6xxxxxx
998 * used by CPGA, INTC and PFC. 996 * used by CPGA, INTC and PFC.
999 */ 997 */
1000 { 998 {
1001 .virtual = 0xe6000000, 999 .virtual = 0xe6000000,
1002 .pfn = __phys_to_pfn(0xe6000000), 1000 .pfn = __phys_to_pfn(0xe6000000),
1003 .length = 256 << 20, 1001 .length = 256 << 20,
1004 .type = MT_DEVICE_NONSHARED 1002 .type = MT_DEVICE_NONSHARED
1005 }, 1003 },
1006 }; 1004 };
1007 1005
1008 static void __init mackerel_map_io(void) 1006 static void __init mackerel_map_io(void)
1009 { 1007 {
1010 iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc)); 1008 iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
1011 1009
1012 /* setup early devices and console here as well */ 1010 /* setup early devices and console here as well */
1013 sh7372_add_early_devices(); 1011 sh7372_add_early_devices();
1014 shmobile_setup_console(); 1012 shmobile_setup_console();
1015 } 1013 }
1016 1014
1017 #define GPIO_PORT9CR 0xE6051009 1015 #define GPIO_PORT9CR 0xE6051009
1018 #define GPIO_PORT10CR 0xE605100A 1016 #define GPIO_PORT10CR 0xE605100A
1019 #define SRCR4 0xe61580bc 1017 #define SRCR4 0xe61580bc
1020 #define USCCR1 0xE6058144 1018 #define USCCR1 0xE6058144
1021 static void __init mackerel_init(void) 1019 static void __init mackerel_init(void)
1022 { 1020 {
1023 u32 srcr4; 1021 u32 srcr4;
1024 struct clk *clk; 1022 struct clk *clk;
1025 1023
1026 sh7372_pinmux_init(); 1024 sh7372_pinmux_init();
1027 1025
1028 /* enable SCIFA0 */ 1026 /* enable SCIFA0 */
1029 gpio_request(GPIO_FN_SCIFA0_TXD, NULL); 1027 gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
1030 gpio_request(GPIO_FN_SCIFA0_RXD, NULL); 1028 gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
1031 1029
1032 /* enable SMSC911X */ 1030 /* enable SMSC911X */
1033 gpio_request(GPIO_FN_CS5A, NULL); 1031 gpio_request(GPIO_FN_CS5A, NULL);
1034 gpio_request(GPIO_FN_IRQ6_39, NULL); 1032 gpio_request(GPIO_FN_IRQ6_39, NULL);
1035 1033
1036 /* LCDC */ 1034 /* LCDC */
1037 gpio_request(GPIO_FN_LCDD23, NULL); 1035 gpio_request(GPIO_FN_LCDD23, NULL);
1038 gpio_request(GPIO_FN_LCDD22, NULL); 1036 gpio_request(GPIO_FN_LCDD22, NULL);
1039 gpio_request(GPIO_FN_LCDD21, NULL); 1037 gpio_request(GPIO_FN_LCDD21, NULL);
1040 gpio_request(GPIO_FN_LCDD20, NULL); 1038 gpio_request(GPIO_FN_LCDD20, NULL);
1041 gpio_request(GPIO_FN_LCDD19, NULL); 1039 gpio_request(GPIO_FN_LCDD19, NULL);
1042 gpio_request(GPIO_FN_LCDD18, NULL); 1040 gpio_request(GPIO_FN_LCDD18, NULL);
1043 gpio_request(GPIO_FN_LCDD17, NULL); 1041 gpio_request(GPIO_FN_LCDD17, NULL);
1044 gpio_request(GPIO_FN_LCDD16, NULL); 1042 gpio_request(GPIO_FN_LCDD16, NULL);
1045 gpio_request(GPIO_FN_LCDD15, NULL); 1043 gpio_request(GPIO_FN_LCDD15, NULL);
1046 gpio_request(GPIO_FN_LCDD14, NULL); 1044 gpio_request(GPIO_FN_LCDD14, NULL);
1047 gpio_request(GPIO_FN_LCDD13, NULL); 1045 gpio_request(GPIO_FN_LCDD13, NULL);
1048 gpio_request(GPIO_FN_LCDD12, NULL); 1046 gpio_request(GPIO_FN_LCDD12, NULL);
1049 gpio_request(GPIO_FN_LCDD11, NULL); 1047 gpio_request(GPIO_FN_LCDD11, NULL);
1050 gpio_request(GPIO_FN_LCDD10, NULL); 1048 gpio_request(GPIO_FN_LCDD10, NULL);
1051 gpio_request(GPIO_FN_LCDD9, NULL); 1049 gpio_request(GPIO_FN_LCDD9, NULL);
1052 gpio_request(GPIO_FN_LCDD8, NULL); 1050 gpio_request(GPIO_FN_LCDD8, NULL);
1053 gpio_request(GPIO_FN_LCDD7, NULL); 1051 gpio_request(GPIO_FN_LCDD7, NULL);
1054 gpio_request(GPIO_FN_LCDD6, NULL); 1052 gpio_request(GPIO_FN_LCDD6, NULL);
1055 gpio_request(GPIO_FN_LCDD5, NULL); 1053 gpio_request(GPIO_FN_LCDD5, NULL);
1056 gpio_request(GPIO_FN_LCDD4, NULL); 1054 gpio_request(GPIO_FN_LCDD4, NULL);
1057 gpio_request(GPIO_FN_LCDD3, NULL); 1055 gpio_request(GPIO_FN_LCDD3, NULL);
1058 gpio_request(GPIO_FN_LCDD2, NULL); 1056 gpio_request(GPIO_FN_LCDD2, NULL);
1059 gpio_request(GPIO_FN_LCDD1, NULL); 1057 gpio_request(GPIO_FN_LCDD1, NULL);
1060 gpio_request(GPIO_FN_LCDD0, NULL); 1058 gpio_request(GPIO_FN_LCDD0, NULL);
1061 gpio_request(GPIO_FN_LCDDISP, NULL); 1059 gpio_request(GPIO_FN_LCDDISP, NULL);
1062 gpio_request(GPIO_FN_LCDDCK, NULL); 1060 gpio_request(GPIO_FN_LCDDCK, NULL);
1063 1061
1064 gpio_request(GPIO_PORT31, NULL); /* backlight */ 1062 gpio_request(GPIO_PORT31, NULL); /* backlight */
1065 gpio_direction_output(GPIO_PORT31, 1); 1063 gpio_direction_output(GPIO_PORT31, 1);
1066 1064
1067 gpio_request(GPIO_PORT151, NULL); /* LCDDON */ 1065 gpio_request(GPIO_PORT151, NULL); /* LCDDON */
1068 gpio_direction_output(GPIO_PORT151, 1); 1066 gpio_direction_output(GPIO_PORT151, 1);
1069 1067
1070 /* USB enable */ 1068 /* USB enable */
1071 gpio_request(GPIO_FN_VBUS0_1, NULL); 1069 gpio_request(GPIO_FN_VBUS0_1, NULL);
1072 gpio_request(GPIO_FN_IDIN_1_18, NULL); 1070 gpio_request(GPIO_FN_IDIN_1_18, NULL);
1073 gpio_request(GPIO_FN_PWEN_1_115, NULL); 1071 gpio_request(GPIO_FN_PWEN_1_115, NULL);
1074 gpio_request(GPIO_FN_OVCN_1_114, NULL); 1072 gpio_request(GPIO_FN_OVCN_1_114, NULL);
1075 gpio_request(GPIO_FN_EXTLP_1, NULL); 1073 gpio_request(GPIO_FN_EXTLP_1, NULL);
1076 gpio_request(GPIO_FN_OVCN2_1, NULL); 1074 gpio_request(GPIO_FN_OVCN2_1, NULL);
1077 1075
1078 /* setup USB phy */ 1076 /* setup USB phy */
1079 __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */ 1077 __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */
1080 1078
1081 /* enable FSI2 port A (ak4643) */ 1079 /* enable FSI2 port A (ak4643) */
1082 gpio_request(GPIO_FN_FSIAIBT, NULL); 1080 gpio_request(GPIO_FN_FSIAIBT, NULL);
1083 gpio_request(GPIO_FN_FSIAILR, NULL); 1081 gpio_request(GPIO_FN_FSIAILR, NULL);
1084 gpio_request(GPIO_FN_FSIAISLD, NULL); 1082 gpio_request(GPIO_FN_FSIAISLD, NULL);
1085 gpio_request(GPIO_FN_FSIAOSLD, NULL); 1083 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1086 gpio_request(GPIO_PORT161, NULL); 1084 gpio_request(GPIO_PORT161, NULL);
1087 gpio_direction_output(GPIO_PORT161, 0); /* slave */ 1085 gpio_direction_output(GPIO_PORT161, 0); /* slave */
1088 1086
1089 gpio_request(GPIO_PORT9, NULL); 1087 gpio_request(GPIO_PORT9, NULL);
1090 gpio_request(GPIO_PORT10, NULL); 1088 gpio_request(GPIO_PORT10, NULL);
1091 gpio_no_direction(GPIO_PORT9CR); /* FSIAOBT needs no direction */ 1089 gpio_no_direction(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1092 gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */ 1090 gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
1093 1091
1094 intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */ 1092 intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
1095 1093
1096 /* setup FSI2 port B (HDMI) */ 1094 /* setup FSI2 port B (HDMI) */
1097 gpio_request(GPIO_FN_FSIBCK, NULL); 1095 gpio_request(GPIO_FN_FSIBCK, NULL);
1098 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ 1096 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
1099 1097
1100 /* set SPU2 clock to 119.6 MHz */ 1098 /* set SPU2 clock to 119.6 MHz */
1101 clk = clk_get(NULL, "spu_clk"); 1099 clk = clk_get(NULL, "spu_clk");
1102 if (!IS_ERR(clk)) { 1100 if (!IS_ERR(clk)) {
1103 clk_set_rate(clk, clk_round_rate(clk, 119600000)); 1101 clk_set_rate(clk, clk_round_rate(clk, 119600000));
1104 clk_put(clk); 1102 clk_put(clk);
1105 } 1103 }
1106 1104
1107 /* enable Keypad */ 1105 /* enable Keypad */
1108 gpio_request(GPIO_FN_IRQ9_42, NULL); 1106 gpio_request(GPIO_FN_IRQ9_42, NULL);
1109 set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); 1107 set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
1110 1108
1111 /* enable Touchscreen */ 1109 /* enable Touchscreen */
1112 gpio_request(GPIO_FN_IRQ7_40, NULL); 1110 gpio_request(GPIO_FN_IRQ7_40, NULL);
1113 set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); 1111 set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
1114 1112
1115 /* enable Accelerometer */ 1113 /* enable Accelerometer */
1116 gpio_request(GPIO_FN_IRQ21, NULL); 1114 gpio_request(GPIO_FN_IRQ21, NULL);
1117 set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); 1115 set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
1118 1116
1119 /* enable SDHI0 */ 1117 /* enable SDHI0 */
1120 gpio_request(GPIO_FN_SDHICD0, NULL); 1118 gpio_request(GPIO_FN_SDHICD0, NULL);
1121 gpio_request(GPIO_FN_SDHIWP0, NULL); 1119 gpio_request(GPIO_FN_SDHIWP0, NULL);
1122 gpio_request(GPIO_FN_SDHICMD0, NULL); 1120 gpio_request(GPIO_FN_SDHICMD0, NULL);
1123 gpio_request(GPIO_FN_SDHICLK0, NULL); 1121 gpio_request(GPIO_FN_SDHICLK0, NULL);
1124 gpio_request(GPIO_FN_SDHID0_3, NULL); 1122 gpio_request(GPIO_FN_SDHID0_3, NULL);
1125 gpio_request(GPIO_FN_SDHID0_2, NULL); 1123 gpio_request(GPIO_FN_SDHID0_2, NULL);
1126 gpio_request(GPIO_FN_SDHID0_1, NULL); 1124 gpio_request(GPIO_FN_SDHID0_1, NULL);
1127 gpio_request(GPIO_FN_SDHID0_0, NULL); 1125 gpio_request(GPIO_FN_SDHID0_0, NULL);
1128 1126
1129 #if !defined(CONFIG_MMC_SH_MMCIF) 1127 #if !defined(CONFIG_MMC_SH_MMCIF)
1130 /* enable SDHI1 */ 1128 /* enable SDHI1 */
1131 gpio_request(GPIO_FN_SDHICMD1, NULL); 1129 gpio_request(GPIO_FN_SDHICMD1, NULL);
1132 gpio_request(GPIO_FN_SDHICLK1, NULL); 1130 gpio_request(GPIO_FN_SDHICLK1, NULL);
1133 gpio_request(GPIO_FN_SDHID1_3, NULL); 1131 gpio_request(GPIO_FN_SDHID1_3, NULL);
1134 gpio_request(GPIO_FN_SDHID1_2, NULL); 1132 gpio_request(GPIO_FN_SDHID1_2, NULL);
1135 gpio_request(GPIO_FN_SDHID1_1, NULL); 1133 gpio_request(GPIO_FN_SDHID1_1, NULL);
1136 gpio_request(GPIO_FN_SDHID1_0, NULL); 1134 gpio_request(GPIO_FN_SDHID1_0, NULL);
1137 #endif 1135 #endif
1138 /* card detect pin for MMC slot (CN7) */ 1136 /* card detect pin for MMC slot (CN7) */
1139 gpio_request(GPIO_PORT41, NULL); 1137 gpio_request(GPIO_PORT41, NULL);
1140 gpio_direction_input(GPIO_PORT41); 1138 gpio_direction_input(GPIO_PORT41);
1141 1139
1142 /* enable SDHI2 */ 1140 /* enable SDHI2 */
1143 gpio_request(GPIO_FN_SDHICMD2, NULL); 1141 gpio_request(GPIO_FN_SDHICMD2, NULL);
1144 gpio_request(GPIO_FN_SDHICLK2, NULL); 1142 gpio_request(GPIO_FN_SDHICLK2, NULL);
1145 gpio_request(GPIO_FN_SDHID2_3, NULL); 1143 gpio_request(GPIO_FN_SDHID2_3, NULL);
1146 gpio_request(GPIO_FN_SDHID2_2, NULL); 1144 gpio_request(GPIO_FN_SDHID2_2, NULL);
1147 gpio_request(GPIO_FN_SDHID2_1, NULL); 1145 gpio_request(GPIO_FN_SDHID2_1, NULL);
1148 gpio_request(GPIO_FN_SDHID2_0, NULL); 1146 gpio_request(GPIO_FN_SDHID2_0, NULL);
1149 1147
1150 /* card detect pin for microSD slot (CN23) */ 1148 /* card detect pin for microSD slot (CN23) */
1151 gpio_request(GPIO_PORT162, NULL); 1149 gpio_request(GPIO_PORT162, NULL);
1152 gpio_direction_input(GPIO_PORT162); 1150 gpio_direction_input(GPIO_PORT162);
1153 1151
1154 /* MMCIF */ 1152 /* MMCIF */
1155 gpio_request(GPIO_FN_MMCD0_0, NULL); 1153 gpio_request(GPIO_FN_MMCD0_0, NULL);
1156 gpio_request(GPIO_FN_MMCD0_1, NULL); 1154 gpio_request(GPIO_FN_MMCD0_1, NULL);
1157 gpio_request(GPIO_FN_MMCD0_2, NULL); 1155 gpio_request(GPIO_FN_MMCD0_2, NULL);
1158 gpio_request(GPIO_FN_MMCD0_3, NULL); 1156 gpio_request(GPIO_FN_MMCD0_3, NULL);
1159 gpio_request(GPIO_FN_MMCD0_4, NULL); 1157 gpio_request(GPIO_FN_MMCD0_4, NULL);
1160 gpio_request(GPIO_FN_MMCD0_5, NULL); 1158 gpio_request(GPIO_FN_MMCD0_5, NULL);
1161 gpio_request(GPIO_FN_MMCD0_6, NULL); 1159 gpio_request(GPIO_FN_MMCD0_6, NULL);
1162 gpio_request(GPIO_FN_MMCD0_7, NULL); 1160 gpio_request(GPIO_FN_MMCD0_7, NULL);
1163 gpio_request(GPIO_FN_MMCCMD0, NULL); 1161 gpio_request(GPIO_FN_MMCCMD0, NULL);
1164 gpio_request(GPIO_FN_MMCCLK0, NULL); 1162 gpio_request(GPIO_FN_MMCCLK0, NULL);
1165 1163
1166 /* enable GPS module (GT-720F) */ 1164 /* enable GPS module (GT-720F) */
1167 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); 1165 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
1168 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); 1166 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
1169 1167
1170 /* CEU */ 1168 /* CEU */
1171 gpio_request(GPIO_FN_VIO_CLK, NULL); 1169 gpio_request(GPIO_FN_VIO_CLK, NULL);
1172 gpio_request(GPIO_FN_VIO_VD, NULL); 1170 gpio_request(GPIO_FN_VIO_VD, NULL);
1173 gpio_request(GPIO_FN_VIO_HD, NULL); 1171 gpio_request(GPIO_FN_VIO_HD, NULL);
1174 gpio_request(GPIO_FN_VIO_FIELD, NULL); 1172 gpio_request(GPIO_FN_VIO_FIELD, NULL);
1175 gpio_request(GPIO_FN_VIO_CKO, NULL); 1173 gpio_request(GPIO_FN_VIO_CKO, NULL);
1176 gpio_request(GPIO_FN_VIO_D7, NULL); 1174 gpio_request(GPIO_FN_VIO_D7, NULL);
1177 gpio_request(GPIO_FN_VIO_D6, NULL); 1175 gpio_request(GPIO_FN_VIO_D6, NULL);
1178 gpio_request(GPIO_FN_VIO_D5, NULL); 1176 gpio_request(GPIO_FN_VIO_D5, NULL);
1179 gpio_request(GPIO_FN_VIO_D4, NULL); 1177 gpio_request(GPIO_FN_VIO_D4, NULL);
1180 gpio_request(GPIO_FN_VIO_D3, NULL); 1178 gpio_request(GPIO_FN_VIO_D3, NULL);
1181 gpio_request(GPIO_FN_VIO_D2, NULL); 1179 gpio_request(GPIO_FN_VIO_D2, NULL);
1182 gpio_request(GPIO_FN_VIO_D1, NULL); 1180 gpio_request(GPIO_FN_VIO_D1, NULL);
1183 gpio_request(GPIO_FN_VIO_D0, NULL); 1181 gpio_request(GPIO_FN_VIO_D0, NULL);
1184 1182
1185 /* HDMI */ 1183 /* HDMI */
1186 gpio_request(GPIO_FN_HDMI_HPD, NULL); 1184 gpio_request(GPIO_FN_HDMI_HPD, NULL);
1187 gpio_request(GPIO_FN_HDMI_CEC, NULL); 1185 gpio_request(GPIO_FN_HDMI_CEC, NULL);
1188 1186
1189 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ 1187 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
1190 srcr4 = __raw_readl(SRCR4); 1188 srcr4 = __raw_readl(SRCR4);
1191 __raw_writel(srcr4 | (1 << 13), SRCR4); 1189 __raw_writel(srcr4 | (1 << 13), SRCR4);
1192 udelay(50); 1190 udelay(50);
1193 __raw_writel(srcr4 & ~(1 << 13), SRCR4); 1191 __raw_writel(srcr4 & ~(1 << 13), SRCR4);
1194 1192
1195 i2c_register_board_info(0, i2c0_devices, 1193 i2c_register_board_info(0, i2c0_devices,
1196 ARRAY_SIZE(i2c0_devices)); 1194 ARRAY_SIZE(i2c0_devices));
1197 i2c_register_board_info(1, i2c1_devices, 1195 i2c_register_board_info(1, i2c1_devices,
1198 ARRAY_SIZE(i2c1_devices)); 1196 ARRAY_SIZE(i2c1_devices));
1199 1197
1200 sh7372_add_standard_devices(); 1198 sh7372_add_standard_devices();
1201 1199
1202 platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices)); 1200 platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
1203 } 1201 }
1204 1202
1205 static void __init mackerel_timer_init(void) 1203 static void __init mackerel_timer_init(void)
1206 { 1204 {
1207 sh7372_clock_init(); 1205 sh7372_clock_init();
1208 shmobile_timer.init(); 1206 shmobile_timer.init();
1209 1207
1210 /* External clock source */ 1208 /* External clock source */
1211 clk_set_rate(&sh7372_dv_clki_clk, 27000000); 1209 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1212 } 1210 }
1213 1211
1214 static struct sys_timer mackerel_timer = { 1212 static struct sys_timer mackerel_timer = {
1215 .init = mackerel_timer_init, 1213 .init = mackerel_timer_init,
1216 }; 1214 };
1217 1215
1218 MACHINE_START(MACKEREL, "mackerel") 1216 MACHINE_START(MACKEREL, "mackerel")
1219 .map_io = mackerel_map_io, 1217 .map_io = mackerel_map_io,
1220 .init_irq = sh7372_init_irq, 1218 .init_irq = sh7372_init_irq,
1221 .handle_irq = shmobile_handle_irq_intc, 1219 .handle_irq = shmobile_handle_irq_intc,
1222 .init_machine = mackerel_init, 1220 .init_machine = mackerel_init,
1223 .timer = &mackerel_timer, 1221 .timer = &mackerel_timer,
1224 MACHINE_END 1222 MACHINE_END
1225 1223
arch/sh/boards/mach-ecovec24/setup.c
Diff comments   View file @ f17c13c
1 /* 1 /*
2 * Copyright (C) 2009 Renesas Solutions Corp. 2 * Copyright (C) 2009 Renesas Solutions Corp.
3 * 3 *
4 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 4 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details. 8 * for more details.
9 */ 9 */
10 10
11 #include <linux/init.h> 11 #include <linux/init.h>
12 #include <linux/device.h> 12 #include <linux/device.h>
13 #include <linux/platform_device.h> 13 #include <linux/platform_device.h>
14 #include <linux/mfd/sh_mobile_sdhi.h> 14 #include <linux/mfd/sh_mobile_sdhi.h>
15 #include <linux/mmc/host.h> 15 #include <linux/mmc/host.h>
16 #include <linux/mmc/sh_mmcif.h> 16 #include <linux/mmc/sh_mmcif.h>
17 #include <linux/mtd/physmap.h> 17 #include <linux/mtd/physmap.h>
18 #include <linux/gpio.h> 18 #include <linux/gpio.h>
19 #include <linux/interrupt.h> 19 #include <linux/interrupt.h>
20 #include <linux/io.h> 20 #include <linux/io.h>
21 #include <linux/delay.h> 21 #include <linux/delay.h>
22 #include <linux/usb/r8a66597.h> 22 #include <linux/usb/r8a66597.h>
23 #include <linux/i2c.h> 23 #include <linux/i2c.h>
24 #include <linux/i2c/tsc2007.h> 24 #include <linux/i2c/tsc2007.h>
25 #include <linux/spi/spi.h> 25 #include <linux/spi/spi.h>
26 #include <linux/spi/sh_msiof.h> 26 #include <linux/spi/sh_msiof.h>
27 #include <linux/spi/mmc_spi.h> 27 #include <linux/spi/mmc_spi.h>
28 #include <linux/input.h> 28 #include <linux/input.h>
29 #include <linux/input/sh_keysc.h> 29 #include <linux/input/sh_keysc.h>
30 #include <video/sh_mobile_lcdc.h> 30 #include <video/sh_mobile_lcdc.h>
31 #include <sound/sh_fsi.h> 31 #include <sound/sh_fsi.h>
32 #include <media/sh_mobile_ceu.h> 32 #include <media/sh_mobile_ceu.h>
33 #include <media/tw9910.h> 33 #include <media/tw9910.h>
34 #include <media/mt9t112.h> 34 #include <media/mt9t112.h>
35 #include <asm/heartbeat.h> 35 #include <asm/heartbeat.h>
36 #include <asm/sh_eth.h> 36 #include <asm/sh_eth.h>
37 #include <asm/clock.h> 37 #include <asm/clock.h>
38 #include <asm/suspend.h> 38 #include <asm/suspend.h>
39 #include <cpu/sh7724.h> 39 #include <cpu/sh7724.h>
40 40
41 /* 41 /*
42 * Address Interface BusWidth 42 * Address Interface BusWidth
43 *----------------------------------------- 43 *-----------------------------------------
44 * 0x0000_0000 uboot 16bit 44 * 0x0000_0000 uboot 16bit
45 * 0x0004_0000 Linux romImage 16bit 45 * 0x0004_0000 Linux romImage 16bit
46 * 0x0014_0000 MTD for Linux 16bit 46 * 0x0014_0000 MTD for Linux 16bit
47 * 0x0400_0000 Internal I/O 16/32bit 47 * 0x0400_0000 Internal I/O 16/32bit
48 * 0x0800_0000 DRAM 32bit 48 * 0x0800_0000 DRAM 32bit
49 * 0x1800_0000 MFI 16bit 49 * 0x1800_0000 MFI 16bit
50 */ 50 */
51 51
52 /* SWITCH 52 /* SWITCH
53 *------------------------------ 53 *------------------------------
54 * DS2[1] = FlashROM write protect ON : write protect 54 * DS2[1] = FlashROM write protect ON : write protect
55 * OFF : No write protect 55 * OFF : No write protect
56 * DS2[2] = RMII / TS, SCIF ON : RMII 56 * DS2[2] = RMII / TS, SCIF ON : RMII
57 * OFF : TS, SCIF3 57 * OFF : TS, SCIF3
58 * DS2[3] = Camera / Video ON : Camera 58 * DS2[3] = Camera / Video ON : Camera
59 * OFF : NTSC/PAL (IN) 59 * OFF : NTSC/PAL (IN)
60 * DS2[5] = NTSC_OUT Clock ON : On board OSC 60 * DS2[5] = NTSC_OUT Clock ON : On board OSC
61 * OFF : SH7724 DV_CLK 61 * OFF : SH7724 DV_CLK
62 * DS2[6-7] = MMC / SD ON-OFF : SD 62 * DS2[6-7] = MMC / SD ON-OFF : SD
63 * OFF-ON : MMC 63 * OFF-ON : MMC
64 */ 64 */
65 65
66 /* Heartbeat */ 66 /* Heartbeat */
67 static unsigned char led_pos[] = { 0, 1, 2, 3 }; 67 static unsigned char led_pos[] = { 0, 1, 2, 3 };
68 68
69 static struct heartbeat_data heartbeat_data = { 69 static struct heartbeat_data heartbeat_data = {
70 .nr_bits = 4, 70 .nr_bits = 4,
71 .bit_pos = led_pos, 71 .bit_pos = led_pos,
72 }; 72 };
73 73
74 static struct resource heartbeat_resource = { 74 static struct resource heartbeat_resource = {
75 .start = 0xA405012C, /* PTG */ 75 .start = 0xA405012C, /* PTG */
76 .end = 0xA405012E - 1, 76 .end = 0xA405012E - 1,
77 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, 77 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
78 }; 78 };
79 79
80 static struct platform_device heartbeat_device = { 80 static struct platform_device heartbeat_device = {
81 .name = "heartbeat", 81 .name = "heartbeat",
82 .id = -1, 82 .id = -1,
83 .dev = { 83 .dev = {
84 .platform_data = &heartbeat_data, 84 .platform_data = &heartbeat_data,
85 }, 85 },
86 .num_resources = 1, 86 .num_resources = 1,
87 .resource = &heartbeat_resource, 87 .resource = &heartbeat_resource,
88 }; 88 };
89 89
90 /* MTD */ 90 /* MTD */
91 static struct mtd_partition nor_flash_partitions[] = { 91 static struct mtd_partition nor_flash_partitions[] = {
92 { 92 {
93 .name = "boot loader", 93 .name = "boot loader",
94 .offset = 0, 94 .offset = 0,
95 .size = (5 * 1024 * 1024), 95 .size = (5 * 1024 * 1024),
96 .mask_flags = MTD_WRITEABLE, /* force read-only */ 96 .mask_flags = MTD_WRITEABLE, /* force read-only */
97 }, { 97 }, {
98 .name = "free-area", 98 .name = "free-area",
99 .offset = MTDPART_OFS_APPEND, 99 .offset = MTDPART_OFS_APPEND,
100 .size = MTDPART_SIZ_FULL, 100 .size = MTDPART_SIZ_FULL,
101 }, 101 },
102 }; 102 };
103 103
104 static struct physmap_flash_data nor_flash_data = { 104 static struct physmap_flash_data nor_flash_data = {
105 .width = 2, 105 .width = 2,
106 .parts = nor_flash_partitions, 106 .parts = nor_flash_partitions,
107 .nr_parts = ARRAY_SIZE(nor_flash_partitions), 107 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
108 }; 108 };
109 109
110 static struct resource nor_flash_resources[] = { 110 static struct resource nor_flash_resources[] = {
111 [0] = { 111 [0] = {
112 .name = "NOR Flash", 112 .name = "NOR Flash",
113 .start = 0x00000000, 113 .start = 0x00000000,
114 .end = 0x03ffffff, 114 .end = 0x03ffffff,
115 .flags = IORESOURCE_MEM, 115 .flags = IORESOURCE_MEM,
116 } 116 }
117 }; 117 };
118 118
119 static struct platform_device nor_flash_device = { 119 static struct platform_device nor_flash_device = {
120 .name = "physmap-flash", 120 .name = "physmap-flash",
121 .resource = nor_flash_resources, 121 .resource = nor_flash_resources,
122 .num_resources = ARRAY_SIZE(nor_flash_resources), 122 .num_resources = ARRAY_SIZE(nor_flash_resources),
123 .dev = { 123 .dev = {
124 .platform_data = &nor_flash_data, 124 .platform_data = &nor_flash_data,
125 }, 125 },
126 }; 126 };
127 127
128 /* SH Eth */ 128 /* SH Eth */
129 #define SH_ETH_ADDR (0xA4600000) 129 #define SH_ETH_ADDR (0xA4600000)
130 static struct resource sh_eth_resources[] = { 130 static struct resource sh_eth_resources[] = {
131 [0] = { 131 [0] = {
132 .start = SH_ETH_ADDR, 132 .start = SH_ETH_ADDR,
133 .end = SH_ETH_ADDR + 0x1FC, 133 .end = SH_ETH_ADDR + 0x1FC,
134 .flags = IORESOURCE_MEM, 134 .flags = IORESOURCE_MEM,
135 }, 135 },
136 [1] = { 136 [1] = {
137 .start = 91, 137 .start = 91,
138 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 138 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
139 }, 139 },
140 }; 140 };
141 141
142 static struct sh_eth_plat_data sh_eth_plat = { 142 static struct sh_eth_plat_data sh_eth_plat = {
143 .phy = 0x1f, /* SMSC LAN8700 */ 143 .phy = 0x1f, /* SMSC LAN8700 */
144 .edmac_endian = EDMAC_LITTLE_ENDIAN, 144 .edmac_endian = EDMAC_LITTLE_ENDIAN,
145 .ether_link_active_low = 1 145 .ether_link_active_low = 1
146 }; 146 };
147 147
148 static struct platform_device sh_eth_device = { 148 static struct platform_device sh_eth_device = {
149 .name = "sh-eth", 149 .name = "sh-eth",
150 .id = 0, 150 .id = 0,
151 .dev = { 151 .dev = {
152 .platform_data = &sh_eth_plat, 152 .platform_data = &sh_eth_plat,
153 }, 153 },
154 .num_resources = ARRAY_SIZE(sh_eth_resources), 154 .num_resources = ARRAY_SIZE(sh_eth_resources),
155 .resource = sh_eth_resources, 155 .resource = sh_eth_resources,
156 .archdata = { 156 .archdata = {
157 .hwblk_id = HWBLK_ETHER, 157 .hwblk_id = HWBLK_ETHER,
158 }, 158 },
159 }; 159 };
160 160
161 /* USB0 host */ 161 /* USB0 host */
162 static void usb0_port_power(int port, int power) 162 static void usb0_port_power(int port, int power)
163 { 163 {
164 gpio_set_value(GPIO_PTB4, power); 164 gpio_set_value(GPIO_PTB4, power);
165 } 165 }
166 166
167 static struct r8a66597_platdata usb0_host_data = { 167 static struct r8a66597_platdata usb0_host_data = {
168 .on_chip = 1, 168 .on_chip = 1,
169 .port_power = usb0_port_power, 169 .port_power = usb0_port_power,
170 }; 170 };
171 171
172 static struct resource usb0_host_resources[] = { 172 static struct resource usb0_host_resources[] = {
173 [0] = { 173 [0] = {
174 .start = 0xa4d80000, 174 .start = 0xa4d80000,
175 .end = 0xa4d80124 - 1, 175 .end = 0xa4d80124 - 1,
176 .flags = IORESOURCE_MEM, 176 .flags = IORESOURCE_MEM,
177 }, 177 },
178 [1] = { 178 [1] = {
179 .start = 65, 179 .start = 65,
180 .end = 65, 180 .end = 65,
181 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 181 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
182 }, 182 },
183 }; 183 };
184 184
185 static struct platform_device usb0_host_device = { 185 static struct platform_device usb0_host_device = {
186 .name = "r8a66597_hcd", 186 .name = "r8a66597_hcd",
187 .id = 0, 187 .id = 0,
188 .dev = { 188 .dev = {
189 .dma_mask = NULL, /* not use dma */ 189 .dma_mask = NULL, /* not use dma */
190 .coherent_dma_mask = 0xffffffff, 190 .coherent_dma_mask = 0xffffffff,
191 .platform_data = &usb0_host_data, 191 .platform_data = &usb0_host_data,
192 }, 192 },
193 .num_resources = ARRAY_SIZE(usb0_host_resources), 193 .num_resources = ARRAY_SIZE(usb0_host_resources),
194 .resource = usb0_host_resources, 194 .resource = usb0_host_resources,
195 }; 195 };
196 196
197 /* USB1 host/function */ 197 /* USB1 host/function */
198 static void usb1_port_power(int port, int power) 198 static void usb1_port_power(int port, int power)
199 { 199 {
200 gpio_set_value(GPIO_PTB5, power); 200 gpio_set_value(GPIO_PTB5, power);
201 } 201 }
202 202
203 static struct r8a66597_platdata usb1_common_data = { 203 static struct r8a66597_platdata usb1_common_data = {
204 .on_chip = 1, 204 .on_chip = 1,
205 .port_power = usb1_port_power, 205 .port_power = usb1_port_power,
206 }; 206 };
207 207
208 static struct resource usb1_common_resources[] = { 208 static struct resource usb1_common_resources[] = {
209 [0] = { 209 [0] = {
210 .start = 0xa4d90000, 210 .start = 0xa4d90000,
211 .end = 0xa4d90124 - 1, 211 .end = 0xa4d90124 - 1,
212 .flags = IORESOURCE_MEM, 212 .flags = IORESOURCE_MEM,
213 }, 213 },
214 [1] = { 214 [1] = {
215 .start = 66, 215 .start = 66,
216 .end = 66, 216 .end = 66,
217 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 217 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
218 }, 218 },
219 }; 219 };
220 220
221 static struct platform_device usb1_common_device = { 221 static struct platform_device usb1_common_device = {
222 /* .name will be added in arch_setup */ 222 /* .name will be added in arch_setup */
223 .id = 1, 223 .id = 1,
224 .dev = { 224 .dev = {
225 .dma_mask = NULL, /* not use dma */ 225 .dma_mask = NULL, /* not use dma */
226 .coherent_dma_mask = 0xffffffff, 226 .coherent_dma_mask = 0xffffffff,
227 .platform_data = &usb1_common_data, 227 .platform_data = &usb1_common_data,
228 }, 228 },
229 .num_resources = ARRAY_SIZE(usb1_common_resources), 229 .num_resources = ARRAY_SIZE(usb1_common_resources),
230 .resource = usb1_common_resources, 230 .resource = usb1_common_resources,
231 }; 231 };
232 232
233 /* LCDC */ 233 /* LCDC */
234 const static struct fb_videomode ecovec_lcd_modes[] = { 234 const static struct fb_videomode ecovec_lcd_modes[] = {
235 { 235 {
236 .name = "Panel", 236 .name = "Panel",
237 .xres = 800, 237 .xres = 800,
238 .yres = 480, 238 .yres = 480,
239 .left_margin = 220, 239 .left_margin = 220,
240 .right_margin = 110, 240 .right_margin = 110,
241 .hsync_len = 70, 241 .hsync_len = 70,
242 .upper_margin = 20, 242 .upper_margin = 20,
243 .lower_margin = 5, 243 .lower_margin = 5,
244 .vsync_len = 5, 244 .vsync_len = 5,
245 .sync = 0, /* hsync and vsync are active low */ 245 .sync = 0, /* hsync and vsync are active low */
246 }, 246 },
247 }; 247 };
248 248
249 const static struct fb_videomode ecovec_dvi_modes[] = { 249 const static struct fb_videomode ecovec_dvi_modes[] = {
250 { 250 {
251 .name = "DVI", 251 .name = "DVI",
252 .xres = 1280, 252 .xres = 1280,
253 .yres = 720, 253 .yres = 720,
254 .left_margin = 220, 254 .left_margin = 220,
255 .right_margin = 110, 255 .right_margin = 110,
256 .hsync_len = 40, 256 .hsync_len = 40,
257 .upper_margin = 20, 257 .upper_margin = 20,
258 .lower_margin = 5, 258 .lower_margin = 5,
259 .vsync_len = 5, 259 .vsync_len = 5,
260 .sync = 0, /* hsync and vsync are active low */ 260 .sync = 0, /* hsync and vsync are active low */
261 }, 261 },
262 }; 262 };
263 263
264 static struct sh_mobile_lcdc_info lcdc_info = { 264 static struct sh_mobile_lcdc_info lcdc_info = {
265 .ch[0] = { 265 .ch[0] = {
266 .interface_type = RGB18, 266 .interface_type = RGB18,
267 .chan = LCDC_CHAN_MAINLCD, 267 .chan = LCDC_CHAN_MAINLCD,
268 .bpp = 16, 268 .bpp = 16,
269 .lcd_size_cfg = { /* 7.0 inch */ 269 .lcd_size_cfg = { /* 7.0 inch */
270 .width = 152, 270 .width = 152,
271 .height = 91, 271 .height = 91,
272 }, 272 },
273 .board_cfg = { 273 .board_cfg = {
274 }, 274 },
275 } 275 }
276 }; 276 };
277 277
278 static struct resource lcdc_resources[] = { 278 static struct resource lcdc_resources[] = {
279 [0] = { 279 [0] = {
280 .name = "LCDC", 280 .name = "LCDC",
281 .start = 0xfe940000, 281 .start = 0xfe940000,
282 .end = 0xfe942fff, 282 .end = 0xfe942fff,
283 .flags = IORESOURCE_MEM, 283 .flags = IORESOURCE_MEM,
284 }, 284 },
285 [1] = { 285 [1] = {
286 .start = 106, 286 .start = 106,
287 .flags = IORESOURCE_IRQ, 287 .flags = IORESOURCE_IRQ,
288 }, 288 },
289 }; 289 };
290 290
291 static struct platform_device lcdc_device = { 291 static struct platform_device lcdc_device = {
292 .name = "sh_mobile_lcdc_fb", 292 .name = "sh_mobile_lcdc_fb",
293 .num_resources = ARRAY_SIZE(lcdc_resources), 293 .num_resources = ARRAY_SIZE(lcdc_resources),
294 .resource = lcdc_resources, 294 .resource = lcdc_resources,
295 .dev = { 295 .dev = {
296 .platform_data = &lcdc_info, 296 .platform_data = &lcdc_info,
297 }, 297 },
298 .archdata = { 298 .archdata = {
299 .hwblk_id = HWBLK_LCDC, 299 .hwblk_id = HWBLK_LCDC,
300 }, 300 },
301 }; 301 };
302 302
303 /* CEU0 */ 303 /* CEU0 */
304 static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { 304 static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
305 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 305 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
306 }; 306 };
307 307
308 static struct resource ceu0_resources[] = { 308 static struct resource ceu0_resources[] = {
309 [0] = { 309 [0] = {
310 .name = "CEU0", 310 .name = "CEU0",
311 .start = 0xfe910000, 311 .start = 0xfe910000,
312 .end = 0xfe91009f, 312 .end = 0xfe91009f,
313 .flags = IORESOURCE_MEM, 313 .flags = IORESOURCE_MEM,
314 }, 314 },
315 [1] = { 315 [1] = {
316 .start = 52, 316 .start = 52,
317 .flags = IORESOURCE_IRQ, 317 .flags = IORESOURCE_IRQ,
318 }, 318 },
319 [2] = { 319 [2] = {
320 /* place holder for contiguous memory */ 320 /* place holder for contiguous memory */
321 }, 321 },
322 }; 322 };
323 323
324 static struct platform_device ceu0_device = { 324 static struct platform_device ceu0_device = {
325 .name = "sh_mobile_ceu", 325 .name = "sh_mobile_ceu",
326 .id = 0, /* "ceu0" clock */ 326 .id = 0, /* "ceu0" clock */
327 .num_resources = ARRAY_SIZE(ceu0_resources), 327 .num_resources = ARRAY_SIZE(ceu0_resources),
328 .resource = ceu0_resources, 328 .resource = ceu0_resources,
329 .dev = { 329 .dev = {
330 .platform_data = &sh_mobile_ceu0_info, 330 .platform_data = &sh_mobile_ceu0_info,
331 }, 331 },
332 .archdata = { 332 .archdata = {
333 .hwblk_id = HWBLK_CEU0, 333 .hwblk_id = HWBLK_CEU0,
334 }, 334 },
335 }; 335 };
336 336
337 /* CEU1 */ 337 /* CEU1 */
338 static struct sh_mobile_ceu_info sh_mobile_ceu1_info = { 338 static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
339 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 339 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
340 }; 340 };
341 341
342 static struct resource ceu1_resources[] = { 342 static struct resource ceu1_resources[] = {
343 [0] = { 343 [0] = {
344 .name = "CEU1", 344 .name = "CEU1",
345 .start = 0xfe914000, 345 .start = 0xfe914000,
346 .end = 0xfe91409f, 346 .end = 0xfe91409f,
347 .flags = IORESOURCE_MEM, 347 .flags = IORESOURCE_MEM,
348 }, 348 },
349 [1] = { 349 [1] = {
350 .start = 63, 350 .start = 63,
351 .flags = IORESOURCE_IRQ, 351 .flags = IORESOURCE_IRQ,
352 }, 352 },
353 [2] = { 353 [2] = {
354 /* place holder for contiguous memory */ 354 /* place holder for contiguous memory */
355 }, 355 },
356 }; 356 };
357 357
358 static struct platform_device ceu1_device = { 358 static struct platform_device ceu1_device = {
359 .name = "sh_mobile_ceu", 359 .name = "sh_mobile_ceu",
360 .id = 1, /* "ceu1" clock */ 360 .id = 1, /* "ceu1" clock */
361 .num_resources = ARRAY_SIZE(ceu1_resources), 361 .num_resources = ARRAY_SIZE(ceu1_resources),
362 .resource = ceu1_resources, 362 .resource = ceu1_resources,
363 .dev = { 363 .dev = {
364 .platform_data = &sh_mobile_ceu1_info, 364 .platform_data = &sh_mobile_ceu1_info,
365 }, 365 },
366 .archdata = { 366 .archdata = {
367 .hwblk_id = HWBLK_CEU1, 367 .hwblk_id = HWBLK_CEU1,
368 }, 368 },
369 }; 369 };
370 370
371 /* I2C device */ 371 /* I2C device */
372 static struct i2c_board_info i2c0_devices[] = { 372 static struct i2c_board_info i2c0_devices[] = {
373 { 373 {
374 I2C_BOARD_INFO("da7210", 0x1a), 374 I2C_BOARD_INFO("da7210", 0x1a),
375 }, 375 },
376 }; 376 };
377 377
378 static struct i2c_board_info i2c1_devices[] = { 378 static struct i2c_board_info i2c1_devices[] = {
379 { 379 {
380 I2C_BOARD_INFO("r2025sd", 0x32), 380 I2C_BOARD_INFO("r2025sd", 0x32),
381 }, 381 },
382 { 382 {
383 I2C_BOARD_INFO("lis3lv02d", 0x1c), 383 I2C_BOARD_INFO("lis3lv02d", 0x1c),
384 .irq = 33, 384 .irq = 33,
385 } 385 }
386 }; 386 };
387 387
388 /* KEYSC */ 388 /* KEYSC */
389 static struct sh_keysc_info keysc_info = { 389 static struct sh_keysc_info keysc_info = {
390 .mode = SH_KEYSC_MODE_1, 390 .mode = SH_KEYSC_MODE_1,
391 .scan_timing = 3, 391 .scan_timing = 3,
392 .delay = 50, 392 .delay = 50,
393 .kycr2_delay = 100, 393 .kycr2_delay = 100,
394 .keycodes = { KEY_1, 0, 0, 0, 0, 394 .keycodes = { KEY_1, 0, 0, 0, 0,
395 KEY_2, 0, 0, 0, 0, 395 KEY_2, 0, 0, 0, 0,
396 KEY_3, 0, 0, 0, 0, 396 KEY_3, 0, 0, 0, 0,
397 KEY_4, 0, 0, 0, 0, 397 KEY_4, 0, 0, 0, 0,
398 KEY_5, 0, 0, 0, 0, 398 KEY_5, 0, 0, 0, 0,
399 KEY_6, 0, 0, 0, 0, }, 399 KEY_6, 0, 0, 0, 0, },
400 }; 400 };
401 401
402 static struct resource keysc_resources[] = { 402 static struct resource keysc_resources[] = {
403 [0] = { 403 [0] = {
404 .name = "KEYSC", 404 .name = "KEYSC",
405 .start = 0x044b0000, 405 .start = 0x044b0000,
406 .end = 0x044b000f, 406 .end = 0x044b000f,
407 .flags = IORESOURCE_MEM, 407 .flags = IORESOURCE_MEM,
408 }, 408 },
409 [1] = { 409 [1] = {
410 .start = 79, 410 .start = 79,
411 .flags = IORESOURCE_IRQ, 411 .flags = IORESOURCE_IRQ,
412 }, 412 },
413 }; 413 };
414 414
415 static struct platform_device keysc_device = { 415 static struct platform_device keysc_device = {
416 .name = "sh_keysc", 416 .name = "sh_keysc",
417 .id = 0, /* keysc0 clock */ 417 .id = 0, /* keysc0 clock */
418 .num_resources = ARRAY_SIZE(keysc_resources), 418 .num_resources = ARRAY_SIZE(keysc_resources),
419 .resource = keysc_resources, 419 .resource = keysc_resources,
420 .dev = { 420 .dev = {
421 .platform_data = &keysc_info, 421 .platform_data = &keysc_info,
422 }, 422 },
423 .archdata = { 423 .archdata = {
424 .hwblk_id = HWBLK_KEYSC, 424 .hwblk_id = HWBLK_KEYSC,
425 }, 425 },
426 }; 426 };
427 427
428 /* TouchScreen */ 428 /* TouchScreen */
429 #define IRQ0 32 429 #define IRQ0 32
430 static int ts_get_pendown_state(void) 430 static int ts_get_pendown_state(void)
431 { 431 {
432 int val = 0; 432 int val = 0;
433 gpio_free(GPIO_FN_INTC_IRQ0); 433 gpio_free(GPIO_FN_INTC_IRQ0);
434 gpio_request(GPIO_PTZ0, NULL); 434 gpio_request(GPIO_PTZ0, NULL);
435 gpio_direction_input(GPIO_PTZ0); 435 gpio_direction_input(GPIO_PTZ0);
436 436
437 val = gpio_get_value(GPIO_PTZ0); 437 val = gpio_get_value(GPIO_PTZ0);
438 438
439 gpio_free(GPIO_PTZ0); 439 gpio_free(GPIO_PTZ0);
440 gpio_request(GPIO_FN_INTC_IRQ0, NULL); 440 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
441 441
442 return val ? 0 : 1; 442 return val ? 0 : 1;
443 } 443 }
444 444
445 static int ts_init(void) 445 static int ts_init(void)
446 { 446 {
447 gpio_request(GPIO_FN_INTC_IRQ0, NULL); 447 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
448 return 0; 448 return 0;
449 } 449 }
450 450
451 static struct tsc2007_platform_data tsc2007_info = { 451 static struct tsc2007_platform_data tsc2007_info = {
452 .model = 2007, 452 .model = 2007,
453 .x_plate_ohms = 180, 453 .x_plate_ohms = 180,
454 .get_pendown_state = ts_get_pendown_state, 454 .get_pendown_state = ts_get_pendown_state,
455 .init_platform_hw = ts_init, 455 .init_platform_hw = ts_init,
456 }; 456 };
457 457
458 static struct i2c_board_info ts_i2c_clients = { 458 static struct i2c_board_info ts_i2c_clients = {
459 I2C_BOARD_INFO("tsc2007", 0x48), 459 I2C_BOARD_INFO("tsc2007", 0x48),
460 .type = "tsc2007", 460 .type = "tsc2007",
461 .platform_data = &tsc2007_info, 461 .platform_data = &tsc2007_info,
462 .irq = IRQ0, 462 .irq = IRQ0,
463 }; 463 };
464 464
465 #ifdef CONFIG_MFD_SH_MOBILE_SDHI 465 #ifdef CONFIG_MFD_SH_MOBILE_SDHI
466 /* SDHI0 */ 466 /* SDHI0 */
467 static void sdhi0_set_pwr(struct platform_device *pdev, int state) 467 static void sdhi0_set_pwr(struct platform_device *pdev, int state)
468 { 468 {
469 gpio_set_value(GPIO_PTB6, state); 469 gpio_set_value(GPIO_PTB6, state);
470 } 470 }
471 471
472 static struct sh_mobile_sdhi_info sdhi0_info = { 472 static struct sh_mobile_sdhi_info sdhi0_info = {
473 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 473 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
474 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 474 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
475 .set_pwr = sdhi0_set_pwr, 475 .set_pwr = sdhi0_set_pwr,
476 .tmio_caps = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD, 476 .tmio_caps = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD,
477 }; 477 };
478 478
479 static struct resource sdhi0_resources[] = { 479 static struct resource sdhi0_resources[] = {
480 [0] = { 480 [0] = {
481 .name = "SDHI0", 481 .name = "SDHI0",
482 .start = 0x04ce0000, 482 .start = 0x04ce0000,
483 .end = 0x04ce01ff, 483 .end = 0x04ce01ff,
484 .flags = IORESOURCE_MEM, 484 .flags = IORESOURCE_MEM,
485 }, 485 },
486 [1] = { 486 [1] = {
487 .start = 100, 487 .start = 100,
488 .flags = IORESOURCE_IRQ, 488 .flags = IORESOURCE_IRQ,
489 }, 489 },
490 }; 490 };
491 491
492 static struct platform_device sdhi0_device = { 492 static struct platform_device sdhi0_device = {
493 .name = "sh_mobile_sdhi", 493 .name = "sh_mobile_sdhi",
494 .num_resources = ARRAY_SIZE(sdhi0_resources), 494 .num_resources = ARRAY_SIZE(sdhi0_resources),
495 .resource = sdhi0_resources, 495 .resource = sdhi0_resources,
496 .id = 0, 496 .id = 0,
497 .dev = { 497 .dev = {
498 .platform_data = &sdhi0_info, 498 .platform_data = &sdhi0_info,
499 }, 499 },
500 .archdata = { 500 .archdata = {
501 .hwblk_id = HWBLK_SDHI0, 501 .hwblk_id = HWBLK_SDHI0,
502 }, 502 },
503 }; 503 };
504 504
505 #if !defined(CONFIG_MMC_SH_MMCIF) 505 #if !defined(CONFIG_MMC_SH_MMCIF)
506 /* SDHI1 */ 506 /* SDHI1 */
507 static void sdhi1_set_pwr(struct platform_device *pdev, int state) 507 static void sdhi1_set_pwr(struct platform_device *pdev, int state)
508 { 508 {
509 gpio_set_value(GPIO_PTB7, state); 509 gpio_set_value(GPIO_PTB7, state);
510 } 510 }
511 511
512 static struct sh_mobile_sdhi_info sdhi1_info = { 512 static struct sh_mobile_sdhi_info sdhi1_info = {
513 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, 513 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
514 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, 514 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
515 .tmio_caps = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD, 515 .tmio_caps = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD,
516 .set_pwr = sdhi1_set_pwr, 516 .set_pwr = sdhi1_set_pwr,
517 }; 517 };
518 518
519 static struct resource sdhi1_resources[] = { 519 static struct resource sdhi1_resources[] = {
520 [0] = { 520 [0] = {
521 .name = "SDHI1", 521 .name = "SDHI1",
522 .start = 0x04cf0000, 522 .start = 0x04cf0000,
523 .end = 0x04cf01ff, 523 .end = 0x04cf01ff,
524 .flags = IORESOURCE_MEM, 524 .flags = IORESOURCE_MEM,
525 }, 525 },
526 [1] = { 526 [1] = {
527 .start = 23, 527 .start = 23,
528 .flags = IORESOURCE_IRQ, 528 .flags = IORESOURCE_IRQ,
529 }, 529 },
530 }; 530 };
531 531
532 static struct platform_device sdhi1_device = { 532 static struct platform_device sdhi1_device = {
533 .name = "sh_mobile_sdhi", 533 .name = "sh_mobile_sdhi",
534 .num_resources = ARRAY_SIZE(sdhi1_resources), 534 .num_resources = ARRAY_SIZE(sdhi1_resources),
535 .resource = sdhi1_resources, 535 .resource = sdhi1_resources,
536 .id = 1, 536 .id = 1,
537 .dev = { 537 .dev = {
538 .platform_data = &sdhi1_info, 538 .platform_data = &sdhi1_info,
539 }, 539 },
540 .archdata = { 540 .archdata = {
541 .hwblk_id = HWBLK_SDHI1, 541 .hwblk_id = HWBLK_SDHI1,
542 }, 542 },
543 }; 543 };
544 #endif /* CONFIG_MMC_SH_MMCIF */ 544 #endif /* CONFIG_MMC_SH_MMCIF */
545 545
546 #else 546 #else
547 547
548 /* MMC SPI */ 548 /* MMC SPI */
549 static int mmc_spi_get_ro(struct device *dev) 549 static int mmc_spi_get_ro(struct device *dev)
550 { 550 {
551 return gpio_get_value(GPIO_PTY6); 551 return gpio_get_value(GPIO_PTY6);
552 } 552 }
553 553
554 static int mmc_spi_get_cd(struct device *dev) 554 static int mmc_spi_get_cd(struct device *dev)
555 { 555 {
556 return !gpio_get_value(GPIO_PTY7); 556 return !gpio_get_value(GPIO_PTY7);
557 } 557 }
558 558
559 static void mmc_spi_setpower(struct device *dev, unsigned int maskval) 559 static void mmc_spi_setpower(struct device *dev, unsigned int maskval)
560 { 560 {
561 gpio_set_value(GPIO_PTB6, maskval ? 1 : 0); 561 gpio_set_value(GPIO_PTB6, maskval ? 1 : 0);
562 } 562 }
563 563
564 static struct mmc_spi_platform_data mmc_spi_info = { 564 static struct mmc_spi_platform_data mmc_spi_info = {
565 .get_ro = mmc_spi_get_ro, 565 .get_ro = mmc_spi_get_ro,
566 .get_cd = mmc_spi_get_cd, 566 .get_cd = mmc_spi_get_cd,
567 .caps = MMC_CAP_NEEDS_POLL, 567 .caps = MMC_CAP_NEEDS_POLL,
568 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3.3V only */ 568 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3.3V only */
569 .setpower = mmc_spi_setpower, 569 .setpower = mmc_spi_setpower,
570 }; 570 };
571 571
572 static struct spi_board_info spi_bus[] = { 572 static struct spi_board_info spi_bus[] = {
573 { 573 {
574 .modalias = "mmc_spi", 574 .modalias = "mmc_spi",
575 .platform_data = &mmc_spi_info, 575 .platform_data = &mmc_spi_info,
576 .max_speed_hz = 5000000, 576 .max_speed_hz = 5000000,
577 .mode = SPI_MODE_0, 577 .mode = SPI_MODE_0,
578 .controller_data = (void *) GPIO_PTM4, 578 .controller_data = (void *) GPIO_PTM4,
579 }, 579 },
580 }; 580 };
581 581
582 /* MSIOF0 */ 582 /* MSIOF0 */
583 static struct sh_msiof_spi_info msiof0_data = { 583 static struct sh_msiof_spi_info msiof0_data = {
584 .num_chipselect = 1, 584 .num_chipselect = 1,
585 }; 585 };
586 586
587 static struct resource msiof0_resources[] = { 587 static struct resource msiof0_resources[] = {
588 [0] = { 588 [0] = {
589 .name = "MSIOF0", 589 .name = "MSIOF0",
590 .start = 0xa4c40000, 590 .start = 0xa4c40000,
591 .end = 0xa4c40063, 591 .end = 0xa4c40063,
592 .flags = IORESOURCE_MEM, 592 .flags = IORESOURCE_MEM,
593 }, 593 },
594 [1] = { 594 [1] = {
595 .start = 84, 595 .start = 84,
596 .flags = IORESOURCE_IRQ, 596 .flags = IORESOURCE_IRQ,
597 }, 597 },
598 }; 598 };
599 599
600 static struct platform_device msiof0_device = { 600 static struct platform_device msiof0_device = {
601 .name = "spi_sh_msiof", 601 .name = "spi_sh_msiof",
602 .id = 0, /* MSIOF0 */ 602 .id = 0, /* MSIOF0 */
603 .dev = { 603 .dev = {
604 .platform_data = &msiof0_data, 604 .platform_data = &msiof0_data,
605 }, 605 },
606 .num_resources = ARRAY_SIZE(msiof0_resources), 606 .num_resources = ARRAY_SIZE(msiof0_resources),
607 .resource = msiof0_resources, 607 .resource = msiof0_resources,
608 .archdata = { 608 .archdata = {
609 .hwblk_id = HWBLK_MSIOF0, 609 .hwblk_id = HWBLK_MSIOF0,
610 }, 610 },
611 }; 611 };
612 612
613 #endif 613 #endif
614 614
615 /* I2C Video/Camera */ 615 /* I2C Video/Camera */
616 static struct i2c_board_info i2c_camera[] = { 616 static struct i2c_board_info i2c_camera[] = {
617 { 617 {
618 I2C_BOARD_INFO("tw9910", 0x45), 618 I2C_BOARD_INFO("tw9910", 0x45),
619 }, 619 },
620 { 620 {
621 /* 1st camera */ 621 /* 1st camera */
622 I2C_BOARD_INFO("mt9t112", 0x3c), 622 I2C_BOARD_INFO("mt9t112", 0x3c),
623 }, 623 },
624 { 624 {
625 /* 2nd camera */ 625 /* 2nd camera */
626 I2C_BOARD_INFO("mt9t112", 0x3c), 626 I2C_BOARD_INFO("mt9t112", 0x3c),
627 }, 627 },
628 }; 628 };
629 629
630 /* tw9910 */ 630 /* tw9910 */
631 static int tw9910_power(struct device *dev, int mode) 631 static int tw9910_power(struct device *dev, int mode)
632 { 632 {
633 int val = mode ? 0 : 1; 633 int val = mode ? 0 : 1;
634 634
635 gpio_set_value(GPIO_PTU2, val); 635 gpio_set_value(GPIO_PTU2, val);
636 if (mode) 636 if (mode)
637 mdelay(100); 637 mdelay(100);
638 638
639 return 0; 639 return 0;
640 } 640 }
641 641
642 static struct tw9910_video_info tw9910_info = { 642 static struct tw9910_video_info tw9910_info = {
643 .buswidth = SOCAM_DATAWIDTH_8, 643 .buswidth = SOCAM_DATAWIDTH_8,
644 .mpout = TW9910_MPO_FIELD, 644 .mpout = TW9910_MPO_FIELD,
645 }; 645 };
646 646
647 static struct soc_camera_link tw9910_link = { 647 static struct soc_camera_link tw9910_link = {
648 .i2c_adapter_id = 0, 648 .i2c_adapter_id = 0,
649 .bus_id = 1, 649 .bus_id = 1,
650 .power = tw9910_power, 650 .power = tw9910_power,
651 .board_info = &i2c_camera[0], 651 .board_info = &i2c_camera[0],
652 .priv = &tw9910_info, 652 .priv = &tw9910_info,
653 }; 653 };
654 654
655 /* mt9t112 */ 655 /* mt9t112 */
656 static int mt9t112_power1(struct device *dev, int mode) 656 static int mt9t112_power1(struct device *dev, int mode)
657 { 657 {
658 gpio_set_value(GPIO_PTA3, mode); 658 gpio_set_value(GPIO_PTA3, mode);
659 if (mode) 659 if (mode)
660 mdelay(100); 660 mdelay(100);
661 661
662 return 0; 662 return 0;
663 } 663 }
664 664
665 static struct mt9t112_camera_info mt9t112_info1 = { 665 static struct mt9t112_camera_info mt9t112_info1 = {
666 .flags = MT9T112_FLAG_PCLK_RISING_EDGE | MT9T112_FLAG_DATAWIDTH_8, 666 .flags = MT9T112_FLAG_PCLK_RISING_EDGE | MT9T112_FLAG_DATAWIDTH_8,
667 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */ 667 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
668 }; 668 };
669 669
670 static struct soc_camera_link mt9t112_link1 = { 670 static struct soc_camera_link mt9t112_link1 = {
671 .i2c_adapter_id = 0, 671 .i2c_adapter_id = 0,
672 .power = mt9t112_power1, 672 .power = mt9t112_power1,
673 .bus_id = 0, 673 .bus_id = 0,
674 .board_info = &i2c_camera[1], 674 .board_info = &i2c_camera[1],
675 .priv = &mt9t112_info1, 675 .priv = &mt9t112_info1,
676 }; 676 };
677 677
678 static int mt9t112_power2(struct device *dev, int mode) 678 static int mt9t112_power2(struct device *dev, int mode)
679 { 679 {
680 gpio_set_value(GPIO_PTA4, mode); 680 gpio_set_value(GPIO_PTA4, mode);
681 if (mode) 681 if (mode)
682 mdelay(100); 682 mdelay(100);
683 683
684 return 0; 684 return 0;
685 } 685 }
686 686
687 static struct mt9t112_camera_info mt9t112_info2 = { 687 static struct mt9t112_camera_info mt9t112_info2 = {
688 .flags = MT9T112_FLAG_PCLK_RISING_EDGE | MT9T112_FLAG_DATAWIDTH_8, 688 .flags = MT9T112_FLAG_PCLK_RISING_EDGE | MT9T112_FLAG_DATAWIDTH_8,
689 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */ 689 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
690 }; 690 };
691 691
692 static struct soc_camera_link mt9t112_link2 = { 692 static struct soc_camera_link mt9t112_link2 = {
693 .i2c_adapter_id = 1, 693 .i2c_adapter_id = 1,
694 .power = mt9t112_power2, 694 .power = mt9t112_power2,
695 .bus_id = 1, 695 .bus_id = 1,
696 .board_info = &i2c_camera[2], 696 .board_info = &i2c_camera[2],
697 .priv = &mt9t112_info2, 697 .priv = &mt9t112_info2,
698 }; 698 };
699 699
700 static struct platform_device camera_devices[] = { 700 static struct platform_device camera_devices[] = {
701 { 701 {
702 .name = "soc-camera-pdrv", 702 .name = "soc-camera-pdrv",
703 .id = 0, 703 .id = 0,
704 .dev = { 704 .dev = {
705 .platform_data = &tw9910_link, 705 .platform_data = &tw9910_link,
706 }, 706 },
707 }, 707 },
708 { 708 {
709 .name = "soc-camera-pdrv", 709 .name = "soc-camera-pdrv",
710 .id = 1, 710 .id = 1,
711 .dev = { 711 .dev = {
712 .platform_data = &mt9t112_link1, 712 .platform_data = &mt9t112_link1,
713 }, 713 },
714 }, 714 },
715 { 715 {
716 .name = "soc-camera-pdrv", 716 .name = "soc-camera-pdrv",
717 .id = 2, 717 .id = 2,
718 .dev = { 718 .dev = {
719 .platform_data = &mt9t112_link2, 719 .platform_data = &mt9t112_link2,
720 }, 720 },
721 }, 721 },
722 }; 722 };
723 723
724 /* FSI */ 724 /* FSI */
725 static struct sh_fsi_platform_info fsi_info = { 725 static struct sh_fsi_platform_info fsi_info = {
726 .portb_flags = SH_FSI_BRS_INV | 726 .portb_flags = SH_FSI_BRS_INV,
727 SH_FSI_OFMT(I2S) |
728 SH_FSI_IFMT(I2S),
729 }; 727 };
730 728
731 static struct resource fsi_resources[] = { 729 static struct resource fsi_resources[] = {
732 [0] = { 730 [0] = {
733 .name = "FSI", 731 .name = "FSI",
734 .start = 0xFE3C0000, 732 .start = 0xFE3C0000,
735 .end = 0xFE3C021d, 733 .end = 0xFE3C021d,
736 .flags = IORESOURCE_MEM, 734 .flags = IORESOURCE_MEM,
737 }, 735 },
738 [1] = { 736 [1] = {
739 .start = 108, 737 .start = 108,
740 .flags = IORESOURCE_IRQ, 738 .flags = IORESOURCE_IRQ,
741 }, 739 },
742 }; 740 };
743 741
744 static struct platform_device fsi_device = { 742 static struct platform_device fsi_device = {
745 .name = "sh_fsi", 743 .name = "sh_fsi",
746 .id = 0, 744 .id = 0,
747 .num_resources = ARRAY_SIZE(fsi_resources), 745 .num_resources = ARRAY_SIZE(fsi_resources),
748 .resource = fsi_resources, 746 .resource = fsi_resources,
749 .dev = { 747 .dev = {
750 .platform_data = &fsi_info, 748 .platform_data = &fsi_info,
751 }, 749 },
752 .archdata = { 750 .archdata = {
753 .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */ 751 .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */
754 }, 752 },
755 }; 753 };
756 754
757 /* IrDA */ 755 /* IrDA */
758 static struct resource irda_resources[] = { 756 static struct resource irda_resources[] = {
759 [0] = { 757 [0] = {
760 .name = "IrDA", 758 .name = "IrDA",
761 .start = 0xA45D0000, 759 .start = 0xA45D0000,
762 .end = 0xA45D0049, 760 .end = 0xA45D0049,
763 .flags = IORESOURCE_MEM, 761 .flags = IORESOURCE_MEM,
764 }, 762 },
765 [1] = { 763 [1] = {
766 .start = 20, 764 .start = 20,
767 .flags = IORESOURCE_IRQ, 765 .flags = IORESOURCE_IRQ,
768 }, 766 },
769 }; 767 };
770 768
771 static struct platform_device irda_device = { 769 static struct platform_device irda_device = {
772 .name = "sh_sir", 770 .name = "sh_sir",
773 .num_resources = ARRAY_SIZE(irda_resources), 771 .num_resources = ARRAY_SIZE(irda_resources),
774 .resource = irda_resources, 772 .resource = irda_resources,
775 }; 773 };
776 774
777 #include <media/ak881x.h> 775 #include <media/ak881x.h>
778 #include <media/sh_vou.h> 776 #include <media/sh_vou.h>
779 777
780 static struct ak881x_pdata ak881x_pdata = { 778 static struct ak881x_pdata ak881x_pdata = {
781 .flags = AK881X_IF_MODE_SLAVE, 779 .flags = AK881X_IF_MODE_SLAVE,
782 }; 780 };
783 781
784 static struct i2c_board_info ak8813 = { 782 static struct i2c_board_info ak8813 = {
785 I2C_BOARD_INFO("ak8813", 0x20), 783 I2C_BOARD_INFO("ak8813", 0x20),
786 .platform_data = &ak881x_pdata, 784 .platform_data = &ak881x_pdata,
787 }; 785 };
788 786
789 static struct sh_vou_pdata sh_vou_pdata = { 787 static struct sh_vou_pdata sh_vou_pdata = {
790 .bus_fmt = SH_VOU_BUS_8BIT, 788 .bus_fmt = SH_VOU_BUS_8BIT,
791 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW, 789 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
792 .board_info = &ak8813, 790 .board_info = &ak8813,
793 .i2c_adap = 0, 791 .i2c_adap = 0,
794 }; 792 };
795 793
796 static struct resource sh_vou_resources[] = { 794 static struct resource sh_vou_resources[] = {
797 [0] = { 795 [0] = {
798 .start = 0xfe960000, 796 .start = 0xfe960000,
799 .end = 0xfe962043, 797 .end = 0xfe962043,
800 .flags = IORESOURCE_MEM, 798 .flags = IORESOURCE_MEM,
801 }, 799 },
802 [1] = { 800 [1] = {
803 .start = 55, 801 .start = 55,
804 .flags = IORESOURCE_IRQ, 802 .flags = IORESOURCE_IRQ,
805 }, 803 },
806 }; 804 };
807 805
808 static struct platform_device vou_device = { 806 static struct platform_device vou_device = {
809 .name = "sh-vou", 807 .name = "sh-vou",
810 .id = -1, 808 .id = -1,
811 .num_resources = ARRAY_SIZE(sh_vou_resources), 809 .num_resources = ARRAY_SIZE(sh_vou_resources),
812 .resource = sh_vou_resources, 810 .resource = sh_vou_resources,
813 .dev = { 811 .dev = {
814 .platform_data = &sh_vou_pdata, 812 .platform_data = &sh_vou_pdata,
815 }, 813 },
816 .archdata = { 814 .archdata = {
817 .hwblk_id = HWBLK_VOU, 815 .hwblk_id = HWBLK_VOU,
818 }, 816 },
819 }; 817 };
820 818
821 #if defined(CONFIG_MMC_SH_MMCIF) 819 #if defined(CONFIG_MMC_SH_MMCIF)
822 /* SH_MMCIF */ 820 /* SH_MMCIF */
823 static void mmcif_set_pwr(struct platform_device *pdev, int state) 821 static void mmcif_set_pwr(struct platform_device *pdev, int state)
824 { 822 {
825 gpio_set_value(GPIO_PTB7, state); 823 gpio_set_value(GPIO_PTB7, state);
826 } 824 }
827 825
828 static void mmcif_down_pwr(struct platform_device *pdev) 826 static void mmcif_down_pwr(struct platform_device *pdev)
829 { 827 {
830 gpio_set_value(GPIO_PTB7, 0); 828 gpio_set_value(GPIO_PTB7, 0);
831 } 829 }
832 830
833 static struct resource sh_mmcif_resources[] = { 831 static struct resource sh_mmcif_resources[] = {
834 [0] = { 832 [0] = {
835 .name = "SH_MMCIF", 833 .name = "SH_MMCIF",
836 .start = 0xA4CA0000, 834 .start = 0xA4CA0000,
837 .end = 0xA4CA00FF, 835 .end = 0xA4CA00FF,
838 .flags = IORESOURCE_MEM, 836 .flags = IORESOURCE_MEM,
839 }, 837 },
840 [1] = { 838 [1] = {
841 /* MMC2I */ 839 /* MMC2I */
842 .start = 29, 840 .start = 29,
843 .flags = IORESOURCE_IRQ, 841 .flags = IORESOURCE_IRQ,
844 }, 842 },
845 [2] = { 843 [2] = {
846 /* MMC3I */ 844 /* MMC3I */
847 .start = 30, 845 .start = 30,
848 .flags = IORESOURCE_IRQ, 846 .flags = IORESOURCE_IRQ,
849 }, 847 },
850 }; 848 };
851 849
852 static struct sh_mmcif_plat_data sh_mmcif_plat = { 850 static struct sh_mmcif_plat_data sh_mmcif_plat = {
853 .set_pwr = mmcif_set_pwr, 851 .set_pwr = mmcif_set_pwr,
854 .down_pwr = mmcif_down_pwr, 852 .down_pwr = mmcif_down_pwr,
855 .sup_pclk = 0, /* SH7724: Max Pclk/2 */ 853 .sup_pclk = 0, /* SH7724: Max Pclk/2 */
856 .caps = MMC_CAP_4_BIT_DATA | 854 .caps = MMC_CAP_4_BIT_DATA |
857 MMC_CAP_8_BIT_DATA | 855 MMC_CAP_8_BIT_DATA |
858 MMC_CAP_NEEDS_POLL, 856 MMC_CAP_NEEDS_POLL,
859 .ocr = MMC_VDD_32_33 | MMC_VDD_33_34, 857 .ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
860 }; 858 };
861 859
862 static struct platform_device sh_mmcif_device = { 860 static struct platform_device sh_mmcif_device = {
863 .name = "sh_mmcif", 861 .name = "sh_mmcif",
864 .id = 0, 862 .id = 0,
865 .dev = { 863 .dev = {
866 .platform_data = &sh_mmcif_plat, 864 .platform_data = &sh_mmcif_plat,
867 }, 865 },
868 .num_resources = ARRAY_SIZE(sh_mmcif_resources), 866 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
869 .resource = sh_mmcif_resources, 867 .resource = sh_mmcif_resources,
870 }; 868 };
871 #endif 869 #endif
872 870
873 static struct platform_device *ecovec_devices[] __initdata = { 871 static struct platform_device *ecovec_devices[] __initdata = {
874 &heartbeat_device, 872 &heartbeat_device,
875 &nor_flash_device, 873 &nor_flash_device,
876 &sh_eth_device, 874 &sh_eth_device,
877 &usb0_host_device, 875 &usb0_host_device,
878 &usb1_common_device, 876 &usb1_common_device,
879 &lcdc_device, 877 &lcdc_device,
880 &ceu0_device, 878 &ceu0_device,
881 &ceu1_device, 879 &ceu1_device,
882 &keysc_device, 880 &keysc_device,
883 #ifdef CONFIG_MFD_SH_MOBILE_SDHI 881 #ifdef CONFIG_MFD_SH_MOBILE_SDHI
884 &sdhi0_device, 882 &sdhi0_device,
885 #if !defined(CONFIG_MMC_SH_MMCIF) 883 #if !defined(CONFIG_MMC_SH_MMCIF)
886 &sdhi1_device, 884 &sdhi1_device,
887 #endif 885 #endif
888 #else 886 #else
889 &msiof0_device, 887 &msiof0_device,
890 #endif 888 #endif
891 &camera_devices[0], 889 &camera_devices[0],
892 &camera_devices[1], 890 &camera_devices[1],
893 &camera_devices[2], 891 &camera_devices[2],
894 &fsi_device, 892 &fsi_device,
895 &irda_device, 893 &irda_device,
896 &vou_device, 894 &vou_device,
897 #if defined(CONFIG_MMC_SH_MMCIF) 895 #if defined(CONFIG_MMC_SH_MMCIF)
898 &sh_mmcif_device, 896 &sh_mmcif_device,
899 #endif 897 #endif
900 }; 898 };
901 899
902 #ifdef CONFIG_I2C 900 #ifdef CONFIG_I2C
903 #define EEPROM_ADDR 0x50 901 #define EEPROM_ADDR 0x50
904 static u8 mac_read(struct i2c_adapter *a, u8 command) 902 static u8 mac_read(struct i2c_adapter *a, u8 command)
905 { 903 {
906 struct i2c_msg msg[2]; 904 struct i2c_msg msg[2];
907 u8 buf; 905 u8 buf;
908 int ret; 906 int ret;
909 907
910 msg[0].addr = EEPROM_ADDR; 908 msg[0].addr = EEPROM_ADDR;
911 msg[0].flags = 0; 909 msg[0].flags = 0;
912 msg[0].len = 1; 910 msg[0].len = 1;
913 msg[0].buf = &command; 911 msg[0].buf = &command;
914 912
915 msg[1].addr = EEPROM_ADDR; 913 msg[1].addr = EEPROM_ADDR;
916 msg[1].flags = I2C_M_RD; 914 msg[1].flags = I2C_M_RD;
917 msg[1].len = 1; 915 msg[1].len = 1;
918 msg[1].buf = &buf; 916 msg[1].buf = &buf;
919 917
920 ret = i2c_transfer(a, msg, 2); 918 ret = i2c_transfer(a, msg, 2);
921 if (ret < 0) { 919 if (ret < 0) {
922 printk(KERN_ERR "error %d\n", ret); 920 printk(KERN_ERR "error %d\n", ret);
923 buf = 0xff; 921 buf = 0xff;
924 } 922 }
925 923
926 return buf; 924 return buf;
927 } 925 }
928 926
929 static void __init sh_eth_init(struct sh_eth_plat_data *pd) 927 static void __init sh_eth_init(struct sh_eth_plat_data *pd)
930 { 928 {
931 struct i2c_adapter *a = i2c_get_adapter(1); 929 struct i2c_adapter *a = i2c_get_adapter(1);
932 int i; 930 int i;
933 931
934 if (!a) { 932 if (!a) {
935 pr_err("can not get I2C 1\n"); 933 pr_err("can not get I2C 1\n");
936 return; 934 return;
937 } 935 }
938 936
939 /* read MAC address frome EEPROM */ 937 /* read MAC address frome EEPROM */
940 for (i = 0; i < sizeof(pd->mac_addr); i++) { 938 for (i = 0; i < sizeof(pd->mac_addr); i++) {
941 pd->mac_addr[i] = mac_read(a, 0x10 + i); 939 pd->mac_addr[i] = mac_read(a, 0x10 + i);
942 msleep(10); 940 msleep(10);
943 } 941 }
944 942
945 i2c_put_adapter(a); 943 i2c_put_adapter(a);
946 } 944 }
947 #else 945 #else
948 static void __init sh_eth_init(struct sh_eth_plat_data *pd) 946 static void __init sh_eth_init(struct sh_eth_plat_data *pd)
949 { 947 {
950 pr_err("unable to read sh_eth MAC address\n"); 948 pr_err("unable to read sh_eth MAC address\n");
951 } 949 }
952 #endif 950 #endif
953 951
954 #define PORT_HIZA 0xA4050158 952 #define PORT_HIZA 0xA4050158
955 #define IODRIVEA 0xA405018A 953 #define IODRIVEA 0xA405018A
956 954
957 extern char ecovec24_sdram_enter_start; 955 extern char ecovec24_sdram_enter_start;
958 extern char ecovec24_sdram_enter_end; 956 extern char ecovec24_sdram_enter_end;
959 extern char ecovec24_sdram_leave_start; 957 extern char ecovec24_sdram_leave_start;
960 extern char ecovec24_sdram_leave_end; 958 extern char ecovec24_sdram_leave_end;
961 959
962 static int __init arch_setup(void) 960 static int __init arch_setup(void)
963 { 961 {
964 struct clk *clk; 962 struct clk *clk;
965 963
966 /* register board specific self-refresh code */ 964 /* register board specific self-refresh code */
967 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | 965 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
968 SUSP_SH_RSTANDBY, 966 SUSP_SH_RSTANDBY,
969 &ecovec24_sdram_enter_start, 967 &ecovec24_sdram_enter_start,
970 &ecovec24_sdram_enter_end, 968 &ecovec24_sdram_enter_end,
971 &ecovec24_sdram_leave_start, 969 &ecovec24_sdram_leave_start,
972 &ecovec24_sdram_leave_end); 970 &ecovec24_sdram_leave_end);
973 971
974 /* enable STATUS0, STATUS2 and PDSTATUS */ 972 /* enable STATUS0, STATUS2 and PDSTATUS */
975 gpio_request(GPIO_FN_STATUS0, NULL); 973 gpio_request(GPIO_FN_STATUS0, NULL);
976 gpio_request(GPIO_FN_STATUS2, NULL); 974 gpio_request(GPIO_FN_STATUS2, NULL);
977 gpio_request(GPIO_FN_PDSTATUS, NULL); 975 gpio_request(GPIO_FN_PDSTATUS, NULL);
978 976
979 /* enable SCIFA0 */ 977 /* enable SCIFA0 */
980 gpio_request(GPIO_FN_SCIF0_TXD, NULL); 978 gpio_request(GPIO_FN_SCIF0_TXD, NULL);
981 gpio_request(GPIO_FN_SCIF0_RXD, NULL); 979 gpio_request(GPIO_FN_SCIF0_RXD, NULL);
982 980
983 /* enable debug LED */ 981 /* enable debug LED */
984 gpio_request(GPIO_PTG0, NULL); 982 gpio_request(GPIO_PTG0, NULL);
985 gpio_request(GPIO_PTG1, NULL); 983 gpio_request(GPIO_PTG1, NULL);
986 gpio_request(GPIO_PTG2, NULL); 984 gpio_request(GPIO_PTG2, NULL);
987 gpio_request(GPIO_PTG3, NULL); 985 gpio_request(GPIO_PTG3, NULL);
988 gpio_direction_output(GPIO_PTG0, 0); 986 gpio_direction_output(GPIO_PTG0, 0);
989 gpio_direction_output(GPIO_PTG1, 0); 987 gpio_direction_output(GPIO_PTG1, 0);
990 gpio_direction_output(GPIO_PTG2, 0); 988 gpio_direction_output(GPIO_PTG2, 0);
991 gpio_direction_output(GPIO_PTG3, 0); 989 gpio_direction_output(GPIO_PTG3, 0);
992 __raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA); 990 __raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
993 991
994 /* enable SH-Eth */ 992 /* enable SH-Eth */
995 gpio_request(GPIO_PTA1, NULL); 993 gpio_request(GPIO_PTA1, NULL);
996 gpio_direction_output(GPIO_PTA1, 1); 994 gpio_direction_output(GPIO_PTA1, 1);
997 mdelay(20); 995 mdelay(20);
998 996
999 gpio_request(GPIO_FN_RMII_RXD0, NULL); 997 gpio_request(GPIO_FN_RMII_RXD0, NULL);
1000 gpio_request(GPIO_FN_RMII_RXD1, NULL); 998 gpio_request(GPIO_FN_RMII_RXD1, NULL);
1001 gpio_request(GPIO_FN_RMII_TXD0, NULL); 999 gpio_request(GPIO_FN_RMII_TXD0, NULL);
1002 gpio_request(GPIO_FN_RMII_TXD1, NULL); 1000 gpio_request(GPIO_FN_RMII_TXD1, NULL);
1003 gpio_request(GPIO_FN_RMII_REF_CLK, NULL); 1001 gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
1004 gpio_request(GPIO_FN_RMII_TX_EN, NULL); 1002 gpio_request(GPIO_FN_RMII_TX_EN, NULL);
1005 gpio_request(GPIO_FN_RMII_RX_ER, NULL); 1003 gpio_request(GPIO_FN_RMII_RX_ER, NULL);
1006 gpio_request(GPIO_FN_RMII_CRS_DV, NULL); 1004 gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
1007 gpio_request(GPIO_FN_MDIO, NULL); 1005 gpio_request(GPIO_FN_MDIO, NULL);
1008 gpio_request(GPIO_FN_MDC, NULL); 1006 gpio_request(GPIO_FN_MDC, NULL);
1009 gpio_request(GPIO_FN_LNKSTA, NULL); 1007 gpio_request(GPIO_FN_LNKSTA, NULL);
1010 1008
1011 /* enable USB */ 1009 /* enable USB */
1012 __raw_writew(0x0000, 0xA4D80000); 1010 __raw_writew(0x0000, 0xA4D80000);
1013 __raw_writew(0x0000, 0xA4D90000); 1011 __raw_writew(0x0000, 0xA4D90000);
1014 gpio_request(GPIO_PTB3, NULL); 1012 gpio_request(GPIO_PTB3, NULL);
1015 gpio_request(GPIO_PTB4, NULL); 1013 gpio_request(GPIO_PTB4, NULL);
1016 gpio_request(GPIO_PTB5, NULL); 1014 gpio_request(GPIO_PTB5, NULL);
1017 gpio_direction_input(GPIO_PTB3); 1015 gpio_direction_input(GPIO_PTB3);
1018 gpio_direction_output(GPIO_PTB4, 0); 1016 gpio_direction_output(GPIO_PTB4, 0);
1019 gpio_direction_output(GPIO_PTB5, 0); 1017 gpio_direction_output(GPIO_PTB5, 0);
1020 __raw_writew(0x0600, 0xa40501d4); 1018 __raw_writew(0x0600, 0xa40501d4);
1021 __raw_writew(0x0600, 0xa4050192); 1019 __raw_writew(0x0600, 0xa4050192);
1022 1020
1023 if (gpio_get_value(GPIO_PTB3)) { 1021 if (gpio_get_value(GPIO_PTB3)) {
1024 printk(KERN_INFO "USB1 function is selected\n"); 1022 printk(KERN_INFO "USB1 function is selected\n");
1025 usb1_common_device.name = "r8a66597_udc"; 1023 usb1_common_device.name = "r8a66597_udc";
1026 } else { 1024 } else {
1027 printk(KERN_INFO "USB1 host is selected\n"); 1025 printk(KERN_INFO "USB1 host is selected\n");
1028 usb1_common_device.name = "r8a66597_hcd"; 1026 usb1_common_device.name = "r8a66597_hcd";
1029 } 1027 }
1030 1028
1031 /* enable LCDC */ 1029 /* enable LCDC */
1032 gpio_request(GPIO_FN_LCDD23, NULL); 1030 gpio_request(GPIO_FN_LCDD23, NULL);
1033 gpio_request(GPIO_FN_LCDD22, NULL); 1031 gpio_request(GPIO_FN_LCDD22, NULL);
1034 gpio_request(GPIO_FN_LCDD21, NULL); 1032 gpio_request(GPIO_FN_LCDD21, NULL);
1035 gpio_request(GPIO_FN_LCDD20, NULL); 1033 gpio_request(GPIO_FN_LCDD20, NULL);
1036 gpio_request(GPIO_FN_LCDD19, NULL); 1034 gpio_request(GPIO_FN_LCDD19, NULL);
1037 gpio_request(GPIO_FN_LCDD18, NULL); 1035 gpio_request(GPIO_FN_LCDD18, NULL);
1038 gpio_request(GPIO_FN_LCDD17, NULL); 1036 gpio_request(GPIO_FN_LCDD17, NULL);
1039 gpio_request(GPIO_FN_LCDD16, NULL); 1037 gpio_request(GPIO_FN_LCDD16, NULL);
1040 gpio_request(GPIO_FN_LCDD15, NULL); 1038 gpio_request(GPIO_FN_LCDD15, NULL);
1041 gpio_request(GPIO_FN_LCDD14, NULL); 1039 gpio_request(GPIO_FN_LCDD14, NULL);
1042 gpio_request(GPIO_FN_LCDD13, NULL); 1040 gpio_request(GPIO_FN_LCDD13, NULL);
1043 gpio_request(GPIO_FN_LCDD12, NULL); 1041 gpio_request(GPIO_FN_LCDD12, NULL);
1044 gpio_request(GPIO_FN_LCDD11, NULL); 1042 gpio_request(GPIO_FN_LCDD11, NULL);
1045 gpio_request(GPIO_FN_LCDD10, NULL); 1043 gpio_request(GPIO_FN_LCDD10, NULL);
1046 gpio_request(GPIO_FN_LCDD9, NULL); 1044 gpio_request(GPIO_FN_LCDD9, NULL);
1047 gpio_request(GPIO_FN_LCDD8, NULL); 1045 gpio_request(GPIO_FN_LCDD8, NULL);
1048 gpio_request(GPIO_FN_LCDD7, NULL); 1046 gpio_request(GPIO_FN_LCDD7, NULL);
1049 gpio_request(GPIO_FN_LCDD6, NULL); 1047 gpio_request(GPIO_FN_LCDD6, NULL);
1050 gpio_request(GPIO_FN_LCDD5, NULL); 1048 gpio_request(GPIO_FN_LCDD5, NULL);
1051 gpio_request(GPIO_FN_LCDD4, NULL); 1049 gpio_request(GPIO_FN_LCDD4, NULL);
1052 gpio_request(GPIO_FN_LCDD3, NULL); 1050 gpio_request(GPIO_FN_LCDD3, NULL);
1053 gpio_request(GPIO_FN_LCDD2, NULL); 1051 gpio_request(GPIO_FN_LCDD2, NULL);
1054 gpio_request(GPIO_FN_LCDD1, NULL); 1052 gpio_request(GPIO_FN_LCDD1, NULL);
1055 gpio_request(GPIO_FN_LCDD0, NULL); 1053 gpio_request(GPIO_FN_LCDD0, NULL);
1056 gpio_request(GPIO_FN_LCDDISP, NULL); 1054 gpio_request(GPIO_FN_LCDDISP, NULL);
1057 gpio_request(GPIO_FN_LCDHSYN, NULL); 1055 gpio_request(GPIO_FN_LCDHSYN, NULL);
1058 gpio_request(GPIO_FN_LCDDCK, NULL); 1056 gpio_request(GPIO_FN_LCDDCK, NULL);
1059 gpio_request(GPIO_FN_LCDVSYN, NULL); 1057 gpio_request(GPIO_FN_LCDVSYN, NULL);
1060 gpio_request(GPIO_FN_LCDDON, NULL); 1058 gpio_request(GPIO_FN_LCDDON, NULL);
1061 gpio_request(GPIO_FN_LCDLCLK, NULL); 1059 gpio_request(GPIO_FN_LCDLCLK, NULL);
1062 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA); 1060 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
1063 1061
1064 gpio_request(GPIO_PTE6, NULL); 1062 gpio_request(GPIO_PTE6, NULL);
1065 gpio_request(GPIO_PTU1, NULL); 1063 gpio_request(GPIO_PTU1, NULL);
1066 gpio_request(GPIO_PTR1, NULL); 1064 gpio_request(GPIO_PTR1, NULL);
1067 gpio_request(GPIO_PTA2, NULL); 1065 gpio_request(GPIO_PTA2, NULL);
1068 gpio_direction_input(GPIO_PTE6); 1066 gpio_direction_input(GPIO_PTE6);
1069 gpio_direction_output(GPIO_PTU1, 0); 1067 gpio_direction_output(GPIO_PTU1, 0);
1070 gpio_direction_output(GPIO_PTR1, 0); 1068 gpio_direction_output(GPIO_PTR1, 0);
1071 gpio_direction_output(GPIO_PTA2, 0); 1069 gpio_direction_output(GPIO_PTA2, 0);
1072 1070
1073 /* I/O buffer drive ability is high */ 1071 /* I/O buffer drive ability is high */
1074 __raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA); 1072 __raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
1075 1073
1076 if (gpio_get_value(GPIO_PTE6)) { 1074 if (gpio_get_value(GPIO_PTE6)) {
1077 /* DVI */ 1075 /* DVI */
1078 lcdc_info.clock_source = LCDC_CLK_EXTERNAL; 1076 lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
1079 lcdc_info.ch[0].clock_divider = 1; 1077 lcdc_info.ch[0].clock_divider = 1;
1080 lcdc_info.ch[0].lcd_cfg = ecovec_dvi_modes; 1078 lcdc_info.ch[0].lcd_cfg = ecovec_dvi_modes;
1081 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_dvi_modes); 1079 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_dvi_modes);
1082 1080
1083 gpio_set_value(GPIO_PTA2, 1); 1081 gpio_set_value(GPIO_PTA2, 1);
1084 gpio_set_value(GPIO_PTU1, 1); 1082 gpio_set_value(GPIO_PTU1, 1);
1085 } else { 1083 } else {
1086 /* Panel */ 1084 /* Panel */
1087 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL; 1085 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
1088 lcdc_info.ch[0].clock_divider = 2; 1086 lcdc_info.ch[0].clock_divider = 2;
1089 lcdc_info.ch[0].lcd_cfg = ecovec_lcd_modes; 1087 lcdc_info.ch[0].lcd_cfg = ecovec_lcd_modes;
1090 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_lcd_modes); 1088 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_lcd_modes);
1091 1089
1092 gpio_set_value(GPIO_PTR1, 1); 1090 gpio_set_value(GPIO_PTR1, 1);
1093 1091
1094 /* FIXME 1092 /* FIXME
1095 * 1093 *
1096 * LCDDON control is needed for Panel, 1094 * LCDDON control is needed for Panel,
1097 * but current sh_mobile_lcdc driver doesn't control it. 1095 * but current sh_mobile_lcdc driver doesn't control it.
1098 * It is temporary correspondence 1096 * It is temporary correspondence
1099 */ 1097 */
1100 gpio_request(GPIO_PTF4, NULL); 1098 gpio_request(GPIO_PTF4, NULL);
1101 gpio_direction_output(GPIO_PTF4, 1); 1099 gpio_direction_output(GPIO_PTF4, 1);
1102 1100
1103 /* enable TouchScreen */ 1101 /* enable TouchScreen */
1104 i2c_register_board_info(0, &ts_i2c_clients, 1); 1102 i2c_register_board_info(0, &ts_i2c_clients, 1);
1105 set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW); 1103 set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW);
1106 } 1104 }
1107 1105
1108 /* enable CEU0 */ 1106 /* enable CEU0 */
1109 gpio_request(GPIO_FN_VIO0_D15, NULL); 1107 gpio_request(GPIO_FN_VIO0_D15, NULL);
1110 gpio_request(GPIO_FN_VIO0_D14, NULL); 1108 gpio_request(GPIO_FN_VIO0_D14, NULL);
1111 gpio_request(GPIO_FN_VIO0_D13, NULL); 1109 gpio_request(GPIO_FN_VIO0_D13, NULL);
1112 gpio_request(GPIO_FN_VIO0_D12, NULL); 1110 gpio_request(GPIO_FN_VIO0_D12, NULL);
1113 gpio_request(GPIO_FN_VIO0_D11, NULL); 1111 gpio_request(GPIO_FN_VIO0_D11, NULL);
1114 gpio_request(GPIO_FN_VIO0_D10, NULL); 1112 gpio_request(GPIO_FN_VIO0_D10, NULL);
1115 gpio_request(GPIO_FN_VIO0_D9, NULL); 1113 gpio_request(GPIO_FN_VIO0_D9, NULL);
1116 gpio_request(GPIO_FN_VIO0_D8, NULL); 1114 gpio_request(GPIO_FN_VIO0_D8, NULL);
1117 gpio_request(GPIO_FN_VIO0_D7, NULL); 1115 gpio_request(GPIO_FN_VIO0_D7, NULL);
1118 gpio_request(GPIO_FN_VIO0_D6, NULL); 1116 gpio_request(GPIO_FN_VIO0_D6, NULL);
1119 gpio_request(GPIO_FN_VIO0_D5, NULL); 1117 gpio_request(GPIO_FN_VIO0_D5, NULL);
1120 gpio_request(GPIO_FN_VIO0_D4, NULL); 1118 gpio_request(GPIO_FN_VIO0_D4, NULL);
1121 gpio_request(GPIO_FN_VIO0_D3, NULL); 1119 gpio_request(GPIO_FN_VIO0_D3, NULL);
1122 gpio_request(GPIO_FN_VIO0_D2, NULL); 1120 gpio_request(GPIO_FN_VIO0_D2, NULL);
1123 gpio_request(GPIO_FN_VIO0_D1, NULL); 1121 gpio_request(GPIO_FN_VIO0_D1, NULL);
1124 gpio_request(GPIO_FN_VIO0_D0, NULL); 1122 gpio_request(GPIO_FN_VIO0_D0, NULL);
1125 gpio_request(GPIO_FN_VIO0_VD, NULL); 1123 gpio_request(GPIO_FN_VIO0_VD, NULL);
1126 gpio_request(GPIO_FN_VIO0_CLK, NULL); 1124 gpio_request(GPIO_FN_VIO0_CLK, NULL);
1127 gpio_request(GPIO_FN_VIO0_FLD, NULL); 1125 gpio_request(GPIO_FN_VIO0_FLD, NULL);
1128 gpio_request(GPIO_FN_VIO0_HD, NULL); 1126 gpio_request(GPIO_FN_VIO0_HD, NULL);
1129 platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); 1127 platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
1130 1128
1131 /* enable CEU1 */ 1129 /* enable CEU1 */
1132 gpio_request(GPIO_FN_VIO1_D7, NULL); 1130 gpio_request(GPIO_FN_VIO1_D7, NULL);
1133 gpio_request(GPIO_FN_VIO1_D6, NULL); 1131 gpio_request(GPIO_FN_VIO1_D6, NULL);
1134 gpio_request(GPIO_FN_VIO1_D5, NULL); 1132 gpio_request(GPIO_FN_VIO1_D5, NULL);
1135 gpio_request(GPIO_FN_VIO1_D4, NULL); 1133 gpio_request(GPIO_FN_VIO1_D4, NULL);
1136 gpio_request(GPIO_FN_VIO1_D3, NULL); 1134 gpio_request(GPIO_FN_VIO1_D3, NULL);
1137 gpio_request(GPIO_FN_VIO1_D2, NULL); 1135 gpio_request(GPIO_FN_VIO1_D2, NULL);
1138 gpio_request(GPIO_FN_VIO1_D1, NULL); 1136 gpio_request(GPIO_FN_VIO1_D1, NULL);
1139 gpio_request(GPIO_FN_VIO1_D0, NULL); 1137 gpio_request(GPIO_FN_VIO1_D0, NULL);
1140 gpio_request(GPIO_FN_VIO1_FLD, NULL); 1138 gpio_request(GPIO_FN_VIO1_FLD, NULL);
1141 gpio_request(GPIO_FN_VIO1_HD, NULL); 1139 gpio_request(GPIO_FN_VIO1_HD, NULL);
1142 gpio_request(GPIO_FN_VIO1_VD, NULL); 1140 gpio_request(GPIO_FN_VIO1_VD, NULL);
1143 gpio_request(GPIO_FN_VIO1_CLK, NULL); 1141 gpio_request(GPIO_FN_VIO1_CLK, NULL);
1144 platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); 1142 platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
1145 1143
1146 /* enable KEYSC */ 1144 /* enable KEYSC */
1147 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); 1145 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
1148 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); 1146 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
1149 gpio_request(GPIO_FN_KEYOUT3, NULL); 1147 gpio_request(GPIO_FN_KEYOUT3, NULL);
1150 gpio_request(GPIO_FN_KEYOUT2, NULL); 1148 gpio_request(GPIO_FN_KEYOUT2, NULL);
1151 gpio_request(GPIO_FN_KEYOUT1, NULL); 1149 gpio_request(GPIO_FN_KEYOUT1, NULL);
1152 gpio_request(GPIO_FN_KEYOUT0, NULL); 1150 gpio_request(GPIO_FN_KEYOUT0, NULL);
1153 gpio_request(GPIO_FN_KEYIN0, NULL); 1151 gpio_request(GPIO_FN_KEYIN0, NULL);
1154 1152
1155 /* enable user debug switch */ 1153 /* enable user debug switch */
1156 gpio_request(GPIO_PTR0, NULL); 1154 gpio_request(GPIO_PTR0, NULL);
1157 gpio_request(GPIO_PTR4, NULL); 1155 gpio_request(GPIO_PTR4, NULL);
1158 gpio_request(GPIO_PTR5, NULL); 1156 gpio_request(GPIO_PTR5, NULL);
1159 gpio_request(GPIO_PTR6, NULL); 1157 gpio_request(GPIO_PTR6, NULL);
1160 gpio_direction_input(GPIO_PTR0); 1158 gpio_direction_input(GPIO_PTR0);
1161 gpio_direction_input(GPIO_PTR4); 1159 gpio_direction_input(GPIO_PTR4);
1162 gpio_direction_input(GPIO_PTR5); 1160 gpio_direction_input(GPIO_PTR5);
1163 gpio_direction_input(GPIO_PTR6); 1161 gpio_direction_input(GPIO_PTR6);
1164 1162
1165 #ifdef CONFIG_MFD_SH_MOBILE_SDHI 1163 #ifdef CONFIG_MFD_SH_MOBILE_SDHI
1166 /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */ 1164 /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */
1167 gpio_request(GPIO_FN_SDHI0CD, NULL); 1165 gpio_request(GPIO_FN_SDHI0CD, NULL);
1168 gpio_request(GPIO_FN_SDHI0WP, NULL); 1166 gpio_request(GPIO_FN_SDHI0WP, NULL);
1169 gpio_request(GPIO_FN_SDHI0CMD, NULL); 1167 gpio_request(GPIO_FN_SDHI0CMD, NULL);
1170 gpio_request(GPIO_FN_SDHI0CLK, NULL); 1168 gpio_request(GPIO_FN_SDHI0CLK, NULL);
1171 gpio_request(GPIO_FN_SDHI0D3, NULL); 1169 gpio_request(GPIO_FN_SDHI0D3, NULL);
1172 gpio_request(GPIO_FN_SDHI0D2, NULL); 1170 gpio_request(GPIO_FN_SDHI0D2, NULL);
1173 gpio_request(GPIO_FN_SDHI0D1, NULL); 1171 gpio_request(GPIO_FN_SDHI0D1, NULL);
1174 gpio_request(GPIO_FN_SDHI0D0, NULL); 1172 gpio_request(GPIO_FN_SDHI0D0, NULL);
1175 gpio_request(GPIO_PTB6, NULL); 1173 gpio_request(GPIO_PTB6, NULL);
1176 gpio_direction_output(GPIO_PTB6, 0); 1174 gpio_direction_output(GPIO_PTB6, 0);
1177 1175
1178 #if !defined(CONFIG_MMC_SH_MMCIF) 1176 #if !defined(CONFIG_MMC_SH_MMCIF)
1179 /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */ 1177 /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
1180 gpio_request(GPIO_FN_SDHI1CD, NULL); 1178 gpio_request(GPIO_FN_SDHI1CD, NULL);
1181 gpio_request(GPIO_FN_SDHI1WP, NULL); 1179 gpio_request(GPIO_FN_SDHI1WP, NULL);
1182 gpio_request(GPIO_FN_SDHI1CMD, NULL); 1180 gpio_request(GPIO_FN_SDHI1CMD, NULL);
1183 gpio_request(GPIO_FN_SDHI1CLK, NULL); 1181 gpio_request(GPIO_FN_SDHI1CLK, NULL);
1184 gpio_request(GPIO_FN_SDHI1D3, NULL); 1182 gpio_request(GPIO_FN_SDHI1D3, NULL);
1185 gpio_request(GPIO_FN_SDHI1D2, NULL); 1183 gpio_request(GPIO_FN_SDHI1D2, NULL);
1186 gpio_request(GPIO_FN_SDHI1D1, NULL); 1184 gpio_request(GPIO_FN_SDHI1D1, NULL);
1187 gpio_request(GPIO_FN_SDHI1D0, NULL); 1185 gpio_request(GPIO_FN_SDHI1D0, NULL);
1188 gpio_request(GPIO_PTB7, NULL); 1186 gpio_request(GPIO_PTB7, NULL);
1189 gpio_direction_output(GPIO_PTB7, 0); 1187 gpio_direction_output(GPIO_PTB7, 0);
1190 1188
1191 /* I/O buffer drive ability is high for SDHI1 */ 1189 /* I/O buffer drive ability is high for SDHI1 */
1192 __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA); 1190 __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
1193 #endif /* CONFIG_MMC_SH_MMCIF */ 1191 #endif /* CONFIG_MMC_SH_MMCIF */
1194 #else 1192 #else
1195 /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */ 1193 /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
1196 gpio_request(GPIO_FN_MSIOF0_TXD, NULL); 1194 gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
1197 gpio_request(GPIO_FN_MSIOF0_RXD, NULL); 1195 gpio_request(GPIO_FN_MSIOF0_RXD, NULL);
1198 gpio_request(GPIO_FN_MSIOF0_TSCK, NULL); 1196 gpio_request(GPIO_FN_MSIOF0_TSCK, NULL);
1199 gpio_request(GPIO_PTM4, NULL); /* software CS control of TSYNC pin */ 1197 gpio_request(GPIO_PTM4, NULL); /* software CS control of TSYNC pin */
1200 gpio_direction_output(GPIO_PTM4, 1); /* active low CS */ 1198 gpio_direction_output(GPIO_PTM4, 1); /* active low CS */
1201 gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */ 1199 gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */
1202 gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */ 1200 gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */
1203 gpio_request(GPIO_PTY6, NULL); /* write protect */ 1201 gpio_request(GPIO_PTY6, NULL); /* write protect */
1204 gpio_direction_input(GPIO_PTY6); 1202 gpio_direction_input(GPIO_PTY6);
1205 gpio_request(GPIO_PTY7, NULL); /* card detect */ 1203 gpio_request(GPIO_PTY7, NULL); /* card detect */
1206 gpio_direction_input(GPIO_PTY7); 1204 gpio_direction_input(GPIO_PTY7);
1207 1205
1208 spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus)); 1206 spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
1209 #endif 1207 #endif
1210 1208
1211 /* enable Video */ 1209 /* enable Video */
1212 gpio_request(GPIO_PTU2, NULL); 1210 gpio_request(GPIO_PTU2, NULL);
1213 gpio_direction_output(GPIO_PTU2, 1); 1211 gpio_direction_output(GPIO_PTU2, 1);
1214 1212
1215 /* enable Camera */ 1213 /* enable Camera */
1216 gpio_request(GPIO_PTA3, NULL); 1214 gpio_request(GPIO_PTA3, NULL);
1217 gpio_request(GPIO_PTA4, NULL); 1215 gpio_request(GPIO_PTA4, NULL);
1218 gpio_direction_output(GPIO_PTA3, 0); 1216 gpio_direction_output(GPIO_PTA3, 0);
1219 gpio_direction_output(GPIO_PTA4, 0); 1217 gpio_direction_output(GPIO_PTA4, 0);
1220 1218
1221 /* enable FSI */ 1219 /* enable FSI */
1222 gpio_request(GPIO_FN_FSIMCKB, NULL); 1220 gpio_request(GPIO_FN_FSIMCKB, NULL);
1223 gpio_request(GPIO_FN_FSIIBSD, NULL); 1221 gpio_request(GPIO_FN_FSIIBSD, NULL);
1224 gpio_request(GPIO_FN_FSIOBSD, NULL); 1222 gpio_request(GPIO_FN_FSIOBSD, NULL);
1225 gpio_request(GPIO_FN_FSIIBBCK, NULL); 1223 gpio_request(GPIO_FN_FSIIBBCK, NULL);
1226 gpio_request(GPIO_FN_FSIIBLRCK, NULL); 1224 gpio_request(GPIO_FN_FSIIBLRCK, NULL);
1227 gpio_request(GPIO_FN_FSIOBBCK, NULL); 1225 gpio_request(GPIO_FN_FSIOBBCK, NULL);
1228 gpio_request(GPIO_FN_FSIOBLRCK, NULL); 1226 gpio_request(GPIO_FN_FSIOBLRCK, NULL);
1229 gpio_request(GPIO_FN_CLKAUDIOBO, NULL); 1227 gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
1230 1228
1231 /* set SPU2 clock to 83.4 MHz */ 1229 /* set SPU2 clock to 83.4 MHz */
1232 clk = clk_get(NULL, "spu_clk"); 1230 clk = clk_get(NULL, "spu_clk");
1233 if (!IS_ERR(clk)) { 1231 if (!IS_ERR(clk)) {
1234 clk_set_rate(clk, clk_round_rate(clk, 83333333)); 1232 clk_set_rate(clk, clk_round_rate(clk, 83333333));
1235 clk_put(clk); 1233 clk_put(clk);
1236 } 1234 }
1237 1235
1238 /* change parent of FSI B */ 1236 /* change parent of FSI B */
1239 clk = clk_get(NULL, "fsib_clk"); 1237 clk = clk_get(NULL, "fsib_clk");
1240 if (!IS_ERR(clk)) { 1238 if (!IS_ERR(clk)) {
1241 /* 48kHz dummy clock was used to make sure 1/1 divide */ 1239 /* 48kHz dummy clock was used to make sure 1/1 divide */
1242 clk_set_rate(&sh7724_fsimckb_clk, 48000); 1240 clk_set_rate(&sh7724_fsimckb_clk, 48000);
1243 clk_set_parent(clk, &sh7724_fsimckb_clk); 1241 clk_set_parent(clk, &sh7724_fsimckb_clk);
1244 clk_set_rate(clk, 48000); 1242 clk_set_rate(clk, 48000);
1245 clk_put(clk); 1243 clk_put(clk);
1246 } 1244 }
1247 1245
1248 gpio_request(GPIO_PTU0, NULL); 1246 gpio_request(GPIO_PTU0, NULL);
1249 gpio_direction_output(GPIO_PTU0, 0); 1247 gpio_direction_output(GPIO_PTU0, 0);
1250 mdelay(20); 1248 mdelay(20);
1251 1249
1252 /* enable motion sensor */ 1250 /* enable motion sensor */
1253 gpio_request(GPIO_FN_INTC_IRQ1, NULL); 1251 gpio_request(GPIO_FN_INTC_IRQ1, NULL);
1254 gpio_direction_input(GPIO_FN_INTC_IRQ1); 1252 gpio_direction_input(GPIO_FN_INTC_IRQ1);
1255 1253
1256 /* set VPU clock to 166 MHz */ 1254 /* set VPU clock to 166 MHz */
1257 clk = clk_get(NULL, "vpu_clk"); 1255 clk = clk_get(NULL, "vpu_clk");
1258 if (!IS_ERR(clk)) { 1256 if (!IS_ERR(clk)) {
1259 clk_set_rate(clk, clk_round_rate(clk, 166000000)); 1257 clk_set_rate(clk, clk_round_rate(clk, 166000000));
1260 clk_put(clk); 1258 clk_put(clk);
1261 } 1259 }
1262 1260
1263 /* enable IrDA */ 1261 /* enable IrDA */
1264 gpio_request(GPIO_FN_IRDA_OUT, NULL); 1262 gpio_request(GPIO_FN_IRDA_OUT, NULL);
1265 gpio_request(GPIO_FN_IRDA_IN, NULL); 1263 gpio_request(GPIO_FN_IRDA_IN, NULL);
1266 gpio_request(GPIO_PTU5, NULL); 1264 gpio_request(GPIO_PTU5, NULL);
1267 gpio_direction_output(GPIO_PTU5, 0); 1265 gpio_direction_output(GPIO_PTU5, 0);
1268 1266
1269 #if defined(CONFIG_MMC_SH_MMCIF) 1267 #if defined(CONFIG_MMC_SH_MMCIF)
1270 /* enable MMCIF (needs DS2.6,7 set to OFF,ON) */ 1268 /* enable MMCIF (needs DS2.6,7 set to OFF,ON) */
1271 gpio_request(GPIO_FN_MMC_D7, NULL); 1269 gpio_request(GPIO_FN_MMC_D7, NULL);
1272 gpio_request(GPIO_FN_MMC_D6, NULL); 1270 gpio_request(GPIO_FN_MMC_D6, NULL);
1273 gpio_request(GPIO_FN_MMC_D5, NULL); 1271 gpio_request(GPIO_FN_MMC_D5, NULL);
1274 gpio_request(GPIO_FN_MMC_D4, NULL); 1272 gpio_request(GPIO_FN_MMC_D4, NULL);
1275 gpio_request(GPIO_FN_MMC_D3, NULL); 1273 gpio_request(GPIO_FN_MMC_D3, NULL);
1276 gpio_request(GPIO_FN_MMC_D2, NULL); 1274 gpio_request(GPIO_FN_MMC_D2, NULL);
1277 gpio_request(GPIO_FN_MMC_D1, NULL); 1275 gpio_request(GPIO_FN_MMC_D1, NULL);
1278 gpio_request(GPIO_FN_MMC_D0, NULL); 1276 gpio_request(GPIO_FN_MMC_D0, NULL);
1279 gpio_request(GPIO_FN_MMC_CLK, NULL); 1277 gpio_request(GPIO_FN_MMC_CLK, NULL);
1280 gpio_request(GPIO_FN_MMC_CMD, NULL); 1278 gpio_request(GPIO_FN_MMC_CMD, NULL);
1281 gpio_request(GPIO_PTB7, NULL); 1279 gpio_request(GPIO_PTB7, NULL);
1282 gpio_direction_output(GPIO_PTB7, 0); 1280 gpio_direction_output(GPIO_PTB7, 0);
1283 1281
1284 /* I/O buffer drive ability is high for MMCIF */ 1282 /* I/O buffer drive ability is high for MMCIF */
1285 __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA); 1283 __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
1286 #endif 1284 #endif
1287 1285
1288 /* enable I2C device */ 1286 /* enable I2C device */
1289 i2c_register_board_info(0, i2c0_devices, 1287 i2c_register_board_info(0, i2c0_devices,
1290 ARRAY_SIZE(i2c0_devices)); 1288 ARRAY_SIZE(i2c0_devices));
1291 1289
1292 i2c_register_board_info(1, i2c1_devices, 1290 i2c_register_board_info(1, i2c1_devices,
1293 ARRAY_SIZE(i2c1_devices)); 1291 ARRAY_SIZE(i2c1_devices));
1294 1292
1295 /* VOU */ 1293 /* VOU */
1296 gpio_request(GPIO_FN_DV_D15, NULL); 1294 gpio_request(GPIO_FN_DV_D15, NULL);
1297 gpio_request(GPIO_FN_DV_D14, NULL); 1295 gpio_request(GPIO_FN_DV_D14, NULL);
1298 gpio_request(GPIO_FN_DV_D13, NULL); 1296 gpio_request(GPIO_FN_DV_D13, NULL);
1299 gpio_request(GPIO_FN_DV_D12, NULL); 1297 gpio_request(GPIO_FN_DV_D12, NULL);
1300 gpio_request(GPIO_FN_DV_D11, NULL); 1298 gpio_request(GPIO_FN_DV_D11, NULL);
1301 gpio_request(GPIO_FN_DV_D10, NULL); 1299 gpio_request(GPIO_FN_DV_D10, NULL);
1302 gpio_request(GPIO_FN_DV_D9, NULL); 1300 gpio_request(GPIO_FN_DV_D9, NULL);
1303 gpio_request(GPIO_FN_DV_D8, NULL); 1301 gpio_request(GPIO_FN_DV_D8, NULL);
1304 gpio_request(GPIO_FN_DV_CLKI, NULL); 1302 gpio_request(GPIO_FN_DV_CLKI, NULL);
1305 gpio_request(GPIO_FN_DV_CLK, NULL); 1303 gpio_request(GPIO_FN_DV_CLK, NULL);
1306 gpio_request(GPIO_FN_DV_VSYNC, NULL); 1304 gpio_request(GPIO_FN_DV_VSYNC, NULL);
1307 gpio_request(GPIO_FN_DV_HSYNC, NULL); 1305 gpio_request(GPIO_FN_DV_HSYNC, NULL);
1308 1306
1309 /* AK8813 power / reset sequence */ 1307 /* AK8813 power / reset sequence */
1310 gpio_request(GPIO_PTG4, NULL); 1308 gpio_request(GPIO_PTG4, NULL);
1311 gpio_request(GPIO_PTU3, NULL); 1309 gpio_request(GPIO_PTU3, NULL);
1312 /* Reset */ 1310 /* Reset */
1313 gpio_direction_output(GPIO_PTG4, 0); 1311 gpio_direction_output(GPIO_PTG4, 0);
1314 /* Power down */ 1312 /* Power down */
1315 gpio_direction_output(GPIO_PTU3, 1); 1313 gpio_direction_output(GPIO_PTU3, 1);
1316 1314
1317 udelay(10); 1315 udelay(10);
1318 1316
1319 /* Power up, reset */ 1317 /* Power up, reset */
1320 gpio_set_value(GPIO_PTU3, 0); 1318 gpio_set_value(GPIO_PTU3, 0);
1321 1319
1322 udelay(10); 1320 udelay(10);
1323 1321
1324 /* Remove reset */ 1322 /* Remove reset */
1325 gpio_set_value(GPIO_PTG4, 1); 1323 gpio_set_value(GPIO_PTG4, 1);
1326 1324
1327 return platform_add_devices(ecovec_devices, 1325 return platform_add_devices(ecovec_devices,
1328 ARRAY_SIZE(ecovec_devices)); 1326 ARRAY_SIZE(ecovec_devices));
1329 } 1327 }
1330 arch_initcall(arch_setup); 1328 arch_initcall(arch_setup);
1331 1329
1332 static int __init devices_setup(void) 1330 static int __init devices_setup(void)
1333 { 1331 {
1334 sh_eth_init(&sh_eth_plat); 1332 sh_eth_init(&sh_eth_plat);
1335 return 0; 1333 return 0;
1336 } 1334 }
1337 device_initcall(devices_setup); 1335 device_initcall(devices_setup);
1338 1336
1339 static struct sh_machine_vector mv_ecovec __initmv = { 1337 static struct sh_machine_vector mv_ecovec __initmv = {
1340 .mv_name = "R0P7724 (EcoVec)", 1338 .mv_name = "R0P7724 (EcoVec)",
1341 }; 1339 };
1342 1340
arch/sh/boards/mach-se/7724/setup.c
Diff comments   View file @ f17c13c
1 /* 1 /*
2 * linux/arch/sh/boards/se/7724/setup.c 2 * linux/arch/sh/boards/se/7724/setup.c
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * 5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details. 10 * for more details.
11 */ 11 */
12 12
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/device.h> 14 #include <linux/device.h>
15 #include <linux/interrupt.h> 15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include <linux/mfd/sh_mobile_sdhi.h> 17 #include <linux/mfd/sh_mobile_sdhi.h>
18 #include <linux/mmc/host.h> 18 #include <linux/mmc/host.h>
19 #include <linux/mtd/physmap.h> 19 #include <linux/mtd/physmap.h>
20 #include <linux/delay.h> 20 #include <linux/delay.h>
21 #include <linux/smc91x.h> 21 #include <linux/smc91x.h>
22 #include <linux/gpio.h> 22 #include <linux/gpio.h>
23 #include <linux/input.h> 23 #include <linux/input.h>
24 #include <linux/input/sh_keysc.h> 24 #include <linux/input/sh_keysc.h>
25 #include <linux/usb/r8a66597.h> 25 #include <linux/usb/r8a66597.h>
26 #include <video/sh_mobile_lcdc.h> 26 #include <video/sh_mobile_lcdc.h>
27 #include <media/sh_mobile_ceu.h> 27 #include <media/sh_mobile_ceu.h>
28 #include <sound/sh_fsi.h> 28 #include <sound/sh_fsi.h>
29 #include <asm/io.h> 29 #include <asm/io.h>
30 #include <asm/heartbeat.h> 30 #include <asm/heartbeat.h>
31 #include <asm/sh_eth.h> 31 #include <asm/sh_eth.h>
32 #include <asm/clock.h> 32 #include <asm/clock.h>
33 #include <asm/suspend.h> 33 #include <asm/suspend.h>
34 #include <cpu/sh7724.h> 34 #include <cpu/sh7724.h>
35 #include <mach-se/mach/se7724.h> 35 #include <mach-se/mach/se7724.h>
36 36
37 /* 37 /*
38 * SWx 1234 5678 38 * SWx 1234 5678
39 * ------------------------------------ 39 * ------------------------------------
40 * SW31 : 1001 1100 : default 40 * SW31 : 1001 1100 : default
41 * SW32 : 0111 1111 : use on board flash 41 * SW32 : 0111 1111 : use on board flash
42 * 42 *
43 * SW41 : abxx xxxx -> a = 0 : Analog monitor 43 * SW41 : abxx xxxx -> a = 0 : Analog monitor
44 * 1 : Digital monitor 44 * 1 : Digital monitor
45 * b = 0 : VGA 45 * b = 0 : VGA
46 * 1 : 720p 46 * 1 : 720p
47 */ 47 */
48 48
49 /* 49 /*
50 * about 720p 50 * about 720p
51 * 51 *
52 * When you use 1280 x 720 lcdc output, 52 * When you use 1280 x 720 lcdc output,
53 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz, 53 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
54 * and change SW41 to use 720p 54 * and change SW41 to use 720p
55 */ 55 */
56 56
57 /* 57 /*
58 * about sound 58 * about sound
59 * 59 *
60 * This setup.c supports FSI slave mode. 60 * This setup.c supports FSI slave mode.
61 * Please change J20, J21, J22 pin to 1-2 connection. 61 * Please change J20, J21, J22 pin to 1-2 connection.
62 */ 62 */
63 63
64 /* Heartbeat */ 64 /* Heartbeat */
65 static struct resource heartbeat_resource = { 65 static struct resource heartbeat_resource = {
66 .start = PA_LED, 66 .start = PA_LED,
67 .end = PA_LED, 67 .end = PA_LED,
68 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, 68 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
69 }; 69 };
70 70
71 static struct platform_device heartbeat_device = { 71 static struct platform_device heartbeat_device = {
72 .name = "heartbeat", 72 .name = "heartbeat",
73 .id = -1, 73 .id = -1,
74 .num_resources = 1, 74 .num_resources = 1,
75 .resource = &heartbeat_resource, 75 .resource = &heartbeat_resource,
76 }; 76 };
77 77
78 /* LAN91C111 */ 78 /* LAN91C111 */
79 static struct smc91x_platdata smc91x_info = { 79 static struct smc91x_platdata smc91x_info = {
80 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, 80 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
81 }; 81 };
82 82
83 static struct resource smc91x_eth_resources[] = { 83 static struct resource smc91x_eth_resources[] = {
84 [0] = { 84 [0] = {
85 .name = "SMC91C111" , 85 .name = "SMC91C111" ,
86 .start = 0x1a300300, 86 .start = 0x1a300300,
87 .end = 0x1a30030f, 87 .end = 0x1a30030f,
88 .flags = IORESOURCE_MEM, 88 .flags = IORESOURCE_MEM,
89 }, 89 },
90 [1] = { 90 [1] = {
91 .start = IRQ0_SMC, 91 .start = IRQ0_SMC,
92 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 92 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
93 }, 93 },
94 }; 94 };
95 95
96 static struct platform_device smc91x_eth_device = { 96 static struct platform_device smc91x_eth_device = {
97 .name = "smc91x", 97 .name = "smc91x",
98 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 98 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
99 .resource = smc91x_eth_resources, 99 .resource = smc91x_eth_resources,
100 .dev = { 100 .dev = {
101 .platform_data = &smc91x_info, 101 .platform_data = &smc91x_info,
102 }, 102 },
103 }; 103 };
104 104
105 /* MTD */ 105 /* MTD */
106 static struct mtd_partition nor_flash_partitions[] = { 106 static struct mtd_partition nor_flash_partitions[] = {
107 { 107 {
108 .name = "uboot", 108 .name = "uboot",
109 .offset = 0, 109 .offset = 0,
110 .size = (1 * 1024 * 1024), 110 .size = (1 * 1024 * 1024),
111 .mask_flags = MTD_WRITEABLE, /* Read-only */ 111 .mask_flags = MTD_WRITEABLE, /* Read-only */
112 }, { 112 }, {
113 .name = "kernel", 113 .name = "kernel",
114 .offset = MTDPART_OFS_APPEND, 114 .offset = MTDPART_OFS_APPEND,
115 .size = (2 * 1024 * 1024), 115 .size = (2 * 1024 * 1024),
116 }, { 116 }, {
117 .name = "free-area", 117 .name = "free-area",
118 .offset = MTDPART_OFS_APPEND, 118 .offset = MTDPART_OFS_APPEND,
119 .size = MTDPART_SIZ_FULL, 119 .size = MTDPART_SIZ_FULL,
120 }, 120 },
121 }; 121 };
122 122
123 static struct physmap_flash_data nor_flash_data = { 123 static struct physmap_flash_data nor_flash_data = {
124 .width = 2, 124 .width = 2,
125 .parts = nor_flash_partitions, 125 .parts = nor_flash_partitions,
126 .nr_parts = ARRAY_SIZE(nor_flash_partitions), 126 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
127 }; 127 };
128 128
129 static struct resource nor_flash_resources[] = { 129 static struct resource nor_flash_resources[] = {
130 [0] = { 130 [0] = {
131 .name = "NOR Flash", 131 .name = "NOR Flash",
132 .start = 0x00000000, 132 .start = 0x00000000,
133 .end = 0x01ffffff, 133 .end = 0x01ffffff,
134 .flags = IORESOURCE_MEM, 134 .flags = IORESOURCE_MEM,
135 } 135 }
136 }; 136 };
137 137
138 static struct platform_device nor_flash_device = { 138 static struct platform_device nor_flash_device = {
139 .name = "physmap-flash", 139 .name = "physmap-flash",
140 .resource = nor_flash_resources, 140 .resource = nor_flash_resources,
141 .num_resources = ARRAY_SIZE(nor_flash_resources), 141 .num_resources = ARRAY_SIZE(nor_flash_resources),
142 .dev = { 142 .dev = {
143 .platform_data = &nor_flash_data, 143 .platform_data = &nor_flash_data,
144 }, 144 },
145 }; 145 };
146 146
147 /* LCDC */ 147 /* LCDC */
148 const static struct fb_videomode lcdc_720p_modes[] = { 148 const static struct fb_videomode lcdc_720p_modes[] = {
149 { 149 {
150 .name = "LB070WV1", 150 .name = "LB070WV1",
151 .sync = 0, /* hsync and vsync are active low */ 151 .sync = 0, /* hsync and vsync are active low */
152 .xres = 1280, 152 .xres = 1280,
153 .yres = 720, 153 .yres = 720,
154 .left_margin = 220, 154 .left_margin = 220,
155 .right_margin = 110, 155 .right_margin = 110,
156 .hsync_len = 40, 156 .hsync_len = 40,
157 .upper_margin = 20, 157 .upper_margin = 20,
158 .lower_margin = 5, 158 .lower_margin = 5,
159 .vsync_len = 5, 159 .vsync_len = 5,
160 }, 160 },
161 }; 161 };
162 162
163 const static struct fb_videomode lcdc_vga_modes[] = { 163 const static struct fb_videomode lcdc_vga_modes[] = {
164 { 164 {
165 .name = "LB070WV1", 165 .name = "LB070WV1",
166 .sync = 0, /* hsync and vsync are active low */ 166 .sync = 0, /* hsync and vsync are active low */
167 .xres = 640, 167 .xres = 640,
168 .yres = 480, 168 .yres = 480,
169 .left_margin = 105, 169 .left_margin = 105,
170 .right_margin = 50, 170 .right_margin = 50,
171 .hsync_len = 96, 171 .hsync_len = 96,
172 .upper_margin = 33, 172 .upper_margin = 33,
173 .lower_margin = 10, 173 .lower_margin = 10,
174 .vsync_len = 2, 174 .vsync_len = 2,
175 }, 175 },
176 }; 176 };
177 177
178 static struct sh_mobile_lcdc_info lcdc_info = { 178 static struct sh_mobile_lcdc_info lcdc_info = {
179 .clock_source = LCDC_CLK_EXTERNAL, 179 .clock_source = LCDC_CLK_EXTERNAL,
180 .ch[0] = { 180 .ch[0] = {
181 .chan = LCDC_CHAN_MAINLCD, 181 .chan = LCDC_CHAN_MAINLCD,
182 .bpp = 16, 182 .bpp = 16,
183 .clock_divider = 1, 183 .clock_divider = 1,
184 .lcd_size_cfg = { /* 7.0 inch */ 184 .lcd_size_cfg = { /* 7.0 inch */
185 .width = 152, 185 .width = 152,
186 .height = 91, 186 .height = 91,
187 }, 187 },
188 .board_cfg = { 188 .board_cfg = {
189 }, 189 },
190 } 190 }
191 }; 191 };
192 192
193 static struct resource lcdc_resources[] = { 193 static struct resource lcdc_resources[] = {
194 [0] = { 194 [0] = {
195 .name = "LCDC", 195 .name = "LCDC",
196 .start = 0xfe940000, 196 .start = 0xfe940000,
197 .end = 0xfe942fff, 197 .end = 0xfe942fff,
198 .flags = IORESOURCE_MEM, 198 .flags = IORESOURCE_MEM,
199 }, 199 },
200 [1] = { 200 [1] = {
201 .start = 106, 201 .start = 106,
202 .flags = IORESOURCE_IRQ, 202 .flags = IORESOURCE_IRQ,
203 }, 203 },
204 }; 204 };
205 205
206 static struct platform_device lcdc_device = { 206 static struct platform_device lcdc_device = {
207 .name = "sh_mobile_lcdc_fb", 207 .name = "sh_mobile_lcdc_fb",
208 .num_resources = ARRAY_SIZE(lcdc_resources), 208 .num_resources = ARRAY_SIZE(lcdc_resources),
209 .resource = lcdc_resources, 209 .resource = lcdc_resources,
210 .dev = { 210 .dev = {
211 .platform_data = &lcdc_info, 211 .platform_data = &lcdc_info,
212 }, 212 },
213 .archdata = { 213 .archdata = {
214 .hwblk_id = HWBLK_LCDC, 214 .hwblk_id = HWBLK_LCDC,
215 }, 215 },
216 }; 216 };
217 217
218 /* CEU0 */ 218 /* CEU0 */
219 static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { 219 static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
220 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 220 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
221 }; 221 };
222 222
223 static struct resource ceu0_resources[] = { 223 static struct resource ceu0_resources[] = {
224 [0] = { 224 [0] = {
225 .name = "CEU0", 225 .name = "CEU0",
226 .start = 0xfe910000, 226 .start = 0xfe910000,
227 .end = 0xfe91009f, 227 .end = 0xfe91009f,
228 .flags = IORESOURCE_MEM, 228 .flags = IORESOURCE_MEM,
229 }, 229 },
230 [1] = { 230 [1] = {
231 .start = 52, 231 .start = 52,
232 .flags = IORESOURCE_IRQ, 232 .flags = IORESOURCE_IRQ,
233 }, 233 },
234 [2] = { 234 [2] = {
235 /* place holder for contiguous memory */ 235 /* place holder for contiguous memory */
236 }, 236 },
237 }; 237 };
238 238
239 static struct platform_device ceu0_device = { 239 static struct platform_device ceu0_device = {
240 .name = "sh_mobile_ceu", 240 .name = "sh_mobile_ceu",
241 .id = 0, /* "ceu0" clock */ 241 .id = 0, /* "ceu0" clock */
242 .num_resources = ARRAY_SIZE(ceu0_resources), 242 .num_resources = ARRAY_SIZE(ceu0_resources),
243 .resource = ceu0_resources, 243 .resource = ceu0_resources,
244 .dev = { 244 .dev = {
245 .platform_data = &sh_mobile_ceu0_info, 245 .platform_data = &sh_mobile_ceu0_info,
246 }, 246 },
247 .archdata = { 247 .archdata = {
248 .hwblk_id = HWBLK_CEU0, 248 .hwblk_id = HWBLK_CEU0,
249 }, 249 },
250 }; 250 };
251 251
252 /* CEU1 */ 252 /* CEU1 */
253 static struct sh_mobile_ceu_info sh_mobile_ceu1_info = { 253 static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
254 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 254 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
255 }; 255 };
256 256
257 static struct resource ceu1_resources[] = { 257 static struct resource ceu1_resources[] = {
258 [0] = { 258 [0] = {
259 .name = "CEU1", 259 .name = "CEU1",
260 .start = 0xfe914000, 260 .start = 0xfe914000,
261 .end = 0xfe91409f, 261 .end = 0xfe91409f,
262 .flags = IORESOURCE_MEM, 262 .flags = IORESOURCE_MEM,
263 }, 263 },
264 [1] = { 264 [1] = {
265 .start = 63, 265 .start = 63,
266 .flags = IORESOURCE_IRQ, 266 .flags = IORESOURCE_IRQ,
267 }, 267 },
268 [2] = { 268 [2] = {
269 /* place holder for contiguous memory */ 269 /* place holder for contiguous memory */
270 }, 270 },
271 }; 271 };
272 272
273 static struct platform_device ceu1_device = { 273 static struct platform_device ceu1_device = {
274 .name = "sh_mobile_ceu", 274 .name = "sh_mobile_ceu",
275 .id = 1, /* "ceu1" clock */ 275 .id = 1, /* "ceu1" clock */
276 .num_resources = ARRAY_SIZE(ceu1_resources), 276 .num_resources = ARRAY_SIZE(ceu1_resources),
277 .resource = ceu1_resources, 277 .resource = ceu1_resources,
278 .dev = { 278 .dev = {
279 .platform_data = &sh_mobile_ceu1_info, 279 .platform_data = &sh_mobile_ceu1_info,
280 }, 280 },
281 .archdata = { 281 .archdata = {
282 .hwblk_id = HWBLK_CEU1, 282 .hwblk_id = HWBLK_CEU1,
283 }, 283 },
284 }; 284 };
285 285
286 /* FSI */ 286 /* FSI */
287 /* change J20, J21, J22 pin to 1-2 connection to use slave mode */ 287 /* change J20, J21, J22 pin to 1-2 connection to use slave mode */
288 static struct sh_fsi_platform_info fsi_info = { 288 static struct sh_fsi_platform_info fsi_info = {
289 .porta_flags = SH_FSI_BRS_INV | 289 .porta_flags = SH_FSI_BRS_INV,
290 SH_FSI_OFMT(PCM) |
291 SH_FSI_IFMT(PCM),
292 }; 290 };
293 291
294 static struct resource fsi_resources[] = { 292 static struct resource fsi_resources[] = {
295 [0] = { 293 [0] = {
296 .name = "FSI", 294 .name = "FSI",
297 .start = 0xFE3C0000, 295 .start = 0xFE3C0000,
298 .end = 0xFE3C021d, 296 .end = 0xFE3C021d,
299 .flags = IORESOURCE_MEM, 297 .flags = IORESOURCE_MEM,
300 }, 298 },
301 [1] = { 299 [1] = {
302 .start = 108, 300 .start = 108,
303 .flags = IORESOURCE_IRQ, 301 .flags = IORESOURCE_IRQ,
304 }, 302 },
305 }; 303 };
306 304
307 static struct platform_device fsi_device = { 305 static struct platform_device fsi_device = {
308 .name = "sh_fsi", 306 .name = "sh_fsi",
309 .id = 0, 307 .id = 0,
310 .num_resources = ARRAY_SIZE(fsi_resources), 308 .num_resources = ARRAY_SIZE(fsi_resources),
311 .resource = fsi_resources, 309 .resource = fsi_resources,
312 .dev = { 310 .dev = {
313 .platform_data = &fsi_info, 311 .platform_data = &fsi_info,
314 }, 312 },
315 .archdata = { 313 .archdata = {
316 .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */ 314 .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */
317 }, 315 },
318 }; 316 };
319 317
320 static struct platform_device fsi_ak4642_device = { 318 static struct platform_device fsi_ak4642_device = {
321 .name = "sh_fsi_a_ak4642", 319 .name = "sh_fsi_a_ak4642",
322 }; 320 };
323 321
324 /* KEYSC in SoC (Needs SW33-2 set to ON) */ 322 /* KEYSC in SoC (Needs SW33-2 set to ON) */
325 static struct sh_keysc_info keysc_info = { 323 static struct sh_keysc_info keysc_info = {
326 .mode = SH_KEYSC_MODE_1, 324 .mode = SH_KEYSC_MODE_1,
327 .scan_timing = 3, 325 .scan_timing = 3,
328 .delay = 50, 326 .delay = 50,
329 .keycodes = { 327 .keycodes = {
330 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5, 328 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
331 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A, 329 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
332 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, 330 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
333 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L, 331 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
334 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q, 332 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
335 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V, 333 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
336 }, 334 },
337 }; 335 };
338 336
339 static struct resource keysc_resources[] = { 337 static struct resource keysc_resources[] = {
340 [0] = { 338 [0] = {
341 .name = "KEYSC", 339 .name = "KEYSC",
342 .start = 0x044b0000, 340 .start = 0x044b0000,
343 .end = 0x044b000f, 341 .end = 0x044b000f,
344 .flags = IORESOURCE_MEM, 342 .flags = IORESOURCE_MEM,
345 }, 343 },
346 [1] = { 344 [1] = {
347 .start = 79, 345 .start = 79,
348 .flags = IORESOURCE_IRQ, 346 .flags = IORESOURCE_IRQ,
349 }, 347 },
350 }; 348 };
351 349
352 static struct platform_device keysc_device = { 350 static struct platform_device keysc_device = {
353 .name = "sh_keysc", 351 .name = "sh_keysc",
354 .id = 0, /* "keysc0" clock */ 352 .id = 0, /* "keysc0" clock */
355 .num_resources = ARRAY_SIZE(keysc_resources), 353 .num_resources = ARRAY_SIZE(keysc_resources),
356 .resource = keysc_resources, 354 .resource = keysc_resources,
357 .dev = { 355 .dev = {
358 .platform_data = &keysc_info, 356 .platform_data = &keysc_info,
359 }, 357 },
360 .archdata = { 358 .archdata = {
361 .hwblk_id = HWBLK_KEYSC, 359 .hwblk_id = HWBLK_KEYSC,
362 }, 360 },
363 }; 361 };
364 362
365 /* SH Eth */ 363 /* SH Eth */
366 static struct resource sh_eth_resources[] = { 364 static struct resource sh_eth_resources[] = {
367 [0] = { 365 [0] = {
368 .start = SH_ETH_ADDR, 366 .start = SH_ETH_ADDR,
369 .end = SH_ETH_ADDR + 0x1FC, 367 .end = SH_ETH_ADDR + 0x1FC,
370 .flags = IORESOURCE_MEM, 368 .flags = IORESOURCE_MEM,
371 }, 369 },
372 [1] = { 370 [1] = {
373 .start = 91, 371 .start = 91,
374 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 372 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
375 }, 373 },
376 }; 374 };
377 375
378 static struct sh_eth_plat_data sh_eth_plat = { 376 static struct sh_eth_plat_data sh_eth_plat = {
379 .phy = 0x1f, /* SMSC LAN8187 */ 377 .phy = 0x1f, /* SMSC LAN8187 */
380 .edmac_endian = EDMAC_LITTLE_ENDIAN, 378 .edmac_endian = EDMAC_LITTLE_ENDIAN,
381 }; 379 };
382 380
383 static struct platform_device sh_eth_device = { 381 static struct platform_device sh_eth_device = {
384 .name = "sh-eth", 382 .name = "sh-eth",
385 .id = 0, 383 .id = 0,
386 .dev = { 384 .dev = {
387 .platform_data = &sh_eth_plat, 385 .platform_data = &sh_eth_plat,
388 }, 386 },
389 .num_resources = ARRAY_SIZE(sh_eth_resources), 387 .num_resources = ARRAY_SIZE(sh_eth_resources),
390 .resource = sh_eth_resources, 388 .resource = sh_eth_resources,
391 .archdata = { 389 .archdata = {
392 .hwblk_id = HWBLK_ETHER, 390 .hwblk_id = HWBLK_ETHER,
393 }, 391 },
394 }; 392 };
395 393
396 static struct r8a66597_platdata sh7724_usb0_host_data = { 394 static struct r8a66597_platdata sh7724_usb0_host_data = {
397 .on_chip = 1, 395 .on_chip = 1,
398 }; 396 };
399 397
400 static struct resource sh7724_usb0_host_resources[] = { 398 static struct resource sh7724_usb0_host_resources[] = {
401 [0] = { 399 [0] = {
402 .start = 0xa4d80000, 400 .start = 0xa4d80000,
403 .end = 0xa4d80124 - 1, 401 .end = 0xa4d80124 - 1,
404 .flags = IORESOURCE_MEM, 402 .flags = IORESOURCE_MEM,
405 }, 403 },
406 [1] = { 404 [1] = {
407 .start = 65, 405 .start = 65,
408 .end = 65, 406 .end = 65,
409 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 407 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
410 }, 408 },
411 }; 409 };
412 410
413 static struct platform_device sh7724_usb0_host_device = { 411 static struct platform_device sh7724_usb0_host_device = {
414 .name = "r8a66597_hcd", 412 .name = "r8a66597_hcd",
415 .id = 0, 413 .id = 0,
416 .dev = { 414 .dev = {
417 .dma_mask = NULL, /* not use dma */ 415 .dma_mask = NULL, /* not use dma */
418 .coherent_dma_mask = 0xffffffff, 416 .coherent_dma_mask = 0xffffffff,
419 .platform_data = &sh7724_usb0_host_data, 417 .platform_data = &sh7724_usb0_host_data,
420 }, 418 },
421 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources), 419 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
422 .resource = sh7724_usb0_host_resources, 420 .resource = sh7724_usb0_host_resources,
423 .archdata = { 421 .archdata = {
424 .hwblk_id = HWBLK_USB0, 422 .hwblk_id = HWBLK_USB0,
425 }, 423 },
426 }; 424 };
427 425
428 static struct r8a66597_platdata sh7724_usb1_gadget_data = { 426 static struct r8a66597_platdata sh7724_usb1_gadget_data = {
429 .on_chip = 1, 427 .on_chip = 1,
430 }; 428 };
431 429
432 static struct resource sh7724_usb1_gadget_resources[] = { 430 static struct resource sh7724_usb1_gadget_resources[] = {
433 [0] = { 431 [0] = {
434 .start = 0xa4d90000, 432 .start = 0xa4d90000,
435 .end = 0xa4d90123, 433 .end = 0xa4d90123,
436 .flags = IORESOURCE_MEM, 434 .flags = IORESOURCE_MEM,
437 }, 435 },
438 [1] = { 436 [1] = {
439 .start = 66, 437 .start = 66,
440 .end = 66, 438 .end = 66,
441 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 439 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
442 }, 440 },
443 }; 441 };
444 442
445 static struct platform_device sh7724_usb1_gadget_device = { 443 static struct platform_device sh7724_usb1_gadget_device = {
446 .name = "r8a66597_udc", 444 .name = "r8a66597_udc",
447 .id = 1, /* USB1 */ 445 .id = 1, /* USB1 */
448 .dev = { 446 .dev = {
449 .dma_mask = NULL, /* not use dma */ 447 .dma_mask = NULL, /* not use dma */
450 .coherent_dma_mask = 0xffffffff, 448 .coherent_dma_mask = 0xffffffff,
451 .platform_data = &sh7724_usb1_gadget_data, 449 .platform_data = &sh7724_usb1_gadget_data,
452 }, 450 },
453 .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources), 451 .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources),
454 .resource = sh7724_usb1_gadget_resources, 452 .resource = sh7724_usb1_gadget_resources,
455 }; 453 };
456 454
457 static struct resource sdhi0_cn7_resources[] = { 455 static struct resource sdhi0_cn7_resources[] = {
458 [0] = { 456 [0] = {
459 .name = "SDHI0", 457 .name = "SDHI0",
460 .start = 0x04ce0000, 458 .start = 0x04ce0000,
461 .end = 0x04ce01ff, 459 .end = 0x04ce01ff,
462 .flags = IORESOURCE_MEM, 460 .flags = IORESOURCE_MEM,
463 }, 461 },
464 [1] = { 462 [1] = {
465 .start = 100, 463 .start = 100,
466 .flags = IORESOURCE_IRQ, 464 .flags = IORESOURCE_IRQ,
467 }, 465 },
468 }; 466 };
469 467
470 static struct sh_mobile_sdhi_info sh7724_sdhi0_data = { 468 static struct sh_mobile_sdhi_info sh7724_sdhi0_data = {
471 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 469 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
472 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 470 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
473 .tmio_caps = MMC_CAP_SDIO_IRQ, 471 .tmio_caps = MMC_CAP_SDIO_IRQ,
474 }; 472 };
475 473
476 static struct platform_device sdhi0_cn7_device = { 474 static struct platform_device sdhi0_cn7_device = {
477 .name = "sh_mobile_sdhi", 475 .name = "sh_mobile_sdhi",
478 .id = 0, 476 .id = 0,
479 .num_resources = ARRAY_SIZE(sdhi0_cn7_resources), 477 .num_resources = ARRAY_SIZE(sdhi0_cn7_resources),
480 .resource = sdhi0_cn7_resources, 478 .resource = sdhi0_cn7_resources,
481 .dev = { 479 .dev = {
482 .platform_data = &sh7724_sdhi0_data, 480 .platform_data = &sh7724_sdhi0_data,
483 }, 481 },
484 .archdata = { 482 .archdata = {
485 .hwblk_id = HWBLK_SDHI0, 483 .hwblk_id = HWBLK_SDHI0,
486 }, 484 },
487 }; 485 };
488 486
489 static struct resource sdhi1_cn8_resources[] = { 487 static struct resource sdhi1_cn8_resources[] = {
490 [0] = { 488 [0] = {
491 .name = "SDHI1", 489 .name = "SDHI1",
492 .start = 0x04cf0000, 490 .start = 0x04cf0000,
493 .end = 0x04cf01ff, 491 .end = 0x04cf01ff,
494 .flags = IORESOURCE_MEM, 492 .flags = IORESOURCE_MEM,
495 }, 493 },
496 [1] = { 494 [1] = {
497 .start = 23, 495 .start = 23,
498 .flags = IORESOURCE_IRQ, 496 .flags = IORESOURCE_IRQ,
499 }, 497 },
500 }; 498 };
501 499
502 static struct sh_mobile_sdhi_info sh7724_sdhi1_data = { 500 static struct sh_mobile_sdhi_info sh7724_sdhi1_data = {
503 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, 501 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
504 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, 502 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
505 .tmio_caps = MMC_CAP_SDIO_IRQ, 503 .tmio_caps = MMC_CAP_SDIO_IRQ,
506 }; 504 };
507 505
508 static struct platform_device sdhi1_cn8_device = { 506 static struct platform_device sdhi1_cn8_device = {
509 .name = "sh_mobile_sdhi", 507 .name = "sh_mobile_sdhi",
510 .id = 1, 508 .id = 1,
511 .num_resources = ARRAY_SIZE(sdhi1_cn8_resources), 509 .num_resources = ARRAY_SIZE(sdhi1_cn8_resources),
512 .resource = sdhi1_cn8_resources, 510 .resource = sdhi1_cn8_resources,
513 .dev = { 511 .dev = {
514 .platform_data = &sh7724_sdhi1_data, 512 .platform_data = &sh7724_sdhi1_data,
515 }, 513 },
516 .archdata = { 514 .archdata = {
517 .hwblk_id = HWBLK_SDHI1, 515 .hwblk_id = HWBLK_SDHI1,
518 }, 516 },
519 }; 517 };
520 518
521 /* IrDA */ 519 /* IrDA */
522 static struct resource irda_resources[] = { 520 static struct resource irda_resources[] = {
523 [0] = { 521 [0] = {
524 .name = "IrDA", 522 .name = "IrDA",
525 .start = 0xA45D0000, 523 .start = 0xA45D0000,
526 .end = 0xA45D0049, 524 .end = 0xA45D0049,
527 .flags = IORESOURCE_MEM, 525 .flags = IORESOURCE_MEM,
528 }, 526 },
529 [1] = { 527 [1] = {
530 .start = 20, 528 .start = 20,
531 .flags = IORESOURCE_IRQ, 529 .flags = IORESOURCE_IRQ,
532 }, 530 },
533 }; 531 };
534 532
535 static struct platform_device irda_device = { 533 static struct platform_device irda_device = {
536 .name = "sh_sir", 534 .name = "sh_sir",
537 .num_resources = ARRAY_SIZE(irda_resources), 535 .num_resources = ARRAY_SIZE(irda_resources),
538 .resource = irda_resources, 536 .resource = irda_resources,
539 }; 537 };
540 538
541 #include <media/ak881x.h> 539 #include <media/ak881x.h>
542 #include <media/sh_vou.h> 540 #include <media/sh_vou.h>
543 541
544 static struct ak881x_pdata ak881x_pdata = { 542 static struct ak881x_pdata ak881x_pdata = {
545 .flags = AK881X_IF_MODE_SLAVE, 543 .flags = AK881X_IF_MODE_SLAVE,
546 }; 544 };
547 545
548 static struct i2c_board_info ak8813 = { 546 static struct i2c_board_info ak8813 = {
549 /* With open J18 jumper address is 0x21 */ 547 /* With open J18 jumper address is 0x21 */
550 I2C_BOARD_INFO("ak8813", 0x20), 548 I2C_BOARD_INFO("ak8813", 0x20),
551 .platform_data = &ak881x_pdata, 549 .platform_data = &ak881x_pdata,
552 }; 550 };
553 551
554 static struct sh_vou_pdata sh_vou_pdata = { 552 static struct sh_vou_pdata sh_vou_pdata = {
555 .bus_fmt = SH_VOU_BUS_8BIT, 553 .bus_fmt = SH_VOU_BUS_8BIT,
556 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW, 554 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
557 .board_info = &ak8813, 555 .board_info = &ak8813,
558 .i2c_adap = 0, 556 .i2c_adap = 0,
559 }; 557 };
560 558
561 static struct resource sh_vou_resources[] = { 559 static struct resource sh_vou_resources[] = {
562 [0] = { 560 [0] = {
563 .start = 0xfe960000, 561 .start = 0xfe960000,
564 .end = 0xfe962043, 562 .end = 0xfe962043,
565 .flags = IORESOURCE_MEM, 563 .flags = IORESOURCE_MEM,
566 }, 564 },
567 [1] = { 565 [1] = {
568 .start = 55, 566 .start = 55,
569 .flags = IORESOURCE_IRQ, 567 .flags = IORESOURCE_IRQ,
570 }, 568 },
571 }; 569 };
572 570
573 static struct platform_device vou_device = { 571 static struct platform_device vou_device = {
574 .name = "sh-vou", 572 .name = "sh-vou",
575 .id = -1, 573 .id = -1,
576 .num_resources = ARRAY_SIZE(sh_vou_resources), 574 .num_resources = ARRAY_SIZE(sh_vou_resources),
577 .resource = sh_vou_resources, 575 .resource = sh_vou_resources,
578 .dev = { 576 .dev = {
579 .platform_data = &sh_vou_pdata, 577 .platform_data = &sh_vou_pdata,
580 }, 578 },
581 .archdata = { 579 .archdata = {
582 .hwblk_id = HWBLK_VOU, 580 .hwblk_id = HWBLK_VOU,
583 }, 581 },
584 }; 582 };
585 583
586 static struct platform_device *ms7724se_devices[] __initdata = { 584 static struct platform_device *ms7724se_devices[] __initdata = {
587 &heartbeat_device, 585 &heartbeat_device,
588 &smc91x_eth_device, 586 &smc91x_eth_device,
589 &lcdc_device, 587 &lcdc_device,
590 &nor_flash_device, 588 &nor_flash_device,
591 &ceu0_device, 589 &ceu0_device,
592 &ceu1_device, 590 &ceu1_device,
593 &keysc_device, 591 &keysc_device,
594 &sh_eth_device, 592 &sh_eth_device,
595 &sh7724_usb0_host_device, 593 &sh7724_usb0_host_device,
596 &sh7724_usb1_gadget_device, 594 &sh7724_usb1_gadget_device,
597 &fsi_device, 595 &fsi_device,
598 &fsi_ak4642_device, 596 &fsi_ak4642_device,
599 &sdhi0_cn7_device, 597 &sdhi0_cn7_device,
600 &sdhi1_cn8_device, 598 &sdhi1_cn8_device,
601 &irda_device, 599 &irda_device,
602 &vou_device, 600 &vou_device,
603 }; 601 };
604 602
605 /* I2C device */ 603 /* I2C device */
606 static struct i2c_board_info i2c0_devices[] = { 604 static struct i2c_board_info i2c0_devices[] = {
607 { 605 {
608 I2C_BOARD_INFO("ak4642", 0x12), 606 I2C_BOARD_INFO("ak4642", 0x12),
609 }, 607 },
610 }; 608 };
611 609
612 #define EEPROM_OP 0xBA206000 610 #define EEPROM_OP 0xBA206000
613 #define EEPROM_ADR 0xBA206004 611 #define EEPROM_ADR 0xBA206004
614 #define EEPROM_DATA 0xBA20600C 612 #define EEPROM_DATA 0xBA20600C
615 #define EEPROM_STAT 0xBA206010 613 #define EEPROM_STAT 0xBA206010
616 #define EEPROM_STRT 0xBA206014 614 #define EEPROM_STRT 0xBA206014
617 static int __init sh_eth_is_eeprom_ready(void) 615 static int __init sh_eth_is_eeprom_ready(void)
618 { 616 {
619 int t = 10000; 617 int t = 10000;
620 618
621 while (t--) { 619 while (t--) {
622 if (!__raw_readw(EEPROM_STAT)) 620 if (!__raw_readw(EEPROM_STAT))
623 return 1; 621 return 1;
624 udelay(1); 622 udelay(1);
625 } 623 }
626 624
627 printk(KERN_ERR "ms7724se can not access to eeprom\n"); 625 printk(KERN_ERR "ms7724se can not access to eeprom\n");
628 return 0; 626 return 0;
629 } 627 }
630 628
631 static void __init sh_eth_init(void) 629 static void __init sh_eth_init(void)
632 { 630 {
633 int i; 631 int i;
634 u16 mac; 632 u16 mac;
635 633
636 /* check EEPROM status */ 634 /* check EEPROM status */
637 if (!sh_eth_is_eeprom_ready()) 635 if (!sh_eth_is_eeprom_ready())
638 return; 636 return;
639 637
640 /* read MAC addr from EEPROM */ 638 /* read MAC addr from EEPROM */
641 for (i = 0 ; i < 3 ; i++) { 639 for (i = 0 ; i < 3 ; i++) {
642 __raw_writew(0x0, EEPROM_OP); /* read */ 640 __raw_writew(0x0, EEPROM_OP); /* read */
643 __raw_writew(i*2, EEPROM_ADR); 641 __raw_writew(i*2, EEPROM_ADR);
644 __raw_writew(0x1, EEPROM_STRT); 642 __raw_writew(0x1, EEPROM_STRT);
645 if (!sh_eth_is_eeprom_ready()) 643 if (!sh_eth_is_eeprom_ready())
646 return; 644 return;
647 645
648 mac = __raw_readw(EEPROM_DATA); 646 mac = __raw_readw(EEPROM_DATA);
649 sh_eth_plat.mac_addr[i << 1] = mac & 0xff; 647 sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
650 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8; 648 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
651 } 649 }
652 } 650 }
653 651
654 #define SW4140 0xBA201000 652 #define SW4140 0xBA201000
655 #define FPGA_OUT 0xBA200400 653 #define FPGA_OUT 0xBA200400
656 #define PORT_HIZA 0xA4050158 654 #define PORT_HIZA 0xA4050158
657 #define PORT_MSELCRB 0xA4050182 655 #define PORT_MSELCRB 0xA4050182
658 656
659 #define SW41_A 0x0100 657 #define SW41_A 0x0100
660 #define SW41_B 0x0200 658 #define SW41_B 0x0200
661 #define SW41_C 0x0400 659 #define SW41_C 0x0400
662 #define SW41_D 0x0800 660 #define SW41_D 0x0800
663 #define SW41_E 0x1000 661 #define SW41_E 0x1000
664 #define SW41_F 0x2000 662 #define SW41_F 0x2000
665 #define SW41_G 0x4000 663 #define SW41_G 0x4000
666 #define SW41_H 0x8000 664 #define SW41_H 0x8000
667 665
668 extern char ms7724se_sdram_enter_start; 666 extern char ms7724se_sdram_enter_start;
669 extern char ms7724se_sdram_enter_end; 667 extern char ms7724se_sdram_enter_end;
670 extern char ms7724se_sdram_leave_start; 668 extern char ms7724se_sdram_leave_start;
671 extern char ms7724se_sdram_leave_end; 669 extern char ms7724se_sdram_leave_end;
672 670
673 671
674 static int __init arch_setup(void) 672 static int __init arch_setup(void)
675 { 673 {
676 /* enable I2C device */ 674 /* enable I2C device */
677 i2c_register_board_info(0, i2c0_devices, 675 i2c_register_board_info(0, i2c0_devices,
678 ARRAY_SIZE(i2c0_devices)); 676 ARRAY_SIZE(i2c0_devices));
679 return 0; 677 return 0;
680 } 678 }
681 arch_initcall(arch_setup); 679 arch_initcall(arch_setup);
682 680
683 static int __init devices_setup(void) 681 static int __init devices_setup(void)
684 { 682 {
685 u16 sw = __raw_readw(SW4140); /* select camera, monitor */ 683 u16 sw = __raw_readw(SW4140); /* select camera, monitor */
686 struct clk *clk; 684 struct clk *clk;
687 u16 fpga_out; 685 u16 fpga_out;
688 686
689 /* register board specific self-refresh code */ 687 /* register board specific self-refresh code */
690 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | 688 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
691 SUSP_SH_RSTANDBY, 689 SUSP_SH_RSTANDBY,
692 &ms7724se_sdram_enter_start, 690 &ms7724se_sdram_enter_start,
693 &ms7724se_sdram_enter_end, 691 &ms7724se_sdram_enter_end,
694 &ms7724se_sdram_leave_start, 692 &ms7724se_sdram_leave_start,
695 &ms7724se_sdram_leave_end); 693 &ms7724se_sdram_leave_end);
696 /* Reset Release */ 694 /* Reset Release */
697 fpga_out = __raw_readw(FPGA_OUT); 695 fpga_out = __raw_readw(FPGA_OUT);
698 /* bit4: NTSC_PDN, bit5: NTSC_RESET */ 696 /* bit4: NTSC_PDN, bit5: NTSC_RESET */
699 fpga_out &= ~((1 << 1) | /* LAN */ 697 fpga_out &= ~((1 << 1) | /* LAN */
700 (1 << 4) | /* AK8813 PDN */ 698 (1 << 4) | /* AK8813 PDN */
701 (1 << 5) | /* AK8813 RESET */ 699 (1 << 5) | /* AK8813 RESET */
702 (1 << 6) | /* VIDEO DAC */ 700 (1 << 6) | /* VIDEO DAC */
703 (1 << 7) | /* AK4643 */ 701 (1 << 7) | /* AK4643 */
704 (1 << 8) | /* IrDA */ 702 (1 << 8) | /* IrDA */
705 (1 << 12) | /* USB0 */ 703 (1 << 12) | /* USB0 */
706 (1 << 14)); /* RMII */ 704 (1 << 14)); /* RMII */
707 __raw_writew(fpga_out | (1 << 4), FPGA_OUT); 705 __raw_writew(fpga_out | (1 << 4), FPGA_OUT);
708 706
709 udelay(10); 707 udelay(10);
710 708
711 /* AK8813 RESET */ 709 /* AK8813 RESET */
712 __raw_writew(fpga_out | (1 << 5), FPGA_OUT); 710 __raw_writew(fpga_out | (1 << 5), FPGA_OUT);
713 711
714 udelay(10); 712 udelay(10);
715 713
716 __raw_writew(fpga_out, FPGA_OUT); 714 __raw_writew(fpga_out, FPGA_OUT);
717 715
718 /* turn on USB clocks, use external clock */ 716 /* turn on USB clocks, use external clock */
719 __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); 717 __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
720 718
721 /* Let LED9 show STATUS2 */ 719 /* Let LED9 show STATUS2 */
722 gpio_request(GPIO_FN_STATUS2, NULL); 720 gpio_request(GPIO_FN_STATUS2, NULL);
723 721
724 /* Lit LED10 show STATUS0 */ 722 /* Lit LED10 show STATUS0 */
725 gpio_request(GPIO_FN_STATUS0, NULL); 723 gpio_request(GPIO_FN_STATUS0, NULL);
726 724
727 /* Lit LED11 show PDSTATUS */ 725 /* Lit LED11 show PDSTATUS */
728 gpio_request(GPIO_FN_PDSTATUS, NULL); 726 gpio_request(GPIO_FN_PDSTATUS, NULL);
729 727
730 /* enable USB0 port */ 728 /* enable USB0 port */
731 __raw_writew(0x0600, 0xa40501d4); 729 __raw_writew(0x0600, 0xa40501d4);
732 730
733 /* enable USB1 port */ 731 /* enable USB1 port */
734 __raw_writew(0x0600, 0xa4050192); 732 __raw_writew(0x0600, 0xa4050192);
735 733
736 /* enable IRQ 0,1,2 */ 734 /* enable IRQ 0,1,2 */
737 gpio_request(GPIO_FN_INTC_IRQ0, NULL); 735 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
738 gpio_request(GPIO_FN_INTC_IRQ1, NULL); 736 gpio_request(GPIO_FN_INTC_IRQ1, NULL);
739 gpio_request(GPIO_FN_INTC_IRQ2, NULL); 737 gpio_request(GPIO_FN_INTC_IRQ2, NULL);
740 738
741 /* enable SCIFA3 */ 739 /* enable SCIFA3 */
742 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL); 740 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
743 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL); 741 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
744 gpio_request(GPIO_FN_SCIF3_I_TXD, NULL); 742 gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
745 gpio_request(GPIO_FN_SCIF3_I_CTS, NULL); 743 gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
746 gpio_request(GPIO_FN_SCIF3_I_RTS, NULL); 744 gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
747 745
748 /* enable LCDC */ 746 /* enable LCDC */
749 gpio_request(GPIO_FN_LCDD23, NULL); 747 gpio_request(GPIO_FN_LCDD23, NULL);
750 gpio_request(GPIO_FN_LCDD22, NULL); 748 gpio_request(GPIO_FN_LCDD22, NULL);
751 gpio_request(GPIO_FN_LCDD21, NULL); 749 gpio_request(GPIO_FN_LCDD21, NULL);
752 gpio_request(GPIO_FN_LCDD20, NULL); 750 gpio_request(GPIO_FN_LCDD20, NULL);
753 gpio_request(GPIO_FN_LCDD19, NULL); 751 gpio_request(GPIO_FN_LCDD19, NULL);
754 gpio_request(GPIO_FN_LCDD18, NULL); 752 gpio_request(GPIO_FN_LCDD18, NULL);
755 gpio_request(GPIO_FN_LCDD17, NULL); 753 gpio_request(GPIO_FN_LCDD17, NULL);
756 gpio_request(GPIO_FN_LCDD16, NULL); 754 gpio_request(GPIO_FN_LCDD16, NULL);
757 gpio_request(GPIO_FN_LCDD15, NULL); 755 gpio_request(GPIO_FN_LCDD15, NULL);
758 gpio_request(GPIO_FN_LCDD14, NULL); 756 gpio_request(GPIO_FN_LCDD14, NULL);
759 gpio_request(GPIO_FN_LCDD13, NULL); 757 gpio_request(GPIO_FN_LCDD13, NULL);
760 gpio_request(GPIO_FN_LCDD12, NULL); 758 gpio_request(GPIO_FN_LCDD12, NULL);
761 gpio_request(GPIO_FN_LCDD11, NULL); 759 gpio_request(GPIO_FN_LCDD11, NULL);
762 gpio_request(GPIO_FN_LCDD10, NULL); 760 gpio_request(GPIO_FN_LCDD10, NULL);
763 gpio_request(GPIO_FN_LCDD9, NULL); 761 gpio_request(GPIO_FN_LCDD9, NULL);
764 gpio_request(GPIO_FN_LCDD8, NULL); 762 gpio_request(GPIO_FN_LCDD8, NULL);
765 gpio_request(GPIO_FN_LCDD7, NULL); 763 gpio_request(GPIO_FN_LCDD7, NULL);
766 gpio_request(GPIO_FN_LCDD6, NULL); 764 gpio_request(GPIO_FN_LCDD6, NULL);
767 gpio_request(GPIO_FN_LCDD5, NULL); 765 gpio_request(GPIO_FN_LCDD5, NULL);
768 gpio_request(GPIO_FN_LCDD4, NULL); 766 gpio_request(GPIO_FN_LCDD4, NULL);
769 gpio_request(GPIO_FN_LCDD3, NULL); 767 gpio_request(GPIO_FN_LCDD3, NULL);
770 gpio_request(GPIO_FN_LCDD2, NULL); 768 gpio_request(GPIO_FN_LCDD2, NULL);
771 gpio_request(GPIO_FN_LCDD1, NULL); 769 gpio_request(GPIO_FN_LCDD1, NULL);
772 gpio_request(GPIO_FN_LCDD0, NULL); 770 gpio_request(GPIO_FN_LCDD0, NULL);
773 gpio_request(GPIO_FN_LCDDISP, NULL); 771 gpio_request(GPIO_FN_LCDDISP, NULL);
774 gpio_request(GPIO_FN_LCDHSYN, NULL); 772 gpio_request(GPIO_FN_LCDHSYN, NULL);
775 gpio_request(GPIO_FN_LCDDCK, NULL); 773 gpio_request(GPIO_FN_LCDDCK, NULL);
776 gpio_request(GPIO_FN_LCDVSYN, NULL); 774 gpio_request(GPIO_FN_LCDVSYN, NULL);
777 gpio_request(GPIO_FN_LCDDON, NULL); 775 gpio_request(GPIO_FN_LCDDON, NULL);
778 gpio_request(GPIO_FN_LCDVEPWC, NULL); 776 gpio_request(GPIO_FN_LCDVEPWC, NULL);
779 gpio_request(GPIO_FN_LCDVCPWC, NULL); 777 gpio_request(GPIO_FN_LCDVCPWC, NULL);
780 gpio_request(GPIO_FN_LCDRD, NULL); 778 gpio_request(GPIO_FN_LCDRD, NULL);
781 gpio_request(GPIO_FN_LCDLCLK, NULL); 779 gpio_request(GPIO_FN_LCDLCLK, NULL);
782 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA); 780 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
783 781
784 /* enable CEU0 */ 782 /* enable CEU0 */
785 gpio_request(GPIO_FN_VIO0_D15, NULL); 783 gpio_request(GPIO_FN_VIO0_D15, NULL);
786 gpio_request(GPIO_FN_VIO0_D14, NULL); 784 gpio_request(GPIO_FN_VIO0_D14, NULL);
787 gpio_request(GPIO_FN_VIO0_D13, NULL); 785 gpio_request(GPIO_FN_VIO0_D13, NULL);
788 gpio_request(GPIO_FN_VIO0_D12, NULL); 786 gpio_request(GPIO_FN_VIO0_D12, NULL);
789 gpio_request(GPIO_FN_VIO0_D11, NULL); 787 gpio_request(GPIO_FN_VIO0_D11, NULL);
790 gpio_request(GPIO_FN_VIO0_D10, NULL); 788 gpio_request(GPIO_FN_VIO0_D10, NULL);
791 gpio_request(GPIO_FN_VIO0_D9, NULL); 789 gpio_request(GPIO_FN_VIO0_D9, NULL);
792 gpio_request(GPIO_FN_VIO0_D8, NULL); 790 gpio_request(GPIO_FN_VIO0_D8, NULL);
793 gpio_request(GPIO_FN_VIO0_D7, NULL); 791 gpio_request(GPIO_FN_VIO0_D7, NULL);
794 gpio_request(GPIO_FN_VIO0_D6, NULL); 792 gpio_request(GPIO_FN_VIO0_D6, NULL);
795 gpio_request(GPIO_FN_VIO0_D5, NULL); 793 gpio_request(GPIO_FN_VIO0_D5, NULL);
796 gpio_request(GPIO_FN_VIO0_D4, NULL); 794 gpio_request(GPIO_FN_VIO0_D4, NULL);
797 gpio_request(GPIO_FN_VIO0_D3, NULL); 795 gpio_request(GPIO_FN_VIO0_D3, NULL);
798 gpio_request(GPIO_FN_VIO0_D2, NULL); 796 gpio_request(GPIO_FN_VIO0_D2, NULL);
799 gpio_request(GPIO_FN_VIO0_D1, NULL); 797 gpio_request(GPIO_FN_VIO0_D1, NULL);
800 gpio_request(GPIO_FN_VIO0_D0, NULL); 798 gpio_request(GPIO_FN_VIO0_D0, NULL);
801 gpio_request(GPIO_FN_VIO0_VD, NULL); 799 gpio_request(GPIO_FN_VIO0_VD, NULL);
802 gpio_request(GPIO_FN_VIO0_CLK, NULL); 800 gpio_request(GPIO_FN_VIO0_CLK, NULL);
803 gpio_request(GPIO_FN_VIO0_FLD, NULL); 801 gpio_request(GPIO_FN_VIO0_FLD, NULL);
804 gpio_request(GPIO_FN_VIO0_HD, NULL); 802 gpio_request(GPIO_FN_VIO0_HD, NULL);
805 platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); 803 platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
806 804
807 /* enable CEU1 */ 805 /* enable CEU1 */
808 gpio_request(GPIO_FN_VIO1_D7, NULL); 806 gpio_request(GPIO_FN_VIO1_D7, NULL);
809 gpio_request(GPIO_FN_VIO1_D6, NULL); 807 gpio_request(GPIO_FN_VIO1_D6, NULL);
810 gpio_request(GPIO_FN_VIO1_D5, NULL); 808 gpio_request(GPIO_FN_VIO1_D5, NULL);
811 gpio_request(GPIO_FN_VIO1_D4, NULL); 809 gpio_request(GPIO_FN_VIO1_D4, NULL);
812 gpio_request(GPIO_FN_VIO1_D3, NULL); 810 gpio_request(GPIO_FN_VIO1_D3, NULL);
813 gpio_request(GPIO_FN_VIO1_D2, NULL); 811 gpio_request(GPIO_FN_VIO1_D2, NULL);
814 gpio_request(GPIO_FN_VIO1_D1, NULL); 812 gpio_request(GPIO_FN_VIO1_D1, NULL);
815 gpio_request(GPIO_FN_VIO1_D0, NULL); 813 gpio_request(GPIO_FN_VIO1_D0, NULL);
816 gpio_request(GPIO_FN_VIO1_FLD, NULL); 814 gpio_request(GPIO_FN_VIO1_FLD, NULL);
817 gpio_request(GPIO_FN_VIO1_HD, NULL); 815 gpio_request(GPIO_FN_VIO1_HD, NULL);
818 gpio_request(GPIO_FN_VIO1_VD, NULL); 816 gpio_request(GPIO_FN_VIO1_VD, NULL);
819 gpio_request(GPIO_FN_VIO1_CLK, NULL); 817 gpio_request(GPIO_FN_VIO1_CLK, NULL);
820 platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); 818 platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
821 819
822 /* KEYSC */ 820 /* KEYSC */
823 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); 821 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
824 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); 822 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
825 gpio_request(GPIO_FN_KEYIN4, NULL); 823 gpio_request(GPIO_FN_KEYIN4, NULL);
826 gpio_request(GPIO_FN_KEYIN3, NULL); 824 gpio_request(GPIO_FN_KEYIN3, NULL);
827 gpio_request(GPIO_FN_KEYIN2, NULL); 825 gpio_request(GPIO_FN_KEYIN2, NULL);
828 gpio_request(GPIO_FN_KEYIN1, NULL); 826 gpio_request(GPIO_FN_KEYIN1, NULL);
829 gpio_request(GPIO_FN_KEYIN0, NULL); 827 gpio_request(GPIO_FN_KEYIN0, NULL);
830 gpio_request(GPIO_FN_KEYOUT3, NULL); 828 gpio_request(GPIO_FN_KEYOUT3, NULL);
831 gpio_request(GPIO_FN_KEYOUT2, NULL); 829 gpio_request(GPIO_FN_KEYOUT2, NULL);
832 gpio_request(GPIO_FN_KEYOUT1, NULL); 830 gpio_request(GPIO_FN_KEYOUT1, NULL);
833 gpio_request(GPIO_FN_KEYOUT0, NULL); 831 gpio_request(GPIO_FN_KEYOUT0, NULL);
834 832
835 /* enable FSI */ 833 /* enable FSI */
836 gpio_request(GPIO_FN_FSIMCKA, NULL); 834 gpio_request(GPIO_FN_FSIMCKA, NULL);
837 gpio_request(GPIO_FN_FSIIASD, NULL); 835 gpio_request(GPIO_FN_FSIIASD, NULL);
838 gpio_request(GPIO_FN_FSIOASD, NULL); 836 gpio_request(GPIO_FN_FSIOASD, NULL);
839 gpio_request(GPIO_FN_FSIIABCK, NULL); 837 gpio_request(GPIO_FN_FSIIABCK, NULL);
840 gpio_request(GPIO_FN_FSIIALRCK, NULL); 838 gpio_request(GPIO_FN_FSIIALRCK, NULL);
841 gpio_request(GPIO_FN_FSIOABCK, NULL); 839 gpio_request(GPIO_FN_FSIOABCK, NULL);
842 gpio_request(GPIO_FN_FSIOALRCK, NULL); 840 gpio_request(GPIO_FN_FSIOALRCK, NULL);
843 gpio_request(GPIO_FN_CLKAUDIOAO, NULL); 841 gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
844 842
845 /* set SPU2 clock to 83.4 MHz */ 843 /* set SPU2 clock to 83.4 MHz */
846 clk = clk_get(NULL, "spu_clk"); 844 clk = clk_get(NULL, "spu_clk");
847 if (!IS_ERR(clk)) { 845 if (!IS_ERR(clk)) {
848 clk_set_rate(clk, clk_round_rate(clk, 83333333)); 846 clk_set_rate(clk, clk_round_rate(clk, 83333333));
849 clk_put(clk); 847 clk_put(clk);
850 } 848 }
851 849
852 /* change parent of FSI A */ 850 /* change parent of FSI A */
853 clk = clk_get(NULL, "fsia_clk"); 851 clk = clk_get(NULL, "fsia_clk");
854 if (!IS_ERR(clk)) { 852 if (!IS_ERR(clk)) {
855 /* 48kHz dummy clock was used to make sure 1/1 divide */ 853 /* 48kHz dummy clock was used to make sure 1/1 divide */
856 clk_set_rate(&sh7724_fsimcka_clk, 48000); 854 clk_set_rate(&sh7724_fsimcka_clk, 48000);
857 clk_set_parent(clk, &sh7724_fsimcka_clk); 855 clk_set_parent(clk, &sh7724_fsimcka_clk);
858 clk_set_rate(clk, 48000); 856 clk_set_rate(clk, 48000);
859 clk_put(clk); 857 clk_put(clk);
860 } 858 }
861 859
862 /* SDHI0 connected to cn7 */ 860 /* SDHI0 connected to cn7 */
863 gpio_request(GPIO_FN_SDHI0CD, NULL); 861 gpio_request(GPIO_FN_SDHI0CD, NULL);
864 gpio_request(GPIO_FN_SDHI0WP, NULL); 862 gpio_request(GPIO_FN_SDHI0WP, NULL);
865 gpio_request(GPIO_FN_SDHI0D3, NULL); 863 gpio_request(GPIO_FN_SDHI0D3, NULL);
866 gpio_request(GPIO_FN_SDHI0D2, NULL); 864 gpio_request(GPIO_FN_SDHI0D2, NULL);
867 gpio_request(GPIO_FN_SDHI0D1, NULL); 865 gpio_request(GPIO_FN_SDHI0D1, NULL);
868 gpio_request(GPIO_FN_SDHI0D0, NULL); 866 gpio_request(GPIO_FN_SDHI0D0, NULL);
869 gpio_request(GPIO_FN_SDHI0CMD, NULL); 867 gpio_request(GPIO_FN_SDHI0CMD, NULL);
870 gpio_request(GPIO_FN_SDHI0CLK, NULL); 868 gpio_request(GPIO_FN_SDHI0CLK, NULL);
871 869
872 /* SDHI1 connected to cn8 */ 870 /* SDHI1 connected to cn8 */
873 gpio_request(GPIO_FN_SDHI1CD, NULL); 871 gpio_request(GPIO_FN_SDHI1CD, NULL);
874 gpio_request(GPIO_FN_SDHI1WP, NULL); 872 gpio_request(GPIO_FN_SDHI1WP, NULL);
875 gpio_request(GPIO_FN_SDHI1D3, NULL); 873 gpio_request(GPIO_FN_SDHI1D3, NULL);
876 gpio_request(GPIO_FN_SDHI1D2, NULL); 874 gpio_request(GPIO_FN_SDHI1D2, NULL);
877 gpio_request(GPIO_FN_SDHI1D1, NULL); 875 gpio_request(GPIO_FN_SDHI1D1, NULL);
878 gpio_request(GPIO_FN_SDHI1D0, NULL); 876 gpio_request(GPIO_FN_SDHI1D0, NULL);
879 gpio_request(GPIO_FN_SDHI1CMD, NULL); 877 gpio_request(GPIO_FN_SDHI1CMD, NULL);
880 gpio_request(GPIO_FN_SDHI1CLK, NULL); 878 gpio_request(GPIO_FN_SDHI1CLK, NULL);
881 879
882 /* enable IrDA */ 880 /* enable IrDA */
883 gpio_request(GPIO_FN_IRDA_OUT, NULL); 881 gpio_request(GPIO_FN_IRDA_OUT, NULL);
884 gpio_request(GPIO_FN_IRDA_IN, NULL); 882 gpio_request(GPIO_FN_IRDA_IN, NULL);
885 883
886 /* 884 /*
887 * enable SH-Eth 885 * enable SH-Eth
888 * 886 *
889 * please remove J33 pin from your board !! 887 * please remove J33 pin from your board !!
890 * 888 *
891 * ms7724 board should not use GPIO_FN_LNKSTA pin 889 * ms7724 board should not use GPIO_FN_LNKSTA pin
892 * So, This time PTX5 is set to input pin 890 * So, This time PTX5 is set to input pin
893 */ 891 */
894 gpio_request(GPIO_FN_RMII_RXD0, NULL); 892 gpio_request(GPIO_FN_RMII_RXD0, NULL);
895 gpio_request(GPIO_FN_RMII_RXD1, NULL); 893 gpio_request(GPIO_FN_RMII_RXD1, NULL);
896 gpio_request(GPIO_FN_RMII_TXD0, NULL); 894 gpio_request(GPIO_FN_RMII_TXD0, NULL);
897 gpio_request(GPIO_FN_RMII_TXD1, NULL); 895 gpio_request(GPIO_FN_RMII_TXD1, NULL);
898 gpio_request(GPIO_FN_RMII_REF_CLK, NULL); 896 gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
899 gpio_request(GPIO_FN_RMII_TX_EN, NULL); 897 gpio_request(GPIO_FN_RMII_TX_EN, NULL);
900 gpio_request(GPIO_FN_RMII_RX_ER, NULL); 898 gpio_request(GPIO_FN_RMII_RX_ER, NULL);
901 gpio_request(GPIO_FN_RMII_CRS_DV, NULL); 899 gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
902 gpio_request(GPIO_FN_MDIO, NULL); 900 gpio_request(GPIO_FN_MDIO, NULL);
903 gpio_request(GPIO_FN_MDC, NULL); 901 gpio_request(GPIO_FN_MDC, NULL);
904 gpio_request(GPIO_PTX5, NULL); 902 gpio_request(GPIO_PTX5, NULL);
905 gpio_direction_input(GPIO_PTX5); 903 gpio_direction_input(GPIO_PTX5);
906 sh_eth_init(); 904 sh_eth_init();
907 905
908 if (sw & SW41_B) { 906 if (sw & SW41_B) {
909 /* 720p */ 907 /* 720p */
910 lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes; 908 lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes;
911 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes); 909 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes);
912 } else { 910 } else {
913 /* VGA */ 911 /* VGA */
914 lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes; 912 lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes;
915 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes); 913 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes);
916 } 914 }
917 915
918 if (sw & SW41_A) { 916 if (sw & SW41_A) {
919 /* Digital monitor */ 917 /* Digital monitor */
920 lcdc_info.ch[0].interface_type = RGB18; 918 lcdc_info.ch[0].interface_type = RGB18;
921 lcdc_info.ch[0].flags = 0; 919 lcdc_info.ch[0].flags = 0;
922 } else { 920 } else {
923 /* Analog monitor */ 921 /* Analog monitor */
924 lcdc_info.ch[0].interface_type = RGB24; 922 lcdc_info.ch[0].interface_type = RGB24;
925 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; 923 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
926 } 924 }
927 925
928 /* VOU */ 926 /* VOU */
929 gpio_request(GPIO_FN_DV_D15, NULL); 927 gpio_request(GPIO_FN_DV_D15, NULL);
930 gpio_request(GPIO_FN_DV_D14, NULL); 928 gpio_request(GPIO_FN_DV_D14, NULL);
931 gpio_request(GPIO_FN_DV_D13, NULL); 929 gpio_request(GPIO_FN_DV_D13, NULL);
932 gpio_request(GPIO_FN_DV_D12, NULL); 930 gpio_request(GPIO_FN_DV_D12, NULL);
933 gpio_request(GPIO_FN_DV_D11, NULL); 931 gpio_request(GPIO_FN_DV_D11, NULL);
934 gpio_request(GPIO_FN_DV_D10, NULL); 932 gpio_request(GPIO_FN_DV_D10, NULL);
935 gpio_request(GPIO_FN_DV_D9, NULL); 933 gpio_request(GPIO_FN_DV_D9, NULL);
936 gpio_request(GPIO_FN_DV_D8, NULL); 934 gpio_request(GPIO_FN_DV_D8, NULL);
937 gpio_request(GPIO_FN_DV_CLKI, NULL); 935 gpio_request(GPIO_FN_DV_CLKI, NULL);
938 gpio_request(GPIO_FN_DV_CLK, NULL); 936 gpio_request(GPIO_FN_DV_CLK, NULL);
939 gpio_request(GPIO_FN_DV_VSYNC, NULL); 937 gpio_request(GPIO_FN_DV_VSYNC, NULL);
940 gpio_request(GPIO_FN_DV_HSYNC, NULL); 938 gpio_request(GPIO_FN_DV_HSYNC, NULL);
941 939
942 return platform_add_devices(ms7724se_devices, 940 return platform_add_devices(ms7724se_devices,
943 ARRAY_SIZE(ms7724se_devices)); 941 ARRAY_SIZE(ms7724se_devices));
944 } 942 }
945 device_initcall(devices_setup); 943 device_initcall(devices_setup);
946 944
947 static struct sh_machine_vector mv_ms7724se __initmv = { 945 static struct sh_machine_vector mv_ms7724se __initmv = {
948 .mv_name = "ms7724se", 946 .mv_name = "ms7724se",
949 .mv_init_irq = init_se7724_IRQ, 947 .mv_init_irq = init_se7724_IRQ,
950 .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR, 948 .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR,
951 }; 949 };
952 950
include/sound/sh_fsi.h
Diff comments   View file @ f17c13c
1 #ifndef __SOUND_FSI_H 1 #ifndef __SOUND_FSI_H
2 #define __SOUND_FSI_H 2 #define __SOUND_FSI_H
3 3
4 /* 4 /*
5 * Fifo-attached Serial Interface (FSI) support for SH7724 5 * Fifo-attached Serial Interface (FSI) support for SH7724
6 * 6 *
7 * Copyright (C) 2009 Renesas Solutions Corp. 7 * Copyright (C) 2009 Renesas Solutions Corp.
8 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 8 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14 14
15 #define FSI_PORT_A 0 15 #define FSI_PORT_A 0
16 #define FSI_PORT_B 1 16 #define FSI_PORT_B 1
17 17
18 /* flags format 18 #include <linux/clk.h>
19 #include <sound/soc.h>
19 20
20 * 0xABC0EEFF 21 /*
22 * flags format
21 * 23 *
22 * A: channel size for TDM (input) 24 * 0x000000BA
23 * B: channel size for TDM (ooutput) 25 *
24 * C: inversion 26 * A: inversion
25 * E: input format 27 * B: format mode
26 * F: output format
27 */ 28 */
28 29
29 #include <linux/clk.h> 30 /* A: clock inversion */
30 #include <sound/soc.h> 31 #define SH_FSI_INVERSION_MASK 0x0000000F
32 #define SH_FSI_LRM_INV (1 << 0)
33 #define SH_FSI_BRM_INV (1 << 1)
34 #define SH_FSI_LRS_INV (1 << 2)
35 #define SH_FSI_BRS_INV (1 << 3)
31 36
32 /* TDM channel */ 37 /* B: format mode */
33 #define SH_FSI_SET_CH_I(x) ((x & 0xF) << 28) 38 #define SH_FSI_FMT_MASK 0x000000F0
34 #define SH_FSI_SET_CH_O(x) ((x & 0xF) << 24) 39 #define SH_FSI_FMT_DAI (0 << 4)
35 40 #define SH_FSI_FMT_SPDIF (1 << 4)
36 #define SH_FSI_CH_IMASK 0xF0000000
37 #define SH_FSI_CH_OMASK 0x0F000000
38 #define SH_FSI_GET_CH_I(x) ((x & SH_FSI_CH_IMASK) >> 28)
39 #define SH_FSI_GET_CH_O(x) ((x & SH_FSI_CH_OMASK) >> 24)
40
41 /* clock inversion */
42 #define SH_FSI_INVERSION_MASK 0x00F00000
43 #define SH_FSI_LRM_INV (1 << 20)
44 #define SH_FSI_BRM_INV (1 << 21)
45 #define SH_FSI_LRS_INV (1 << 22)
46 #define SH_FSI_BRS_INV (1 << 23)
47
48 /* DI format */
49 #define SH_FSI_FMT_MASK 0x000000FF
50 #define SH_FSI_IFMT(x) (((SH_FSI_FMT_ ## x) & SH_FSI_FMT_MASK) << 8)
51 #define SH_FSI_OFMT(x) (((SH_FSI_FMT_ ## x) & SH_FSI_FMT_MASK) << 0)
52 #define SH_FSI_GET_IFMT(x) ((x >> 8) & SH_FSI_FMT_MASK)
53 #define SH_FSI_GET_OFMT(x) ((x >> 0) & SH_FSI_FMT_MASK)
54
55 #define SH_FSI_FMT_MONO 0
56 #define SH_FSI_FMT_MONO_DELAY 1
57 #define SH_FSI_FMT_PCM 2
58 #define SH_FSI_FMT_I2S 3
59 #define SH_FSI_FMT_TDM 4
60 #define SH_FSI_FMT_TDM_DELAY 5
61 #define SH_FSI_FMT_SPDIF 6
62
63
64 #define SH_FSI_IFMT_TDM_CH(x) \
65 (SH_FSI_IFMT(TDM) | SH_FSI_SET_CH_I(x))
66 #define SH_FSI_IFMT_TDM_DELAY_CH(x) \
67 (SH_FSI_IFMT(TDM_DELAY) | SH_FSI_SET_CH_I(x))
68
69 #define SH_FSI_OFMT_TDM_CH(x) \
70 (SH_FSI_OFMT(TDM) | SH_FSI_SET_CH_O(x))
71 #define SH_FSI_OFMT_TDM_DELAY_CH(x) \
72 (SH_FSI_OFMT(TDM_DELAY) | SH_FSI_SET_CH_O(x))
73 41
74 42
75 /* 43 /*
76 * set_rate return value 44 * set_rate return value
77 * 45 *
78 * see ACKMD/BPFMD on 46 * see ACKMD/BPFMD on
79 * ACK_MD (FSI2) 47 * ACK_MD (FSI2)
80 * CKG1 (FSI) 48 * CKG1 (FSI)
81 * 49 *
82 * err : return value < 0 50 * err : return value < 0
83 * no change : return value == 0 51 * no change : return value == 0
84 * change xMD : return value > 0 52 * change xMD : return value > 0
85 * 53 *
86 * 0x-00000AB 54 * 0x-00000AB
87 * 55 *
88 * A: ACKMD value 56 * A: ACKMD value
89 * B: BPFMD value 57 * B: BPFMD value
90 */ 58 */
91 59
92 #define SH_FSI_ACKMD_MASK (0xF << 0) 60 #define SH_FSI_ACKMD_MASK (0xF << 0)
93 #define SH_FSI_ACKMD_512 (1 << 0) 61 #define SH_FSI_ACKMD_512 (1 << 0)
94 #define SH_FSI_ACKMD_256 (2 << 0) 62 #define SH_FSI_ACKMD_256 (2 << 0)
95 #define SH_FSI_ACKMD_128 (3 << 0) 63 #define SH_FSI_ACKMD_128 (3 << 0)
96 #define SH_FSI_ACKMD_64 (4 << 0) 64 #define SH_FSI_ACKMD_64 (4 << 0)
97 #define SH_FSI_ACKMD_32 (5 << 0) 65 #define SH_FSI_ACKMD_32 (5 << 0)
98 66
99 #define SH_FSI_BPFMD_MASK (0xF << 4) 67 #define SH_FSI_BPFMD_MASK (0xF << 4)
100 #define SH_FSI_BPFMD_512 (1 << 4) 68 #define SH_FSI_BPFMD_512 (1 << 4)
101 #define SH_FSI_BPFMD_256 (2 << 4) 69 #define SH_FSI_BPFMD_256 (2 << 4)
102 #define SH_FSI_BPFMD_128 (3 << 4) 70 #define SH_FSI_BPFMD_128 (3 << 4)
103 #define SH_FSI_BPFMD_64 (4 << 4) 71 #define SH_FSI_BPFMD_64 (4 << 4)
104 #define SH_FSI_BPFMD_32 (5 << 4) 72 #define SH_FSI_BPFMD_32 (5 << 4)
105 #define SH_FSI_BPFMD_16 (6 << 4) 73 #define SH_FSI_BPFMD_16 (6 << 4)
106 74
107 struct sh_fsi_platform_info { 75 struct sh_fsi_platform_info {
108 unsigned long porta_flags; 76 unsigned long porta_flags;
sound/soc/sh/fsi-ak4642.c
Diff comments   View file @ f17c13c
1 /* 1 /*
2 * FSI-AK464x sound support for ms7724se 2 * FSI-AK464x sound support for ms7724se
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details. 9 * for more details.
10 */ 10 */
11 11
12 #include <linux/platform_device.h> 12 #include <linux/platform_device.h>
13 #include <sound/sh_fsi.h> 13 #include <sound/sh_fsi.h>
14 14
15 struct fsi_ak4642_data { 15 struct fsi_ak4642_data {
16 const char *name; 16 const char *name;
17 const char *card; 17 const char *card;
18 const char *cpu_dai; 18 const char *cpu_dai;
19 const char *codec; 19 const char *codec;
20 const char *platform; 20 const char *platform;
21 int id; 21 int id;
22 }; 22 };
23 23
24 static int fsi_ak4642_dai_init(struct snd_soc_pcm_runtime *rtd) 24 static int fsi_ak4642_dai_init(struct snd_soc_pcm_runtime *rtd)
25 { 25 {
26 struct snd_soc_dai *codec = rtd->codec_dai; 26 struct snd_soc_dai *codec = rtd->codec_dai;
27 struct snd_soc_dai *cpu = rtd->cpu_dai; 27 struct snd_soc_dai *cpu = rtd->cpu_dai;
28 int ret; 28 int ret;
29 29
30 ret = snd_soc_dai_set_fmt(codec, SND_SOC_DAIFMT_LEFT_J | 30 ret = snd_soc_dai_set_fmt(codec, SND_SOC_DAIFMT_LEFT_J |
31 SND_SOC_DAIFMT_CBM_CFM); 31 SND_SOC_DAIFMT_CBM_CFM);
32 if (ret < 0) 32 if (ret < 0)
33 return ret; 33 return ret;
34 34
35 ret = snd_soc_dai_set_sysclk(codec, 0, 11289600, 0); 35 ret = snd_soc_dai_set_sysclk(codec, 0, 11289600, 0);
36 if (ret < 0) 36 if (ret < 0)
37 return ret; 37 return ret;
38 38
39 ret = snd_soc_dai_set_fmt(cpu, SND_SOC_DAIFMT_CBS_CFS); 39 ret = snd_soc_dai_set_fmt(cpu, SND_SOC_DAIFMT_LEFT_J |
40 SND_SOC_DAIFMT_CBS_CFS);
40 41
41 return ret; 42 return ret;
42 } 43 }
43 44
44 static struct snd_soc_dai_link fsi_dai_link = { 45 static struct snd_soc_dai_link fsi_dai_link = {
45 .codec_dai_name = "ak4642-hifi", 46 .codec_dai_name = "ak4642-hifi",
46 .init = fsi_ak4642_dai_init, 47 .init = fsi_ak4642_dai_init,
47 }; 48 };
48 49
49 static struct snd_soc_card fsi_soc_card = { 50 static struct snd_soc_card fsi_soc_card = {
50 .dai_link = &fsi_dai_link, 51 .dai_link = &fsi_dai_link,
51 .num_links = 1, 52 .num_links = 1,
52 }; 53 };
53 54
54 static struct platform_device *fsi_snd_device; 55 static struct platform_device *fsi_snd_device;
55 56
56 static int fsi_ak4642_probe(struct platform_device *pdev) 57 static int fsi_ak4642_probe(struct platform_device *pdev)
57 { 58 {
58 int ret = -ENOMEM; 59 int ret = -ENOMEM;
59 const struct platform_device_id *id_entry; 60 const struct platform_device_id *id_entry;
60 struct fsi_ak4642_data *pdata; 61 struct fsi_ak4642_data *pdata;
61 62
62 id_entry = pdev->id_entry; 63 id_entry = pdev->id_entry;
63 if (!id_entry) { 64 if (!id_entry) {
64 dev_err(&pdev->dev, "unknown fsi ak4642\n"); 65 dev_err(&pdev->dev, "unknown fsi ak4642\n");
65 return -ENODEV; 66 return -ENODEV;
66 } 67 }
67 68
68 pdata = (struct fsi_ak4642_data *)id_entry->driver_data; 69 pdata = (struct fsi_ak4642_data *)id_entry->driver_data;
69 70
70 fsi_snd_device = platform_device_alloc("soc-audio", pdata->id); 71 fsi_snd_device = platform_device_alloc("soc-audio", pdata->id);
71 if (!fsi_snd_device) 72 if (!fsi_snd_device)
72 goto out; 73 goto out;
73 74
74 fsi_dai_link.name = pdata->name; 75 fsi_dai_link.name = pdata->name;
75 fsi_dai_link.stream_name = pdata->name; 76 fsi_dai_link.stream_name = pdata->name;
76 fsi_dai_link.cpu_dai_name = pdata->cpu_dai; 77 fsi_dai_link.cpu_dai_name = pdata->cpu_dai;
77 fsi_dai_link.platform_name = pdata->platform; 78 fsi_dai_link.platform_name = pdata->platform;
78 fsi_dai_link.codec_name = pdata->codec; 79 fsi_dai_link.codec_name = pdata->codec;
79 fsi_soc_card.name = pdata->card; 80 fsi_soc_card.name = pdata->card;
80 81
81 platform_set_drvdata(fsi_snd_device, &fsi_soc_card); 82 platform_set_drvdata(fsi_snd_device, &fsi_soc_card);
82 ret = platform_device_add(fsi_snd_device); 83 ret = platform_device_add(fsi_snd_device);
83 84
84 if (ret) 85 if (ret)
85 platform_device_put(fsi_snd_device); 86 platform_device_put(fsi_snd_device);
86 87
87 out: 88 out:
88 return ret; 89 return ret;
89 } 90 }
90 91
91 static int fsi_ak4642_remove(struct platform_device *pdev) 92 static int fsi_ak4642_remove(struct platform_device *pdev)
92 { 93 {
93 platform_device_unregister(fsi_snd_device); 94 platform_device_unregister(fsi_snd_device);
94 return 0; 95 return 0;
95 } 96 }
96 97
97 static struct fsi_ak4642_data fsi_a_ak4642 = { 98 static struct fsi_ak4642_data fsi_a_ak4642 = {
98 .name = "AK4642", 99 .name = "AK4642",
99 .card = "FSIA (AK4642)", 100 .card = "FSIA (AK4642)",
100 .cpu_dai = "fsia-dai", 101 .cpu_dai = "fsia-dai",
101 .codec = "ak4642-codec.0-0012", 102 .codec = "ak4642-codec.0-0012",
102 .platform = "sh_fsi.0", 103 .platform = "sh_fsi.0",
103 .id = FSI_PORT_A, 104 .id = FSI_PORT_A,
104 }; 105 };
105 106
106 static struct fsi_ak4642_data fsi_b_ak4642 = { 107 static struct fsi_ak4642_data fsi_b_ak4642 = {
107 .name = "AK4642", 108 .name = "AK4642",
108 .card = "FSIB (AK4642)", 109 .card = "FSIB (AK4642)",
109 .cpu_dai = "fsib-dai", 110 .cpu_dai = "fsib-dai",
110 .codec = "ak4642-codec.0-0012", 111 .codec = "ak4642-codec.0-0012",
111 .platform = "sh_fsi.0", 112 .platform = "sh_fsi.0",
112 .id = FSI_PORT_B, 113 .id = FSI_PORT_B,
113 }; 114 };
114 115
115 static struct fsi_ak4642_data fsi_a_ak4643 = { 116 static struct fsi_ak4642_data fsi_a_ak4643 = {
116 .name = "AK4643", 117 .name = "AK4643",
117 .card = "FSIA (AK4643)", 118 .card = "FSIA (AK4643)",
118 .cpu_dai = "fsia-dai", 119 .cpu_dai = "fsia-dai",
119 .codec = "ak4642-codec.0-0013", 120 .codec = "ak4642-codec.0-0013",
120 .platform = "sh_fsi.0", 121 .platform = "sh_fsi.0",
121 .id = FSI_PORT_A, 122 .id = FSI_PORT_A,
122 }; 123 };
123 124
124 static struct fsi_ak4642_data fsi_b_ak4643 = { 125 static struct fsi_ak4642_data fsi_b_ak4643 = {
125 .name = "AK4643", 126 .name = "AK4643",
126 .card = "FSIB (AK4643)", 127 .card = "FSIB (AK4643)",
127 .cpu_dai = "fsib-dai", 128 .cpu_dai = "fsib-dai",
128 .codec = "ak4642-codec.0-0013", 129 .codec = "ak4642-codec.0-0013",
129 .platform = "sh_fsi.0", 130 .platform = "sh_fsi.0",
130 .id = FSI_PORT_B, 131 .id = FSI_PORT_B,
131 }; 132 };
132 133
133 static struct fsi_ak4642_data fsi2_a_ak4642 = { 134 static struct fsi_ak4642_data fsi2_a_ak4642 = {
134 .name = "AK4642", 135 .name = "AK4642",
135 .card = "FSI2A (AK4642)", 136 .card = "FSI2A (AK4642)",
136 .cpu_dai = "fsia-dai", 137 .cpu_dai = "fsia-dai",
137 .codec = "ak4642-codec.0-0012", 138 .codec = "ak4642-codec.0-0012",
138 .platform = "sh_fsi2", 139 .platform = "sh_fsi2",
139 .id = FSI_PORT_A, 140 .id = FSI_PORT_A,
140 }; 141 };
141 142
142 static struct fsi_ak4642_data fsi2_b_ak4642 = { 143 static struct fsi_ak4642_data fsi2_b_ak4642 = {
143 .name = "AK4642", 144 .name = "AK4642",
144 .card = "FSI2B (AK4642)", 145 .card = "FSI2B (AK4642)",
145 .cpu_dai = "fsib-dai", 146 .cpu_dai = "fsib-dai",
146 .codec = "ak4642-codec.0-0012", 147 .codec = "ak4642-codec.0-0012",
147 .platform = "sh_fsi2", 148 .platform = "sh_fsi2",
148 .id = FSI_PORT_B, 149 .id = FSI_PORT_B,
149 }; 150 };
150 151
151 static struct fsi_ak4642_data fsi2_a_ak4643 = { 152 static struct fsi_ak4642_data fsi2_a_ak4643 = {
152 .name = "AK4643", 153 .name = "AK4643",
153 .card = "FSI2A (AK4643)", 154 .card = "FSI2A (AK4643)",
154 .cpu_dai = "fsia-dai", 155 .cpu_dai = "fsia-dai",
155 .codec = "ak4642-codec.0-0013", 156 .codec = "ak4642-codec.0-0013",
156 .platform = "sh_fsi2", 157 .platform = "sh_fsi2",
157 .id = FSI_PORT_A, 158 .id = FSI_PORT_A,
158 }; 159 };
159 160
160 static struct fsi_ak4642_data fsi2_b_ak4643 = { 161 static struct fsi_ak4642_data fsi2_b_ak4643 = {
161 .name = "AK4643", 162 .name = "AK4643",
162 .card = "FSI2B (AK4643)", 163 .card = "FSI2B (AK4643)",
163 .cpu_dai = "fsib-dai", 164 .cpu_dai = "fsib-dai",
164 .codec = "ak4642-codec.0-0013", 165 .codec = "ak4642-codec.0-0013",
165 .platform = "sh_fsi2", 166 .platform = "sh_fsi2",
166 .id = FSI_PORT_B, 167 .id = FSI_PORT_B,
167 }; 168 };
168 169
169 static struct platform_device_id fsi_id_table[] = { 170 static struct platform_device_id fsi_id_table[] = {
170 /* FSI */ 171 /* FSI */
171 { "sh_fsi_a_ak4642", (kernel_ulong_t)&fsi_a_ak4642 }, 172 { "sh_fsi_a_ak4642", (kernel_ulong_t)&fsi_a_ak4642 },
172 { "sh_fsi_b_ak4642", (kernel_ulong_t)&fsi_b_ak4642 }, 173 { "sh_fsi_b_ak4642", (kernel_ulong_t)&fsi_b_ak4642 },
173 { "sh_fsi_a_ak4643", (kernel_ulong_t)&fsi_a_ak4643 }, 174 { "sh_fsi_a_ak4643", (kernel_ulong_t)&fsi_a_ak4643 },
174 { "sh_fsi_b_ak4643", (kernel_ulong_t)&fsi_b_ak4643 }, 175 { "sh_fsi_b_ak4643", (kernel_ulong_t)&fsi_b_ak4643 },
175 176
176 /* FSI 2 */ 177 /* FSI 2 */
177 { "sh_fsi2_a_ak4642", (kernel_ulong_t)&fsi2_a_ak4642 }, 178 { "sh_fsi2_a_ak4642", (kernel_ulong_t)&fsi2_a_ak4642 },
178 { "sh_fsi2_b_ak4642", (kernel_ulong_t)&fsi2_b_ak4642 }, 179 { "sh_fsi2_b_ak4642", (kernel_ulong_t)&fsi2_b_ak4642 },
179 { "sh_fsi2_a_ak4643", (kernel_ulong_t)&fsi2_a_ak4643 }, 180 { "sh_fsi2_a_ak4643", (kernel_ulong_t)&fsi2_a_ak4643 },
180 { "sh_fsi2_b_ak4643", (kernel_ulong_t)&fsi2_b_ak4643 }, 181 { "sh_fsi2_b_ak4643", (kernel_ulong_t)&fsi2_b_ak4643 },
181 {}, 182 {},
182 }; 183 };
183 184
184 static struct platform_driver fsi_ak4642 = { 185 static struct platform_driver fsi_ak4642 = {
185 .driver = { 186 .driver = {
186 .name = "fsi-ak4642-audio", 187 .name = "fsi-ak4642-audio",
187 }, 188 },
188 .probe = fsi_ak4642_probe, 189 .probe = fsi_ak4642_probe,
189 .remove = fsi_ak4642_remove, 190 .remove = fsi_ak4642_remove,
190 .id_table = fsi_id_table, 191 .id_table = fsi_id_table,
191 }; 192 };
192 193
193 static int __init fsi_ak4642_init(void) 194 static int __init fsi_ak4642_init(void)
194 { 195 {
195 return platform_driver_register(&fsi_ak4642); 196 return platform_driver_register(&fsi_ak4642);
196 } 197 }
197 198
198 static void __exit fsi_ak4642_exit(void) 199 static void __exit fsi_ak4642_exit(void)
199 { 200 {
200 platform_driver_unregister(&fsi_ak4642); 201 platform_driver_unregister(&fsi_ak4642);
201 } 202 }
202 203
203 module_init(fsi_ak4642_init); 204 module_init(fsi_ak4642_init);
204 module_exit(fsi_ak4642_exit); 205 module_exit(fsi_ak4642_exit);
205 206
206 MODULE_LICENSE("GPL"); 207 MODULE_LICENSE("GPL");
207 MODULE_DESCRIPTION("Generic SH4 FSI-AK4642 sound card"); 208 MODULE_DESCRIPTION("Generic SH4 FSI-AK4642 sound card");
208 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 209 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
209 210
sound/soc/sh/fsi-da7210.c
Diff comments   View file @ f17c13c
1 /* 1 /*
2 * fsi-da7210.c 2 * fsi-da7210.c
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your 9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13 #include <linux/platform_device.h> 13 #include <linux/platform_device.h>
14 #include <sound/sh_fsi.h> 14 #include <sound/sh_fsi.h>
15 15
16 static int fsi_da7210_init(struct snd_soc_pcm_runtime *rtd) 16 static int fsi_da7210_init(struct snd_soc_pcm_runtime *rtd)
17 { 17 {
18 struct snd_soc_dai *codec = rtd->codec_dai; 18 struct snd_soc_dai *codec = rtd->codec_dai;
19 struct snd_soc_dai *cpu = rtd->cpu_dai; 19 struct snd_soc_dai *cpu = rtd->cpu_dai;
20 int ret; 20 int ret;
21 21
22 ret = snd_soc_dai_set_fmt(codec, 22 ret = snd_soc_dai_set_fmt(codec,
23 SND_SOC_DAIFMT_I2S | 23 SND_SOC_DAIFMT_I2S |
24 SND_SOC_DAIFMT_CBM_CFM); 24 SND_SOC_DAIFMT_CBM_CFM);
25 if (ret < 0) 25 if (ret < 0)
26 return ret; 26 return ret;
27 27
28 ret = snd_soc_dai_set_fmt(cpu, SND_SOC_DAIFMT_CBS_CFS); 28 ret = snd_soc_dai_set_fmt(cpu, SND_SOC_DAIFMT_I2S |
29 SND_SOC_DAIFMT_CBS_CFS);
29 30
30 return ret; 31 return ret;
31 } 32 }
32 33
33 static struct snd_soc_dai_link fsi_da7210_dai = { 34 static struct snd_soc_dai_link fsi_da7210_dai = {
34 .name = "DA7210", 35 .name = "DA7210",
35 .stream_name = "DA7210", 36 .stream_name = "DA7210",
36 .cpu_dai_name = "fsib-dai", /* FSI B */ 37 .cpu_dai_name = "fsib-dai", /* FSI B */
37 .codec_dai_name = "da7210-hifi", 38 .codec_dai_name = "da7210-hifi",
38 .platform_name = "sh_fsi.0", 39 .platform_name = "sh_fsi.0",
39 .codec_name = "da7210-codec.0-001a", 40 .codec_name = "da7210-codec.0-001a",
40 .init = fsi_da7210_init, 41 .init = fsi_da7210_init,
41 }; 42 };
42 43
43 static struct snd_soc_card fsi_soc_card = { 44 static struct snd_soc_card fsi_soc_card = {
44 .name = "FSI (DA7210)", 45 .name = "FSI (DA7210)",
45 .dai_link = &fsi_da7210_dai, 46 .dai_link = &fsi_da7210_dai,
46 .num_links = 1, 47 .num_links = 1,
47 }; 48 };
48 49
49 static struct platform_device *fsi_da7210_snd_device; 50 static struct platform_device *fsi_da7210_snd_device;
50 51
51 static int __init fsi_da7210_sound_init(void) 52 static int __init fsi_da7210_sound_init(void)
52 { 53 {
53 int ret; 54 int ret;
54 55
55 fsi_da7210_snd_device = platform_device_alloc("soc-audio", FSI_PORT_B); 56 fsi_da7210_snd_device = platform_device_alloc("soc-audio", FSI_PORT_B);
56 if (!fsi_da7210_snd_device) 57 if (!fsi_da7210_snd_device)
57 return -ENOMEM; 58 return -ENOMEM;
58 59
59 platform_set_drvdata(fsi_da7210_snd_device, &fsi_soc_card); 60 platform_set_drvdata(fsi_da7210_snd_device, &fsi_soc_card);
60 ret = platform_device_add(fsi_da7210_snd_device); 61 ret = platform_device_add(fsi_da7210_snd_device);
61 if (ret) 62 if (ret)
62 platform_device_put(fsi_da7210_snd_device); 63 platform_device_put(fsi_da7210_snd_device);
63 64
64 return ret; 65 return ret;
65 } 66 }
66 67
67 static void __exit fsi_da7210_sound_exit(void) 68 static void __exit fsi_da7210_sound_exit(void)
68 { 69 {
69 platform_device_unregister(fsi_da7210_snd_device); 70 platform_device_unregister(fsi_da7210_snd_device);
70 } 71 }
71 72
72 module_init(fsi_da7210_sound_init); 73 module_init(fsi_da7210_sound_init);
73 module_exit(fsi_da7210_sound_exit); 74 module_exit(fsi_da7210_sound_exit);
74 75
75 /* Module information */ 76 /* Module information */
76 MODULE_DESCRIPTION("ALSA SoC FSI DA2710"); 77 MODULE_DESCRIPTION("ALSA SoC FSI DA2710");
77 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 78 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
78 MODULE_LICENSE("GPL"); 79 MODULE_LICENSE("GPL");
79 80
1 /* 1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724 2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * 6 *
7 * Based on ssi.c 7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> 8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14 14
15 #include <linux/delay.h> 15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h> 16 #include <linux/pm_runtime.h>
17 #include <linux/io.h> 17 #include <linux/io.h>
18 #include <linux/slab.h> 18 #include <linux/slab.h>
19 #include <sound/soc.h> 19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h> 20 #include <sound/sh_fsi.h>
21 21
22 /* PortA/PortB register */ 22 /* PortA/PortB register */
23 #define REG_DO_FMT 0x0000 23 #define REG_DO_FMT 0x0000
24 #define REG_DOFF_CTL 0x0004 24 #define REG_DOFF_CTL 0x0004
25 #define REG_DOFF_ST 0x0008 25 #define REG_DOFF_ST 0x0008
26 #define REG_DI_FMT 0x000C 26 #define REG_DI_FMT 0x000C
27 #define REG_DIFF_CTL 0x0010 27 #define REG_DIFF_CTL 0x0010
28 #define REG_DIFF_ST 0x0014 28 #define REG_DIFF_ST 0x0014
29 #define REG_CKG1 0x0018 29 #define REG_CKG1 0x0018
30 #define REG_CKG2 0x001C 30 #define REG_CKG2 0x001C
31 #define REG_DIDT 0x0020 31 #define REG_DIDT 0x0020
32 #define REG_DODT 0x0024 32 #define REG_DODT 0x0024
33 #define REG_MUTE_ST 0x0028 33 #define REG_MUTE_ST 0x0028
34 #define REG_OUT_SEL 0x0030 34 #define REG_OUT_SEL 0x0030
35 35
36 /* master register */ 36 /* master register */
37 #define MST_CLK_RST 0x0210 37 #define MST_CLK_RST 0x0210
38 #define MST_SOFT_RST 0x0214 38 #define MST_SOFT_RST 0x0214
39 #define MST_FIFO_SZ 0x0218 39 #define MST_FIFO_SZ 0x0218
40 40
41 /* core register (depend on FSI version) */ 41 /* core register (depend on FSI version) */
42 #define A_MST_CTLR 0x0180 42 #define A_MST_CTLR 0x0180
43 #define B_MST_CTLR 0x01A0 43 #define B_MST_CTLR 0x01A0
44 #define CPU_INT_ST 0x01F4 44 #define CPU_INT_ST 0x01F4
45 #define CPU_IEMSK 0x01F8 45 #define CPU_IEMSK 0x01F8
46 #define CPU_IMSK 0x01FC 46 #define CPU_IMSK 0x01FC
47 #define INT_ST 0x0200 47 #define INT_ST 0x0200
48 #define IEMSK 0x0204 48 #define IEMSK 0x0204
49 #define IMSK 0x0208 49 #define IMSK 0x0208
50 50
51 /* DO_FMT */ 51 /* DO_FMT */
52 /* DI_FMT */ 52 /* DI_FMT */
53 #define CR_BWS_24 (0x0 << 20) /* FSI2 */ 53 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
54 #define CR_BWS_16 (0x1 << 20) /* FSI2 */ 54 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
55 #define CR_BWS_20 (0x2 << 20) /* FSI2 */ 55 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
56 56
57 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ 57 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
58 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ 58 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
59 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ 59 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
60 60
61 #define CR_MONO (0x0 << 4) 61 #define CR_MONO (0x0 << 4)
62 #define CR_MONO_D (0x1 << 4) 62 #define CR_MONO_D (0x1 << 4)
63 #define CR_PCM (0x2 << 4) 63 #define CR_PCM (0x2 << 4)
64 #define CR_I2S (0x3 << 4) 64 #define CR_I2S (0x3 << 4)
65 #define CR_TDM (0x4 << 4) 65 #define CR_TDM (0x4 << 4)
66 #define CR_TDM_D (0x5 << 4) 66 #define CR_TDM_D (0x5 << 4)
67 67
68 /* DOFF_CTL */ 68 /* DOFF_CTL */
69 /* DIFF_CTL */ 69 /* DIFF_CTL */
70 #define IRQ_HALF 0x00100000 70 #define IRQ_HALF 0x00100000
71 #define FIFO_CLR 0x00000001 71 #define FIFO_CLR 0x00000001
72 72
73 /* DOFF_ST */ 73 /* DOFF_ST */
74 #define ERR_OVER 0x00000010 74 #define ERR_OVER 0x00000010
75 #define ERR_UNDER 0x00000001 75 #define ERR_UNDER 0x00000001
76 #define ST_ERR (ERR_OVER | ERR_UNDER) 76 #define ST_ERR (ERR_OVER | ERR_UNDER)
77 77
78 /* CKG1 */ 78 /* CKG1 */
79 #define ACKMD_MASK 0x00007000 79 #define ACKMD_MASK 0x00007000
80 #define BPFMD_MASK 0x00000700 80 #define BPFMD_MASK 0x00000700
81 #define DIMD (1 << 4) 81 #define DIMD (1 << 4)
82 #define DOMD (1 << 0) 82 #define DOMD (1 << 0)
83 83
84 /* A/B MST_CTLR */ 84 /* A/B MST_CTLR */
85 #define BP (1 << 4) /* Fix the signal of Biphase output */ 85 #define BP (1 << 4) /* Fix the signal of Biphase output */
86 #define SE (1 << 0) /* Fix the master clock */ 86 #define SE (1 << 0) /* Fix the master clock */
87 87
88 /* CLK_RST */ 88 /* CLK_RST */
89 #define B_CLK 0x00000010 89 #define B_CLK 0x00000010
90 #define A_CLK 0x00000001 90 #define A_CLK 0x00000001
91 91
92 /* IO SHIFT / MACRO */ 92 /* IO SHIFT / MACRO */
93 #define BI_SHIFT 12 93 #define BI_SHIFT 12
94 #define BO_SHIFT 8 94 #define BO_SHIFT 8
95 #define AI_SHIFT 4 95 #define AI_SHIFT 4
96 #define AO_SHIFT 0 96 #define AO_SHIFT 0
97 #define AB_IO(param, shift) (param << shift) 97 #define AB_IO(param, shift) (param << shift)
98 98
99 /* SOFT_RST */ 99 /* SOFT_RST */
100 #define PBSR (1 << 12) /* Port B Software Reset */ 100 #define PBSR (1 << 12) /* Port B Software Reset */
101 #define PASR (1 << 8) /* Port A Software Reset */ 101 #define PASR (1 << 8) /* Port A Software Reset */
102 #define IR (1 << 4) /* Interrupt Reset */ 102 #define IR (1 << 4) /* Interrupt Reset */
103 #define FSISR (1 << 0) /* Software Reset */ 103 #define FSISR (1 << 0) /* Software Reset */
104 104
105 /* OUT_SEL (FSI2) */ 105 /* OUT_SEL (FSI2) */
106 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ 106 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
107 /* 1: Biphase and serial */ 107 /* 1: Biphase and serial */
108 108
109 /* FIFO_SZ */ 109 /* FIFO_SZ */
110 #define FIFO_SZ_MASK 0x7 110 #define FIFO_SZ_MASK 0x7
111 111
112 #define FSI_RATES SNDRV_PCM_RATE_8000_96000 112 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
113 113
114 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) 114 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
115 115
116 typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable); 116 typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable);
117 117
118 /* 118 /*
119 * FSI driver use below type name for variable 119 * FSI driver use below type name for variable
120 * 120 *
121 * xxx_len : data length 121 * xxx_len : data length
122 * xxx_width : data width 122 * xxx_width : data width
123 * xxx_offset : data offset 123 * xxx_offset : data offset
124 * xxx_num : number of data 124 * xxx_num : number of data
125 */ 125 */
126 126
127 /* 127 /*
128 * struct 128 * struct
129 */ 129 */
130 130
131 struct fsi_stream { 131 struct fsi_stream {
132 struct snd_pcm_substream *substream; 132 struct snd_pcm_substream *substream;
133 133
134 int fifo_max_num; 134 int fifo_max_num;
135 135
136 int buff_offset; 136 int buff_offset;
137 int buff_len; 137 int buff_len;
138 int period_len; 138 int period_len;
139 int period_num; 139 int period_num;
140 140
141 int uerr_num; 141 int uerr_num;
142 int oerr_num; 142 int oerr_num;
143 }; 143 };
144 144
145 struct fsi_priv { 145 struct fsi_priv {
146 void __iomem *base; 146 void __iomem *base;
147 struct fsi_master *master; 147 struct fsi_master *master;
148 148
149 int chan_num; 149 int chan_num;
150 struct fsi_stream playback; 150 struct fsi_stream playback;
151 struct fsi_stream capture; 151 struct fsi_stream capture;
152 152
153 long rate; 153 long rate;
154 }; 154 };
155 155
156 struct fsi_core { 156 struct fsi_core {
157 int ver; 157 int ver;
158 158
159 u32 int_st; 159 u32 int_st;
160 u32 iemsk; 160 u32 iemsk;
161 u32 imsk; 161 u32 imsk;
162 u32 a_mclk; 162 u32 a_mclk;
163 u32 b_mclk; 163 u32 b_mclk;
164 }; 164 };
165 165
166 struct fsi_master { 166 struct fsi_master {
167 void __iomem *base; 167 void __iomem *base;
168 int irq; 168 int irq;
169 struct fsi_priv fsia; 169 struct fsi_priv fsia;
170 struct fsi_priv fsib; 170 struct fsi_priv fsib;
171 struct fsi_core *core; 171 struct fsi_core *core;
172 struct sh_fsi_platform_info *info; 172 struct sh_fsi_platform_info *info;
173 spinlock_t lock; 173 spinlock_t lock;
174 }; 174 };
175 175
176 /* 176 /*
177 * basic read write function 177 * basic read write function
178 */ 178 */
179 179
180 static void __fsi_reg_write(u32 reg, u32 data) 180 static void __fsi_reg_write(u32 reg, u32 data)
181 { 181 {
182 /* valid data area is 24bit */ 182 /* valid data area is 24bit */
183 data &= 0x00ffffff; 183 data &= 0x00ffffff;
184 184
185 __raw_writel(data, reg); 185 __raw_writel(data, reg);
186 } 186 }
187 187
188 static u32 __fsi_reg_read(u32 reg) 188 static u32 __fsi_reg_read(u32 reg)
189 { 189 {
190 return __raw_readl(reg); 190 return __raw_readl(reg);
191 } 191 }
192 192
193 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) 193 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
194 { 194 {
195 u32 val = __fsi_reg_read(reg); 195 u32 val = __fsi_reg_read(reg);
196 196
197 val &= ~mask; 197 val &= ~mask;
198 val |= data & mask; 198 val |= data & mask;
199 199
200 __fsi_reg_write(reg, val); 200 __fsi_reg_write(reg, val);
201 } 201 }
202 202
203 #define fsi_reg_write(p, r, d)\ 203 #define fsi_reg_write(p, r, d)\
204 __fsi_reg_write((u32)(p->base + REG_##r), d) 204 __fsi_reg_write((u32)(p->base + REG_##r), d)
205 205
206 #define fsi_reg_read(p, r)\ 206 #define fsi_reg_read(p, r)\
207 __fsi_reg_read((u32)(p->base + REG_##r)) 207 __fsi_reg_read((u32)(p->base + REG_##r))
208 208
209 #define fsi_reg_mask_set(p, r, m, d)\ 209 #define fsi_reg_mask_set(p, r, m, d)\
210 __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d) 210 __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d)
211 211
212 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) 212 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
213 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) 213 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
214 static u32 _fsi_master_read(struct fsi_master *master, u32 reg) 214 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
215 { 215 {
216 u32 ret; 216 u32 ret;
217 unsigned long flags; 217 unsigned long flags;
218 218
219 spin_lock_irqsave(&master->lock, flags); 219 spin_lock_irqsave(&master->lock, flags);
220 ret = __fsi_reg_read((u32)(master->base + reg)); 220 ret = __fsi_reg_read((u32)(master->base + reg));
221 spin_unlock_irqrestore(&master->lock, flags); 221 spin_unlock_irqrestore(&master->lock, flags);
222 222
223 return ret; 223 return ret;
224 } 224 }
225 225
226 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) 226 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
227 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) 227 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
228 static void _fsi_master_mask_set(struct fsi_master *master, 228 static void _fsi_master_mask_set(struct fsi_master *master,
229 u32 reg, u32 mask, u32 data) 229 u32 reg, u32 mask, u32 data)
230 { 230 {
231 unsigned long flags; 231 unsigned long flags;
232 232
233 spin_lock_irqsave(&master->lock, flags); 233 spin_lock_irqsave(&master->lock, flags);
234 __fsi_reg_mask_set((u32)(master->base + reg), mask, data); 234 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
235 spin_unlock_irqrestore(&master->lock, flags); 235 spin_unlock_irqrestore(&master->lock, flags);
236 } 236 }
237 237
238 /* 238 /*
239 * basic function 239 * basic function
240 */ 240 */
241 241
242 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) 242 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
243 { 243 {
244 return fsi->master; 244 return fsi->master;
245 } 245 }
246 246
247 static int fsi_is_port_a(struct fsi_priv *fsi) 247 static int fsi_is_port_a(struct fsi_priv *fsi)
248 { 248 {
249 return fsi->master->base == fsi->base; 249 return fsi->master->base == fsi->base;
250 } 250 }
251 251
252 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) 252 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
253 { 253 {
254 struct snd_soc_pcm_runtime *rtd = substream->private_data; 254 struct snd_soc_pcm_runtime *rtd = substream->private_data;
255 255
256 return rtd->cpu_dai; 256 return rtd->cpu_dai;
257 } 257 }
258 258
259 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) 259 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
260 { 260 {
261 struct fsi_master *master = snd_soc_dai_get_drvdata(dai); 261 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
262 262
263 if (dai->id == 0) 263 if (dai->id == 0)
264 return &master->fsia; 264 return &master->fsia;
265 else 265 else
266 return &master->fsib; 266 return &master->fsib;
267 } 267 }
268 268
269 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) 269 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
270 { 270 {
271 return fsi_get_priv_frm_dai(fsi_get_dai(substream)); 271 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
272 } 272 }
273 273
274 static set_rate_func fsi_get_info_set_rate(struct fsi_master *master) 274 static set_rate_func fsi_get_info_set_rate(struct fsi_master *master)
275 { 275 {
276 if (!master->info) 276 if (!master->info)
277 return NULL; 277 return NULL;
278 278
279 return master->info->set_rate; 279 return master->info->set_rate;
280 } 280 }
281 281
282 static u32 fsi_get_info_flags(struct fsi_priv *fsi) 282 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
283 { 283 {
284 int is_porta = fsi_is_port_a(fsi); 284 int is_porta = fsi_is_port_a(fsi);
285 struct fsi_master *master = fsi_get_master(fsi); 285 struct fsi_master *master = fsi_get_master(fsi);
286 286
287 if (!master->info) 287 if (!master->info)
288 return 0; 288 return 0;
289 289
290 return is_porta ? master->info->porta_flags : 290 return is_porta ? master->info->porta_flags :
291 master->info->portb_flags; 291 master->info->portb_flags;
292 } 292 }
293 293
294 static inline int fsi_stream_is_play(int stream) 294 static inline int fsi_stream_is_play(int stream)
295 { 295 {
296 return stream == SNDRV_PCM_STREAM_PLAYBACK; 296 return stream == SNDRV_PCM_STREAM_PLAYBACK;
297 } 297 }
298 298
299 static inline int fsi_is_play(struct snd_pcm_substream *substream) 299 static inline int fsi_is_play(struct snd_pcm_substream *substream)
300 { 300 {
301 return fsi_stream_is_play(substream->stream); 301 return fsi_stream_is_play(substream->stream);
302 } 302 }
303 303
304 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi, 304 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
305 int is_play) 305 int is_play)
306 { 306 {
307 return is_play ? &fsi->playback : &fsi->capture; 307 return is_play ? &fsi->playback : &fsi->capture;
308 } 308 }
309 309
310 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) 310 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
311 { 311 {
312 int is_porta = fsi_is_port_a(fsi); 312 int is_porta = fsi_is_port_a(fsi);
313 u32 shift; 313 u32 shift;
314 314
315 if (is_porta) 315 if (is_porta)
316 shift = is_play ? AO_SHIFT : AI_SHIFT; 316 shift = is_play ? AO_SHIFT : AI_SHIFT;
317 else 317 else
318 shift = is_play ? BO_SHIFT : BI_SHIFT; 318 shift = is_play ? BO_SHIFT : BI_SHIFT;
319 319
320 return shift; 320 return shift;
321 } 321 }
322 322
323 static void fsi_stream_push(struct fsi_priv *fsi, 323 static void fsi_stream_push(struct fsi_priv *fsi,
324 int is_play, 324 int is_play,
325 struct snd_pcm_substream *substream, 325 struct snd_pcm_substream *substream,
326 u32 buffer_len, 326 u32 buffer_len,
327 u32 period_len) 327 u32 period_len)
328 { 328 {
329 struct fsi_stream *io = fsi_get_stream(fsi, is_play); 329 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
330 330
331 io->substream = substream; 331 io->substream = substream;
332 io->buff_len = buffer_len; 332 io->buff_len = buffer_len;
333 io->buff_offset = 0; 333 io->buff_offset = 0;
334 io->period_len = period_len; 334 io->period_len = period_len;
335 io->period_num = 0; 335 io->period_num = 0;
336 io->oerr_num = -1; /* ignore 1st err */ 336 io->oerr_num = -1; /* ignore 1st err */
337 io->uerr_num = -1; /* ignore 1st err */ 337 io->uerr_num = -1; /* ignore 1st err */
338 } 338 }
339 339
340 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) 340 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
341 { 341 {
342 struct fsi_stream *io = fsi_get_stream(fsi, is_play); 342 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
343 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 343 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
344 344
345 345
346 if (io->oerr_num > 0) 346 if (io->oerr_num > 0)
347 dev_err(dai->dev, "over_run = %d\n", io->oerr_num); 347 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
348 348
349 if (io->uerr_num > 0) 349 if (io->uerr_num > 0)
350 dev_err(dai->dev, "under_run = %d\n", io->uerr_num); 350 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
351 351
352 io->substream = NULL; 352 io->substream = NULL;
353 io->buff_len = 0; 353 io->buff_len = 0;
354 io->buff_offset = 0; 354 io->buff_offset = 0;
355 io->period_len = 0; 355 io->period_len = 0;
356 io->period_num = 0; 356 io->period_num = 0;
357 io->oerr_num = 0; 357 io->oerr_num = 0;
358 io->uerr_num = 0; 358 io->uerr_num = 0;
359 } 359 }
360 360
361 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play) 361 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
362 { 362 {
363 u32 status; 363 u32 status;
364 int data_num; 364 int data_num;
365 365
366 status = is_play ? 366 status = is_play ?
367 fsi_reg_read(fsi, DOFF_ST) : 367 fsi_reg_read(fsi, DOFF_ST) :
368 fsi_reg_read(fsi, DIFF_ST); 368 fsi_reg_read(fsi, DIFF_ST);
369 369
370 data_num = 0x1ff & (status >> 8); 370 data_num = 0x1ff & (status >> 8);
371 data_num *= fsi->chan_num; 371 data_num *= fsi->chan_num;
372 372
373 return data_num; 373 return data_num;
374 } 374 }
375 375
376 static int fsi_len2num(int len, int width) 376 static int fsi_len2num(int len, int width)
377 { 377 {
378 return len / width; 378 return len / width;
379 } 379 }
380 380
381 #define fsi_num2offset(a, b) fsi_num2len(a, b) 381 #define fsi_num2offset(a, b) fsi_num2len(a, b)
382 static int fsi_num2len(int num, int width) 382 static int fsi_num2len(int num, int width)
383 { 383 {
384 return num * width; 384 return num * width;
385 } 385 }
386 386
387 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play) 387 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play)
388 { 388 {
389 struct fsi_stream *io = fsi_get_stream(fsi, is_play); 389 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
390 struct snd_pcm_substream *substream = io->substream; 390 struct snd_pcm_substream *substream = io->substream;
391 struct snd_pcm_runtime *runtime = substream->runtime; 391 struct snd_pcm_runtime *runtime = substream->runtime;
392 392
393 return frames_to_bytes(runtime, 1) / fsi->chan_num; 393 return frames_to_bytes(runtime, 1) / fsi->chan_num;
394 } 394 }
395 395
396 static void fsi_count_fifo_err(struct fsi_priv *fsi) 396 static void fsi_count_fifo_err(struct fsi_priv *fsi)
397 { 397 {
398 u32 ostatus = fsi_reg_read(fsi, DOFF_ST); 398 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
399 u32 istatus = fsi_reg_read(fsi, DIFF_ST); 399 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
400 400
401 if (ostatus & ERR_OVER) 401 if (ostatus & ERR_OVER)
402 fsi->playback.oerr_num++; 402 fsi->playback.oerr_num++;
403 403
404 if (ostatus & ERR_UNDER) 404 if (ostatus & ERR_UNDER)
405 fsi->playback.uerr_num++; 405 fsi->playback.uerr_num++;
406 406
407 if (istatus & ERR_OVER) 407 if (istatus & ERR_OVER)
408 fsi->capture.oerr_num++; 408 fsi->capture.oerr_num++;
409 409
410 if (istatus & ERR_UNDER) 410 if (istatus & ERR_UNDER)
411 fsi->capture.uerr_num++; 411 fsi->capture.uerr_num++;
412 412
413 fsi_reg_write(fsi, DOFF_ST, 0); 413 fsi_reg_write(fsi, DOFF_ST, 0);
414 fsi_reg_write(fsi, DIFF_ST, 0); 414 fsi_reg_write(fsi, DIFF_ST, 0);
415 } 415 }
416 416
417 /* 417 /*
418 * dma function 418 * dma function
419 */ 419 */
420 420
421 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream) 421 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
422 { 422 {
423 int is_play = fsi_stream_is_play(stream); 423 int is_play = fsi_stream_is_play(stream);
424 struct fsi_stream *io = fsi_get_stream(fsi, is_play); 424 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
425 425
426 return io->substream->runtime->dma_area + io->buff_offset; 426 return io->substream->runtime->dma_area + io->buff_offset;
427 } 427 }
428 428
429 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num) 429 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
430 { 430 {
431 u16 *start; 431 u16 *start;
432 int i; 432 int i;
433 433
434 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); 434 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
435 435
436 for (i = 0; i < num; i++) 436 for (i = 0; i < num; i++)
437 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8)); 437 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
438 } 438 }
439 439
440 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num) 440 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
441 { 441 {
442 u16 *start; 442 u16 *start;
443 int i; 443 int i;
444 444
445 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); 445 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
446 446
447 447
448 for (i = 0; i < num; i++) 448 for (i = 0; i < num; i++)
449 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); 449 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
450 } 450 }
451 451
452 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num) 452 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
453 { 453 {
454 u32 *start; 454 u32 *start;
455 int i; 455 int i;
456 456
457 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); 457 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
458 458
459 459
460 for (i = 0; i < num; i++) 460 for (i = 0; i < num; i++)
461 fsi_reg_write(fsi, DODT, *(start + i)); 461 fsi_reg_write(fsi, DODT, *(start + i));
462 } 462 }
463 463
464 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num) 464 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
465 { 465 {
466 u32 *start; 466 u32 *start;
467 int i; 467 int i;
468 468
469 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); 469 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
470 470
471 for (i = 0; i < num; i++) 471 for (i = 0; i < num; i++)
472 *(start + i) = fsi_reg_read(fsi, DIDT); 472 *(start + i) = fsi_reg_read(fsi, DIDT);
473 } 473 }
474 474
475 /* 475 /*
476 * irq function 476 * irq function
477 */ 477 */
478 478
479 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) 479 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
480 { 480 {
481 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); 481 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
482 struct fsi_master *master = fsi_get_master(fsi); 482 struct fsi_master *master = fsi_get_master(fsi);
483 483
484 fsi_core_mask_set(master, imsk, data, data); 484 fsi_core_mask_set(master, imsk, data, data);
485 fsi_core_mask_set(master, iemsk, data, data); 485 fsi_core_mask_set(master, iemsk, data, data);
486 } 486 }
487 487
488 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) 488 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
489 { 489 {
490 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); 490 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
491 struct fsi_master *master = fsi_get_master(fsi); 491 struct fsi_master *master = fsi_get_master(fsi);
492 492
493 fsi_core_mask_set(master, imsk, data, 0); 493 fsi_core_mask_set(master, imsk, data, 0);
494 fsi_core_mask_set(master, iemsk, data, 0); 494 fsi_core_mask_set(master, iemsk, data, 0);
495 } 495 }
496 496
497 static u32 fsi_irq_get_status(struct fsi_master *master) 497 static u32 fsi_irq_get_status(struct fsi_master *master)
498 { 498 {
499 return fsi_core_read(master, int_st); 499 return fsi_core_read(master, int_st);
500 } 500 }
501 501
502 static void fsi_irq_clear_status(struct fsi_priv *fsi) 502 static void fsi_irq_clear_status(struct fsi_priv *fsi)
503 { 503 {
504 u32 data = 0; 504 u32 data = 0;
505 struct fsi_master *master = fsi_get_master(fsi); 505 struct fsi_master *master = fsi_get_master(fsi);
506 506
507 data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); 507 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
508 data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); 508 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
509 509
510 /* clear interrupt factor */ 510 /* clear interrupt factor */
511 fsi_core_mask_set(master, int_st, data, 0); 511 fsi_core_mask_set(master, int_st, data, 0);
512 } 512 }
513 513
514 /* 514 /*
515 * SPDIF master clock function 515 * SPDIF master clock function
516 * 516 *
517 * These functions are used later FSI2 517 * These functions are used later FSI2
518 */ 518 */
519 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) 519 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
520 { 520 {
521 struct fsi_master *master = fsi_get_master(fsi); 521 struct fsi_master *master = fsi_get_master(fsi);
522 u32 mask, val; 522 u32 mask, val;
523 523
524 if (master->core->ver < 2) { 524 if (master->core->ver < 2) {
525 pr_err("fsi: register access err (%s)\n", __func__); 525 pr_err("fsi: register access err (%s)\n", __func__);
526 return; 526 return;
527 } 527 }
528 528
529 mask = BP | SE; 529 mask = BP | SE;
530 val = enable ? mask : 0; 530 val = enable ? mask : 0;
531 531
532 fsi_is_port_a(fsi) ? 532 fsi_is_port_a(fsi) ?
533 fsi_core_mask_set(master, a_mclk, mask, val) : 533 fsi_core_mask_set(master, a_mclk, mask, val) :
534 fsi_core_mask_set(master, b_mclk, mask, val); 534 fsi_core_mask_set(master, b_mclk, mask, val);
535 } 535 }
536 536
537 /* 537 /*
538 * ctrl function 538 * ctrl function
539 */ 539 */
540 540
541 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) 541 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
542 { 542 {
543 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); 543 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
544 struct fsi_master *master = fsi_get_master(fsi); 544 struct fsi_master *master = fsi_get_master(fsi);
545 545
546 if (enable) 546 if (enable)
547 fsi_master_mask_set(master, CLK_RST, val, val); 547 fsi_master_mask_set(master, CLK_RST, val, val);
548 else 548 else
549 fsi_master_mask_set(master, CLK_RST, val, 0); 549 fsi_master_mask_set(master, CLK_RST, val, 0);
550 } 550 }
551 551
552 static void fsi_fifo_init(struct fsi_priv *fsi, 552 static void fsi_fifo_init(struct fsi_priv *fsi,
553 int is_play, 553 int is_play,
554 struct snd_soc_dai *dai) 554 struct snd_soc_dai *dai)
555 { 555 {
556 struct fsi_master *master = fsi_get_master(fsi); 556 struct fsi_master *master = fsi_get_master(fsi);
557 struct fsi_stream *io = fsi_get_stream(fsi, is_play); 557 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
558 u32 shift, i; 558 u32 shift, i;
559 559
560 /* get on-chip RAM capacity */ 560 /* get on-chip RAM capacity */
561 shift = fsi_master_read(master, FIFO_SZ); 561 shift = fsi_master_read(master, FIFO_SZ);
562 shift >>= fsi_get_port_shift(fsi, is_play); 562 shift >>= fsi_get_port_shift(fsi, is_play);
563 shift &= FIFO_SZ_MASK; 563 shift &= FIFO_SZ_MASK;
564 io->fifo_max_num = 256 << shift; 564 io->fifo_max_num = 256 << shift;
565 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num); 565 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num);
566 566
567 /* 567 /*
568 * The maximum number of sample data varies depending 568 * The maximum number of sample data varies depending
569 * on the number of channels selected for the format. 569 * on the number of channels selected for the format.
570 * 570 *
571 * FIFOs are used in 4-channel units in 3-channel mode 571 * FIFOs are used in 4-channel units in 3-channel mode
572 * and in 8-channel units in 5- to 7-channel mode 572 * and in 8-channel units in 5- to 7-channel mode
573 * meaning that more FIFOs than the required size of DPRAM 573 * meaning that more FIFOs than the required size of DPRAM
574 * are used. 574 * are used.
575 * 575 *
576 * ex) if 256 words of DP-RAM is connected 576 * ex) if 256 words of DP-RAM is connected
577 * 1 channel: 256 (256 x 1 = 256) 577 * 1 channel: 256 (256 x 1 = 256)
578 * 2 channels: 128 (128 x 2 = 256) 578 * 2 channels: 128 (128 x 2 = 256)
579 * 3 channels: 64 ( 64 x 3 = 192) 579 * 3 channels: 64 ( 64 x 3 = 192)
580 * 4 channels: 64 ( 64 x 4 = 256) 580 * 4 channels: 64 ( 64 x 4 = 256)
581 * 5 channels: 32 ( 32 x 5 = 160) 581 * 5 channels: 32 ( 32 x 5 = 160)
582 * 6 channels: 32 ( 32 x 6 = 192) 582 * 6 channels: 32 ( 32 x 6 = 192)
583 * 7 channels: 32 ( 32 x 7 = 224) 583 * 7 channels: 32 ( 32 x 7 = 224)
584 * 8 channels: 32 ( 32 x 8 = 256) 584 * 8 channels: 32 ( 32 x 8 = 256)
585 */ 585 */
586 for (i = 1; i < fsi->chan_num; i <<= 1) 586 for (i = 1; i < fsi->chan_num; i <<= 1)
587 io->fifo_max_num >>= 1; 587 io->fifo_max_num >>= 1;
588 dev_dbg(dai->dev, "%d channel %d store\n", 588 dev_dbg(dai->dev, "%d channel %d store\n",
589 fsi->chan_num, io->fifo_max_num); 589 fsi->chan_num, io->fifo_max_num);
590 590
591 /* 591 /*
592 * set interrupt generation factor 592 * set interrupt generation factor
593 * clear FIFO 593 * clear FIFO
594 */ 594 */
595 if (is_play) { 595 if (is_play) {
596 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); 596 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
597 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); 597 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
598 } else { 598 } else {
599 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); 599 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
600 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 600 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
601 } 601 }
602 } 602 }
603 603
604 static void fsi_soft_all_reset(struct fsi_master *master) 604 static void fsi_soft_all_reset(struct fsi_master *master)
605 { 605 {
606 /* port AB reset */ 606 /* port AB reset */
607 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0); 607 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
608 mdelay(10); 608 mdelay(10);
609 609
610 /* soft reset */ 610 /* soft reset */
611 fsi_master_mask_set(master, SOFT_RST, FSISR, 0); 611 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
612 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR); 612 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
613 mdelay(10); 613 mdelay(10);
614 } 614 }
615 615
616 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream) 616 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream)
617 { 617 {
618 struct snd_pcm_runtime *runtime; 618 struct snd_pcm_runtime *runtime;
619 struct snd_pcm_substream *substream = NULL; 619 struct snd_pcm_substream *substream = NULL;
620 int is_play = fsi_stream_is_play(stream); 620 int is_play = fsi_stream_is_play(stream);
621 struct fsi_stream *io = fsi_get_stream(fsi, is_play); 621 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
622 int data_residue_num; 622 int data_residue_num;
623 int data_num; 623 int data_num;
624 int data_num_max; 624 int data_num_max;
625 int ch_width; 625 int ch_width;
626 int over_period; 626 int over_period;
627 void (*fn)(struct fsi_priv *fsi, int size); 627 void (*fn)(struct fsi_priv *fsi, int size);
628 628
629 if (!fsi || 629 if (!fsi ||
630 !io->substream || 630 !io->substream ||
631 !io->substream->runtime) 631 !io->substream->runtime)
632 return -EINVAL; 632 return -EINVAL;
633 633
634 over_period = 0; 634 over_period = 0;
635 substream = io->substream; 635 substream = io->substream;
636 runtime = substream->runtime; 636 runtime = substream->runtime;
637 637
638 /* FSI FIFO has limit. 638 /* FSI FIFO has limit.
639 * So, this driver can not send periods data at a time 639 * So, this driver can not send periods data at a time
640 */ 640 */
641 if (io->buff_offset >= 641 if (io->buff_offset >=
642 fsi_num2offset(io->period_num + 1, io->period_len)) { 642 fsi_num2offset(io->period_num + 1, io->period_len)) {
643 643
644 over_period = 1; 644 over_period = 1;
645 io->period_num = (io->period_num + 1) % runtime->periods; 645 io->period_num = (io->period_num + 1) % runtime->periods;
646 646
647 if (0 == io->period_num) 647 if (0 == io->period_num)
648 io->buff_offset = 0; 648 io->buff_offset = 0;
649 } 649 }
650 650
651 /* get 1 channel data width */ 651 /* get 1 channel data width */
652 ch_width = fsi_get_frame_width(fsi, is_play); 652 ch_width = fsi_get_frame_width(fsi, is_play);
653 653
654 /* get residue data number of alsa */ 654 /* get residue data number of alsa */
655 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset, 655 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset,
656 ch_width); 656 ch_width);
657 657
658 if (is_play) { 658 if (is_play) {
659 /* 659 /*
660 * for play-back 660 * for play-back
661 * 661 *
662 * data_num_max : number of FSI fifo free space 662 * data_num_max : number of FSI fifo free space
663 * data_num : number of ALSA residue data 663 * data_num : number of ALSA residue data
664 */ 664 */
665 data_num_max = io->fifo_max_num * fsi->chan_num; 665 data_num_max = io->fifo_max_num * fsi->chan_num;
666 data_num_max -= fsi_get_fifo_data_num(fsi, is_play); 666 data_num_max -= fsi_get_fifo_data_num(fsi, is_play);
667 667
668 data_num = data_residue_num; 668 data_num = data_residue_num;
669 669
670 switch (ch_width) { 670 switch (ch_width) {
671 case 2: 671 case 2:
672 fn = fsi_dma_soft_push16; 672 fn = fsi_dma_soft_push16;
673 break; 673 break;
674 case 4: 674 case 4:
675 fn = fsi_dma_soft_push32; 675 fn = fsi_dma_soft_push32;
676 break; 676 break;
677 default: 677 default:
678 return -EINVAL; 678 return -EINVAL;
679 } 679 }
680 } else { 680 } else {
681 /* 681 /*
682 * for capture 682 * for capture
683 * 683 *
684 * data_num_max : number of ALSA free space 684 * data_num_max : number of ALSA free space
685 * data_num : number of data in FSI fifo 685 * data_num : number of data in FSI fifo
686 */ 686 */
687 data_num_max = data_residue_num; 687 data_num_max = data_residue_num;
688 data_num = fsi_get_fifo_data_num(fsi, is_play); 688 data_num = fsi_get_fifo_data_num(fsi, is_play);
689 689
690 switch (ch_width) { 690 switch (ch_width) {
691 case 2: 691 case 2:
692 fn = fsi_dma_soft_pop16; 692 fn = fsi_dma_soft_pop16;
693 break; 693 break;
694 case 4: 694 case 4:
695 fn = fsi_dma_soft_pop32; 695 fn = fsi_dma_soft_pop32;
696 break; 696 break;
697 default: 697 default:
698 return -EINVAL; 698 return -EINVAL;
699 } 699 }
700 } 700 }
701 701
702 data_num = min(data_num, data_num_max); 702 data_num = min(data_num, data_num_max);
703 703
704 fn(fsi, data_num); 704 fn(fsi, data_num);
705 705
706 /* update buff_offset */ 706 /* update buff_offset */
707 io->buff_offset += fsi_num2offset(data_num, ch_width); 707 io->buff_offset += fsi_num2offset(data_num, ch_width);
708 708
709 if (over_period) 709 if (over_period)
710 snd_pcm_period_elapsed(substream); 710 snd_pcm_period_elapsed(substream);
711 711
712 return 0; 712 return 0;
713 } 713 }
714 714
715 static int fsi_data_pop(struct fsi_priv *fsi) 715 static int fsi_data_pop(struct fsi_priv *fsi)
716 { 716 {
717 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE); 717 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE);
718 } 718 }
719 719
720 static int fsi_data_push(struct fsi_priv *fsi) 720 static int fsi_data_push(struct fsi_priv *fsi)
721 { 721 {
722 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK); 722 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK);
723 } 723 }
724 724
725 static irqreturn_t fsi_interrupt(int irq, void *data) 725 static irqreturn_t fsi_interrupt(int irq, void *data)
726 { 726 {
727 struct fsi_master *master = data; 727 struct fsi_master *master = data;
728 u32 int_st = fsi_irq_get_status(master); 728 u32 int_st = fsi_irq_get_status(master);
729 729
730 /* clear irq status */ 730 /* clear irq status */
731 fsi_master_mask_set(master, SOFT_RST, IR, 0); 731 fsi_master_mask_set(master, SOFT_RST, IR, 0);
732 fsi_master_mask_set(master, SOFT_RST, IR, IR); 732 fsi_master_mask_set(master, SOFT_RST, IR, IR);
733 733
734 if (int_st & AB_IO(1, AO_SHIFT)) 734 if (int_st & AB_IO(1, AO_SHIFT))
735 fsi_data_push(&master->fsia); 735 fsi_data_push(&master->fsia);
736 if (int_st & AB_IO(1, BO_SHIFT)) 736 if (int_st & AB_IO(1, BO_SHIFT))
737 fsi_data_push(&master->fsib); 737 fsi_data_push(&master->fsib);
738 if (int_st & AB_IO(1, AI_SHIFT)) 738 if (int_st & AB_IO(1, AI_SHIFT))
739 fsi_data_pop(&master->fsia); 739 fsi_data_pop(&master->fsia);
740 if (int_st & AB_IO(1, BI_SHIFT)) 740 if (int_st & AB_IO(1, BI_SHIFT))
741 fsi_data_pop(&master->fsib); 741 fsi_data_pop(&master->fsib);
742 742
743 fsi_count_fifo_err(&master->fsia); 743 fsi_count_fifo_err(&master->fsia);
744 fsi_count_fifo_err(&master->fsib); 744 fsi_count_fifo_err(&master->fsib);
745 745
746 fsi_irq_clear_status(&master->fsia); 746 fsi_irq_clear_status(&master->fsia);
747 fsi_irq_clear_status(&master->fsib); 747 fsi_irq_clear_status(&master->fsib);
748 748
749 return IRQ_HANDLED; 749 return IRQ_HANDLED;
750 } 750 }
751 751
752 /* 752 /*
753 * dai ops 753 * dai ops
754 */ 754 */
755 755
756 static int fsi_dai_startup(struct snd_pcm_substream *substream, 756 static int fsi_dai_startup(struct snd_pcm_substream *substream,
757 struct snd_soc_dai *dai) 757 struct snd_soc_dai *dai)
758 { 758 {
759 struct fsi_priv *fsi = fsi_get_priv(substream); 759 struct fsi_priv *fsi = fsi_get_priv(substream);
760 struct fsi_master *master = fsi_get_master(fsi);
761 u32 flags = fsi_get_info_flags(fsi); 760 u32 flags = fsi_get_info_flags(fsi);
762 u32 fmt;
763 u32 data; 761 u32 data;
764 int is_play = fsi_is_play(substream); 762 int is_play = fsi_is_play(substream);
765 763
766 pm_runtime_get_sync(dai->dev); 764 pm_runtime_get_sync(dai->dev);
767 765
768 766
769 /* clock inversion (CKG2) */ 767 /* clock inversion (CKG2) */
770 data = 0; 768 data = 0;
771 if (SH_FSI_LRM_INV & flags) 769 if (SH_FSI_LRM_INV & flags)
772 data |= 1 << 12; 770 data |= 1 << 12;
773 if (SH_FSI_BRM_INV & flags) 771 if (SH_FSI_BRM_INV & flags)
774 data |= 1 << 8; 772 data |= 1 << 8;
775 if (SH_FSI_LRS_INV & flags) 773 if (SH_FSI_LRS_INV & flags)
776 data |= 1 << 4; 774 data |= 1 << 4;
777 if (SH_FSI_BRS_INV & flags) 775 if (SH_FSI_BRS_INV & flags)
778 data |= 1 << 0; 776 data |= 1 << 0;
779 777
780 fsi_reg_write(fsi, CKG2, data); 778 fsi_reg_write(fsi, CKG2, data);
781 779
782 /* do fmt, di fmt */
783 data = 0;
784 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
785 switch (fmt) {
786 case SH_FSI_FMT_MONO:
787 data = CR_MONO;
788 fsi->chan_num = 1;
789 break;
790 case SH_FSI_FMT_MONO_DELAY:
791 data = CR_MONO_D;
792 fsi->chan_num = 1;
793 break;
794 case SH_FSI_FMT_PCM:
795 data = CR_PCM;
796 fsi->chan_num = 2;
797 break;
798 case SH_FSI_FMT_I2S:
799 data = CR_I2S;
800 fsi->chan_num = 2;
801 break;
802 case SH_FSI_FMT_TDM:
803 fsi->chan_num = is_play ?
804 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
805 data = CR_TDM | (fsi->chan_num - 1);
806 break;
807 case SH_FSI_FMT_TDM_DELAY:
808 fsi->chan_num = is_play ?
809 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
810 data = CR_TDM_D | (fsi->chan_num - 1);
811 break;
812 case SH_FSI_FMT_SPDIF:
813 if (master->core->ver < 2) {
814 dev_err(dai->dev, "This FSI can not use SPDIF\n");
815 return -EINVAL;
816 }
817 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
818 fsi->chan_num = 2;
819 fsi_spdif_clk_ctrl(fsi, 1);
820 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
821 break;
822 default:
823 dev_err(dai->dev, "unknown format.\n");
824 return -EINVAL;
825 }
826 is_play ?
827 fsi_reg_write(fsi, DO_FMT, data) :
828 fsi_reg_write(fsi, DI_FMT, data);
829
830 /* irq clear */ 780 /* irq clear */
831 fsi_irq_disable(fsi, is_play); 781 fsi_irq_disable(fsi, is_play);
832 fsi_irq_clear_status(fsi); 782 fsi_irq_clear_status(fsi);
833 783
834 /* fifo init */ 784 /* fifo init */
835 fsi_fifo_init(fsi, is_play, dai); 785 fsi_fifo_init(fsi, is_play, dai);
836 786
837 return 0; 787 return 0;
838 } 788 }
839 789
840 static void fsi_dai_shutdown(struct snd_pcm_substream *substream, 790 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
841 struct snd_soc_dai *dai) 791 struct snd_soc_dai *dai)
842 { 792 {
843 struct fsi_priv *fsi = fsi_get_priv(substream); 793 struct fsi_priv *fsi = fsi_get_priv(substream);
844 int is_play = fsi_is_play(substream); 794 int is_play = fsi_is_play(substream);
845 struct fsi_master *master = fsi_get_master(fsi); 795 struct fsi_master *master = fsi_get_master(fsi);
846 set_rate_func set_rate; 796 set_rate_func set_rate;
847 797
848 fsi_irq_disable(fsi, is_play); 798 fsi_irq_disable(fsi, is_play);
849 fsi_clk_ctrl(fsi, 0); 799 fsi_clk_ctrl(fsi, 0);
850 800
851 set_rate = fsi_get_info_set_rate(master); 801 set_rate = fsi_get_info_set_rate(master);
852 if (set_rate && fsi->rate) 802 if (set_rate && fsi->rate)
853 set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0); 803 set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0);
854 fsi->rate = 0; 804 fsi->rate = 0;
855 805
856 pm_runtime_put_sync(dai->dev); 806 pm_runtime_put_sync(dai->dev);
857 } 807 }
858 808
859 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 809 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
860 struct snd_soc_dai *dai) 810 struct snd_soc_dai *dai)
861 { 811 {
862 struct fsi_priv *fsi = fsi_get_priv(substream); 812 struct fsi_priv *fsi = fsi_get_priv(substream);
863 struct snd_pcm_runtime *runtime = substream->runtime; 813 struct snd_pcm_runtime *runtime = substream->runtime;
864 int is_play = fsi_is_play(substream); 814 int is_play = fsi_is_play(substream);
865 int ret = 0; 815 int ret = 0;
866 816
867 switch (cmd) { 817 switch (cmd) {
868 case SNDRV_PCM_TRIGGER_START: 818 case SNDRV_PCM_TRIGGER_START:
869 fsi_stream_push(fsi, is_play, substream, 819 fsi_stream_push(fsi, is_play, substream,
870 frames_to_bytes(runtime, runtime->buffer_size), 820 frames_to_bytes(runtime, runtime->buffer_size),
871 frames_to_bytes(runtime, runtime->period_size)); 821 frames_to_bytes(runtime, runtime->period_size));
872 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi); 822 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi);
873 fsi_irq_enable(fsi, is_play); 823 fsi_irq_enable(fsi, is_play);
874 break; 824 break;
875 case SNDRV_PCM_TRIGGER_STOP: 825 case SNDRV_PCM_TRIGGER_STOP:
876 fsi_irq_disable(fsi, is_play); 826 fsi_irq_disable(fsi, is_play);
877 fsi_stream_pop(fsi, is_play); 827 fsi_stream_pop(fsi, is_play);
878 break; 828 break;
879 } 829 }
880 830
881 return ret; 831 return ret;
882 } 832 }
883 833
834 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
835 {
836 u32 data = 0;
837
838 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
839 case SND_SOC_DAIFMT_I2S:
840 data = CR_I2S;
841 fsi->chan_num = 2;
842 break;
843 case SND_SOC_DAIFMT_LEFT_J:
844 data = CR_PCM;
845 fsi->chan_num = 2;
846 break;
847 default:
848 return -EINVAL;
849 }
850
851 fsi_reg_write(fsi, DO_FMT, data);
852 fsi_reg_write(fsi, DI_FMT, data);
853
854 return 0;
855 }
856
857 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
858 {
859 struct fsi_master *master = fsi_get_master(fsi);
860 u32 data = 0;
861
862 if (master->core->ver < 2)
863 return -EINVAL;
864
865 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
866 fsi->chan_num = 2;
867 fsi_spdif_clk_ctrl(fsi, 1);
868 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
869
870 fsi_reg_write(fsi, DO_FMT, data);
871 fsi_reg_write(fsi, DI_FMT, data);
872
873 return 0;
874 }
875
884 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 876 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
885 { 877 {
886 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); 878 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
879 u32 flags = fsi_get_info_flags(fsi);
887 u32 data = 0; 880 u32 data = 0;
888 int ret; 881 int ret;
889 882
890 pm_runtime_get_sync(dai->dev); 883 pm_runtime_get_sync(dai->dev);
891 884
892 /* set master/slave audio interface */ 885 /* set master/slave audio interface */
893 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 886 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
894 case SND_SOC_DAIFMT_CBM_CFM: 887 case SND_SOC_DAIFMT_CBM_CFM:
895 data = DIMD | DOMD; 888 data = DIMD | DOMD;
896 break; 889 break;
897 case SND_SOC_DAIFMT_CBS_CFS: 890 case SND_SOC_DAIFMT_CBS_CFS:
898 break; 891 break;
899 default: 892 default:
900 ret = -EINVAL; 893 ret = -EINVAL;
901 goto set_fmt_exit; 894 goto set_fmt_exit;
902 } 895 }
903 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); 896 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
904 ret = 0; 897
898 /* set format */
899 switch (flags & SH_FSI_FMT_MASK) {
900 case SH_FSI_FMT_DAI:
901 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
902 break;
903 case SH_FSI_FMT_SPDIF:
904 ret = fsi_set_fmt_spdif(fsi);
905 break;
906 default:
907 ret = -EINVAL;
908 }
905 909
906 set_fmt_exit: 910 set_fmt_exit:
907 pm_runtime_put_sync(dai->dev); 911 pm_runtime_put_sync(dai->dev);
908 912
909 return ret; 913 return ret;
910 } 914 }
911 915
912 static int fsi_dai_hw_params(struct snd_pcm_substream *substream, 916 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
913 struct snd_pcm_hw_params *params, 917 struct snd_pcm_hw_params *params,
914 struct snd_soc_dai *dai) 918 struct snd_soc_dai *dai)
915 { 919 {
916 struct fsi_priv *fsi = fsi_get_priv(substream); 920 struct fsi_priv *fsi = fsi_get_priv(substream);
917 struct fsi_master *master = fsi_get_master(fsi); 921 struct fsi_master *master = fsi_get_master(fsi);
918 set_rate_func set_rate; 922 set_rate_func set_rate;
919 int fsi_ver = master->core->ver; 923 int fsi_ver = master->core->ver;
920 long rate = params_rate(params); 924 long rate = params_rate(params);
921 int ret; 925 int ret;
922 926
923 set_rate = fsi_get_info_set_rate(master); 927 set_rate = fsi_get_info_set_rate(master);
924 if (!set_rate) 928 if (!set_rate)
925 return 0; 929 return 0;
926 930
927 ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1); 931 ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1);
928 if (ret < 0) /* error */ 932 if (ret < 0) /* error */
929 return ret; 933 return ret;
930 934
931 fsi->rate = rate; 935 fsi->rate = rate;
932 if (ret > 0) { 936 if (ret > 0) {
933 u32 data = 0; 937 u32 data = 0;
934 938
935 switch (ret & SH_FSI_ACKMD_MASK) { 939 switch (ret & SH_FSI_ACKMD_MASK) {
936 default: 940 default:
937 /* FALL THROUGH */ 941 /* FALL THROUGH */
938 case SH_FSI_ACKMD_512: 942 case SH_FSI_ACKMD_512:
939 data |= (0x0 << 12); 943 data |= (0x0 << 12);
940 break; 944 break;
941 case SH_FSI_ACKMD_256: 945 case SH_FSI_ACKMD_256:
942 data |= (0x1 << 12); 946 data |= (0x1 << 12);
943 break; 947 break;
944 case SH_FSI_ACKMD_128: 948 case SH_FSI_ACKMD_128:
945 data |= (0x2 << 12); 949 data |= (0x2 << 12);
946 break; 950 break;
947 case SH_FSI_ACKMD_64: 951 case SH_FSI_ACKMD_64:
948 data |= (0x3 << 12); 952 data |= (0x3 << 12);
949 break; 953 break;
950 case SH_FSI_ACKMD_32: 954 case SH_FSI_ACKMD_32:
951 if (fsi_ver < 2) 955 if (fsi_ver < 2)
952 dev_err(dai->dev, "unsupported ACKMD\n"); 956 dev_err(dai->dev, "unsupported ACKMD\n");
953 else 957 else
954 data |= (0x4 << 12); 958 data |= (0x4 << 12);
955 break; 959 break;
956 } 960 }
957 961
958 switch (ret & SH_FSI_BPFMD_MASK) { 962 switch (ret & SH_FSI_BPFMD_MASK) {
959 default: 963 default:
960 /* FALL THROUGH */ 964 /* FALL THROUGH */
961 case SH_FSI_BPFMD_32: 965 case SH_FSI_BPFMD_32:
962 data |= (0x0 << 8); 966 data |= (0x0 << 8);
963 break; 967 break;
964 case SH_FSI_BPFMD_64: 968 case SH_FSI_BPFMD_64:
965 data |= (0x1 << 8); 969 data |= (0x1 << 8);
966 break; 970 break;
967 case SH_FSI_BPFMD_128: 971 case SH_FSI_BPFMD_128:
968 data |= (0x2 << 8); 972 data |= (0x2 << 8);
969 break; 973 break;
970 case SH_FSI_BPFMD_256: 974 case SH_FSI_BPFMD_256:
971 data |= (0x3 << 8); 975 data |= (0x3 << 8);
972 break; 976 break;
973 case SH_FSI_BPFMD_512: 977 case SH_FSI_BPFMD_512:
974 data |= (0x4 << 8); 978 data |= (0x4 << 8);
975 break; 979 break;
976 case SH_FSI_BPFMD_16: 980 case SH_FSI_BPFMD_16:
977 if (fsi_ver < 2) 981 if (fsi_ver < 2)
978 dev_err(dai->dev, "unsupported ACKMD\n"); 982 dev_err(dai->dev, "unsupported ACKMD\n");
979 else 983 else
980 data |= (0x7 << 8); 984 data |= (0x7 << 8);
981 break; 985 break;
982 } 986 }
983 987
984 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); 988 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
985 udelay(10); 989 udelay(10);
986 fsi_clk_ctrl(fsi, 1); 990 fsi_clk_ctrl(fsi, 1);
987 ret = 0; 991 ret = 0;
988 } 992 }
989 993
990 return ret; 994 return ret;
991 995
992 } 996 }
993 997
994 static struct snd_soc_dai_ops fsi_dai_ops = { 998 static struct snd_soc_dai_ops fsi_dai_ops = {
995 .startup = fsi_dai_startup, 999 .startup = fsi_dai_startup,
996 .shutdown = fsi_dai_shutdown, 1000 .shutdown = fsi_dai_shutdown,
997 .trigger = fsi_dai_trigger, 1001 .trigger = fsi_dai_trigger,
998 .set_fmt = fsi_dai_set_fmt, 1002 .set_fmt = fsi_dai_set_fmt,
999 .hw_params = fsi_dai_hw_params, 1003 .hw_params = fsi_dai_hw_params,
1000 }; 1004 };
1001 1005
1002 /* 1006 /*
1003 * pcm ops 1007 * pcm ops
1004 */ 1008 */
1005 1009
1006 static struct snd_pcm_hardware fsi_pcm_hardware = { 1010 static struct snd_pcm_hardware fsi_pcm_hardware = {
1007 .info = SNDRV_PCM_INFO_INTERLEAVED | 1011 .info = SNDRV_PCM_INFO_INTERLEAVED |
1008 SNDRV_PCM_INFO_MMAP | 1012 SNDRV_PCM_INFO_MMAP |
1009 SNDRV_PCM_INFO_MMAP_VALID | 1013 SNDRV_PCM_INFO_MMAP_VALID |
1010 SNDRV_PCM_INFO_PAUSE, 1014 SNDRV_PCM_INFO_PAUSE,
1011 .formats = FSI_FMTS, 1015 .formats = FSI_FMTS,
1012 .rates = FSI_RATES, 1016 .rates = FSI_RATES,
1013 .rate_min = 8000, 1017 .rate_min = 8000,
1014 .rate_max = 192000, 1018 .rate_max = 192000,
1015 .channels_min = 1, 1019 .channels_min = 1,
1016 .channels_max = 2, 1020 .channels_max = 2,
1017 .buffer_bytes_max = 64 * 1024, 1021 .buffer_bytes_max = 64 * 1024,
1018 .period_bytes_min = 32, 1022 .period_bytes_min = 32,
1019 .period_bytes_max = 8192, 1023 .period_bytes_max = 8192,
1020 .periods_min = 1, 1024 .periods_min = 1,
1021 .periods_max = 32, 1025 .periods_max = 32,
1022 .fifo_size = 256, 1026 .fifo_size = 256,
1023 }; 1027 };
1024 1028
1025 static int fsi_pcm_open(struct snd_pcm_substream *substream) 1029 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1026 { 1030 {
1027 struct snd_pcm_runtime *runtime = substream->runtime; 1031 struct snd_pcm_runtime *runtime = substream->runtime;
1028 int ret = 0; 1032 int ret = 0;
1029 1033
1030 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); 1034 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1031 1035
1032 ret = snd_pcm_hw_constraint_integer(runtime, 1036 ret = snd_pcm_hw_constraint_integer(runtime,
1033 SNDRV_PCM_HW_PARAM_PERIODS); 1037 SNDRV_PCM_HW_PARAM_PERIODS);
1034 1038
1035 return ret; 1039 return ret;
1036 } 1040 }
1037 1041
1038 static int fsi_hw_params(struct snd_pcm_substream *substream, 1042 static int fsi_hw_params(struct snd_pcm_substream *substream,
1039 struct snd_pcm_hw_params *hw_params) 1043 struct snd_pcm_hw_params *hw_params)
1040 { 1044 {
1041 return snd_pcm_lib_malloc_pages(substream, 1045 return snd_pcm_lib_malloc_pages(substream,
1042 params_buffer_bytes(hw_params)); 1046 params_buffer_bytes(hw_params));
1043 } 1047 }
1044 1048
1045 static int fsi_hw_free(struct snd_pcm_substream *substream) 1049 static int fsi_hw_free(struct snd_pcm_substream *substream)
1046 { 1050 {
1047 return snd_pcm_lib_free_pages(substream); 1051 return snd_pcm_lib_free_pages(substream);
1048 } 1052 }
1049 1053
1050 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) 1054 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1051 { 1055 {
1052 struct snd_pcm_runtime *runtime = substream->runtime; 1056 struct snd_pcm_runtime *runtime = substream->runtime;
1053 struct fsi_priv *fsi = fsi_get_priv(substream); 1057 struct fsi_priv *fsi = fsi_get_priv(substream);
1054 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream)); 1058 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1055 long location; 1059 long location;
1056 1060
1057 location = (io->buff_offset - 1); 1061 location = (io->buff_offset - 1);
1058 if (location < 0) 1062 if (location < 0)
1059 location = 0; 1063 location = 0;
1060 1064
1061 return bytes_to_frames(runtime, location); 1065 return bytes_to_frames(runtime, location);
1062 } 1066 }
1063 1067
1064 static struct snd_pcm_ops fsi_pcm_ops = { 1068 static struct snd_pcm_ops fsi_pcm_ops = {
1065 .open = fsi_pcm_open, 1069 .open = fsi_pcm_open,
1066 .ioctl = snd_pcm_lib_ioctl, 1070 .ioctl = snd_pcm_lib_ioctl,
1067 .hw_params = fsi_hw_params, 1071 .hw_params = fsi_hw_params,
1068 .hw_free = fsi_hw_free, 1072 .hw_free = fsi_hw_free,
1069 .pointer = fsi_pointer, 1073 .pointer = fsi_pointer,
1070 }; 1074 };
1071 1075
1072 /* 1076 /*
1073 * snd_soc_platform 1077 * snd_soc_platform
1074 */ 1078 */
1075 1079
1076 #define PREALLOC_BUFFER (32 * 1024) 1080 #define PREALLOC_BUFFER (32 * 1024)
1077 #define PREALLOC_BUFFER_MAX (32 * 1024) 1081 #define PREALLOC_BUFFER_MAX (32 * 1024)
1078 1082
1079 static void fsi_pcm_free(struct snd_pcm *pcm) 1083 static void fsi_pcm_free(struct snd_pcm *pcm)
1080 { 1084 {
1081 snd_pcm_lib_preallocate_free_for_all(pcm); 1085 snd_pcm_lib_preallocate_free_for_all(pcm);
1082 } 1086 }
1083 1087
1084 static int fsi_pcm_new(struct snd_card *card, 1088 static int fsi_pcm_new(struct snd_card *card,
1085 struct snd_soc_dai *dai, 1089 struct snd_soc_dai *dai,
1086 struct snd_pcm *pcm) 1090 struct snd_pcm *pcm)
1087 { 1091 {
1088 /* 1092 /*
1089 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel 1093 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1090 * in MMAP mode (i.e. aplay -M) 1094 * in MMAP mode (i.e. aplay -M)
1091 */ 1095 */
1092 return snd_pcm_lib_preallocate_pages_for_all( 1096 return snd_pcm_lib_preallocate_pages_for_all(
1093 pcm, 1097 pcm,
1094 SNDRV_DMA_TYPE_CONTINUOUS, 1098 SNDRV_DMA_TYPE_CONTINUOUS,
1095 snd_dma_continuous_data(GFP_KERNEL), 1099 snd_dma_continuous_data(GFP_KERNEL),
1096 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1100 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1097 } 1101 }
1098 1102
1099 /* 1103 /*
1100 * alsa struct 1104 * alsa struct
1101 */ 1105 */
1102 1106
1103 static struct snd_soc_dai_driver fsi_soc_dai[] = { 1107 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1104 { 1108 {
1105 .name = "fsia-dai", 1109 .name = "fsia-dai",
1106 .playback = { 1110 .playback = {
1107 .rates = FSI_RATES, 1111 .rates = FSI_RATES,
1108 .formats = FSI_FMTS, 1112 .formats = FSI_FMTS,
1109 .channels_min = 1, 1113 .channels_min = 1,
1110 .channels_max = 8, 1114 .channels_max = 8,
1111 }, 1115 },
1112 .capture = { 1116 .capture = {
1113 .rates = FSI_RATES, 1117 .rates = FSI_RATES,
1114 .formats = FSI_FMTS, 1118 .formats = FSI_FMTS,
1115 .channels_min = 1, 1119 .channels_min = 1,
1116 .channels_max = 8, 1120 .channels_max = 8,
1117 }, 1121 },
1118 .ops = &fsi_dai_ops, 1122 .ops = &fsi_dai_ops,
1119 }, 1123 },
1120 { 1124 {
1121 .name = "fsib-dai", 1125 .name = "fsib-dai",
1122 .playback = { 1126 .playback = {
1123 .rates = FSI_RATES, 1127 .rates = FSI_RATES,
1124 .formats = FSI_FMTS, 1128 .formats = FSI_FMTS,
1125 .channels_min = 1, 1129 .channels_min = 1,
1126 .channels_max = 8, 1130 .channels_max = 8,
1127 }, 1131 },
1128 .capture = { 1132 .capture = {
1129 .rates = FSI_RATES, 1133 .rates = FSI_RATES,
1130 .formats = FSI_FMTS, 1134 .formats = FSI_FMTS,
1131 .channels_min = 1, 1135 .channels_min = 1,
1132 .channels_max = 8, 1136 .channels_max = 8,
1133 }, 1137 },
1134 .ops = &fsi_dai_ops, 1138 .ops = &fsi_dai_ops,
1135 }, 1139 },
1136 }; 1140 };
1137 1141
1138 static struct snd_soc_platform_driver fsi_soc_platform = { 1142 static struct snd_soc_platform_driver fsi_soc_platform = {
1139 .ops = &fsi_pcm_ops, 1143 .ops = &fsi_pcm_ops,
1140 .pcm_new = fsi_pcm_new, 1144 .pcm_new = fsi_pcm_new,
1141 .pcm_free = fsi_pcm_free, 1145 .pcm_free = fsi_pcm_free,
1142 }; 1146 };
1143 1147
1144 /* 1148 /*
1145 * platform function 1149 * platform function
1146 */ 1150 */
1147 1151
1148 static int fsi_probe(struct platform_device *pdev) 1152 static int fsi_probe(struct platform_device *pdev)
1149 { 1153 {
1150 struct fsi_master *master; 1154 struct fsi_master *master;
1151 const struct platform_device_id *id_entry; 1155 const struct platform_device_id *id_entry;
1152 struct resource *res; 1156 struct resource *res;
1153 unsigned int irq; 1157 unsigned int irq;
1154 int ret; 1158 int ret;
1155 1159
1156 id_entry = pdev->id_entry; 1160 id_entry = pdev->id_entry;
1157 if (!id_entry) { 1161 if (!id_entry) {
1158 dev_err(&pdev->dev, "unknown fsi device\n"); 1162 dev_err(&pdev->dev, "unknown fsi device\n");
1159 return -ENODEV; 1163 return -ENODEV;
1160 } 1164 }
1161 1165
1162 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1166 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1163 irq = platform_get_irq(pdev, 0); 1167 irq = platform_get_irq(pdev, 0);
1164 if (!res || (int)irq <= 0) { 1168 if (!res || (int)irq <= 0) {
1165 dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); 1169 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1166 ret = -ENODEV; 1170 ret = -ENODEV;
1167 goto exit; 1171 goto exit;
1168 } 1172 }
1169 1173
1170 master = kzalloc(sizeof(*master), GFP_KERNEL); 1174 master = kzalloc(sizeof(*master), GFP_KERNEL);
1171 if (!master) { 1175 if (!master) {
1172 dev_err(&pdev->dev, "Could not allocate master\n"); 1176 dev_err(&pdev->dev, "Could not allocate master\n");
1173 ret = -ENOMEM; 1177 ret = -ENOMEM;
1174 goto exit; 1178 goto exit;
1175 } 1179 }
1176 1180
1177 master->base = ioremap_nocache(res->start, resource_size(res)); 1181 master->base = ioremap_nocache(res->start, resource_size(res));
1178 if (!master->base) { 1182 if (!master->base) {
1179 ret = -ENXIO; 1183 ret = -ENXIO;
1180 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); 1184 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1181 goto exit_kfree; 1185 goto exit_kfree;
1182 } 1186 }
1183 1187
1184 /* master setting */ 1188 /* master setting */
1185 master->irq = irq; 1189 master->irq = irq;
1186 master->info = pdev->dev.platform_data; 1190 master->info = pdev->dev.platform_data;
1187 master->core = (struct fsi_core *)id_entry->driver_data; 1191 master->core = (struct fsi_core *)id_entry->driver_data;
1188 spin_lock_init(&master->lock); 1192 spin_lock_init(&master->lock);
1189 1193
1190 /* FSI A setting */ 1194 /* FSI A setting */
1191 master->fsia.base = master->base; 1195 master->fsia.base = master->base;
1192 master->fsia.master = master; 1196 master->fsia.master = master;
1193 1197
1194 /* FSI B setting */ 1198 /* FSI B setting */
1195 master->fsib.base = master->base + 0x40; 1199 master->fsib.base = master->base + 0x40;
1196 master->fsib.master = master; 1200 master->fsib.master = master;
1197 1201
1198 pm_runtime_enable(&pdev->dev); 1202 pm_runtime_enable(&pdev->dev);
1199 pm_runtime_resume(&pdev->dev); 1203 pm_runtime_resume(&pdev->dev);
1200 dev_set_drvdata(&pdev->dev, master); 1204 dev_set_drvdata(&pdev->dev, master);
1201 1205
1202 fsi_soft_all_reset(master); 1206 fsi_soft_all_reset(master);
1203 1207
1204 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, 1208 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1205 id_entry->name, master); 1209 id_entry->name, master);
1206 if (ret) { 1210 if (ret) {
1207 dev_err(&pdev->dev, "irq request err\n"); 1211 dev_err(&pdev->dev, "irq request err\n");
1208 goto exit_iounmap; 1212 goto exit_iounmap;
1209 } 1213 }
1210 1214
1211 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); 1215 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1212 if (ret < 0) { 1216 if (ret < 0) {
1213 dev_err(&pdev->dev, "cannot snd soc register\n"); 1217 dev_err(&pdev->dev, "cannot snd soc register\n");
1214 goto exit_free_irq; 1218 goto exit_free_irq;
1215 } 1219 }
1216 1220
1217 return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); 1221 return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1218 1222
1219 exit_free_irq: 1223 exit_free_irq:
1220 free_irq(irq, master); 1224 free_irq(irq, master);
1221 exit_iounmap: 1225 exit_iounmap:
1222 iounmap(master->base); 1226 iounmap(master->base);
1223 pm_runtime_disable(&pdev->dev); 1227 pm_runtime_disable(&pdev->dev);
1224 exit_kfree: 1228 exit_kfree:
1225 kfree(master); 1229 kfree(master);
1226 master = NULL; 1230 master = NULL;
1227 exit: 1231 exit:
1228 return ret; 1232 return ret;
1229 } 1233 }
1230 1234
1231 static int fsi_remove(struct platform_device *pdev) 1235 static int fsi_remove(struct platform_device *pdev)
1232 { 1236 {
1233 struct fsi_master *master; 1237 struct fsi_master *master;
1234 1238
1235 master = dev_get_drvdata(&pdev->dev); 1239 master = dev_get_drvdata(&pdev->dev);
1236 1240
1237 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); 1241 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1238 snd_soc_unregister_platform(&pdev->dev); 1242 snd_soc_unregister_platform(&pdev->dev);
1239 1243
1240 pm_runtime_disable(&pdev->dev); 1244 pm_runtime_disable(&pdev->dev);
1241 1245
1242 free_irq(master->irq, master); 1246 free_irq(master->irq, master);
1243 1247
1244 iounmap(master->base); 1248 iounmap(master->base);
1245 kfree(master); 1249 kfree(master);
1246 1250
1247 return 0; 1251 return 0;
1248 } 1252 }
1249 1253
1250 static int fsi_runtime_nop(struct device *dev) 1254 static int fsi_runtime_nop(struct device *dev)
1251 { 1255 {
1252 /* Runtime PM callback shared between ->runtime_suspend() 1256 /* Runtime PM callback shared between ->runtime_suspend()
1253 * and ->runtime_resume(). Simply returns success. 1257 * and ->runtime_resume(). Simply returns success.
1254 * 1258 *
1255 * This driver re-initializes all registers after 1259 * This driver re-initializes all registers after
1256 * pm_runtime_get_sync() anyway so there is no need 1260 * pm_runtime_get_sync() anyway so there is no need
1257 * to save and restore registers here. 1261 * to save and restore registers here.
1258 */ 1262 */
1259 return 0; 1263 return 0;
1260 } 1264 }
1261 1265
1262 static struct dev_pm_ops fsi_pm_ops = { 1266 static struct dev_pm_ops fsi_pm_ops = {
1263 .runtime_suspend = fsi_runtime_nop, 1267 .runtime_suspend = fsi_runtime_nop,
1264 .runtime_resume = fsi_runtime_nop, 1268 .runtime_resume = fsi_runtime_nop,
1265 }; 1269 };
1266 1270
1267 static struct fsi_core fsi1_core = { 1271 static struct fsi_core fsi1_core = {
1268 .ver = 1, 1272 .ver = 1,
1269 1273
1270 /* Interrupt */ 1274 /* Interrupt */