Doug / smarc-fsl-linux-kernel

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/*

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/*

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*

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*

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* Permission is hereby granted, free of charge, to any person obtaining a

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* Permission is hereby granted, free of charge, to any person obtaining a

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* copy of this software and associated documentation files (the "Software"),

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* copy of this software and associated documentation files (the "Software"),

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* to deal in the Software without restriction, including without limitation

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* to deal in the Software without restriction, including without limitation

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* the rights to use, copy, modify, merge, publish, distribute, sublicense,

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* the rights to use, copy, modify, merge, publish, distribute, sublicense,

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* and/or sell copies of the Software, and to permit persons to whom the

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* and/or sell copies of the Software, and to permit persons to whom the

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* Software is furnished to do so, subject to the following conditions:

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* Software is furnished to do so, subject to the following conditions:

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*

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*

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* The above copyright notice and this permission notice shall be included in

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* The above copyright notice and this permission notice shall be included in

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* all copies or substantial portions of the Software.

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* all copies or substantial portions of the Software.

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*

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*

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

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* OTHER DEALINGS IN THE SOFTWARE.

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* OTHER DEALINGS IN THE SOFTWARE.

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*

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*

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* Authors: Dave Airlie

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* Authors: Dave Airlie

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* Alex Deucher

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* Alex Deucher

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*/

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*/

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#include <drm/drmP.h>

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#include <drm/drmP.h>

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#include <drm/radeon_drm.h>

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#include <drm/radeon_drm.h>

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#include "radeon.h"

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#include "radeon.h"

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#include "atom.h"

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#include "atom.h"

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#include <asm/div64.h>

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#include <asm/div64.h>

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#include <drm/drm_crtc_helper.h>

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#include <drm/drm_crtc_helper.h>

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#include <drm/drm_edid.h>

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#include <drm/drm_edid.h>

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static void avivo_crtc_load_lut(struct drm_crtc *crtc)

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static void avivo_crtc_load_lut(struct drm_crtc *crtc)

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{

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{

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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

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struct drm_device *dev = crtc->dev;

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struct drm_device *dev = crtc->dev;

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struct radeon_device *rdev = dev->dev_private;

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struct radeon_device *rdev = dev->dev_private;

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int i;

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int i;

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DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

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DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

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WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);

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WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);

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WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

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WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

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WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

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WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

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WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

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WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

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WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

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WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

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WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

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WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

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WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

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WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

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WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);

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WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);

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WREG32(AVIVO_DC_LUT_RW_MODE, 0);

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WREG32(AVIVO_DC_LUT_RW_MODE, 0);

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WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);

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WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);

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WREG8(AVIVO_DC_LUT_RW_INDEX, 0);

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WREG8(AVIVO_DC_LUT_RW_INDEX, 0);

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for (i = 0; i < 256; i++) {

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for (i = 0; i < 256; i++) {

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WREG32(AVIVO_DC_LUT_30_COLOR,

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WREG32(AVIVO_DC_LUT_30_COLOR,

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(radeon_crtc->lut_r[i] << 20) |

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(radeon_crtc->lut_r[i] << 20) |

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(radeon_crtc->lut_g[i] << 10) |

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(radeon_crtc->lut_g[i] << 10) |

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(radeon_crtc->lut_b[i] << 0));

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(radeon_crtc->lut_b[i] << 0));

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}

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}

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WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);

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WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);

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}

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}

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static void dce4_crtc_load_lut(struct drm_crtc *crtc)

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static void dce4_crtc_load_lut(struct drm_crtc *crtc)

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{

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{

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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

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struct drm_device *dev = crtc->dev;

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struct drm_device *dev = crtc->dev;

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struct radeon_device *rdev = dev->dev_private;

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struct radeon_device *rdev = dev->dev_private;

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int i;

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int i;

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DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

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DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

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WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

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WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);

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WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);

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WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);

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for (i = 0; i < 256; i++) {

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for (i = 0; i < 256; i++) {

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WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,

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WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,

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(radeon_crtc->lut_r[i] << 20) |

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(radeon_crtc->lut_r[i] << 20) |

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(radeon_crtc->lut_g[i] << 10) |

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(radeon_crtc->lut_g[i] << 10) |

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(radeon_crtc->lut_b[i] << 0));

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(radeon_crtc->lut_b[i] << 0));

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}

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}

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}

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}

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static void dce5_crtc_load_lut(struct drm_crtc *crtc)

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static void dce5_crtc_load_lut(struct drm_crtc *crtc)

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{

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{

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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

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struct drm_device *dev = crtc->dev;

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struct drm_device *dev = crtc->dev;

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struct radeon_device *rdev = dev->dev_private;

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struct radeon_device *rdev = dev->dev_private;

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int i;

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int i;

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DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

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DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

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WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

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WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

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(NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |

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(NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |

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NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));

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NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));

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WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,

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WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,

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NI_GRPH_PRESCALE_BYPASS);

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NI_GRPH_PRESCALE_BYPASS);

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WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,

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WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,

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NI_OVL_PRESCALE_BYPASS);

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NI_OVL_PRESCALE_BYPASS);

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WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,

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WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,

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(NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |

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(NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |

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NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));

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NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));

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WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

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WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);

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WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);

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WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);

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WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);

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for (i = 0; i < 256; i++) {

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for (i = 0; i < 256; i++) {

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WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,

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WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,

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(radeon_crtc->lut_r[i] << 20) |

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(radeon_crtc->lut_r[i] << 20) |

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(radeon_crtc->lut_g[i] << 10) |

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(radeon_crtc->lut_g[i] << 10) |

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(radeon_crtc->lut_b[i] << 0));

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(radeon_crtc->lut_b[i] << 0));

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}

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}

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WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,

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WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,

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(NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |

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(NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |

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NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |

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NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |

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NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |

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NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |

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NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));

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NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));

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WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,

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WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,

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(NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |

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(NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |

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NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));

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NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));

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WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,

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WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,

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(NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |

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(NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |

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NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));

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NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));

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WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

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WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

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(NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |

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(NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |

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NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));

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NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));

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/* XXX match this to the depth of the crtc fmt block, move to modeset? */

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/* XXX match this to the depth of the crtc fmt block, move to modeset? */

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WREG32(0x6940 + radeon_crtc->crtc_offset, 0);

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WREG32(0x6940 + radeon_crtc->crtc_offset, 0);

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}

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}

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static void legacy_crtc_load_lut(struct drm_crtc *crtc)

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static void legacy_crtc_load_lut(struct drm_crtc *crtc)

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{

160

{

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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

161

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

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struct drm_device *dev = crtc->dev;

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struct drm_device *dev = crtc->dev;

163

struct radeon_device *rdev = dev->dev_private;

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struct radeon_device *rdev = dev->dev_private;

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int i;

164

int i;

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uint32_t dac2_cntl;

165

uint32_t dac2_cntl;

166

167

dac2_cntl = RREG32(RADEON_DAC_CNTL2);

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dac2_cntl = RREG32(RADEON_DAC_CNTL2);

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if (radeon_crtc->crtc_id == 0)

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if (radeon_crtc->crtc_id == 0)

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dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;

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dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;

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else

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else

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dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;

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dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;

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WREG32(RADEON_DAC_CNTL2, dac2_cntl);

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WREG32(RADEON_DAC_CNTL2, dac2_cntl);

173

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WREG8(RADEON_PALETTE_INDEX, 0);

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WREG8(RADEON_PALETTE_INDEX, 0);

175

for (i = 0; i < 256; i++) {

175

for (i = 0; i < 256; i++) {

176

WREG32(RADEON_PALETTE_30_DATA,

176

WREG32(RADEON_PALETTE_30_DATA,

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(radeon_crtc->lut_r[i] << 20) |

177

(radeon_crtc->lut_r[i] << 20) |

178

(radeon_crtc->lut_g[i] << 10) |

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(radeon_crtc->lut_g[i] << 10) |

179

(radeon_crtc->lut_b[i] << 0));

179

(radeon_crtc->lut_b[i] << 0));

180

}

180

}

181

}

181

}

182

183

void radeon_crtc_load_lut(struct drm_crtc *crtc)

183

void radeon_crtc_load_lut(struct drm_crtc *crtc)

184

{

184

{

185

struct drm_device *dev = crtc->dev;

185

struct drm_device *dev = crtc->dev;

186

struct radeon_device *rdev = dev->dev_private;

186

struct radeon_device *rdev = dev->dev_private;

187

188

if (!crtc->enabled)

188

if (!crtc->enabled)

189

return;

189

return;

190

191

if (ASIC_IS_DCE5(rdev))

191

if (ASIC_IS_DCE5(rdev))

192

dce5_crtc_load_lut(crtc);

192

dce5_crtc_load_lut(crtc);

193

else if (ASIC_IS_DCE4(rdev))

193

else if (ASIC_IS_DCE4(rdev))

194

dce4_crtc_load_lut(crtc);

194

dce4_crtc_load_lut(crtc);

195

else if (ASIC_IS_AVIVO(rdev))

195

else if (ASIC_IS_AVIVO(rdev))

196

avivo_crtc_load_lut(crtc);

196

avivo_crtc_load_lut(crtc);

197

else

197

else

198

legacy_crtc_load_lut(crtc);

198

legacy_crtc_load_lut(crtc);

199

}

199

}

200

201

/** Sets the color ramps on behalf of fbcon */

201

/** Sets the color ramps on behalf of fbcon */

202

void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,

202

void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,

203

u16 blue, int regno)

203

u16 blue, int regno)

204

{

204

{

205

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

205

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

206

207

radeon_crtc->lut_r[regno] = red >> 6;

207

radeon_crtc->lut_r[regno] = red >> 6;

208

radeon_crtc->lut_g[regno] = green >> 6;

208

radeon_crtc->lut_g[regno] = green >> 6;

209

radeon_crtc->lut_b[regno] = blue >> 6;

209

radeon_crtc->lut_b[regno] = blue >> 6;

210

}

210

}

211

212

/** Gets the color ramps on behalf of fbcon */

212

/** Gets the color ramps on behalf of fbcon */

213

void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,

213

void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,

214

u16 *blue, int regno)

214

u16 *blue, int regno)

215

{

215

{

216

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

216

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

217

218

*red = radeon_crtc->lut_r[regno] << 6;

218

*red = radeon_crtc->lut_r[regno] << 6;

219

*green = radeon_crtc->lut_g[regno] << 6;

219

*green = radeon_crtc->lut_g[regno] << 6;

220

*blue = radeon_crtc->lut_b[regno] << 6;

220

*blue = radeon_crtc->lut_b[regno] << 6;

221

}

221

}

222

223

static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,

223

static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,

224

u16 *blue, uint32_t start, uint32_t size)

224

u16 *blue, uint32_t start, uint32_t size)

225

{

225

{

226

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

226

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

227

int end = (start + size > 256) ? 256 : start + size, i;

227

int end = (start + size > 256) ? 256 : start + size, i;

228

229

/* userspace palettes are always correct as is */

229

/* userspace palettes are always correct as is */

230

for (i = start; i < end; i++) {

230

for (i = start; i < end; i++) {

231

radeon_crtc->lut_r[i] = red[i] >> 6;

231

radeon_crtc->lut_r[i] = red[i] >> 6;

232

radeon_crtc->lut_g[i] = green[i] >> 6;

232

radeon_crtc->lut_g[i] = green[i] >> 6;

233

radeon_crtc->lut_b[i] = blue[i] >> 6;

233

radeon_crtc->lut_b[i] = blue[i] >> 6;

234

}

234

}

235

radeon_crtc_load_lut(crtc);

235

radeon_crtc_load_lut(crtc);

236

}

236

}

237

238

static void radeon_crtc_destroy(struct drm_crtc *crtc)

238

static void radeon_crtc_destroy(struct drm_crtc *crtc)

239

{

239

{

240

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

240

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

241

242

drm_crtc_cleanup(crtc);

242

drm_crtc_cleanup(crtc);

243

kfree(radeon_crtc);

243

kfree(radeon_crtc);

244

}

244

}

245

246

/*

246

/*

247

* Handle unpin events outside the interrupt handler proper.

247

* Handle unpin events outside the interrupt handler proper.

248

*/

248

*/

249

static void radeon_unpin_work_func(struct work_struct *__work)

249

static void radeon_unpin_work_func(struct work_struct *__work)

250

{

250

{

251

struct radeon_unpin_work *work =

251

struct radeon_unpin_work *work =

252

container_of(__work, struct radeon_unpin_work, work);

252

container_of(__work, struct radeon_unpin_work, work);

253

int r;

253

int r;

254

255

/* unpin of the old buffer */

255

/* unpin of the old buffer */

256

r = radeon_bo_reserve(work->old_rbo, false);

256

r = radeon_bo_reserve(work->old_rbo, false);

257

if (likely(r == 0)) {

257

if (likely(r == 0)) {

258

r = radeon_bo_unpin(work->old_rbo);

258

r = radeon_bo_unpin(work->old_rbo);

259

if (unlikely(r != 0)) {

259

if (unlikely(r != 0)) {

260

DRM_ERROR("failed to unpin buffer after flip\n");

260

DRM_ERROR("failed to unpin buffer after flip\n");

261

}

261

}

262

radeon_bo_unreserve(work->old_rbo);

262

radeon_bo_unreserve(work->old_rbo);

263

} else

263

} else

264

DRM_ERROR("failed to reserve buffer after flip\n");

264

DRM_ERROR("failed to reserve buffer after flip\n");

265

266

drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);

266

drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);

267

kfree(work);

267

kfree(work);

268

}

268

}

269

270

void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)

270

void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)

271

{

271

{

272

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

272

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

273

struct radeon_unpin_work *work;

273

struct radeon_unpin_work *work;

274

struct drm_pending_vblank_event *e;

274

struct drm_pending_vblank_event *e;

275

struct timeval now;

275

struct timeval now;

276

unsigned long flags;

276

unsigned long flags;

277

u32 update_pending;

277

u32 update_pending;

278

int vpos, hpos;

278

int vpos, hpos;

279

280

spin_lock_irqsave(&rdev->ddev->event_lock, flags);

280

spin_lock_irqsave(&rdev->ddev->event_lock, flags);

281

work = radeon_crtc->unpin_work;

281

work = radeon_crtc->unpin_work;

282

if (work == NULL ||

282

if (work == NULL ||

283

(work->fence && !radeon_fence_signaled(work->fence))) {

283

(work->fence && !radeon_fence_signaled(work->fence))) {

284

spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);

284

spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);

285

return;

285

return;

286

}

286

}

287

/* New pageflip, or just completion of a previous one? */

287

/* New pageflip, or just completion of a previous one? */

288

if (!radeon_crtc->deferred_flip_completion) {

288

if (!radeon_crtc->deferred_flip_completion) {

289

/* do the flip (mmio) */

289

/* do the flip (mmio) */

290

update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);

290

update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);

291

} else {

291

} else {

292

/* This is just a completion of a flip queued in crtc

292

/* This is just a completion of a flip queued in crtc

293

* at last invocation. Make sure we go directly to

293

* at last invocation. Make sure we go directly to

294

* completion routine.

294

* completion routine.

295

*/

295

*/

296

update_pending = 0;

296

update_pending = 0;

297

radeon_crtc->deferred_flip_completion = 0;

297

radeon_crtc->deferred_flip_completion = 0;

298

}

298

}

299

300

/* Has the pageflip already completed in crtc, or is it certain

300

/* Has the pageflip already completed in crtc, or is it certain

301

* to complete in this vblank?

301

* to complete in this vblank?

302

*/

302

*/

303

if (update_pending &&

303

if (update_pending &&

304

(DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,

304

(DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,

305

&vpos, &hpos)) &&

305

&vpos, &hpos)) &&

306

((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||

306

((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||

307

(vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {

307

(vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {

308

/* crtc didn't flip in this target vblank interval,

308

/* crtc didn't flip in this target vblank interval,

309

* but flip is pending in crtc. Based on the current

309

* but flip is pending in crtc. Based on the current

310

* scanout position we know that the current frame is

310

* scanout position we know that the current frame is

311

* (nearly) complete and the flip will (likely)

311

* (nearly) complete and the flip will (likely)

312

* complete before the start of the next frame.

312

* complete before the start of the next frame.

313

*/

313

*/

314

update_pending = 0;

314

update_pending = 0;

315

}

315

}

316

if (update_pending) {

316

if (update_pending) {

317

/* crtc didn't flip in this target vblank interval,

317

/* crtc didn't flip in this target vblank interval,

318

* but flip is pending in crtc. It will complete it

318

* but flip is pending in crtc. It will complete it

319

* in next vblank interval, so complete the flip at

319

* in next vblank interval, so complete the flip at

320

* next vblank irq.

320

* next vblank irq.

321

*/

321

*/

322

radeon_crtc->deferred_flip_completion = 1;

322

radeon_crtc->deferred_flip_completion = 1;

323

spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);

323

spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);

324

return;

324

return;

325

}

325

}

326

327

/* Pageflip (will be) certainly completed in this vblank. Clean up. */

327

/* Pageflip (will be) certainly completed in this vblank. Clean up. */

328

radeon_crtc->unpin_work = NULL;

328

radeon_crtc->unpin_work = NULL;

329

330

/* wakeup userspace */

330

/* wakeup userspace */

331

if (work->event) {

331

if (work->event) {

332

e = work->event;

332

e = work->event;

333

e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);

333

e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);

334

e->event.tv_sec = now.tv_sec;

334

e->event.tv_sec = now.tv_sec;

335

e->event.tv_usec = now.tv_usec;

335

e->event.tv_usec = now.tv_usec;

336

list_add_tail(&e->base.link, &e->base.file_priv->event_list);

336

list_add_tail(&e->base.link, &e->base.file_priv->event_list);

337

wake_up_interruptible(&e->base.file_priv->event_wait);

337

wake_up_interruptible(&e->base.file_priv->event_wait);

338

}

338

}

339

spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);

339

spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);

340

341

drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);

341

drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);

342

radeon_fence_unref(&work->fence);

342

radeon_fence_unref(&work->fence);

343

radeon_post_page_flip(work->rdev, work->crtc_id);

343

radeon_post_page_flip(work->rdev, work->crtc_id);

344

schedule_work(&work->work);

344

schedule_work(&work->work);

345

}

345

}

346

347

static int radeon_crtc_page_flip(struct drm_crtc *crtc,

347

static int radeon_crtc_page_flip(struct drm_crtc *crtc,

348

struct drm_framebuffer *fb,

348

struct drm_framebuffer *fb,

349

struct drm_pending_vblank_event *event)

349

struct drm_pending_vblank_event *event)

350

{

350

{

351

struct drm_device *dev = crtc->dev;

351

struct drm_device *dev = crtc->dev;

352

struct radeon_device *rdev = dev->dev_private;

352

struct radeon_device *rdev = dev->dev_private;

353

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

353

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

354

struct radeon_framebuffer *old_radeon_fb;

354

struct radeon_framebuffer *old_radeon_fb;

355

struct radeon_framebuffer *new_radeon_fb;

355

struct radeon_framebuffer *new_radeon_fb;

356

struct drm_gem_object *obj;

356

struct drm_gem_object *obj;

357

struct radeon_bo *rbo;

357

struct radeon_bo *rbo;

358

struct radeon_unpin_work *work;

358

struct radeon_unpin_work *work;

359

unsigned long flags;

359

unsigned long flags;

360

u32 tiling_flags, pitch_pixels;

360

u32 tiling_flags, pitch_pixels;

361

u64 base;

361

u64 base;

362

int r;

362

int r;

363

364

work = kzalloc(sizeof *work, GFP_KERNEL);

364

work = kzalloc(sizeof *work, GFP_KERNEL);

365

if (work == NULL)

365

if (work == NULL)

366

return -ENOMEM;

366

return -ENOMEM;

367

368

work->event = event;

368

work->event = event;

369

work->rdev = rdev;

369

work->rdev = rdev;

370

work->crtc_id = radeon_crtc->crtc_id;

370

work->crtc_id = radeon_crtc->crtc_id;

371

old_radeon_fb = to_radeon_framebuffer(crtc->fb);

371

old_radeon_fb = to_radeon_framebuffer(crtc->fb);

372

new_radeon_fb = to_radeon_framebuffer(fb);

372

new_radeon_fb = to_radeon_framebuffer(fb);

373

/* schedule unpin of the old buffer */

373

/* schedule unpin of the old buffer */

374

obj = old_radeon_fb->obj;

374

obj = old_radeon_fb->obj;

375

/* take a reference to the old object */

375

/* take a reference to the old object */

376

drm_gem_object_reference(obj);

376

drm_gem_object_reference(obj);

377

rbo = gem_to_radeon_bo(obj);

377

rbo = gem_to_radeon_bo(obj);

378

work->old_rbo = rbo;

378

work->old_rbo = rbo;

379

obj = new_radeon_fb->obj;

379

obj = new_radeon_fb->obj;

380

rbo = gem_to_radeon_bo(obj);

380

rbo = gem_to_radeon_bo(obj);

381

382

spin_lock(&rbo->tbo.bdev->fence_lock);

382

spin_lock(&rbo->tbo.bdev->fence_lock);

383

if (rbo->tbo.sync_obj)

383

if (rbo->tbo.sync_obj)

384

work->fence = radeon_fence_ref(rbo->tbo.sync_obj);

384

work->fence = radeon_fence_ref(rbo->tbo.sync_obj);

385

spin_unlock(&rbo->tbo.bdev->fence_lock);

385

spin_unlock(&rbo->tbo.bdev->fence_lock);

386

387

INIT_WORK(&work->work, radeon_unpin_work_func);

387

INIT_WORK(&work->work, radeon_unpin_work_func);

388

389

/* We borrow the event spin lock for protecting unpin_work */

389

/* We borrow the event spin lock for protecting unpin_work */

390

spin_lock_irqsave(&dev->event_lock, flags);

390

spin_lock_irqsave(&dev->event_lock, flags);

391

if (radeon_crtc->unpin_work) {

391

if (radeon_crtc->unpin_work) {

392

DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");

392

DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");

393

r = -EBUSY;

393

r = -EBUSY;

394

goto unlock_free;

394

goto unlock_free;

395

}

395

}

396

radeon_crtc->unpin_work = work;

396

radeon_crtc->unpin_work = work;

397

radeon_crtc->deferred_flip_completion = 0;

397

radeon_crtc->deferred_flip_completion = 0;

398

spin_unlock_irqrestore(&dev->event_lock, flags);

398

spin_unlock_irqrestore(&dev->event_lock, flags);

399

400

/* pin the new buffer */

400

/* pin the new buffer */

401

DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",

401

DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",

402

work->old_rbo, rbo);

402

work->old_rbo, rbo);

403

404

r = radeon_bo_reserve(rbo, false);

404

r = radeon_bo_reserve(rbo, false);

405

if (unlikely(r != 0)) {

405

if (unlikely(r != 0)) {

406

DRM_ERROR("failed to reserve new rbo buffer before flip\n");

406

DRM_ERROR("failed to reserve new rbo buffer before flip\n");

407

goto pflip_cleanup;

407

goto pflip_cleanup;

408

}

408

}

409

/* Only 27 bit offset for legacy CRTC */

409

/* Only 27 bit offset for legacy CRTC */

410

r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,

410

r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,

411

ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);

411

ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);

412

if (unlikely(r != 0)) {

412

if (unlikely(r != 0)) {

413

radeon_bo_unreserve(rbo);

413

radeon_bo_unreserve(rbo);

414

r = -EINVAL;

414

r = -EINVAL;

415

DRM_ERROR("failed to pin new rbo buffer before flip\n");

415

DRM_ERROR("failed to pin new rbo buffer before flip\n");

416

goto pflip_cleanup;

416

goto pflip_cleanup;

417

}

417

}

418

radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);

418

radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);

419

radeon_bo_unreserve(rbo);

419

radeon_bo_unreserve(rbo);

420

421

if (!ASIC_IS_AVIVO(rdev)) {

421

if (!ASIC_IS_AVIVO(rdev)) {

422

/* crtc offset is from display base addr not FB location */

422

/* crtc offset is from display base addr not FB location */

423

base -= radeon_crtc->legacy_display_base_addr;

423

base -= radeon_crtc->legacy_display_base_addr;

424

pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);

424

pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);

425

426

if (tiling_flags & RADEON_TILING_MACRO) {

426

if (tiling_flags & RADEON_TILING_MACRO) {

427

if (ASIC_IS_R300(rdev)) {

427

if (ASIC_IS_R300(rdev)) {

428

base &= ~0x7ff;

428

base &= ~0x7ff;

429

} else {

429

} else {

430

int byteshift = fb->bits_per_pixel >> 4;

430

int byteshift = fb->bits_per_pixel >> 4;

431

int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;

431

int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;

432

base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);

432

base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);

433

}

433

}

434

} else {

434

} else {

435

int offset = crtc->y * pitch_pixels + crtc->x;

435

int offset = crtc->y * pitch_pixels + crtc->x;

436

switch (fb->bits_per_pixel) {

436

switch (fb->bits_per_pixel) {

437

case 8:

437

case 8:

438

default:

438

default:

439

offset *= 1;

439

offset *= 1;

440

break;

440

break;

441

case 15:

441

case 15:

442

case 16:

442

case 16:

443

offset *= 2;

443

offset *= 2;

444

break;

444

break;

445

case 24:

445

case 24:

446

offset *= 3;

446

offset *= 3;

447

break;

447

break;

448

case 32:

448

case 32:

449

offset *= 4;

449

offset *= 4;

450

break;

450

break;

451

}

451

}

452

base += offset;

452

base += offset;

453

}

453

}

454

base &= ~7;

454

base &= ~7;

455

}

455

}

456

457

spin_lock_irqsave(&dev->event_lock, flags);

457

spin_lock_irqsave(&dev->event_lock, flags);

458

work->new_crtc_base = base;

458

work->new_crtc_base = base;

459

spin_unlock_irqrestore(&dev->event_lock, flags);

459

spin_unlock_irqrestore(&dev->event_lock, flags);

460

461

/* update crtc fb */

461

/* update crtc fb */

462

crtc->fb = fb;

462

crtc->fb = fb;

463

464

r = drm_vblank_get(dev, radeon_crtc->crtc_id);

464

r = drm_vblank_get(dev, radeon_crtc->crtc_id);

465

if (r) {

465

if (r) {

466

DRM_ERROR("failed to get vblank before flip\n");

466

DRM_ERROR("failed to get vblank before flip\n");

467

goto pflip_cleanup1;

467

goto pflip_cleanup1;

468

}

468

}

469

470

/* set the proper interrupt */

470

/* set the proper interrupt */

471

radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);

471

radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);

472

473

return 0;

473

return 0;

474

475

pflip_cleanup1:

475

pflip_cleanup1:

476

if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {

476

if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {

477

DRM_ERROR("failed to reserve new rbo in error path\n");

477

DRM_ERROR("failed to reserve new rbo in error path\n");

478

goto pflip_cleanup;

478

goto pflip_cleanup;

479

}

479

}

480

if (unlikely(radeon_bo_unpin(rbo) != 0)) {

480

if (unlikely(radeon_bo_unpin(rbo) != 0)) {

481

DRM_ERROR("failed to unpin new rbo in error path\n");

481

DRM_ERROR("failed to unpin new rbo in error path\n");

482

}

482

}

483

radeon_bo_unreserve(rbo);

483

radeon_bo_unreserve(rbo);

484

485

pflip_cleanup:

485

pflip_cleanup:

486

spin_lock_irqsave(&dev->event_lock, flags);

486

spin_lock_irqsave(&dev->event_lock, flags);

487

radeon_crtc->unpin_work = NULL;

487

radeon_crtc->unpin_work = NULL;

488

unlock_free:

488

unlock_free:

489

spin_unlock_irqrestore(&dev->event_lock, flags);

489

spin_unlock_irqrestore(&dev->event_lock, flags);

490

drm_gem_object_unreference_unlocked(old_radeon_fb->obj);

490

drm_gem_object_unreference_unlocked(old_radeon_fb->obj);

491

radeon_fence_unref(&work->fence);

491

radeon_fence_unref(&work->fence);

492

kfree(work);

492

kfree(work);

493

494

return r;

494

return r;

495

}

495

}

496

497

static const struct drm_crtc_funcs radeon_crtc_funcs = {

497

static const struct drm_crtc_funcs radeon_crtc_funcs = {

498

.cursor_set = radeon_crtc_cursor_set,

498

.cursor_set = radeon_crtc_cursor_set,

499

.cursor_move = radeon_crtc_cursor_move,

499

.cursor_move = radeon_crtc_cursor_move,

500

.gamma_set = radeon_crtc_gamma_set,

500

.gamma_set = radeon_crtc_gamma_set,

501

.set_config = drm_crtc_helper_set_config,

501

.set_config = drm_crtc_helper_set_config,

502

.destroy = radeon_crtc_destroy,

502

.destroy = radeon_crtc_destroy,

503

.page_flip = radeon_crtc_page_flip,

503

.page_flip = radeon_crtc_page_flip,

504

};

504

};

505

506

static void radeon_crtc_init(struct drm_device *dev, int index)

506

static void radeon_crtc_init(struct drm_device *dev, int index)

507

{

507

{

508

struct radeon_device *rdev = dev->dev_private;

508

struct radeon_device *rdev = dev->dev_private;

509

struct radeon_crtc *radeon_crtc;

509

struct radeon_crtc *radeon_crtc;

510

int i;

510

int i;

511

512

radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);

512

radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);

513

if (radeon_crtc == NULL)

513

if (radeon_crtc == NULL)

514

return;

514

return;

515

516

drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);

516

drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);

517

518

drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);

518

drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);

519

radeon_crtc->crtc_id = index;

519

radeon_crtc->crtc_id = index;

520

rdev->mode_info.crtcs[index] = radeon_crtc;

520

rdev->mode_info.crtcs[index] = radeon_crtc;

521

522

#if 0

522

#if 0

523

radeon_crtc->mode_set.crtc = &radeon_crtc->base;

523

radeon_crtc->mode_set.crtc = &radeon_crtc->base;

524

radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);

524

radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);

525

radeon_crtc->mode_set.num_connectors = 0;

525

radeon_crtc->mode_set.num_connectors = 0;

526

#endif

526

#endif

527

528

for (i = 0; i < 256; i++) {

528

for (i = 0; i < 256; i++) {

529

radeon_crtc->lut_r[i] = i << 2;

529

radeon_crtc->lut_r[i] = i << 2;

530

radeon_crtc->lut_g[i] = i << 2;

530

radeon_crtc->lut_g[i] = i << 2;

531

radeon_crtc->lut_b[i] = i << 2;

531

radeon_crtc->lut_b[i] = i << 2;

532

}

532

}

533

534

if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))

534

if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))

535

radeon_atombios_init_crtc(dev, radeon_crtc);

535

radeon_atombios_init_crtc(dev, radeon_crtc);

536

else

536

else

537

radeon_legacy_init_crtc(dev, radeon_crtc);

537

radeon_legacy_init_crtc(dev, radeon_crtc);

538

}

538

}

539

540

static const char *encoder_names[37] = {

540

static const char *encoder_names[37] = {

541

"NONE",

541

"NONE",

542

"INTERNAL_LVDS",

542

"INTERNAL_LVDS",

543

"INTERNAL_TMDS1",

543

"INTERNAL_TMDS1",

544

"INTERNAL_TMDS2",

544

"INTERNAL_TMDS2",

545

"INTERNAL_DAC1",

545

"INTERNAL_DAC1",

546

"INTERNAL_DAC2",

546

"INTERNAL_DAC2",

547

"INTERNAL_SDVOA",

547

"INTERNAL_SDVOA",

548

"INTERNAL_SDVOB",

548

"INTERNAL_SDVOB",

549

"SI170B",

549

"SI170B",

550

"CH7303",

550

"CH7303",

551

"CH7301",

551

"CH7301",

552

"INTERNAL_DVO1",

552

"INTERNAL_DVO1",

553

"EXTERNAL_SDVOA",

553

"EXTERNAL_SDVOA",

554

"EXTERNAL_SDVOB",

554

"EXTERNAL_SDVOB",

555

"TITFP513",

555

"TITFP513",

556

"INTERNAL_LVTM1",

556

"INTERNAL_LVTM1",

557

"VT1623",

557

"VT1623",

558

"HDMI_SI1930",

558

"HDMI_SI1930",

559

"HDMI_INTERNAL",

559

"HDMI_INTERNAL",

560

"INTERNAL_KLDSCP_TMDS1",

560

"INTERNAL_KLDSCP_TMDS1",

561

"INTERNAL_KLDSCP_DVO1",

561

"INTERNAL_KLDSCP_DVO1",

562

"INTERNAL_KLDSCP_DAC1",

562

"INTERNAL_KLDSCP_DAC1",

563

"INTERNAL_KLDSCP_DAC2",

563

"INTERNAL_KLDSCP_DAC2",

564

"SI178",

564

"SI178",

565

"MVPU_FPGA",

565

"MVPU_FPGA",

566

"INTERNAL_DDI",

566

"INTERNAL_DDI",

567

"VT1625",

567

"VT1625",

568

"HDMI_SI1932",

568

"HDMI_SI1932",

569

"DP_AN9801",

569

"DP_AN9801",

570

"DP_DP501",

570

"DP_DP501",

571

"INTERNAL_UNIPHY",

571

"INTERNAL_UNIPHY",

572

"INTERNAL_KLDSCP_LVTMA",

572

"INTERNAL_KLDSCP_LVTMA",

573

"INTERNAL_UNIPHY1",

573

"INTERNAL_UNIPHY1",

574

"INTERNAL_UNIPHY2",

574

"INTERNAL_UNIPHY2",

575

"NUTMEG",

575

"NUTMEG",

576

"TRAVIS",

576

"TRAVIS",

577

"INTERNAL_VCE"

577

"INTERNAL_VCE"

578

};

578

};

579

580

static const char *hpd_names[6] = {

580

static const char *hpd_names[6] = {

581

"HPD1",

581

"HPD1",

582

"HPD2",

582

"HPD2",

583

"HPD3",

583

"HPD3",

584

"HPD4",

584

"HPD4",

585

"HPD5",

585

"HPD5",

586

"HPD6",

586

"HPD6",

587

};

587

};

588

589

static void radeon_print_display_setup(struct drm_device *dev)

589

static void radeon_print_display_setup(struct drm_device *dev)

590

{

590

{

591

struct drm_connector *connector;

591

struct drm_connector *connector;

592

struct radeon_connector *radeon_connector;

592

struct radeon_connector *radeon_connector;

593

struct drm_encoder *encoder;

593

struct drm_encoder *encoder;

594

struct radeon_encoder *radeon_encoder;

594

struct radeon_encoder *radeon_encoder;

595

uint32_t devices;

595

uint32_t devices;

596

int i = 0;

596

int i = 0;

597

598

DRM_INFO("Radeon Display Connectors\n");

598

DRM_INFO("Radeon Display Connectors\n");

599

list_for_each_entry(connector, &dev->mode_config.connector_list, head) {

599

list_for_each_entry(connector, &dev->mode_config.connector_list, head) {

600

radeon_connector = to_radeon_connector(connector);

600

radeon_connector = to_radeon_connector(connector);

601

DRM_INFO("Connector %d:\n", i);

601

DRM_INFO("Connector %d:\n", i);

602

DRM_INFO(" %s\n", drm_get_connector_name(connector));

602

DRM_INFO(" %s\n", drm_get_connector_name(connector));

603

if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)

603

if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)

604

DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);

604

DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);

605

if (radeon_connector->ddc_bus) {

605

if (radeon_connector->ddc_bus) {

606

DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",

606

DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",

607

radeon_connector->ddc_bus->rec.mask_clk_reg,

607

radeon_connector->ddc_bus->rec.mask_clk_reg,

608

radeon_connector->ddc_bus->rec.mask_data_reg,

608

radeon_connector->ddc_bus->rec.mask_data_reg,

609

radeon_connector->ddc_bus->rec.a_clk_reg,

609

radeon_connector->ddc_bus->rec.a_clk_reg,

610

radeon_connector->ddc_bus->rec.a_data_reg,

610

radeon_connector->ddc_bus->rec.a_data_reg,

611

radeon_connector->ddc_bus->rec.en_clk_reg,

611

radeon_connector->ddc_bus->rec.en_clk_reg,

612

radeon_connector->ddc_bus->rec.en_data_reg,

612

radeon_connector->ddc_bus->rec.en_data_reg,

613

radeon_connector->ddc_bus->rec.y_clk_reg,

613

radeon_connector->ddc_bus->rec.y_clk_reg,

614

radeon_connector->ddc_bus->rec.y_data_reg);

614

radeon_connector->ddc_bus->rec.y_data_reg);

615

if (radeon_connector->router.ddc_valid)

615

if (radeon_connector->router.ddc_valid)

616

DRM_INFO(" DDC Router 0x%x/0x%x\n",

616

DRM_INFO(" DDC Router 0x%x/0x%x\n",

617

radeon_connector->router.ddc_mux_control_pin,

617

radeon_connector->router.ddc_mux_control_pin,

618

radeon_connector->router.ddc_mux_state);

618

radeon_connector->router.ddc_mux_state);

619

if (radeon_connector->router.cd_valid)

619

if (radeon_connector->router.cd_valid)

620

DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",

620

DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",

621

radeon_connector->router.cd_mux_control_pin,

621

radeon_connector->router.cd_mux_control_pin,

622

radeon_connector->router.cd_mux_state);

622

radeon_connector->router.cd_mux_state);

623

} else {

623

} else {

624

if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||

624

if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||

625

connector->connector_type == DRM_MODE_CONNECTOR_DVII ||

625

connector->connector_type == DRM_MODE_CONNECTOR_DVII ||

626

connector->connector_type == DRM_MODE_CONNECTOR_DVID ||

626

connector->connector_type == DRM_MODE_CONNECTOR_DVID ||

627

connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||

627

connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||

628

connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||

628

connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||

629

connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)

629

connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)

630

DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");

630

DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");

631

}

631

}

632

DRM_INFO(" Encoders:\n");

632

DRM_INFO(" Encoders:\n");

633

list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {

633

list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {

634

radeon_encoder = to_radeon_encoder(encoder);

634

radeon_encoder = to_radeon_encoder(encoder);

635

devices = radeon_encoder->devices & radeon_connector->devices;

635

devices = radeon_encoder->devices & radeon_connector->devices;

636

if (devices) {

636

if (devices) {

637

if (devices & ATOM_DEVICE_CRT1_SUPPORT)

637

if (devices & ATOM_DEVICE_CRT1_SUPPORT)

638

DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);

638

DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);

639

if (devices & ATOM_DEVICE_CRT2_SUPPORT)

639

if (devices & ATOM_DEVICE_CRT2_SUPPORT)

640

DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);

640

DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);

641

if (devices & ATOM_DEVICE_LCD1_SUPPORT)

641

if (devices & ATOM_DEVICE_LCD1_SUPPORT)

642

DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);

642

DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);

643

if (devices & ATOM_DEVICE_DFP1_SUPPORT)

643

if (devices & ATOM_DEVICE_DFP1_SUPPORT)

644

DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);

644

DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);

645

if (devices & ATOM_DEVICE_DFP2_SUPPORT)

645

if (devices & ATOM_DEVICE_DFP2_SUPPORT)

646

DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);

646

DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);

647

if (devices & ATOM_DEVICE_DFP3_SUPPORT)

647

if (devices & ATOM_DEVICE_DFP3_SUPPORT)

648

DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);

648

DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);

649

if (devices & ATOM_DEVICE_DFP4_SUPPORT)

649

if (devices & ATOM_DEVICE_DFP4_SUPPORT)

650

DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);

650

DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);

651

if (devices & ATOM_DEVICE_DFP5_SUPPORT)

651

if (devices & ATOM_DEVICE_DFP5_SUPPORT)

652

DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);

652

DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);

653

if (devices & ATOM_DEVICE_DFP6_SUPPORT)

653

if (devices & ATOM_DEVICE_DFP6_SUPPORT)

654

DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);

654

DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);

655

if (devices & ATOM_DEVICE_TV1_SUPPORT)

655

if (devices & ATOM_DEVICE_TV1_SUPPORT)

656

DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);

656

DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);

657

if (devices & ATOM_DEVICE_CV_SUPPORT)

657

if (devices & ATOM_DEVICE_CV_SUPPORT)

658

DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);

658

DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);

659

}

659

}

660

}

660

}

661

i++;

661

i++;

662

}

662

}

663

}

663

}

664

665

static bool radeon_setup_enc_conn(struct drm_device *dev)

665

static bool radeon_setup_enc_conn(struct drm_device *dev)

666

{

666

{

667

struct radeon_device *rdev = dev->dev_private;

667

struct radeon_device *rdev = dev->dev_private;

668

bool ret = false;

668

bool ret = false;

669

670

if (rdev->bios) {

670

if (rdev->bios) {

671

if (rdev->is_atom_bios) {

671

if (rdev->is_atom_bios) {

672

ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);

672

ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);

673

if (ret == false)

673

if (ret == false)

674

ret = radeon_get_atom_connector_info_from_object_table(dev);

674

ret = radeon_get_atom_connector_info_from_object_table(dev);

675

} else {

675

} else {

676

ret = radeon_get_legacy_connector_info_from_bios(dev);

676

ret = radeon_get_legacy_connector_info_from_bios(dev);

677

if (ret == false)

677

if (ret == false)

678

ret = radeon_get_legacy_connector_info_from_table(dev);

678

ret = radeon_get_legacy_connector_info_from_table(dev);

679

}

679

}

680

} else {

680

} else {

681

if (!ASIC_IS_AVIVO(rdev))

681

if (!ASIC_IS_AVIVO(rdev))

682

ret = radeon_get_legacy_connector_info_from_table(dev);

682

ret = radeon_get_legacy_connector_info_from_table(dev);

683

}

683

}

684

if (ret) {

684

if (ret) {

685

radeon_setup_encoder_clones(dev);

685

radeon_setup_encoder_clones(dev);

686

radeon_print_display_setup(dev);

686

radeon_print_display_setup(dev);

687

}

687

}

688

689

return ret;

689

return ret;

690

}

690

}

691

692

int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)

692

int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)

693

{

693

{

694

struct drm_device *dev = radeon_connector->base.dev;

694

struct drm_device *dev = radeon_connector->base.dev;

695

struct radeon_device *rdev = dev->dev_private;

695

struct radeon_device *rdev = dev->dev_private;

696

int ret = 0;

696

int ret = 0;

697

698

/* on hw with routers, select right port */

698

/* on hw with routers, select right port */

699

if (radeon_connector->router.ddc_valid)

699

if (radeon_connector->router.ddc_valid)

700

radeon_router_select_ddc_port(radeon_connector);

700

radeon_router_select_ddc_port(radeon_connector);

701

702

if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=

702

if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=

703

ENCODER_OBJECT_ID_NONE) {

703

ENCODER_OBJECT_ID_NONE) {

704

struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;

704

struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;

705

706

if (dig->dp_i2c_bus)

706

if (dig->dp_i2c_bus)

707

radeon_connector->edid = drm_get_edid(&radeon_connector->base,

707

radeon_connector->edid = drm_get_edid(&radeon_connector->base,

708

&dig->dp_i2c_bus->adapter);

708

&dig->dp_i2c_bus->adapter);

709

} else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||

709

} else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||

710

(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {

710

(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {

711

struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;

711

struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;

712

713

if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||

713

if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||

714

dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)

714

dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)

715

radeon_connector->edid = drm_get_edid(&radeon_connector->base,

715

radeon_connector->edid = drm_get_edid(&radeon_connector->base,

716

&dig->dp_i2c_bus->adapter);

716

&dig->dp_i2c_bus->adapter);

717

else if (radeon_connector->ddc_bus && !radeon_connector->edid)

717

else if (radeon_connector->ddc_bus && !radeon_connector->edid)

718

radeon_connector->edid = drm_get_edid(&radeon_connector->base,

718

radeon_connector->edid = drm_get_edid(&radeon_connector->base,

719

&radeon_connector->ddc_bus->adapter);

719

&radeon_connector->ddc_bus->adapter);

720

} else {

720

} else {

721

if (radeon_connector->ddc_bus && !radeon_connector->edid)

721

if (radeon_connector->ddc_bus && !radeon_connector->edid)

722

radeon_connector->edid = drm_get_edid(&radeon_connector->base,

722

radeon_connector->edid = drm_get_edid(&radeon_connector->base,

723

&radeon_connector->ddc_bus->adapter);

723

&radeon_connector->ddc_bus->adapter);

724

}

724

}

725

726

if (!radeon_connector->edid) {

726

if (!radeon_connector->edid) {

727

if (rdev->is_atom_bios) {

727

if (rdev->is_atom_bios) {

728

/* some laptops provide a hardcoded edid in rom for LCDs */

728

/* some laptops provide a hardcoded edid in rom for LCDs */

729

if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||

729

if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||

730

(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))

730

(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))

731

radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);

731

radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);

732

} else

732

} else

733

/* some servers provide a hardcoded edid in rom for KVMs */

733

/* some servers provide a hardcoded edid in rom for KVMs */

734

radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);

734

radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);

735

}

735

}

736

if (radeon_connector->edid) {

736

if (radeon_connector->edid) {

737

drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);

737

drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);

738

ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);

738

ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);

739

return ret;

739

return ret;

740

}

740

}

741

drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);

741

drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);

742

return 0;

742

return 0;

743

}

743

}

744

745

/* avivo */

745

/* avivo */

746

static void avivo_get_fb_div(struct radeon_pll *pll,

746

static void avivo_get_fb_div(struct radeon_pll *pll,

747

u32 target_clock,

747

u32 target_clock,

748

u32 post_div,

748

u32 post_div,

749

u32 ref_div,

749

u32 ref_div,

750

u32 *fb_div,

750

u32 *fb_div,

751

u32 *frac_fb_div)

751

u32 *frac_fb_div)

752

{

752

{

753

u32 tmp = post_div * ref_div;

753

u32 tmp = post_div * ref_div;

754

755

tmp *= target_clock;

755

tmp *= target_clock;

756

*fb_div = tmp / pll->reference_freq;

756

*fb_div = tmp / pll->reference_freq;

757

*frac_fb_div = tmp % pll->reference_freq;

757

*frac_fb_div = tmp % pll->reference_freq;

758

759

if (*fb_div > pll->max_feedback_div)

759

if (*fb_div > pll->max_feedback_div)

760

*fb_div = pll->max_feedback_div;

760

*fb_div = pll->max_feedback_div;

761

else if (*fb_div < pll->min_feedback_div)

761

else if (*fb_div < pll->min_feedback_div)

762

*fb_div = pll->min_feedback_div;

762

*fb_div = pll->min_feedback_div;

763

}

763

}

764

765

static u32 avivo_get_post_div(struct radeon_pll *pll,

765

static u32 avivo_get_post_div(struct radeon_pll *pll,

766

u32 target_clock)

766

u32 target_clock)

767

{

767

{

768

u32 vco, post_div, tmp;

768

u32 vco, post_div, tmp;

769

770

if (pll->flags & RADEON_PLL_USE_POST_DIV)

770

if (pll->flags & RADEON_PLL_USE_POST_DIV)

771

return pll->post_div;

771

return pll->post_div;

772

773

if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {

773

if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {

774

if (pll->flags & RADEON_PLL_IS_LCD)

774

if (pll->flags & RADEON_PLL_IS_LCD)

775

vco = pll->lcd_pll_out_min;

775

vco = pll->lcd_pll_out_min;

776

else

776

else

777

vco = pll->pll_out_min;

777

vco = pll->pll_out_min;

778

} else {

778

} else {

779

if (pll->flags & RADEON_PLL_IS_LCD)

779

if (pll->flags & RADEON_PLL_IS_LCD)

780

vco = pll->lcd_pll_out_max;

780

vco = pll->lcd_pll_out_max;

781

else

781

else

782

vco = pll->pll_out_max;

782

vco = pll->pll_out_max;

783

}

783

}

784

785

post_div = vco / target_clock;

785

post_div = vco / target_clock;

786

tmp = vco % target_clock;

786

tmp = vco % target_clock;

787

788

if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {

788

if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {

789

if (tmp)

789

if (tmp)

790

post_div++;

790

post_div++;

791

} else {

791

} else {

792

if (!tmp)

792

if (!tmp)

793

post_div--;

793

post_div--;

794

}

794

}

795

796

if (post_div > pll->max_post_div)

796

if (post_div > pll->max_post_div)

797

post_div = pll->max_post_div;

797

post_div = pll->max_post_div;

798

else if (post_div < pll->min_post_div)

798

else if (post_div < pll->min_post_div)

799

post_div = pll->min_post_div;

799

post_div = pll->min_post_div;

800

801

return post_div;

801

return post_div;

802

}

802

}

803

804

#define MAX_TOLERANCE 10

804

#define MAX_TOLERANCE 10

805

806

void radeon_compute_pll_avivo(struct radeon_pll *pll,

806

void radeon_compute_pll_avivo(struct radeon_pll *pll,

807

u32 freq,

807

u32 freq,

808

u32 *dot_clock_p,

808

u32 *dot_clock_p,

809

u32 *fb_div_p,

809

u32 *fb_div_p,

810

u32 *frac_fb_div_p,

810

u32 *frac_fb_div_p,

811

u32 *ref_div_p,

811

u32 *ref_div_p,

812

u32 *post_div_p)

812

u32 *post_div_p)

813

{

813

{

814

u32 target_clock = freq / 10;

814

u32 target_clock = freq / 10;

815

u32 post_div = avivo_get_post_div(pll, target_clock);

815

u32 post_div = avivo_get_post_div(pll, target_clock);

816

u32 ref_div = pll->min_ref_div;

816

u32 ref_div = pll->min_ref_div;

817

u32 fb_div = 0, frac_fb_div = 0, tmp;

817

u32 fb_div = 0, frac_fb_div = 0, tmp;

818

819

if (pll->flags & RADEON_PLL_USE_REF_DIV)

819

if (pll->flags & RADEON_PLL_USE_REF_DIV)

820

ref_div = pll->reference_div;

820

ref_div = pll->reference_div;

821

822

if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {

822

if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {

823

avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);

823

avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);

824

frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;

824

frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;

825

if (frac_fb_div >= 5) {

825

if (frac_fb_div >= 5) {

826

frac_fb_div -= 5;

826

frac_fb_div -= 5;

827

frac_fb_div = frac_fb_div / 10;

827

frac_fb_div = frac_fb_div / 10;

828

frac_fb_div++;

828

frac_fb_div++;

829

}

829

}

830

if (frac_fb_div >= 10) {

830

if (frac_fb_div >= 10) {

831

fb_div++;

831

fb_div++;

832

frac_fb_div = 0;

832

frac_fb_div = 0;

833

}

833

}

834

} else {

834

} else {

835

while (ref_div <= pll->max_ref_div) {

835

while (ref_div <= pll->max_ref_div) {

836

avivo_get_fb_div(pll, target_clock, post_div, ref_div,

836

avivo_get_fb_div(pll, target_clock, post_div, ref_div,

837

&fb_div, &frac_fb_div);

837

&fb_div, &frac_fb_div);

838

if (frac_fb_div >= (pll->reference_freq / 2))

838

if (frac_fb_div >= (pll->reference_freq / 2))

839

fb_div++;

839

fb_div++;

840

frac_fb_div = 0;

840

frac_fb_div = 0;

841

tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);

841

tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);

842

tmp = (tmp * 10000) / target_clock;

842

tmp = (tmp * 10000) / target_clock;

843

844

if (tmp > (10000 + MAX_TOLERANCE))

844

if (tmp > (10000 + MAX_TOLERANCE))

845

ref_div++;

845

ref_div++;

846

else if (tmp >= (10000 - MAX_TOLERANCE))

846

else if (tmp >= (10000 - MAX_TOLERANCE))

847

break;

847

break;

848

else

848

else

849

ref_div++;

849

ref_div++;

850

}

850

}

851

}

851

}

852

853

*dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /

853

*dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /

854

(ref_div * post_div * 10);

854

(ref_div * post_div * 10);

855

*fb_div_p = fb_div;

855

*fb_div_p = fb_div;

856

*frac_fb_div_p = frac_fb_div;

856

*frac_fb_div_p = frac_fb_div;

857

*ref_div_p = ref_div;

857

*ref_div_p = ref_div;

858

*post_div_p = post_div;

858

*post_div_p = post_div;

859

DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",

859

DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",

860

*dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);

860

*dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);

861

}

861

}

862

863

/* pre-avivo */

863

/* pre-avivo */

864

static inline uint32_t radeon_div(uint64_t n, uint32_t d)

864

static inline uint32_t radeon_div(uint64_t n, uint32_t d)

865

{

865

{

866

uint64_t mod;

866

uint64_t mod;

867

868

n += d / 2;

868

n += d / 2;

869

870

mod = do_div(n, d);

870

mod = do_div(n, d);

871

return n;

871

return n;

872

}

872

}

873

874

void radeon_compute_pll_legacy(struct radeon_pll *pll,

874

void radeon_compute_pll_legacy(struct radeon_pll *pll,

875

uint64_t freq,

875

uint64_t freq,

876

uint32_t *dot_clock_p,

876

uint32_t *dot_clock_p,

877

uint32_t *fb_div_p,

877

uint32_t *fb_div_p,

878

uint32_t *frac_fb_div_p,

878

uint32_t *frac_fb_div_p,

879

uint32_t *ref_div_p,

879

uint32_t *ref_div_p,

880

uint32_t *post_div_p)

880

uint32_t *post_div_p)

881

{

881

{

882

uint32_t min_ref_div = pll->min_ref_div;

882

uint32_t min_ref_div = pll->min_ref_div;

883

uint32_t max_ref_div = pll->max_ref_div;

883

uint32_t max_ref_div = pll->max_ref_div;

884

uint32_t min_post_div = pll->min_post_div;

884

uint32_t min_post_div = pll->min_post_div;

885

uint32_t max_post_div = pll->max_post_div;

885

uint32_t max_post_div = pll->max_post_div;

886

uint32_t min_fractional_feed_div = 0;

886

uint32_t min_fractional_feed_div = 0;

887

uint32_t max_fractional_feed_div = 0;

887

uint32_t max_fractional_feed_div = 0;

888

uint32_t best_vco = pll->best_vco;

888

uint32_t best_vco = pll->best_vco;

889

uint32_t best_post_div = 1;

889

uint32_t best_post_div = 1;

890

uint32_t best_ref_div = 1;

890

uint32_t best_ref_div = 1;

891

uint32_t best_feedback_div = 1;

891

uint32_t best_feedback_div = 1;

892

uint32_t best_frac_feedback_div = 0;

892

uint32_t best_frac_feedback_div = 0;

893

uint32_t best_freq = -1;

893

uint32_t best_freq = -1;

894

uint32_t best_error = 0xffffffff;

894

uint32_t best_error = 0xffffffff;

895

uint32_t best_vco_diff = 1;

895

uint32_t best_vco_diff = 1;

896

uint32_t post_div;

896

uint32_t post_div;

897

u32 pll_out_min, pll_out_max;

897

u32 pll_out_min, pll_out_max;

898

899

DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);

899

DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);

900

freq = freq * 1000;

900

freq = freq * 1000;

901

902

if (pll->flags & RADEON_PLL_IS_LCD) {

902

if (pll->flags & RADEON_PLL_IS_LCD) {

903

pll_out_min = pll->lcd_pll_out_min;

903

pll_out_min = pll->lcd_pll_out_min;

904

pll_out_max = pll->lcd_pll_out_max;

904

pll_out_max = pll->lcd_pll_out_max;

905

} else {

905

} else {

906

pll_out_min = pll->pll_out_min;

906

pll_out_min = pll->pll_out_min;

907

pll_out_max = pll->pll_out_max;

907

pll_out_max = pll->pll_out_max;

908

}

908

}

909

910

if (pll_out_min > 64800)

910

if (pll_out_min > 64800)

911

pll_out_min = 64800;

911

pll_out_min = 64800;

912

913

if (pll->flags & RADEON_PLL_USE_REF_DIV)

913

if (pll->flags & RADEON_PLL_USE_REF_DIV)

914

min_ref_div = max_ref_div = pll->reference_div;

914

min_ref_div = max_ref_div = pll->reference_div;

915

else {

915

else {

916

while (min_ref_div < max_ref_div-1) {

916

while (min_ref_div < max_ref_div-1) {

917

uint32_t mid = (min_ref_div + max_ref_div) / 2;

917

uint32_t mid = (min_ref_div + max_ref_div) / 2;

918

uint32_t pll_in = pll->reference_freq / mid;

918

uint32_t pll_in = pll->reference_freq / mid;

919

if (pll_in < pll->pll_in_min)

919

if (pll_in < pll->pll_in_min)

920

max_ref_div = mid;

920

max_ref_div = mid;

921

else if (pll_in > pll->pll_in_max)

921

else if (pll_in > pll->pll_in_max)

922

min_ref_div = mid;

922

min_ref_div = mid;

923

else

923

else

924

break;

924

break;

925

}

925

}

926

}

926

}

927

928

if (pll->flags & RADEON_PLL_USE_POST_DIV)

928

if (pll->flags & RADEON_PLL_USE_POST_DIV)

929

min_post_div = max_post_div = pll->post_div;

929

min_post_div = max_post_div = pll->post_div;

930

931

if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {

931

if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {

932

min_fractional_feed_div = pll->min_frac_feedback_div;

932

min_fractional_feed_div = pll->min_frac_feedback_div;

933

max_fractional_feed_div = pll->max_frac_feedback_div;

933

max_fractional_feed_div = pll->max_frac_feedback_div;

934

}

934

}

935

936

for (post_div = max_post_div; post_div >= min_post_div; --post_div) {

936

for (post_div = max_post_div; post_div >= min_post_div; --post_div) {

937

uint32_t ref_div;

937

uint32_t ref_div;

938

939

if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))

939

if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))

940

continue;

940

continue;

941

942

/* legacy radeons only have a few post_divs */

942

/* legacy radeons only have a few post_divs */

943

if (pll->flags & RADEON_PLL_LEGACY) {

943

if (pll->flags & RADEON_PLL_LEGACY) {

944

if ((post_div == 5) ||

944

if ((post_div == 5) ||

945

(post_div == 7) ||

945

(post_div == 7) ||

946

(post_div == 9) ||

946

(post_div == 9) ||

947

(post_div == 10) ||

947

(post_div == 10) ||

948

(post_div == 11) ||

948

(post_div == 11) ||

949

(post_div == 13) ||

949

(post_div == 13) ||

950

(post_div == 14) ||

950

(post_div == 14) ||

951

(post_div == 15))

951

(post_div == 15))

952

continue;

952

continue;

953

}

953

}

954

955

for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {

955

for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {

956

uint32_t feedback_div, current_freq = 0, error, vco_diff;

956

uint32_t feedback_div, current_freq = 0, error, vco_diff;

957

uint32_t pll_in = pll->reference_freq / ref_div;

957

uint32_t pll_in = pll->reference_freq / ref_div;

958

uint32_t min_feed_div = pll->min_feedback_div;

958

uint32_t min_feed_div = pll->min_feedback_div;

959

uint32_t max_feed_div = pll->max_feedback_div + 1;

959

uint32_t max_feed_div = pll->max_feedback_div + 1;

960

961

if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)

961

if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)

962

continue;

962

continue;

963

964

while (min_feed_div < max_feed_div) {

964

while (min_feed_div < max_feed_div) {

965

uint32_t vco;

965

uint32_t vco;

966

uint32_t min_frac_feed_div = min_fractional_feed_div;

966

uint32_t min_frac_feed_div = min_fractional_feed_div;

967

uint32_t max_frac_feed_div = max_fractional_feed_div + 1;

967

uint32_t max_frac_feed_div = max_fractional_feed_div + 1;

968

uint32_t frac_feedback_div;

968

uint32_t frac_feedback_div;

969

uint64_t tmp;

969

uint64_t tmp;

970

971

feedback_div = (min_feed_div + max_feed_div) / 2;

971

feedback_div = (min_feed_div + max_feed_div) / 2;

972

973

tmp = (uint64_t)pll->reference_freq * feedback_div;

973

tmp = (uint64_t)pll->reference_freq * feedback_div;

974

vco = radeon_div(tmp, ref_div);

974

vco = radeon_div(tmp, ref_div);

975

976

if (vco < pll_out_min) {

976

if (vco < pll_out_min) {

977

min_feed_div = feedback_div + 1;

977

min_feed_div = feedback_div + 1;

978

continue;

978

continue;

979

} else if (vco > pll_out_max) {

979

} else if (vco > pll_out_max) {

980

max_feed_div = feedback_div;

980

max_feed_div = feedback_div;

981

continue;

981

continue;

982

}

982

}

983

984

while (min_frac_feed_div < max_frac_feed_div) {

984

while (min_frac_feed_div < max_frac_feed_div) {

985

frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;

985

frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;

986

tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;

986

tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;

987

tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;

987

tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;

988

current_freq = radeon_div(tmp, ref_div * post_div);

988

current_freq = radeon_div(tmp, ref_div * post_div);

989

990

if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {

990

if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {

991

if (freq < current_freq)

991

if (freq < current_freq)

992

error = 0xffffffff;

992

error = 0xffffffff;

993

else

993

else

994

error = freq - current_freq;

994

error = freq - current_freq;

995

} else

995

} else

996

error = abs(current_freq - freq);

996

error = abs(current_freq - freq);

997

vco_diff = abs(vco - best_vco);

997

vco_diff = abs(vco - best_vco);

998

999

if ((best_vco == 0 && error < best_error) ||

999

if ((best_vco == 0 && error < best_error) ||

1000

(best_vco != 0 &&

1000

(best_vco != 0 &&

1001

((best_error > 100 && error < best_error - 100) ||

1001

((best_error > 100 && error < best_error - 100) ||

1002

(abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {

1002

(abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {

1003

best_post_div = post_div;

1003

best_post_div = post_div;

1004

best_ref_div = ref_div;

1004

best_ref_div = ref_div;

1005

best_feedback_div = feedback_div;

1005

best_feedback_div = feedback_div;

1006

best_frac_feedback_div = frac_feedback_div;

1006

best_frac_feedback_div = frac_feedback_div;

1007

best_freq = current_freq;

1007

best_freq = current_freq;

1008

best_error = error;

1008

best_error = error;

1009

best_vco_diff = vco_diff;

1009

best_vco_diff = vco_diff;

1010

} else if (current_freq == freq) {

1010

} else if (current_freq == freq) {

1011

if (best_freq == -1) {

1011

if (best_freq == -1) {

1012

best_post_div = post_div;

1012

best_post_div = post_div;

1013

best_ref_div = ref_div;

1013

best_ref_div = ref_div;

1014

best_feedback_div = feedback_div;

1014

best_feedback_div = feedback_div;

1015

best_frac_feedback_div = frac_feedback_div;

1015

best_frac_feedback_div = frac_feedback_div;

1016

best_freq = current_freq;

1016

best_freq = current_freq;

1017

best_error = error;

1017

best_error = error;

1018

best_vco_diff = vco_diff;

1018

best_vco_diff = vco_diff;

1019

} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||

1019

} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||

1020

((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||

1020

((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||

1021

((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||

1021

((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||

1022

((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||

1022

((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||

1023

((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||

1023

((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||

1024

((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {

1024

((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {

1025

best_post_div = post_div;

1025

best_post_div = post_div;

1026

best_ref_div = ref_div;

1026

best_ref_div = ref_div;

1027

best_feedback_div = feedback_div;

1027

best_feedback_div = feedback_div;

1028

best_frac_feedback_div = frac_feedback_div;

1028

best_frac_feedback_div = frac_feedback_div;

1029

best_freq = current_freq;

1029

best_freq = current_freq;

1030

best_error = error;

1030

best_error = error;

1031

best_vco_diff = vco_diff;

1031

best_vco_diff = vco_diff;

1032

}

1032

}

1033

}

1033

}

1034

if (current_freq < freq)

1034

if (current_freq < freq)

1035

min_frac_feed_div = frac_feedback_div + 1;

1035

min_frac_feed_div = frac_feedback_div + 1;

1036

else

1036

else

1037

max_frac_feed_div = frac_feedback_div;

1037

max_frac_feed_div = frac_feedback_div;

1038

}

1038

}

1039

if (current_freq < freq)

1039

if (current_freq < freq)

1040

min_feed_div = feedback_div + 1;

1040

min_feed_div = feedback_div + 1;

1041

else

1041

else

1042

max_feed_div = feedback_div;

1042

max_feed_div = feedback_div;

1043

}

1043

}

1044

}

1044

}

1045

}

1045

}

1046

1047

*dot_clock_p = best_freq / 10000;

1047

*dot_clock_p = best_freq / 10000;

1048

*fb_div_p = best_feedback_div;

1048

*fb_div_p = best_feedback_div;

1049

*frac_fb_div_p = best_frac_feedback_div;

1049

*frac_fb_div_p = best_frac_feedback_div;

1050

*ref_div_p = best_ref_div;

1050

*ref_div_p = best_ref_div;

1051

*post_div_p = best_post_div;

1051

*post_div_p = best_post_div;

1052

DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",

1052

DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",

1053

(long long)freq,

1053

(long long)freq,

1054

best_freq / 1000, best_feedback_div, best_frac_feedback_div,

1054

best_freq / 1000, best_feedback_div, best_frac_feedback_div,

1055

best_ref_div, best_post_div);

1055

best_ref_div, best_post_div);

1056

1057

}

1057

}

1058

1059

static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)

1059

static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)

1060

{

1060

{

1061

struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);

1061

struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);

1062

1063

if (radeon_fb->obj) {

1063

if (radeon_fb->obj) {

1064

drm_gem_object_unreference_unlocked(radeon_fb->obj);

1064

drm_gem_object_unreference_unlocked(radeon_fb->obj);

1065

}

1065

}

1066

drm_framebuffer_cleanup(fb);

1066

drm_framebuffer_cleanup(fb);

1067

kfree(radeon_fb);

1067

kfree(radeon_fb);

1068

}

1068

}

1069

1070

static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,

1070

static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,

1071

struct drm_file *file_priv,

1071

struct drm_file *file_priv,

1072

unsigned int *handle)

1072

unsigned int *handle)

1073

{

1073

{

1074

struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);

1074

struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);

1075

1076

return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);

1076

return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);

1077

}

1077

}

1078

1079

static const struct drm_framebuffer_funcs radeon_fb_funcs = {

1079

static const struct drm_framebuffer_funcs radeon_fb_funcs = {

1080

.destroy = radeon_user_framebuffer_destroy,

1080

.destroy = radeon_user_framebuffer_destroy,

1081

.create_handle = radeon_user_framebuffer_create_handle,

1081

.create_handle = radeon_user_framebuffer_create_handle,

1082

};

1082

};

1083

1084

int

1084

int

1085

radeon_framebuffer_init(struct drm_device *dev,

1085

radeon_framebuffer_init(struct drm_device *dev,

1086

struct radeon_framebuffer *rfb,

1086

struct radeon_framebuffer *rfb,

1087

struct drm_mode_fb_cmd2 *mode_cmd,

1087

struct drm_mode_fb_cmd2 *mode_cmd,

1088

struct drm_gem_object *obj)

1088

struct drm_gem_object *obj)

1089

{

1089

{

1090

int ret;

1090

int ret;

1091

rfb->obj = obj;

1091

rfb->obj = obj;

1092

ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);

1092

ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);

1093

if (ret) {

1093

if (ret) {

1094

rfb->obj = NULL;

1094

rfb->obj = NULL;

1095

return ret;

1095

return ret;

1096

}

1096

}

1097

drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);

1097

drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);

1098

return 0;

1098

return 0;

1099

}

1099

}

1100

1101

static struct drm_framebuffer *

1101

static struct drm_framebuffer *

1102

radeon_user_framebuffer_create(struct drm_device *dev,

1102

radeon_user_framebuffer_create(struct drm_device *dev,

1103

struct drm_file *file_priv,

1103

struct drm_file *file_priv,

1104

struct drm_mode_fb_cmd2 *mode_cmd)

1104

struct drm_mode_fb_cmd2 *mode_cmd)

1105

{

1105

{

1106

struct drm_gem_object *obj;

1106

struct drm_gem_object *obj;

1107

struct radeon_framebuffer *radeon_fb;

1107

struct radeon_framebuffer *radeon_fb;

1108

int ret;

1108

int ret;

1109

1110

obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);

1110

obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);

1111

if (obj == NULL) {

1111

if (obj == NULL) {

1112

dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "

1112

dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "

1113

"can't create framebuffer\n", mode_cmd->handles[0]);

1113

"can't create framebuffer\n", mode_cmd->handles[0]);

1114

return ERR_PTR(-ENOENT);

1114

return ERR_PTR(-ENOENT);

1115

}

1115

}

1116

1117

radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);

1117

radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);

1118

if (radeon_fb == NULL)

1118

if (radeon_fb == NULL) {

1119

drm_gem_object_unreference_unlocked(obj);

1119

return ERR_PTR(-ENOMEM);

1120

return ERR_PTR(-ENOMEM);

1121

}

1120

1122

1121

ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);

1123

ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);

1122

if (ret) {

1124

if (ret) {

1123

kfree(radeon_fb);

1125

kfree(radeon_fb);

1124

drm_gem_object_unreference_unlocked(obj);

1126

drm_gem_object_unreference_unlocked(obj);

1125

return ERR_PTR(ret);

1127

return ERR_PTR(ret);

1126

}

1128

}

1127

1129

1128

return &radeon_fb->base;

1130

return &radeon_fb->base;

1129

}

1131

}

1130

1132

1131

static void radeon_output_poll_changed(struct drm_device *dev)

1133

static void radeon_output_poll_changed(struct drm_device *dev)

1132

{

1134

{

1133

struct radeon_device *rdev = dev->dev_private;

1135

struct radeon_device *rdev = dev->dev_private;

1134

radeon_fb_output_poll_changed(rdev);

1136

radeon_fb_output_poll_changed(rdev);

1135

}

1137

}

1136

1138

1137

static const struct drm_mode_config_funcs radeon_mode_funcs = {

1139

static const struct drm_mode_config_funcs radeon_mode_funcs = {

1138

.fb_create = radeon_user_framebuffer_create,

1140

.fb_create = radeon_user_framebuffer_create,

1139

.output_poll_changed = radeon_output_poll_changed

1141

.output_poll_changed = radeon_output_poll_changed

1140

};

1142

};

1141

1143

1142

static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =

1144

static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =

1143

{ { 0, "driver" },

1145

{ { 0, "driver" },

1144

{ 1, "bios" },

1146

{ 1, "bios" },

1145

};

1147

};

1146

1148

1147

static struct drm_prop_enum_list radeon_tv_std_enum_list[] =

1149

static struct drm_prop_enum_list radeon_tv_std_enum_list[] =

1148

{ { TV_STD_NTSC, "ntsc" },

1150

{ { TV_STD_NTSC, "ntsc" },

1149

{ TV_STD_PAL, "pal" },

1151

{ TV_STD_PAL, "pal" },

1150

{ TV_STD_PAL_M, "pal-m" },

1152

{ TV_STD_PAL_M, "pal-m" },

1151

{ TV_STD_PAL_60, "pal-60" },

1153

{ TV_STD_PAL_60, "pal-60" },

1152

{ TV_STD_NTSC_J, "ntsc-j" },

1154

{ TV_STD_NTSC_J, "ntsc-j" },

1153

{ TV_STD_SCART_PAL, "scart-pal" },

1155

{ TV_STD_SCART_PAL, "scart-pal" },

1154

{ TV_STD_PAL_CN, "pal-cn" },

1156

{ TV_STD_PAL_CN, "pal-cn" },

1155

{ TV_STD_SECAM, "secam" },

1157

{ TV_STD_SECAM, "secam" },

1156

};

1158

};

1157

1159

1158

static struct drm_prop_enum_list radeon_underscan_enum_list[] =

1160

static struct drm_prop_enum_list radeon_underscan_enum_list[] =

1159

{ { UNDERSCAN_OFF, "off" },

1161

{ { UNDERSCAN_OFF, "off" },

1160

{ UNDERSCAN_ON, "on" },

1162

{ UNDERSCAN_ON, "on" },

1161

{ UNDERSCAN_AUTO, "auto" },

1163

{ UNDERSCAN_AUTO, "auto" },

1162

};

1164

};

1163

1165

1164

static int radeon_modeset_create_props(struct radeon_device *rdev)

1166

static int radeon_modeset_create_props(struct radeon_device *rdev)

1165

{

1167

{

1166

int sz;

1168

int sz;

1167

1169

1168

if (rdev->is_atom_bios) {

1170

if (rdev->is_atom_bios) {

1169

rdev->mode_info.coherent_mode_property =

1171

rdev->mode_info.coherent_mode_property =

1170

drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);

1172

drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);

1171

if (!rdev->mode_info.coherent_mode_property)

1173

if (!rdev->mode_info.coherent_mode_property)

1172

return -ENOMEM;

1174

return -ENOMEM;

1173

}

1175

}

1174

1176

1175

if (!ASIC_IS_AVIVO(rdev)) {

1177

if (!ASIC_IS_AVIVO(rdev)) {

1176

sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);

1178

sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);

1177

rdev->mode_info.tmds_pll_property =

1179

rdev->mode_info.tmds_pll_property =

1178

drm_property_create_enum(rdev->ddev, 0,

1180

drm_property_create_enum(rdev->ddev, 0,

1179

"tmds_pll",

1181

"tmds_pll",

1180

radeon_tmds_pll_enum_list, sz);

1182

radeon_tmds_pll_enum_list, sz);

1181

}

1183

}

1182

1184

1183

rdev->mode_info.load_detect_property =

1185

rdev->mode_info.load_detect_property =

1184

drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);

1186

drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);

1185

if (!rdev->mode_info.load_detect_property)

1187

if (!rdev->mode_info.load_detect_property)

1186

return -ENOMEM;

1188

return -ENOMEM;

1187

1189

1188

drm_mode_create_scaling_mode_property(rdev->ddev);

1190

drm_mode_create_scaling_mode_property(rdev->ddev);

1189

1191

1190

sz = ARRAY_SIZE(radeon_tv_std_enum_list);

1192

sz = ARRAY_SIZE(radeon_tv_std_enum_list);

1191

rdev->mode_info.tv_std_property =

1193

rdev->mode_info.tv_std_property =

1192

drm_property_create_enum(rdev->ddev, 0,

1194

drm_property_create_enum(rdev->ddev, 0,

1193

"tv standard",

1195

"tv standard",

1194

radeon_tv_std_enum_list, sz);

1196

radeon_tv_std_enum_list, sz);

1195

1197

1196

sz = ARRAY_SIZE(radeon_underscan_enum_list);

1198

sz = ARRAY_SIZE(radeon_underscan_enum_list);

1197

rdev->mode_info.underscan_property =

1199

rdev->mode_info.underscan_property =

1198

drm_property_create_enum(rdev->ddev, 0,

1200

drm_property_create_enum(rdev->ddev, 0,

1199

"underscan",

1201

"underscan",

1200

radeon_underscan_enum_list, sz);

1202

radeon_underscan_enum_list, sz);

1201

1203

1202

rdev->mode_info.underscan_hborder_property =

1204

rdev->mode_info.underscan_hborder_property =

1203

drm_property_create_range(rdev->ddev, 0,

1205

drm_property_create_range(rdev->ddev, 0,

1204

"underscan hborder", 0, 128);

1206

"underscan hborder", 0, 128);

1205

if (!rdev->mode_info.underscan_hborder_property)

1207

if (!rdev->mode_info.underscan_hborder_property)

1206

return -ENOMEM;

1208

return -ENOMEM;

1207

1209

1208

rdev->mode_info.underscan_vborder_property =

1210

rdev->mode_info.underscan_vborder_property =

1209

drm_property_create_range(rdev->ddev, 0,

1211

drm_property_create_range(rdev->ddev, 0,

1210

"underscan vborder", 0, 128);

1212

"underscan vborder", 0, 128);

1211

if (!rdev->mode_info.underscan_vborder_property)

1213

if (!rdev->mode_info.underscan_vborder_property)

1212

return -ENOMEM;

1214

return -ENOMEM;

1213

1215

1214

return 0;

1216

return 0;

1215

}

1217

}

1216

1218

1217

void radeon_update_display_priority(struct radeon_device *rdev)

1219

void radeon_update_display_priority(struct radeon_device *rdev)

1218

{

1220

{

1219

/* adjustment options for the display watermarks */

1221

/* adjustment options for the display watermarks */

1220

if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {

1222

if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {

1221

/* set display priority to high for r3xx, rv515 chips

1223

/* set display priority to high for r3xx, rv515 chips

1222

* this avoids flickering due to underflow to the

1224

* this avoids flickering due to underflow to the

1223

* display controllers during heavy acceleration.

1225

* display controllers during heavy acceleration.

1224

* Don't force high on rs4xx igp chips as it seems to

1226

* Don't force high on rs4xx igp chips as it seems to

1225

* affect the sound card. See kernel bug 15982.

1227

* affect the sound card. See kernel bug 15982.

1226

*/

1228

*/

1227

if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&

1229

if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&

1228

!(rdev->flags & RADEON_IS_IGP))

1230

!(rdev->flags & RADEON_IS_IGP))

1229

rdev->disp_priority = 2;

1231

rdev->disp_priority = 2;

1230

else

1232

else

1231

rdev->disp_priority = 0;

1233

rdev->disp_priority = 0;

1232

} else

1234

} else

1233

rdev->disp_priority = radeon_disp_priority;

1235

rdev->disp_priority = radeon_disp_priority;

1234

1236

1235

}

1237

}

1236

1238

1237

/*

1239

/*

1238

* Allocate hdmi structs and determine register offsets

1240

* Allocate hdmi structs and determine register offsets

1239

*/

1241

*/

1240

static void radeon_afmt_init(struct radeon_device *rdev)

1242

static void radeon_afmt_init(struct radeon_device *rdev)

1241

{

1243

{

1242

int i;

1244

int i;

1243

1245

1244

for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)

1246

for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)

1245

rdev->mode_info.afmt[i] = NULL;

1247

rdev->mode_info.afmt[i] = NULL;

1246

1248

1247

if (ASIC_IS_DCE6(rdev)) {

1249

if (ASIC_IS_DCE6(rdev)) {

1248

/* todo */

1250

/* todo */

1249

} else if (ASIC_IS_DCE4(rdev)) {

1251

} else if (ASIC_IS_DCE4(rdev)) {

1250

/* DCE4/5 has 6 audio blocks tied to DIG encoders */

1252

/* DCE4/5 has 6 audio blocks tied to DIG encoders */

1251

/* DCE4.1 has 2 audio blocks tied to DIG encoders */

1253

/* DCE4.1 has 2 audio blocks tied to DIG encoders */

1252

rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1254

rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1253

if (rdev->mode_info.afmt[0]) {

1255

if (rdev->mode_info.afmt[0]) {

1254

rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;

1256

rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;

1255

rdev->mode_info.afmt[0]->id = 0;

1257

rdev->mode_info.afmt[0]->id = 0;

1256

}

1258

}

1257

rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1259

rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1258

if (rdev->mode_info.afmt[1]) {

1260

if (rdev->mode_info.afmt[1]) {

1259

rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;

1261

rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;

1260

rdev->mode_info.afmt[1]->id = 1;

1262

rdev->mode_info.afmt[1]->id = 1;

1261

}

1263

}

1262

if (!ASIC_IS_DCE41(rdev)) {

1264

if (!ASIC_IS_DCE41(rdev)) {

1263

rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1265

rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1264

if (rdev->mode_info.afmt[2]) {

1266

if (rdev->mode_info.afmt[2]) {

1265

rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;

1267

rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;

1266

rdev->mode_info.afmt[2]->id = 2;

1268

rdev->mode_info.afmt[2]->id = 2;

1267

}

1269

}

1268

rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1270

rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1269

if (rdev->mode_info.afmt[3]) {

1271

if (rdev->mode_info.afmt[3]) {

1270

rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;

1272

rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;

1271

rdev->mode_info.afmt[3]->id = 3;

1273

rdev->mode_info.afmt[3]->id = 3;

1272

}

1274

}

1273

rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1275

rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1274

if (rdev->mode_info.afmt[4]) {

1276

if (rdev->mode_info.afmt[4]) {

1275

rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;

1277

rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;

1276

rdev->mode_info.afmt[4]->id = 4;

1278

rdev->mode_info.afmt[4]->id = 4;

1277

}

1279

}

1278

rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1280

rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1279

if (rdev->mode_info.afmt[5]) {

1281

if (rdev->mode_info.afmt[5]) {

1280

rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;

1282

rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;

1281

rdev->mode_info.afmt[5]->id = 5;

1283

rdev->mode_info.afmt[5]->id = 5;

1282

}

1284

}

1283

}

1285

}

1284

} else if (ASIC_IS_DCE3(rdev)) {

1286

} else if (ASIC_IS_DCE3(rdev)) {

1285

/* DCE3.x has 2 audio blocks tied to DIG encoders */

1287

/* DCE3.x has 2 audio blocks tied to DIG encoders */

1286

rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1288

rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1287

if (rdev->mode_info.afmt[0]) {

1289

if (rdev->mode_info.afmt[0]) {

1288

rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;

1290

rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;

1289

rdev->mode_info.afmt[0]->id = 0;

1291

rdev->mode_info.afmt[0]->id = 0;

1290

}

1292

}

1291

rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1293

rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1292

if (rdev->mode_info.afmt[1]) {

1294

if (rdev->mode_info.afmt[1]) {

1293

rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;

1295

rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;

1294

rdev->mode_info.afmt[1]->id = 1;

1296

rdev->mode_info.afmt[1]->id = 1;

1295

}

1297

}

1296

} else if (ASIC_IS_DCE2(rdev)) {

1298

} else if (ASIC_IS_DCE2(rdev)) {

1297

/* DCE2 has at least 1 routable audio block */

1299

/* DCE2 has at least 1 routable audio block */

1298

rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1300

rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1299

if (rdev->mode_info.afmt[0]) {

1301

if (rdev->mode_info.afmt[0]) {

1300

rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;

1302

rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;

1301

rdev->mode_info.afmt[0]->id = 0;

1303

rdev->mode_info.afmt[0]->id = 0;

1302

}

1304

}

1303

/* r6xx has 2 routable audio blocks */

1305

/* r6xx has 2 routable audio blocks */

1304

if (rdev->family >= CHIP_R600) {

1306

if (rdev->family >= CHIP_R600) {

1305

rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1307

rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);

1306

if (rdev->mode_info.afmt[1]) {

1308

if (rdev->mode_info.afmt[1]) {

1307

rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;

1309

rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;

1308

rdev->mode_info.afmt[1]->id = 1;

1310

rdev->mode_info.afmt[1]->id = 1;

1309

}

1311

}

1310

}

1312

}

1311

}

1313

}

1312

}

1314

}

1313

1315

1314

static void radeon_afmt_fini(struct radeon_device *rdev)

1316

static void radeon_afmt_fini(struct radeon_device *rdev)

1315

{

1317

{

1316

int i;

1318

int i;

1317

1319

1318

for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {

1320

for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {

1319

kfree(rdev->mode_info.afmt[i]);

1321

kfree(rdev->mode_info.afmt[i]);

1320

rdev->mode_info.afmt[i] = NULL;

1322

rdev->mode_info.afmt[i] = NULL;

1321

}

1323

}

1322

}

1324

}

1323

1325

1324

int radeon_modeset_init(struct radeon_device *rdev)

1326

int radeon_modeset_init(struct radeon_device *rdev)

1325

{

1327

{

1326

int i;

1328

int i;

1327

int ret;

1329

int ret;

1328

1330

1329

drm_mode_config_init(rdev->ddev);

1331

drm_mode_config_init(rdev->ddev);

1330

rdev->mode_info.mode_config_initialized = true;

1332

rdev->mode_info.mode_config_initialized = true;

1331

1333

1332

rdev->ddev->mode_config.funcs = &radeon_mode_funcs;

1334

rdev->ddev->mode_config.funcs = &radeon_mode_funcs;

1333

1335

1334

if (ASIC_IS_DCE5(rdev)) {

1336

if (ASIC_IS_DCE5(rdev)) {

1335

rdev->ddev->mode_config.max_width = 16384;

1337

rdev->ddev->mode_config.max_width = 16384;

1336

rdev->ddev->mode_config.max_height = 16384;

1338

rdev->ddev->mode_config.max_height = 16384;

1337

} else if (ASIC_IS_AVIVO(rdev)) {

1339

} else if (ASIC_IS_AVIVO(rdev)) {

1338

rdev->ddev->mode_config.max_width = 8192;

1340

rdev->ddev->mode_config.max_width = 8192;

1339

rdev->ddev->mode_config.max_height = 8192;

1341

rdev->ddev->mode_config.max_height = 8192;

1340

} else {

1342

} else {

1341

rdev->ddev->mode_config.max_width = 4096;

1343

rdev->ddev->mode_config.max_width = 4096;

1342

rdev->ddev->mode_config.max_height = 4096;

1344

rdev->ddev->mode_config.max_height = 4096;

1343

}

1345

}

1344

1346

1345

rdev->ddev->mode_config.preferred_depth = 24;

1347

rdev->ddev->mode_config.preferred_depth = 24;

1346

rdev->ddev->mode_config.prefer_shadow = 1;

1348

rdev->ddev->mode_config.prefer_shadow = 1;

1347

1349

1348

rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;

1350

rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;

1349

1351

1350

ret = radeon_modeset_create_props(rdev);

1352

ret = radeon_modeset_create_props(rdev);

1351

if (ret) {

1353

if (ret) {

1352

return ret;

1354

return ret;

1353

}

1355

}

1354

1356

1355

/* init i2c buses */

1357

/* init i2c buses */

1356

radeon_i2c_init(rdev);

1358

radeon_i2c_init(rdev);

1357

1359

1358

/* check combios for a valid hardcoded EDID - Sun servers */

1360

/* check combios for a valid hardcoded EDID - Sun servers */

1359

if (!rdev->is_atom_bios) {

1361

if (!rdev->is_atom_bios) {

1360

/* check for hardcoded EDID in BIOS */

1362

/* check for hardcoded EDID in BIOS */

1361

radeon_combios_check_hardcoded_edid(rdev);

1363

radeon_combios_check_hardcoded_edid(rdev);

1362

}

1364

}

1363

1365

1364

/* allocate crtcs */

1366

/* allocate crtcs */

1365

for (i = 0; i < rdev->num_crtc; i++) {

1367

for (i = 0; i < rdev->num_crtc; i++) {

1366

radeon_crtc_init(rdev->ddev, i);

1368

radeon_crtc_init(rdev->ddev, i);

1367

}

1369

}

1368

1370

1369

/* okay we should have all the bios connectors */

1371

/* okay we should have all the bios connectors */

1370

ret = radeon_setup_enc_conn(rdev->ddev);

1372

ret = radeon_setup_enc_conn(rdev->ddev);

1371

if (!ret) {

1373

if (!ret) {

1372

return ret;

1374

return ret;

1373

}

1375

}

1374

1376

1375

/* init dig PHYs, disp eng pll */

1377

/* init dig PHYs, disp eng pll */

1376

if (rdev->is_atom_bios) {

1378

if (rdev->is_atom_bios) {

1377

radeon_atom_encoder_init(rdev);

1379

radeon_atom_encoder_init(rdev);

1378

radeon_atom_disp_eng_pll_init(rdev);

1380

radeon_atom_disp_eng_pll_init(rdev);

1379

}

1381

}

1380

1382

1381

/* initialize hpd */

1383

/* initialize hpd */

1382

radeon_hpd_init(rdev);

1384

radeon_hpd_init(rdev);

1383

1385

1384

/* setup afmt */

1386

/* setup afmt */

1385

radeon_afmt_init(rdev);

1387

radeon_afmt_init(rdev);

1386

1388

1387

/* Initialize power management */

1389

/* Initialize power management */

1388

radeon_pm_init(rdev);

1390

radeon_pm_init(rdev);

1389

1391

1390

radeon_fbdev_init(rdev);

1392

radeon_fbdev_init(rdev);

1391

drm_kms_helper_poll_init(rdev->ddev);

1393

drm_kms_helper_poll_init(rdev->ddev);

1392

1394

1393

return 0;

1395

return 0;

1394

}

1396

}

1395

1397

1396

void radeon_modeset_fini(struct radeon_device *rdev)

1398

void radeon_modeset_fini(struct radeon_device *rdev)

1397

{

1399

{

1398

radeon_fbdev_fini(rdev);

1400

radeon_fbdev_fini(rdev);

1399

kfree(rdev->mode_info.bios_hardcoded_edid);

1401

kfree(rdev->mode_info.bios_hardcoded_edid);

1400

radeon_pm_fini(rdev);

1402

radeon_pm_fini(rdev);

1401

1403

1402

if (rdev->mode_info.mode_config_initialized) {

1404

if (rdev->mode_info.mode_config_initialized) {

1403

radeon_afmt_fini(rdev);

1405

radeon_afmt_fini(rdev);

1404

drm_kms_helper_poll_fini(rdev->ddev);

1406

drm_kms_helper_poll_fini(rdev->ddev);

1405

radeon_hpd_fini(rdev);

1407

radeon_hpd_fini(rdev);

1406

drm_mode_config_cleanup(rdev->ddev);

1408

drm_mode_config_cleanup(rdev->ddev);

1407

rdev->mode_info.mode_config_initialized = false;

1409

rdev->mode_info.mode_config_initialized = false;

1408

}

1410

}

1409

/* free i2c buses */

1411

/* free i2c buses */

1410

radeon_i2c_fini(rdev);

1412

radeon_i2c_fini(rdev);

1411

}

1413

}

1412

1414

1413

static bool is_hdtv_mode(const struct drm_display_mode *mode)

1415

static bool is_hdtv_mode(const struct drm_display_mode *mode)

1414

{

1416

{

1415

/* try and guess if this is a tv or a monitor */

1417

/* try and guess if this is a tv or a monitor */

1416

if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */

1418

if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */

1417

(mode->vdisplay == 576) || /* 576p */

1419

(mode->vdisplay == 576) || /* 576p */

1418

(mode->vdisplay == 720) || /* 720p */

1420

(mode->vdisplay == 720) || /* 720p */

1419

(mode->vdisplay == 1080)) /* 1080p */

1421

(mode->vdisplay == 1080)) /* 1080p */

1420

return true;

1422

return true;

1421

else

1423

else

1422

return false;

1424

return false;

1423

}

1425

}

1424

1426

1425

bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,

1427

bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,

1426

const struct drm_display_mode *mode,

1428

const struct drm_display_mode *mode,

1427

struct drm_display_mode *adjusted_mode)

1429

struct drm_display_mode *adjusted_mode)

1428

{

1430

{

1429

struct drm_device *dev = crtc->dev;

1431

struct drm_device *dev = crtc->dev;

1430

struct radeon_device *rdev = dev->dev_private;

1432

struct radeon_device *rdev = dev->dev_private;

1431

struct drm_encoder *encoder;

1433

struct drm_encoder *encoder;

1432

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

1434

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

1433

struct radeon_encoder *radeon_encoder;

1435

struct radeon_encoder *radeon_encoder;

1434

struct drm_connector *connector;

1436

struct drm_connector *connector;

1435

struct radeon_connector *radeon_connector;

1437

struct radeon_connector *radeon_connector;

1436

bool first = true;

1438

bool first = true;

1437

u32 src_v = 1, dst_v = 1;

1439

u32 src_v = 1, dst_v = 1;

1438

u32 src_h = 1, dst_h = 1;

1440

u32 src_h = 1, dst_h = 1;

1439

1441

1440

radeon_crtc->h_border = 0;

1442

radeon_crtc->h_border = 0;

1441

radeon_crtc->v_border = 0;

1443

radeon_crtc->v_border = 0;

1442

1444

1443

list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {

1445

list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {

1444

if (encoder->crtc != crtc)

1446

if (encoder->crtc != crtc)

1445

continue;

1447

continue;

1446

radeon_encoder = to_radeon_encoder(encoder);

1448

radeon_encoder = to_radeon_encoder(encoder);

1447

connector = radeon_get_connector_for_encoder(encoder);

1449

connector = radeon_get_connector_for_encoder(encoder);

1448

radeon_connector = to_radeon_connector(connector);

1450

radeon_connector = to_radeon_connector(connector);

1449

1451

1450

if (first) {

1452

if (first) {

1451

/* set scaling */

1453

/* set scaling */

1452

if (radeon_encoder->rmx_type == RMX_OFF)

1454

if (radeon_encoder->rmx_type == RMX_OFF)

1453

radeon_crtc->rmx_type = RMX_OFF;

1455

radeon_crtc->rmx_type = RMX_OFF;

1454

else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||

1456

else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||

1455

mode->vdisplay < radeon_encoder->native_mode.vdisplay)

1457

mode->vdisplay < radeon_encoder->native_mode.vdisplay)

1456

radeon_crtc->rmx_type = radeon_encoder->rmx_type;

1458

radeon_crtc->rmx_type = radeon_encoder->rmx_type;

1457

else

1459

else

1458

radeon_crtc->rmx_type = RMX_OFF;

1460

radeon_crtc->rmx_type = RMX_OFF;

1459

/* copy native mode */

1461

/* copy native mode */

1460

memcpy(&radeon_crtc->native_mode,

1462

memcpy(&radeon_crtc->native_mode,

1461

&radeon_encoder->native_mode,

1463

&radeon_encoder->native_mode,

1462

sizeof(struct drm_display_mode));

1464

sizeof(struct drm_display_mode));

1463

src_v = crtc->mode.vdisplay;

1465

src_v = crtc->mode.vdisplay;

1464

dst_v = radeon_crtc->native_mode.vdisplay;

1466

dst_v = radeon_crtc->native_mode.vdisplay;

1465

src_h = crtc->mode.hdisplay;

1467

src_h = crtc->mode.hdisplay;

1466

dst_h = radeon_crtc->native_mode.hdisplay;

1468

dst_h = radeon_crtc->native_mode.hdisplay;

1467

1469

1468

/* fix up for overscan on hdmi */

1470

/* fix up for overscan on hdmi */

1469

if (ASIC_IS_AVIVO(rdev) &&

1471

if (ASIC_IS_AVIVO(rdev) &&

1470

(!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&

1472

(!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&

1471

((radeon_encoder->underscan_type == UNDERSCAN_ON) ||

1473

((radeon_encoder->underscan_type == UNDERSCAN_ON) ||

1472

((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&

1474

((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&

1473

drm_detect_hdmi_monitor(radeon_connector->edid) &&

1475

drm_detect_hdmi_monitor(radeon_connector->edid) &&

1474

is_hdtv_mode(mode)))) {

1476

is_hdtv_mode(mode)))) {

1475

if (radeon_encoder->underscan_hborder != 0)

1477

if (radeon_encoder->underscan_hborder != 0)

1476

radeon_crtc->h_border = radeon_encoder->underscan_hborder;

1478

radeon_crtc->h_border = radeon_encoder->underscan_hborder;

1477

else

1479

else

1478

radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;

1480

radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;

1479

if (radeon_encoder->underscan_vborder != 0)

1481

if (radeon_encoder->underscan_vborder != 0)

1480

radeon_crtc->v_border = radeon_encoder->underscan_vborder;

1482

radeon_crtc->v_border = radeon_encoder->underscan_vborder;

1481

else

1483

else

1482

radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;

1484

radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;

1483

radeon_crtc->rmx_type = RMX_FULL;

1485

radeon_crtc->rmx_type = RMX_FULL;

1484

src_v = crtc->mode.vdisplay;

1486

src_v = crtc->mode.vdisplay;

1485

dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);

1487

dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);

1486

src_h = crtc->mode.hdisplay;

1488

src_h = crtc->mode.hdisplay;

1487

dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);

1489

dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);

1488

}

1490

}

1489

first = false;

1491

first = false;

1490

} else {

1492

} else {

1491

if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {

1493

if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {

1492

/* WARNING: Right now this can't happen but

1494

/* WARNING: Right now this can't happen but

1493

* in the future we need to check that scaling

1495

* in the future we need to check that scaling

1494

* are consistent across different encoder

1496

* are consistent across different encoder

1495

* (ie all encoder can work with the same

1497

* (ie all encoder can work with the same

1496

* scaling).

1498

* scaling).

1497

*/

1499

*/

1498

DRM_ERROR("Scaling not consistent across encoder.\n");

1500

DRM_ERROR("Scaling not consistent across encoder.\n");

1499

return false;

1501

return false;

1500

}

1502

}

1501

}

1503

}

1502

}

1504

}

1503

if (radeon_crtc->rmx_type != RMX_OFF) {

1505

if (radeon_crtc->rmx_type != RMX_OFF) {

1504

fixed20_12 a, b;

1506

fixed20_12 a, b;

1505

a.full = dfixed_const(src_v);

1507

a.full = dfixed_const(src_v);

1506

b.full = dfixed_const(dst_v);

1508

b.full = dfixed_const(dst_v);

1507

radeon_crtc->vsc.full = dfixed_div(a, b);

1509

radeon_crtc->vsc.full = dfixed_div(a, b);

1508

a.full = dfixed_const(src_h);

1510

a.full = dfixed_const(src_h);

1509

b.full = dfixed_const(dst_h);

1511

b.full = dfixed_const(dst_h);

1510

radeon_crtc->hsc.full = dfixed_div(a, b);

1512

radeon_crtc->hsc.full = dfixed_div(a, b);

1511

} else {

1513

} else {

1512

radeon_crtc->vsc.full = dfixed_const(1);

1514

radeon_crtc->vsc.full = dfixed_const(1);

1513

radeon_crtc->hsc.full = dfixed_const(1);

1515

radeon_crtc->hsc.full = dfixed_const(1);

1514

}

1516

}

1515

return true;

1517

return true;

1516

}

1518

}

1517

1519

1518

/*

1520

/*

1519

* Retrieve current video scanout position of crtc on a given gpu.

1521

* Retrieve current video scanout position of crtc on a given gpu.

1520

*

1522

*

1521

* \param dev Device to query.

1523

* \param dev Device to query.

1522

* \param crtc Crtc to query.

1524

* \param crtc Crtc to query.

1523

* \param *vpos Location where vertical scanout position should be stored.

1525

* \param *vpos Location where vertical scanout position should be stored.

1524

* \param *hpos Location where horizontal scanout position should go.

1526

* \param *hpos Location where horizontal scanout position should go.

1525

*

1527

*

1526

* Returns vpos as a positive number while in active scanout area.

1528

* Returns vpos as a positive number while in active scanout area.

1527

* Returns vpos as a negative number inside vblank, counting the number

1529

* Returns vpos as a negative number inside vblank, counting the number

1528

* of scanlines to go until end of vblank, e.g., -1 means "one scanline

1530

* of scanlines to go until end of vblank, e.g., -1 means "one scanline

1529

* until start of active scanout / end of vblank."

1531

* until start of active scanout / end of vblank."

1530

*

1532

*

1531

* \return Flags, or'ed together as follows:

1533

* \return Flags, or'ed together as follows:

1532

*

1534

*

1533

* DRM_SCANOUTPOS_VALID = Query successful.

1535

* DRM_SCANOUTPOS_VALID = Query successful.

1534

* DRM_SCANOUTPOS_INVBL = Inside vblank.

1536

* DRM_SCANOUTPOS_INVBL = Inside vblank.

1535

* DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of

1537

* DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of

1536

* this flag means that returned position may be offset by a constant but

1538

* this flag means that returned position may be offset by a constant but

1537

* unknown small number of scanlines wrt. real scanout position.

1539

* unknown small number of scanlines wrt. real scanout position.

1538

*

1540

*

1539

*/

1541

*/

1540

int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)

1542

int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)

1541

{

1543

{

1542

u32 stat_crtc = 0, vbl = 0, position = 0;

1544

u32 stat_crtc = 0, vbl = 0, position = 0;

1543

int vbl_start, vbl_end, vtotal, ret = 0;

1545

int vbl_start, vbl_end, vtotal, ret = 0;

1544

bool in_vbl = true;

1546

bool in_vbl = true;

1545

1547

1546

struct radeon_device *rdev = dev->dev_private;

1548

struct radeon_device *rdev = dev->dev_private;

1547

1549

1548

if (ASIC_IS_DCE4(rdev)) {

1550

if (ASIC_IS_DCE4(rdev)) {

1549

if (crtc == 0) {

1551

if (crtc == 0) {

1550

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

1552

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

1551

EVERGREEN_CRTC0_REGISTER_OFFSET);

1553

EVERGREEN_CRTC0_REGISTER_OFFSET);

1552

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

1554

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

1553

EVERGREEN_CRTC0_REGISTER_OFFSET);

1555

EVERGREEN_CRTC0_REGISTER_OFFSET);

1554

ret |= DRM_SCANOUTPOS_VALID;

1556

ret |= DRM_SCANOUTPOS_VALID;

1555

}

1557

}

1556

if (crtc == 1) {

1558

if (crtc == 1) {

1557

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

1559

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

1558

EVERGREEN_CRTC1_REGISTER_OFFSET);

1560

EVERGREEN_CRTC1_REGISTER_OFFSET);

1559

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

1561

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

1560

EVERGREEN_CRTC1_REGISTER_OFFSET);

1562

EVERGREEN_CRTC1_REGISTER_OFFSET);

1561

ret |= DRM_SCANOUTPOS_VALID;

1563

ret |= DRM_SCANOUTPOS_VALID;

1562

}

1564

}

1563

if (crtc == 2) {

1565

if (crtc == 2) {

1564

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

1566

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

1565

EVERGREEN_CRTC2_REGISTER_OFFSET);

1567

EVERGREEN_CRTC2_REGISTER_OFFSET);

1566

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

1568

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

1567

EVERGREEN_CRTC2_REGISTER_OFFSET);

1569

EVERGREEN_CRTC2_REGISTER_OFFSET);

1568

ret |= DRM_SCANOUTPOS_VALID;

1570

ret |= DRM_SCANOUTPOS_VALID;

1569

}

1571

}

1570

if (crtc == 3) {

1572

if (crtc == 3) {

1571

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

1573

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

1572

EVERGREEN_CRTC3_REGISTER_OFFSET);

1574

EVERGREEN_CRTC3_REGISTER_OFFSET);

1573

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

1575

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

1574

EVERGREEN_CRTC3_REGISTER_OFFSET);

1576

EVERGREEN_CRTC3_REGISTER_OFFSET);

1575

ret |= DRM_SCANOUTPOS_VALID;

1577

ret |= DRM_SCANOUTPOS_VALID;

1576

}

1578

}

1577

if (crtc == 4) {

1579

if (crtc == 4) {

1578

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

1580

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

1579

EVERGREEN_CRTC4_REGISTER_OFFSET);

1581

EVERGREEN_CRTC4_REGISTER_OFFSET);

1580

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

1582

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

1581

EVERGREEN_CRTC4_REGISTER_OFFSET);

1583

EVERGREEN_CRTC4_REGISTER_OFFSET);

1582

ret |= DRM_SCANOUTPOS_VALID;

1584

ret |= DRM_SCANOUTPOS_VALID;

1583

}

1585

}

1584

if (crtc == 5) {

1586

if (crtc == 5) {

1585

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

1587

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

1586

EVERGREEN_CRTC5_REGISTER_OFFSET);

1588

EVERGREEN_CRTC5_REGISTER_OFFSET);

1587

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

1589

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

1588

EVERGREEN_CRTC5_REGISTER_OFFSET);

1590

EVERGREEN_CRTC5_REGISTER_OFFSET);

1589

ret |= DRM_SCANOUTPOS_VALID;

1591

ret |= DRM_SCANOUTPOS_VALID;

1590

}

1592

}

1591

} else if (ASIC_IS_AVIVO(rdev)) {

1593

} else if (ASIC_IS_AVIVO(rdev)) {

1592

if (crtc == 0) {

1594

if (crtc == 0) {

1593

vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);

1595

vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);

1594

position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);

1596

position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);

1595

ret |= DRM_SCANOUTPOS_VALID;

1597

ret |= DRM_SCANOUTPOS_VALID;

1596

}

1598

}

1597

if (crtc == 1) {

1599

if (crtc == 1) {

1598

vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);

1600

vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);

1599

position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);

1601

position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);

1600

ret |= DRM_SCANOUTPOS_VALID;

1602

ret |= DRM_SCANOUTPOS_VALID;

1601

}

1603

}

1602

} else {

1604

} else {

1603

/* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */

1605

/* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */

1604

if (crtc == 0) {

1606

if (crtc == 0) {

1605

/* Assume vbl_end == 0, get vbl_start from

1607

/* Assume vbl_end == 0, get vbl_start from

1606

* upper 16 bits.

1608

* upper 16 bits.

1607

*/

1609

*/

1608

vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &

1610

vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &

1609

RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;

1611

RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;

1610

/* Only retrieve vpos from upper 16 bits, set hpos == 0. */

1612

/* Only retrieve vpos from upper 16 bits, set hpos == 0. */

1611

position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;

1613

position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;

1612

stat_crtc = RREG32(RADEON_CRTC_STATUS);

1614

stat_crtc = RREG32(RADEON_CRTC_STATUS);

1613

if (!(stat_crtc & 1))

1615

if (!(stat_crtc & 1))

1614

in_vbl = false;

1616

in_vbl = false;

1615

1617

1616

ret |= DRM_SCANOUTPOS_VALID;

1618

ret |= DRM_SCANOUTPOS_VALID;

1617

}

1619

}

1618

if (crtc == 1) {

1620

if (crtc == 1) {

1619

vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &

1621

vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &

1620

RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;

1622

RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;

1621

position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;

1623

position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;

1622

stat_crtc = RREG32(RADEON_CRTC2_STATUS);

1624

stat_crtc = RREG32(RADEON_CRTC2_STATUS);

1623

if (!(stat_crtc & 1))

1625

if (!(stat_crtc & 1))

1624

in_vbl = false;

1626

in_vbl = false;

1625

1627

1626

ret |= DRM_SCANOUTPOS_VALID;

1628

ret |= DRM_SCANOUTPOS_VALID;

1627

}

1629

}

1628

}

1630

}

1629

1631

1630

/* Decode into vertical and horizontal scanout position. */

1632

/* Decode into vertical and horizontal scanout position. */

1631

*vpos = position & 0x1fff;

1633

*vpos = position & 0x1fff;

1632

*hpos = (position >> 16) & 0x1fff;

1634

*hpos = (position >> 16) & 0x1fff;

1633

1635

1634

/* Valid vblank area boundaries from gpu retrieved? */

1636

/* Valid vblank area boundaries from gpu retrieved? */

1635

if (vbl > 0) {

1637

if (vbl > 0) {

1636

/* Yes: Decode. */

1638

/* Yes: Decode. */

1637

ret |= DRM_SCANOUTPOS_ACCURATE;

1639

ret |= DRM_SCANOUTPOS_ACCURATE;

1638

vbl_start = vbl & 0x1fff;

1640

vbl_start = vbl & 0x1fff;

1639

vbl_end = (vbl >> 16) & 0x1fff;

1641

vbl_end = (vbl >> 16) & 0x1fff;

1640

}

1642

}

1641

else {

1643

else {

1642

/* No: Fake something reasonable which gives at least ok results. */

1644

/* No: Fake something reasonable which gives at least ok results. */

1643

vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;

1645

vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;

1644

vbl_end = 0;

1646

vbl_end = 0;

1645

}

1647

}

1646

1648

1647

/* Test scanout position against vblank region. */

1649

/* Test scanout position against vblank region. */

1648

if ((*vpos < vbl_start) && (*vpos >= vbl_end))

1650

if ((*vpos < vbl_start) && (*vpos >= vbl_end))

1649

in_vbl = false;

1651

in_vbl = false;

1650

1652

1651

/* Check if inside vblank area and apply corrective offsets:

1653

/* Check if inside vblank area and apply corrective offsets:

1652

* vpos will then be >=0 in video scanout area, but negative

1654

* vpos will then be >=0 in video scanout area, but negative

1653

* within vblank area, counting down the number of lines until

1655

* within vblank area, counting down the number of lines until

1654

* start of scanout.

1656

* start of scanout.

1655

*/

1657

*/

1656

1658

1657

/* Inside "upper part" of vblank area? Apply corrective offset if so: */

1659

/* Inside "upper part" of vblank area? Apply corrective offset if so: */

1658

if (in_vbl && (*vpos >= vbl_start)) {

1660

if (in_vbl && (*vpos >= vbl_start)) {

1659

vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;

1661

vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;

1660

*vpos = *vpos - vtotal;

1662

*vpos = *vpos - vtotal;

1661

}

1663

}

1662

1664

1663

/* Correct for shifted end of vbl at vbl_end. */

1665

/* Correct for shifted end of vbl at vbl_end. */

1664

*vpos = *vpos - vbl_end;

1666

*vpos = *vpos - vbl_end;

1665

1667

1666

/* In vblank? */

1668

/* In vblank? */

1667

if (in_vbl)

1669

if (in_vbl)

1668

ret |= DRM_SCANOUTPOS_INVBL;

1670

ret |= DRM_SCANOUTPOS_INVBL;

1669

1671

1670

return ret;

1672

return ret;

1671

}

1673

}

1672

1674

GITLAB

drm/radeon: Calling object_unrefer() when creating fb failure

 /*
  * Copyright 2007-8 Advanced Micro Devices, Inc.
  * Copyright 2008 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Dave Airlie
  *          Alex Deucher
  */
 #include <drm/drmP.h>
 #include <drm/radeon_drm.h>
 #include "radeon.h"
 #include "atom.h"
 #include <asm/div64.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_edid.h>
 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int i;
 	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 	WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
 	WREG32(AVIVO_DC_LUT_RW_MODE, 0);
 	WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
 	WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
 	for (i = 0; i < 256; i++) {
 		WREG32(AVIVO_DC_LUT_30_COLOR,
 			     (radeon_crtc->lut_r[i] << 20) |
 			     (radeon_crtc->lut_g[i] << 10) |
 			     (radeon_crtc->lut_b[i] << 0));
 	}
 	WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
 }
 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int i;
 	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 	for (i = 0; i < 256; i++) {
 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 		       (radeon_crtc->lut_r[i] << 20) |
 		       (radeon_crtc->lut_g[i] << 10) |
 		       (radeon_crtc->lut_b[i] << 0));
 	}
 }
 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int i;
 	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 	       (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 		NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 	WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 	       NI_GRPH_PRESCALE_BYPASS);
 	WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 	       NI_OVL_PRESCALE_BYPASS);
 	WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 	       (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 		NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 	for (i = 0; i < 256; i++) {
 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 		       (radeon_crtc->lut_r[i] << 20) |
 		       (radeon_crtc->lut_g[i] << 10) |
 		       (radeon_crtc->lut_b[i] << 0));
 	}
 	WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 	       (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 		NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 		NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 		NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 	WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 	       (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 		NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 	WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 	       (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 		NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 	WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 	       (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 		NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
 	WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 }
 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int i;
 	uint32_t dac2_cntl;
 	dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 	if (radeon_crtc->crtc_id == 0)
 		dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 	else
 		dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 	WREG8(RADEON_PALETTE_INDEX, 0);
 	for (i = 0; i < 256; i++) {
 		WREG32(RADEON_PALETTE_30_DATA,
 			     (radeon_crtc->lut_r[i] << 20) |
 			     (radeon_crtc->lut_g[i] << 10) |
 			     (radeon_crtc->lut_b[i] << 0));
 	}
 }
 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	if (!crtc->enabled)
 		return;
 	if (ASIC_IS_DCE5(rdev))
 		dce5_crtc_load_lut(crtc);
 	else if (ASIC_IS_DCE4(rdev))
 		dce4_crtc_load_lut(crtc);
 	else if (ASIC_IS_AVIVO(rdev))
 		avivo_crtc_load_lut(crtc);
 	else
 		legacy_crtc_load_lut(crtc);
 }
 /** Sets the color ramps on behalf of fbcon */
 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 			      u16 blue, int regno)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	radeon_crtc->lut_r[regno] = red >> 6;
 	radeon_crtc->lut_g[regno] = green >> 6;
 	radeon_crtc->lut_b[regno] = blue >> 6;
 }
 /** Gets the color ramps on behalf of fbcon */
 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 			      u16 *blue, int regno)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	*red = radeon_crtc->lut_r[regno] << 6;
 	*green = radeon_crtc->lut_g[regno] << 6;
 	*blue = radeon_crtc->lut_b[regno] << 6;
 }
 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 				  u16 *blue, uint32_t start, uint32_t size)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	int end = (start + size > 256) ? 256 : start + size, i;
 	/* userspace palettes are always correct as is */
 	for (i = start; i < end; i++) {
 		radeon_crtc->lut_r[i] = red[i] >> 6;
 		radeon_crtc->lut_g[i] = green[i] >> 6;
 		radeon_crtc->lut_b[i] = blue[i] >> 6;
 	}
 	radeon_crtc_load_lut(crtc);
 }
 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	drm_crtc_cleanup(crtc);
 	kfree(radeon_crtc);
 }
 /*
  * Handle unpin events outside the interrupt handler proper.
  */
 static void radeon_unpin_work_func(struct work_struct *__work)
 {
 	struct radeon_unpin_work *work =
 		container_of(__work, struct radeon_unpin_work, work);
 	int r;
 	/* unpin of the old buffer */
 	r = radeon_bo_reserve(work->old_rbo, false);
 	if (likely(r == 0)) {
 		r = radeon_bo_unpin(work->old_rbo);
 		if (unlikely(r != 0)) {
 			DRM_ERROR("failed to unpin buffer after flip\n");
 		}
 		radeon_bo_unreserve(work->old_rbo);
 	} else
 		DRM_ERROR("failed to reserve buffer after flip\n");
 	drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 	kfree(work);
 }
 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 {
 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 	struct radeon_unpin_work *work;
 	struct drm_pending_vblank_event *e;
 	struct timeval now;
 	unsigned long flags;
 	u32 update_pending;
 	int vpos, hpos;
 	spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 	work = radeon_crtc->unpin_work;
 	if (work == NULL ||
 	    (work->fence && !radeon_fence_signaled(work->fence))) {
 		spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 		return;
 	}
 	/* New pageflip, or just completion of a previous one? */
 	if (!radeon_crtc->deferred_flip_completion) {
 		/* do the flip (mmio) */
 		update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 	} else {
 		/* This is just a completion of a flip queued in crtc
 		 * at last invocation. Make sure we go directly to
 		 * completion routine.
 		 */
 		update_pending = 0;
 		radeon_crtc->deferred_flip_completion = 0;
 	}
 	/* Has the pageflip already completed in crtc, or is it certain
 	 * to complete in this vblank?
 	 */
 	if (update_pending &&
 	    (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 							       &vpos, &hpos)) &&
 	    ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 	     (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 		/* crtc didn't flip in this target vblank interval,
 		 * but flip is pending in crtc. Based on the current
 		 * scanout position we know that the current frame is
 		 * (nearly) complete and the flip will (likely)
 		 * complete before the start of the next frame.
 		 */
 		update_pending = 0;
 	}
 	if (update_pending) {
 		/* crtc didn't flip in this target vblank interval,
 		 * but flip is pending in crtc. It will complete it
 		 * in next vblank interval, so complete the flip at
 		 * next vblank irq.
 		 */
 		radeon_crtc->deferred_flip_completion = 1;
 		spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 		return;
 	}
 	/* Pageflip (will be) certainly completed in this vblank. Clean up. */
 	radeon_crtc->unpin_work = NULL;
 	/* wakeup userspace */
 	if (work->event) {
 		e = work->event;
 		e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
 		e->event.tv_sec = now.tv_sec;
 		e->event.tv_usec = now.tv_usec;
 		list_add_tail(&e->base.link, &e->base.file_priv->event_list);
 		wake_up_interruptible(&e->base.file_priv->event_wait);
 	}
 	spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 	drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 	radeon_fence_unref(&work->fence);
 	radeon_post_page_flip(work->rdev, work->crtc_id);
 	schedule_work(&work->work);
 }
 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 				 struct drm_framebuffer *fb,
 				 struct drm_pending_vblank_event *event)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct radeon_framebuffer *old_radeon_fb;
 	struct radeon_framebuffer *new_radeon_fb;
 	struct drm_gem_object *obj;
 	struct radeon_bo *rbo;
 	struct radeon_unpin_work *work;
 	unsigned long flags;
 	u32 tiling_flags, pitch_pixels;
 	u64 base;
 	int r;
 	work = kzalloc(sizeof *work, GFP_KERNEL);
 	if (work == NULL)
 		return -ENOMEM;
 	work->event = event;
 	work->rdev = rdev;
 	work->crtc_id = radeon_crtc->crtc_id;
 	old_radeon_fb = to_radeon_framebuffer(crtc->fb);
 	new_radeon_fb = to_radeon_framebuffer(fb);
 	/* schedule unpin of the old buffer */
 	obj = old_radeon_fb->obj;
 	/* take a reference to the old object */
 	drm_gem_object_reference(obj);
 	rbo = gem_to_radeon_bo(obj);
 	work->old_rbo = rbo;
 	obj = new_radeon_fb->obj;
 	rbo = gem_to_radeon_bo(obj);
 	spin_lock(&rbo->tbo.bdev->fence_lock);
 	if (rbo->tbo.sync_obj)
 		work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 	spin_unlock(&rbo->tbo.bdev->fence_lock);
 	INIT_WORK(&work->work, radeon_unpin_work_func);
 	/* We borrow the event spin lock for protecting unpin_work */
 	spin_lock_irqsave(&dev->event_lock, flags);
 	if (radeon_crtc->unpin_work) {
 		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 		r = -EBUSY;
 		goto unlock_free;
 	}
 	radeon_crtc->unpin_work = work;
 	radeon_crtc->deferred_flip_completion = 0;
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	/* pin the new buffer */
 	DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 			 work->old_rbo, rbo);
 	r = radeon_bo_reserve(rbo, false);
 	if (unlikely(r != 0)) {
 		DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 		goto pflip_cleanup;
 	}
 	/* Only 27 bit offset for legacy CRTC */
 	r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
 				     ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 	if (unlikely(r != 0)) {
 		radeon_bo_unreserve(rbo);
 		r = -EINVAL;
 		DRM_ERROR("failed to pin new rbo buffer before flip\n");
 		goto pflip_cleanup;
 	}
 	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 	radeon_bo_unreserve(rbo);
 	if (!ASIC_IS_AVIVO(rdev)) {
 		/* crtc offset is from display base addr not FB location */
 		base -= radeon_crtc->legacy_display_base_addr;
 		pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 		if (tiling_flags & RADEON_TILING_MACRO) {
 			if (ASIC_IS_R300(rdev)) {
 				base &= ~0x7ff;
 			} else {
 				int byteshift = fb->bits_per_pixel >> 4;
 				int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 				base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 			}
 		} else {
 			int offset = crtc->y * pitch_pixels + crtc->x;
 			switch (fb->bits_per_pixel) {
 			case 8:
 			default:
 				offset *= 1;
 				break;
 			case 15:
 			case 16:
 				offset *= 2;
 				break;
 			case 24:
 				offset *= 3;
 				break;
 			case 32:
 				offset *= 4;
 				break;
 			}
 			base += offset;
 		}
 		base &= ~7;
 	}
 	spin_lock_irqsave(&dev->event_lock, flags);
 	work->new_crtc_base = base;
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	/* update crtc fb */
 	crtc->fb = fb;
 	r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 	if (r) {
 		DRM_ERROR("failed to get vblank before flip\n");
 		goto pflip_cleanup1;
 	}
 	/* set the proper interrupt */
 	radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 	return 0;
 pflip_cleanup1:
 	if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
 		DRM_ERROR("failed to reserve new rbo in error path\n");
 		goto pflip_cleanup;
 	}
 	if (unlikely(radeon_bo_unpin(rbo) != 0)) {
 		DRM_ERROR("failed to unpin new rbo in error path\n");
 	}
 	radeon_bo_unreserve(rbo);
 pflip_cleanup:
 	spin_lock_irqsave(&dev->event_lock, flags);
 	radeon_crtc->unpin_work = NULL;
 unlock_free:
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 	radeon_fence_unref(&work->fence);
 	kfree(work);
 	return r;
 }
 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 	.cursor_set = radeon_crtc_cursor_set,
 	.cursor_move = radeon_crtc_cursor_move,
 	.gamma_set = radeon_crtc_gamma_set,
 	.set_config = drm_crtc_helper_set_config,
 	.destroy = radeon_crtc_destroy,
 	.page_flip = radeon_crtc_page_flip,
 };
 static void radeon_crtc_init(struct drm_device *dev, int index)
 {
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_crtc *radeon_crtc;
 	int i;
 	radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 	if (radeon_crtc == NULL)
 		return;
 	drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 	drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 	radeon_crtc->crtc_id = index;
 	rdev->mode_info.crtcs[index] = radeon_crtc;
 #if 0
 	radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 	radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 	radeon_crtc->mode_set.num_connectors = 0;
 #endif
 	for (i = 0; i < 256; i++) {
 		radeon_crtc->lut_r[i] = i << 2;
 		radeon_crtc->lut_g[i] = i << 2;
 		radeon_crtc->lut_b[i] = i << 2;
 	}
 	if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 		radeon_atombios_init_crtc(dev, radeon_crtc);
 	else
 		radeon_legacy_init_crtc(dev, radeon_crtc);
 }
 static const char *encoder_names[37] = {
 	"NONE",
 	"INTERNAL_LVDS",
 	"INTERNAL_TMDS1",
 	"INTERNAL_TMDS2",
 	"INTERNAL_DAC1",
 	"INTERNAL_DAC2",
 	"INTERNAL_SDVOA",
 	"INTERNAL_SDVOB",
 	"SI170B",
 	"CH7303",
 	"CH7301",
 	"INTERNAL_DVO1",
 	"EXTERNAL_SDVOA",
 	"EXTERNAL_SDVOB",
 	"TITFP513",
 	"INTERNAL_LVTM1",
 	"VT1623",
 	"HDMI_SI1930",
 	"HDMI_INTERNAL",
 	"INTERNAL_KLDSCP_TMDS1",
 	"INTERNAL_KLDSCP_DVO1",
 	"INTERNAL_KLDSCP_DAC1",
 	"INTERNAL_KLDSCP_DAC2",
 	"SI178",
 	"MVPU_FPGA",
 	"INTERNAL_DDI",
 	"VT1625",
 	"HDMI_SI1932",
 	"DP_AN9801",
 	"DP_DP501",
 	"INTERNAL_UNIPHY",
 	"INTERNAL_KLDSCP_LVTMA",
 	"INTERNAL_UNIPHY1",
 	"INTERNAL_UNIPHY2",
 	"NUTMEG",
 	"TRAVIS",
 	"INTERNAL_VCE"
 };
 static const char *hpd_names[6] = {
 	"HPD1",
 	"HPD2",
 	"HPD3",
 	"HPD4",
 	"HPD5",
 	"HPD6",
 };
 static void radeon_print_display_setup(struct drm_device *dev)
 {
 	struct drm_connector *connector;
 	struct radeon_connector *radeon_connector;
 	struct drm_encoder *encoder;
 	struct radeon_encoder *radeon_encoder;
 	uint32_t devices;
 	int i = 0;
 	DRM_INFO("Radeon Display Connectors\n");
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		radeon_connector = to_radeon_connector(connector);
 		DRM_INFO("Connector %d:\n", i);
 		DRM_INFO("  %s\n", drm_get_connector_name(connector));
 		if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 			DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 		if (radeon_connector->ddc_bus) {
 			DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 				 radeon_connector->ddc_bus->rec.mask_clk_reg,
 				 radeon_connector->ddc_bus->rec.mask_data_reg,
 				 radeon_connector->ddc_bus->rec.a_clk_reg,
 				 radeon_connector->ddc_bus->rec.a_data_reg,
 				 radeon_connector->ddc_bus->rec.en_clk_reg,
 				 radeon_connector->ddc_bus->rec.en_data_reg,
 				 radeon_connector->ddc_bus->rec.y_clk_reg,
 				 radeon_connector->ddc_bus->rec.y_data_reg);
 			if (radeon_connector->router.ddc_valid)
 				DRM_INFO("  DDC Router 0x%x/0x%x\n",
 					 radeon_connector->router.ddc_mux_control_pin,
 					 radeon_connector->router.ddc_mux_state);
 			if (radeon_connector->router.cd_valid)
 				DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 					 radeon_connector->router.cd_mux_control_pin,
 					 radeon_connector->router.cd_mux_state);
 		} else {
 			if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 			    connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 			    connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 			    connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 				DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 		}
 		DRM_INFO("  Encoders:\n");
 		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 			radeon_encoder = to_radeon_encoder(encoder);
 			devices = radeon_encoder->devices & radeon_connector->devices;
 			if (devices) {
 				if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 					DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 					DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 					DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 					DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 					DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 					DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 					DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 					DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 					DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_TV1_SUPPORT)
 					DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_CV_SUPPORT)
 					DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 			}
 		}
 		i++;
 	}
 }
 static bool radeon_setup_enc_conn(struct drm_device *dev)
 {
 	struct radeon_device *rdev = dev->dev_private;
 	bool ret = false;
 	if (rdev->bios) {
 		if (rdev->is_atom_bios) {
 			ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 			if (ret == false)
 				ret = radeon_get_atom_connector_info_from_object_table(dev);
 		} else {
 			ret = radeon_get_legacy_connector_info_from_bios(dev);
 			if (ret == false)
 				ret = radeon_get_legacy_connector_info_from_table(dev);
 		}
 	} else {
 		if (!ASIC_IS_AVIVO(rdev))
 			ret = radeon_get_legacy_connector_info_from_table(dev);
 	}
 	if (ret) {
 		radeon_setup_encoder_clones(dev);
 		radeon_print_display_setup(dev);
 	}
 	return ret;
 }
 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 {
 	struct drm_device *dev = radeon_connector->base.dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int ret = 0;
 	/* on hw with routers, select right port */
 	if (radeon_connector->router.ddc_valid)
 		radeon_router_select_ddc_port(radeon_connector);
 	if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 	    ENCODER_OBJECT_ID_NONE) {
 		struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 		if (dig->dp_i2c_bus)
 			radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 							      &dig->dp_i2c_bus->adapter);
 	} else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 		   (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 		struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 		if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 		     dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 			radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 							      &dig->dp_i2c_bus->adapter);
 		else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 			radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 							      &radeon_connector->ddc_bus->adapter);
 	} else {
 		if (radeon_connector->ddc_bus && !radeon_connector->edid)
 			radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 							      &radeon_connector->ddc_bus->adapter);
 	}
 	if (!radeon_connector->edid) {
 		if (rdev->is_atom_bios) {
 			/* some laptops provide a hardcoded edid in rom for LCDs */
 			if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 			     (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 				radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 		} else
 			/* some servers provide a hardcoded edid in rom for KVMs */
 			radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 	}
 	if (radeon_connector->edid) {
 		drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 		ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 		return ret;
 	}
 	drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 	return 0;
 }
 /* avivo */
 static void avivo_get_fb_div(struct radeon_pll *pll,
 			     u32 target_clock,
 			     u32 post_div,
 			     u32 ref_div,
 			     u32 *fb_div,
 			     u32 *frac_fb_div)
 {
 	u32 tmp = post_div * ref_div;
 	tmp *= target_clock;
 	*fb_div = tmp / pll->reference_freq;
 	*frac_fb_div = tmp % pll->reference_freq;
         if (*fb_div > pll->max_feedback_div)
 		*fb_div = pll->max_feedback_div;
         else if (*fb_div < pll->min_feedback_div)
                 *fb_div = pll->min_feedback_div;
 }
 static u32 avivo_get_post_div(struct radeon_pll *pll,
 			      u32 target_clock)
 {
 	u32 vco, post_div, tmp;
 	if (pll->flags & RADEON_PLL_USE_POST_DIV)
 		return pll->post_div;
 	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 		if (pll->flags & RADEON_PLL_IS_LCD)
 			vco = pll->lcd_pll_out_min;
 		else
 			vco = pll->pll_out_min;
 	} else {
 		if (pll->flags & RADEON_PLL_IS_LCD)
 			vco = pll->lcd_pll_out_max;
 		else
 			vco = pll->pll_out_max;
 	}
 	post_div = vco / target_clock;
 	tmp = vco % target_clock;
 	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 		if (tmp)
 			post_div++;
 	} else {
 		if (!tmp)
 			post_div--;
 	}
 	if (post_div > pll->max_post_div)
 		post_div = pll->max_post_div;
 	else if (post_div < pll->min_post_div)
 		post_div = pll->min_post_div;
 	return post_div;
 }
 #define MAX_TOLERANCE 10
 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 			      u32 freq,
 			      u32 *dot_clock_p,
 			      u32 *fb_div_p,
 			      u32 *frac_fb_div_p,
 			      u32 *ref_div_p,
 			      u32 *post_div_p)
 {
 	u32 target_clock = freq / 10;
 	u32 post_div = avivo_get_post_div(pll, target_clock);
 	u32 ref_div = pll->min_ref_div;
 	u32 fb_div = 0, frac_fb_div = 0, tmp;
 	if (pll->flags & RADEON_PLL_USE_REF_DIV)
 		ref_div = pll->reference_div;
 	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 		avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
 		frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
 		if (frac_fb_div >= 5) {
 			frac_fb_div -= 5;
 			frac_fb_div = frac_fb_div / 10;
 			frac_fb_div++;
 		}
 		if (frac_fb_div >= 10) {
 			fb_div++;
 			frac_fb_div = 0;
 		}
 	} else {
 		while (ref_div <= pll->max_ref_div) {
 			avivo_get_fb_div(pll, target_clock, post_div, ref_div,
 					 &fb_div, &frac_fb_div);
 			if (frac_fb_div >= (pll->reference_freq / 2))
 				fb_div++;
 			frac_fb_div = 0;
 			tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
 			tmp = (tmp * 10000) / target_clock;
 			if (tmp > (10000 + MAX_TOLERANCE))
 				ref_div++;
 			else if (tmp >= (10000 - MAX_TOLERANCE))
 				break;
 			else
 				ref_div++;
 		}
 	}
 	*dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
 		(ref_div * post_div * 10);
 	*fb_div_p = fb_div;
 	*frac_fb_div_p = frac_fb_div;
 	*ref_div_p = ref_div;
 	*post_div_p = post_div;
 	DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 		      *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
 }
 /* pre-avivo */
 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 {
 	uint64_t mod;
 	n += d / 2;
 	mod = do_div(n, d);
 	return n;
 }
 void radeon_compute_pll_legacy(struct radeon_pll *pll,
 			       uint64_t freq,
 			       uint32_t *dot_clock_p,
 			       uint32_t *fb_div_p,
 			       uint32_t *frac_fb_div_p,
 			       uint32_t *ref_div_p,
 			       uint32_t *post_div_p)
 {
 	uint32_t min_ref_div = pll->min_ref_div;
 	uint32_t max_ref_div = pll->max_ref_div;
 	uint32_t min_post_div = pll->min_post_div;
 	uint32_t max_post_div = pll->max_post_div;
 	uint32_t min_fractional_feed_div = 0;
 	uint32_t max_fractional_feed_div = 0;
 	uint32_t best_vco = pll->best_vco;
 	uint32_t best_post_div = 1;
 	uint32_t best_ref_div = 1;
 	uint32_t best_feedback_div = 1;
 	uint32_t best_frac_feedback_div = 0;
 	uint32_t best_freq = -1;
 	uint32_t best_error = 0xffffffff;
 	uint32_t best_vco_diff = 1;
 	uint32_t post_div;
 	u32 pll_out_min, pll_out_max;
 	DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 	freq = freq * 1000;
 	if (pll->flags & RADEON_PLL_IS_LCD) {
 		pll_out_min = pll->lcd_pll_out_min;
 		pll_out_max = pll->lcd_pll_out_max;
 	} else {
 		pll_out_min = pll->pll_out_min;
 		pll_out_max = pll->pll_out_max;
 	}
 	if (pll_out_min > 64800)
 		pll_out_min = 64800;
 	if (pll->flags & RADEON_PLL_USE_REF_DIV)
 		min_ref_div = max_ref_div = pll->reference_div;
 	else {
 		while (min_ref_div < max_ref_div-1) {
 			uint32_t mid = (min_ref_div + max_ref_div) / 2;
 			uint32_t pll_in = pll->reference_freq / mid;
 			if (pll_in < pll->pll_in_min)
 				max_ref_div = mid;
 			else if (pll_in > pll->pll_in_max)
 				min_ref_div = mid;
 			else
 				break;
 		}
 	}
 	if (pll->flags & RADEON_PLL_USE_POST_DIV)
 		min_post_div = max_post_div = pll->post_div;
 	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 		min_fractional_feed_div = pll->min_frac_feedback_div;
 		max_fractional_feed_div = pll->max_frac_feedback_div;
 	}
 	for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
 		uint32_t ref_div;
 		if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 			continue;
 		/* legacy radeons only have a few post_divs */
 		if (pll->flags & RADEON_PLL_LEGACY) {
 			if ((post_div == 5) ||
 			    (post_div == 7) ||
 			    (post_div == 9) ||
 			    (post_div == 10) ||
 			    (post_div == 11) ||
 			    (post_div == 13) ||
 			    (post_div == 14) ||
 			    (post_div == 15))
 				continue;
 		}
 		for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 			uint32_t feedback_div, current_freq = 0, error, vco_diff;
 			uint32_t pll_in = pll->reference_freq / ref_div;
 			uint32_t min_feed_div = pll->min_feedback_div;
 			uint32_t max_feed_div = pll->max_feedback_div + 1;
 			if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 				continue;
 			while (min_feed_div < max_feed_div) {
 				uint32_t vco;
 				uint32_t min_frac_feed_div = min_fractional_feed_div;
 				uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 				uint32_t frac_feedback_div;
 				uint64_t tmp;
 				feedback_div = (min_feed_div + max_feed_div) / 2;
 				tmp = (uint64_t)pll->reference_freq * feedback_div;
 				vco = radeon_div(tmp, ref_div);
 				if (vco < pll_out_min) {
 					min_feed_div = feedback_div + 1;
 					continue;
 				} else if (vco > pll_out_max) {
 					max_feed_div = feedback_div;
 					continue;
 				}
 				while (min_frac_feed_div < max_frac_feed_div) {
 					frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 					tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 					tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 					current_freq = radeon_div(tmp, ref_div * post_div);
 					if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 						if (freq < current_freq)
 							error = 0xffffffff;
 						else
 							error = freq - current_freq;
 					} else
 						error = abs(current_freq - freq);
 					vco_diff = abs(vco - best_vco);
 					if ((best_vco == 0 && error < best_error) ||
 					    (best_vco != 0 &&
 					     ((best_error > 100 && error < best_error - 100) ||
 					      (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
 						best_post_div = post_div;
 						best_ref_div = ref_div;
 						best_feedback_div = feedback_div;
 						best_frac_feedback_div = frac_feedback_div;
 						best_freq = current_freq;
 						best_error = error;
 						best_vco_diff = vco_diff;
 					} else if (current_freq == freq) {
 						if (best_freq == -1) {
 							best_post_div = post_div;
 							best_ref_div = ref_div;
 							best_feedback_div = feedback_div;
 							best_frac_feedback_div = frac_feedback_div;
 							best_freq = current_freq;
 							best_error = error;
 							best_vco_diff = vco_diff;
 						} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
 							   ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
 							   ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
 							   ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
 							   ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
 							   ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
 							best_post_div = post_div;
 							best_ref_div = ref_div;
 							best_feedback_div = feedback_div;
 							best_frac_feedback_div = frac_feedback_div;
 							best_freq = current_freq;
 							best_error = error;
 							best_vco_diff = vco_diff;
 						}
 					}
 					if (current_freq < freq)
 						min_frac_feed_div = frac_feedback_div + 1;
 					else
 						max_frac_feed_div = frac_feedback_div;
 				}
 				if (current_freq < freq)
 					min_feed_div = feedback_div + 1;
 				else
 					max_feed_div = feedback_div;
 			}
 		}
 	}
 	*dot_clock_p = best_freq / 10000;
 	*fb_div_p = best_feedback_div;
 	*frac_fb_div_p = best_frac_feedback_div;
 	*ref_div_p = best_ref_div;
 	*post_div_p = best_post_div;
 	DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 		      (long long)freq,
 		      best_freq / 1000, best_feedback_div, best_frac_feedback_div,
 		      best_ref_div, best_post_div);
 }
 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
 {
 	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 	if (radeon_fb->obj) {
 		drm_gem_object_unreference_unlocked(radeon_fb->obj);
 	}
 	drm_framebuffer_cleanup(fb);
 	kfree(radeon_fb);
 }
 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 						  struct drm_file *file_priv,
 						  unsigned int *handle)
 {
 	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 	return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
 }
 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
 	.destroy = radeon_user_framebuffer_destroy,
 	.create_handle = radeon_user_framebuffer_create_handle,
 };
 int
 radeon_framebuffer_init(struct drm_device *dev,
 			struct radeon_framebuffer *rfb,
 			struct drm_mode_fb_cmd2 *mode_cmd,
 			struct drm_gem_object *obj)
 {
 	int ret;
 	rfb->obj = obj;
 	ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
 	if (ret) {
 		rfb->obj = NULL;
 		return ret;
 	}
 	drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
 	return 0;
 }
 static struct drm_framebuffer *
 radeon_user_framebuffer_create(struct drm_device *dev,
 			       struct drm_file *file_priv,
 			       struct drm_mode_fb_cmd2 *mode_cmd)
 {
 	struct drm_gem_object *obj;
 	struct radeon_framebuffer *radeon_fb;
 	int ret;
 	obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
 	if (obj ==  NULL) {
 		dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 			"can't create framebuffer\n", mode_cmd->handles[0]);
 		return ERR_PTR(-ENOENT);
 	}
 	radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
-	if (radeon_fb == NULL)
+	if (radeon_fb == NULL) {
+		drm_gem_object_unreference_unlocked(obj);
 		return ERR_PTR(-ENOMEM);
+	}
 	ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
 	if (ret) {
 		kfree(radeon_fb);
 		drm_gem_object_unreference_unlocked(obj);
 		return ERR_PTR(ret);
 	}
 	return &radeon_fb->base;
 }
 static void radeon_output_poll_changed(struct drm_device *dev)
 {
 	struct radeon_device *rdev = dev->dev_private;
 	radeon_fb_output_poll_changed(rdev);
 }
 static const struct drm_mode_config_funcs radeon_mode_funcs = {
 	.fb_create = radeon_user_framebuffer_create,
 	.output_poll_changed = radeon_output_poll_changed
 };
 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
 {	{ 0, "driver" },
 	{ 1, "bios" },
 };
 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
 {	{ TV_STD_NTSC, "ntsc" },
 	{ TV_STD_PAL, "pal" },
 	{ TV_STD_PAL_M, "pal-m" },
 	{ TV_STD_PAL_60, "pal-60" },
 	{ TV_STD_NTSC_J, "ntsc-j" },
 	{ TV_STD_SCART_PAL, "scart-pal" },
 	{ TV_STD_PAL_CN, "pal-cn" },
 	{ TV_STD_SECAM, "secam" },
 };
 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
 {	{ UNDERSCAN_OFF, "off" },
 	{ UNDERSCAN_ON, "on" },
 	{ UNDERSCAN_AUTO, "auto" },
 };
 static int radeon_modeset_create_props(struct radeon_device *rdev)
 {
 	int sz;
 	if (rdev->is_atom_bios) {
 		rdev->mode_info.coherent_mode_property =
 			drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
 		if (!rdev->mode_info.coherent_mode_property)
 			return -ENOMEM;
 	}
 	if (!ASIC_IS_AVIVO(rdev)) {
 		sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
 		rdev->mode_info.tmds_pll_property =
 			drm_property_create_enum(rdev->ddev, 0,
 					    "tmds_pll",
 					    radeon_tmds_pll_enum_list, sz);
 	}
 	rdev->mode_info.load_detect_property =
 		drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
 	if (!rdev->mode_info.load_detect_property)
 		return -ENOMEM;
 	drm_mode_create_scaling_mode_property(rdev->ddev);
 	sz = ARRAY_SIZE(radeon_tv_std_enum_list);
 	rdev->mode_info.tv_std_property =
 		drm_property_create_enum(rdev->ddev, 0,
 				    "tv standard",
 				    radeon_tv_std_enum_list, sz);
 	sz = ARRAY_SIZE(radeon_underscan_enum_list);
 	rdev->mode_info.underscan_property =
 		drm_property_create_enum(rdev->ddev, 0,
 				    "underscan",
 				    radeon_underscan_enum_list, sz);
 	rdev->mode_info.underscan_hborder_property =
 		drm_property_create_range(rdev->ddev, 0,
 					"underscan hborder", 0, 128);
 	if (!rdev->mode_info.underscan_hborder_property)
 		return -ENOMEM;
 	rdev->mode_info.underscan_vborder_property =
 		drm_property_create_range(rdev->ddev, 0,
 					"underscan vborder", 0, 128);
 	if (!rdev->mode_info.underscan_vborder_property)
 		return -ENOMEM;
 	return 0;
 }
 void radeon_update_display_priority(struct radeon_device *rdev)
 {
 	/* adjustment options for the display watermarks */
 	if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
 		/* set display priority to high for r3xx, rv515 chips
 		 * this avoids flickering due to underflow to the
 		 * display controllers during heavy acceleration.
 		 * Don't force high on rs4xx igp chips as it seems to
 		 * affect the sound card.  See kernel bug 15982.
 		 */
 		if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
 		    !(rdev->flags & RADEON_IS_IGP))
 			rdev->disp_priority = 2;
 		else
 			rdev->disp_priority = 0;
 	} else
 		rdev->disp_priority = radeon_disp_priority;
 }
 /*
  * Allocate hdmi structs and determine register offsets
  */
 static void radeon_afmt_init(struct radeon_device *rdev)
 {
 	int i;
 	for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
 		rdev->mode_info.afmt[i] = NULL;
 	if (ASIC_IS_DCE6(rdev)) {
 		/* todo */
 	} else if (ASIC_IS_DCE4(rdev)) {
 		/* DCE4/5 has 6 audio blocks tied to DIG encoders */
 		/* DCE4.1 has 2 audio blocks tied to DIG encoders */
 		rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
 		if (rdev->mode_info.afmt[0]) {
 			rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
 			rdev->mode_info.afmt[0]->id = 0;
 		}
 		rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
 		if (rdev->mode_info.afmt[1]) {
 			rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
 			rdev->mode_info.afmt[1]->id = 1;
 		}
 		if (!ASIC_IS_DCE41(rdev)) {
 			rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
 			if (rdev->mode_info.afmt[2]) {
 				rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
 				rdev->mode_info.afmt[2]->id = 2;
 			}
 			rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
 			if (rdev->mode_info.afmt[3]) {
 				rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
 				rdev->mode_info.afmt[3]->id = 3;
 			}
 			rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
 			if (rdev->mode_info.afmt[4]) {
 				rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
 				rdev->mode_info.afmt[4]->id = 4;
 			}
 			rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
 			if (rdev->mode_info.afmt[5]) {
 				rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
 				rdev->mode_info.afmt[5]->id = 5;
 			}
 		}
 	} else if (ASIC_IS_DCE3(rdev)) {
 		/* DCE3.x has 2 audio blocks tied to DIG encoders */
 		rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
 		if (rdev->mode_info.afmt[0]) {
 			rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
 			rdev->mode_info.afmt[0]->id = 0;
 		}
 		rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
 		if (rdev->mode_info.afmt[1]) {
 			rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
 			rdev->mode_info.afmt[1]->id = 1;
 		}
 	} else if (ASIC_IS_DCE2(rdev)) {
 		/* DCE2 has at least 1 routable audio block */
 		rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
 		if (rdev->mode_info.afmt[0]) {
 			rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
 			rdev->mode_info.afmt[0]->id = 0;
 		}
 		/* r6xx has 2 routable audio blocks */
 		if (rdev->family >= CHIP_R600) {
 			rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
 			if (rdev->mode_info.afmt[1]) {
 				rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
 				rdev->mode_info.afmt[1]->id = 1;
 			}
 		}
 	}
 }
 static void radeon_afmt_fini(struct radeon_device *rdev)
 {
 	int i;
 	for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
 		kfree(rdev->mode_info.afmt[i]);
 		rdev->mode_info.afmt[i] = NULL;
 	}
 }
 int radeon_modeset_init(struct radeon_device *rdev)
 {
 	int i;
 	int ret;
 	drm_mode_config_init(rdev->ddev);
 	rdev->mode_info.mode_config_initialized = true;
 	rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
 	if (ASIC_IS_DCE5(rdev)) {
 		rdev->ddev->mode_config.max_width = 16384;
 		rdev->ddev->mode_config.max_height = 16384;
 	} else if (ASIC_IS_AVIVO(rdev)) {
 		rdev->ddev->mode_config.max_width = 8192;
 		rdev->ddev->mode_config.max_height = 8192;
 	} else {
 		rdev->ddev->mode_config.max_width = 4096;
 		rdev->ddev->mode_config.max_height = 4096;
 	}
 	rdev->ddev->mode_config.preferred_depth = 24;
 	rdev->ddev->mode_config.prefer_shadow = 1;
 	rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
 	ret = radeon_modeset_create_props(rdev);
 	if (ret) {
 		return ret;
 	}
 	/* init i2c buses */
 	radeon_i2c_init(rdev);
 	/* check combios for a valid hardcoded EDID - Sun servers */
 	if (!rdev->is_atom_bios) {
 		/* check for hardcoded EDID in BIOS */
 		radeon_combios_check_hardcoded_edid(rdev);
 	}
 	/* allocate crtcs */
 	for (i = 0; i < rdev->num_crtc; i++) {
 		radeon_crtc_init(rdev->ddev, i);
 	}
 	/* okay we should have all the bios connectors */
 	ret = radeon_setup_enc_conn(rdev->ddev);
 	if (!ret) {
 		return ret;
 	}
 	/* init dig PHYs, disp eng pll */
 	if (rdev->is_atom_bios) {
 		radeon_atom_encoder_init(rdev);
 		radeon_atom_disp_eng_pll_init(rdev);
 	}
 	/* initialize hpd */
 	radeon_hpd_init(rdev);
 	/* setup afmt */
 	radeon_afmt_init(rdev);
 	/* Initialize power management */
 	radeon_pm_init(rdev);
 	radeon_fbdev_init(rdev);
 	drm_kms_helper_poll_init(rdev->ddev);
 	return 0;
 }
 void radeon_modeset_fini(struct radeon_device *rdev)
 {
 	radeon_fbdev_fini(rdev);
 	kfree(rdev->mode_info.bios_hardcoded_edid);
 	radeon_pm_fini(rdev);
 	if (rdev->mode_info.mode_config_initialized) {
 		radeon_afmt_fini(rdev);
 		drm_kms_helper_poll_fini(rdev->ddev);
 		radeon_hpd_fini(rdev);
 		drm_mode_config_cleanup(rdev->ddev);
 		rdev->mode_info.mode_config_initialized = false;
 	}
 	/* free i2c buses */
 	radeon_i2c_fini(rdev);
 }
 static bool is_hdtv_mode(const struct drm_display_mode *mode)
 {
 	/* try and guess if this is a tv or a monitor */
 	if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
 	    (mode->vdisplay == 576) || /* 576p */
 	    (mode->vdisplay == 720) || /* 720p */
 	    (mode->vdisplay == 1080)) /* 1080p */
 		return true;
 	else
 		return false;
 }
 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 				const struct drm_display_mode *mode,
 				struct drm_display_mode *adjusted_mode)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct drm_encoder *encoder;
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct radeon_encoder *radeon_encoder;
 	struct drm_connector *connector;
 	struct radeon_connector *radeon_connector;
 	bool first = true;
 	u32 src_v = 1, dst_v = 1;
 	u32 src_h = 1, dst_h = 1;
 	radeon_crtc->h_border = 0;
 	radeon_crtc->v_border = 0;
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (encoder->crtc != crtc)
 			continue;
 		radeon_encoder = to_radeon_encoder(encoder);
 		connector = radeon_get_connector_for_encoder(encoder);
 		radeon_connector = to_radeon_connector(connector);
 		if (first) {
 			/* set scaling */
 			if (radeon_encoder->rmx_type == RMX_OFF)
 				radeon_crtc->rmx_type = RMX_OFF;
 			else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
 				 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
 				radeon_crtc->rmx_type = radeon_encoder->rmx_type;
 			else
 				radeon_crtc->rmx_type = RMX_OFF;
 			/* copy native mode */
 			memcpy(&radeon_crtc->native_mode,
 			       &radeon_encoder->native_mode,
 				sizeof(struct drm_display_mode));
 			src_v = crtc->mode.vdisplay;
 			dst_v = radeon_crtc->native_mode.vdisplay;
 			src_h = crtc->mode.hdisplay;
 			dst_h = radeon_crtc->native_mode.hdisplay;
 			/* fix up for overscan on hdmi */
 			if (ASIC_IS_AVIVO(rdev) &&
 			    (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
 			    ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
 			     ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
 			      drm_detect_hdmi_monitor(radeon_connector->edid) &&
 			      is_hdtv_mode(mode)))) {
 				if (radeon_encoder->underscan_hborder != 0)
 					radeon_crtc->h_border = radeon_encoder->underscan_hborder;
 				else
 					radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
 				if (radeon_encoder->underscan_vborder != 0)
 					radeon_crtc->v_border = radeon_encoder->underscan_vborder;
 				else
 					radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
 				radeon_crtc->rmx_type = RMX_FULL;
 				src_v = crtc->mode.vdisplay;
 				dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
 				src_h = crtc->mode.hdisplay;
 				dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
 			}
 			first = false;
 		} else {
 			if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
 				/* WARNING: Right now this can't happen but
 				 * in the future we need to check that scaling
 				 * are consistent across different encoder
 				 * (ie all encoder can work with the same
 				 *  scaling).
 				 */
 				DRM_ERROR("Scaling not consistent across encoder.\n");
 				return false;
 			}
 		}
 	}
 	if (radeon_crtc->rmx_type != RMX_OFF) {
 		fixed20_12 a, b;
 		a.full = dfixed_const(src_v);
 		b.full = dfixed_const(dst_v);
 		radeon_crtc->vsc.full = dfixed_div(a, b);
 		a.full = dfixed_const(src_h);
 		b.full = dfixed_const(dst_h);
 		radeon_crtc->hsc.full = dfixed_div(a, b);
 	} else {
 		radeon_crtc->vsc.full = dfixed_const(1);
 		radeon_crtc->hsc.full = dfixed_const(1);
 	}
 	return true;
 }
 /*
  * Retrieve current video scanout position of crtc on a given gpu.
  *
  * \param dev Device to query.
  * \param crtc Crtc to query.
  * \param *vpos Location where vertical scanout position should be stored.
  * \param *hpos Location where horizontal scanout position should go.
  *
  * Returns vpos as a positive number while in active scanout area.
  * Returns vpos as a negative number inside vblank, counting the number
  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
  * until start of active scanout / end of vblank."
  *
  * \return Flags, or'ed together as follows:
  *
  * DRM_SCANOUTPOS_VALID = Query successful.
  * DRM_SCANOUTPOS_INVBL = Inside vblank.
  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
  * this flag means that returned position may be offset by a constant but
  * unknown small number of scanlines wrt. real scanout position.
  *
  */
 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
 {
 	u32 stat_crtc = 0, vbl = 0, position = 0;
 	int vbl_start, vbl_end, vtotal, ret = 0;
 	bool in_vbl = true;
 	struct radeon_device *rdev = dev->dev_private;
 	if (ASIC_IS_DCE4(rdev)) {
 		if (crtc == 0) {
 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 				     EVERGREEN_CRTC0_REGISTER_OFFSET);
 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 					  EVERGREEN_CRTC0_REGISTER_OFFSET);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 1) {
 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 				     EVERGREEN_CRTC1_REGISTER_OFFSET);
 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 					  EVERGREEN_CRTC1_REGISTER_OFFSET);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 2) {
 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 				     EVERGREEN_CRTC2_REGISTER_OFFSET);
 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 					  EVERGREEN_CRTC2_REGISTER_OFFSET);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 3) {
 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 				     EVERGREEN_CRTC3_REGISTER_OFFSET);
 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 					  EVERGREEN_CRTC3_REGISTER_OFFSET);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 4) {
 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 				     EVERGREEN_CRTC4_REGISTER_OFFSET);
 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 					  EVERGREEN_CRTC4_REGISTER_OFFSET);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 5) {
 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 				     EVERGREEN_CRTC5_REGISTER_OFFSET);
 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 					  EVERGREEN_CRTC5_REGISTER_OFFSET);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 	} else if (ASIC_IS_AVIVO(rdev)) {
 		if (crtc == 0) {
 			vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
 			position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 1) {
 			vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
 			position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 	} else {
 		/* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
 		if (crtc == 0) {
 			/* Assume vbl_end == 0, get vbl_start from
 			 * upper 16 bits.
 			 */
 			vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
 				RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
 			/* Only retrieve vpos from upper 16 bits, set hpos == 0. */
 			position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
 			stat_crtc = RREG32(RADEON_CRTC_STATUS);
 			if (!(stat_crtc & 1))
 				in_vbl = false;
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 1) {
 			vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
 				RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
 			position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
 			stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 			if (!(stat_crtc & 1))
 				in_vbl = false;
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 	}
 	/* Decode into vertical and horizontal scanout position. */
 	*vpos = position & 0x1fff;
 	*hpos = (position >> 16) & 0x1fff;
 	/* Valid vblank area boundaries from gpu retrieved? */
 	if (vbl > 0) {
 		/* Yes: Decode. */
 		ret |= DRM_SCANOUTPOS_ACCURATE;
 		vbl_start = vbl & 0x1fff;
 		vbl_end = (vbl >> 16) & 0x1fff;
 	}
 	else {
 		/* No: Fake something reasonable which gives at least ok results. */
 		vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
 		vbl_end = 0;
 	}
 	/* Test scanout position against vblank region. */
 	if ((*vpos < vbl_start) && (*vpos >= vbl_end))
 		in_vbl = false;
 	/* Check if inside vblank area and apply corrective offsets:
 	 * vpos will then be >=0 in video scanout area, but negative
 	 * within vblank area, counting down the number of lines until
 	 * start of scanout.
 	 */
 	/* Inside "upper part" of vblank area? Apply corrective offset if so: */
 	if (in_vbl && (*vpos >= vbl_start)) {
 		vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
 		*vpos = *vpos - vtotal;
 	}
 	/* Correct for shifted end of vbl at vbl_end. */
 	*vpos = *vpos - vbl_end;
 	/* In vblank? */
 	if (in_vbl)
 		ret |= DRM_SCANOUTPOS_INVBL;
 	return ret;
 }