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Commit f33f1fccbf67b3d9b310a4b09114b7c670320ad4

Authored by Barak Witkowski
Committed by David S. Miller
1 parent 959327c784
Exists in master and in 6 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

bnx2x: fix typo in fcoe stats collection 

Signed-off-by: Barak Witkowski <barak@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
Diff comments   View file @ f33f1fc
1 /* bnx2x_main.c: Broadcom Everest network driver. 1 /* bnx2x_main.c: Broadcom Everest network driver.
2 * 2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation 3 * Copyright (c) 2007-2011 Broadcom Corporation
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation. 7 * the Free Software Foundation.
8 * 8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir 10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman 12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov 13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner 14 * Statistics and Link management by Yitchak Gertner
15 * 15 *
16 */ 16 */
17 17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 19
20 #include <linux/module.h> 20 #include <linux/module.h>
21 #include <linux/moduleparam.h> 21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h> 22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */ 23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h> 24 #include <linux/timer.h>
25 #include <linux/errno.h> 25 #include <linux/errno.h>
26 #include <linux/ioport.h> 26 #include <linux/ioport.h>
27 #include <linux/slab.h> 27 #include <linux/slab.h>
28 #include <linux/interrupt.h> 28 #include <linux/interrupt.h>
29 #include <linux/pci.h> 29 #include <linux/pci.h>
30 #include <linux/init.h> 30 #include <linux/init.h>
31 #include <linux/netdevice.h> 31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h> 32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h> 33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h> 34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h> 35 #include <linux/bitops.h>
36 #include <linux/irq.h> 36 #include <linux/irq.h>
37 #include <linux/delay.h> 37 #include <linux/delay.h>
38 #include <asm/byteorder.h> 38 #include <asm/byteorder.h>
39 #include <linux/time.h> 39 #include <linux/time.h>
40 #include <linux/ethtool.h> 40 #include <linux/ethtool.h>
41 #include <linux/mii.h> 41 #include <linux/mii.h>
42 #include <linux/if.h> 42 #include <linux/if.h>
43 #include <linux/if_vlan.h> 43 #include <linux/if_vlan.h>
44 #include <net/ip.h> 44 #include <net/ip.h>
45 #include <net/ipv6.h> 45 #include <net/ipv6.h>
46 #include <net/tcp.h> 46 #include <net/tcp.h>
47 #include <net/checksum.h> 47 #include <net/checksum.h>
48 #include <net/ip6_checksum.h> 48 #include <net/ip6_checksum.h>
49 #include <linux/workqueue.h> 49 #include <linux/workqueue.h>
50 #include <linux/crc32.h> 50 #include <linux/crc32.h>
51 #include <linux/crc32c.h> 51 #include <linux/crc32c.h>
52 #include <linux/prefetch.h> 52 #include <linux/prefetch.h>
53 #include <linux/zlib.h> 53 #include <linux/zlib.h>
54 #include <linux/io.h> 54 #include <linux/io.h>
55 #include <linux/stringify.h> 55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h> 56 #include <linux/vmalloc.h>
57 57
58 #include "bnx2x.h" 58 #include "bnx2x.h"
59 #include "bnx2x_init.h" 59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h" 60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h" 61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h" 62 #include "bnx2x_dcb.h"
63 #include "bnx2x_sp.h" 63 #include "bnx2x_sp.h"
64 64
65 #include <linux/firmware.h> 65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h" 66 #include "bnx2x_fw_file_hdr.h"
67 /* FW files */ 67 /* FW files */
68 #define FW_FILE_VERSION \ 68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
76 76
77 /* Time in jiffies before concluding the transmitter is hung */ 77 /* Time in jiffies before concluding the transmitter is hung */
78 #define TX_TIMEOUT (5*HZ) 78 #define TX_TIMEOUT (5*HZ)
79 79
80 static char version[] __devinitdata = 80 static char version[] __devinitdata =
81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
83 83
84 MODULE_AUTHOR("Eliezer Tamir"); 84 MODULE_AUTHOR("Eliezer Tamir");
85 MODULE_DESCRIPTION("Broadcom NetXtreme II " 85 MODULE_DESCRIPTION("Broadcom NetXtreme II "
86 "BCM57710/57711/57711E/" 86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver"); 88 "57840/57840_MF Driver");
89 MODULE_LICENSE("GPL"); 89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(DRV_MODULE_VERSION); 90 MODULE_VERSION(DRV_MODULE_VERSION);
91 MODULE_FIRMWARE(FW_FILE_NAME_E1); 91 MODULE_FIRMWARE(FW_FILE_NAME_E1);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1H); 92 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
93 MODULE_FIRMWARE(FW_FILE_NAME_E2); 93 MODULE_FIRMWARE(FW_FILE_NAME_E2);
94 94
95 static int multi_mode = 1; 95 static int multi_mode = 1;
96 module_param(multi_mode, int, 0); 96 module_param(multi_mode, int, 0);
97 MODULE_PARM_DESC(multi_mode, " Multi queue mode " 97 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
98 "(0 Disable; 1 Enable (default))"); 98 "(0 Disable; 1 Enable (default))");
99 99
100 int num_queues; 100 int num_queues;
101 module_param(num_queues, int, 0); 101 module_param(num_queues, int, 0);
102 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 102 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
103 " (default is as a number of CPUs)"); 103 " (default is as a number of CPUs)");
104 104
105 static int disable_tpa; 105 static int disable_tpa;
106 module_param(disable_tpa, int, 0); 106 module_param(disable_tpa, int, 0);
107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
108 108
109 #define INT_MODE_INTx 1 109 #define INT_MODE_INTx 1
110 #define INT_MODE_MSI 2 110 #define INT_MODE_MSI 2
111 static int int_mode; 111 static int int_mode;
112 module_param(int_mode, int, 0); 112 module_param(int_mode, int, 0);
113 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 113 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
114 "(1 INT#x; 2 MSI)"); 114 "(1 INT#x; 2 MSI)");
115 115
116 static int dropless_fc; 116 static int dropless_fc;
117 module_param(dropless_fc, int, 0); 117 module_param(dropless_fc, int, 0);
118 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 118 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
119 119
120 static int poll; 120 static int poll;
121 module_param(poll, int, 0); 121 module_param(poll, int, 0);
122 MODULE_PARM_DESC(poll, " Use polling (for debug)"); 122 MODULE_PARM_DESC(poll, " Use polling (for debug)");
123 123
124 static int mrrs = -1; 124 static int mrrs = -1;
125 module_param(mrrs, int, 0); 125 module_param(mrrs, int, 0);
126 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 126 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
127 127
128 static int debug; 128 static int debug;
129 module_param(debug, int, 0); 129 module_param(debug, int, 0);
130 MODULE_PARM_DESC(debug, " Default debug msglevel"); 130 MODULE_PARM_DESC(debug, " Default debug msglevel");
131 131
132 132
133 133
134 struct workqueue_struct *bnx2x_wq; 134 struct workqueue_struct *bnx2x_wq;
135 135
136 enum bnx2x_board_type { 136 enum bnx2x_board_type {
137 BCM57710 = 0, 137 BCM57710 = 0,
138 BCM57711, 138 BCM57711,
139 BCM57711E, 139 BCM57711E,
140 BCM57712, 140 BCM57712,
141 BCM57712_MF, 141 BCM57712_MF,
142 BCM57800, 142 BCM57800,
143 BCM57800_MF, 143 BCM57800_MF,
144 BCM57810, 144 BCM57810,
145 BCM57810_MF, 145 BCM57810_MF,
146 BCM57840, 146 BCM57840,
147 BCM57840_MF 147 BCM57840_MF
148 }; 148 };
149 149
150 /* indexed by board_type, above */ 150 /* indexed by board_type, above */
151 static struct { 151 static struct {
152 char *name; 152 char *name;
153 } board_info[] __devinitdata = { 153 } board_info[] __devinitdata = {
154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " 164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
165 "Ethernet Multi Function"} 165 "Ethernet Multi Function"}
166 }; 166 };
167 167
168 #ifndef PCI_DEVICE_ID_NX2_57710 168 #ifndef PCI_DEVICE_ID_NX2_57710
169 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 169 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
170 #endif 170 #endif
171 #ifndef PCI_DEVICE_ID_NX2_57711 171 #ifndef PCI_DEVICE_ID_NX2_57711
172 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 172 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
173 #endif 173 #endif
174 #ifndef PCI_DEVICE_ID_NX2_57711E 174 #ifndef PCI_DEVICE_ID_NX2_57711E
175 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 175 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
176 #endif 176 #endif
177 #ifndef PCI_DEVICE_ID_NX2_57712 177 #ifndef PCI_DEVICE_ID_NX2_57712
178 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 178 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
179 #endif 179 #endif
180 #ifndef PCI_DEVICE_ID_NX2_57712_MF 180 #ifndef PCI_DEVICE_ID_NX2_57712_MF
181 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 181 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
182 #endif 182 #endif
183 #ifndef PCI_DEVICE_ID_NX2_57800 183 #ifndef PCI_DEVICE_ID_NX2_57800
184 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 184 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
185 #endif 185 #endif
186 #ifndef PCI_DEVICE_ID_NX2_57800_MF 186 #ifndef PCI_DEVICE_ID_NX2_57800_MF
187 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 187 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
188 #endif 188 #endif
189 #ifndef PCI_DEVICE_ID_NX2_57810 189 #ifndef PCI_DEVICE_ID_NX2_57810
190 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 190 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
191 #endif 191 #endif
192 #ifndef PCI_DEVICE_ID_NX2_57810_MF 192 #ifndef PCI_DEVICE_ID_NX2_57810_MF
193 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 193 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
194 #endif 194 #endif
195 #ifndef PCI_DEVICE_ID_NX2_57840 195 #ifndef PCI_DEVICE_ID_NX2_57840
196 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 196 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
197 #endif 197 #endif
198 #ifndef PCI_DEVICE_ID_NX2_57840_MF 198 #ifndef PCI_DEVICE_ID_NX2_57840_MF
199 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 199 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
200 #endif 200 #endif
201 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 201 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, 211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
213 { 0 } 213 { 0 }
214 }; 214 };
215 215
216 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 216 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
217 217
218 /**************************************************************************** 218 /****************************************************************************
219 * General service functions 219 * General service functions
220 ****************************************************************************/ 220 ****************************************************************************/
221 221
222 static inline void __storm_memset_dma_mapping(struct bnx2x *bp, 222 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
223 u32 addr, dma_addr_t mapping) 223 u32 addr, dma_addr_t mapping)
224 { 224 {
225 REG_WR(bp, addr, U64_LO(mapping)); 225 REG_WR(bp, addr, U64_LO(mapping));
226 REG_WR(bp, addr + 4, U64_HI(mapping)); 226 REG_WR(bp, addr + 4, U64_HI(mapping));
227 } 227 }
228 228
229 static inline void storm_memset_spq_addr(struct bnx2x *bp, 229 static inline void storm_memset_spq_addr(struct bnx2x *bp,
230 dma_addr_t mapping, u16 abs_fid) 230 dma_addr_t mapping, u16 abs_fid)
231 { 231 {
232 u32 addr = XSEM_REG_FAST_MEMORY + 232 u32 addr = XSEM_REG_FAST_MEMORY +
233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
234 234
235 __storm_memset_dma_mapping(bp, addr, mapping); 235 __storm_memset_dma_mapping(bp, addr, mapping);
236 } 236 }
237 237
238 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 238 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
239 u16 pf_id) 239 u16 pf_id)
240 { 240 {
241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
242 pf_id); 242 pf_id);
243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
244 pf_id); 244 pf_id);
245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
246 pf_id); 246 pf_id);
247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
248 pf_id); 248 pf_id);
249 } 249 }
250 250
251 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 251 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
252 u8 enable) 252 u8 enable)
253 { 253 {
254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
255 enable); 255 enable);
256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
257 enable); 257 enable);
258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
259 enable); 259 enable);
260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
261 enable); 261 enable);
262 } 262 }
263 263
264 static inline void storm_memset_eq_data(struct bnx2x *bp, 264 static inline void storm_memset_eq_data(struct bnx2x *bp,
265 struct event_ring_data *eq_data, 265 struct event_ring_data *eq_data,
266 u16 pfid) 266 u16 pfid)
267 { 267 {
268 size_t size = sizeof(struct event_ring_data); 268 size_t size = sizeof(struct event_ring_data);
269 269
270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
271 271
272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
273 } 273 }
274 274
275 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 275 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
276 u16 pfid) 276 u16 pfid)
277 { 277 {
278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
279 REG_WR16(bp, addr, eq_prod); 279 REG_WR16(bp, addr, eq_prod);
280 } 280 }
281 281
282 /* used only at init 282 /* used only at init
283 * locking is done by mcp 283 * locking is done by mcp
284 */ 284 */
285 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 285 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
286 { 286 {
287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
290 PCICFG_VENDOR_ID_OFFSET); 290 PCICFG_VENDOR_ID_OFFSET);
291 } 291 }
292 292
293 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 293 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
294 { 294 {
295 u32 val; 295 u32 val;
296 296
297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
300 PCICFG_VENDOR_ID_OFFSET); 300 PCICFG_VENDOR_ID_OFFSET);
301 301
302 return val; 302 return val;
303 } 303 }
304 304
305 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 305 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
306 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 306 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
307 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 307 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
308 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 308 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
309 #define DMAE_DP_DST_NONE "dst_addr [none]" 309 #define DMAE_DP_DST_NONE "dst_addr [none]"
310 310
311 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, 311 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
312 int msglvl) 312 int msglvl)
313 { 313 {
314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
315 315
316 switch (dmae->opcode & DMAE_COMMAND_DST) { 316 switch (dmae->opcode & DMAE_COMMAND_DST) {
317 case DMAE_CMD_DST_PCI: 317 case DMAE_CMD_DST_PCI:
318 if (src_type == DMAE_CMD_SRC_PCI) 318 if (src_type == DMAE_CMD_SRC_PCI)
319 DP(msglvl, "DMAE: opcode 0x%08x\n" 319 DP(msglvl, "DMAE: opcode 0x%08x\n"
320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
321 "comp_addr [%x:%08x], comp_val 0x%08x\n", 321 "comp_addr [%x:%08x], comp_val 0x%08x\n",
322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
324 dmae->comp_addr_hi, dmae->comp_addr_lo, 324 dmae->comp_addr_hi, dmae->comp_addr_lo,
325 dmae->comp_val); 325 dmae->comp_val);
326 else 326 else
327 DP(msglvl, "DMAE: opcode 0x%08x\n" 327 DP(msglvl, "DMAE: opcode 0x%08x\n"
328 "src [%08x], len [%d*4], dst [%x:%08x]\n" 328 "src [%08x], len [%d*4], dst [%x:%08x]\n"
329 "comp_addr [%x:%08x], comp_val 0x%08x\n", 329 "comp_addr [%x:%08x], comp_val 0x%08x\n",
330 dmae->opcode, dmae->src_addr_lo >> 2, 330 dmae->opcode, dmae->src_addr_lo >> 2,
331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
332 dmae->comp_addr_hi, dmae->comp_addr_lo, 332 dmae->comp_addr_hi, dmae->comp_addr_lo,
333 dmae->comp_val); 333 dmae->comp_val);
334 break; 334 break;
335 case DMAE_CMD_DST_GRC: 335 case DMAE_CMD_DST_GRC:
336 if (src_type == DMAE_CMD_SRC_PCI) 336 if (src_type == DMAE_CMD_SRC_PCI)
337 DP(msglvl, "DMAE: opcode 0x%08x\n" 337 DP(msglvl, "DMAE: opcode 0x%08x\n"
338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
339 "comp_addr [%x:%08x], comp_val 0x%08x\n", 339 "comp_addr [%x:%08x], comp_val 0x%08x\n",
340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
341 dmae->len, dmae->dst_addr_lo >> 2, 341 dmae->len, dmae->dst_addr_lo >> 2,
342 dmae->comp_addr_hi, dmae->comp_addr_lo, 342 dmae->comp_addr_hi, dmae->comp_addr_lo,
343 dmae->comp_val); 343 dmae->comp_val);
344 else 344 else
345 DP(msglvl, "DMAE: opcode 0x%08x\n" 345 DP(msglvl, "DMAE: opcode 0x%08x\n"
346 "src [%08x], len [%d*4], dst [%08x]\n" 346 "src [%08x], len [%d*4], dst [%08x]\n"
347 "comp_addr [%x:%08x], comp_val 0x%08x\n", 347 "comp_addr [%x:%08x], comp_val 0x%08x\n",
348 dmae->opcode, dmae->src_addr_lo >> 2, 348 dmae->opcode, dmae->src_addr_lo >> 2,
349 dmae->len, dmae->dst_addr_lo >> 2, 349 dmae->len, dmae->dst_addr_lo >> 2,
350 dmae->comp_addr_hi, dmae->comp_addr_lo, 350 dmae->comp_addr_hi, dmae->comp_addr_lo,
351 dmae->comp_val); 351 dmae->comp_val);
352 break; 352 break;
353 default: 353 default:
354 if (src_type == DMAE_CMD_SRC_PCI) 354 if (src_type == DMAE_CMD_SRC_PCI)
355 DP(msglvl, "DMAE: opcode 0x%08x\n" 355 DP(msglvl, "DMAE: opcode 0x%08x\n"
356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
357 "comp_addr [%x:%08x] comp_val 0x%08x\n", 357 "comp_addr [%x:%08x] comp_val 0x%08x\n",
358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
360 dmae->comp_val); 360 dmae->comp_val);
361 else 361 else
362 DP(msglvl, "DMAE: opcode 0x%08x\n" 362 DP(msglvl, "DMAE: opcode 0x%08x\n"
363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
364 "comp_addr [%x:%08x] comp_val 0x%08x\n", 364 "comp_addr [%x:%08x] comp_val 0x%08x\n",
365 dmae->opcode, dmae->src_addr_lo >> 2, 365 dmae->opcode, dmae->src_addr_lo >> 2,
366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
367 dmae->comp_val); 367 dmae->comp_val);
368 break; 368 break;
369 } 369 }
370 370
371 } 371 }
372 372
373 /* copy command into DMAE command memory and set DMAE command go */ 373 /* copy command into DMAE command memory and set DMAE command go */
374 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 374 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
375 { 375 {
376 u32 cmd_offset; 376 u32 cmd_offset;
377 int i; 377 int i;
378 378
379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
382 382
383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", 383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); 384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
385 } 385 }
386 REG_WR(bp, dmae_reg_go_c[idx], 1); 386 REG_WR(bp, dmae_reg_go_c[idx], 1);
387 } 387 }
388 388
389 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 389 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
390 { 390 {
391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
392 DMAE_CMD_C_ENABLE); 392 DMAE_CMD_C_ENABLE);
393 } 393 }
394 394
395 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 395 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
396 { 396 {
397 return opcode & ~DMAE_CMD_SRC_RESET; 397 return opcode & ~DMAE_CMD_SRC_RESET;
398 } 398 }
399 399
400 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 400 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
401 bool with_comp, u8 comp_type) 401 bool with_comp, u8 comp_type)
402 { 402 {
403 u32 opcode = 0; 403 u32 opcode = 0;
404 404
405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
406 (dst_type << DMAE_COMMAND_DST_SHIFT)); 406 (dst_type << DMAE_COMMAND_DST_SHIFT));
407 407
408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
409 409
410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
411 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 411 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
412 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 412 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
414 414
415 #ifdef __BIG_ENDIAN 415 #ifdef __BIG_ENDIAN
416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
417 #else 417 #else
418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
419 #endif 419 #endif
420 if (with_comp) 420 if (with_comp)
421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
422 return opcode; 422 return opcode;
423 } 423 }
424 424
425 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 425 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
426 struct dmae_command *dmae, 426 struct dmae_command *dmae,
427 u8 src_type, u8 dst_type) 427 u8 src_type, u8 dst_type)
428 { 428 {
429 memset(dmae, 0, sizeof(struct dmae_command)); 429 memset(dmae, 0, sizeof(struct dmae_command));
430 430
431 /* set the opcode */ 431 /* set the opcode */
432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
433 true, DMAE_COMP_PCI); 433 true, DMAE_COMP_PCI);
434 434
435 /* fill in the completion parameters */ 435 /* fill in the completion parameters */
436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
438 dmae->comp_val = DMAE_COMP_VAL; 438 dmae->comp_val = DMAE_COMP_VAL;
439 } 439 }
440 440
441 /* issue a dmae command over the init-channel and wailt for completion */ 441 /* issue a dmae command over the init-channel and wailt for completion */
442 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, 442 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
443 struct dmae_command *dmae) 443 struct dmae_command *dmae)
444 { 444 {
445 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 445 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
447 int rc = 0; 447 int rc = 0;
448 448
449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", 449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
452 452
453 /* 453 /*
454 * Lock the dmae channel. Disable BHs to prevent a dead-lock 454 * Lock the dmae channel. Disable BHs to prevent a dead-lock
455 * as long as this code is called both from syscall context and 455 * as long as this code is called both from syscall context and
456 * from ndo_set_rx_mode() flow that may be called from BH. 456 * from ndo_set_rx_mode() flow that may be called from BH.
457 */ 457 */
458 spin_lock_bh(&bp->dmae_lock); 458 spin_lock_bh(&bp->dmae_lock);
459 459
460 /* reset completion */ 460 /* reset completion */
461 *wb_comp = 0; 461 *wb_comp = 0;
462 462
463 /* post the command on the channel used for initializations */ 463 /* post the command on the channel used for initializations */
464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
465 465
466 /* wait for completion */ 466 /* wait for completion */
467 udelay(5); 467 udelay(5);
468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
470 470
471 if (!cnt) { 471 if (!cnt) {
472 BNX2X_ERR("DMAE timeout!\n"); 472 BNX2X_ERR("DMAE timeout!\n");
473 rc = DMAE_TIMEOUT; 473 rc = DMAE_TIMEOUT;
474 goto unlock; 474 goto unlock;
475 } 475 }
476 cnt--; 476 cnt--;
477 udelay(50); 477 udelay(50);
478 } 478 }
479 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 479 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
480 BNX2X_ERR("DMAE PCI error!\n"); 480 BNX2X_ERR("DMAE PCI error!\n");
481 rc = DMAE_PCI_ERROR; 481 rc = DMAE_PCI_ERROR;
482 } 482 }
483 483
484 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", 484 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
485 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 485 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
486 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 486 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
487 487
488 unlock: 488 unlock:
489 spin_unlock_bh(&bp->dmae_lock); 489 spin_unlock_bh(&bp->dmae_lock);
490 return rc; 490 return rc;
491 } 491 }
492 492
493 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 493 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
494 u32 len32) 494 u32 len32)
495 { 495 {
496 struct dmae_command dmae; 496 struct dmae_command dmae;
497 497
498 if (!bp->dmae_ready) { 498 if (!bp->dmae_ready) {
499 u32 *data = bnx2x_sp(bp, wb_data[0]); 499 u32 *data = bnx2x_sp(bp, wb_data[0]);
500 500
501 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)" 501 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
502 " using indirect\n", dst_addr, len32); 502 " using indirect\n", dst_addr, len32);
503 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 503 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
504 return; 504 return;
505 } 505 }
506 506
507 /* set opcode and fixed command fields */ 507 /* set opcode and fixed command fields */
508 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 508 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
509 509
510 /* fill in addresses and len */ 510 /* fill in addresses and len */
511 dmae.src_addr_lo = U64_LO(dma_addr); 511 dmae.src_addr_lo = U64_LO(dma_addr);
512 dmae.src_addr_hi = U64_HI(dma_addr); 512 dmae.src_addr_hi = U64_HI(dma_addr);
513 dmae.dst_addr_lo = dst_addr >> 2; 513 dmae.dst_addr_lo = dst_addr >> 2;
514 dmae.dst_addr_hi = 0; 514 dmae.dst_addr_hi = 0;
515 dmae.len = len32; 515 dmae.len = len32;
516 516
517 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 517 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
518 518
519 /* issue the command and wait for completion */ 519 /* issue the command and wait for completion */
520 bnx2x_issue_dmae_with_comp(bp, &dmae); 520 bnx2x_issue_dmae_with_comp(bp, &dmae);
521 } 521 }
522 522
523 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 523 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
524 { 524 {
525 struct dmae_command dmae; 525 struct dmae_command dmae;
526 526
527 if (!bp->dmae_ready) { 527 if (!bp->dmae_ready) {
528 u32 *data = bnx2x_sp(bp, wb_data[0]); 528 u32 *data = bnx2x_sp(bp, wb_data[0]);
529 int i; 529 int i;
530 530
531 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)" 531 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
532 " using indirect\n", src_addr, len32); 532 " using indirect\n", src_addr, len32);
533 for (i = 0; i < len32; i++) 533 for (i = 0; i < len32; i++)
534 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 534 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
535 return; 535 return;
536 } 536 }
537 537
538 /* set opcode and fixed command fields */ 538 /* set opcode and fixed command fields */
539 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 539 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
540 540
541 /* fill in addresses and len */ 541 /* fill in addresses and len */
542 dmae.src_addr_lo = src_addr >> 2; 542 dmae.src_addr_lo = src_addr >> 2;
543 dmae.src_addr_hi = 0; 543 dmae.src_addr_hi = 0;
544 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 544 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
545 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 545 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
546 dmae.len = len32; 546 dmae.len = len32;
547 547
548 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 548 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
549 549
550 /* issue the command and wait for completion */ 550 /* issue the command and wait for completion */
551 bnx2x_issue_dmae_with_comp(bp, &dmae); 551 bnx2x_issue_dmae_with_comp(bp, &dmae);
552 } 552 }
553 553
554 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 554 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
555 u32 addr, u32 len) 555 u32 addr, u32 len)
556 { 556 {
557 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 557 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
558 int offset = 0; 558 int offset = 0;
559 559
560 while (len > dmae_wr_max) { 560 while (len > dmae_wr_max) {
561 bnx2x_write_dmae(bp, phys_addr + offset, 561 bnx2x_write_dmae(bp, phys_addr + offset,
562 addr + offset, dmae_wr_max); 562 addr + offset, dmae_wr_max);
563 offset += dmae_wr_max * 4; 563 offset += dmae_wr_max * 4;
564 len -= dmae_wr_max; 564 len -= dmae_wr_max;
565 } 565 }
566 566
567 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 567 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
568 } 568 }
569 569
570 /* used only for slowpath so not inlined */ 570 /* used only for slowpath so not inlined */
571 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) 571 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
572 { 572 {
573 u32 wb_write[2]; 573 u32 wb_write[2];
574 574
575 wb_write[0] = val_hi; 575 wb_write[0] = val_hi;
576 wb_write[1] = val_lo; 576 wb_write[1] = val_lo;
577 REG_WR_DMAE(bp, reg, wb_write, 2); 577 REG_WR_DMAE(bp, reg, wb_write, 2);
578 } 578 }
579 579
580 #ifdef USE_WB_RD 580 #ifdef USE_WB_RD
581 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) 581 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
582 { 582 {
583 u32 wb_data[2]; 583 u32 wb_data[2];
584 584
585 REG_RD_DMAE(bp, reg, wb_data, 2); 585 REG_RD_DMAE(bp, reg, wb_data, 2);
586 586
587 return HILO_U64(wb_data[0], wb_data[1]); 587 return HILO_U64(wb_data[0], wb_data[1]);
588 } 588 }
589 #endif 589 #endif
590 590
591 static int bnx2x_mc_assert(struct bnx2x *bp) 591 static int bnx2x_mc_assert(struct bnx2x *bp)
592 { 592 {
593 char last_idx; 593 char last_idx;
594 int i, rc = 0; 594 int i, rc = 0;
595 u32 row0, row1, row2, row3; 595 u32 row0, row1, row2, row3;
596 596
597 /* XSTORM */ 597 /* XSTORM */
598 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 598 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
599 XSTORM_ASSERT_LIST_INDEX_OFFSET); 599 XSTORM_ASSERT_LIST_INDEX_OFFSET);
600 if (last_idx) 600 if (last_idx)
601 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 601 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
602 602
603 /* print the asserts */ 603 /* print the asserts */
604 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 604 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
605 605
606 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 606 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
607 XSTORM_ASSERT_LIST_OFFSET(i)); 607 XSTORM_ASSERT_LIST_OFFSET(i));
608 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 608 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
609 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 609 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
610 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 610 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
611 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 611 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
612 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 612 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
613 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 613 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
614 614
615 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 615 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
616 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" 616 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
617 " 0x%08x 0x%08x 0x%08x\n", 617 " 0x%08x 0x%08x 0x%08x\n",
618 i, row3, row2, row1, row0); 618 i, row3, row2, row1, row0);
619 rc++; 619 rc++;
620 } else { 620 } else {
621 break; 621 break;
622 } 622 }
623 } 623 }
624 624
625 /* TSTORM */ 625 /* TSTORM */
626 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 626 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
627 TSTORM_ASSERT_LIST_INDEX_OFFSET); 627 TSTORM_ASSERT_LIST_INDEX_OFFSET);
628 if (last_idx) 628 if (last_idx)
629 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 629 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
630 630
631 /* print the asserts */ 631 /* print the asserts */
632 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 632 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
633 633
634 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 634 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
635 TSTORM_ASSERT_LIST_OFFSET(i)); 635 TSTORM_ASSERT_LIST_OFFSET(i));
636 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 636 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
637 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 637 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
638 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 638 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
639 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 639 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
640 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 640 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
641 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 641 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
642 642
643 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 643 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
644 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" 644 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
645 " 0x%08x 0x%08x 0x%08x\n", 645 " 0x%08x 0x%08x 0x%08x\n",
646 i, row3, row2, row1, row0); 646 i, row3, row2, row1, row0);
647 rc++; 647 rc++;
648 } else { 648 } else {
649 break; 649 break;
650 } 650 }
651 } 651 }
652 652
653 /* CSTORM */ 653 /* CSTORM */
654 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 654 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
655 CSTORM_ASSERT_LIST_INDEX_OFFSET); 655 CSTORM_ASSERT_LIST_INDEX_OFFSET);
656 if (last_idx) 656 if (last_idx)
657 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 657 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
658 658
659 /* print the asserts */ 659 /* print the asserts */
660 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 660 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
661 661
662 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 662 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
663 CSTORM_ASSERT_LIST_OFFSET(i)); 663 CSTORM_ASSERT_LIST_OFFSET(i));
664 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 664 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
665 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 665 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
666 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 666 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
667 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 667 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
668 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 668 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
669 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 669 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
670 670
671 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 671 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
672 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" 672 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
673 " 0x%08x 0x%08x 0x%08x\n", 673 " 0x%08x 0x%08x 0x%08x\n",
674 i, row3, row2, row1, row0); 674 i, row3, row2, row1, row0);
675 rc++; 675 rc++;
676 } else { 676 } else {
677 break; 677 break;
678 } 678 }
679 } 679 }
680 680
681 /* USTORM */ 681 /* USTORM */
682 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 682 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
683 USTORM_ASSERT_LIST_INDEX_OFFSET); 683 USTORM_ASSERT_LIST_INDEX_OFFSET);
684 if (last_idx) 684 if (last_idx)
685 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 685 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
686 686
687 /* print the asserts */ 687 /* print the asserts */
688 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 688 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
689 689
690 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 690 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
691 USTORM_ASSERT_LIST_OFFSET(i)); 691 USTORM_ASSERT_LIST_OFFSET(i));
692 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 692 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
693 USTORM_ASSERT_LIST_OFFSET(i) + 4); 693 USTORM_ASSERT_LIST_OFFSET(i) + 4);
694 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 694 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
695 USTORM_ASSERT_LIST_OFFSET(i) + 8); 695 USTORM_ASSERT_LIST_OFFSET(i) + 8);
696 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 696 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
697 USTORM_ASSERT_LIST_OFFSET(i) + 12); 697 USTORM_ASSERT_LIST_OFFSET(i) + 12);
698 698
699 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 699 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
700 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" 700 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
701 " 0x%08x 0x%08x 0x%08x\n", 701 " 0x%08x 0x%08x 0x%08x\n",
702 i, row3, row2, row1, row0); 702 i, row3, row2, row1, row0);
703 rc++; 703 rc++;
704 } else { 704 } else {
705 break; 705 break;
706 } 706 }
707 } 707 }
708 708
709 return rc; 709 return rc;
710 } 710 }
711 711
712 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 712 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
713 { 713 {
714 u32 addr, val; 714 u32 addr, val;
715 u32 mark, offset; 715 u32 mark, offset;
716 __be32 data[9]; 716 __be32 data[9];
717 int word; 717 int word;
718 u32 trace_shmem_base; 718 u32 trace_shmem_base;
719 if (BP_NOMCP(bp)) { 719 if (BP_NOMCP(bp)) {
720 BNX2X_ERR("NO MCP - can not dump\n"); 720 BNX2X_ERR("NO MCP - can not dump\n");
721 return; 721 return;
722 } 722 }
723 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 723 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
724 (bp->common.bc_ver & 0xff0000) >> 16, 724 (bp->common.bc_ver & 0xff0000) >> 16,
725 (bp->common.bc_ver & 0xff00) >> 8, 725 (bp->common.bc_ver & 0xff00) >> 8,
726 (bp->common.bc_ver & 0xff)); 726 (bp->common.bc_ver & 0xff));
727 727
728 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 728 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
729 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 729 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
730 printk("%s" "MCP PC at 0x%x\n", lvl, val); 730 printk("%s" "MCP PC at 0x%x\n", lvl, val);
731 731
732 if (BP_PATH(bp) == 0) 732 if (BP_PATH(bp) == 0)
733 trace_shmem_base = bp->common.shmem_base; 733 trace_shmem_base = bp->common.shmem_base;
734 else 734 else
735 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 735 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
736 addr = trace_shmem_base - 0x0800 + 4; 736 addr = trace_shmem_base - 0x0800 + 4;
737 mark = REG_RD(bp, addr); 737 mark = REG_RD(bp, addr);
738 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 738 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
739 + ((mark + 0x3) & ~0x3) - 0x08000000; 739 + ((mark + 0x3) & ~0x3) - 0x08000000;
740 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 740 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
741 741
742 printk("%s", lvl); 742 printk("%s", lvl);
743 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 743 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
744 for (word = 0; word < 8; word++) 744 for (word = 0; word < 8; word++)
745 data[word] = htonl(REG_RD(bp, offset + 4*word)); 745 data[word] = htonl(REG_RD(bp, offset + 4*word));
746 data[8] = 0x0; 746 data[8] = 0x0;
747 pr_cont("%s", (char *)data); 747 pr_cont("%s", (char *)data);
748 } 748 }
749 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 749 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
750 for (word = 0; word < 8; word++) 750 for (word = 0; word < 8; word++)
751 data[word] = htonl(REG_RD(bp, offset + 4*word)); 751 data[word] = htonl(REG_RD(bp, offset + 4*word));
752 data[8] = 0x0; 752 data[8] = 0x0;
753 pr_cont("%s", (char *)data); 753 pr_cont("%s", (char *)data);
754 } 754 }
755 printk("%s" "end of fw dump\n", lvl); 755 printk("%s" "end of fw dump\n", lvl);
756 } 756 }
757 757
758 static inline void bnx2x_fw_dump(struct bnx2x *bp) 758 static inline void bnx2x_fw_dump(struct bnx2x *bp)
759 { 759 {
760 bnx2x_fw_dump_lvl(bp, KERN_ERR); 760 bnx2x_fw_dump_lvl(bp, KERN_ERR);
761 } 761 }
762 762
763 void bnx2x_panic_dump(struct bnx2x *bp) 763 void bnx2x_panic_dump(struct bnx2x *bp)
764 { 764 {
765 int i; 765 int i;
766 u16 j; 766 u16 j;
767 struct hc_sp_status_block_data sp_sb_data; 767 struct hc_sp_status_block_data sp_sb_data;
768 int func = BP_FUNC(bp); 768 int func = BP_FUNC(bp);
769 #ifdef BNX2X_STOP_ON_ERROR 769 #ifdef BNX2X_STOP_ON_ERROR
770 u16 start = 0, end = 0; 770 u16 start = 0, end = 0;
771 u8 cos; 771 u8 cos;
772 #endif 772 #endif
773 773
774 bp->stats_state = STATS_STATE_DISABLED; 774 bp->stats_state = STATS_STATE_DISABLED;
775 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 775 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
776 776
777 BNX2X_ERR("begin crash dump -----------------\n"); 777 BNX2X_ERR("begin crash dump -----------------\n");
778 778
779 /* Indices */ 779 /* Indices */
780 /* Common */ 780 /* Common */
781 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" 781 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
782 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 782 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
783 bp->def_idx, bp->def_att_idx, bp->attn_state, 783 bp->def_idx, bp->def_att_idx, bp->attn_state,
784 bp->spq_prod_idx, bp->stats_counter); 784 bp->spq_prod_idx, bp->stats_counter);
785 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 785 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
786 bp->def_status_blk->atten_status_block.attn_bits, 786 bp->def_status_blk->atten_status_block.attn_bits,
787 bp->def_status_blk->atten_status_block.attn_bits_ack, 787 bp->def_status_blk->atten_status_block.attn_bits_ack,
788 bp->def_status_blk->atten_status_block.status_block_id, 788 bp->def_status_blk->atten_status_block.status_block_id,
789 bp->def_status_blk->atten_status_block.attn_bits_index); 789 bp->def_status_blk->atten_status_block.attn_bits_index);
790 BNX2X_ERR(" def ("); 790 BNX2X_ERR(" def (");
791 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 791 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
792 pr_cont("0x%x%s", 792 pr_cont("0x%x%s",
793 bp->def_status_blk->sp_sb.index_values[i], 793 bp->def_status_blk->sp_sb.index_values[i],
794 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 794 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
795 795
796 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 796 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
797 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 797 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
798 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 798 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
799 i*sizeof(u32)); 799 i*sizeof(u32));
800 800
801 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 801 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
802 sp_sb_data.igu_sb_id, 802 sp_sb_data.igu_sb_id,
803 sp_sb_data.igu_seg_id, 803 sp_sb_data.igu_seg_id,
804 sp_sb_data.p_func.pf_id, 804 sp_sb_data.p_func.pf_id,
805 sp_sb_data.p_func.vnic_id, 805 sp_sb_data.p_func.vnic_id,
806 sp_sb_data.p_func.vf_id, 806 sp_sb_data.p_func.vf_id,
807 sp_sb_data.p_func.vf_valid, 807 sp_sb_data.p_func.vf_valid,
808 sp_sb_data.state); 808 sp_sb_data.state);
809 809
810 810
811 for_each_eth_queue(bp, i) { 811 for_each_eth_queue(bp, i) {
812 struct bnx2x_fastpath *fp = &bp->fp[i]; 812 struct bnx2x_fastpath *fp = &bp->fp[i];
813 int loop; 813 int loop;
814 struct hc_status_block_data_e2 sb_data_e2; 814 struct hc_status_block_data_e2 sb_data_e2;
815 struct hc_status_block_data_e1x sb_data_e1x; 815 struct hc_status_block_data_e1x sb_data_e1x;
816 struct hc_status_block_sm *hc_sm_p = 816 struct hc_status_block_sm *hc_sm_p =
817 CHIP_IS_E1x(bp) ? 817 CHIP_IS_E1x(bp) ?
818 sb_data_e1x.common.state_machine : 818 sb_data_e1x.common.state_machine :
819 sb_data_e2.common.state_machine; 819 sb_data_e2.common.state_machine;
820 struct hc_index_data *hc_index_p = 820 struct hc_index_data *hc_index_p =
821 CHIP_IS_E1x(bp) ? 821 CHIP_IS_E1x(bp) ?
822 sb_data_e1x.index_data : 822 sb_data_e1x.index_data :
823 sb_data_e2.index_data; 823 sb_data_e2.index_data;
824 u8 data_size, cos; 824 u8 data_size, cos;
825 u32 *sb_data_p; 825 u32 *sb_data_p;
826 struct bnx2x_fp_txdata txdata; 826 struct bnx2x_fp_txdata txdata;
827 827
828 /* Rx */ 828 /* Rx */
829 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" 829 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
830 " rx_comp_prod(0x%x)" 830 " rx_comp_prod(0x%x)"
831 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 831 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
832 i, fp->rx_bd_prod, fp->rx_bd_cons, 832 i, fp->rx_bd_prod, fp->rx_bd_cons,
833 fp->rx_comp_prod, 833 fp->rx_comp_prod,
834 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 834 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
835 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" 835 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
836 " fp_hc_idx(0x%x)\n", 836 " fp_hc_idx(0x%x)\n",
837 fp->rx_sge_prod, fp->last_max_sge, 837 fp->rx_sge_prod, fp->last_max_sge,
838 le16_to_cpu(fp->fp_hc_idx)); 838 le16_to_cpu(fp->fp_hc_idx));
839 839
840 /* Tx */ 840 /* Tx */
841 for_each_cos_in_tx_queue(fp, cos) 841 for_each_cos_in_tx_queue(fp, cos)
842 { 842 {
843 txdata = fp->txdata[cos]; 843 txdata = fp->txdata[cos];
844 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" 844 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
845 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" 845 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
846 " *tx_cons_sb(0x%x)\n", 846 " *tx_cons_sb(0x%x)\n",
847 i, txdata.tx_pkt_prod, 847 i, txdata.tx_pkt_prod,
848 txdata.tx_pkt_cons, txdata.tx_bd_prod, 848 txdata.tx_pkt_cons, txdata.tx_bd_prod,
849 txdata.tx_bd_cons, 849 txdata.tx_bd_cons,
850 le16_to_cpu(*txdata.tx_cons_sb)); 850 le16_to_cpu(*txdata.tx_cons_sb));
851 } 851 }
852 852
853 loop = CHIP_IS_E1x(bp) ? 853 loop = CHIP_IS_E1x(bp) ?
854 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 854 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
855 855
856 /* host sb data */ 856 /* host sb data */
857 857
858 #ifdef BCM_CNIC 858 #ifdef BCM_CNIC
859 if (IS_FCOE_FP(fp)) 859 if (IS_FCOE_FP(fp))
860 continue; 860 continue;
861 #endif 861 #endif
862 BNX2X_ERR(" run indexes ("); 862 BNX2X_ERR(" run indexes (");
863 for (j = 0; j < HC_SB_MAX_SM; j++) 863 for (j = 0; j < HC_SB_MAX_SM; j++)
864 pr_cont("0x%x%s", 864 pr_cont("0x%x%s",
865 fp->sb_running_index[j], 865 fp->sb_running_index[j],
866 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 866 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
867 867
868 BNX2X_ERR(" indexes ("); 868 BNX2X_ERR(" indexes (");
869 for (j = 0; j < loop; j++) 869 for (j = 0; j < loop; j++)
870 pr_cont("0x%x%s", 870 pr_cont("0x%x%s",
871 fp->sb_index_values[j], 871 fp->sb_index_values[j],
872 (j == loop - 1) ? ")" : " "); 872 (j == loop - 1) ? ")" : " ");
873 /* fw sb data */ 873 /* fw sb data */
874 data_size = CHIP_IS_E1x(bp) ? 874 data_size = CHIP_IS_E1x(bp) ?
875 sizeof(struct hc_status_block_data_e1x) : 875 sizeof(struct hc_status_block_data_e1x) :
876 sizeof(struct hc_status_block_data_e2); 876 sizeof(struct hc_status_block_data_e2);
877 data_size /= sizeof(u32); 877 data_size /= sizeof(u32);
878 sb_data_p = CHIP_IS_E1x(bp) ? 878 sb_data_p = CHIP_IS_E1x(bp) ?
879 (u32 *)&sb_data_e1x : 879 (u32 *)&sb_data_e1x :
880 (u32 *)&sb_data_e2; 880 (u32 *)&sb_data_e2;
881 /* copy sb data in here */ 881 /* copy sb data in here */
882 for (j = 0; j < data_size; j++) 882 for (j = 0; j < data_size; j++)
883 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 883 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
884 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 884 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
885 j * sizeof(u32)); 885 j * sizeof(u32));
886 886
887 if (!CHIP_IS_E1x(bp)) { 887 if (!CHIP_IS_E1x(bp)) {
888 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 888 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
889 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 889 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
890 "state(0x%x)\n", 890 "state(0x%x)\n",
891 sb_data_e2.common.p_func.pf_id, 891 sb_data_e2.common.p_func.pf_id,
892 sb_data_e2.common.p_func.vf_id, 892 sb_data_e2.common.p_func.vf_id,
893 sb_data_e2.common.p_func.vf_valid, 893 sb_data_e2.common.p_func.vf_valid,
894 sb_data_e2.common.p_func.vnic_id, 894 sb_data_e2.common.p_func.vnic_id,
895 sb_data_e2.common.same_igu_sb_1b, 895 sb_data_e2.common.same_igu_sb_1b,
896 sb_data_e2.common.state); 896 sb_data_e2.common.state);
897 } else { 897 } else {
898 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 898 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
899 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 899 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
900 "state(0x%x)\n", 900 "state(0x%x)\n",
901 sb_data_e1x.common.p_func.pf_id, 901 sb_data_e1x.common.p_func.pf_id,
902 sb_data_e1x.common.p_func.vf_id, 902 sb_data_e1x.common.p_func.vf_id,
903 sb_data_e1x.common.p_func.vf_valid, 903 sb_data_e1x.common.p_func.vf_valid,
904 sb_data_e1x.common.p_func.vnic_id, 904 sb_data_e1x.common.p_func.vnic_id,
905 sb_data_e1x.common.same_igu_sb_1b, 905 sb_data_e1x.common.same_igu_sb_1b,
906 sb_data_e1x.common.state); 906 sb_data_e1x.common.state);
907 } 907 }
908 908
909 /* SB_SMs data */ 909 /* SB_SMs data */
910 for (j = 0; j < HC_SB_MAX_SM; j++) { 910 for (j = 0; j < HC_SB_MAX_SM; j++) {
911 pr_cont("SM[%d] __flags (0x%x) " 911 pr_cont("SM[%d] __flags (0x%x) "
912 "igu_sb_id (0x%x) igu_seg_id(0x%x) " 912 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
913 "time_to_expire (0x%x) " 913 "time_to_expire (0x%x) "
914 "timer_value(0x%x)\n", j, 914 "timer_value(0x%x)\n", j,
915 hc_sm_p[j].__flags, 915 hc_sm_p[j].__flags,
916 hc_sm_p[j].igu_sb_id, 916 hc_sm_p[j].igu_sb_id,
917 hc_sm_p[j].igu_seg_id, 917 hc_sm_p[j].igu_seg_id,
918 hc_sm_p[j].time_to_expire, 918 hc_sm_p[j].time_to_expire,
919 hc_sm_p[j].timer_value); 919 hc_sm_p[j].timer_value);
920 } 920 }
921 921
922 /* Indecies data */ 922 /* Indecies data */
923 for (j = 0; j < loop; j++) { 923 for (j = 0; j < loop; j++) {
924 pr_cont("INDEX[%d] flags (0x%x) " 924 pr_cont("INDEX[%d] flags (0x%x) "
925 "timeout (0x%x)\n", j, 925 "timeout (0x%x)\n", j,
926 hc_index_p[j].flags, 926 hc_index_p[j].flags,
927 hc_index_p[j].timeout); 927 hc_index_p[j].timeout);
928 } 928 }
929 } 929 }
930 930
931 #ifdef BNX2X_STOP_ON_ERROR 931 #ifdef BNX2X_STOP_ON_ERROR
932 /* Rings */ 932 /* Rings */
933 /* Rx */ 933 /* Rx */
934 for_each_rx_queue(bp, i) { 934 for_each_rx_queue(bp, i) {
935 struct bnx2x_fastpath *fp = &bp->fp[i]; 935 struct bnx2x_fastpath *fp = &bp->fp[i];
936 936
937 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 937 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
938 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 938 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
939 for (j = start; j != end; j = RX_BD(j + 1)) { 939 for (j = start; j != end; j = RX_BD(j + 1)) {
940 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 940 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
941 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 941 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
942 942
943 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 943 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
944 i, j, rx_bd[1], rx_bd[0], sw_bd->skb); 944 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
945 } 945 }
946 946
947 start = RX_SGE(fp->rx_sge_prod); 947 start = RX_SGE(fp->rx_sge_prod);
948 end = RX_SGE(fp->last_max_sge); 948 end = RX_SGE(fp->last_max_sge);
949 for (j = start; j != end; j = RX_SGE(j + 1)) { 949 for (j = start; j != end; j = RX_SGE(j + 1)) {
950 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 950 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
951 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 951 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
952 952
953 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 953 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
954 i, j, rx_sge[1], rx_sge[0], sw_page->page); 954 i, j, rx_sge[1], rx_sge[0], sw_page->page);
955 } 955 }
956 956
957 start = RCQ_BD(fp->rx_comp_cons - 10); 957 start = RCQ_BD(fp->rx_comp_cons - 10);
958 end = RCQ_BD(fp->rx_comp_cons + 503); 958 end = RCQ_BD(fp->rx_comp_cons + 503);
959 for (j = start; j != end; j = RCQ_BD(j + 1)) { 959 for (j = start; j != end; j = RCQ_BD(j + 1)) {
960 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 960 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
961 961
962 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 962 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
963 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 963 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
964 } 964 }
965 } 965 }
966 966
967 /* Tx */ 967 /* Tx */
968 for_each_tx_queue(bp, i) { 968 for_each_tx_queue(bp, i) {
969 struct bnx2x_fastpath *fp = &bp->fp[i]; 969 struct bnx2x_fastpath *fp = &bp->fp[i];
970 for_each_cos_in_tx_queue(fp, cos) { 970 for_each_cos_in_tx_queue(fp, cos) {
971 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 971 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
972 972
973 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 973 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
974 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 974 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
975 for (j = start; j != end; j = TX_BD(j + 1)) { 975 for (j = start; j != end; j = TX_BD(j + 1)) {
976 struct sw_tx_bd *sw_bd = 976 struct sw_tx_bd *sw_bd =
977 &txdata->tx_buf_ring[j]; 977 &txdata->tx_buf_ring[j];
978 978
979 BNX2X_ERR("fp%d: txdata %d, " 979 BNX2X_ERR("fp%d: txdata %d, "
980 "packet[%x]=[%p,%x]\n", 980 "packet[%x]=[%p,%x]\n",
981 i, cos, j, sw_bd->skb, 981 i, cos, j, sw_bd->skb,
982 sw_bd->first_bd); 982 sw_bd->first_bd);
983 } 983 }
984 984
985 start = TX_BD(txdata->tx_bd_cons - 10); 985 start = TX_BD(txdata->tx_bd_cons - 10);
986 end = TX_BD(txdata->tx_bd_cons + 254); 986 end = TX_BD(txdata->tx_bd_cons + 254);
987 for (j = start; j != end; j = TX_BD(j + 1)) { 987 for (j = start; j != end; j = TX_BD(j + 1)) {
988 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 988 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
989 989
990 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" 990 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
991 "[%x:%x:%x:%x]\n", 991 "[%x:%x:%x:%x]\n",
992 i, cos, j, tx_bd[0], tx_bd[1], 992 i, cos, j, tx_bd[0], tx_bd[1],
993 tx_bd[2], tx_bd[3]); 993 tx_bd[2], tx_bd[3]);
994 } 994 }
995 } 995 }
996 } 996 }
997 #endif 997 #endif
998 bnx2x_fw_dump(bp); 998 bnx2x_fw_dump(bp);
999 bnx2x_mc_assert(bp); 999 bnx2x_mc_assert(bp);
1000 BNX2X_ERR("end crash dump -----------------\n"); 1000 BNX2X_ERR("end crash dump -----------------\n");
1001 } 1001 }
1002 1002
1003 /* 1003 /*
1004 * FLR Support for E2 1004 * FLR Support for E2
1005 * 1005 *
1006 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1006 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1007 * initialization. 1007 * initialization.
1008 */ 1008 */
1009 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 1009 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1010 #define FLR_WAIT_INTERAVAL 50 /* usec */ 1010 #define FLR_WAIT_INTERAVAL 50 /* usec */
1011 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */ 1011 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1012 1012
1013 struct pbf_pN_buf_regs { 1013 struct pbf_pN_buf_regs {
1014 int pN; 1014 int pN;
1015 u32 init_crd; 1015 u32 init_crd;
1016 u32 crd; 1016 u32 crd;
1017 u32 crd_freed; 1017 u32 crd_freed;
1018 }; 1018 };
1019 1019
1020 struct pbf_pN_cmd_regs { 1020 struct pbf_pN_cmd_regs {
1021 int pN; 1021 int pN;
1022 u32 lines_occup; 1022 u32 lines_occup;
1023 u32 lines_freed; 1023 u32 lines_freed;
1024 }; 1024 };
1025 1025
1026 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1026 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1027 struct pbf_pN_buf_regs *regs, 1027 struct pbf_pN_buf_regs *regs,
1028 u32 poll_count) 1028 u32 poll_count)
1029 { 1029 {
1030 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1030 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1031 u32 cur_cnt = poll_count; 1031 u32 cur_cnt = poll_count;
1032 1032
1033 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1033 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1034 crd = crd_start = REG_RD(bp, regs->crd); 1034 crd = crd_start = REG_RD(bp, regs->crd);
1035 init_crd = REG_RD(bp, regs->init_crd); 1035 init_crd = REG_RD(bp, regs->init_crd);
1036 1036
1037 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1037 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1038 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1038 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1039 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1039 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1040 1040
1041 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1041 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1042 (init_crd - crd_start))) { 1042 (init_crd - crd_start))) {
1043 if (cur_cnt--) { 1043 if (cur_cnt--) {
1044 udelay(FLR_WAIT_INTERAVAL); 1044 udelay(FLR_WAIT_INTERAVAL);
1045 crd = REG_RD(bp, regs->crd); 1045 crd = REG_RD(bp, regs->crd);
1046 crd_freed = REG_RD(bp, regs->crd_freed); 1046 crd_freed = REG_RD(bp, regs->crd_freed);
1047 } else { 1047 } else {
1048 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1048 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1049 regs->pN); 1049 regs->pN);
1050 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1050 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1051 regs->pN, crd); 1051 regs->pN, crd);
1052 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1052 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1053 regs->pN, crd_freed); 1053 regs->pN, crd_freed);
1054 break; 1054 break;
1055 } 1055 }
1056 } 1056 }
1057 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1057 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1058 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); 1058 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1059 } 1059 }
1060 1060
1061 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1061 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1062 struct pbf_pN_cmd_regs *regs, 1062 struct pbf_pN_cmd_regs *regs,
1063 u32 poll_count) 1063 u32 poll_count)
1064 { 1064 {
1065 u32 occup, to_free, freed, freed_start; 1065 u32 occup, to_free, freed, freed_start;
1066 u32 cur_cnt = poll_count; 1066 u32 cur_cnt = poll_count;
1067 1067
1068 occup = to_free = REG_RD(bp, regs->lines_occup); 1068 occup = to_free = REG_RD(bp, regs->lines_occup);
1069 freed = freed_start = REG_RD(bp, regs->lines_freed); 1069 freed = freed_start = REG_RD(bp, regs->lines_freed);
1070 1070
1071 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1071 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1072 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1072 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1073 1073
1074 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1074 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1075 if (cur_cnt--) { 1075 if (cur_cnt--) {
1076 udelay(FLR_WAIT_INTERAVAL); 1076 udelay(FLR_WAIT_INTERAVAL);
1077 occup = REG_RD(bp, regs->lines_occup); 1077 occup = REG_RD(bp, regs->lines_occup);
1078 freed = REG_RD(bp, regs->lines_freed); 1078 freed = REG_RD(bp, regs->lines_freed);
1079 } else { 1079 } else {
1080 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1080 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1081 regs->pN); 1081 regs->pN);
1082 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1082 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1083 regs->pN, occup); 1083 regs->pN, occup);
1084 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1084 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1085 regs->pN, freed); 1085 regs->pN, freed);
1086 break; 1086 break;
1087 } 1087 }
1088 } 1088 }
1089 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1089 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1090 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); 1090 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1091 } 1091 }
1092 1092
1093 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1093 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1094 u32 expected, u32 poll_count) 1094 u32 expected, u32 poll_count)
1095 { 1095 {
1096 u32 cur_cnt = poll_count; 1096 u32 cur_cnt = poll_count;
1097 u32 val; 1097 u32 val;
1098 1098
1099 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1099 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1100 udelay(FLR_WAIT_INTERAVAL); 1100 udelay(FLR_WAIT_INTERAVAL);
1101 1101
1102 return val; 1102 return val;
1103 } 1103 }
1104 1104
1105 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1105 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1106 char *msg, u32 poll_cnt) 1106 char *msg, u32 poll_cnt)
1107 { 1107 {
1108 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1108 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1109 if (val != 0) { 1109 if (val != 0) {
1110 BNX2X_ERR("%s usage count=%d\n", msg, val); 1110 BNX2X_ERR("%s usage count=%d\n", msg, val);
1111 return 1; 1111 return 1;
1112 } 1112 }
1113 return 0; 1113 return 0;
1114 } 1114 }
1115 1115
1116 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1116 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1117 { 1117 {
1118 /* adjust polling timeout */ 1118 /* adjust polling timeout */
1119 if (CHIP_REV_IS_EMUL(bp)) 1119 if (CHIP_REV_IS_EMUL(bp))
1120 return FLR_POLL_CNT * 2000; 1120 return FLR_POLL_CNT * 2000;
1121 1121
1122 if (CHIP_REV_IS_FPGA(bp)) 1122 if (CHIP_REV_IS_FPGA(bp))
1123 return FLR_POLL_CNT * 120; 1123 return FLR_POLL_CNT * 120;
1124 1124
1125 return FLR_POLL_CNT; 1125 return FLR_POLL_CNT;
1126 } 1126 }
1127 1127
1128 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1128 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1129 { 1129 {
1130 struct pbf_pN_cmd_regs cmd_regs[] = { 1130 struct pbf_pN_cmd_regs cmd_regs[] = {
1131 {0, (CHIP_IS_E3B0(bp)) ? 1131 {0, (CHIP_IS_E3B0(bp)) ?
1132 PBF_REG_TQ_OCCUPANCY_Q0 : 1132 PBF_REG_TQ_OCCUPANCY_Q0 :
1133 PBF_REG_P0_TQ_OCCUPANCY, 1133 PBF_REG_P0_TQ_OCCUPANCY,
1134 (CHIP_IS_E3B0(bp)) ? 1134 (CHIP_IS_E3B0(bp)) ?
1135 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1135 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1136 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1136 PBF_REG_P0_TQ_LINES_FREED_CNT},
1137 {1, (CHIP_IS_E3B0(bp)) ? 1137 {1, (CHIP_IS_E3B0(bp)) ?
1138 PBF_REG_TQ_OCCUPANCY_Q1 : 1138 PBF_REG_TQ_OCCUPANCY_Q1 :
1139 PBF_REG_P1_TQ_OCCUPANCY, 1139 PBF_REG_P1_TQ_OCCUPANCY,
1140 (CHIP_IS_E3B0(bp)) ? 1140 (CHIP_IS_E3B0(bp)) ?
1141 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1141 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1142 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1142 PBF_REG_P1_TQ_LINES_FREED_CNT},
1143 {4, (CHIP_IS_E3B0(bp)) ? 1143 {4, (CHIP_IS_E3B0(bp)) ?
1144 PBF_REG_TQ_OCCUPANCY_LB_Q : 1144 PBF_REG_TQ_OCCUPANCY_LB_Q :
1145 PBF_REG_P4_TQ_OCCUPANCY, 1145 PBF_REG_P4_TQ_OCCUPANCY,
1146 (CHIP_IS_E3B0(bp)) ? 1146 (CHIP_IS_E3B0(bp)) ?
1147 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1147 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1148 PBF_REG_P4_TQ_LINES_FREED_CNT} 1148 PBF_REG_P4_TQ_LINES_FREED_CNT}
1149 }; 1149 };
1150 1150
1151 struct pbf_pN_buf_regs buf_regs[] = { 1151 struct pbf_pN_buf_regs buf_regs[] = {
1152 {0, (CHIP_IS_E3B0(bp)) ? 1152 {0, (CHIP_IS_E3B0(bp)) ?
1153 PBF_REG_INIT_CRD_Q0 : 1153 PBF_REG_INIT_CRD_Q0 :
1154 PBF_REG_P0_INIT_CRD , 1154 PBF_REG_P0_INIT_CRD ,
1155 (CHIP_IS_E3B0(bp)) ? 1155 (CHIP_IS_E3B0(bp)) ?
1156 PBF_REG_CREDIT_Q0 : 1156 PBF_REG_CREDIT_Q0 :
1157 PBF_REG_P0_CREDIT, 1157 PBF_REG_P0_CREDIT,
1158 (CHIP_IS_E3B0(bp)) ? 1158 (CHIP_IS_E3B0(bp)) ?
1159 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1159 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1160 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1160 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1161 {1, (CHIP_IS_E3B0(bp)) ? 1161 {1, (CHIP_IS_E3B0(bp)) ?
1162 PBF_REG_INIT_CRD_Q1 : 1162 PBF_REG_INIT_CRD_Q1 :
1163 PBF_REG_P1_INIT_CRD, 1163 PBF_REG_P1_INIT_CRD,
1164 (CHIP_IS_E3B0(bp)) ? 1164 (CHIP_IS_E3B0(bp)) ?
1165 PBF_REG_CREDIT_Q1 : 1165 PBF_REG_CREDIT_Q1 :
1166 PBF_REG_P1_CREDIT, 1166 PBF_REG_P1_CREDIT,
1167 (CHIP_IS_E3B0(bp)) ? 1167 (CHIP_IS_E3B0(bp)) ?
1168 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1168 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1169 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1169 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1170 {4, (CHIP_IS_E3B0(bp)) ? 1170 {4, (CHIP_IS_E3B0(bp)) ?
1171 PBF_REG_INIT_CRD_LB_Q : 1171 PBF_REG_INIT_CRD_LB_Q :
1172 PBF_REG_P4_INIT_CRD, 1172 PBF_REG_P4_INIT_CRD,
1173 (CHIP_IS_E3B0(bp)) ? 1173 (CHIP_IS_E3B0(bp)) ?
1174 PBF_REG_CREDIT_LB_Q : 1174 PBF_REG_CREDIT_LB_Q :
1175 PBF_REG_P4_CREDIT, 1175 PBF_REG_P4_CREDIT,
1176 (CHIP_IS_E3B0(bp)) ? 1176 (CHIP_IS_E3B0(bp)) ?
1177 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1177 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1178 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1178 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1179 }; 1179 };
1180 1180
1181 int i; 1181 int i;
1182 1182
1183 /* Verify the command queues are flushed P0, P1, P4 */ 1183 /* Verify the command queues are flushed P0, P1, P4 */
1184 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1184 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1185 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1185 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1186 1186
1187 1187
1188 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1188 /* Verify the transmission buffers are flushed P0, P1, P4 */
1189 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1189 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1190 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1190 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1191 } 1191 }
1192 1192
1193 #define OP_GEN_PARAM(param) \ 1193 #define OP_GEN_PARAM(param) \
1194 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1194 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1195 1195
1196 #define OP_GEN_TYPE(type) \ 1196 #define OP_GEN_TYPE(type) \
1197 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1197 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1198 1198
1199 #define OP_GEN_AGG_VECT(index) \ 1199 #define OP_GEN_AGG_VECT(index) \
1200 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1200 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1201 1201
1202 1202
1203 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 1203 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1204 u32 poll_cnt) 1204 u32 poll_cnt)
1205 { 1205 {
1206 struct sdm_op_gen op_gen = {0}; 1206 struct sdm_op_gen op_gen = {0};
1207 1207
1208 u32 comp_addr = BAR_CSTRORM_INTMEM + 1208 u32 comp_addr = BAR_CSTRORM_INTMEM +
1209 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1209 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1210 int ret = 0; 1210 int ret = 0;
1211 1211
1212 if (REG_RD(bp, comp_addr)) { 1212 if (REG_RD(bp, comp_addr)) {
1213 BNX2X_ERR("Cleanup complete is not 0\n"); 1213 BNX2X_ERR("Cleanup complete is not 0\n");
1214 return 1; 1214 return 1;
1215 } 1215 }
1216 1216
1217 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1217 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1218 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1218 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1219 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1219 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1220 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1220 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1221 1221
1222 DP(BNX2X_MSG_SP, "FW Final cleanup\n"); 1222 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1223 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1223 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1224 1224
1225 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1225 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1226 BNX2X_ERR("FW final cleanup did not succeed\n"); 1226 BNX2X_ERR("FW final cleanup did not succeed\n");
1227 ret = 1; 1227 ret = 1;
1228 } 1228 }
1229 /* Zero completion for nxt FLR */ 1229 /* Zero completion for nxt FLR */
1230 REG_WR(bp, comp_addr, 0); 1230 REG_WR(bp, comp_addr, 0);
1231 1231
1232 return ret; 1232 return ret;
1233 } 1233 }
1234 1234
1235 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1235 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1236 { 1236 {
1237 int pos; 1237 int pos;
1238 u16 status; 1238 u16 status;
1239 1239
1240 pos = pci_pcie_cap(dev); 1240 pos = pci_pcie_cap(dev);
1241 if (!pos) 1241 if (!pos)
1242 return false; 1242 return false;
1243 1243
1244 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 1244 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1245 return status & PCI_EXP_DEVSTA_TRPND; 1245 return status & PCI_EXP_DEVSTA_TRPND;
1246 } 1246 }
1247 1247
1248 /* PF FLR specific routines 1248 /* PF FLR specific routines
1249 */ 1249 */
1250 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1250 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1251 { 1251 {
1252 1252
1253 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1253 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1254 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1254 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1255 CFC_REG_NUM_LCIDS_INSIDE_PF, 1255 CFC_REG_NUM_LCIDS_INSIDE_PF,
1256 "CFC PF usage counter timed out", 1256 "CFC PF usage counter timed out",
1257 poll_cnt)) 1257 poll_cnt))
1258 return 1; 1258 return 1;
1259 1259
1260 1260
1261 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1261 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1262 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1262 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1263 DORQ_REG_PF_USAGE_CNT, 1263 DORQ_REG_PF_USAGE_CNT,
1264 "DQ PF usage counter timed out", 1264 "DQ PF usage counter timed out",
1265 poll_cnt)) 1265 poll_cnt))
1266 return 1; 1266 return 1;
1267 1267
1268 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1268 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1269 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1269 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1270 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1270 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1271 "QM PF usage counter timed out", 1271 "QM PF usage counter timed out",
1272 poll_cnt)) 1272 poll_cnt))
1273 return 1; 1273 return 1;
1274 1274
1275 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1275 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1276 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1276 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1277 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1277 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1278 "Timers VNIC usage counter timed out", 1278 "Timers VNIC usage counter timed out",
1279 poll_cnt)) 1279 poll_cnt))
1280 return 1; 1280 return 1;
1281 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1281 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1282 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1282 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1283 "Timers NUM_SCANS usage counter timed out", 1283 "Timers NUM_SCANS usage counter timed out",
1284 poll_cnt)) 1284 poll_cnt))
1285 return 1; 1285 return 1;
1286 1286
1287 /* Wait DMAE PF usage counter to zero */ 1287 /* Wait DMAE PF usage counter to zero */
1288 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1288 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1289 dmae_reg_go_c[INIT_DMAE_C(bp)], 1289 dmae_reg_go_c[INIT_DMAE_C(bp)],
1290 "DMAE dommand register timed out", 1290 "DMAE dommand register timed out",
1291 poll_cnt)) 1291 poll_cnt))
1292 return 1; 1292 return 1;
1293 1293
1294 return 0; 1294 return 0;
1295 } 1295 }
1296 1296
1297 static void bnx2x_hw_enable_status(struct bnx2x *bp) 1297 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1298 { 1298 {
1299 u32 val; 1299 u32 val;
1300 1300
1301 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1301 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1302 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1302 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1303 1303
1304 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1304 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1305 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1305 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1306 1306
1307 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1307 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1308 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1308 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1309 1309
1310 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1310 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1311 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1311 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1312 1312
1313 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1313 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1314 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1314 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1315 1315
1316 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1316 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1317 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1317 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1318 1318
1319 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1319 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1320 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1320 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1321 1321
1322 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1322 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1323 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1323 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1324 val); 1324 val);
1325 } 1325 }
1326 1326
1327 static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1327 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1328 { 1328 {
1329 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1329 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1330 1330
1331 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1331 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1332 1332
1333 /* Re-enable PF target read access */ 1333 /* Re-enable PF target read access */
1334 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1334 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1335 1335
1336 /* Poll HW usage counters */ 1336 /* Poll HW usage counters */
1337 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1337 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1338 return -EBUSY; 1338 return -EBUSY;
1339 1339
1340 /* Zero the igu 'trailing edge' and 'leading edge' */ 1340 /* Zero the igu 'trailing edge' and 'leading edge' */
1341 1341
1342 /* Send the FW cleanup command */ 1342 /* Send the FW cleanup command */
1343 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1343 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1344 return -EBUSY; 1344 return -EBUSY;
1345 1345
1346 /* ATC cleanup */ 1346 /* ATC cleanup */
1347 1347
1348 /* Verify TX hw is flushed */ 1348 /* Verify TX hw is flushed */
1349 bnx2x_tx_hw_flushed(bp, poll_cnt); 1349 bnx2x_tx_hw_flushed(bp, poll_cnt);
1350 1350
1351 /* Wait 100ms (not adjusted according to platform) */ 1351 /* Wait 100ms (not adjusted according to platform) */
1352 msleep(100); 1352 msleep(100);
1353 1353
1354 /* Verify no pending pci transactions */ 1354 /* Verify no pending pci transactions */
1355 if (bnx2x_is_pcie_pending(bp->pdev)) 1355 if (bnx2x_is_pcie_pending(bp->pdev))
1356 BNX2X_ERR("PCIE Transactions still pending\n"); 1356 BNX2X_ERR("PCIE Transactions still pending\n");
1357 1357
1358 /* Debug */ 1358 /* Debug */
1359 bnx2x_hw_enable_status(bp); 1359 bnx2x_hw_enable_status(bp);
1360 1360
1361 /* 1361 /*
1362 * Master enable - Due to WB DMAE writes performed before this 1362 * Master enable - Due to WB DMAE writes performed before this
1363 * register is re-initialized as part of the regular function init 1363 * register is re-initialized as part of the regular function init
1364 */ 1364 */
1365 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1365 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1366 1366
1367 return 0; 1367 return 0;
1368 } 1368 }
1369 1369
1370 static void bnx2x_hc_int_enable(struct bnx2x *bp) 1370 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1371 { 1371 {
1372 int port = BP_PORT(bp); 1372 int port = BP_PORT(bp);
1373 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1373 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1374 u32 val = REG_RD(bp, addr); 1374 u32 val = REG_RD(bp, addr);
1375 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1375 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1376 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1376 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1377 1377
1378 if (msix) { 1378 if (msix) {
1379 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1379 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1380 HC_CONFIG_0_REG_INT_LINE_EN_0); 1380 HC_CONFIG_0_REG_INT_LINE_EN_0);
1381 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1381 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1382 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1382 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1383 } else if (msi) { 1383 } else if (msi) {
1384 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1384 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1385 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1385 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1387 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1387 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1388 } else { 1388 } else {
1389 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1389 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1390 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1390 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1391 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1391 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1392 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1392 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1393 1393
1394 if (!CHIP_IS_E1(bp)) { 1394 if (!CHIP_IS_E1(bp)) {
1395 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1395 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1396 val, port, addr); 1396 val, port, addr);
1397 1397
1398 REG_WR(bp, addr, val); 1398 REG_WR(bp, addr, val);
1399 1399
1400 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1400 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1401 } 1401 }
1402 } 1402 }
1403 1403
1404 if (CHIP_IS_E1(bp)) 1404 if (CHIP_IS_E1(bp))
1405 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1405 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1406 1406
1407 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 1407 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1408 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1408 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1409 1409
1410 REG_WR(bp, addr, val); 1410 REG_WR(bp, addr, val);
1411 /* 1411 /*
1412 * Ensure that HC_CONFIG is written before leading/trailing edge config 1412 * Ensure that HC_CONFIG is written before leading/trailing edge config
1413 */ 1413 */
1414 mmiowb(); 1414 mmiowb();
1415 barrier(); 1415 barrier();
1416 1416
1417 if (!CHIP_IS_E1(bp)) { 1417 if (!CHIP_IS_E1(bp)) {
1418 /* init leading/trailing edge */ 1418 /* init leading/trailing edge */
1419 if (IS_MF(bp)) { 1419 if (IS_MF(bp)) {
1420 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1420 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1421 if (bp->port.pmf) 1421 if (bp->port.pmf)
1422 /* enable nig and gpio3 attention */ 1422 /* enable nig and gpio3 attention */
1423 val |= 0x1100; 1423 val |= 0x1100;
1424 } else 1424 } else
1425 val = 0xffff; 1425 val = 0xffff;
1426 1426
1427 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1427 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1428 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1428 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1429 } 1429 }
1430 1430
1431 /* Make sure that interrupts are indeed enabled from here on */ 1431 /* Make sure that interrupts are indeed enabled from here on */
1432 mmiowb(); 1432 mmiowb();
1433 } 1433 }
1434 1434
1435 static void bnx2x_igu_int_enable(struct bnx2x *bp) 1435 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1436 { 1436 {
1437 u32 val; 1437 u32 val;
1438 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1438 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1439 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1439 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1440 1440
1441 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1441 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1442 1442
1443 if (msix) { 1443 if (msix) {
1444 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1444 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1445 IGU_PF_CONF_SINGLE_ISR_EN); 1445 IGU_PF_CONF_SINGLE_ISR_EN);
1446 val |= (IGU_PF_CONF_FUNC_EN | 1446 val |= (IGU_PF_CONF_FUNC_EN |
1447 IGU_PF_CONF_MSI_MSIX_EN | 1447 IGU_PF_CONF_MSI_MSIX_EN |
1448 IGU_PF_CONF_ATTN_BIT_EN); 1448 IGU_PF_CONF_ATTN_BIT_EN);
1449 } else if (msi) { 1449 } else if (msi) {
1450 val &= ~IGU_PF_CONF_INT_LINE_EN; 1450 val &= ~IGU_PF_CONF_INT_LINE_EN;
1451 val |= (IGU_PF_CONF_FUNC_EN | 1451 val |= (IGU_PF_CONF_FUNC_EN |
1452 IGU_PF_CONF_MSI_MSIX_EN | 1452 IGU_PF_CONF_MSI_MSIX_EN |
1453 IGU_PF_CONF_ATTN_BIT_EN | 1453 IGU_PF_CONF_ATTN_BIT_EN |
1454 IGU_PF_CONF_SINGLE_ISR_EN); 1454 IGU_PF_CONF_SINGLE_ISR_EN);
1455 } else { 1455 } else {
1456 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1456 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1457 val |= (IGU_PF_CONF_FUNC_EN | 1457 val |= (IGU_PF_CONF_FUNC_EN |
1458 IGU_PF_CONF_INT_LINE_EN | 1458 IGU_PF_CONF_INT_LINE_EN |
1459 IGU_PF_CONF_ATTN_BIT_EN | 1459 IGU_PF_CONF_ATTN_BIT_EN |
1460 IGU_PF_CONF_SINGLE_ISR_EN); 1460 IGU_PF_CONF_SINGLE_ISR_EN);
1461 } 1461 }
1462 1462
1463 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", 1463 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1464 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1464 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1465 1465
1466 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1466 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1467 1467
1468 barrier(); 1468 barrier();
1469 1469
1470 /* init leading/trailing edge */ 1470 /* init leading/trailing edge */
1471 if (IS_MF(bp)) { 1471 if (IS_MF(bp)) {
1472 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1472 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1473 if (bp->port.pmf) 1473 if (bp->port.pmf)
1474 /* enable nig and gpio3 attention */ 1474 /* enable nig and gpio3 attention */
1475 val |= 0x1100; 1475 val |= 0x1100;
1476 } else 1476 } else
1477 val = 0xffff; 1477 val = 0xffff;
1478 1478
1479 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1479 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1480 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1480 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1481 1481
1482 /* Make sure that interrupts are indeed enabled from here on */ 1482 /* Make sure that interrupts are indeed enabled from here on */
1483 mmiowb(); 1483 mmiowb();
1484 } 1484 }
1485 1485
1486 void bnx2x_int_enable(struct bnx2x *bp) 1486 void bnx2x_int_enable(struct bnx2x *bp)
1487 { 1487 {
1488 if (bp->common.int_block == INT_BLOCK_HC) 1488 if (bp->common.int_block == INT_BLOCK_HC)
1489 bnx2x_hc_int_enable(bp); 1489 bnx2x_hc_int_enable(bp);
1490 else 1490 else
1491 bnx2x_igu_int_enable(bp); 1491 bnx2x_igu_int_enable(bp);
1492 } 1492 }
1493 1493
1494 static void bnx2x_hc_int_disable(struct bnx2x *bp) 1494 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1495 { 1495 {
1496 int port = BP_PORT(bp); 1496 int port = BP_PORT(bp);
1497 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1497 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1498 u32 val = REG_RD(bp, addr); 1498 u32 val = REG_RD(bp, addr);
1499 1499
1500 /* 1500 /*
1501 * in E1 we must use only PCI configuration space to disable 1501 * in E1 we must use only PCI configuration space to disable
1502 * MSI/MSIX capablility 1502 * MSI/MSIX capablility
1503 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1503 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1504 */ 1504 */
1505 if (CHIP_IS_E1(bp)) { 1505 if (CHIP_IS_E1(bp)) {
1506 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1506 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1507 * Use mask register to prevent from HC sending interrupts 1507 * Use mask register to prevent from HC sending interrupts
1508 * after we exit the function 1508 * after we exit the function
1509 */ 1509 */
1510 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1510 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1511 1511
1512 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1512 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1513 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1513 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1514 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1514 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1515 } else 1515 } else
1516 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1516 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1517 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1517 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1518 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1518 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1519 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1519 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1520 1520
1521 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1521 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1522 val, port, addr); 1522 val, port, addr);
1523 1523
1524 /* flush all outstanding writes */ 1524 /* flush all outstanding writes */
1525 mmiowb(); 1525 mmiowb();
1526 1526
1527 REG_WR(bp, addr, val); 1527 REG_WR(bp, addr, val);
1528 if (REG_RD(bp, addr) != val) 1528 if (REG_RD(bp, addr) != val)
1529 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1529 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1530 } 1530 }
1531 1531
1532 static void bnx2x_igu_int_disable(struct bnx2x *bp) 1532 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1533 { 1533 {
1534 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1534 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1535 1535
1536 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1536 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1537 IGU_PF_CONF_INT_LINE_EN | 1537 IGU_PF_CONF_INT_LINE_EN |
1538 IGU_PF_CONF_ATTN_BIT_EN); 1538 IGU_PF_CONF_ATTN_BIT_EN);
1539 1539
1540 DP(NETIF_MSG_INTR, "write %x to IGU\n", val); 1540 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1541 1541
1542 /* flush all outstanding writes */ 1542 /* flush all outstanding writes */
1543 mmiowb(); 1543 mmiowb();
1544 1544
1545 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1545 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1546 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1546 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1547 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1547 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1548 } 1548 }
1549 1549
1550 void bnx2x_int_disable(struct bnx2x *bp) 1550 void bnx2x_int_disable(struct bnx2x *bp)
1551 { 1551 {
1552 if (bp->common.int_block == INT_BLOCK_HC) 1552 if (bp->common.int_block == INT_BLOCK_HC)
1553 bnx2x_hc_int_disable(bp); 1553 bnx2x_hc_int_disable(bp);
1554 else 1554 else
1555 bnx2x_igu_int_disable(bp); 1555 bnx2x_igu_int_disable(bp);
1556 } 1556 }
1557 1557
1558 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1558 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1559 { 1559 {
1560 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1560 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1561 int i, offset; 1561 int i, offset;
1562 1562
1563 if (disable_hw) 1563 if (disable_hw)
1564 /* prevent the HW from sending interrupts */ 1564 /* prevent the HW from sending interrupts */
1565 bnx2x_int_disable(bp); 1565 bnx2x_int_disable(bp);
1566 1566
1567 /* make sure all ISRs are done */ 1567 /* make sure all ISRs are done */
1568 if (msix) { 1568 if (msix) {
1569 synchronize_irq(bp->msix_table[0].vector); 1569 synchronize_irq(bp->msix_table[0].vector);
1570 offset = 1; 1570 offset = 1;
1571 #ifdef BCM_CNIC 1571 #ifdef BCM_CNIC
1572 offset++; 1572 offset++;
1573 #endif 1573 #endif
1574 for_each_eth_queue(bp, i) 1574 for_each_eth_queue(bp, i)
1575 synchronize_irq(bp->msix_table[offset++].vector); 1575 synchronize_irq(bp->msix_table[offset++].vector);
1576 } else 1576 } else
1577 synchronize_irq(bp->pdev->irq); 1577 synchronize_irq(bp->pdev->irq);
1578 1578
1579 /* make sure sp_task is not running */ 1579 /* make sure sp_task is not running */
1580 cancel_delayed_work(&bp->sp_task); 1580 cancel_delayed_work(&bp->sp_task);
1581 cancel_delayed_work(&bp->period_task); 1581 cancel_delayed_work(&bp->period_task);
1582 flush_workqueue(bnx2x_wq); 1582 flush_workqueue(bnx2x_wq);
1583 } 1583 }
1584 1584
1585 /* fast path */ 1585 /* fast path */
1586 1586
1587 /* 1587 /*
1588 * General service functions 1588 * General service functions
1589 */ 1589 */
1590 1590
1591 /* Return true if succeeded to acquire the lock */ 1591 /* Return true if succeeded to acquire the lock */
1592 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1592 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1593 { 1593 {
1594 u32 lock_status; 1594 u32 lock_status;
1595 u32 resource_bit = (1 << resource); 1595 u32 resource_bit = (1 << resource);
1596 int func = BP_FUNC(bp); 1596 int func = BP_FUNC(bp);
1597 u32 hw_lock_control_reg; 1597 u32 hw_lock_control_reg;
1598 1598
1599 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); 1599 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1600 1600
1601 /* Validating that the resource is within range */ 1601 /* Validating that the resource is within range */
1602 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1602 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1603 DP(NETIF_MSG_HW, 1603 DP(NETIF_MSG_HW,
1604 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1604 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1605 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1605 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1606 return false; 1606 return false;
1607 } 1607 }
1608 1608
1609 if (func <= 5) 1609 if (func <= 5)
1610 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1610 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1611 else 1611 else
1612 hw_lock_control_reg = 1612 hw_lock_control_reg =
1613 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1613 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1614 1614
1615 /* Try to acquire the lock */ 1615 /* Try to acquire the lock */
1616 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1616 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1617 lock_status = REG_RD(bp, hw_lock_control_reg); 1617 lock_status = REG_RD(bp, hw_lock_control_reg);
1618 if (lock_status & resource_bit) 1618 if (lock_status & resource_bit)
1619 return true; 1619 return true;
1620 1620
1621 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); 1621 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1622 return false; 1622 return false;
1623 } 1623 }
1624 1624
1625 /** 1625 /**
1626 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1626 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1627 * 1627 *
1628 * @bp: driver handle 1628 * @bp: driver handle
1629 * 1629 *
1630 * Returns the recovery leader resource id according to the engine this function 1630 * Returns the recovery leader resource id according to the engine this function
1631 * belongs to. Currently only only 2 engines is supported. 1631 * belongs to. Currently only only 2 engines is supported.
1632 */ 1632 */
1633 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1633 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1634 { 1634 {
1635 if (BP_PATH(bp)) 1635 if (BP_PATH(bp))
1636 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1636 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1637 else 1637 else
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1639 } 1639 }
1640 1640
1641 /** 1641 /**
1642 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1642 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1643 * 1643 *
1644 * @bp: driver handle 1644 * @bp: driver handle
1645 * 1645 *
1646 * Tries to aquire a leader lock for cuurent engine. 1646 * Tries to aquire a leader lock for cuurent engine.
1647 */ 1647 */
1648 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1648 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1649 { 1649 {
1650 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1650 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1651 } 1651 }
1652 1652
1653 #ifdef BCM_CNIC 1653 #ifdef BCM_CNIC
1654 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1654 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1655 #endif 1655 #endif
1656 1656
1657 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1657 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1658 { 1658 {
1659 struct bnx2x *bp = fp->bp; 1659 struct bnx2x *bp = fp->bp;
1660 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1660 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1661 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1661 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1662 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1662 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1663 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; 1663 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1664 1664
1665 DP(BNX2X_MSG_SP, 1665 DP(BNX2X_MSG_SP,
1666 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1666 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1667 fp->index, cid, command, bp->state, 1667 fp->index, cid, command, bp->state,
1668 rr_cqe->ramrod_cqe.ramrod_type); 1668 rr_cqe->ramrod_cqe.ramrod_type);
1669 1669
1670 switch (command) { 1670 switch (command) {
1671 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1671 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1672 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1672 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1673 drv_cmd = BNX2X_Q_CMD_UPDATE; 1673 drv_cmd = BNX2X_Q_CMD_UPDATE;
1674 break; 1674 break;
1675 1675
1676 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1676 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1677 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1677 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1678 drv_cmd = BNX2X_Q_CMD_SETUP; 1678 drv_cmd = BNX2X_Q_CMD_SETUP;
1679 break; 1679 break;
1680 1680
1681 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1681 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1682 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1682 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1683 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1683 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1684 break; 1684 break;
1685 1685
1686 case (RAMROD_CMD_ID_ETH_HALT): 1686 case (RAMROD_CMD_ID_ETH_HALT):
1687 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1687 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1688 drv_cmd = BNX2X_Q_CMD_HALT; 1688 drv_cmd = BNX2X_Q_CMD_HALT;
1689 break; 1689 break;
1690 1690
1691 case (RAMROD_CMD_ID_ETH_TERMINATE): 1691 case (RAMROD_CMD_ID_ETH_TERMINATE):
1692 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1692 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1693 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1693 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1694 break; 1694 break;
1695 1695
1696 case (RAMROD_CMD_ID_ETH_EMPTY): 1696 case (RAMROD_CMD_ID_ETH_EMPTY):
1697 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1697 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1698 drv_cmd = BNX2X_Q_CMD_EMPTY; 1698 drv_cmd = BNX2X_Q_CMD_EMPTY;
1699 break; 1699 break;
1700 1700
1701 default: 1701 default:
1702 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1702 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1703 command, fp->index); 1703 command, fp->index);
1704 return; 1704 return;
1705 } 1705 }
1706 1706
1707 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1707 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1708 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1708 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1709 /* q_obj->complete_cmd() failure means that this was 1709 /* q_obj->complete_cmd() failure means that this was
1710 * an unexpected completion. 1710 * an unexpected completion.
1711 * 1711 *
1712 * In this case we don't want to increase the bp->spq_left 1712 * In this case we don't want to increase the bp->spq_left
1713 * because apparently we haven't sent this command the first 1713 * because apparently we haven't sent this command the first
1714 * place. 1714 * place.
1715 */ 1715 */
1716 #ifdef BNX2X_STOP_ON_ERROR 1716 #ifdef BNX2X_STOP_ON_ERROR
1717 bnx2x_panic(); 1717 bnx2x_panic();
1718 #else 1718 #else
1719 return; 1719 return;
1720 #endif 1720 #endif
1721 1721
1722 smp_mb__before_atomic_inc(); 1722 smp_mb__before_atomic_inc();
1723 atomic_inc(&bp->cq_spq_left); 1723 atomic_inc(&bp->cq_spq_left);
1724 /* push the change in bp->spq_left and towards the memory */ 1724 /* push the change in bp->spq_left and towards the memory */
1725 smp_mb__after_atomic_inc(); 1725 smp_mb__after_atomic_inc();
1726 1726
1727 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1727 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1728 1728
1729 return; 1729 return;
1730 } 1730 }
1731 1731
1732 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 1732 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1733 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) 1733 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1734 { 1734 {
1735 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; 1735 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1736 1736
1737 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, 1737 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1738 start); 1738 start);
1739 } 1739 }
1740 1740
1741 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1741 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1742 { 1742 {
1743 struct bnx2x *bp = netdev_priv(dev_instance); 1743 struct bnx2x *bp = netdev_priv(dev_instance);
1744 u16 status = bnx2x_ack_int(bp); 1744 u16 status = bnx2x_ack_int(bp);
1745 u16 mask; 1745 u16 mask;
1746 int i; 1746 int i;
1747 u8 cos; 1747 u8 cos;
1748 1748
1749 /* Return here if interrupt is shared and it's not for us */ 1749 /* Return here if interrupt is shared and it's not for us */
1750 if (unlikely(status == 0)) { 1750 if (unlikely(status == 0)) {
1751 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1751 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1752 return IRQ_NONE; 1752 return IRQ_NONE;
1753 } 1753 }
1754 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1754 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1755 1755
1756 #ifdef BNX2X_STOP_ON_ERROR 1756 #ifdef BNX2X_STOP_ON_ERROR
1757 if (unlikely(bp->panic)) 1757 if (unlikely(bp->panic))
1758 return IRQ_HANDLED; 1758 return IRQ_HANDLED;
1759 #endif 1759 #endif
1760 1760
1761 for_each_eth_queue(bp, i) { 1761 for_each_eth_queue(bp, i) {
1762 struct bnx2x_fastpath *fp = &bp->fp[i]; 1762 struct bnx2x_fastpath *fp = &bp->fp[i];
1763 1763
1764 mask = 0x2 << (fp->index + CNIC_PRESENT); 1764 mask = 0x2 << (fp->index + CNIC_PRESENT);
1765 if (status & mask) { 1765 if (status & mask) {
1766 /* Handle Rx or Tx according to SB id */ 1766 /* Handle Rx or Tx according to SB id */
1767 prefetch(fp->rx_cons_sb); 1767 prefetch(fp->rx_cons_sb);
1768 for_each_cos_in_tx_queue(fp, cos) 1768 for_each_cos_in_tx_queue(fp, cos)
1769 prefetch(fp->txdata[cos].tx_cons_sb); 1769 prefetch(fp->txdata[cos].tx_cons_sb);
1770 prefetch(&fp->sb_running_index[SM_RX_ID]); 1770 prefetch(&fp->sb_running_index[SM_RX_ID]);
1771 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1771 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1772 status &= ~mask; 1772 status &= ~mask;
1773 } 1773 }
1774 } 1774 }
1775 1775
1776 #ifdef BCM_CNIC 1776 #ifdef BCM_CNIC
1777 mask = 0x2; 1777 mask = 0x2;
1778 if (status & (mask | 0x1)) { 1778 if (status & (mask | 0x1)) {
1779 struct cnic_ops *c_ops = NULL; 1779 struct cnic_ops *c_ops = NULL;
1780 1780
1781 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1781 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1782 rcu_read_lock(); 1782 rcu_read_lock();
1783 c_ops = rcu_dereference(bp->cnic_ops); 1783 c_ops = rcu_dereference(bp->cnic_ops);
1784 if (c_ops) 1784 if (c_ops)
1785 c_ops->cnic_handler(bp->cnic_data, NULL); 1785 c_ops->cnic_handler(bp->cnic_data, NULL);
1786 rcu_read_unlock(); 1786 rcu_read_unlock();
1787 } 1787 }
1788 1788
1789 status &= ~mask; 1789 status &= ~mask;
1790 } 1790 }
1791 #endif 1791 #endif
1792 1792
1793 if (unlikely(status & 0x1)) { 1793 if (unlikely(status & 0x1)) {
1794 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1794 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1795 1795
1796 status &= ~0x1; 1796 status &= ~0x1;
1797 if (!status) 1797 if (!status)
1798 return IRQ_HANDLED; 1798 return IRQ_HANDLED;
1799 } 1799 }
1800 1800
1801 if (unlikely(status)) 1801 if (unlikely(status))
1802 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1802 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1803 status); 1803 status);
1804 1804
1805 return IRQ_HANDLED; 1805 return IRQ_HANDLED;
1806 } 1806 }
1807 1807
1808 /* Link */ 1808 /* Link */
1809 1809
1810 /* 1810 /*
1811 * General service functions 1811 * General service functions
1812 */ 1812 */
1813 1813
1814 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1814 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1815 { 1815 {
1816 u32 lock_status; 1816 u32 lock_status;
1817 u32 resource_bit = (1 << resource); 1817 u32 resource_bit = (1 << resource);
1818 int func = BP_FUNC(bp); 1818 int func = BP_FUNC(bp);
1819 u32 hw_lock_control_reg; 1819 u32 hw_lock_control_reg;
1820 int cnt; 1820 int cnt;
1821 1821
1822 /* Validating that the resource is within range */ 1822 /* Validating that the resource is within range */
1823 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1823 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1824 DP(NETIF_MSG_HW, 1824 DP(NETIF_MSG_HW,
1825 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1825 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1826 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1826 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1827 return -EINVAL; 1827 return -EINVAL;
1828 } 1828 }
1829 1829
1830 if (func <= 5) { 1830 if (func <= 5) {
1831 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1831 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1832 } else { 1832 } else {
1833 hw_lock_control_reg = 1833 hw_lock_control_reg =
1834 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1834 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1835 } 1835 }
1836 1836
1837 /* Validating that the resource is not already taken */ 1837 /* Validating that the resource is not already taken */
1838 lock_status = REG_RD(bp, hw_lock_control_reg); 1838 lock_status = REG_RD(bp, hw_lock_control_reg);
1839 if (lock_status & resource_bit) { 1839 if (lock_status & resource_bit) {
1840 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1840 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1841 lock_status, resource_bit); 1841 lock_status, resource_bit);
1842 return -EEXIST; 1842 return -EEXIST;
1843 } 1843 }
1844 1844
1845 /* Try for 5 second every 5ms */ 1845 /* Try for 5 second every 5ms */
1846 for (cnt = 0; cnt < 1000; cnt++) { 1846 for (cnt = 0; cnt < 1000; cnt++) {
1847 /* Try to acquire the lock */ 1847 /* Try to acquire the lock */
1848 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1848 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1849 lock_status = REG_RD(bp, hw_lock_control_reg); 1849 lock_status = REG_RD(bp, hw_lock_control_reg);
1850 if (lock_status & resource_bit) 1850 if (lock_status & resource_bit)
1851 return 0; 1851 return 0;
1852 1852
1853 msleep(5); 1853 msleep(5);
1854 } 1854 }
1855 DP(NETIF_MSG_HW, "Timeout\n"); 1855 DP(NETIF_MSG_HW, "Timeout\n");
1856 return -EAGAIN; 1856 return -EAGAIN;
1857 } 1857 }
1858 1858
1859 int bnx2x_release_leader_lock(struct bnx2x *bp) 1859 int bnx2x_release_leader_lock(struct bnx2x *bp)
1860 { 1860 {
1861 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1861 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1862 } 1862 }
1863 1863
1864 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1864 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1865 { 1865 {
1866 u32 lock_status; 1866 u32 lock_status;
1867 u32 resource_bit = (1 << resource); 1867 u32 resource_bit = (1 << resource);
1868 int func = BP_FUNC(bp); 1868 int func = BP_FUNC(bp);
1869 u32 hw_lock_control_reg; 1869 u32 hw_lock_control_reg;
1870 1870
1871 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); 1871 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1872 1872
1873 /* Validating that the resource is within range */ 1873 /* Validating that the resource is within range */
1874 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1874 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1875 DP(NETIF_MSG_HW, 1875 DP(NETIF_MSG_HW,
1876 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1876 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1877 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1877 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1878 return -EINVAL; 1878 return -EINVAL;
1879 } 1879 }
1880 1880
1881 if (func <= 5) { 1881 if (func <= 5) {
1882 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1882 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1883 } else { 1883 } else {
1884 hw_lock_control_reg = 1884 hw_lock_control_reg =
1885 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1885 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1886 } 1886 }
1887 1887
1888 /* Validating that the resource is currently taken */ 1888 /* Validating that the resource is currently taken */
1889 lock_status = REG_RD(bp, hw_lock_control_reg); 1889 lock_status = REG_RD(bp, hw_lock_control_reg);
1890 if (!(lock_status & resource_bit)) { 1890 if (!(lock_status & resource_bit)) {
1891 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1891 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1892 lock_status, resource_bit); 1892 lock_status, resource_bit);
1893 return -EFAULT; 1893 return -EFAULT;
1894 } 1894 }
1895 1895
1896 REG_WR(bp, hw_lock_control_reg, resource_bit); 1896 REG_WR(bp, hw_lock_control_reg, resource_bit);
1897 return 0; 1897 return 0;
1898 } 1898 }
1899 1899
1900 1900
1901 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1901 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1902 { 1902 {
1903 /* The GPIO should be swapped if swap register is set and active */ 1903 /* The GPIO should be swapped if swap register is set and active */
1904 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1904 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1905 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1905 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1906 int gpio_shift = gpio_num + 1906 int gpio_shift = gpio_num +
1907 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1907 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1908 u32 gpio_mask = (1 << gpio_shift); 1908 u32 gpio_mask = (1 << gpio_shift);
1909 u32 gpio_reg; 1909 u32 gpio_reg;
1910 int value; 1910 int value;
1911 1911
1912 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1912 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1913 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1913 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1914 return -EINVAL; 1914 return -EINVAL;
1915 } 1915 }
1916 1916
1917 /* read GPIO value */ 1917 /* read GPIO value */
1918 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1918 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1919 1919
1920 /* get the requested pin value */ 1920 /* get the requested pin value */
1921 if ((gpio_reg & gpio_mask) == gpio_mask) 1921 if ((gpio_reg & gpio_mask) == gpio_mask)
1922 value = 1; 1922 value = 1;
1923 else 1923 else
1924 value = 0; 1924 value = 0;
1925 1925
1926 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1926 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1927 1927
1928 return value; 1928 return value;
1929 } 1929 }
1930 1930
1931 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1931 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1932 { 1932 {
1933 /* The GPIO should be swapped if swap register is set and active */ 1933 /* The GPIO should be swapped if swap register is set and active */
1934 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1934 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1935 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1935 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1936 int gpio_shift = gpio_num + 1936 int gpio_shift = gpio_num +
1937 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1937 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1938 u32 gpio_mask = (1 << gpio_shift); 1938 u32 gpio_mask = (1 << gpio_shift);
1939 u32 gpio_reg; 1939 u32 gpio_reg;
1940 1940
1941 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1941 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1942 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1942 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1943 return -EINVAL; 1943 return -EINVAL;
1944 } 1944 }
1945 1945
1946 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1946 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1947 /* read GPIO and mask except the float bits */ 1947 /* read GPIO and mask except the float bits */
1948 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1948 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1949 1949
1950 switch (mode) { 1950 switch (mode) {
1951 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1951 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1952 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", 1952 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1953 gpio_num, gpio_shift); 1953 gpio_num, gpio_shift);
1954 /* clear FLOAT and set CLR */ 1954 /* clear FLOAT and set CLR */
1955 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1955 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1956 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1956 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1957 break; 1957 break;
1958 1958
1959 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1959 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1960 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", 1960 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1961 gpio_num, gpio_shift); 1961 gpio_num, gpio_shift);
1962 /* clear FLOAT and set SET */ 1962 /* clear FLOAT and set SET */
1963 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1963 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1964 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1964 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1965 break; 1965 break;
1966 1966
1967 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1967 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1968 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1968 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1969 gpio_num, gpio_shift); 1969 gpio_num, gpio_shift);
1970 /* set FLOAT */ 1970 /* set FLOAT */
1971 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1971 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1972 break; 1972 break;
1973 1973
1974 default: 1974 default:
1975 break; 1975 break;
1976 } 1976 }
1977 1977
1978 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1978 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1979 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1979 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1980 1980
1981 return 0; 1981 return 0;
1982 } 1982 }
1983 1983
1984 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 1984 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1985 { 1985 {
1986 u32 gpio_reg = 0; 1986 u32 gpio_reg = 0;
1987 int rc = 0; 1987 int rc = 0;
1988 1988
1989 /* Any port swapping should be handled by caller. */ 1989 /* Any port swapping should be handled by caller. */
1990 1990
1991 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1991 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1992 /* read GPIO and mask except the float bits */ 1992 /* read GPIO and mask except the float bits */
1993 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1993 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1997 1997
1998 switch (mode) { 1998 switch (mode) {
1999 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1999 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2000 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2000 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2001 /* set CLR */ 2001 /* set CLR */
2002 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2002 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2003 break; 2003 break;
2004 2004
2005 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2005 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2006 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2006 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2007 /* set SET */ 2007 /* set SET */
2008 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2008 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2009 break; 2009 break;
2010 2010
2011 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2011 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2012 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2012 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2013 /* set FLOAT */ 2013 /* set FLOAT */
2014 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2014 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2015 break; 2015 break;
2016 2016
2017 default: 2017 default:
2018 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2018 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2019 rc = -EINVAL; 2019 rc = -EINVAL;
2020 break; 2020 break;
2021 } 2021 }
2022 2022
2023 if (rc == 0) 2023 if (rc == 0)
2024 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2024 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2025 2025
2026 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2026 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2027 2027
2028 return rc; 2028 return rc;
2029 } 2029 }
2030 2030
2031 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2031 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2032 { 2032 {
2033 /* The GPIO should be swapped if swap register is set and active */ 2033 /* The GPIO should be swapped if swap register is set and active */
2034 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2034 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2035 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2035 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2036 int gpio_shift = gpio_num + 2036 int gpio_shift = gpio_num +
2037 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2037 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2038 u32 gpio_mask = (1 << gpio_shift); 2038 u32 gpio_mask = (1 << gpio_shift);
2039 u32 gpio_reg; 2039 u32 gpio_reg;
2040 2040
2041 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2041 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2042 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2042 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2043 return -EINVAL; 2043 return -EINVAL;
2044 } 2044 }
2045 2045
2046 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2046 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2047 /* read GPIO int */ 2047 /* read GPIO int */
2048 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2048 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2049 2049
2050 switch (mode) { 2050 switch (mode) {
2051 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2051 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2052 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " 2052 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2053 "output low\n", gpio_num, gpio_shift); 2053 "output low\n", gpio_num, gpio_shift);
2054 /* clear SET and set CLR */ 2054 /* clear SET and set CLR */
2055 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2055 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2056 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2056 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2057 break; 2057 break;
2058 2058
2059 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2059 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2060 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " 2060 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2061 "output high\n", gpio_num, gpio_shift); 2061 "output high\n", gpio_num, gpio_shift);
2062 /* clear CLR and set SET */ 2062 /* clear CLR and set SET */
2063 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2063 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2064 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2064 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2065 break; 2065 break;
2066 2066
2067 default: 2067 default:
2068 break; 2068 break;
2069 } 2069 }
2070 2070
2071 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2071 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2072 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2072 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2073 2073
2074 return 0; 2074 return 0;
2075 } 2075 }
2076 2076
2077 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2077 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2078 { 2078 {
2079 u32 spio_mask = (1 << spio_num); 2079 u32 spio_mask = (1 << spio_num);
2080 u32 spio_reg; 2080 u32 spio_reg;
2081 2081
2082 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2082 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2083 (spio_num > MISC_REGISTERS_SPIO_7)) { 2083 (spio_num > MISC_REGISTERS_SPIO_7)) {
2084 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2084 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2085 return -EINVAL; 2085 return -EINVAL;
2086 } 2086 }
2087 2087
2088 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2088 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2089 /* read SPIO and mask except the float bits */ 2089 /* read SPIO and mask except the float bits */
2090 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2090 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2091 2091
2092 switch (mode) { 2092 switch (mode) {
2093 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2093 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2094 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 2094 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2095 /* clear FLOAT and set CLR */ 2095 /* clear FLOAT and set CLR */
2096 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2096 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2097 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2097 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2098 break; 2098 break;
2099 2099
2100 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2100 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2101 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 2101 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2102 /* clear FLOAT and set SET */ 2102 /* clear FLOAT and set SET */
2103 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2103 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2104 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2104 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2105 break; 2105 break;
2106 2106
2107 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2107 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2108 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); 2108 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2109 /* set FLOAT */ 2109 /* set FLOAT */
2110 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2110 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2111 break; 2111 break;
2112 2112
2113 default: 2113 default:
2114 break; 2114 break;
2115 } 2115 }
2116 2116
2117 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2117 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2118 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2118 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2119 2119
2120 return 0; 2120 return 0;
2121 } 2121 }
2122 2122
2123 void bnx2x_calc_fc_adv(struct bnx2x *bp) 2123 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2124 { 2124 {
2125 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2125 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2126 switch (bp->link_vars.ieee_fc & 2126 switch (bp->link_vars.ieee_fc &
2127 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2127 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2128 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2128 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2129 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2129 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2130 ADVERTISED_Pause); 2130 ADVERTISED_Pause);
2131 break; 2131 break;
2132 2132
2133 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2133 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2134 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2134 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2135 ADVERTISED_Pause); 2135 ADVERTISED_Pause);
2136 break; 2136 break;
2137 2137
2138 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2138 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2139 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2139 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2140 break; 2140 break;
2141 2141
2142 default: 2142 default:
2143 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2143 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2144 ADVERTISED_Pause); 2144 ADVERTISED_Pause);
2145 break; 2145 break;
2146 } 2146 }
2147 } 2147 }
2148 2148
2149 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2149 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2150 { 2150 {
2151 if (!BP_NOMCP(bp)) { 2151 if (!BP_NOMCP(bp)) {
2152 u8 rc; 2152 u8 rc;
2153 int cfx_idx = bnx2x_get_link_cfg_idx(bp); 2153 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2154 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2154 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2155 /* 2155 /*
2156 * Initialize link parameters structure variables 2156 * Initialize link parameters structure variables
2157 * It is recommended to turn off RX FC for jumbo frames 2157 * It is recommended to turn off RX FC for jumbo frames
2158 * for better performance 2158 * for better performance
2159 */ 2159 */
2160 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2160 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2161 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2161 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2162 else 2162 else
2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2164 2164
2165 bnx2x_acquire_phy_lock(bp); 2165 bnx2x_acquire_phy_lock(bp);
2166 2166
2167 if (load_mode == LOAD_DIAG) { 2167 if (load_mode == LOAD_DIAG) {
2168 struct link_params *lp = &bp->link_params; 2168 struct link_params *lp = &bp->link_params;
2169 lp->loopback_mode = LOOPBACK_XGXS; 2169 lp->loopback_mode = LOOPBACK_XGXS;
2170 /* do PHY loopback at 10G speed, if possible */ 2170 /* do PHY loopback at 10G speed, if possible */
2171 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2171 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2172 if (lp->speed_cap_mask[cfx_idx] & 2172 if (lp->speed_cap_mask[cfx_idx] &
2173 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2173 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2174 lp->req_line_speed[cfx_idx] = 2174 lp->req_line_speed[cfx_idx] =
2175 SPEED_10000; 2175 SPEED_10000;
2176 else 2176 else
2177 lp->req_line_speed[cfx_idx] = 2177 lp->req_line_speed[cfx_idx] =
2178 SPEED_1000; 2178 SPEED_1000;
2179 } 2179 }
2180 } 2180 }
2181 2181
2182 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2182 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2183 2183
2184 bnx2x_release_phy_lock(bp); 2184 bnx2x_release_phy_lock(bp);
2185 2185
2186 bnx2x_calc_fc_adv(bp); 2186 bnx2x_calc_fc_adv(bp);
2187 2187
2188 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { 2188 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2189 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2189 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2190 bnx2x_link_report(bp); 2190 bnx2x_link_report(bp);
2191 } else 2191 } else
2192 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2192 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2193 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2193 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2194 return rc; 2194 return rc;
2195 } 2195 }
2196 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2196 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2197 return -EINVAL; 2197 return -EINVAL;
2198 } 2198 }
2199 2199
2200 void bnx2x_link_set(struct bnx2x *bp) 2200 void bnx2x_link_set(struct bnx2x *bp)
2201 { 2201 {
2202 if (!BP_NOMCP(bp)) { 2202 if (!BP_NOMCP(bp)) {
2203 bnx2x_acquire_phy_lock(bp); 2203 bnx2x_acquire_phy_lock(bp);
2204 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2204 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2205 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2205 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2206 bnx2x_release_phy_lock(bp); 2206 bnx2x_release_phy_lock(bp);
2207 2207
2208 bnx2x_calc_fc_adv(bp); 2208 bnx2x_calc_fc_adv(bp);
2209 } else 2209 } else
2210 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2210 BNX2X_ERR("Bootcode is missing - can not set link\n");
2211 } 2211 }
2212 2212
2213 static void bnx2x__link_reset(struct bnx2x *bp) 2213 static void bnx2x__link_reset(struct bnx2x *bp)
2214 { 2214 {
2215 if (!BP_NOMCP(bp)) { 2215 if (!BP_NOMCP(bp)) {
2216 bnx2x_acquire_phy_lock(bp); 2216 bnx2x_acquire_phy_lock(bp);
2217 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2217 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2218 bnx2x_release_phy_lock(bp); 2218 bnx2x_release_phy_lock(bp);
2219 } else 2219 } else
2220 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2220 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2221 } 2221 }
2222 2222
2223 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2223 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2224 { 2224 {
2225 u8 rc = 0; 2225 u8 rc = 0;
2226 2226
2227 if (!BP_NOMCP(bp)) { 2227 if (!BP_NOMCP(bp)) {
2228 bnx2x_acquire_phy_lock(bp); 2228 bnx2x_acquire_phy_lock(bp);
2229 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2229 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2230 is_serdes); 2230 is_serdes);
2231 bnx2x_release_phy_lock(bp); 2231 bnx2x_release_phy_lock(bp);
2232 } else 2232 } else
2233 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2233 BNX2X_ERR("Bootcode is missing - can not test link\n");
2234 2234
2235 return rc; 2235 return rc;
2236 } 2236 }
2237 2237
2238 static void bnx2x_init_port_minmax(struct bnx2x *bp) 2238 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2239 { 2239 {
2240 u32 r_param = bp->link_vars.line_speed / 8; 2240 u32 r_param = bp->link_vars.line_speed / 8;
2241 u32 fair_periodic_timeout_usec; 2241 u32 fair_periodic_timeout_usec;
2242 u32 t_fair; 2242 u32 t_fair;
2243 2243
2244 memset(&(bp->cmng.rs_vars), 0, 2244 memset(&(bp->cmng.rs_vars), 0,
2245 sizeof(struct rate_shaping_vars_per_port)); 2245 sizeof(struct rate_shaping_vars_per_port));
2246 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); 2246 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2247 2247
2248 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ 2248 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2249 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; 2249 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2250 2250
2251 /* this is the threshold below which no timer arming will occur 2251 /* this is the threshold below which no timer arming will occur
2252 1.25 coefficient is for the threshold to be a little bigger 2252 1.25 coefficient is for the threshold to be a little bigger
2253 than the real time, to compensate for timer in-accuracy */ 2253 than the real time, to compensate for timer in-accuracy */
2254 bp->cmng.rs_vars.rs_threshold = 2254 bp->cmng.rs_vars.rs_threshold =
2255 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; 2255 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2256 2256
2257 /* resolution of fairness timer */ 2257 /* resolution of fairness timer */
2258 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 2258 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2259 /* for 10G it is 1000usec. for 1G it is 10000usec. */ 2259 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2260 t_fair = T_FAIR_COEF / bp->link_vars.line_speed; 2260 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2261 2261
2262 /* this is the threshold below which we won't arm the timer anymore */ 2262 /* this is the threshold below which we won't arm the timer anymore */
2263 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; 2263 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2264 2264
2265 /* we multiply by 1e3/8 to get bytes/msec. 2265 /* we multiply by 1e3/8 to get bytes/msec.
2266 We don't want the credits to pass a credit 2266 We don't want the credits to pass a credit
2267 of the t_fair*FAIR_MEM (algorithm resolution) */ 2267 of the t_fair*FAIR_MEM (algorithm resolution) */
2268 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; 2268 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2269 /* since each tick is 4 usec */ 2269 /* since each tick is 4 usec */
2270 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; 2270 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2271 } 2271 }
2272 2272
2273 /* Calculates the sum of vn_min_rates. 2273 /* Calculates the sum of vn_min_rates.
2274 It's needed for further normalizing of the min_rates. 2274 It's needed for further normalizing of the min_rates.
2275 Returns: 2275 Returns:
2276 sum of vn_min_rates. 2276 sum of vn_min_rates.
2277 or 2277 or
2278 0 - if all the min_rates are 0. 2278 0 - if all the min_rates are 0.
2279 In the later case fainess algorithm should be deactivated. 2279 In the later case fainess algorithm should be deactivated.
2280 If not all min_rates are zero then those that are zeroes will be set to 1. 2280 If not all min_rates are zero then those that are zeroes will be set to 1.
2281 */ 2281 */
2282 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 2282 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2283 { 2283 {
2284 int all_zero = 1; 2284 int all_zero = 1;
2285 int vn; 2285 int vn;
2286 2286
2287 bp->vn_weight_sum = 0; 2287 bp->vn_weight_sum = 0;
2288 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2288 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2289 u32 vn_cfg = bp->mf_config[vn]; 2289 u32 vn_cfg = bp->mf_config[vn];
2290 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2290 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2291 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2291 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2292 2292
2293 /* Skip hidden vns */ 2293 /* Skip hidden vns */
2294 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2294 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2295 continue; 2295 continue;
2296 2296
2297 /* If min rate is zero - set it to 1 */ 2297 /* If min rate is zero - set it to 1 */
2298 if (!vn_min_rate) 2298 if (!vn_min_rate)
2299 vn_min_rate = DEF_MIN_RATE; 2299 vn_min_rate = DEF_MIN_RATE;
2300 else 2300 else
2301 all_zero = 0; 2301 all_zero = 0;
2302 2302
2303 bp->vn_weight_sum += vn_min_rate; 2303 bp->vn_weight_sum += vn_min_rate;
2304 } 2304 }
2305 2305
2306 /* if ETS or all min rates are zeros - disable fairness */ 2306 /* if ETS or all min rates are zeros - disable fairness */
2307 if (BNX2X_IS_ETS_ENABLED(bp)) { 2307 if (BNX2X_IS_ETS_ENABLED(bp)) {
2308 bp->cmng.flags.cmng_enables &= 2308 bp->cmng.flags.cmng_enables &=
2309 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2309 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2310 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2310 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2311 } else if (all_zero) { 2311 } else if (all_zero) {
2312 bp->cmng.flags.cmng_enables &= 2312 bp->cmng.flags.cmng_enables &=
2313 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2313 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2314 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2314 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2315 " fairness will be disabled\n"); 2315 " fairness will be disabled\n");
2316 } else 2316 } else
2317 bp->cmng.flags.cmng_enables |= 2317 bp->cmng.flags.cmng_enables |=
2318 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2318 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2319 } 2319 }
2320 2320
2321 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2321 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2322 { 2322 {
2323 struct rate_shaping_vars_per_vn m_rs_vn; 2323 struct rate_shaping_vars_per_vn m_rs_vn;
2324 struct fairness_vars_per_vn m_fair_vn; 2324 struct fairness_vars_per_vn m_fair_vn;
2325 u32 vn_cfg = bp->mf_config[vn]; 2325 u32 vn_cfg = bp->mf_config[vn];
2326 int func = func_by_vn(bp, vn); 2326 int func = func_by_vn(bp, vn);
2327 u16 vn_min_rate, vn_max_rate; 2327 u16 vn_min_rate, vn_max_rate;
2328 int i; 2328 int i;
2329 2329
2330 /* If function is hidden - set min and max to zeroes */ 2330 /* If function is hidden - set min and max to zeroes */
2331 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 2331 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2332 vn_min_rate = 0; 2332 vn_min_rate = 0;
2333 vn_max_rate = 0; 2333 vn_max_rate = 0;
2334 2334
2335 } else { 2335 } else {
2336 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2336 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2337 2337
2338 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2338 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2339 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2339 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2340 /* If fairness is enabled (not all min rates are zeroes) and 2340 /* If fairness is enabled (not all min rates are zeroes) and
2341 if current min rate is zero - set it to 1. 2341 if current min rate is zero - set it to 1.
2342 This is a requirement of the algorithm. */ 2342 This is a requirement of the algorithm. */
2343 if (bp->vn_weight_sum && (vn_min_rate == 0)) 2343 if (bp->vn_weight_sum && (vn_min_rate == 0))
2344 vn_min_rate = DEF_MIN_RATE; 2344 vn_min_rate = DEF_MIN_RATE;
2345 2345
2346 if (IS_MF_SI(bp)) 2346 if (IS_MF_SI(bp))
2347 /* maxCfg in percents of linkspeed */ 2347 /* maxCfg in percents of linkspeed */
2348 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2348 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2349 else 2349 else
2350 /* maxCfg is absolute in 100Mb units */ 2350 /* maxCfg is absolute in 100Mb units */
2351 vn_max_rate = maxCfg * 100; 2351 vn_max_rate = maxCfg * 100;
2352 } 2352 }
2353 2353
2354 DP(NETIF_MSG_IFUP, 2354 DP(NETIF_MSG_IFUP,
2355 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 2355 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2356 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 2356 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2357 2357
2358 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); 2358 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2359 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); 2359 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2360 2360
2361 /* global vn counter - maximal Mbps for this vn */ 2361 /* global vn counter - maximal Mbps for this vn */
2362 m_rs_vn.vn_counter.rate = vn_max_rate; 2362 m_rs_vn.vn_counter.rate = vn_max_rate;
2363 2363
2364 /* quota - number of bytes transmitted in this period */ 2364 /* quota - number of bytes transmitted in this period */
2365 m_rs_vn.vn_counter.quota = 2365 m_rs_vn.vn_counter.quota =
2366 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; 2366 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2367 2367
2368 if (bp->vn_weight_sum) { 2368 if (bp->vn_weight_sum) {
2369 /* credit for each period of the fairness algorithm: 2369 /* credit for each period of the fairness algorithm:
2370 number of bytes in T_FAIR (the vn share the port rate). 2370 number of bytes in T_FAIR (the vn share the port rate).
2371 vn_weight_sum should not be larger than 10000, thus 2371 vn_weight_sum should not be larger than 10000, thus
2372 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater 2372 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2373 than zero */ 2373 than zero */
2374 m_fair_vn.vn_credit_delta = 2374 m_fair_vn.vn_credit_delta =
2375 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2375 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2376 (8 * bp->vn_weight_sum))), 2376 (8 * bp->vn_weight_sum))),
2377 (bp->cmng.fair_vars.fair_threshold + 2377 (bp->cmng.fair_vars.fair_threshold +
2378 MIN_ABOVE_THRESH)); 2378 MIN_ABOVE_THRESH));
2379 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2379 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2380 m_fair_vn.vn_credit_delta); 2380 m_fair_vn.vn_credit_delta);
2381 } 2381 }
2382 2382
2383 /* Store it to internal memory */ 2383 /* Store it to internal memory */
2384 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) 2384 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2385 REG_WR(bp, BAR_XSTRORM_INTMEM + 2385 REG_WR(bp, BAR_XSTRORM_INTMEM +
2386 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, 2386 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2387 ((u32 *)(&m_rs_vn))[i]); 2387 ((u32 *)(&m_rs_vn))[i]);
2388 2388
2389 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) 2389 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2390 REG_WR(bp, BAR_XSTRORM_INTMEM + 2390 REG_WR(bp, BAR_XSTRORM_INTMEM +
2391 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, 2391 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2392 ((u32 *)(&m_fair_vn))[i]); 2392 ((u32 *)(&m_fair_vn))[i]);
2393 } 2393 }
2394 2394
2395 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2395 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2396 { 2396 {
2397 if (CHIP_REV_IS_SLOW(bp)) 2397 if (CHIP_REV_IS_SLOW(bp))
2398 return CMNG_FNS_NONE; 2398 return CMNG_FNS_NONE;
2399 if (IS_MF(bp)) 2399 if (IS_MF(bp))
2400 return CMNG_FNS_MINMAX; 2400 return CMNG_FNS_MINMAX;
2401 2401
2402 return CMNG_FNS_NONE; 2402 return CMNG_FNS_NONE;
2403 } 2403 }
2404 2404
2405 void bnx2x_read_mf_cfg(struct bnx2x *bp) 2405 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2406 { 2406 {
2407 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2407 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2408 2408
2409 if (BP_NOMCP(bp)) 2409 if (BP_NOMCP(bp))
2410 return; /* what should be the default bvalue in this case */ 2410 return; /* what should be the default bvalue in this case */
2411 2411
2412 /* For 2 port configuration the absolute function number formula 2412 /* For 2 port configuration the absolute function number formula
2413 * is: 2413 * is:
2414 * abs_func = 2 * vn + BP_PORT + BP_PATH 2414 * abs_func = 2 * vn + BP_PORT + BP_PATH
2415 * 2415 *
2416 * and there are 4 functions per port 2416 * and there are 4 functions per port
2417 * 2417 *
2418 * For 4 port configuration it is 2418 * For 4 port configuration it is
2419 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2419 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2420 * 2420 *
2421 * and there are 2 functions per port 2421 * and there are 2 functions per port
2422 */ 2422 */
2423 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2423 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2424 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2424 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2425 2425
2426 if (func >= E1H_FUNC_MAX) 2426 if (func >= E1H_FUNC_MAX)
2427 break; 2427 break;
2428 2428
2429 bp->mf_config[vn] = 2429 bp->mf_config[vn] =
2430 MF_CFG_RD(bp, func_mf_config[func].config); 2430 MF_CFG_RD(bp, func_mf_config[func].config);
2431 } 2431 }
2432 } 2432 }
2433 2433
2434 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2434 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2435 { 2435 {
2436 2436
2437 if (cmng_type == CMNG_FNS_MINMAX) { 2437 if (cmng_type == CMNG_FNS_MINMAX) {
2438 int vn; 2438 int vn;
2439 2439
2440 /* clear cmng_enables */ 2440 /* clear cmng_enables */
2441 bp->cmng.flags.cmng_enables = 0; 2441 bp->cmng.flags.cmng_enables = 0;
2442 2442
2443 /* read mf conf from shmem */ 2443 /* read mf conf from shmem */
2444 if (read_cfg) 2444 if (read_cfg)
2445 bnx2x_read_mf_cfg(bp); 2445 bnx2x_read_mf_cfg(bp);
2446 2446
2447 /* Init rate shaping and fairness contexts */ 2447 /* Init rate shaping and fairness contexts */
2448 bnx2x_init_port_minmax(bp); 2448 bnx2x_init_port_minmax(bp);
2449 2449
2450 /* vn_weight_sum and enable fairness if not 0 */ 2450 /* vn_weight_sum and enable fairness if not 0 */
2451 bnx2x_calc_vn_weight_sum(bp); 2451 bnx2x_calc_vn_weight_sum(bp);
2452 2452
2453 /* calculate and set min-max rate for each vn */ 2453 /* calculate and set min-max rate for each vn */
2454 if (bp->port.pmf) 2454 if (bp->port.pmf)
2455 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2455 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2456 bnx2x_init_vn_minmax(bp, vn); 2456 bnx2x_init_vn_minmax(bp, vn);
2457 2457
2458 /* always enable rate shaping and fairness */ 2458 /* always enable rate shaping and fairness */
2459 bp->cmng.flags.cmng_enables |= 2459 bp->cmng.flags.cmng_enables |=
2460 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2460 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2461 if (!bp->vn_weight_sum) 2461 if (!bp->vn_weight_sum)
2462 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2462 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2463 " fairness will be disabled\n"); 2463 " fairness will be disabled\n");
2464 return; 2464 return;
2465 } 2465 }
2466 2466
2467 /* rate shaping and fairness are disabled */ 2467 /* rate shaping and fairness are disabled */
2468 DP(NETIF_MSG_IFUP, 2468 DP(NETIF_MSG_IFUP,
2469 "rate shaping and fairness are disabled\n"); 2469 "rate shaping and fairness are disabled\n");
2470 } 2470 }
2471 2471
2472 /* This function is called upon link interrupt */ 2472 /* This function is called upon link interrupt */
2473 static void bnx2x_link_attn(struct bnx2x *bp) 2473 static void bnx2x_link_attn(struct bnx2x *bp)
2474 { 2474 {
2475 /* Make sure that we are synced with the current statistics */ 2475 /* Make sure that we are synced with the current statistics */
2476 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2476 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2477 2477
2478 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2478 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2479 2479
2480 if (bp->link_vars.link_up) { 2480 if (bp->link_vars.link_up) {
2481 2481
2482 /* dropless flow control */ 2482 /* dropless flow control */
2483 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2483 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2484 int port = BP_PORT(bp); 2484 int port = BP_PORT(bp);
2485 u32 pause_enabled = 0; 2485 u32 pause_enabled = 0;
2486 2486
2487 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2487 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2488 pause_enabled = 1; 2488 pause_enabled = 1;
2489 2489
2490 REG_WR(bp, BAR_USTRORM_INTMEM + 2490 REG_WR(bp, BAR_USTRORM_INTMEM +
2491 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2491 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2492 pause_enabled); 2492 pause_enabled);
2493 } 2493 }
2494 2494
2495 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2495 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2496 struct host_port_stats *pstats; 2496 struct host_port_stats *pstats;
2497 2497
2498 pstats = bnx2x_sp(bp, port_stats); 2498 pstats = bnx2x_sp(bp, port_stats);
2499 /* reset old mac stats */ 2499 /* reset old mac stats */
2500 memset(&(pstats->mac_stx[0]), 0, 2500 memset(&(pstats->mac_stx[0]), 0,
2501 sizeof(struct mac_stx)); 2501 sizeof(struct mac_stx));
2502 } 2502 }
2503 if (bp->state == BNX2X_STATE_OPEN) 2503 if (bp->state == BNX2X_STATE_OPEN)
2504 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2504 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2505 } 2505 }
2506 2506
2507 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2507 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2508 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2508 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2509 2509
2510 if (cmng_fns != CMNG_FNS_NONE) { 2510 if (cmng_fns != CMNG_FNS_NONE) {
2511 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2511 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2512 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2512 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2513 } else 2513 } else
2514 /* rate shaping and fairness are disabled */ 2514 /* rate shaping and fairness are disabled */
2515 DP(NETIF_MSG_IFUP, 2515 DP(NETIF_MSG_IFUP,
2516 "single function mode without fairness\n"); 2516 "single function mode without fairness\n");
2517 } 2517 }
2518 2518
2519 __bnx2x_link_report(bp); 2519 __bnx2x_link_report(bp);
2520 2520
2521 if (IS_MF(bp)) 2521 if (IS_MF(bp))
2522 bnx2x_link_sync_notify(bp); 2522 bnx2x_link_sync_notify(bp);
2523 } 2523 }
2524 2524
2525 void bnx2x__link_status_update(struct bnx2x *bp) 2525 void bnx2x__link_status_update(struct bnx2x *bp)
2526 { 2526 {
2527 if (bp->state != BNX2X_STATE_OPEN) 2527 if (bp->state != BNX2X_STATE_OPEN)
2528 return; 2528 return;
2529 2529
2530 /* read updated dcb configuration */ 2530 /* read updated dcb configuration */
2531 bnx2x_dcbx_pmf_update(bp); 2531 bnx2x_dcbx_pmf_update(bp);
2532 2532
2533 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2533 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2534 2534
2535 if (bp->link_vars.link_up) 2535 if (bp->link_vars.link_up)
2536 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2536 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2537 else 2537 else
2538 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2538 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2539 2539
2540 /* indicate link status */ 2540 /* indicate link status */
2541 bnx2x_link_report(bp); 2541 bnx2x_link_report(bp);
2542 } 2542 }
2543 2543
2544 static void bnx2x_pmf_update(struct bnx2x *bp) 2544 static void bnx2x_pmf_update(struct bnx2x *bp)
2545 { 2545 {
2546 int port = BP_PORT(bp); 2546 int port = BP_PORT(bp);
2547 u32 val; 2547 u32 val;
2548 2548
2549 bp->port.pmf = 1; 2549 bp->port.pmf = 1;
2550 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); 2550 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2551 2551
2552 /* 2552 /*
2553 * We need the mb() to ensure the ordering between the writing to 2553 * We need the mb() to ensure the ordering between the writing to
2554 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2554 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2555 */ 2555 */
2556 smp_mb(); 2556 smp_mb();
2557 2557
2558 /* queue a periodic task */ 2558 /* queue a periodic task */
2559 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2559 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2560 2560
2561 bnx2x_dcbx_pmf_update(bp); 2561 bnx2x_dcbx_pmf_update(bp);
2562 2562
2563 /* enable nig attention */ 2563 /* enable nig attention */
2564 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2564 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2565 if (bp->common.int_block == INT_BLOCK_HC) { 2565 if (bp->common.int_block == INT_BLOCK_HC) {
2566 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2566 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2567 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2567 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2568 } else if (!CHIP_IS_E1x(bp)) { 2568 } else if (!CHIP_IS_E1x(bp)) {
2569 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2569 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2570 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2570 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2571 } 2571 }
2572 2572
2573 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2573 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2574 } 2574 }
2575 2575
2576 /* end of Link */ 2576 /* end of Link */
2577 2577
2578 /* slow path */ 2578 /* slow path */
2579 2579
2580 /* 2580 /*
2581 * General service functions 2581 * General service functions
2582 */ 2582 */
2583 2583
2584 /* send the MCP a request, block until there is a reply */ 2584 /* send the MCP a request, block until there is a reply */
2585 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2585 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2586 { 2586 {
2587 int mb_idx = BP_FW_MB_IDX(bp); 2587 int mb_idx = BP_FW_MB_IDX(bp);
2588 u32 seq; 2588 u32 seq;
2589 u32 rc = 0; 2589 u32 rc = 0;
2590 u32 cnt = 1; 2590 u32 cnt = 1;
2591 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2591 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2592 2592
2593 mutex_lock(&bp->fw_mb_mutex); 2593 mutex_lock(&bp->fw_mb_mutex);
2594 seq = ++bp->fw_seq; 2594 seq = ++bp->fw_seq;
2595 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2595 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2596 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2596 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2597 2597
2598 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2598 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2599 (command | seq), param); 2599 (command | seq), param);
2600 2600
2601 do { 2601 do {
2602 /* let the FW do it's magic ... */ 2602 /* let the FW do it's magic ... */
2603 msleep(delay); 2603 msleep(delay);
2604 2604
2605 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2605 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2606 2606
2607 /* Give the FW up to 5 second (500*10ms) */ 2607 /* Give the FW up to 5 second (500*10ms) */
2608 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2608 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2609 2609
2610 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2610 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2611 cnt*delay, rc, seq); 2611 cnt*delay, rc, seq);
2612 2612
2613 /* is this a reply to our command? */ 2613 /* is this a reply to our command? */
2614 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2614 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2615 rc &= FW_MSG_CODE_MASK; 2615 rc &= FW_MSG_CODE_MASK;
2616 else { 2616 else {
2617 /* FW BUG! */ 2617 /* FW BUG! */
2618 BNX2X_ERR("FW failed to respond!\n"); 2618 BNX2X_ERR("FW failed to respond!\n");
2619 bnx2x_fw_dump(bp); 2619 bnx2x_fw_dump(bp);
2620 rc = 0; 2620 rc = 0;
2621 } 2621 }
2622 mutex_unlock(&bp->fw_mb_mutex); 2622 mutex_unlock(&bp->fw_mb_mutex);
2623 2623
2624 return rc; 2624 return rc;
2625 } 2625 }
2626 2626
2627 2627
2628 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2628 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2629 { 2629 {
2630 if (CHIP_IS_E1x(bp)) { 2630 if (CHIP_IS_E1x(bp)) {
2631 struct tstorm_eth_function_common_config tcfg = {0}; 2631 struct tstorm_eth_function_common_config tcfg = {0};
2632 2632
2633 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2633 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2634 } 2634 }
2635 2635
2636 /* Enable the function in the FW */ 2636 /* Enable the function in the FW */
2637 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2637 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2638 storm_memset_func_en(bp, p->func_id, 1); 2638 storm_memset_func_en(bp, p->func_id, 1);
2639 2639
2640 /* spq */ 2640 /* spq */
2641 if (p->func_flgs & FUNC_FLG_SPQ) { 2641 if (p->func_flgs & FUNC_FLG_SPQ) {
2642 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2642 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2643 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2643 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2644 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2644 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2645 } 2645 }
2646 } 2646 }
2647 2647
2648 /** 2648 /**
2649 * bnx2x_get_tx_only_flags - Return common flags 2649 * bnx2x_get_tx_only_flags - Return common flags
2650 * 2650 *
2651 * @bp device handle 2651 * @bp device handle
2652 * @fp queue handle 2652 * @fp queue handle
2653 * @zero_stats TRUE if statistics zeroing is needed 2653 * @zero_stats TRUE if statistics zeroing is needed
2654 * 2654 *
2655 * Return the flags that are common for the Tx-only and not normal connections. 2655 * Return the flags that are common for the Tx-only and not normal connections.
2656 */ 2656 */
2657 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2657 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2658 struct bnx2x_fastpath *fp, 2658 struct bnx2x_fastpath *fp,
2659 bool zero_stats) 2659 bool zero_stats)
2660 { 2660 {
2661 unsigned long flags = 0; 2661 unsigned long flags = 0;
2662 2662
2663 /* PF driver will always initialize the Queue to an ACTIVE state */ 2663 /* PF driver will always initialize the Queue to an ACTIVE state */
2664 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2664 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2665 2665
2666 /* tx only connections collect statistics (on the same index as the 2666 /* tx only connections collect statistics (on the same index as the
2667 * parent connection). The statistics are zeroed when the parent 2667 * parent connection). The statistics are zeroed when the parent
2668 * connection is initialized. 2668 * connection is initialized.
2669 */ 2669 */
2670 2670
2671 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2671 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2672 if (zero_stats) 2672 if (zero_stats)
2673 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2673 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2674 2674
2675 2675
2676 return flags; 2676 return flags;
2677 } 2677 }
2678 2678
2679 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2679 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2680 struct bnx2x_fastpath *fp, 2680 struct bnx2x_fastpath *fp,
2681 bool leading) 2681 bool leading)
2682 { 2682 {
2683 unsigned long flags = 0; 2683 unsigned long flags = 0;
2684 2684
2685 /* calculate other queue flags */ 2685 /* calculate other queue flags */
2686 if (IS_MF_SD(bp)) 2686 if (IS_MF_SD(bp))
2687 __set_bit(BNX2X_Q_FLG_OV, &flags); 2687 __set_bit(BNX2X_Q_FLG_OV, &flags);
2688 2688
2689 if (IS_FCOE_FP(fp)) 2689 if (IS_FCOE_FP(fp))
2690 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2690 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2691 2691
2692 if (!fp->disable_tpa) { 2692 if (!fp->disable_tpa) {
2693 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2693 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2694 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2694 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2695 } 2695 }
2696 2696
2697 if (leading) { 2697 if (leading) {
2698 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2698 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2699 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2699 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2700 } 2700 }
2701 2701
2702 /* Always set HW VLAN stripping */ 2702 /* Always set HW VLAN stripping */
2703 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2703 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2704 2704
2705 2705
2706 return flags | bnx2x_get_common_flags(bp, fp, true); 2706 return flags | bnx2x_get_common_flags(bp, fp, true);
2707 } 2707 }
2708 2708
2709 static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2709 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2710 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2710 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2711 u8 cos) 2711 u8 cos)
2712 { 2712 {
2713 gen_init->stat_id = bnx2x_stats_id(fp); 2713 gen_init->stat_id = bnx2x_stats_id(fp);
2714 gen_init->spcl_id = fp->cl_id; 2714 gen_init->spcl_id = fp->cl_id;
2715 2715
2716 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2716 /* Always use mini-jumbo MTU for FCoE L2 ring */
2717 if (IS_FCOE_FP(fp)) 2717 if (IS_FCOE_FP(fp))
2718 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2718 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2719 else 2719 else
2720 gen_init->mtu = bp->dev->mtu; 2720 gen_init->mtu = bp->dev->mtu;
2721 2721
2722 gen_init->cos = cos; 2722 gen_init->cos = cos;
2723 } 2723 }
2724 2724
2725 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2725 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2726 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2726 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2727 struct bnx2x_rxq_setup_params *rxq_init) 2727 struct bnx2x_rxq_setup_params *rxq_init)
2728 { 2728 {
2729 u8 max_sge = 0; 2729 u8 max_sge = 0;
2730 u16 sge_sz = 0; 2730 u16 sge_sz = 0;
2731 u16 tpa_agg_size = 0; 2731 u16 tpa_agg_size = 0;
2732 2732
2733 if (!fp->disable_tpa) { 2733 if (!fp->disable_tpa) {
2734 pause->sge_th_lo = SGE_TH_LO(bp); 2734 pause->sge_th_lo = SGE_TH_LO(bp);
2735 pause->sge_th_hi = SGE_TH_HI(bp); 2735 pause->sge_th_hi = SGE_TH_HI(bp);
2736 2736
2737 /* validate SGE ring has enough to cross high threshold */ 2737 /* validate SGE ring has enough to cross high threshold */
2738 WARN_ON(bp->dropless_fc && 2738 WARN_ON(bp->dropless_fc &&
2739 pause->sge_th_hi + FW_PREFETCH_CNT > 2739 pause->sge_th_hi + FW_PREFETCH_CNT >
2740 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 2740 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2741 2741
2742 tpa_agg_size = min_t(u32, 2742 tpa_agg_size = min_t(u32,
2743 (min_t(u32, 8, MAX_SKB_FRAGS) * 2743 (min_t(u32, 8, MAX_SKB_FRAGS) *
2744 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 2744 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2745 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 2745 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2746 SGE_PAGE_SHIFT; 2746 SGE_PAGE_SHIFT;
2747 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 2747 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2748 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 2748 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2749 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 2749 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2750 0xffff); 2750 0xffff);
2751 } 2751 }
2752 2752
2753 /* pause - not for e1 */ 2753 /* pause - not for e1 */
2754 if (!CHIP_IS_E1(bp)) { 2754 if (!CHIP_IS_E1(bp)) {
2755 pause->bd_th_lo = BD_TH_LO(bp); 2755 pause->bd_th_lo = BD_TH_LO(bp);
2756 pause->bd_th_hi = BD_TH_HI(bp); 2756 pause->bd_th_hi = BD_TH_HI(bp);
2757 2757
2758 pause->rcq_th_lo = RCQ_TH_LO(bp); 2758 pause->rcq_th_lo = RCQ_TH_LO(bp);
2759 pause->rcq_th_hi = RCQ_TH_HI(bp); 2759 pause->rcq_th_hi = RCQ_TH_HI(bp);
2760 /* 2760 /*
2761 * validate that rings have enough entries to cross 2761 * validate that rings have enough entries to cross
2762 * high thresholds 2762 * high thresholds
2763 */ 2763 */
2764 WARN_ON(bp->dropless_fc && 2764 WARN_ON(bp->dropless_fc &&
2765 pause->bd_th_hi + FW_PREFETCH_CNT > 2765 pause->bd_th_hi + FW_PREFETCH_CNT >
2766 bp->rx_ring_size); 2766 bp->rx_ring_size);
2767 WARN_ON(bp->dropless_fc && 2767 WARN_ON(bp->dropless_fc &&
2768 pause->rcq_th_hi + FW_PREFETCH_CNT > 2768 pause->rcq_th_hi + FW_PREFETCH_CNT >
2769 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 2769 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2770 2770
2771 pause->pri_map = 1; 2771 pause->pri_map = 1;
2772 } 2772 }
2773 2773
2774 /* rxq setup */ 2774 /* rxq setup */
2775 rxq_init->dscr_map = fp->rx_desc_mapping; 2775 rxq_init->dscr_map = fp->rx_desc_mapping;
2776 rxq_init->sge_map = fp->rx_sge_mapping; 2776 rxq_init->sge_map = fp->rx_sge_mapping;
2777 rxq_init->rcq_map = fp->rx_comp_mapping; 2777 rxq_init->rcq_map = fp->rx_comp_mapping;
2778 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 2778 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2779 2779
2780 /* This should be a maximum number of data bytes that may be 2780 /* This should be a maximum number of data bytes that may be
2781 * placed on the BD (not including paddings). 2781 * placed on the BD (not including paddings).
2782 */ 2782 */
2783 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 2783 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2784 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 2784 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
2785 2785
2786 rxq_init->cl_qzone_id = fp->cl_qzone_id; 2786 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2787 rxq_init->tpa_agg_sz = tpa_agg_size; 2787 rxq_init->tpa_agg_sz = tpa_agg_size;
2788 rxq_init->sge_buf_sz = sge_sz; 2788 rxq_init->sge_buf_sz = sge_sz;
2789 rxq_init->max_sges_pkt = max_sge; 2789 rxq_init->max_sges_pkt = max_sge;
2790 rxq_init->rss_engine_id = BP_FUNC(bp); 2790 rxq_init->rss_engine_id = BP_FUNC(bp);
2791 2791
2792 /* Maximum number or simultaneous TPA aggregation for this Queue. 2792 /* Maximum number or simultaneous TPA aggregation for this Queue.
2793 * 2793 *
2794 * For PF Clients it should be the maximum avaliable number. 2794 * For PF Clients it should be the maximum avaliable number.
2795 * VF driver(s) may want to define it to a smaller value. 2795 * VF driver(s) may want to define it to a smaller value.
2796 */ 2796 */
2797 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 2797 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2798 2798
2799 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 2799 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2800 rxq_init->fw_sb_id = fp->fw_sb_id; 2800 rxq_init->fw_sb_id = fp->fw_sb_id;
2801 2801
2802 if (IS_FCOE_FP(fp)) 2802 if (IS_FCOE_FP(fp))
2803 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 2803 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2804 else 2804 else
2805 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 2805 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2806 } 2806 }
2807 2807
2808 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 2808 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2809 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 2809 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2810 u8 cos) 2810 u8 cos)
2811 { 2811 {
2812 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; 2812 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2813 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 2813 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2814 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 2814 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2815 txq_init->fw_sb_id = fp->fw_sb_id; 2815 txq_init->fw_sb_id = fp->fw_sb_id;
2816 2816
2817 /* 2817 /*
2818 * set the tss leading client id for TX classfication == 2818 * set the tss leading client id for TX classfication ==
2819 * leading RSS client id 2819 * leading RSS client id
2820 */ 2820 */
2821 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 2821 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2822 2822
2823 if (IS_FCOE_FP(fp)) { 2823 if (IS_FCOE_FP(fp)) {
2824 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 2824 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2825 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 2825 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2826 } 2826 }
2827 } 2827 }
2828 2828
2829 static void bnx2x_pf_init(struct bnx2x *bp) 2829 static void bnx2x_pf_init(struct bnx2x *bp)
2830 { 2830 {
2831 struct bnx2x_func_init_params func_init = {0}; 2831 struct bnx2x_func_init_params func_init = {0};
2832 struct event_ring_data eq_data = { {0} }; 2832 struct event_ring_data eq_data = { {0} };
2833 u16 flags; 2833 u16 flags;
2834 2834
2835 if (!CHIP_IS_E1x(bp)) { 2835 if (!CHIP_IS_E1x(bp)) {
2836 /* reset IGU PF statistics: MSIX + ATTN */ 2836 /* reset IGU PF statistics: MSIX + ATTN */
2837 /* PF */ 2837 /* PF */
2838 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2838 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2839 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2839 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2840 (CHIP_MODE_IS_4_PORT(bp) ? 2840 (CHIP_MODE_IS_4_PORT(bp) ?
2841 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2841 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2842 /* ATTN */ 2842 /* ATTN */
2843 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2843 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2844 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2844 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2845 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 2845 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2846 (CHIP_MODE_IS_4_PORT(bp) ? 2846 (CHIP_MODE_IS_4_PORT(bp) ?
2847 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2847 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2848 } 2848 }
2849 2849
2850 /* function setup flags */ 2850 /* function setup flags */
2851 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 2851 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2852 2852
2853 /* This flag is relevant for E1x only. 2853 /* This flag is relevant for E1x only.
2854 * E2 doesn't have a TPA configuration in a function level. 2854 * E2 doesn't have a TPA configuration in a function level.
2855 */ 2855 */
2856 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 2856 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2857 2857
2858 func_init.func_flgs = flags; 2858 func_init.func_flgs = flags;
2859 func_init.pf_id = BP_FUNC(bp); 2859 func_init.pf_id = BP_FUNC(bp);
2860 func_init.func_id = BP_FUNC(bp); 2860 func_init.func_id = BP_FUNC(bp);
2861 func_init.spq_map = bp->spq_mapping; 2861 func_init.spq_map = bp->spq_mapping;
2862 func_init.spq_prod = bp->spq_prod_idx; 2862 func_init.spq_prod = bp->spq_prod_idx;
2863 2863
2864 bnx2x_func_init(bp, &func_init); 2864 bnx2x_func_init(bp, &func_init);
2865 2865
2866 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 2866 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2867 2867
2868 /* 2868 /*
2869 * Congestion management values depend on the link rate 2869 * Congestion management values depend on the link rate
2870 * There is no active link so initial link rate is set to 10 Gbps. 2870 * There is no active link so initial link rate is set to 10 Gbps.
2871 * When the link comes up The congestion management values are 2871 * When the link comes up The congestion management values are
2872 * re-calculated according to the actual link rate. 2872 * re-calculated according to the actual link rate.
2873 */ 2873 */
2874 bp->link_vars.line_speed = SPEED_10000; 2874 bp->link_vars.line_speed = SPEED_10000;
2875 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 2875 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2876 2876
2877 /* Only the PMF sets the HW */ 2877 /* Only the PMF sets the HW */
2878 if (bp->port.pmf) 2878 if (bp->port.pmf)
2879 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2879 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2880 2880
2881 /* init Event Queue */ 2881 /* init Event Queue */
2882 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 2882 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2883 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 2883 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2884 eq_data.producer = bp->eq_prod; 2884 eq_data.producer = bp->eq_prod;
2885 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 2885 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2886 eq_data.sb_id = DEF_SB_ID; 2886 eq_data.sb_id = DEF_SB_ID;
2887 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 2887 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2888 } 2888 }
2889 2889
2890 2890
2891 static void bnx2x_e1h_disable(struct bnx2x *bp) 2891 static void bnx2x_e1h_disable(struct bnx2x *bp)
2892 { 2892 {
2893 int port = BP_PORT(bp); 2893 int port = BP_PORT(bp);
2894 2894
2895 bnx2x_tx_disable(bp); 2895 bnx2x_tx_disable(bp);
2896 2896
2897 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2897 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2898 } 2898 }
2899 2899
2900 static void bnx2x_e1h_enable(struct bnx2x *bp) 2900 static void bnx2x_e1h_enable(struct bnx2x *bp)
2901 { 2901 {
2902 int port = BP_PORT(bp); 2902 int port = BP_PORT(bp);
2903 2903
2904 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2904 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2905 2905
2906 /* Tx queue should be only reenabled */ 2906 /* Tx queue should be only reenabled */
2907 netif_tx_wake_all_queues(bp->dev); 2907 netif_tx_wake_all_queues(bp->dev);
2908 2908
2909 /* 2909 /*
2910 * Should not call netif_carrier_on since it will be called if the link 2910 * Should not call netif_carrier_on since it will be called if the link
2911 * is up when checking for link state 2911 * is up when checking for link state
2912 */ 2912 */
2913 } 2913 }
2914 2914
2915 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 2915 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
2916 2916
2917 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 2917 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
2918 { 2918 {
2919 struct eth_stats_info *ether_stat = 2919 struct eth_stats_info *ether_stat =
2920 &bp->slowpath->drv_info_to_mcp.ether_stat; 2920 &bp->slowpath->drv_info_to_mcp.ether_stat;
2921 2921
2922 /* leave last char as NULL */ 2922 /* leave last char as NULL */
2923 memcpy(ether_stat->version, DRV_MODULE_VERSION, 2923 memcpy(ether_stat->version, DRV_MODULE_VERSION,
2924 ETH_STAT_INFO_VERSION_LEN - 1); 2924 ETH_STAT_INFO_VERSION_LEN - 1);
2925 2925
2926 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj, 2926 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj,
2927 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 2927 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
2928 ether_stat->mac_local); 2928 ether_stat->mac_local);
2929 2929
2930 ether_stat->mtu_size = bp->dev->mtu; 2930 ether_stat->mtu_size = bp->dev->mtu;
2931 2931
2932 if (bp->dev->features & NETIF_F_RXCSUM) 2932 if (bp->dev->features & NETIF_F_RXCSUM)
2933 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 2933 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
2934 if (bp->dev->features & NETIF_F_TSO) 2934 if (bp->dev->features & NETIF_F_TSO)
2935 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 2935 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
2936 ether_stat->feature_flags |= bp->common.boot_mode; 2936 ether_stat->feature_flags |= bp->common.boot_mode;
2937 2937
2938 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 2938 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
2939 2939
2940 ether_stat->txq_size = bp->tx_ring_size; 2940 ether_stat->txq_size = bp->tx_ring_size;
2941 ether_stat->rxq_size = bp->rx_ring_size; 2941 ether_stat->rxq_size = bp->rx_ring_size;
2942 } 2942 }
2943 2943
2944 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 2944 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
2945 { 2945 {
2946 #ifdef BCM_CNIC 2946 #ifdef BCM_CNIC
2947 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 2947 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
2948 struct fcoe_stats_info *fcoe_stat = 2948 struct fcoe_stats_info *fcoe_stat =
2949 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 2949 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
2950 2950
2951 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN); 2951 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN);
2952 2952
2953 fcoe_stat->qos_priority = 2953 fcoe_stat->qos_priority =
2954 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 2954 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
2955 2955
2956 /* insert FCoE stats from ramrod response */ 2956 /* insert FCoE stats from ramrod response */
2957 if (!NO_FCOE(bp)) { 2957 if (!NO_FCOE(bp)) {
2958 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 2958 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
2959 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2959 &bp->fw_stats_data->queue_stats[FCOE_IDX].
2960 tstorm_queue_statistics; 2960 tstorm_queue_statistics;
2961 2961
2962 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 2962 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
2963 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2963 &bp->fw_stats_data->queue_stats[FCOE_IDX].
2964 xstorm_queue_statistics; 2964 xstorm_queue_statistics;
2965 2965
2966 struct fcoe_statistics_params *fw_fcoe_stat = 2966 struct fcoe_statistics_params *fw_fcoe_stat =
2967 &bp->fw_stats_data->fcoe; 2967 &bp->fw_stats_data->fcoe;
2968 2968
2969 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, 2969 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
2970 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 2970 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
2971 2971
2972 ADD_64(fcoe_stat->rx_bytes_hi, 2972 ADD_64(fcoe_stat->rx_bytes_hi,
2973 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 2973 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
2974 fcoe_stat->rx_bytes_lo, 2974 fcoe_stat->rx_bytes_lo,
2975 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 2975 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
2976 2976
2977 ADD_64(fcoe_stat->rx_bytes_hi, 2977 ADD_64(fcoe_stat->rx_bytes_hi,
2978 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 2978 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
2979 fcoe_stat->rx_bytes_lo, 2979 fcoe_stat->rx_bytes_lo,
2980 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 2980 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
2981 2981
2982 ADD_64(fcoe_stat->rx_bytes_hi, 2982 ADD_64(fcoe_stat->rx_bytes_hi,
2983 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 2983 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
2984 fcoe_stat->rx_bytes_lo, 2984 fcoe_stat->rx_bytes_lo,
2985 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 2985 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
2986 2986
2987 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2987 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2988 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 2988 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
2989 2989
2990 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2990 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2991 fcoe_q_tstorm_stats->rcv_ucast_pkts); 2991 fcoe_q_tstorm_stats->rcv_ucast_pkts);
2992 2992
2993 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2993 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2994 fcoe_q_tstorm_stats->rcv_bcast_pkts); 2994 fcoe_q_tstorm_stats->rcv_bcast_pkts);
2995 2995
2996 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2996 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2997 fcoe_q_tstorm_stats->rcv_ucast_pkts); 2997 fcoe_q_tstorm_stats->rcv_mcast_pkts);
2998 2998
2999 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, 2999 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3000 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 3000 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3001 3001
3002 ADD_64(fcoe_stat->tx_bytes_hi, 3002 ADD_64(fcoe_stat->tx_bytes_hi,
3003 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3003 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3004 fcoe_stat->tx_bytes_lo, 3004 fcoe_stat->tx_bytes_lo,
3005 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3005 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3006 3006
3007 ADD_64(fcoe_stat->tx_bytes_hi, 3007 ADD_64(fcoe_stat->tx_bytes_hi,
3008 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3008 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3009 fcoe_stat->tx_bytes_lo, 3009 fcoe_stat->tx_bytes_lo,
3010 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3010 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3011 3011
3012 ADD_64(fcoe_stat->tx_bytes_hi, 3012 ADD_64(fcoe_stat->tx_bytes_hi,
3013 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3013 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3014 fcoe_stat->tx_bytes_lo, 3014 fcoe_stat->tx_bytes_lo,
3015 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3015 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3016 3016
3017 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3017 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3018 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3018 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3019 3019
3020 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3020 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3021 fcoe_q_xstorm_stats->ucast_pkts_sent); 3021 fcoe_q_xstorm_stats->ucast_pkts_sent);
3022 3022
3023 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3023 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3024 fcoe_q_xstorm_stats->bcast_pkts_sent); 3024 fcoe_q_xstorm_stats->bcast_pkts_sent);
3025 3025
3026 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3026 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3027 fcoe_q_xstorm_stats->mcast_pkts_sent); 3027 fcoe_q_xstorm_stats->mcast_pkts_sent);
3028 } 3028 }
3029 3029
3030 /* ask L5 driver to add data to the struct */ 3030 /* ask L5 driver to add data to the struct */
3031 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3031 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3032 #endif 3032 #endif
3033 } 3033 }
3034 3034
3035 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3035 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3036 { 3036 {
3037 #ifdef BCM_CNIC 3037 #ifdef BCM_CNIC
3038 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3038 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3039 struct iscsi_stats_info *iscsi_stat = 3039 struct iscsi_stats_info *iscsi_stat =
3040 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3040 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3041 3041
3042 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); 3042 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3043 3043
3044 iscsi_stat->qos_priority = 3044 iscsi_stat->qos_priority =
3045 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3045 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3046 3046
3047 /* ask L5 driver to add data to the struct */ 3047 /* ask L5 driver to add data to the struct */
3048 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3048 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3049 #endif 3049 #endif
3050 } 3050 }
3051 3051
3052 /* called due to MCP event (on pmf): 3052 /* called due to MCP event (on pmf):
3053 * reread new bandwidth configuration 3053 * reread new bandwidth configuration
3054 * configure FW 3054 * configure FW
3055 * notify others function about the change 3055 * notify others function about the change
3056 */ 3056 */
3057 static inline void bnx2x_config_mf_bw(struct bnx2x *bp) 3057 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
3058 { 3058 {
3059 if (bp->link_vars.link_up) { 3059 if (bp->link_vars.link_up) {
3060 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3060 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3061 bnx2x_link_sync_notify(bp); 3061 bnx2x_link_sync_notify(bp);
3062 } 3062 }
3063 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3063 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3064 } 3064 }
3065 3065
3066 static inline void bnx2x_set_mf_bw(struct bnx2x *bp) 3066 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
3067 { 3067 {
3068 bnx2x_config_mf_bw(bp); 3068 bnx2x_config_mf_bw(bp);
3069 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3069 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3070 } 3070 }
3071 3071
3072 static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3072 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3073 { 3073 {
3074 enum drv_info_opcode op_code; 3074 enum drv_info_opcode op_code;
3075 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3075 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3076 3076
3077 /* if drv_info version supported by MFW doesn't match - send NACK */ 3077 /* if drv_info version supported by MFW doesn't match - send NACK */
3078 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3078 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3079 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3079 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3080 return; 3080 return;
3081 } 3081 }
3082 3082
3083 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3083 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3084 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3084 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3085 3085
3086 memset(&bp->slowpath->drv_info_to_mcp, 0, 3086 memset(&bp->slowpath->drv_info_to_mcp, 0,
3087 sizeof(union drv_info_to_mcp)); 3087 sizeof(union drv_info_to_mcp));
3088 3088
3089 switch (op_code) { 3089 switch (op_code) {
3090 case ETH_STATS_OPCODE: 3090 case ETH_STATS_OPCODE:
3091 bnx2x_drv_info_ether_stat(bp); 3091 bnx2x_drv_info_ether_stat(bp);
3092 break; 3092 break;
3093 case FCOE_STATS_OPCODE: 3093 case FCOE_STATS_OPCODE:
3094 bnx2x_drv_info_fcoe_stat(bp); 3094 bnx2x_drv_info_fcoe_stat(bp);
3095 break; 3095 break;
3096 case ISCSI_STATS_OPCODE: 3096 case ISCSI_STATS_OPCODE:
3097 bnx2x_drv_info_iscsi_stat(bp); 3097 bnx2x_drv_info_iscsi_stat(bp);
3098 break; 3098 break;
3099 default: 3099 default:
3100 /* if op code isn't supported - send NACK */ 3100 /* if op code isn't supported - send NACK */
3101 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3101 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3102 return; 3102 return;
3103 } 3103 }
3104 3104
3105 /* if we got drv_info attn from MFW then these fields are defined in 3105 /* if we got drv_info attn from MFW then these fields are defined in
3106 * shmem2 for sure 3106 * shmem2 for sure
3107 */ 3107 */
3108 SHMEM2_WR(bp, drv_info_host_addr_lo, 3108 SHMEM2_WR(bp, drv_info_host_addr_lo,
3109 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3109 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3110 SHMEM2_WR(bp, drv_info_host_addr_hi, 3110 SHMEM2_WR(bp, drv_info_host_addr_hi,
3111 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3111 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3112 3112
3113 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3113 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3114 } 3114 }
3115 3115
3116 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 3116 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3117 { 3117 {
3118 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 3118 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3119 3119
3120 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 3120 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3121 3121
3122 /* 3122 /*
3123 * This is the only place besides the function initialization 3123 * This is the only place besides the function initialization
3124 * where the bp->flags can change so it is done without any 3124 * where the bp->flags can change so it is done without any
3125 * locks 3125 * locks
3126 */ 3126 */
3127 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3127 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3128 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); 3128 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
3129 bp->flags |= MF_FUNC_DIS; 3129 bp->flags |= MF_FUNC_DIS;
3130 3130
3131 bnx2x_e1h_disable(bp); 3131 bnx2x_e1h_disable(bp);
3132 } else { 3132 } else {
3133 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 3133 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
3134 bp->flags &= ~MF_FUNC_DIS; 3134 bp->flags &= ~MF_FUNC_DIS;
3135 3135
3136 bnx2x_e1h_enable(bp); 3136 bnx2x_e1h_enable(bp);
3137 } 3137 }
3138 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 3138 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3139 } 3139 }
3140 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 3140 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3141 bnx2x_config_mf_bw(bp); 3141 bnx2x_config_mf_bw(bp);
3142 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 3142 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3143 } 3143 }
3144 3144
3145 /* Report results to MCP */ 3145 /* Report results to MCP */
3146 if (dcc_event) 3146 if (dcc_event)
3147 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 3147 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3148 else 3148 else
3149 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 3149 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3150 } 3150 }
3151 3151
3152 /* must be called under the spq lock */ 3152 /* must be called under the spq lock */
3153 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3153 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3154 { 3154 {
3155 struct eth_spe *next_spe = bp->spq_prod_bd; 3155 struct eth_spe *next_spe = bp->spq_prod_bd;
3156 3156
3157 if (bp->spq_prod_bd == bp->spq_last_bd) { 3157 if (bp->spq_prod_bd == bp->spq_last_bd) {
3158 bp->spq_prod_bd = bp->spq; 3158 bp->spq_prod_bd = bp->spq;
3159 bp->spq_prod_idx = 0; 3159 bp->spq_prod_idx = 0;
3160 DP(NETIF_MSG_TIMER, "end of spq\n"); 3160 DP(NETIF_MSG_TIMER, "end of spq\n");
3161 } else { 3161 } else {
3162 bp->spq_prod_bd++; 3162 bp->spq_prod_bd++;
3163 bp->spq_prod_idx++; 3163 bp->spq_prod_idx++;
3164 } 3164 }
3165 return next_spe; 3165 return next_spe;
3166 } 3166 }
3167 3167
3168 /* must be called under the spq lock */ 3168 /* must be called under the spq lock */
3169 static inline void bnx2x_sp_prod_update(struct bnx2x *bp) 3169 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
3170 { 3170 {
3171 int func = BP_FUNC(bp); 3171 int func = BP_FUNC(bp);
3172 3172
3173 /* 3173 /*
3174 * Make sure that BD data is updated before writing the producer: 3174 * Make sure that BD data is updated before writing the producer:
3175 * BD data is written to the memory, the producer is read from the 3175 * BD data is written to the memory, the producer is read from the
3176 * memory, thus we need a full memory barrier to ensure the ordering. 3176 * memory, thus we need a full memory barrier to ensure the ordering.
3177 */ 3177 */
3178 mb(); 3178 mb();
3179 3179
3180 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3180 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3181 bp->spq_prod_idx); 3181 bp->spq_prod_idx);
3182 mmiowb(); 3182 mmiowb();
3183 } 3183 }
3184 3184
3185 /** 3185 /**
3186 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3186 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3187 * 3187 *
3188 * @cmd: command to check 3188 * @cmd: command to check
3189 * @cmd_type: command type 3189 * @cmd_type: command type
3190 */ 3190 */
3191 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3191 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3192 { 3192 {
3193 if ((cmd_type == NONE_CONNECTION_TYPE) || 3193 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3194 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3194 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3195 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3195 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3196 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3196 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3197 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3197 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3198 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3198 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3199 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3199 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3200 return true; 3200 return true;
3201 else 3201 else
3202 return false; 3202 return false;
3203 3203
3204 } 3204 }
3205 3205
3206 3206
3207 /** 3207 /**
3208 * bnx2x_sp_post - place a single command on an SP ring 3208 * bnx2x_sp_post - place a single command on an SP ring
3209 * 3209 *
3210 * @bp: driver handle 3210 * @bp: driver handle
3211 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3211 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3212 * @cid: SW CID the command is related to 3212 * @cid: SW CID the command is related to
3213 * @data_hi: command private data address (high 32 bits) 3213 * @data_hi: command private data address (high 32 bits)
3214 * @data_lo: command private data address (low 32 bits) 3214 * @data_lo: command private data address (low 32 bits)
3215 * @cmd_type: command type (e.g. NONE, ETH) 3215 * @cmd_type: command type (e.g. NONE, ETH)
3216 * 3216 *
3217 * SP data is handled as if it's always an address pair, thus data fields are 3217 * SP data is handled as if it's always an address pair, thus data fields are
3218 * not swapped to little endian in upper functions. Instead this function swaps 3218 * not swapped to little endian in upper functions. Instead this function swaps
3219 * data as if it's two u32 fields. 3219 * data as if it's two u32 fields.
3220 */ 3220 */
3221 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3221 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3222 u32 data_hi, u32 data_lo, int cmd_type) 3222 u32 data_hi, u32 data_lo, int cmd_type)
3223 { 3223 {
3224 struct eth_spe *spe; 3224 struct eth_spe *spe;
3225 u16 type; 3225 u16 type;
3226 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3226 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3227 3227
3228 #ifdef BNX2X_STOP_ON_ERROR 3228 #ifdef BNX2X_STOP_ON_ERROR
3229 if (unlikely(bp->panic)) 3229 if (unlikely(bp->panic))
3230 return -EIO; 3230 return -EIO;
3231 #endif 3231 #endif
3232 3232
3233 spin_lock_bh(&bp->spq_lock); 3233 spin_lock_bh(&bp->spq_lock);
3234 3234
3235 if (common) { 3235 if (common) {
3236 if (!atomic_read(&bp->eq_spq_left)) { 3236 if (!atomic_read(&bp->eq_spq_left)) {
3237 BNX2X_ERR("BUG! EQ ring full!\n"); 3237 BNX2X_ERR("BUG! EQ ring full!\n");
3238 spin_unlock_bh(&bp->spq_lock); 3238 spin_unlock_bh(&bp->spq_lock);
3239 bnx2x_panic(); 3239 bnx2x_panic();
3240 return -EBUSY; 3240 return -EBUSY;
3241 } 3241 }
3242 } else if (!atomic_read(&bp->cq_spq_left)) { 3242 } else if (!atomic_read(&bp->cq_spq_left)) {
3243 BNX2X_ERR("BUG! SPQ ring full!\n"); 3243 BNX2X_ERR("BUG! SPQ ring full!\n");
3244 spin_unlock_bh(&bp->spq_lock); 3244 spin_unlock_bh(&bp->spq_lock);
3245 bnx2x_panic(); 3245 bnx2x_panic();
3246 return -EBUSY; 3246 return -EBUSY;
3247 } 3247 }
3248 3248
3249 spe = bnx2x_sp_get_next(bp); 3249 spe = bnx2x_sp_get_next(bp);
3250 3250
3251 /* CID needs port number to be encoded int it */ 3251 /* CID needs port number to be encoded int it */
3252 spe->hdr.conn_and_cmd_data = 3252 spe->hdr.conn_and_cmd_data =
3253 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3253 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3254 HW_CID(bp, cid)); 3254 HW_CID(bp, cid));
3255 3255
3256 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3256 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3257 3257
3258 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3258 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3259 SPE_HDR_FUNCTION_ID); 3259 SPE_HDR_FUNCTION_ID);
3260 3260
3261 spe->hdr.type = cpu_to_le16(type); 3261 spe->hdr.type = cpu_to_le16(type);
3262 3262
3263 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3263 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3264 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3264 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3265 3265
3266 /* 3266 /*
3267 * It's ok if the actual decrement is issued towards the memory 3267 * It's ok if the actual decrement is issued towards the memory
3268 * somewhere between the spin_lock and spin_unlock. Thus no 3268 * somewhere between the spin_lock and spin_unlock. Thus no
3269 * more explict memory barrier is needed. 3269 * more explict memory barrier is needed.
3270 */ 3270 */
3271 if (common) 3271 if (common)
3272 atomic_dec(&bp->eq_spq_left); 3272 atomic_dec(&bp->eq_spq_left);
3273 else 3273 else
3274 atomic_dec(&bp->cq_spq_left); 3274 atomic_dec(&bp->cq_spq_left);
3275 3275
3276 3276
3277 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, 3277 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
3278 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " 3278 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3279 "type(0x%x) left (CQ, EQ) (%x,%x)\n", 3279 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
3280 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3280 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3281 (u32)(U64_LO(bp->spq_mapping) + 3281 (u32)(U64_LO(bp->spq_mapping) +
3282 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3282 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3283 HW_CID(bp, cid), data_hi, data_lo, type, 3283 HW_CID(bp, cid), data_hi, data_lo, type,
3284 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3284 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3285 3285
3286 bnx2x_sp_prod_update(bp); 3286 bnx2x_sp_prod_update(bp);
3287 spin_unlock_bh(&bp->spq_lock); 3287 spin_unlock_bh(&bp->spq_lock);
3288 return 0; 3288 return 0;
3289 } 3289 }
3290 3290
3291 /* acquire split MCP access lock register */ 3291 /* acquire split MCP access lock register */
3292 static int bnx2x_acquire_alr(struct bnx2x *bp) 3292 static int bnx2x_acquire_alr(struct bnx2x *bp)
3293 { 3293 {
3294 u32 j, val; 3294 u32 j, val;
3295 int rc = 0; 3295 int rc = 0;
3296 3296
3297 might_sleep(); 3297 might_sleep();
3298 for (j = 0; j < 1000; j++) { 3298 for (j = 0; j < 1000; j++) {
3299 val = (1UL << 31); 3299 val = (1UL << 31);
3300 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3300 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3301 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3301 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3302 if (val & (1L << 31)) 3302 if (val & (1L << 31))
3303 break; 3303 break;
3304 3304
3305 msleep(5); 3305 msleep(5);
3306 } 3306 }
3307 if (!(val & (1L << 31))) { 3307 if (!(val & (1L << 31))) {
3308 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3308 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3309 rc = -EBUSY; 3309 rc = -EBUSY;
3310 } 3310 }
3311 3311
3312 return rc; 3312 return rc;
3313 } 3313 }
3314 3314
3315 /* release split MCP access lock register */ 3315 /* release split MCP access lock register */
3316 static void bnx2x_release_alr(struct bnx2x *bp) 3316 static void bnx2x_release_alr(struct bnx2x *bp)
3317 { 3317 {
3318 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3318 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3319 } 3319 }
3320 3320
3321 #define BNX2X_DEF_SB_ATT_IDX 0x0001 3321 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3322 #define BNX2X_DEF_SB_IDX 0x0002 3322 #define BNX2X_DEF_SB_IDX 0x0002
3323 3323
3324 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3324 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3325 { 3325 {
3326 struct host_sp_status_block *def_sb = bp->def_status_blk; 3326 struct host_sp_status_block *def_sb = bp->def_status_blk;
3327 u16 rc = 0; 3327 u16 rc = 0;
3328 3328
3329 barrier(); /* status block is written to by the chip */ 3329 barrier(); /* status block is written to by the chip */
3330 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3330 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3331 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3331 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3332 rc |= BNX2X_DEF_SB_ATT_IDX; 3332 rc |= BNX2X_DEF_SB_ATT_IDX;
3333 } 3333 }
3334 3334
3335 if (bp->def_idx != def_sb->sp_sb.running_index) { 3335 if (bp->def_idx != def_sb->sp_sb.running_index) {
3336 bp->def_idx = def_sb->sp_sb.running_index; 3336 bp->def_idx = def_sb->sp_sb.running_index;
3337 rc |= BNX2X_DEF_SB_IDX; 3337 rc |= BNX2X_DEF_SB_IDX;
3338 } 3338 }
3339 3339
3340 /* Do not reorder: indecies reading should complete before handling */ 3340 /* Do not reorder: indecies reading should complete before handling */
3341 barrier(); 3341 barrier();
3342 return rc; 3342 return rc;
3343 } 3343 }
3344 3344
3345 /* 3345 /*
3346 * slow path service functions 3346 * slow path service functions
3347 */ 3347 */
3348 3348
3349 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3349 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3350 { 3350 {
3351 int port = BP_PORT(bp); 3351 int port = BP_PORT(bp);
3352 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3352 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3353 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3353 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3354 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3354 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3355 NIG_REG_MASK_INTERRUPT_PORT0; 3355 NIG_REG_MASK_INTERRUPT_PORT0;
3356 u32 aeu_mask; 3356 u32 aeu_mask;
3357 u32 nig_mask = 0; 3357 u32 nig_mask = 0;
3358 u32 reg_addr; 3358 u32 reg_addr;
3359 3359
3360 if (bp->attn_state & asserted) 3360 if (bp->attn_state & asserted)
3361 BNX2X_ERR("IGU ERROR\n"); 3361 BNX2X_ERR("IGU ERROR\n");
3362 3362
3363 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3363 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3364 aeu_mask = REG_RD(bp, aeu_addr); 3364 aeu_mask = REG_RD(bp, aeu_addr);
3365 3365
3366 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3366 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3367 aeu_mask, asserted); 3367 aeu_mask, asserted);
3368 aeu_mask &= ~(asserted & 0x3ff); 3368 aeu_mask &= ~(asserted & 0x3ff);
3369 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3369 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3370 3370
3371 REG_WR(bp, aeu_addr, aeu_mask); 3371 REG_WR(bp, aeu_addr, aeu_mask);
3372 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3372 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3373 3373
3374 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3374 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3375 bp->attn_state |= asserted; 3375 bp->attn_state |= asserted;
3376 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3376 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3377 3377
3378 if (asserted & ATTN_HARD_WIRED_MASK) { 3378 if (asserted & ATTN_HARD_WIRED_MASK) {
3379 if (asserted & ATTN_NIG_FOR_FUNC) { 3379 if (asserted & ATTN_NIG_FOR_FUNC) {
3380 3380
3381 bnx2x_acquire_phy_lock(bp); 3381 bnx2x_acquire_phy_lock(bp);
3382 3382
3383 /* save nig interrupt mask */ 3383 /* save nig interrupt mask */
3384 nig_mask = REG_RD(bp, nig_int_mask_addr); 3384 nig_mask = REG_RD(bp, nig_int_mask_addr);
3385 3385
3386 /* If nig_mask is not set, no need to call the update 3386 /* If nig_mask is not set, no need to call the update
3387 * function. 3387 * function.
3388 */ 3388 */
3389 if (nig_mask) { 3389 if (nig_mask) {
3390 REG_WR(bp, nig_int_mask_addr, 0); 3390 REG_WR(bp, nig_int_mask_addr, 0);
3391 3391
3392 bnx2x_link_attn(bp); 3392 bnx2x_link_attn(bp);
3393 } 3393 }
3394 3394
3395 /* handle unicore attn? */ 3395 /* handle unicore attn? */
3396 } 3396 }
3397 if (asserted & ATTN_SW_TIMER_4_FUNC) 3397 if (asserted & ATTN_SW_TIMER_4_FUNC)
3398 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3398 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3399 3399
3400 if (asserted & GPIO_2_FUNC) 3400 if (asserted & GPIO_2_FUNC)
3401 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3401 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3402 3402
3403 if (asserted & GPIO_3_FUNC) 3403 if (asserted & GPIO_3_FUNC)
3404 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3404 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3405 3405
3406 if (asserted & GPIO_4_FUNC) 3406 if (asserted & GPIO_4_FUNC)
3407 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3407 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3408 3408
3409 if (port == 0) { 3409 if (port == 0) {
3410 if (asserted & ATTN_GENERAL_ATTN_1) { 3410 if (asserted & ATTN_GENERAL_ATTN_1) {
3411 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3411 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3412 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3412 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3413 } 3413 }
3414 if (asserted & ATTN_GENERAL_ATTN_2) { 3414 if (asserted & ATTN_GENERAL_ATTN_2) {
3415 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3415 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3416 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3416 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3417 } 3417 }
3418 if (asserted & ATTN_GENERAL_ATTN_3) { 3418 if (asserted & ATTN_GENERAL_ATTN_3) {
3419 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3419 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3420 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3420 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3421 } 3421 }
3422 } else { 3422 } else {
3423 if (asserted & ATTN_GENERAL_ATTN_4) { 3423 if (asserted & ATTN_GENERAL_ATTN_4) {
3424 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3424 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3425 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3425 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3426 } 3426 }
3427 if (asserted & ATTN_GENERAL_ATTN_5) { 3427 if (asserted & ATTN_GENERAL_ATTN_5) {
3428 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3428 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3429 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3429 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3430 } 3430 }
3431 if (asserted & ATTN_GENERAL_ATTN_6) { 3431 if (asserted & ATTN_GENERAL_ATTN_6) {
3432 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3432 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3433 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3433 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3434 } 3434 }
3435 } 3435 }
3436 3436
3437 } /* if hardwired */ 3437 } /* if hardwired */
3438 3438
3439 if (bp->common.int_block == INT_BLOCK_HC) 3439 if (bp->common.int_block == INT_BLOCK_HC)
3440 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3440 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3441 COMMAND_REG_ATTN_BITS_SET); 3441 COMMAND_REG_ATTN_BITS_SET);
3442 else 3442 else
3443 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3443 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3444 3444
3445 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3445 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3446 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3446 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3447 REG_WR(bp, reg_addr, asserted); 3447 REG_WR(bp, reg_addr, asserted);
3448 3448
3449 /* now set back the mask */ 3449 /* now set back the mask */
3450 if (asserted & ATTN_NIG_FOR_FUNC) { 3450 if (asserted & ATTN_NIG_FOR_FUNC) {
3451 REG_WR(bp, nig_int_mask_addr, nig_mask); 3451 REG_WR(bp, nig_int_mask_addr, nig_mask);
3452 bnx2x_release_phy_lock(bp); 3452 bnx2x_release_phy_lock(bp);
3453 } 3453 }
3454 } 3454 }
3455 3455
3456 static inline void bnx2x_fan_failure(struct bnx2x *bp) 3456 static inline void bnx2x_fan_failure(struct bnx2x *bp)
3457 { 3457 {
3458 int port = BP_PORT(bp); 3458 int port = BP_PORT(bp);
3459 u32 ext_phy_config; 3459 u32 ext_phy_config;
3460 /* mark the failure */ 3460 /* mark the failure */
3461 ext_phy_config = 3461 ext_phy_config =
3462 SHMEM_RD(bp, 3462 SHMEM_RD(bp,
3463 dev_info.port_hw_config[port].external_phy_config); 3463 dev_info.port_hw_config[port].external_phy_config);
3464 3464
3465 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3465 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3466 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3466 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3467 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3467 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3468 ext_phy_config); 3468 ext_phy_config);
3469 3469
3470 /* log the failure */ 3470 /* log the failure */
3471 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 3471 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3472 " the driver to shutdown the card to prevent permanent" 3472 " the driver to shutdown the card to prevent permanent"
3473 " damage. Please contact OEM Support for assistance\n"); 3473 " damage. Please contact OEM Support for assistance\n");
3474 3474
3475 /* 3475 /*
3476 * Scheudle device reset (unload) 3476 * Scheudle device reset (unload)
3477 * This is due to some boards consuming sufficient power when driver is 3477 * This is due to some boards consuming sufficient power when driver is
3478 * up to overheat if fan fails. 3478 * up to overheat if fan fails.
3479 */ 3479 */
3480 smp_mb__before_clear_bit(); 3480 smp_mb__before_clear_bit();
3481 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3481 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3482 smp_mb__after_clear_bit(); 3482 smp_mb__after_clear_bit();
3483 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3483 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3484 3484
3485 } 3485 }
3486 3486
3487 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3487 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3488 { 3488 {
3489 int port = BP_PORT(bp); 3489 int port = BP_PORT(bp);
3490 int reg_offset; 3490 int reg_offset;
3491 u32 val; 3491 u32 val;
3492 3492
3493 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3493 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3494 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3494 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3495 3495
3496 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3496 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3497 3497
3498 val = REG_RD(bp, reg_offset); 3498 val = REG_RD(bp, reg_offset);
3499 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3499 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3500 REG_WR(bp, reg_offset, val); 3500 REG_WR(bp, reg_offset, val);
3501 3501
3502 BNX2X_ERR("SPIO5 hw attention\n"); 3502 BNX2X_ERR("SPIO5 hw attention\n");
3503 3503
3504 /* Fan failure attention */ 3504 /* Fan failure attention */
3505 bnx2x_hw_reset_phy(&bp->link_params); 3505 bnx2x_hw_reset_phy(&bp->link_params);
3506 bnx2x_fan_failure(bp); 3506 bnx2x_fan_failure(bp);
3507 } 3507 }
3508 3508
3509 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3509 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3510 bnx2x_acquire_phy_lock(bp); 3510 bnx2x_acquire_phy_lock(bp);
3511 bnx2x_handle_module_detect_int(&bp->link_params); 3511 bnx2x_handle_module_detect_int(&bp->link_params);
3512 bnx2x_release_phy_lock(bp); 3512 bnx2x_release_phy_lock(bp);
3513 } 3513 }
3514 3514
3515 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3515 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3516 3516
3517 val = REG_RD(bp, reg_offset); 3517 val = REG_RD(bp, reg_offset);
3518 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3518 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3519 REG_WR(bp, reg_offset, val); 3519 REG_WR(bp, reg_offset, val);
3520 3520
3521 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3521 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3522 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3522 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3523 bnx2x_panic(); 3523 bnx2x_panic();
3524 } 3524 }
3525 } 3525 }
3526 3526
3527 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3527 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3528 { 3528 {
3529 u32 val; 3529 u32 val;
3530 3530
3531 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3531 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3532 3532
3533 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3533 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3534 BNX2X_ERR("DB hw attention 0x%x\n", val); 3534 BNX2X_ERR("DB hw attention 0x%x\n", val);
3535 /* DORQ discard attention */ 3535 /* DORQ discard attention */
3536 if (val & 0x2) 3536 if (val & 0x2)
3537 BNX2X_ERR("FATAL error from DORQ\n"); 3537 BNX2X_ERR("FATAL error from DORQ\n");
3538 } 3538 }
3539 3539
3540 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3540 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3541 3541
3542 int port = BP_PORT(bp); 3542 int port = BP_PORT(bp);
3543 int reg_offset; 3543 int reg_offset;
3544 3544
3545 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3545 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3546 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3546 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3547 3547
3548 val = REG_RD(bp, reg_offset); 3548 val = REG_RD(bp, reg_offset);
3549 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3549 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3550 REG_WR(bp, reg_offset, val); 3550 REG_WR(bp, reg_offset, val);
3551 3551
3552 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3552 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3553 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3553 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3554 bnx2x_panic(); 3554 bnx2x_panic();
3555 } 3555 }
3556 } 3556 }
3557 3557
3558 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3558 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3559 { 3559 {
3560 u32 val; 3560 u32 val;
3561 3561
3562 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3562 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3563 3563
3564 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3564 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3565 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3565 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3566 /* CFC error attention */ 3566 /* CFC error attention */
3567 if (val & 0x2) 3567 if (val & 0x2)
3568 BNX2X_ERR("FATAL error from CFC\n"); 3568 BNX2X_ERR("FATAL error from CFC\n");
3569 } 3569 }
3570 3570
3571 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3571 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3572 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3572 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3573 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3573 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3574 /* RQ_USDMDP_FIFO_OVERFLOW */ 3574 /* RQ_USDMDP_FIFO_OVERFLOW */
3575 if (val & 0x18000) 3575 if (val & 0x18000)
3576 BNX2X_ERR("FATAL error from PXP\n"); 3576 BNX2X_ERR("FATAL error from PXP\n");
3577 3577
3578 if (!CHIP_IS_E1x(bp)) { 3578 if (!CHIP_IS_E1x(bp)) {
3579 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3579 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3580 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3580 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3581 } 3581 }
3582 } 3582 }
3583 3583
3584 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3584 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3585 3585
3586 int port = BP_PORT(bp); 3586 int port = BP_PORT(bp);
3587 int reg_offset; 3587 int reg_offset;
3588 3588
3589 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3589 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3590 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3590 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3591 3591
3592 val = REG_RD(bp, reg_offset); 3592 val = REG_RD(bp, reg_offset);
3593 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3593 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3594 REG_WR(bp, reg_offset, val); 3594 REG_WR(bp, reg_offset, val);
3595 3595
3596 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3596 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3597 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3597 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3598 bnx2x_panic(); 3598 bnx2x_panic();
3599 } 3599 }
3600 } 3600 }
3601 3601
3602 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3602 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3603 { 3603 {
3604 u32 val; 3604 u32 val;
3605 3605
3606 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3606 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3607 3607
3608 if (attn & BNX2X_PMF_LINK_ASSERT) { 3608 if (attn & BNX2X_PMF_LINK_ASSERT) {
3609 int func = BP_FUNC(bp); 3609 int func = BP_FUNC(bp);
3610 3610
3611 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3611 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3612 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3612 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3613 func_mf_config[BP_ABS_FUNC(bp)].config); 3613 func_mf_config[BP_ABS_FUNC(bp)].config);
3614 val = SHMEM_RD(bp, 3614 val = SHMEM_RD(bp,
3615 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3615 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3616 if (val & DRV_STATUS_DCC_EVENT_MASK) 3616 if (val & DRV_STATUS_DCC_EVENT_MASK)
3617 bnx2x_dcc_event(bp, 3617 bnx2x_dcc_event(bp,
3618 (val & DRV_STATUS_DCC_EVENT_MASK)); 3618 (val & DRV_STATUS_DCC_EVENT_MASK));
3619 3619
3620 if (val & DRV_STATUS_SET_MF_BW) 3620 if (val & DRV_STATUS_SET_MF_BW)
3621 bnx2x_set_mf_bw(bp); 3621 bnx2x_set_mf_bw(bp);
3622 3622
3623 if (val & DRV_STATUS_DRV_INFO_REQ) 3623 if (val & DRV_STATUS_DRV_INFO_REQ)
3624 bnx2x_handle_drv_info_req(bp); 3624 bnx2x_handle_drv_info_req(bp);
3625 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3625 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3626 bnx2x_pmf_update(bp); 3626 bnx2x_pmf_update(bp);
3627 3627
3628 if (bp->port.pmf && 3628 if (bp->port.pmf &&
3629 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3629 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3630 bp->dcbx_enabled > 0) 3630 bp->dcbx_enabled > 0)
3631 /* start dcbx state machine */ 3631 /* start dcbx state machine */
3632 bnx2x_dcbx_set_params(bp, 3632 bnx2x_dcbx_set_params(bp,
3633 BNX2X_DCBX_STATE_NEG_RECEIVED); 3633 BNX2X_DCBX_STATE_NEG_RECEIVED);
3634 if (bp->link_vars.periodic_flags & 3634 if (bp->link_vars.periodic_flags &
3635 PERIODIC_FLAGS_LINK_EVENT) { 3635 PERIODIC_FLAGS_LINK_EVENT) {
3636 /* sync with link */ 3636 /* sync with link */
3637 bnx2x_acquire_phy_lock(bp); 3637 bnx2x_acquire_phy_lock(bp);
3638 bp->link_vars.periodic_flags &= 3638 bp->link_vars.periodic_flags &=
3639 ~PERIODIC_FLAGS_LINK_EVENT; 3639 ~PERIODIC_FLAGS_LINK_EVENT;
3640 bnx2x_release_phy_lock(bp); 3640 bnx2x_release_phy_lock(bp);
3641 if (IS_MF(bp)) 3641 if (IS_MF(bp))
3642 bnx2x_link_sync_notify(bp); 3642 bnx2x_link_sync_notify(bp);
3643 bnx2x_link_report(bp); 3643 bnx2x_link_report(bp);
3644 } 3644 }
3645 /* Always call it here: bnx2x_link_report() will 3645 /* Always call it here: bnx2x_link_report() will
3646 * prevent the link indication duplication. 3646 * prevent the link indication duplication.
3647 */ 3647 */
3648 bnx2x__link_status_update(bp); 3648 bnx2x__link_status_update(bp);
3649 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3649 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3650 3650
3651 BNX2X_ERR("MC assert!\n"); 3651 BNX2X_ERR("MC assert!\n");
3652 bnx2x_mc_assert(bp); 3652 bnx2x_mc_assert(bp);
3653 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3653 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3654 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3654 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3655 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3655 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3656 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3656 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3657 bnx2x_panic(); 3657 bnx2x_panic();
3658 3658
3659 } else if (attn & BNX2X_MCP_ASSERT) { 3659 } else if (attn & BNX2X_MCP_ASSERT) {
3660 3660
3661 BNX2X_ERR("MCP assert!\n"); 3661 BNX2X_ERR("MCP assert!\n");
3662 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3662 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3663 bnx2x_fw_dump(bp); 3663 bnx2x_fw_dump(bp);
3664 3664
3665 } else 3665 } else
3666 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3666 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3667 } 3667 }
3668 3668
3669 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3669 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3670 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3670 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3671 if (attn & BNX2X_GRC_TIMEOUT) { 3671 if (attn & BNX2X_GRC_TIMEOUT) {
3672 val = CHIP_IS_E1(bp) ? 0 : 3672 val = CHIP_IS_E1(bp) ? 0 :
3673 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3673 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3674 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3674 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3675 } 3675 }
3676 if (attn & BNX2X_GRC_RSV) { 3676 if (attn & BNX2X_GRC_RSV) {
3677 val = CHIP_IS_E1(bp) ? 0 : 3677 val = CHIP_IS_E1(bp) ? 0 :
3678 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3678 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3679 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3679 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3680 } 3680 }
3681 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3681 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3682 } 3682 }
3683 } 3683 }
3684 3684
3685 /* 3685 /*
3686 * Bits map: 3686 * Bits map:
3687 * 0-7 - Engine0 load counter. 3687 * 0-7 - Engine0 load counter.
3688 * 8-15 - Engine1 load counter. 3688 * 8-15 - Engine1 load counter.
3689 * 16 - Engine0 RESET_IN_PROGRESS bit. 3689 * 16 - Engine0 RESET_IN_PROGRESS bit.
3690 * 17 - Engine1 RESET_IN_PROGRESS bit. 3690 * 17 - Engine1 RESET_IN_PROGRESS bit.
3691 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 3691 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3692 * on the engine 3692 * on the engine
3693 * 19 - Engine1 ONE_IS_LOADED. 3693 * 19 - Engine1 ONE_IS_LOADED.
3694 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 3694 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3695 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 3695 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3696 * just the one belonging to its engine). 3696 * just the one belonging to its engine).
3697 * 3697 *
3698 */ 3698 */
3699 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 3699 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3700 3700
3701 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 3701 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3702 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 3702 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3703 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 3703 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3704 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 3704 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3705 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 3705 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3706 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 3706 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3707 #define BNX2X_GLOBAL_RESET_BIT 0x00040000 3707 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3708 3708
3709 /* 3709 /*
3710 * Set the GLOBAL_RESET bit. 3710 * Set the GLOBAL_RESET bit.
3711 * 3711 *
3712 * Should be run under rtnl lock 3712 * Should be run under rtnl lock
3713 */ 3713 */
3714 void bnx2x_set_reset_global(struct bnx2x *bp) 3714 void bnx2x_set_reset_global(struct bnx2x *bp)
3715 { 3715 {
3716 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3716 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3717 3717
3718 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 3718 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3719 barrier(); 3719 barrier();
3720 mmiowb(); 3720 mmiowb();
3721 } 3721 }
3722 3722
3723 /* 3723 /*
3724 * Clear the GLOBAL_RESET bit. 3724 * Clear the GLOBAL_RESET bit.
3725 * 3725 *
3726 * Should be run under rtnl lock 3726 * Should be run under rtnl lock
3727 */ 3727 */
3728 static inline void bnx2x_clear_reset_global(struct bnx2x *bp) 3728 static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3729 { 3729 {
3730 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3730 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3731 3731
3732 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 3732 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3733 barrier(); 3733 barrier();
3734 mmiowb(); 3734 mmiowb();
3735 } 3735 }
3736 3736
3737 /* 3737 /*
3738 * Checks the GLOBAL_RESET bit. 3738 * Checks the GLOBAL_RESET bit.
3739 * 3739 *
3740 * should be run under rtnl lock 3740 * should be run under rtnl lock
3741 */ 3741 */
3742 static inline bool bnx2x_reset_is_global(struct bnx2x *bp) 3742 static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3743 { 3743 {
3744 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3744 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3745 3745
3746 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3746 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3747 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 3747 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3748 } 3748 }
3749 3749
3750 /* 3750 /*
3751 * Clear RESET_IN_PROGRESS bit for the current engine. 3751 * Clear RESET_IN_PROGRESS bit for the current engine.
3752 * 3752 *
3753 * Should be run under rtnl lock 3753 * Should be run under rtnl lock
3754 */ 3754 */
3755 static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3755 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3756 { 3756 {
3757 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3757 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3758 u32 bit = BP_PATH(bp) ? 3758 u32 bit = BP_PATH(bp) ?
3759 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3759 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3760 3760
3761 /* Clear the bit */ 3761 /* Clear the bit */
3762 val &= ~bit; 3762 val &= ~bit;
3763 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3763 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3764 barrier(); 3764 barrier();
3765 mmiowb(); 3765 mmiowb();
3766 } 3766 }
3767 3767
3768 /* 3768 /*
3769 * Set RESET_IN_PROGRESS for the current engine. 3769 * Set RESET_IN_PROGRESS for the current engine.
3770 * 3770 *
3771 * should be run under rtnl lock 3771 * should be run under rtnl lock
3772 */ 3772 */
3773 void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3773 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3774 { 3774 {
3775 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3775 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3776 u32 bit = BP_PATH(bp) ? 3776 u32 bit = BP_PATH(bp) ?
3777 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3777 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3778 3778
3779 /* Set the bit */ 3779 /* Set the bit */
3780 val |= bit; 3780 val |= bit;
3781 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3781 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3782 barrier(); 3782 barrier();
3783 mmiowb(); 3783 mmiowb();
3784 } 3784 }
3785 3785
3786 /* 3786 /*
3787 * Checks the RESET_IN_PROGRESS bit for the given engine. 3787 * Checks the RESET_IN_PROGRESS bit for the given engine.
3788 * should be run under rtnl lock 3788 * should be run under rtnl lock
3789 */ 3789 */
3790 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 3790 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3791 { 3791 {
3792 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3792 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3793 u32 bit = engine ? 3793 u32 bit = engine ?
3794 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3794 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3795 3795
3796 /* return false if bit is set */ 3796 /* return false if bit is set */
3797 return (val & bit) ? false : true; 3797 return (val & bit) ? false : true;
3798 } 3798 }
3799 3799
3800 /* 3800 /*
3801 * Increment the load counter for the current engine. 3801 * Increment the load counter for the current engine.
3802 * 3802 *
3803 * should be run under rtnl lock 3803 * should be run under rtnl lock
3804 */ 3804 */
3805 void bnx2x_inc_load_cnt(struct bnx2x *bp) 3805 void bnx2x_inc_load_cnt(struct bnx2x *bp)
3806 { 3806 {
3807 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3807 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3808 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3808 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3809 BNX2X_PATH0_LOAD_CNT_MASK; 3809 BNX2X_PATH0_LOAD_CNT_MASK;
3810 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3810 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3811 BNX2X_PATH0_LOAD_CNT_SHIFT; 3811 BNX2X_PATH0_LOAD_CNT_SHIFT;
3812 3812
3813 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3813 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3814 3814
3815 /* get the current counter value */ 3815 /* get the current counter value */
3816 val1 = (val & mask) >> shift; 3816 val1 = (val & mask) >> shift;
3817 3817
3818 /* increment... */ 3818 /* increment... */
3819 val1++; 3819 val1++;
3820 3820
3821 /* clear the old value */ 3821 /* clear the old value */
3822 val &= ~mask; 3822 val &= ~mask;
3823 3823
3824 /* set the new one */ 3824 /* set the new one */
3825 val |= ((val1 << shift) & mask); 3825 val |= ((val1 << shift) & mask);
3826 3826
3827 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3827 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3828 barrier(); 3828 barrier();
3829 mmiowb(); 3829 mmiowb();
3830 } 3830 }
3831 3831
3832 /** 3832 /**
3833 * bnx2x_dec_load_cnt - decrement the load counter 3833 * bnx2x_dec_load_cnt - decrement the load counter
3834 * 3834 *
3835 * @bp: driver handle 3835 * @bp: driver handle
3836 * 3836 *
3837 * Should be run under rtnl lock. 3837 * Should be run under rtnl lock.
3838 * Decrements the load counter for the current engine. Returns 3838 * Decrements the load counter for the current engine. Returns
3839 * the new counter value. 3839 * the new counter value.
3840 */ 3840 */
3841 u32 bnx2x_dec_load_cnt(struct bnx2x *bp) 3841 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3842 { 3842 {
3843 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3843 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3844 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3844 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3845 BNX2X_PATH0_LOAD_CNT_MASK; 3845 BNX2X_PATH0_LOAD_CNT_MASK;
3846 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3846 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3847 BNX2X_PATH0_LOAD_CNT_SHIFT; 3847 BNX2X_PATH0_LOAD_CNT_SHIFT;
3848 3848
3849 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3849 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3850 3850
3851 /* get the current counter value */ 3851 /* get the current counter value */
3852 val1 = (val & mask) >> shift; 3852 val1 = (val & mask) >> shift;
3853 3853
3854 /* decrement... */ 3854 /* decrement... */
3855 val1--; 3855 val1--;
3856 3856
3857 /* clear the old value */ 3857 /* clear the old value */
3858 val &= ~mask; 3858 val &= ~mask;
3859 3859
3860 /* set the new one */ 3860 /* set the new one */
3861 val |= ((val1 << shift) & mask); 3861 val |= ((val1 << shift) & mask);
3862 3862
3863 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3863 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3864 barrier(); 3864 barrier();
3865 mmiowb(); 3865 mmiowb();
3866 3866
3867 return val1; 3867 return val1;
3868 } 3868 }
3869 3869
3870 /* 3870 /*
3871 * Read the load counter for the current engine. 3871 * Read the load counter for the current engine.
3872 * 3872 *
3873 * should be run under rtnl lock 3873 * should be run under rtnl lock
3874 */ 3874 */
3875 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine) 3875 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3876 { 3876 {
3877 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 3877 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3878 BNX2X_PATH0_LOAD_CNT_MASK); 3878 BNX2X_PATH0_LOAD_CNT_MASK);
3879 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3879 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3880 BNX2X_PATH0_LOAD_CNT_SHIFT); 3880 BNX2X_PATH0_LOAD_CNT_SHIFT);
3881 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3881 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3882 3882
3883 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); 3883 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3884 3884
3885 val = (val & mask) >> shift; 3885 val = (val & mask) >> shift;
3886 3886
3887 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val); 3887 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3888 3888
3889 return val; 3889 return val;
3890 } 3890 }
3891 3891
3892 /* 3892 /*
3893 * Reset the load counter for the current engine. 3893 * Reset the load counter for the current engine.
3894 * 3894 *
3895 * should be run under rtnl lock 3895 * should be run under rtnl lock
3896 */ 3896 */
3897 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp) 3897 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3898 { 3898 {
3899 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3899 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3900 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3900 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3901 BNX2X_PATH0_LOAD_CNT_MASK); 3901 BNX2X_PATH0_LOAD_CNT_MASK);
3902 3902
3903 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); 3903 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3904 } 3904 }
3905 3905
3906 static inline void _print_next_block(int idx, const char *blk) 3906 static inline void _print_next_block(int idx, const char *blk)
3907 { 3907 {
3908 pr_cont("%s%s", idx ? ", " : "", blk); 3908 pr_cont("%s%s", idx ? ", " : "", blk);
3909 } 3909 }
3910 3910
3911 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 3911 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3912 bool print) 3912 bool print)
3913 { 3913 {
3914 int i = 0; 3914 int i = 0;
3915 u32 cur_bit = 0; 3915 u32 cur_bit = 0;
3916 for (i = 0; sig; i++) { 3916 for (i = 0; sig; i++) {
3917 cur_bit = ((u32)0x1 << i); 3917 cur_bit = ((u32)0x1 << i);
3918 if (sig & cur_bit) { 3918 if (sig & cur_bit) {
3919 switch (cur_bit) { 3919 switch (cur_bit) {
3920 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3920 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3921 if (print) 3921 if (print)
3922 _print_next_block(par_num++, "BRB"); 3922 _print_next_block(par_num++, "BRB");
3923 break; 3923 break;
3924 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3924 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3925 if (print) 3925 if (print)
3926 _print_next_block(par_num++, "PARSER"); 3926 _print_next_block(par_num++, "PARSER");
3927 break; 3927 break;
3928 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3928 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3929 if (print) 3929 if (print)
3930 _print_next_block(par_num++, "TSDM"); 3930 _print_next_block(par_num++, "TSDM");
3931 break; 3931 break;
3932 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3932 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3933 if (print) 3933 if (print)
3934 _print_next_block(par_num++, 3934 _print_next_block(par_num++,
3935 "SEARCHER"); 3935 "SEARCHER");
3936 break; 3936 break;
3937 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 3937 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3938 if (print) 3938 if (print)
3939 _print_next_block(par_num++, "TCM"); 3939 _print_next_block(par_num++, "TCM");
3940 break; 3940 break;
3941 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3941 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3942 if (print) 3942 if (print)
3943 _print_next_block(par_num++, "TSEMI"); 3943 _print_next_block(par_num++, "TSEMI");
3944 break; 3944 break;
3945 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3945 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3946 if (print) 3946 if (print)
3947 _print_next_block(par_num++, "XPB"); 3947 _print_next_block(par_num++, "XPB");
3948 break; 3948 break;
3949 } 3949 }
3950 3950
3951 /* Clear the bit */ 3951 /* Clear the bit */
3952 sig &= ~cur_bit; 3952 sig &= ~cur_bit;
3953 } 3953 }
3954 } 3954 }
3955 3955
3956 return par_num; 3956 return par_num;
3957 } 3957 }
3958 3958
3959 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 3959 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3960 bool *global, bool print) 3960 bool *global, bool print)
3961 { 3961 {
3962 int i = 0; 3962 int i = 0;
3963 u32 cur_bit = 0; 3963 u32 cur_bit = 0;
3964 for (i = 0; sig; i++) { 3964 for (i = 0; sig; i++) {
3965 cur_bit = ((u32)0x1 << i); 3965 cur_bit = ((u32)0x1 << i);
3966 if (sig & cur_bit) { 3966 if (sig & cur_bit) {
3967 switch (cur_bit) { 3967 switch (cur_bit) {
3968 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 3968 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3969 if (print) 3969 if (print)
3970 _print_next_block(par_num++, "PBF"); 3970 _print_next_block(par_num++, "PBF");
3971 break; 3971 break;
3972 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3972 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3973 if (print) 3973 if (print)
3974 _print_next_block(par_num++, "QM"); 3974 _print_next_block(par_num++, "QM");
3975 break; 3975 break;
3976 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 3976 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3977 if (print) 3977 if (print)
3978 _print_next_block(par_num++, "TM"); 3978 _print_next_block(par_num++, "TM");
3979 break; 3979 break;
3980 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 3980 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3981 if (print) 3981 if (print)
3982 _print_next_block(par_num++, "XSDM"); 3982 _print_next_block(par_num++, "XSDM");
3983 break; 3983 break;
3984 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 3984 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3985 if (print) 3985 if (print)
3986 _print_next_block(par_num++, "XCM"); 3986 _print_next_block(par_num++, "XCM");
3987 break; 3987 break;
3988 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 3988 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3989 if (print) 3989 if (print)
3990 _print_next_block(par_num++, "XSEMI"); 3990 _print_next_block(par_num++, "XSEMI");
3991 break; 3991 break;
3992 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 3992 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3993 if (print) 3993 if (print)
3994 _print_next_block(par_num++, 3994 _print_next_block(par_num++,
3995 "DOORBELLQ"); 3995 "DOORBELLQ");
3996 break; 3996 break;
3997 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 3997 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3998 if (print) 3998 if (print)
3999 _print_next_block(par_num++, "NIG"); 3999 _print_next_block(par_num++, "NIG");
4000 break; 4000 break;
4001 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4001 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4002 if (print) 4002 if (print)
4003 _print_next_block(par_num++, 4003 _print_next_block(par_num++,
4004 "VAUX PCI CORE"); 4004 "VAUX PCI CORE");
4005 *global = true; 4005 *global = true;
4006 break; 4006 break;
4007 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4007 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4008 if (print) 4008 if (print)
4009 _print_next_block(par_num++, "DEBUG"); 4009 _print_next_block(par_num++, "DEBUG");
4010 break; 4010 break;
4011 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4011 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4012 if (print) 4012 if (print)
4013 _print_next_block(par_num++, "USDM"); 4013 _print_next_block(par_num++, "USDM");
4014 break; 4014 break;
4015 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4015 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4016 if (print) 4016 if (print)
4017 _print_next_block(par_num++, "UCM"); 4017 _print_next_block(par_num++, "UCM");
4018 break; 4018 break;
4019 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4019 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4020 if (print) 4020 if (print)
4021 _print_next_block(par_num++, "USEMI"); 4021 _print_next_block(par_num++, "USEMI");
4022 break; 4022 break;
4023 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4023 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4024 if (print) 4024 if (print)
4025 _print_next_block(par_num++, "UPB"); 4025 _print_next_block(par_num++, "UPB");
4026 break; 4026 break;
4027 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4027 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4028 if (print) 4028 if (print)
4029 _print_next_block(par_num++, "CSDM"); 4029 _print_next_block(par_num++, "CSDM");
4030 break; 4030 break;
4031 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4031 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4032 if (print) 4032 if (print)
4033 _print_next_block(par_num++, "CCM"); 4033 _print_next_block(par_num++, "CCM");
4034 break; 4034 break;
4035 } 4035 }
4036 4036
4037 /* Clear the bit */ 4037 /* Clear the bit */
4038 sig &= ~cur_bit; 4038 sig &= ~cur_bit;
4039 } 4039 }
4040 } 4040 }
4041 4041
4042 return par_num; 4042 return par_num;
4043 } 4043 }
4044 4044
4045 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 4045 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4046 bool print) 4046 bool print)
4047 { 4047 {
4048 int i = 0; 4048 int i = 0;
4049 u32 cur_bit = 0; 4049 u32 cur_bit = 0;
4050 for (i = 0; sig; i++) { 4050 for (i = 0; sig; i++) {
4051 cur_bit = ((u32)0x1 << i); 4051 cur_bit = ((u32)0x1 << i);
4052 if (sig & cur_bit) { 4052 if (sig & cur_bit) {
4053 switch (cur_bit) { 4053 switch (cur_bit) {
4054 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4054 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4055 if (print) 4055 if (print)
4056 _print_next_block(par_num++, "CSEMI"); 4056 _print_next_block(par_num++, "CSEMI");
4057 break; 4057 break;
4058 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4058 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4059 if (print) 4059 if (print)
4060 _print_next_block(par_num++, "PXP"); 4060 _print_next_block(par_num++, "PXP");
4061 break; 4061 break;
4062 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4062 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4063 if (print) 4063 if (print)
4064 _print_next_block(par_num++, 4064 _print_next_block(par_num++,
4065 "PXPPCICLOCKCLIENT"); 4065 "PXPPCICLOCKCLIENT");
4066 break; 4066 break;
4067 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4067 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4068 if (print) 4068 if (print)
4069 _print_next_block(par_num++, "CFC"); 4069 _print_next_block(par_num++, "CFC");
4070 break; 4070 break;
4071 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4071 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4072 if (print) 4072 if (print)
4073 _print_next_block(par_num++, "CDU"); 4073 _print_next_block(par_num++, "CDU");
4074 break; 4074 break;
4075 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4075 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4076 if (print) 4076 if (print)
4077 _print_next_block(par_num++, "DMAE"); 4077 _print_next_block(par_num++, "DMAE");
4078 break; 4078 break;
4079 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4079 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4080 if (print) 4080 if (print)
4081 _print_next_block(par_num++, "IGU"); 4081 _print_next_block(par_num++, "IGU");
4082 break; 4082 break;
4083 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4083 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4084 if (print) 4084 if (print)
4085 _print_next_block(par_num++, "MISC"); 4085 _print_next_block(par_num++, "MISC");
4086 break; 4086 break;
4087 } 4087 }
4088 4088
4089 /* Clear the bit */ 4089 /* Clear the bit */
4090 sig &= ~cur_bit; 4090 sig &= ~cur_bit;
4091 } 4091 }
4092 } 4092 }
4093 4093
4094 return par_num; 4094 return par_num;
4095 } 4095 }
4096 4096
4097 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4097 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4098 bool *global, bool print) 4098 bool *global, bool print)
4099 { 4099 {
4100 int i = 0; 4100 int i = 0;
4101 u32 cur_bit = 0; 4101 u32 cur_bit = 0;
4102 for (i = 0; sig; i++) { 4102 for (i = 0; sig; i++) {
4103 cur_bit = ((u32)0x1 << i); 4103 cur_bit = ((u32)0x1 << i);
4104 if (sig & cur_bit) { 4104 if (sig & cur_bit) {
4105 switch (cur_bit) { 4105 switch (cur_bit) {
4106 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4106 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4107 if (print) 4107 if (print)
4108 _print_next_block(par_num++, "MCP ROM"); 4108 _print_next_block(par_num++, "MCP ROM");
4109 *global = true; 4109 *global = true;
4110 break; 4110 break;
4111 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4111 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4112 if (print) 4112 if (print)
4113 _print_next_block(par_num++, 4113 _print_next_block(par_num++,
4114 "MCP UMP RX"); 4114 "MCP UMP RX");
4115 *global = true; 4115 *global = true;
4116 break; 4116 break;
4117 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4117 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4118 if (print) 4118 if (print)
4119 _print_next_block(par_num++, 4119 _print_next_block(par_num++,
4120 "MCP UMP TX"); 4120 "MCP UMP TX");
4121 *global = true; 4121 *global = true;
4122 break; 4122 break;
4123 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4123 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4124 if (print) 4124 if (print)
4125 _print_next_block(par_num++, 4125 _print_next_block(par_num++,
4126 "MCP SCPAD"); 4126 "MCP SCPAD");
4127 *global = true; 4127 *global = true;
4128 break; 4128 break;
4129 } 4129 }
4130 4130
4131 /* Clear the bit */ 4131 /* Clear the bit */
4132 sig &= ~cur_bit; 4132 sig &= ~cur_bit;
4133 } 4133 }
4134 } 4134 }
4135 4135
4136 return par_num; 4136 return par_num;
4137 } 4137 }
4138 4138
4139 static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 4139 static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4140 bool print) 4140 bool print)
4141 { 4141 {
4142 int i = 0; 4142 int i = 0;
4143 u32 cur_bit = 0; 4143 u32 cur_bit = 0;
4144 for (i = 0; sig; i++) { 4144 for (i = 0; sig; i++) {
4145 cur_bit = ((u32)0x1 << i); 4145 cur_bit = ((u32)0x1 << i);
4146 if (sig & cur_bit) { 4146 if (sig & cur_bit) {
4147 switch (cur_bit) { 4147 switch (cur_bit) {
4148 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4148 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4149 if (print) 4149 if (print)
4150 _print_next_block(par_num++, "PGLUE_B"); 4150 _print_next_block(par_num++, "PGLUE_B");
4151 break; 4151 break;
4152 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4152 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4153 if (print) 4153 if (print)
4154 _print_next_block(par_num++, "ATC"); 4154 _print_next_block(par_num++, "ATC");
4155 break; 4155 break;
4156 } 4156 }
4157 4157
4158 /* Clear the bit */ 4158 /* Clear the bit */
4159 sig &= ~cur_bit; 4159 sig &= ~cur_bit;
4160 } 4160 }
4161 } 4161 }
4162 4162
4163 return par_num; 4163 return par_num;
4164 } 4164 }
4165 4165
4166 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4166 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4167 u32 *sig) 4167 u32 *sig)
4168 { 4168 {
4169 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4169 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4170 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4170 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4171 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4171 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4172 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4172 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4173 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4173 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4174 int par_num = 0; 4174 int par_num = 0;
4175 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " 4175 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
4176 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " 4176 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
4177 "[4]:0x%08x\n", 4177 "[4]:0x%08x\n",
4178 sig[0] & HW_PRTY_ASSERT_SET_0, 4178 sig[0] & HW_PRTY_ASSERT_SET_0,
4179 sig[1] & HW_PRTY_ASSERT_SET_1, 4179 sig[1] & HW_PRTY_ASSERT_SET_1,
4180 sig[2] & HW_PRTY_ASSERT_SET_2, 4180 sig[2] & HW_PRTY_ASSERT_SET_2,
4181 sig[3] & HW_PRTY_ASSERT_SET_3, 4181 sig[3] & HW_PRTY_ASSERT_SET_3,
4182 sig[4] & HW_PRTY_ASSERT_SET_4); 4182 sig[4] & HW_PRTY_ASSERT_SET_4);
4183 if (print) 4183 if (print)
4184 netdev_err(bp->dev, 4184 netdev_err(bp->dev,
4185 "Parity errors detected in blocks: "); 4185 "Parity errors detected in blocks: ");
4186 par_num = bnx2x_check_blocks_with_parity0( 4186 par_num = bnx2x_check_blocks_with_parity0(
4187 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4187 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4188 par_num = bnx2x_check_blocks_with_parity1( 4188 par_num = bnx2x_check_blocks_with_parity1(
4189 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4189 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4190 par_num = bnx2x_check_blocks_with_parity2( 4190 par_num = bnx2x_check_blocks_with_parity2(
4191 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4191 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4192 par_num = bnx2x_check_blocks_with_parity3( 4192 par_num = bnx2x_check_blocks_with_parity3(
4193 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4193 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4194 par_num = bnx2x_check_blocks_with_parity4( 4194 par_num = bnx2x_check_blocks_with_parity4(
4195 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4195 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4196 4196
4197 if (print) 4197 if (print)
4198 pr_cont("\n"); 4198 pr_cont("\n");
4199 4199
4200 return true; 4200 return true;
4201 } else 4201 } else
4202 return false; 4202 return false;
4203 } 4203 }
4204 4204
4205 /** 4205 /**
4206 * bnx2x_chk_parity_attn - checks for parity attentions. 4206 * bnx2x_chk_parity_attn - checks for parity attentions.
4207 * 4207 *
4208 * @bp: driver handle 4208 * @bp: driver handle
4209 * @global: true if there was a global attention 4209 * @global: true if there was a global attention
4210 * @print: show parity attention in syslog 4210 * @print: show parity attention in syslog
4211 */ 4211 */
4212 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4212 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4213 { 4213 {
4214 struct attn_route attn = { {0} }; 4214 struct attn_route attn = { {0} };
4215 int port = BP_PORT(bp); 4215 int port = BP_PORT(bp);
4216 4216
4217 attn.sig[0] = REG_RD(bp, 4217 attn.sig[0] = REG_RD(bp,
4218 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4218 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4219 port*4); 4219 port*4);
4220 attn.sig[1] = REG_RD(bp, 4220 attn.sig[1] = REG_RD(bp,
4221 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4221 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4222 port*4); 4222 port*4);
4223 attn.sig[2] = REG_RD(bp, 4223 attn.sig[2] = REG_RD(bp,
4224 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4224 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4225 port*4); 4225 port*4);
4226 attn.sig[3] = REG_RD(bp, 4226 attn.sig[3] = REG_RD(bp,
4227 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4227 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4228 port*4); 4228 port*4);
4229 4229
4230 if (!CHIP_IS_E1x(bp)) 4230 if (!CHIP_IS_E1x(bp))
4231 attn.sig[4] = REG_RD(bp, 4231 attn.sig[4] = REG_RD(bp,
4232 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4232 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4233 port*4); 4233 port*4);
4234 4234
4235 return bnx2x_parity_attn(bp, global, print, attn.sig); 4235 return bnx2x_parity_attn(bp, global, print, attn.sig);
4236 } 4236 }
4237 4237
4238 4238
4239 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4239 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4240 { 4240 {
4241 u32 val; 4241 u32 val;
4242 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4242 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4243 4243
4244 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4244 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4245 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4245 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4246 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4246 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4247 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4247 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4248 "ADDRESS_ERROR\n"); 4248 "ADDRESS_ERROR\n");
4249 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4249 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4250 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4250 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4251 "INCORRECT_RCV_BEHAVIOR\n"); 4251 "INCORRECT_RCV_BEHAVIOR\n");
4252 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4252 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4253 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4253 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4254 "WAS_ERROR_ATTN\n"); 4254 "WAS_ERROR_ATTN\n");
4255 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4255 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4256 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4256 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4257 "VF_LENGTH_VIOLATION_ATTN\n"); 4257 "VF_LENGTH_VIOLATION_ATTN\n");
4258 if (val & 4258 if (val &
4259 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4259 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4260 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4260 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4261 "VF_GRC_SPACE_VIOLATION_ATTN\n"); 4261 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4262 if (val & 4262 if (val &
4263 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4263 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4264 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4264 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4265 "VF_MSIX_BAR_VIOLATION_ATTN\n"); 4265 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4266 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4266 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4267 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4267 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4268 "TCPL_ERROR_ATTN\n"); 4268 "TCPL_ERROR_ATTN\n");
4269 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4269 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4270 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4270 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4271 "TCPL_IN_TWO_RCBS_ATTN\n"); 4271 "TCPL_IN_TWO_RCBS_ATTN\n");
4272 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4272 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4273 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4273 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4274 "CSSNOOP_FIFO_OVERFLOW\n"); 4274 "CSSNOOP_FIFO_OVERFLOW\n");
4275 } 4275 }
4276 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4276 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4277 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4277 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4278 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4278 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4279 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4279 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4280 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4280 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4281 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4281 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4282 BNX2X_ERR("ATC_ATC_INT_STS_REG" 4282 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4283 "_ATC_TCPL_TO_NOT_PEND\n"); 4283 "_ATC_TCPL_TO_NOT_PEND\n");
4284 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4284 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4285 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4285 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4286 "ATC_GPA_MULTIPLE_HITS\n"); 4286 "ATC_GPA_MULTIPLE_HITS\n");
4287 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4287 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4288 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4288 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4289 "ATC_RCPL_TO_EMPTY_CNT\n"); 4289 "ATC_RCPL_TO_EMPTY_CNT\n");
4290 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4290 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4291 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4291 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4292 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4292 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4293 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4293 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4294 "ATC_IREQ_LESS_THAN_STU\n"); 4294 "ATC_IREQ_LESS_THAN_STU\n");
4295 } 4295 }
4296 4296
4297 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4297 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4298 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4298 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4299 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4299 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4300 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4300 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4301 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4301 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4302 } 4302 }
4303 4303
4304 } 4304 }
4305 4305
4306 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4306 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4307 { 4307 {
4308 struct attn_route attn, *group_mask; 4308 struct attn_route attn, *group_mask;
4309 int port = BP_PORT(bp); 4309 int port = BP_PORT(bp);
4310 int index; 4310 int index;
4311 u32 reg_addr; 4311 u32 reg_addr;
4312 u32 val; 4312 u32 val;
4313 u32 aeu_mask; 4313 u32 aeu_mask;
4314 bool global = false; 4314 bool global = false;
4315 4315
4316 /* need to take HW lock because MCP or other port might also 4316 /* need to take HW lock because MCP or other port might also
4317 try to handle this event */ 4317 try to handle this event */
4318 bnx2x_acquire_alr(bp); 4318 bnx2x_acquire_alr(bp);
4319 4319
4320 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4320 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4321 #ifndef BNX2X_STOP_ON_ERROR 4321 #ifndef BNX2X_STOP_ON_ERROR
4322 bp->recovery_state = BNX2X_RECOVERY_INIT; 4322 bp->recovery_state = BNX2X_RECOVERY_INIT;
4323 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4323 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4324 /* Disable HW interrupts */ 4324 /* Disable HW interrupts */
4325 bnx2x_int_disable(bp); 4325 bnx2x_int_disable(bp);
4326 /* In case of parity errors don't handle attentions so that 4326 /* In case of parity errors don't handle attentions so that
4327 * other function would "see" parity errors. 4327 * other function would "see" parity errors.
4328 */ 4328 */
4329 #else 4329 #else
4330 bnx2x_panic(); 4330 bnx2x_panic();
4331 #endif 4331 #endif
4332 bnx2x_release_alr(bp); 4332 bnx2x_release_alr(bp);
4333 return; 4333 return;
4334 } 4334 }
4335 4335
4336 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4336 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4337 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4337 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4338 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4338 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4339 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4339 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4340 if (!CHIP_IS_E1x(bp)) 4340 if (!CHIP_IS_E1x(bp))
4341 attn.sig[4] = 4341 attn.sig[4] =
4342 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4342 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4343 else 4343 else
4344 attn.sig[4] = 0; 4344 attn.sig[4] = 0;
4345 4345
4346 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4346 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4347 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4347 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4348 4348
4349 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4349 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4350 if (deasserted & (1 << index)) { 4350 if (deasserted & (1 << index)) {
4351 group_mask = &bp->attn_group[index]; 4351 group_mask = &bp->attn_group[index];
4352 4352
4353 DP(NETIF_MSG_HW, "group[%d]: %08x %08x " 4353 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4354 "%08x %08x %08x\n", 4354 "%08x %08x %08x\n",
4355 index, 4355 index,
4356 group_mask->sig[0], group_mask->sig[1], 4356 group_mask->sig[0], group_mask->sig[1],
4357 group_mask->sig[2], group_mask->sig[3], 4357 group_mask->sig[2], group_mask->sig[3],
4358 group_mask->sig[4]); 4358 group_mask->sig[4]);
4359 4359
4360 bnx2x_attn_int_deasserted4(bp, 4360 bnx2x_attn_int_deasserted4(bp,
4361 attn.sig[4] & group_mask->sig[4]); 4361 attn.sig[4] & group_mask->sig[4]);
4362 bnx2x_attn_int_deasserted3(bp, 4362 bnx2x_attn_int_deasserted3(bp,
4363 attn.sig[3] & group_mask->sig[3]); 4363 attn.sig[3] & group_mask->sig[3]);
4364 bnx2x_attn_int_deasserted1(bp, 4364 bnx2x_attn_int_deasserted1(bp,
4365 attn.sig[1] & group_mask->sig[1]); 4365 attn.sig[1] & group_mask->sig[1]);
4366 bnx2x_attn_int_deasserted2(bp, 4366 bnx2x_attn_int_deasserted2(bp,
4367 attn.sig[2] & group_mask->sig[2]); 4367 attn.sig[2] & group_mask->sig[2]);
4368 bnx2x_attn_int_deasserted0(bp, 4368 bnx2x_attn_int_deasserted0(bp,
4369 attn.sig[0] & group_mask->sig[0]); 4369 attn.sig[0] & group_mask->sig[0]);
4370 } 4370 }
4371 } 4371 }
4372 4372
4373 bnx2x_release_alr(bp); 4373 bnx2x_release_alr(bp);
4374 4374
4375 if (bp->common.int_block == INT_BLOCK_HC) 4375 if (bp->common.int_block == INT_BLOCK_HC)
4376 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4376 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4377 COMMAND_REG_ATTN_BITS_CLR); 4377 COMMAND_REG_ATTN_BITS_CLR);
4378 else 4378 else
4379 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4379 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4380 4380
4381 val = ~deasserted; 4381 val = ~deasserted;
4382 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4382 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4383 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4383 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4384 REG_WR(bp, reg_addr, val); 4384 REG_WR(bp, reg_addr, val);
4385 4385
4386 if (~bp->attn_state & deasserted) 4386 if (~bp->attn_state & deasserted)
4387 BNX2X_ERR("IGU ERROR\n"); 4387 BNX2X_ERR("IGU ERROR\n");
4388 4388
4389 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4389 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4390 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4390 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4391 4391
4392 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4392 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4393 aeu_mask = REG_RD(bp, reg_addr); 4393 aeu_mask = REG_RD(bp, reg_addr);
4394 4394
4395 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4395 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4396 aeu_mask, deasserted); 4396 aeu_mask, deasserted);
4397 aeu_mask |= (deasserted & 0x3ff); 4397 aeu_mask |= (deasserted & 0x3ff);
4398 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4398 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4399 4399
4400 REG_WR(bp, reg_addr, aeu_mask); 4400 REG_WR(bp, reg_addr, aeu_mask);
4401 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4401 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4402 4402
4403 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4403 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4404 bp->attn_state &= ~deasserted; 4404 bp->attn_state &= ~deasserted;
4405 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4405 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4406 } 4406 }
4407 4407
4408 static void bnx2x_attn_int(struct bnx2x *bp) 4408 static void bnx2x_attn_int(struct bnx2x *bp)
4409 { 4409 {
4410 /* read local copy of bits */ 4410 /* read local copy of bits */
4411 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4411 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4412 attn_bits); 4412 attn_bits);
4413 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4413 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4414 attn_bits_ack); 4414 attn_bits_ack);
4415 u32 attn_state = bp->attn_state; 4415 u32 attn_state = bp->attn_state;
4416 4416
4417 /* look for changed bits */ 4417 /* look for changed bits */
4418 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4418 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4419 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4419 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4420 4420
4421 DP(NETIF_MSG_HW, 4421 DP(NETIF_MSG_HW,
4422 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4422 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4423 attn_bits, attn_ack, asserted, deasserted); 4423 attn_bits, attn_ack, asserted, deasserted);
4424 4424
4425 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4425 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4426 BNX2X_ERR("BAD attention state\n"); 4426 BNX2X_ERR("BAD attention state\n");
4427 4427
4428 /* handle bits that were raised */ 4428 /* handle bits that were raised */
4429 if (asserted) 4429 if (asserted)
4430 bnx2x_attn_int_asserted(bp, asserted); 4430 bnx2x_attn_int_asserted(bp, asserted);
4431 4431
4432 if (deasserted) 4432 if (deasserted)
4433 bnx2x_attn_int_deasserted(bp, deasserted); 4433 bnx2x_attn_int_deasserted(bp, deasserted);
4434 } 4434 }
4435 4435
4436 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4436 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4437 u16 index, u8 op, u8 update) 4437 u16 index, u8 op, u8 update)
4438 { 4438 {
4439 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4439 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4440 4440
4441 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4441 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4442 igu_addr); 4442 igu_addr);
4443 } 4443 }
4444 4444
4445 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4445 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4446 { 4446 {
4447 /* No memory barriers */ 4447 /* No memory barriers */
4448 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4448 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4449 mmiowb(); /* keep prod updates ordered */ 4449 mmiowb(); /* keep prod updates ordered */
4450 } 4450 }
4451 4451
4452 #ifdef BCM_CNIC 4452 #ifdef BCM_CNIC
4453 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4453 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4454 union event_ring_elem *elem) 4454 union event_ring_elem *elem)
4455 { 4455 {
4456 u8 err = elem->message.error; 4456 u8 err = elem->message.error;
4457 4457
4458 if (!bp->cnic_eth_dev.starting_cid || 4458 if (!bp->cnic_eth_dev.starting_cid ||
4459 (cid < bp->cnic_eth_dev.starting_cid && 4459 (cid < bp->cnic_eth_dev.starting_cid &&
4460 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4460 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4461 return 1; 4461 return 1;
4462 4462
4463 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4463 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4464 4464
4465 if (unlikely(err)) { 4465 if (unlikely(err)) {
4466 4466
4467 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4467 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4468 cid); 4468 cid);
4469 bnx2x_panic_dump(bp); 4469 bnx2x_panic_dump(bp);
4470 } 4470 }
4471 bnx2x_cnic_cfc_comp(bp, cid, err); 4471 bnx2x_cnic_cfc_comp(bp, cid, err);
4472 return 0; 4472 return 0;
4473 } 4473 }
4474 #endif 4474 #endif
4475 4475
4476 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4476 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4477 { 4477 {
4478 struct bnx2x_mcast_ramrod_params rparam; 4478 struct bnx2x_mcast_ramrod_params rparam;
4479 int rc; 4479 int rc;
4480 4480
4481 memset(&rparam, 0, sizeof(rparam)); 4481 memset(&rparam, 0, sizeof(rparam));
4482 4482
4483 rparam.mcast_obj = &bp->mcast_obj; 4483 rparam.mcast_obj = &bp->mcast_obj;
4484 4484
4485 netif_addr_lock_bh(bp->dev); 4485 netif_addr_lock_bh(bp->dev);
4486 4486
4487 /* Clear pending state for the last command */ 4487 /* Clear pending state for the last command */
4488 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4488 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4489 4489
4490 /* If there are pending mcast commands - send them */ 4490 /* If there are pending mcast commands - send them */
4491 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4491 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4492 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4492 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4493 if (rc < 0) 4493 if (rc < 0)
4494 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4494 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4495 rc); 4495 rc);
4496 } 4496 }
4497 4497
4498 netif_addr_unlock_bh(bp->dev); 4498 netif_addr_unlock_bh(bp->dev);
4499 } 4499 }
4500 4500
4501 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4501 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4502 union event_ring_elem *elem) 4502 union event_ring_elem *elem)
4503 { 4503 {
4504 unsigned long ramrod_flags = 0; 4504 unsigned long ramrod_flags = 0;
4505 int rc = 0; 4505 int rc = 0;
4506 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4506 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4507 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4507 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4508 4508
4509 /* Always push next commands out, don't wait here */ 4509 /* Always push next commands out, don't wait here */
4510 __set_bit(RAMROD_CONT, &ramrod_flags); 4510 __set_bit(RAMROD_CONT, &ramrod_flags);
4511 4511
4512 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4512 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4513 case BNX2X_FILTER_MAC_PENDING: 4513 case BNX2X_FILTER_MAC_PENDING:
4514 #ifdef BCM_CNIC 4514 #ifdef BCM_CNIC
4515 if (cid == BNX2X_ISCSI_ETH_CID) 4515 if (cid == BNX2X_ISCSI_ETH_CID)
4516 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4516 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4517 else 4517 else
4518 #endif 4518 #endif
4519 vlan_mac_obj = &bp->fp[cid].mac_obj; 4519 vlan_mac_obj = &bp->fp[cid].mac_obj;
4520 4520
4521 break; 4521 break;
4522 case BNX2X_FILTER_MCAST_PENDING: 4522 case BNX2X_FILTER_MCAST_PENDING:
4523 /* This is only relevant for 57710 where multicast MACs are 4523 /* This is only relevant for 57710 where multicast MACs are
4524 * configured as unicast MACs using the same ramrod. 4524 * configured as unicast MACs using the same ramrod.
4525 */ 4525 */
4526 bnx2x_handle_mcast_eqe(bp); 4526 bnx2x_handle_mcast_eqe(bp);
4527 return; 4527 return;
4528 default: 4528 default:
4529 BNX2X_ERR("Unsupported classification command: %d\n", 4529 BNX2X_ERR("Unsupported classification command: %d\n",
4530 elem->message.data.eth_event.echo); 4530 elem->message.data.eth_event.echo);
4531 return; 4531 return;
4532 } 4532 }
4533 4533
4534 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4534 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4535 4535
4536 if (rc < 0) 4536 if (rc < 0)
4537 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4537 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4538 else if (rc > 0) 4538 else if (rc > 0)
4539 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4539 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4540 4540
4541 } 4541 }
4542 4542
4543 #ifdef BCM_CNIC 4543 #ifdef BCM_CNIC
4544 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4544 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4545 #endif 4545 #endif
4546 4546
4547 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4547 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4548 { 4548 {
4549 netif_addr_lock_bh(bp->dev); 4549 netif_addr_lock_bh(bp->dev);
4550 4550
4551 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4551 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4552 4552
4553 /* Send rx_mode command again if was requested */ 4553 /* Send rx_mode command again if was requested */
4554 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4554 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4555 bnx2x_set_storm_rx_mode(bp); 4555 bnx2x_set_storm_rx_mode(bp);
4556 #ifdef BCM_CNIC 4556 #ifdef BCM_CNIC
4557 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4557 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4558 &bp->sp_state)) 4558 &bp->sp_state))
4559 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4559 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4560 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4560 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4561 &bp->sp_state)) 4561 &bp->sp_state))
4562 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4562 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4563 #endif 4563 #endif
4564 4564
4565 netif_addr_unlock_bh(bp->dev); 4565 netif_addr_unlock_bh(bp->dev);
4566 } 4566 }
4567 4567
4568 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4568 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4569 struct bnx2x *bp, u32 cid) 4569 struct bnx2x *bp, u32 cid)
4570 { 4570 {
4571 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4571 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4572 #ifdef BCM_CNIC 4572 #ifdef BCM_CNIC
4573 if (cid == BNX2X_FCOE_ETH_CID) 4573 if (cid == BNX2X_FCOE_ETH_CID)
4574 return &bnx2x_fcoe(bp, q_obj); 4574 return &bnx2x_fcoe(bp, q_obj);
4575 else 4575 else
4576 #endif 4576 #endif
4577 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); 4577 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
4578 } 4578 }
4579 4579
4580 static void bnx2x_eq_int(struct bnx2x *bp) 4580 static void bnx2x_eq_int(struct bnx2x *bp)
4581 { 4581 {
4582 u16 hw_cons, sw_cons, sw_prod; 4582 u16 hw_cons, sw_cons, sw_prod;
4583 union event_ring_elem *elem; 4583 union event_ring_elem *elem;
4584 u32 cid; 4584 u32 cid;
4585 u8 opcode; 4585 u8 opcode;
4586 int spqe_cnt = 0; 4586 int spqe_cnt = 0;
4587 struct bnx2x_queue_sp_obj *q_obj; 4587 struct bnx2x_queue_sp_obj *q_obj;
4588 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4588 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4589 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4589 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4590 4590
4591 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4591 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4592 4592
4593 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4593 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4594 * when we get the the next-page we nned to adjust so the loop 4594 * when we get the the next-page we nned to adjust so the loop
4595 * condition below will be met. The next element is the size of a 4595 * condition below will be met. The next element is the size of a
4596 * regular element and hence incrementing by 1 4596 * regular element and hence incrementing by 1
4597 */ 4597 */
4598 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4598 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4599 hw_cons++; 4599 hw_cons++;
4600 4600
4601 /* This function may never run in parallel with itself for a 4601 /* This function may never run in parallel with itself for a
4602 * specific bp, thus there is no need in "paired" read memory 4602 * specific bp, thus there is no need in "paired" read memory
4603 * barrier here. 4603 * barrier here.
4604 */ 4604 */
4605 sw_cons = bp->eq_cons; 4605 sw_cons = bp->eq_cons;
4606 sw_prod = bp->eq_prod; 4606 sw_prod = bp->eq_prod;
4607 4607
4608 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4608 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4609 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4609 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4610 4610
4611 for (; sw_cons != hw_cons; 4611 for (; sw_cons != hw_cons;
4612 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4612 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4613 4613
4614 4614
4615 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4615 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4616 4616
4617 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4617 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4618 opcode = elem->message.opcode; 4618 opcode = elem->message.opcode;
4619 4619
4620 4620
4621 /* handle eq element */ 4621 /* handle eq element */
4622 switch (opcode) { 4622 switch (opcode) {
4623 case EVENT_RING_OPCODE_STAT_QUERY: 4623 case EVENT_RING_OPCODE_STAT_QUERY:
4624 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", 4624 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4625 bp->stats_comp++); 4625 bp->stats_comp++);
4626 /* nothing to do with stats comp */ 4626 /* nothing to do with stats comp */
4627 goto next_spqe; 4627 goto next_spqe;
4628 4628
4629 case EVENT_RING_OPCODE_CFC_DEL: 4629 case EVENT_RING_OPCODE_CFC_DEL:
4630 /* handle according to cid range */ 4630 /* handle according to cid range */
4631 /* 4631 /*
4632 * we may want to verify here that the bp state is 4632 * we may want to verify here that the bp state is
4633 * HALTING 4633 * HALTING
4634 */ 4634 */
4635 DP(BNX2X_MSG_SP, 4635 DP(BNX2X_MSG_SP,
4636 "got delete ramrod for MULTI[%d]\n", cid); 4636 "got delete ramrod for MULTI[%d]\n", cid);
4637 #ifdef BCM_CNIC 4637 #ifdef BCM_CNIC
4638 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 4638 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4639 goto next_spqe; 4639 goto next_spqe;
4640 #endif 4640 #endif
4641 q_obj = bnx2x_cid_to_q_obj(bp, cid); 4641 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4642 4642
4643 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 4643 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4644 break; 4644 break;
4645 4645
4646 4646
4647 4647
4648 goto next_spqe; 4648 goto next_spqe;
4649 4649
4650 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4650 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4651 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); 4651 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
4652 if (f_obj->complete_cmd(bp, f_obj, 4652 if (f_obj->complete_cmd(bp, f_obj,
4653 BNX2X_F_CMD_TX_STOP)) 4653 BNX2X_F_CMD_TX_STOP))
4654 break; 4654 break;
4655 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 4655 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4656 goto next_spqe; 4656 goto next_spqe;
4657 4657
4658 case EVENT_RING_OPCODE_START_TRAFFIC: 4658 case EVENT_RING_OPCODE_START_TRAFFIC:
4659 DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); 4659 DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
4660 if (f_obj->complete_cmd(bp, f_obj, 4660 if (f_obj->complete_cmd(bp, f_obj,
4661 BNX2X_F_CMD_TX_START)) 4661 BNX2X_F_CMD_TX_START))
4662 break; 4662 break;
4663 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4663 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4664 goto next_spqe; 4664 goto next_spqe;
4665 case EVENT_RING_OPCODE_FUNCTION_START: 4665 case EVENT_RING_OPCODE_FUNCTION_START:
4666 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); 4666 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
4667 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4667 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4668 break; 4668 break;
4669 4669
4670 goto next_spqe; 4670 goto next_spqe;
4671 4671
4672 case EVENT_RING_OPCODE_FUNCTION_STOP: 4672 case EVENT_RING_OPCODE_FUNCTION_STOP:
4673 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); 4673 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
4674 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4674 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4675 break; 4675 break;
4676 4676
4677 goto next_spqe; 4677 goto next_spqe;
4678 } 4678 }
4679 4679
4680 switch (opcode | bp->state) { 4680 switch (opcode | bp->state) {
4681 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4681 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4682 BNX2X_STATE_OPEN): 4682 BNX2X_STATE_OPEN):
4683 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4683 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4684 BNX2X_STATE_OPENING_WAIT4_PORT): 4684 BNX2X_STATE_OPENING_WAIT4_PORT):
4685 cid = elem->message.data.eth_event.echo & 4685 cid = elem->message.data.eth_event.echo &
4686 BNX2X_SWCID_MASK; 4686 BNX2X_SWCID_MASK;
4687 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 4687 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4688 cid); 4688 cid);
4689 rss_raw->clear_pending(rss_raw); 4689 rss_raw->clear_pending(rss_raw);
4690 break; 4690 break;
4691 4691
4692 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 4692 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4693 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 4693 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4694 case (EVENT_RING_OPCODE_SET_MAC | 4694 case (EVENT_RING_OPCODE_SET_MAC |
4695 BNX2X_STATE_CLOSING_WAIT4_HALT): 4695 BNX2X_STATE_CLOSING_WAIT4_HALT):
4696 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4696 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4697 BNX2X_STATE_OPEN): 4697 BNX2X_STATE_OPEN):
4698 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4698 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4699 BNX2X_STATE_DIAG): 4699 BNX2X_STATE_DIAG):
4700 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4700 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4701 BNX2X_STATE_CLOSING_WAIT4_HALT): 4701 BNX2X_STATE_CLOSING_WAIT4_HALT):
4702 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 4702 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4703 bnx2x_handle_classification_eqe(bp, elem); 4703 bnx2x_handle_classification_eqe(bp, elem);
4704 break; 4704 break;
4705 4705
4706 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4706 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4707 BNX2X_STATE_OPEN): 4707 BNX2X_STATE_OPEN):
4708 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4708 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4709 BNX2X_STATE_DIAG): 4709 BNX2X_STATE_DIAG):
4710 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4710 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4711 BNX2X_STATE_CLOSING_WAIT4_HALT): 4711 BNX2X_STATE_CLOSING_WAIT4_HALT):
4712 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 4712 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4713 bnx2x_handle_mcast_eqe(bp); 4713 bnx2x_handle_mcast_eqe(bp);
4714 break; 4714 break;
4715 4715
4716 case (EVENT_RING_OPCODE_FILTERS_RULES | 4716 case (EVENT_RING_OPCODE_FILTERS_RULES |
4717 BNX2X_STATE_OPEN): 4717 BNX2X_STATE_OPEN):
4718 case (EVENT_RING_OPCODE_FILTERS_RULES | 4718 case (EVENT_RING_OPCODE_FILTERS_RULES |
4719 BNX2X_STATE_DIAG): 4719 BNX2X_STATE_DIAG):
4720 case (EVENT_RING_OPCODE_FILTERS_RULES | 4720 case (EVENT_RING_OPCODE_FILTERS_RULES |
4721 BNX2X_STATE_CLOSING_WAIT4_HALT): 4721 BNX2X_STATE_CLOSING_WAIT4_HALT):
4722 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 4722 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4723 bnx2x_handle_rx_mode_eqe(bp); 4723 bnx2x_handle_rx_mode_eqe(bp);
4724 break; 4724 break;
4725 default: 4725 default:
4726 /* unknown event log error and continue */ 4726 /* unknown event log error and continue */
4727 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 4727 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4728 elem->message.opcode, bp->state); 4728 elem->message.opcode, bp->state);
4729 } 4729 }
4730 next_spqe: 4730 next_spqe:
4731 spqe_cnt++; 4731 spqe_cnt++;
4732 } /* for */ 4732 } /* for */
4733 4733
4734 smp_mb__before_atomic_inc(); 4734 smp_mb__before_atomic_inc();
4735 atomic_add(spqe_cnt, &bp->eq_spq_left); 4735 atomic_add(spqe_cnt, &bp->eq_spq_left);
4736 4736
4737 bp->eq_cons = sw_cons; 4737 bp->eq_cons = sw_cons;
4738 bp->eq_prod = sw_prod; 4738 bp->eq_prod = sw_prod;
4739 /* Make sure that above mem writes were issued towards the memory */ 4739 /* Make sure that above mem writes were issued towards the memory */
4740 smp_wmb(); 4740 smp_wmb();
4741 4741
4742 /* update producer */ 4742 /* update producer */
4743 bnx2x_update_eq_prod(bp, bp->eq_prod); 4743 bnx2x_update_eq_prod(bp, bp->eq_prod);
4744 } 4744 }
4745 4745
4746 static void bnx2x_sp_task(struct work_struct *work) 4746 static void bnx2x_sp_task(struct work_struct *work)
4747 { 4747 {
4748 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 4748 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4749 u16 status; 4749 u16 status;
4750 4750
4751 status = bnx2x_update_dsb_idx(bp); 4751 status = bnx2x_update_dsb_idx(bp);
4752 /* if (status == 0) */ 4752 /* if (status == 0) */
4753 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4753 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4754 4754
4755 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); 4755 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
4756 4756
4757 /* HW attentions */ 4757 /* HW attentions */
4758 if (status & BNX2X_DEF_SB_ATT_IDX) { 4758 if (status & BNX2X_DEF_SB_ATT_IDX) {
4759 bnx2x_attn_int(bp); 4759 bnx2x_attn_int(bp);
4760 status &= ~BNX2X_DEF_SB_ATT_IDX; 4760 status &= ~BNX2X_DEF_SB_ATT_IDX;
4761 } 4761 }
4762 4762
4763 /* SP events: STAT_QUERY and others */ 4763 /* SP events: STAT_QUERY and others */
4764 if (status & BNX2X_DEF_SB_IDX) { 4764 if (status & BNX2X_DEF_SB_IDX) {
4765 #ifdef BCM_CNIC 4765 #ifdef BCM_CNIC
4766 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 4766 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4767 4767
4768 if ((!NO_FCOE(bp)) && 4768 if ((!NO_FCOE(bp)) &&
4769 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 4769 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4770 /* 4770 /*
4771 * Prevent local bottom-halves from running as 4771 * Prevent local bottom-halves from running as
4772 * we are going to change the local NAPI list. 4772 * we are going to change the local NAPI list.
4773 */ 4773 */
4774 local_bh_disable(); 4774 local_bh_disable();
4775 napi_schedule(&bnx2x_fcoe(bp, napi)); 4775 napi_schedule(&bnx2x_fcoe(bp, napi));
4776 local_bh_enable(); 4776 local_bh_enable();
4777 } 4777 }
4778 #endif 4778 #endif
4779 /* Handle EQ completions */ 4779 /* Handle EQ completions */
4780 bnx2x_eq_int(bp); 4780 bnx2x_eq_int(bp);
4781 4781
4782 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 4782 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4783 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 4783 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4784 4784
4785 status &= ~BNX2X_DEF_SB_IDX; 4785 status &= ~BNX2X_DEF_SB_IDX;
4786 } 4786 }
4787 4787
4788 if (unlikely(status)) 4788 if (unlikely(status))
4789 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 4789 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4790 status); 4790 status);
4791 4791
4792 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4792 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4793 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 4793 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4794 } 4794 }
4795 4795
4796 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 4796 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4797 { 4797 {
4798 struct net_device *dev = dev_instance; 4798 struct net_device *dev = dev_instance;
4799 struct bnx2x *bp = netdev_priv(dev); 4799 struct bnx2x *bp = netdev_priv(dev);
4800 4800
4801 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 4801 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4802 IGU_INT_DISABLE, 0); 4802 IGU_INT_DISABLE, 0);
4803 4803
4804 #ifdef BNX2X_STOP_ON_ERROR 4804 #ifdef BNX2X_STOP_ON_ERROR
4805 if (unlikely(bp->panic)) 4805 if (unlikely(bp->panic))
4806 return IRQ_HANDLED; 4806 return IRQ_HANDLED;
4807 #endif 4807 #endif
4808 4808
4809 #ifdef BCM_CNIC 4809 #ifdef BCM_CNIC
4810 { 4810 {
4811 struct cnic_ops *c_ops; 4811 struct cnic_ops *c_ops;
4812 4812
4813 rcu_read_lock(); 4813 rcu_read_lock();
4814 c_ops = rcu_dereference(bp->cnic_ops); 4814 c_ops = rcu_dereference(bp->cnic_ops);
4815 if (c_ops) 4815 if (c_ops)
4816 c_ops->cnic_handler(bp->cnic_data, NULL); 4816 c_ops->cnic_handler(bp->cnic_data, NULL);
4817 rcu_read_unlock(); 4817 rcu_read_unlock();
4818 } 4818 }
4819 #endif 4819 #endif
4820 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 4820 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4821 4821
4822 return IRQ_HANDLED; 4822 return IRQ_HANDLED;
4823 } 4823 }
4824 4824
4825 /* end of slow path */ 4825 /* end of slow path */
4826 4826
4827 4827
4828 void bnx2x_drv_pulse(struct bnx2x *bp) 4828 void bnx2x_drv_pulse(struct bnx2x *bp)
4829 { 4829 {
4830 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 4830 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4831 bp->fw_drv_pulse_wr_seq); 4831 bp->fw_drv_pulse_wr_seq);
4832 } 4832 }
4833 4833
4834 4834
4835 static void bnx2x_timer(unsigned long data) 4835 static void bnx2x_timer(unsigned long data)
4836 { 4836 {
4837 u8 cos; 4837 u8 cos;
4838 struct bnx2x *bp = (struct bnx2x *) data; 4838 struct bnx2x *bp = (struct bnx2x *) data;
4839 4839
4840 if (!netif_running(bp->dev)) 4840 if (!netif_running(bp->dev))
4841 return; 4841 return;
4842 4842
4843 if (poll) { 4843 if (poll) {
4844 struct bnx2x_fastpath *fp = &bp->fp[0]; 4844 struct bnx2x_fastpath *fp = &bp->fp[0];
4845 4845
4846 for_each_cos_in_tx_queue(fp, cos) 4846 for_each_cos_in_tx_queue(fp, cos)
4847 bnx2x_tx_int(bp, &fp->txdata[cos]); 4847 bnx2x_tx_int(bp, &fp->txdata[cos]);
4848 bnx2x_rx_int(fp, 1000); 4848 bnx2x_rx_int(fp, 1000);
4849 } 4849 }
4850 4850
4851 if (!BP_NOMCP(bp)) { 4851 if (!BP_NOMCP(bp)) {
4852 int mb_idx = BP_FW_MB_IDX(bp); 4852 int mb_idx = BP_FW_MB_IDX(bp);
4853 u32 drv_pulse; 4853 u32 drv_pulse;
4854 u32 mcp_pulse; 4854 u32 mcp_pulse;
4855 4855
4856 ++bp->fw_drv_pulse_wr_seq; 4856 ++bp->fw_drv_pulse_wr_seq;
4857 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 4857 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4858 /* TBD - add SYSTEM_TIME */ 4858 /* TBD - add SYSTEM_TIME */
4859 drv_pulse = bp->fw_drv_pulse_wr_seq; 4859 drv_pulse = bp->fw_drv_pulse_wr_seq;
4860 bnx2x_drv_pulse(bp); 4860 bnx2x_drv_pulse(bp);
4861 4861
4862 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 4862 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4863 MCP_PULSE_SEQ_MASK); 4863 MCP_PULSE_SEQ_MASK);
4864 /* The delta between driver pulse and mcp response 4864 /* The delta between driver pulse and mcp response
4865 * should be 1 (before mcp response) or 0 (after mcp response) 4865 * should be 1 (before mcp response) or 0 (after mcp response)
4866 */ 4866 */
4867 if ((drv_pulse != mcp_pulse) && 4867 if ((drv_pulse != mcp_pulse) &&
4868 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 4868 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4869 /* someone lost a heartbeat... */ 4869 /* someone lost a heartbeat... */
4870 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 4870 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4871 drv_pulse, mcp_pulse); 4871 drv_pulse, mcp_pulse);
4872 } 4872 }
4873 } 4873 }
4874 4874
4875 if (bp->state == BNX2X_STATE_OPEN) 4875 if (bp->state == BNX2X_STATE_OPEN)
4876 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 4876 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4877 4877
4878 mod_timer(&bp->timer, jiffies + bp->current_interval); 4878 mod_timer(&bp->timer, jiffies + bp->current_interval);
4879 } 4879 }
4880 4880
4881 /* end of Statistics */ 4881 /* end of Statistics */
4882 4882
4883 /* nic init */ 4883 /* nic init */
4884 4884
4885 /* 4885 /*
4886 * nic init service functions 4886 * nic init service functions
4887 */ 4887 */
4888 4888
4889 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 4889 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4890 { 4890 {
4891 u32 i; 4891 u32 i;
4892 if (!(len%4) && !(addr%4)) 4892 if (!(len%4) && !(addr%4))
4893 for (i = 0; i < len; i += 4) 4893 for (i = 0; i < len; i += 4)
4894 REG_WR(bp, addr + i, fill); 4894 REG_WR(bp, addr + i, fill);
4895 else 4895 else
4896 for (i = 0; i < len; i++) 4896 for (i = 0; i < len; i++)
4897 REG_WR8(bp, addr + i, fill); 4897 REG_WR8(bp, addr + i, fill);
4898 4898
4899 } 4899 }
4900 4900
4901 /* helper: writes FP SP data to FW - data_size in dwords */ 4901 /* helper: writes FP SP data to FW - data_size in dwords */
4902 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 4902 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4903 int fw_sb_id, 4903 int fw_sb_id,
4904 u32 *sb_data_p, 4904 u32 *sb_data_p,
4905 u32 data_size) 4905 u32 data_size)
4906 { 4906 {
4907 int index; 4907 int index;
4908 for (index = 0; index < data_size; index++) 4908 for (index = 0; index < data_size; index++)
4909 REG_WR(bp, BAR_CSTRORM_INTMEM + 4909 REG_WR(bp, BAR_CSTRORM_INTMEM +
4910 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 4910 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4911 sizeof(u32)*index, 4911 sizeof(u32)*index,
4912 *(sb_data_p + index)); 4912 *(sb_data_p + index));
4913 } 4913 }
4914 4914
4915 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 4915 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4916 { 4916 {
4917 u32 *sb_data_p; 4917 u32 *sb_data_p;
4918 u32 data_size = 0; 4918 u32 data_size = 0;
4919 struct hc_status_block_data_e2 sb_data_e2; 4919 struct hc_status_block_data_e2 sb_data_e2;
4920 struct hc_status_block_data_e1x sb_data_e1x; 4920 struct hc_status_block_data_e1x sb_data_e1x;
4921 4921
4922 /* disable the function first */ 4922 /* disable the function first */
4923 if (!CHIP_IS_E1x(bp)) { 4923 if (!CHIP_IS_E1x(bp)) {
4924 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4924 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4925 sb_data_e2.common.state = SB_DISABLED; 4925 sb_data_e2.common.state = SB_DISABLED;
4926 sb_data_e2.common.p_func.vf_valid = false; 4926 sb_data_e2.common.p_func.vf_valid = false;
4927 sb_data_p = (u32 *)&sb_data_e2; 4927 sb_data_p = (u32 *)&sb_data_e2;
4928 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4928 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4929 } else { 4929 } else {
4930 memset(&sb_data_e1x, 0, 4930 memset(&sb_data_e1x, 0,
4931 sizeof(struct hc_status_block_data_e1x)); 4931 sizeof(struct hc_status_block_data_e1x));
4932 sb_data_e1x.common.state = SB_DISABLED; 4932 sb_data_e1x.common.state = SB_DISABLED;
4933 sb_data_e1x.common.p_func.vf_valid = false; 4933 sb_data_e1x.common.p_func.vf_valid = false;
4934 sb_data_p = (u32 *)&sb_data_e1x; 4934 sb_data_p = (u32 *)&sb_data_e1x;
4935 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4935 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4936 } 4936 }
4937 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4937 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4938 4938
4939 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4939 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4940 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 4940 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4941 CSTORM_STATUS_BLOCK_SIZE); 4941 CSTORM_STATUS_BLOCK_SIZE);
4942 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4942 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4943 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 4943 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4944 CSTORM_SYNC_BLOCK_SIZE); 4944 CSTORM_SYNC_BLOCK_SIZE);
4945 } 4945 }
4946 4946
4947 /* helper: writes SP SB data to FW */ 4947 /* helper: writes SP SB data to FW */
4948 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 4948 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4949 struct hc_sp_status_block_data *sp_sb_data) 4949 struct hc_sp_status_block_data *sp_sb_data)
4950 { 4950 {
4951 int func = BP_FUNC(bp); 4951 int func = BP_FUNC(bp);
4952 int i; 4952 int i;
4953 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 4953 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4954 REG_WR(bp, BAR_CSTRORM_INTMEM + 4954 REG_WR(bp, BAR_CSTRORM_INTMEM +
4955 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 4955 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4956 i*sizeof(u32), 4956 i*sizeof(u32),
4957 *((u32 *)sp_sb_data + i)); 4957 *((u32 *)sp_sb_data + i));
4958 } 4958 }
4959 4959
4960 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) 4960 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4961 { 4961 {
4962 int func = BP_FUNC(bp); 4962 int func = BP_FUNC(bp);
4963 struct hc_sp_status_block_data sp_sb_data; 4963 struct hc_sp_status_block_data sp_sb_data;
4964 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4964 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4965 4965
4966 sp_sb_data.state = SB_DISABLED; 4966 sp_sb_data.state = SB_DISABLED;
4967 sp_sb_data.p_func.vf_valid = false; 4967 sp_sb_data.p_func.vf_valid = false;
4968 4968
4969 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4969 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4970 4970
4971 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4971 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4972 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 4972 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4973 CSTORM_SP_STATUS_BLOCK_SIZE); 4973 CSTORM_SP_STATUS_BLOCK_SIZE);
4974 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4974 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4975 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 4975 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4976 CSTORM_SP_SYNC_BLOCK_SIZE); 4976 CSTORM_SP_SYNC_BLOCK_SIZE);
4977 4977
4978 } 4978 }
4979 4979
4980 4980
4981 static inline 4981 static inline
4982 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 4982 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4983 int igu_sb_id, int igu_seg_id) 4983 int igu_sb_id, int igu_seg_id)
4984 { 4984 {
4985 hc_sm->igu_sb_id = igu_sb_id; 4985 hc_sm->igu_sb_id = igu_sb_id;
4986 hc_sm->igu_seg_id = igu_seg_id; 4986 hc_sm->igu_seg_id = igu_seg_id;
4987 hc_sm->timer_value = 0xFF; 4987 hc_sm->timer_value = 0xFF;
4988 hc_sm->time_to_expire = 0xFFFFFFFF; 4988 hc_sm->time_to_expire = 0xFFFFFFFF;
4989 } 4989 }
4990 4990
4991 4991
4992 /* allocates state machine ids. */ 4992 /* allocates state machine ids. */
4993 static inline 4993 static inline
4994 void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 4994 void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4995 { 4995 {
4996 /* zero out state machine indices */ 4996 /* zero out state machine indices */
4997 /* rx indices */ 4997 /* rx indices */
4998 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 4998 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4999 4999
5000 /* tx indices */ 5000 /* tx indices */
5001 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5001 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5002 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 5002 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5003 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 5003 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5004 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 5004 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5005 5005
5006 /* map indices */ 5006 /* map indices */
5007 /* rx indices */ 5007 /* rx indices */
5008 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 5008 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5009 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5009 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5010 5010
5011 /* tx indices */ 5011 /* tx indices */
5012 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5012 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5013 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5013 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5014 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5014 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5015 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5015 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5016 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5016 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5017 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5017 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5018 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5018 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5019 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5019 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5020 } 5020 }
5021 5021
5022 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5022 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5023 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5023 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5024 { 5024 {
5025 int igu_seg_id; 5025 int igu_seg_id;
5026 5026
5027 struct hc_status_block_data_e2 sb_data_e2; 5027 struct hc_status_block_data_e2 sb_data_e2;
5028 struct hc_status_block_data_e1x sb_data_e1x; 5028 struct hc_status_block_data_e1x sb_data_e1x;
5029 struct hc_status_block_sm *hc_sm_p; 5029 struct hc_status_block_sm *hc_sm_p;
5030 int data_size; 5030 int data_size;
5031 u32 *sb_data_p; 5031 u32 *sb_data_p;
5032 5032
5033 if (CHIP_INT_MODE_IS_BC(bp)) 5033 if (CHIP_INT_MODE_IS_BC(bp))
5034 igu_seg_id = HC_SEG_ACCESS_NORM; 5034 igu_seg_id = HC_SEG_ACCESS_NORM;
5035 else 5035 else
5036 igu_seg_id = IGU_SEG_ACCESS_NORM; 5036 igu_seg_id = IGU_SEG_ACCESS_NORM;
5037 5037
5038 bnx2x_zero_fp_sb(bp, fw_sb_id); 5038 bnx2x_zero_fp_sb(bp, fw_sb_id);
5039 5039
5040 if (!CHIP_IS_E1x(bp)) { 5040 if (!CHIP_IS_E1x(bp)) {
5041 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5041 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5042 sb_data_e2.common.state = SB_ENABLED; 5042 sb_data_e2.common.state = SB_ENABLED;
5043 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5043 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5044 sb_data_e2.common.p_func.vf_id = vfid; 5044 sb_data_e2.common.p_func.vf_id = vfid;
5045 sb_data_e2.common.p_func.vf_valid = vf_valid; 5045 sb_data_e2.common.p_func.vf_valid = vf_valid;
5046 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5046 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5047 sb_data_e2.common.same_igu_sb_1b = true; 5047 sb_data_e2.common.same_igu_sb_1b = true;
5048 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5048 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5049 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5049 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5050 hc_sm_p = sb_data_e2.common.state_machine; 5050 hc_sm_p = sb_data_e2.common.state_machine;
5051 sb_data_p = (u32 *)&sb_data_e2; 5051 sb_data_p = (u32 *)&sb_data_e2;
5052 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5052 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5053 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5053 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5054 } else { 5054 } else {
5055 memset(&sb_data_e1x, 0, 5055 memset(&sb_data_e1x, 0,
5056 sizeof(struct hc_status_block_data_e1x)); 5056 sizeof(struct hc_status_block_data_e1x));
5057 sb_data_e1x.common.state = SB_ENABLED; 5057 sb_data_e1x.common.state = SB_ENABLED;
5058 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5058 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5059 sb_data_e1x.common.p_func.vf_id = 0xff; 5059 sb_data_e1x.common.p_func.vf_id = 0xff;
5060 sb_data_e1x.common.p_func.vf_valid = false; 5060 sb_data_e1x.common.p_func.vf_valid = false;
5061 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5061 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5062 sb_data_e1x.common.same_igu_sb_1b = true; 5062 sb_data_e1x.common.same_igu_sb_1b = true;
5063 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5063 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5064 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 5064 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5065 hc_sm_p = sb_data_e1x.common.state_machine; 5065 hc_sm_p = sb_data_e1x.common.state_machine;
5066 sb_data_p = (u32 *)&sb_data_e1x; 5066 sb_data_p = (u32 *)&sb_data_e1x;
5067 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5067 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5068 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 5068 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5069 } 5069 }
5070 5070
5071 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 5071 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5072 igu_sb_id, igu_seg_id); 5072 igu_sb_id, igu_seg_id);
5073 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5073 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5074 igu_sb_id, igu_seg_id); 5074 igu_sb_id, igu_seg_id);
5075 5075
5076 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); 5076 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
5077 5077
5078 /* write indecies to HW */ 5078 /* write indecies to HW */
5079 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5079 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5080 } 5080 }
5081 5081
5082 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 5082 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5083 u16 tx_usec, u16 rx_usec) 5083 u16 tx_usec, u16 rx_usec)
5084 { 5084 {
5085 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 5085 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5086 false, rx_usec); 5086 false, rx_usec);
5087 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5087 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5088 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 5088 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5089 tx_usec); 5089 tx_usec);
5090 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5090 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5091 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 5091 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5092 tx_usec); 5092 tx_usec);
5093 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5093 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5094 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 5094 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5095 tx_usec); 5095 tx_usec);
5096 } 5096 }
5097 5097
5098 static void bnx2x_init_def_sb(struct bnx2x *bp) 5098 static void bnx2x_init_def_sb(struct bnx2x *bp)
5099 { 5099 {
5100 struct host_sp_status_block *def_sb = bp->def_status_blk; 5100 struct host_sp_status_block *def_sb = bp->def_status_blk;
5101 dma_addr_t mapping = bp->def_status_blk_mapping; 5101 dma_addr_t mapping = bp->def_status_blk_mapping;
5102 int igu_sp_sb_index; 5102 int igu_sp_sb_index;
5103 int igu_seg_id; 5103 int igu_seg_id;
5104 int port = BP_PORT(bp); 5104 int port = BP_PORT(bp);
5105 int func = BP_FUNC(bp); 5105 int func = BP_FUNC(bp);
5106 int reg_offset, reg_offset_en5; 5106 int reg_offset, reg_offset_en5;
5107 u64 section; 5107 u64 section;
5108 int index; 5108 int index;
5109 struct hc_sp_status_block_data sp_sb_data; 5109 struct hc_sp_status_block_data sp_sb_data;
5110 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5110 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5111 5111
5112 if (CHIP_INT_MODE_IS_BC(bp)) { 5112 if (CHIP_INT_MODE_IS_BC(bp)) {
5113 igu_sp_sb_index = DEF_SB_IGU_ID; 5113 igu_sp_sb_index = DEF_SB_IGU_ID;
5114 igu_seg_id = HC_SEG_ACCESS_DEF; 5114 igu_seg_id = HC_SEG_ACCESS_DEF;
5115 } else { 5115 } else {
5116 igu_sp_sb_index = bp->igu_dsb_id; 5116 igu_sp_sb_index = bp->igu_dsb_id;
5117 igu_seg_id = IGU_SEG_ACCESS_DEF; 5117 igu_seg_id = IGU_SEG_ACCESS_DEF;
5118 } 5118 }
5119 5119
5120 /* ATTN */ 5120 /* ATTN */
5121 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5121 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5122 atten_status_block); 5122 atten_status_block);
5123 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 5123 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5124 5124
5125 bp->attn_state = 0; 5125 bp->attn_state = 0;
5126 5126
5127 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5127 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5128 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5128 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5129 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 5129 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5130 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 5130 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5131 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5131 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5132 int sindex; 5132 int sindex;
5133 /* take care of sig[0]..sig[4] */ 5133 /* take care of sig[0]..sig[4] */
5134 for (sindex = 0; sindex < 4; sindex++) 5134 for (sindex = 0; sindex < 4; sindex++)
5135 bp->attn_group[index].sig[sindex] = 5135 bp->attn_group[index].sig[sindex] =
5136 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 5136 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5137 5137
5138 if (!CHIP_IS_E1x(bp)) 5138 if (!CHIP_IS_E1x(bp))
5139 /* 5139 /*
5140 * enable5 is separate from the rest of the registers, 5140 * enable5 is separate from the rest of the registers,
5141 * and therefore the address skip is 4 5141 * and therefore the address skip is 4
5142 * and not 16 between the different groups 5142 * and not 16 between the different groups
5143 */ 5143 */
5144 bp->attn_group[index].sig[4] = REG_RD(bp, 5144 bp->attn_group[index].sig[4] = REG_RD(bp,
5145 reg_offset_en5 + 0x4*index); 5145 reg_offset_en5 + 0x4*index);
5146 else 5146 else
5147 bp->attn_group[index].sig[4] = 0; 5147 bp->attn_group[index].sig[4] = 0;
5148 } 5148 }
5149 5149
5150 if (bp->common.int_block == INT_BLOCK_HC) { 5150 if (bp->common.int_block == INT_BLOCK_HC) {
5151 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 5151 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5152 HC_REG_ATTN_MSG0_ADDR_L); 5152 HC_REG_ATTN_MSG0_ADDR_L);
5153 5153
5154 REG_WR(bp, reg_offset, U64_LO(section)); 5154 REG_WR(bp, reg_offset, U64_LO(section));
5155 REG_WR(bp, reg_offset + 4, U64_HI(section)); 5155 REG_WR(bp, reg_offset + 4, U64_HI(section));
5156 } else if (!CHIP_IS_E1x(bp)) { 5156 } else if (!CHIP_IS_E1x(bp)) {
5157 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 5157 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5158 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 5158 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5159 } 5159 }
5160 5160
5161 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5161 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5162 sp_sb); 5162 sp_sb);
5163 5163
5164 bnx2x_zero_sp_sb(bp); 5164 bnx2x_zero_sp_sb(bp);
5165 5165
5166 sp_sb_data.state = SB_ENABLED; 5166 sp_sb_data.state = SB_ENABLED;
5167 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5167 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5168 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5168 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5169 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5169 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5170 sp_sb_data.igu_seg_id = igu_seg_id; 5170 sp_sb_data.igu_seg_id = igu_seg_id;
5171 sp_sb_data.p_func.pf_id = func; 5171 sp_sb_data.p_func.pf_id = func;
5172 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5172 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5173 sp_sb_data.p_func.vf_id = 0xff; 5173 sp_sb_data.p_func.vf_id = 0xff;
5174 5174
5175 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5175 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5176 5176
5177 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5177 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5178 } 5178 }
5179 5179
5180 void bnx2x_update_coalesce(struct bnx2x *bp) 5180 void bnx2x_update_coalesce(struct bnx2x *bp)
5181 { 5181 {
5182 int i; 5182 int i;
5183 5183
5184 for_each_eth_queue(bp, i) 5184 for_each_eth_queue(bp, i)
5185 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5185 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5186 bp->tx_ticks, bp->rx_ticks); 5186 bp->tx_ticks, bp->rx_ticks);
5187 } 5187 }
5188 5188
5189 static void bnx2x_init_sp_ring(struct bnx2x *bp) 5189 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5190 { 5190 {
5191 spin_lock_init(&bp->spq_lock); 5191 spin_lock_init(&bp->spq_lock);
5192 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5192 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5193 5193
5194 bp->spq_prod_idx = 0; 5194 bp->spq_prod_idx = 0;
5195 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5195 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5196 bp->spq_prod_bd = bp->spq; 5196 bp->spq_prod_bd = bp->spq;
5197 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5197 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5198 } 5198 }
5199 5199
5200 static void bnx2x_init_eq_ring(struct bnx2x *bp) 5200 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5201 { 5201 {
5202 int i; 5202 int i;
5203 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5203 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5204 union event_ring_elem *elem = 5204 union event_ring_elem *elem =
5205 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5205 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5206 5206
5207 elem->next_page.addr.hi = 5207 elem->next_page.addr.hi =
5208 cpu_to_le32(U64_HI(bp->eq_mapping + 5208 cpu_to_le32(U64_HI(bp->eq_mapping +
5209 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5209 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5210 elem->next_page.addr.lo = 5210 elem->next_page.addr.lo =
5211 cpu_to_le32(U64_LO(bp->eq_mapping + 5211 cpu_to_le32(U64_LO(bp->eq_mapping +
5212 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5212 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5213 } 5213 }
5214 bp->eq_cons = 0; 5214 bp->eq_cons = 0;
5215 bp->eq_prod = NUM_EQ_DESC; 5215 bp->eq_prod = NUM_EQ_DESC;
5216 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5216 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5217 /* we want a warning message before it gets rought... */ 5217 /* we want a warning message before it gets rought... */
5218 atomic_set(&bp->eq_spq_left, 5218 atomic_set(&bp->eq_spq_left,
5219 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5219 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5220 } 5220 }
5221 5221
5222 5222
5223 /* called with netif_addr_lock_bh() */ 5223 /* called with netif_addr_lock_bh() */
5224 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5224 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5225 unsigned long rx_mode_flags, 5225 unsigned long rx_mode_flags,
5226 unsigned long rx_accept_flags, 5226 unsigned long rx_accept_flags,
5227 unsigned long tx_accept_flags, 5227 unsigned long tx_accept_flags,
5228 unsigned long ramrod_flags) 5228 unsigned long ramrod_flags)
5229 { 5229 {
5230 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5230 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5231 int rc; 5231 int rc;
5232 5232
5233 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5233 memset(&ramrod_param, 0, sizeof(ramrod_param));
5234 5234
5235 /* Prepare ramrod parameters */ 5235 /* Prepare ramrod parameters */
5236 ramrod_param.cid = 0; 5236 ramrod_param.cid = 0;
5237 ramrod_param.cl_id = cl_id; 5237 ramrod_param.cl_id = cl_id;
5238 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5238 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5239 ramrod_param.func_id = BP_FUNC(bp); 5239 ramrod_param.func_id = BP_FUNC(bp);
5240 5240
5241 ramrod_param.pstate = &bp->sp_state; 5241 ramrod_param.pstate = &bp->sp_state;
5242 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5242 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5243 5243
5244 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5244 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5245 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5245 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5246 5246
5247 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5247 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5248 5248
5249 ramrod_param.ramrod_flags = ramrod_flags; 5249 ramrod_param.ramrod_flags = ramrod_flags;
5250 ramrod_param.rx_mode_flags = rx_mode_flags; 5250 ramrod_param.rx_mode_flags = rx_mode_flags;
5251 5251
5252 ramrod_param.rx_accept_flags = rx_accept_flags; 5252 ramrod_param.rx_accept_flags = rx_accept_flags;
5253 ramrod_param.tx_accept_flags = tx_accept_flags; 5253 ramrod_param.tx_accept_flags = tx_accept_flags;
5254 5254
5255 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5255 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5256 if (rc < 0) { 5256 if (rc < 0) {
5257 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5257 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5258 return; 5258 return;
5259 } 5259 }
5260 } 5260 }
5261 5261
5262 /* called with netif_addr_lock_bh() */ 5262 /* called with netif_addr_lock_bh() */
5263 void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5263 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5264 { 5264 {
5265 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5265 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5266 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5266 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5267 5267
5268 #ifdef BCM_CNIC 5268 #ifdef BCM_CNIC
5269 if (!NO_FCOE(bp)) 5269 if (!NO_FCOE(bp))
5270 5270
5271 /* Configure rx_mode of FCoE Queue */ 5271 /* Configure rx_mode of FCoE Queue */
5272 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5272 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5273 #endif 5273 #endif
5274 5274
5275 switch (bp->rx_mode) { 5275 switch (bp->rx_mode) {
5276 case BNX2X_RX_MODE_NONE: 5276 case BNX2X_RX_MODE_NONE:
5277 /* 5277 /*
5278 * 'drop all' supersedes any accept flags that may have been 5278 * 'drop all' supersedes any accept flags that may have been
5279 * passed to the function. 5279 * passed to the function.
5280 */ 5280 */
5281 break; 5281 break;
5282 case BNX2X_RX_MODE_NORMAL: 5282 case BNX2X_RX_MODE_NORMAL:
5283 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5283 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5284 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5284 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5285 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5285 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5286 5286
5287 /* internal switching mode */ 5287 /* internal switching mode */
5288 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5288 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5289 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5289 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5290 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5290 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5291 5291
5292 break; 5292 break;
5293 case BNX2X_RX_MODE_ALLMULTI: 5293 case BNX2X_RX_MODE_ALLMULTI:
5294 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5294 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5295 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5295 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5296 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5296 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5297 5297
5298 /* internal switching mode */ 5298 /* internal switching mode */
5299 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5299 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5300 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5300 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5301 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5301 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5302 5302
5303 break; 5303 break;
5304 case BNX2X_RX_MODE_PROMISC: 5304 case BNX2X_RX_MODE_PROMISC:
5305 /* According to deffinition of SI mode, iface in promisc mode 5305 /* According to deffinition of SI mode, iface in promisc mode
5306 * should receive matched and unmatched (in resolution of port) 5306 * should receive matched and unmatched (in resolution of port)
5307 * unicast packets. 5307 * unicast packets.
5308 */ 5308 */
5309 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5309 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5310 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5310 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5311 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5311 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5312 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5312 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5313 5313
5314 /* internal switching mode */ 5314 /* internal switching mode */
5315 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5315 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5316 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5316 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5317 5317
5318 if (IS_MF_SI(bp)) 5318 if (IS_MF_SI(bp))
5319 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5319 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5320 else 5320 else
5321 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5321 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5322 5322
5323 break; 5323 break;
5324 default: 5324 default:
5325 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5325 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5326 return; 5326 return;
5327 } 5327 }
5328 5328
5329 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5329 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5330 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5330 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5331 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5331 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5332 } 5332 }
5333 5333
5334 __set_bit(RAMROD_RX, &ramrod_flags); 5334 __set_bit(RAMROD_RX, &ramrod_flags);
5335 __set_bit(RAMROD_TX, &ramrod_flags); 5335 __set_bit(RAMROD_TX, &ramrod_flags);
5336 5336
5337 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5337 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5338 tx_accept_flags, ramrod_flags); 5338 tx_accept_flags, ramrod_flags);
5339 } 5339 }
5340 5340
5341 static void bnx2x_init_internal_common(struct bnx2x *bp) 5341 static void bnx2x_init_internal_common(struct bnx2x *bp)
5342 { 5342 {
5343 int i; 5343 int i;
5344 5344
5345 if (IS_MF_SI(bp)) 5345 if (IS_MF_SI(bp))
5346 /* 5346 /*
5347 * In switch independent mode, the TSTORM needs to accept 5347 * In switch independent mode, the TSTORM needs to accept
5348 * packets that failed classification, since approximate match 5348 * packets that failed classification, since approximate match
5349 * mac addresses aren't written to NIG LLH 5349 * mac addresses aren't written to NIG LLH
5350 */ 5350 */
5351 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5351 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5352 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5352 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5353 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5353 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5354 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5354 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5355 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5355 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5356 5356
5357 /* Zero this manually as its initialization is 5357 /* Zero this manually as its initialization is
5358 currently missing in the initTool */ 5358 currently missing in the initTool */
5359 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5359 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5360 REG_WR(bp, BAR_USTRORM_INTMEM + 5360 REG_WR(bp, BAR_USTRORM_INTMEM +
5361 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5361 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5362 if (!CHIP_IS_E1x(bp)) { 5362 if (!CHIP_IS_E1x(bp)) {
5363 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5363 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5364 CHIP_INT_MODE_IS_BC(bp) ? 5364 CHIP_INT_MODE_IS_BC(bp) ?
5365 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5365 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5366 } 5366 }
5367 } 5367 }
5368 5368
5369 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5369 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5370 { 5370 {
5371 switch (load_code) { 5371 switch (load_code) {
5372 case FW_MSG_CODE_DRV_LOAD_COMMON: 5372 case FW_MSG_CODE_DRV_LOAD_COMMON:
5373 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5373 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5374 bnx2x_init_internal_common(bp); 5374 bnx2x_init_internal_common(bp);
5375 /* no break */ 5375 /* no break */
5376 5376
5377 case FW_MSG_CODE_DRV_LOAD_PORT: 5377 case FW_MSG_CODE_DRV_LOAD_PORT:
5378 /* nothing to do */ 5378 /* nothing to do */
5379 /* no break */ 5379 /* no break */
5380 5380
5381 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5381 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5382 /* internal memory per function is 5382 /* internal memory per function is
5383 initialized inside bnx2x_pf_init */ 5383 initialized inside bnx2x_pf_init */
5384 break; 5384 break;
5385 5385
5386 default: 5386 default:
5387 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5387 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5388 break; 5388 break;
5389 } 5389 }
5390 } 5390 }
5391 5391
5392 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5392 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5393 { 5393 {
5394 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; 5394 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5395 } 5395 }
5396 5396
5397 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5397 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5398 { 5398 {
5399 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; 5399 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5400 } 5400 }
5401 5401
5402 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5402 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5403 { 5403 {
5404 if (CHIP_IS_E1x(fp->bp)) 5404 if (CHIP_IS_E1x(fp->bp))
5405 return BP_L_ID(fp->bp) + fp->index; 5405 return BP_L_ID(fp->bp) + fp->index;
5406 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5406 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5407 return bnx2x_fp_igu_sb_id(fp); 5407 return bnx2x_fp_igu_sb_id(fp);
5408 } 5408 }
5409 5409
5410 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5410 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5411 { 5411 {
5412 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5412 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5413 u8 cos; 5413 u8 cos;
5414 unsigned long q_type = 0; 5414 unsigned long q_type = 0;
5415 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5415 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5416 fp->rx_queue = fp_idx; 5416 fp->rx_queue = fp_idx;
5417 fp->cid = fp_idx; 5417 fp->cid = fp_idx;
5418 fp->cl_id = bnx2x_fp_cl_id(fp); 5418 fp->cl_id = bnx2x_fp_cl_id(fp);
5419 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5419 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5420 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5420 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5421 /* qZone id equals to FW (per path) client id */ 5421 /* qZone id equals to FW (per path) client id */
5422 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5422 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5423 5423
5424 /* init shortcut */ 5424 /* init shortcut */
5425 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5425 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5426 /* Setup SB indicies */ 5426 /* Setup SB indicies */
5427 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5427 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5428 5428
5429 /* Configure Queue State object */ 5429 /* Configure Queue State object */
5430 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5430 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5431 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5431 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5432 5432
5433 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5433 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5434 5434
5435 /* init tx data */ 5435 /* init tx data */
5436 for_each_cos_in_tx_queue(fp, cos) { 5436 for_each_cos_in_tx_queue(fp, cos) {
5437 bnx2x_init_txdata(bp, &fp->txdata[cos], 5437 bnx2x_init_txdata(bp, &fp->txdata[cos],
5438 CID_COS_TO_TX_ONLY_CID(fp->cid, cos), 5438 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5439 FP_COS_TO_TXQ(fp, cos), 5439 FP_COS_TO_TXQ(fp, cos),
5440 BNX2X_TX_SB_INDEX_BASE + cos); 5440 BNX2X_TX_SB_INDEX_BASE + cos);
5441 cids[cos] = fp->txdata[cos].cid; 5441 cids[cos] = fp->txdata[cos].cid;
5442 } 5442 }
5443 5443
5444 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, 5444 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5445 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5445 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5446 bnx2x_sp_mapping(bp, q_rdata), q_type); 5446 bnx2x_sp_mapping(bp, q_rdata), q_type);
5447 5447
5448 /** 5448 /**
5449 * Configure classification DBs: Always enable Tx switching 5449 * Configure classification DBs: Always enable Tx switching
5450 */ 5450 */
5451 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5451 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5452 5452
5453 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " 5453 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5454 "cl_id %d fw_sb %d igu_sb %d\n", 5454 "cl_id %d fw_sb %d igu_sb %d\n",
5455 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5455 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5456 fp->igu_sb_id); 5456 fp->igu_sb_id);
5457 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5457 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5458 fp->fw_sb_id, fp->igu_sb_id); 5458 fp->fw_sb_id, fp->igu_sb_id);
5459 5459
5460 bnx2x_update_fpsb_idx(fp); 5460 bnx2x_update_fpsb_idx(fp);
5461 } 5461 }
5462 5462
5463 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5463 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5464 { 5464 {
5465 int i; 5465 int i;
5466 5466
5467 for_each_eth_queue(bp, i) 5467 for_each_eth_queue(bp, i)
5468 bnx2x_init_eth_fp(bp, i); 5468 bnx2x_init_eth_fp(bp, i);
5469 #ifdef BCM_CNIC 5469 #ifdef BCM_CNIC
5470 if (!NO_FCOE(bp)) 5470 if (!NO_FCOE(bp))
5471 bnx2x_init_fcoe_fp(bp); 5471 bnx2x_init_fcoe_fp(bp);
5472 5472
5473 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5473 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5474 BNX2X_VF_ID_INVALID, false, 5474 BNX2X_VF_ID_INVALID, false,
5475 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5475 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5476 5476
5477 #endif 5477 #endif
5478 5478
5479 /* Initialize MOD_ABS interrupts */ 5479 /* Initialize MOD_ABS interrupts */
5480 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5480 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5481 bp->common.shmem_base, bp->common.shmem2_base, 5481 bp->common.shmem_base, bp->common.shmem2_base,
5482 BP_PORT(bp)); 5482 BP_PORT(bp));
5483 /* ensure status block indices were read */ 5483 /* ensure status block indices were read */
5484 rmb(); 5484 rmb();
5485 5485
5486 bnx2x_init_def_sb(bp); 5486 bnx2x_init_def_sb(bp);
5487 bnx2x_update_dsb_idx(bp); 5487 bnx2x_update_dsb_idx(bp);
5488 bnx2x_init_rx_rings(bp); 5488 bnx2x_init_rx_rings(bp);
5489 bnx2x_init_tx_rings(bp); 5489 bnx2x_init_tx_rings(bp);
5490 bnx2x_init_sp_ring(bp); 5490 bnx2x_init_sp_ring(bp);
5491 bnx2x_init_eq_ring(bp); 5491 bnx2x_init_eq_ring(bp);
5492 bnx2x_init_internal(bp, load_code); 5492 bnx2x_init_internal(bp, load_code);
5493 bnx2x_pf_init(bp); 5493 bnx2x_pf_init(bp);
5494 bnx2x_stats_init(bp); 5494 bnx2x_stats_init(bp);
5495 5495
5496 /* flush all before enabling interrupts */ 5496 /* flush all before enabling interrupts */
5497 mb(); 5497 mb();
5498 mmiowb(); 5498 mmiowb();
5499 5499
5500 bnx2x_int_enable(bp); 5500 bnx2x_int_enable(bp);
5501 5501
5502 /* Check for SPIO5 */ 5502 /* Check for SPIO5 */
5503 bnx2x_attn_int_deasserted0(bp, 5503 bnx2x_attn_int_deasserted0(bp,
5504 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5504 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5505 AEU_INPUTS_ATTN_BITS_SPIO5); 5505 AEU_INPUTS_ATTN_BITS_SPIO5);
5506 } 5506 }
5507 5507
5508 /* end of nic init */ 5508 /* end of nic init */
5509 5509
5510 /* 5510 /*
5511 * gzip service functions 5511 * gzip service functions
5512 */ 5512 */
5513 5513
5514 static int bnx2x_gunzip_init(struct bnx2x *bp) 5514 static int bnx2x_gunzip_init(struct bnx2x *bp)
5515 { 5515 {
5516 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 5516 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5517 &bp->gunzip_mapping, GFP_KERNEL); 5517 &bp->gunzip_mapping, GFP_KERNEL);
5518 if (bp->gunzip_buf == NULL) 5518 if (bp->gunzip_buf == NULL)
5519 goto gunzip_nomem1; 5519 goto gunzip_nomem1;
5520 5520
5521 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 5521 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5522 if (bp->strm == NULL) 5522 if (bp->strm == NULL)
5523 goto gunzip_nomem2; 5523 goto gunzip_nomem2;
5524 5524
5525 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 5525 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5526 if (bp->strm->workspace == NULL) 5526 if (bp->strm->workspace == NULL)
5527 goto gunzip_nomem3; 5527 goto gunzip_nomem3;
5528 5528
5529 return 0; 5529 return 0;
5530 5530
5531 gunzip_nomem3: 5531 gunzip_nomem3:
5532 kfree(bp->strm); 5532 kfree(bp->strm);
5533 bp->strm = NULL; 5533 bp->strm = NULL;
5534 5534
5535 gunzip_nomem2: 5535 gunzip_nomem2:
5536 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5536 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5537 bp->gunzip_mapping); 5537 bp->gunzip_mapping);
5538 bp->gunzip_buf = NULL; 5538 bp->gunzip_buf = NULL;
5539 5539
5540 gunzip_nomem1: 5540 gunzip_nomem1:
5541 netdev_err(bp->dev, "Cannot allocate firmware buffer for" 5541 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5542 " un-compression\n"); 5542 " un-compression\n");
5543 return -ENOMEM; 5543 return -ENOMEM;
5544 } 5544 }
5545 5545
5546 static void bnx2x_gunzip_end(struct bnx2x *bp) 5546 static void bnx2x_gunzip_end(struct bnx2x *bp)
5547 { 5547 {
5548 if (bp->strm) { 5548 if (bp->strm) {
5549 vfree(bp->strm->workspace); 5549 vfree(bp->strm->workspace);
5550 kfree(bp->strm); 5550 kfree(bp->strm);
5551 bp->strm = NULL; 5551 bp->strm = NULL;
5552 } 5552 }
5553 5553
5554 if (bp->gunzip_buf) { 5554 if (bp->gunzip_buf) {
5555 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5555 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5556 bp->gunzip_mapping); 5556 bp->gunzip_mapping);
5557 bp->gunzip_buf = NULL; 5557 bp->gunzip_buf = NULL;
5558 } 5558 }
5559 } 5559 }
5560 5560
5561 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 5561 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5562 { 5562 {
5563 int n, rc; 5563 int n, rc;
5564 5564
5565 /* check gzip header */ 5565 /* check gzip header */
5566 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 5566 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5567 BNX2X_ERR("Bad gzip header\n"); 5567 BNX2X_ERR("Bad gzip header\n");
5568 return -EINVAL; 5568 return -EINVAL;
5569 } 5569 }
5570 5570
5571 n = 10; 5571 n = 10;
5572 5572
5573 #define FNAME 0x8 5573 #define FNAME 0x8
5574 5574
5575 if (zbuf[3] & FNAME) 5575 if (zbuf[3] & FNAME)
5576 while ((zbuf[n++] != 0) && (n < len)); 5576 while ((zbuf[n++] != 0) && (n < len));
5577 5577
5578 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 5578 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5579 bp->strm->avail_in = len - n; 5579 bp->strm->avail_in = len - n;
5580 bp->strm->next_out = bp->gunzip_buf; 5580 bp->strm->next_out = bp->gunzip_buf;
5581 bp->strm->avail_out = FW_BUF_SIZE; 5581 bp->strm->avail_out = FW_BUF_SIZE;
5582 5582
5583 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 5583 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5584 if (rc != Z_OK) 5584 if (rc != Z_OK)
5585 return rc; 5585 return rc;
5586 5586
5587 rc = zlib_inflate(bp->strm, Z_FINISH); 5587 rc = zlib_inflate(bp->strm, Z_FINISH);
5588 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 5588 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5589 netdev_err(bp->dev, "Firmware decompression error: %s\n", 5589 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5590 bp->strm->msg); 5590 bp->strm->msg);
5591 5591
5592 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5592 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5593 if (bp->gunzip_outlen & 0x3) 5593 if (bp->gunzip_outlen & 0x3)
5594 netdev_err(bp->dev, "Firmware decompression error:" 5594 netdev_err(bp->dev, "Firmware decompression error:"
5595 " gunzip_outlen (%d) not aligned\n", 5595 " gunzip_outlen (%d) not aligned\n",
5596 bp->gunzip_outlen); 5596 bp->gunzip_outlen);
5597 bp->gunzip_outlen >>= 2; 5597 bp->gunzip_outlen >>= 2;
5598 5598
5599 zlib_inflateEnd(bp->strm); 5599 zlib_inflateEnd(bp->strm);
5600 5600
5601 if (rc == Z_STREAM_END) 5601 if (rc == Z_STREAM_END)
5602 return 0; 5602 return 0;
5603 5603
5604 return rc; 5604 return rc;
5605 } 5605 }
5606 5606
5607 /* nic load/unload */ 5607 /* nic load/unload */
5608 5608
5609 /* 5609 /*
5610 * General service functions 5610 * General service functions
5611 */ 5611 */
5612 5612
5613 /* send a NIG loopback debug packet */ 5613 /* send a NIG loopback debug packet */
5614 static void bnx2x_lb_pckt(struct bnx2x *bp) 5614 static void bnx2x_lb_pckt(struct bnx2x *bp)
5615 { 5615 {
5616 u32 wb_write[3]; 5616 u32 wb_write[3];
5617 5617
5618 /* Ethernet source and destination addresses */ 5618 /* Ethernet source and destination addresses */
5619 wb_write[0] = 0x55555555; 5619 wb_write[0] = 0x55555555;
5620 wb_write[1] = 0x55555555; 5620 wb_write[1] = 0x55555555;
5621 wb_write[2] = 0x20; /* SOP */ 5621 wb_write[2] = 0x20; /* SOP */
5622 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5622 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5623 5623
5624 /* NON-IP protocol */ 5624 /* NON-IP protocol */
5625 wb_write[0] = 0x09000000; 5625 wb_write[0] = 0x09000000;
5626 wb_write[1] = 0x55555555; 5626 wb_write[1] = 0x55555555;
5627 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 5627 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5628 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5628 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5629 } 5629 }
5630 5630
5631 /* some of the internal memories 5631 /* some of the internal memories
5632 * are not directly readable from the driver 5632 * are not directly readable from the driver
5633 * to test them we send debug packets 5633 * to test them we send debug packets
5634 */ 5634 */
5635 static int bnx2x_int_mem_test(struct bnx2x *bp) 5635 static int bnx2x_int_mem_test(struct bnx2x *bp)
5636 { 5636 {
5637 int factor; 5637 int factor;
5638 int count, i; 5638 int count, i;
5639 u32 val = 0; 5639 u32 val = 0;
5640 5640
5641 if (CHIP_REV_IS_FPGA(bp)) 5641 if (CHIP_REV_IS_FPGA(bp))
5642 factor = 120; 5642 factor = 120;
5643 else if (CHIP_REV_IS_EMUL(bp)) 5643 else if (CHIP_REV_IS_EMUL(bp))
5644 factor = 200; 5644 factor = 200;
5645 else 5645 else
5646 factor = 1; 5646 factor = 1;
5647 5647
5648 /* Disable inputs of parser neighbor blocks */ 5648 /* Disable inputs of parser neighbor blocks */
5649 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5649 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5650 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5650 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5651 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5651 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5652 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5652 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5653 5653
5654 /* Write 0 to parser credits for CFC search request */ 5654 /* Write 0 to parser credits for CFC search request */
5655 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5655 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5656 5656
5657 /* send Ethernet packet */ 5657 /* send Ethernet packet */
5658 bnx2x_lb_pckt(bp); 5658 bnx2x_lb_pckt(bp);
5659 5659
5660 /* TODO do i reset NIG statistic? */ 5660 /* TODO do i reset NIG statistic? */
5661 /* Wait until NIG register shows 1 packet of size 0x10 */ 5661 /* Wait until NIG register shows 1 packet of size 0x10 */
5662 count = 1000 * factor; 5662 count = 1000 * factor;
5663 while (count) { 5663 while (count) {
5664 5664
5665 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5665 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5666 val = *bnx2x_sp(bp, wb_data[0]); 5666 val = *bnx2x_sp(bp, wb_data[0]);
5667 if (val == 0x10) 5667 if (val == 0x10)
5668 break; 5668 break;
5669 5669
5670 msleep(10); 5670 msleep(10);
5671 count--; 5671 count--;
5672 } 5672 }
5673 if (val != 0x10) { 5673 if (val != 0x10) {
5674 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5674 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5675 return -1; 5675 return -1;
5676 } 5676 }
5677 5677
5678 /* Wait until PRS register shows 1 packet */ 5678 /* Wait until PRS register shows 1 packet */
5679 count = 1000 * factor; 5679 count = 1000 * factor;
5680 while (count) { 5680 while (count) {
5681 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5681 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5682 if (val == 1) 5682 if (val == 1)
5683 break; 5683 break;
5684 5684
5685 msleep(10); 5685 msleep(10);
5686 count--; 5686 count--;
5687 } 5687 }
5688 if (val != 0x1) { 5688 if (val != 0x1) {
5689 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5689 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5690 return -2; 5690 return -2;
5691 } 5691 }
5692 5692
5693 /* Reset and init BRB, PRS */ 5693 /* Reset and init BRB, PRS */
5694 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5694 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5695 msleep(50); 5695 msleep(50);
5696 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5696 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5697 msleep(50); 5697 msleep(50);
5698 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5698 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5699 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5699 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5700 5700
5701 DP(NETIF_MSG_HW, "part2\n"); 5701 DP(NETIF_MSG_HW, "part2\n");
5702 5702
5703 /* Disable inputs of parser neighbor blocks */ 5703 /* Disable inputs of parser neighbor blocks */
5704 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5704 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5705 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5705 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5706 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5706 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5707 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5707 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5708 5708
5709 /* Write 0 to parser credits for CFC search request */ 5709 /* Write 0 to parser credits for CFC search request */
5710 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5710 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5711 5711
5712 /* send 10 Ethernet packets */ 5712 /* send 10 Ethernet packets */
5713 for (i = 0; i < 10; i++) 5713 for (i = 0; i < 10; i++)
5714 bnx2x_lb_pckt(bp); 5714 bnx2x_lb_pckt(bp);
5715 5715
5716 /* Wait until NIG register shows 10 + 1 5716 /* Wait until NIG register shows 10 + 1
5717 packets of size 11*0x10 = 0xb0 */ 5717 packets of size 11*0x10 = 0xb0 */
5718 count = 1000 * factor; 5718 count = 1000 * factor;
5719 while (count) { 5719 while (count) {
5720 5720
5721 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5721 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5722 val = *bnx2x_sp(bp, wb_data[0]); 5722 val = *bnx2x_sp(bp, wb_data[0]);
5723 if (val == 0xb0) 5723 if (val == 0xb0)
5724 break; 5724 break;
5725 5725
5726 msleep(10); 5726 msleep(10);
5727 count--; 5727 count--;
5728 } 5728 }
5729 if (val != 0xb0) { 5729 if (val != 0xb0) {
5730 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5730 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5731 return -3; 5731 return -3;
5732 } 5732 }
5733 5733
5734 /* Wait until PRS register shows 2 packets */ 5734 /* Wait until PRS register shows 2 packets */
5735 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5735 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5736 if (val != 2) 5736 if (val != 2)
5737 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5737 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5738 5738
5739 /* Write 1 to parser credits for CFC search request */ 5739 /* Write 1 to parser credits for CFC search request */
5740 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 5740 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5741 5741
5742 /* Wait until PRS register shows 3 packets */ 5742 /* Wait until PRS register shows 3 packets */
5743 msleep(10 * factor); 5743 msleep(10 * factor);
5744 /* Wait until NIG register shows 1 packet of size 0x10 */ 5744 /* Wait until NIG register shows 1 packet of size 0x10 */
5745 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5745 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5746 if (val != 3) 5746 if (val != 3)
5747 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5747 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5748 5748
5749 /* clear NIG EOP FIFO */ 5749 /* clear NIG EOP FIFO */
5750 for (i = 0; i < 11; i++) 5750 for (i = 0; i < 11; i++)
5751 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 5751 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5752 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 5752 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5753 if (val != 1) { 5753 if (val != 1) {
5754 BNX2X_ERR("clear of NIG failed\n"); 5754 BNX2X_ERR("clear of NIG failed\n");
5755 return -4; 5755 return -4;
5756 } 5756 }
5757 5757
5758 /* Reset and init BRB, PRS, NIG */ 5758 /* Reset and init BRB, PRS, NIG */
5759 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5759 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5760 msleep(50); 5760 msleep(50);
5761 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5761 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5762 msleep(50); 5762 msleep(50);
5763 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5763 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5764 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5764 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5765 #ifndef BCM_CNIC 5765 #ifndef BCM_CNIC
5766 /* set NIC mode */ 5766 /* set NIC mode */
5767 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5767 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5768 #endif 5768 #endif
5769 5769
5770 /* Enable inputs of parser neighbor blocks */ 5770 /* Enable inputs of parser neighbor blocks */
5771 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5771 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5772 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5772 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5773 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5773 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5774 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 5774 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5775 5775
5776 DP(NETIF_MSG_HW, "done\n"); 5776 DP(NETIF_MSG_HW, "done\n");
5777 5777
5778 return 0; /* OK */ 5778 return 0; /* OK */
5779 } 5779 }
5780 5780
5781 static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 5781 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5782 { 5782 {
5783 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5783 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5784 if (!CHIP_IS_E1x(bp)) 5784 if (!CHIP_IS_E1x(bp))
5785 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 5785 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5786 else 5786 else
5787 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 5787 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5788 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5788 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5789 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 5789 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5790 /* 5790 /*
5791 * mask read length error interrupts in brb for parser 5791 * mask read length error interrupts in brb for parser
5792 * (parsing unit and 'checksum and crc' unit) 5792 * (parsing unit and 'checksum and crc' unit)
5793 * these errors are legal (PU reads fixed length and CAC can cause 5793 * these errors are legal (PU reads fixed length and CAC can cause
5794 * read length error on truncated packets) 5794 * read length error on truncated packets)
5795 */ 5795 */
5796 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 5796 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5797 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 5797 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5798 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 5798 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5799 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 5799 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5800 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 5800 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5801 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 5801 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5802 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 5802 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5803 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 5803 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5804 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 5804 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5805 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 5805 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5806 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 5806 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5807 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 5807 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5808 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 5808 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5809 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 5809 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5810 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 5810 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5811 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 5811 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5812 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 5812 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5813 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 5813 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5814 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 5814 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5815 5815
5816 if (CHIP_REV_IS_FPGA(bp)) 5816 if (CHIP_REV_IS_FPGA(bp))
5817 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 5817 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5818 else if (!CHIP_IS_E1x(bp)) 5818 else if (!CHIP_IS_E1x(bp))
5819 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 5819 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5820 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF 5820 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5821 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT 5821 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5822 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN 5822 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5823 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED 5823 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5824 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); 5824 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5825 else 5825 else
5826 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 5826 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5827 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 5827 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5828 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 5828 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5829 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 5829 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5830 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 5830 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5831 5831
5832 if (!CHIP_IS_E1x(bp)) 5832 if (!CHIP_IS_E1x(bp))
5833 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 5833 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5834 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 5834 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5835 5835
5836 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 5836 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5837 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 5837 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5838 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 5838 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5839 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 5839 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5840 } 5840 }
5841 5841
5842 static void bnx2x_reset_common(struct bnx2x *bp) 5842 static void bnx2x_reset_common(struct bnx2x *bp)
5843 { 5843 {
5844 u32 val = 0x1400; 5844 u32 val = 0x1400;
5845 5845
5846 /* reset_common */ 5846 /* reset_common */
5847 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5847 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5848 0xd3ffff7f); 5848 0xd3ffff7f);
5849 5849
5850 if (CHIP_IS_E3(bp)) { 5850 if (CHIP_IS_E3(bp)) {
5851 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5851 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5852 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5852 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5853 } 5853 }
5854 5854
5855 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 5855 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5856 } 5856 }
5857 5857
5858 static void bnx2x_setup_dmae(struct bnx2x *bp) 5858 static void bnx2x_setup_dmae(struct bnx2x *bp)
5859 { 5859 {
5860 bp->dmae_ready = 0; 5860 bp->dmae_ready = 0;
5861 spin_lock_init(&bp->dmae_lock); 5861 spin_lock_init(&bp->dmae_lock);
5862 } 5862 }
5863 5863
5864 static void bnx2x_init_pxp(struct bnx2x *bp) 5864 static void bnx2x_init_pxp(struct bnx2x *bp)
5865 { 5865 {
5866 u16 devctl; 5866 u16 devctl;
5867 int r_order, w_order; 5867 int r_order, w_order;
5868 5868
5869 pci_read_config_word(bp->pdev, 5869 pci_read_config_word(bp->pdev,
5870 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); 5870 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
5871 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 5871 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5872 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 5872 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5873 if (bp->mrrs == -1) 5873 if (bp->mrrs == -1)
5874 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 5874 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5875 else { 5875 else {
5876 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 5876 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5877 r_order = bp->mrrs; 5877 r_order = bp->mrrs;
5878 } 5878 }
5879 5879
5880 bnx2x_init_pxp_arb(bp, r_order, w_order); 5880 bnx2x_init_pxp_arb(bp, r_order, w_order);
5881 } 5881 }
5882 5882
5883 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 5883 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5884 { 5884 {
5885 int is_required; 5885 int is_required;
5886 u32 val; 5886 u32 val;
5887 int port; 5887 int port;
5888 5888
5889 if (BP_NOMCP(bp)) 5889 if (BP_NOMCP(bp))
5890 return; 5890 return;
5891 5891
5892 is_required = 0; 5892 is_required = 0;
5893 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 5893 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5894 SHARED_HW_CFG_FAN_FAILURE_MASK; 5894 SHARED_HW_CFG_FAN_FAILURE_MASK;
5895 5895
5896 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 5896 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5897 is_required = 1; 5897 is_required = 1;
5898 5898
5899 /* 5899 /*
5900 * The fan failure mechanism is usually related to the PHY type since 5900 * The fan failure mechanism is usually related to the PHY type since
5901 * the power consumption of the board is affected by the PHY. Currently, 5901 * the power consumption of the board is affected by the PHY. Currently,
5902 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 5902 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5903 */ 5903 */
5904 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 5904 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5905 for (port = PORT_0; port < PORT_MAX; port++) { 5905 for (port = PORT_0; port < PORT_MAX; port++) {
5906 is_required |= 5906 is_required |=
5907 bnx2x_fan_failure_det_req( 5907 bnx2x_fan_failure_det_req(
5908 bp, 5908 bp,
5909 bp->common.shmem_base, 5909 bp->common.shmem_base,
5910 bp->common.shmem2_base, 5910 bp->common.shmem2_base,
5911 port); 5911 port);
5912 } 5912 }
5913 5913
5914 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 5914 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5915 5915
5916 if (is_required == 0) 5916 if (is_required == 0)
5917 return; 5917 return;
5918 5918
5919 /* Fan failure is indicated by SPIO 5 */ 5919 /* Fan failure is indicated by SPIO 5 */
5920 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 5920 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5921 MISC_REGISTERS_SPIO_INPUT_HI_Z); 5921 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5922 5922
5923 /* set to active low mode */ 5923 /* set to active low mode */
5924 val = REG_RD(bp, MISC_REG_SPIO_INT); 5924 val = REG_RD(bp, MISC_REG_SPIO_INT);
5925 val |= ((1 << MISC_REGISTERS_SPIO_5) << 5925 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5926 MISC_REGISTERS_SPIO_INT_OLD_SET_POS); 5926 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5927 REG_WR(bp, MISC_REG_SPIO_INT, val); 5927 REG_WR(bp, MISC_REG_SPIO_INT, val);
5928 5928
5929 /* enable interrupt to signal the IGU */ 5929 /* enable interrupt to signal the IGU */
5930 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 5930 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5931 val |= (1 << MISC_REGISTERS_SPIO_5); 5931 val |= (1 << MISC_REGISTERS_SPIO_5);
5932 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 5932 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5933 } 5933 }
5934 5934
5935 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) 5935 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5936 { 5936 {
5937 u32 offset = 0; 5937 u32 offset = 0;
5938 5938
5939 if (CHIP_IS_E1(bp)) 5939 if (CHIP_IS_E1(bp))
5940 return; 5940 return;
5941 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) 5941 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5942 return; 5942 return;
5943 5943
5944 switch (BP_ABS_FUNC(bp)) { 5944 switch (BP_ABS_FUNC(bp)) {
5945 case 0: 5945 case 0:
5946 offset = PXP2_REG_PGL_PRETEND_FUNC_F0; 5946 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5947 break; 5947 break;
5948 case 1: 5948 case 1:
5949 offset = PXP2_REG_PGL_PRETEND_FUNC_F1; 5949 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5950 break; 5950 break;
5951 case 2: 5951 case 2:
5952 offset = PXP2_REG_PGL_PRETEND_FUNC_F2; 5952 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5953 break; 5953 break;
5954 case 3: 5954 case 3:
5955 offset = PXP2_REG_PGL_PRETEND_FUNC_F3; 5955 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5956 break; 5956 break;
5957 case 4: 5957 case 4:
5958 offset = PXP2_REG_PGL_PRETEND_FUNC_F4; 5958 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5959 break; 5959 break;
5960 case 5: 5960 case 5:
5961 offset = PXP2_REG_PGL_PRETEND_FUNC_F5; 5961 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5962 break; 5962 break;
5963 case 6: 5963 case 6:
5964 offset = PXP2_REG_PGL_PRETEND_FUNC_F6; 5964 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5965 break; 5965 break;
5966 case 7: 5966 case 7:
5967 offset = PXP2_REG_PGL_PRETEND_FUNC_F7; 5967 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5968 break; 5968 break;
5969 default: 5969 default:
5970 return; 5970 return;
5971 } 5971 }
5972 5972
5973 REG_WR(bp, offset, pretend_func_num); 5973 REG_WR(bp, offset, pretend_func_num);
5974 REG_RD(bp, offset); 5974 REG_RD(bp, offset);
5975 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5975 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5976 } 5976 }
5977 5977
5978 void bnx2x_pf_disable(struct bnx2x *bp) 5978 void bnx2x_pf_disable(struct bnx2x *bp)
5979 { 5979 {
5980 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 5980 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5981 val &= ~IGU_PF_CONF_FUNC_EN; 5981 val &= ~IGU_PF_CONF_FUNC_EN;
5982 5982
5983 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 5983 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5984 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5984 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5985 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 5985 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5986 } 5986 }
5987 5987
5988 static inline void bnx2x__common_init_phy(struct bnx2x *bp) 5988 static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5989 { 5989 {
5990 u32 shmem_base[2], shmem2_base[2]; 5990 u32 shmem_base[2], shmem2_base[2];
5991 shmem_base[0] = bp->common.shmem_base; 5991 shmem_base[0] = bp->common.shmem_base;
5992 shmem2_base[0] = bp->common.shmem2_base; 5992 shmem2_base[0] = bp->common.shmem2_base;
5993 if (!CHIP_IS_E1x(bp)) { 5993 if (!CHIP_IS_E1x(bp)) {
5994 shmem_base[1] = 5994 shmem_base[1] =
5995 SHMEM2_RD(bp, other_shmem_base_addr); 5995 SHMEM2_RD(bp, other_shmem_base_addr);
5996 shmem2_base[1] = 5996 shmem2_base[1] =
5997 SHMEM2_RD(bp, other_shmem2_base_addr); 5997 SHMEM2_RD(bp, other_shmem2_base_addr);
5998 } 5998 }
5999 bnx2x_acquire_phy_lock(bp); 5999 bnx2x_acquire_phy_lock(bp);
6000 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 6000 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6001 bp->common.chip_id); 6001 bp->common.chip_id);
6002 bnx2x_release_phy_lock(bp); 6002 bnx2x_release_phy_lock(bp);
6003 } 6003 }
6004 6004
6005 /** 6005 /**
6006 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 6006 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6007 * 6007 *
6008 * @bp: driver handle 6008 * @bp: driver handle
6009 */ 6009 */
6010 static int bnx2x_init_hw_common(struct bnx2x *bp) 6010 static int bnx2x_init_hw_common(struct bnx2x *bp)
6011 { 6011 {
6012 u32 val; 6012 u32 val;
6013 6013
6014 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); 6014 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
6015 6015
6016 /* 6016 /*
6017 * take the UNDI lock to protect undi_unload flow from accessing 6017 * take the UNDI lock to protect undi_unload flow from accessing
6018 * registers while we're resetting the chip 6018 * registers while we're resetting the chip
6019 */ 6019 */
6020 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6020 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6021 6021
6022 bnx2x_reset_common(bp); 6022 bnx2x_reset_common(bp);
6023 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 6023 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6024 6024
6025 val = 0xfffc; 6025 val = 0xfffc;
6026 if (CHIP_IS_E3(bp)) { 6026 if (CHIP_IS_E3(bp)) {
6027 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6027 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6028 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6028 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6029 } 6029 }
6030 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 6030 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6031 6031
6032 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6032 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6033 6033
6034 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 6034 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6035 6035
6036 if (!CHIP_IS_E1x(bp)) { 6036 if (!CHIP_IS_E1x(bp)) {
6037 u8 abs_func_id; 6037 u8 abs_func_id;
6038 6038
6039 /** 6039 /**
6040 * 4-port mode or 2-port mode we need to turn of master-enable 6040 * 4-port mode or 2-port mode we need to turn of master-enable
6041 * for everyone, after that, turn it back on for self. 6041 * for everyone, after that, turn it back on for self.
6042 * so, we disregard multi-function or not, and always disable 6042 * so, we disregard multi-function or not, and always disable
6043 * for all functions on the given path, this means 0,2,4,6 for 6043 * for all functions on the given path, this means 0,2,4,6 for
6044 * path 0 and 1,3,5,7 for path 1 6044 * path 0 and 1,3,5,7 for path 1
6045 */ 6045 */
6046 for (abs_func_id = BP_PATH(bp); 6046 for (abs_func_id = BP_PATH(bp);
6047 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 6047 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6048 if (abs_func_id == BP_ABS_FUNC(bp)) { 6048 if (abs_func_id == BP_ABS_FUNC(bp)) {
6049 REG_WR(bp, 6049 REG_WR(bp,
6050 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 6050 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6051 1); 6051 1);
6052 continue; 6052 continue;
6053 } 6053 }
6054 6054
6055 bnx2x_pretend_func(bp, abs_func_id); 6055 bnx2x_pretend_func(bp, abs_func_id);
6056 /* clear pf enable */ 6056 /* clear pf enable */
6057 bnx2x_pf_disable(bp); 6057 bnx2x_pf_disable(bp);
6058 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6058 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6059 } 6059 }
6060 } 6060 }
6061 6061
6062 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 6062 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6063 if (CHIP_IS_E1(bp)) { 6063 if (CHIP_IS_E1(bp)) {
6064 /* enable HW interrupt from PXP on USDM overflow 6064 /* enable HW interrupt from PXP on USDM overflow
6065 bit 16 on INT_MASK_0 */ 6065 bit 16 on INT_MASK_0 */
6066 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6066 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6067 } 6067 }
6068 6068
6069 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 6069 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6070 bnx2x_init_pxp(bp); 6070 bnx2x_init_pxp(bp);
6071 6071
6072 #ifdef __BIG_ENDIAN 6072 #ifdef __BIG_ENDIAN
6073 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 6073 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6074 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 6074 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6075 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 6075 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6076 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 6076 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6077 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 6077 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6078 /* make sure this value is 0 */ 6078 /* make sure this value is 0 */
6079 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 6079 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6080 6080
6081 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 6081 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6082 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 6082 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6083 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 6083 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6084 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 6084 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6085 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 6085 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6086 #endif 6086 #endif
6087 6087
6088 bnx2x_ilt_init_page_size(bp, INITOP_SET); 6088 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6089 6089
6090 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 6090 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6091 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 6091 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6092 6092
6093 /* let the HW do it's magic ... */ 6093 /* let the HW do it's magic ... */
6094 msleep(100); 6094 msleep(100);
6095 /* finish PXP init */ 6095 /* finish PXP init */
6096 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 6096 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6097 if (val != 1) { 6097 if (val != 1) {
6098 BNX2X_ERR("PXP2 CFG failed\n"); 6098 BNX2X_ERR("PXP2 CFG failed\n");
6099 return -EBUSY; 6099 return -EBUSY;
6100 } 6100 }
6101 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 6101 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6102 if (val != 1) { 6102 if (val != 1) {
6103 BNX2X_ERR("PXP2 RD_INIT failed\n"); 6103 BNX2X_ERR("PXP2 RD_INIT failed\n");
6104 return -EBUSY; 6104 return -EBUSY;
6105 } 6105 }
6106 6106
6107 /* Timers bug workaround E2 only. We need to set the entire ILT to 6107 /* Timers bug workaround E2 only. We need to set the entire ILT to
6108 * have entries with value "0" and valid bit on. 6108 * have entries with value "0" and valid bit on.
6109 * This needs to be done by the first PF that is loaded in a path 6109 * This needs to be done by the first PF that is loaded in a path
6110 * (i.e. common phase) 6110 * (i.e. common phase)
6111 */ 6111 */
6112 if (!CHIP_IS_E1x(bp)) { 6112 if (!CHIP_IS_E1x(bp)) {
6113 /* In E2 there is a bug in the timers block that can cause function 6 / 7 6113 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6114 * (i.e. vnic3) to start even if it is marked as "scan-off". 6114 * (i.e. vnic3) to start even if it is marked as "scan-off".
6115 * This occurs when a different function (func2,3) is being marked 6115 * This occurs when a different function (func2,3) is being marked
6116 * as "scan-off". Real-life scenario for example: if a driver is being 6116 * as "scan-off". Real-life scenario for example: if a driver is being
6117 * load-unloaded while func6,7 are down. This will cause the timer to access 6117 * load-unloaded while func6,7 are down. This will cause the timer to access
6118 * the ilt, translate to a logical address and send a request to read/write. 6118 * the ilt, translate to a logical address and send a request to read/write.
6119 * Since the ilt for the function that is down is not valid, this will cause 6119 * Since the ilt for the function that is down is not valid, this will cause
6120 * a translation error which is unrecoverable. 6120 * a translation error which is unrecoverable.
6121 * The Workaround is intended to make sure that when this happens nothing fatal 6121 * The Workaround is intended to make sure that when this happens nothing fatal
6122 * will occur. The workaround: 6122 * will occur. The workaround:
6123 * 1. First PF driver which loads on a path will: 6123 * 1. First PF driver which loads on a path will:
6124 * a. After taking the chip out of reset, by using pretend, 6124 * a. After taking the chip out of reset, by using pretend,
6125 * it will write "0" to the following registers of 6125 * it will write "0" to the following registers of
6126 * the other vnics. 6126 * the other vnics.
6127 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6127 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6128 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 6128 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6129 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 6129 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6130 * And for itself it will write '1' to 6130 * And for itself it will write '1' to
6131 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 6131 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6132 * dmae-operations (writing to pram for example.) 6132 * dmae-operations (writing to pram for example.)
6133 * note: can be done for only function 6,7 but cleaner this 6133 * note: can be done for only function 6,7 but cleaner this
6134 * way. 6134 * way.
6135 * b. Write zero+valid to the entire ILT. 6135 * b. Write zero+valid to the entire ILT.
6136 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 6136 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6137 * VNIC3 (of that port). The range allocated will be the 6137 * VNIC3 (of that port). The range allocated will be the
6138 * entire ILT. This is needed to prevent ILT range error. 6138 * entire ILT. This is needed to prevent ILT range error.
6139 * 2. Any PF driver load flow: 6139 * 2. Any PF driver load flow:
6140 * a. ILT update with the physical addresses of the allocated 6140 * a. ILT update with the physical addresses of the allocated
6141 * logical pages. 6141 * logical pages.
6142 * b. Wait 20msec. - note that this timeout is needed to make 6142 * b. Wait 20msec. - note that this timeout is needed to make
6143 * sure there are no requests in one of the PXP internal 6143 * sure there are no requests in one of the PXP internal
6144 * queues with "old" ILT addresses. 6144 * queues with "old" ILT addresses.
6145 * c. PF enable in the PGLC. 6145 * c. PF enable in the PGLC.
6146 * d. Clear the was_error of the PF in the PGLC. (could have 6146 * d. Clear the was_error of the PF in the PGLC. (could have
6147 * occured while driver was down) 6147 * occured while driver was down)
6148 * e. PF enable in the CFC (WEAK + STRONG) 6148 * e. PF enable in the CFC (WEAK + STRONG)
6149 * f. Timers scan enable 6149 * f. Timers scan enable
6150 * 3. PF driver unload flow: 6150 * 3. PF driver unload flow:
6151 * a. Clear the Timers scan_en. 6151 * a. Clear the Timers scan_en.
6152 * b. Polling for scan_on=0 for that PF. 6152 * b. Polling for scan_on=0 for that PF.
6153 * c. Clear the PF enable bit in the PXP. 6153 * c. Clear the PF enable bit in the PXP.
6154 * d. Clear the PF enable in the CFC (WEAK + STRONG) 6154 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6155 * e. Write zero+valid to all ILT entries (The valid bit must 6155 * e. Write zero+valid to all ILT entries (The valid bit must
6156 * stay set) 6156 * stay set)
6157 * f. If this is VNIC 3 of a port then also init 6157 * f. If this is VNIC 3 of a port then also init
6158 * first_timers_ilt_entry to zero and last_timers_ilt_entry 6158 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6159 * to the last enrty in the ILT. 6159 * to the last enrty in the ILT.
6160 * 6160 *
6161 * Notes: 6161 * Notes:
6162 * Currently the PF error in the PGLC is non recoverable. 6162 * Currently the PF error in the PGLC is non recoverable.
6163 * In the future the there will be a recovery routine for this error. 6163 * In the future the there will be a recovery routine for this error.
6164 * Currently attention is masked. 6164 * Currently attention is masked.
6165 * Having an MCP lock on the load/unload process does not guarantee that 6165 * Having an MCP lock on the load/unload process does not guarantee that
6166 * there is no Timer disable during Func6/7 enable. This is because the 6166 * there is no Timer disable during Func6/7 enable. This is because the
6167 * Timers scan is currently being cleared by the MCP on FLR. 6167 * Timers scan is currently being cleared by the MCP on FLR.
6168 * Step 2.d can be done only for PF6/7 and the driver can also check if 6168 * Step 2.d can be done only for PF6/7 and the driver can also check if
6169 * there is error before clearing it. But the flow above is simpler and 6169 * there is error before clearing it. But the flow above is simpler and
6170 * more general. 6170 * more general.
6171 * All ILT entries are written by zero+valid and not just PF6/7 6171 * All ILT entries are written by zero+valid and not just PF6/7
6172 * ILT entries since in the future the ILT entries allocation for 6172 * ILT entries since in the future the ILT entries allocation for
6173 * PF-s might be dynamic. 6173 * PF-s might be dynamic.
6174 */ 6174 */
6175 struct ilt_client_info ilt_cli; 6175 struct ilt_client_info ilt_cli;
6176 struct bnx2x_ilt ilt; 6176 struct bnx2x_ilt ilt;
6177 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6177 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6178 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6178 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6179 6179
6180 /* initialize dummy TM client */ 6180 /* initialize dummy TM client */
6181 ilt_cli.start = 0; 6181 ilt_cli.start = 0;
6182 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6182 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6183 ilt_cli.client_num = ILT_CLIENT_TM; 6183 ilt_cli.client_num = ILT_CLIENT_TM;
6184 6184
6185 /* Step 1: set zeroes to all ilt page entries with valid bit on 6185 /* Step 1: set zeroes to all ilt page entries with valid bit on
6186 * Step 2: set the timers first/last ilt entry to point 6186 * Step 2: set the timers first/last ilt entry to point
6187 * to the entire range to prevent ILT range error for 3rd/4th 6187 * to the entire range to prevent ILT range error for 3rd/4th
6188 * vnic (this code assumes existance of the vnic) 6188 * vnic (this code assumes existance of the vnic)
6189 * 6189 *
6190 * both steps performed by call to bnx2x_ilt_client_init_op() 6190 * both steps performed by call to bnx2x_ilt_client_init_op()
6191 * with dummy TM client 6191 * with dummy TM client
6192 * 6192 *
6193 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6193 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6194 * and his brother are split registers 6194 * and his brother are split registers
6195 */ 6195 */
6196 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6196 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6197 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6197 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6198 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6198 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6199 6199
6200 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6200 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6201 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6201 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6202 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6202 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6203 } 6203 }
6204 6204
6205 6205
6206 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6206 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6207 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6207 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6208 6208
6209 if (!CHIP_IS_E1x(bp)) { 6209 if (!CHIP_IS_E1x(bp)) {
6210 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6210 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6211 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6211 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6212 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6212 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6213 6213
6214 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6214 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6215 6215
6216 /* let the HW do it's magic ... */ 6216 /* let the HW do it's magic ... */
6217 do { 6217 do {
6218 msleep(200); 6218 msleep(200);
6219 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6219 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6220 } while (factor-- && (val != 1)); 6220 } while (factor-- && (val != 1));
6221 6221
6222 if (val != 1) { 6222 if (val != 1) {
6223 BNX2X_ERR("ATC_INIT failed\n"); 6223 BNX2X_ERR("ATC_INIT failed\n");
6224 return -EBUSY; 6224 return -EBUSY;
6225 } 6225 }
6226 } 6226 }
6227 6227
6228 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6228 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6229 6229
6230 /* clean the DMAE memory */ 6230 /* clean the DMAE memory */
6231 bp->dmae_ready = 1; 6231 bp->dmae_ready = 1;
6232 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6232 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6233 6233
6234 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6234 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6235 6235
6236 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6236 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6237 6237
6238 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6238 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6239 6239
6240 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6240 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6241 6241
6242 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6242 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6243 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6243 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6244 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6244 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6245 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6245 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6246 6246
6247 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6247 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6248 6248
6249 6249
6250 /* QM queues pointers table */ 6250 /* QM queues pointers table */
6251 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6251 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6252 6252
6253 /* soft reset pulse */ 6253 /* soft reset pulse */
6254 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6254 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6255 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6255 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6256 6256
6257 #ifdef BCM_CNIC 6257 #ifdef BCM_CNIC
6258 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6258 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6259 #endif 6259 #endif
6260 6260
6261 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6261 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6262 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6262 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6263 if (!CHIP_REV_IS_SLOW(bp)) 6263 if (!CHIP_REV_IS_SLOW(bp))
6264 /* enable hw interrupt from doorbell Q */ 6264 /* enable hw interrupt from doorbell Q */
6265 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6265 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6266 6266
6267 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6267 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6268 6268
6269 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6269 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6270 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6270 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6271 6271
6272 if (!CHIP_IS_E1(bp)) 6272 if (!CHIP_IS_E1(bp))
6273 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6273 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6274 6274
6275 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) 6275 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6276 /* Bit-map indicating which L2 hdrs may appear 6276 /* Bit-map indicating which L2 hdrs may appear
6277 * after the basic Ethernet header 6277 * after the basic Ethernet header
6278 */ 6278 */
6279 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6279 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6280 bp->path_has_ovlan ? 7 : 6); 6280 bp->path_has_ovlan ? 7 : 6);
6281 6281
6282 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6282 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6283 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6283 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6284 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6284 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6285 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6285 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6286 6286
6287 if (!CHIP_IS_E1x(bp)) { 6287 if (!CHIP_IS_E1x(bp)) {
6288 /* reset VFC memories */ 6288 /* reset VFC memories */
6289 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6289 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6290 VFC_MEMORIES_RST_REG_CAM_RST | 6290 VFC_MEMORIES_RST_REG_CAM_RST |
6291 VFC_MEMORIES_RST_REG_RAM_RST); 6291 VFC_MEMORIES_RST_REG_RAM_RST);
6292 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6292 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6293 VFC_MEMORIES_RST_REG_CAM_RST | 6293 VFC_MEMORIES_RST_REG_CAM_RST |
6294 VFC_MEMORIES_RST_REG_RAM_RST); 6294 VFC_MEMORIES_RST_REG_RAM_RST);
6295 6295
6296 msleep(20); 6296 msleep(20);
6297 } 6297 }
6298 6298
6299 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6299 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6300 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6300 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6301 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6301 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6302 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6302 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6303 6303
6304 /* sync semi rtc */ 6304 /* sync semi rtc */
6305 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6305 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6306 0x80000000); 6306 0x80000000);
6307 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6307 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6308 0x80000000); 6308 0x80000000);
6309 6309
6310 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6310 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6311 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6311 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6312 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6312 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6313 6313
6314 if (!CHIP_IS_E1x(bp)) 6314 if (!CHIP_IS_E1x(bp))
6315 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6315 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6316 bp->path_has_ovlan ? 7 : 6); 6316 bp->path_has_ovlan ? 7 : 6);
6317 6317
6318 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6318 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6319 6319
6320 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6320 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6321 6321
6322 #ifdef BCM_CNIC 6322 #ifdef BCM_CNIC
6323 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6323 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6324 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6324 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6325 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6325 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6326 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6326 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6327 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6327 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6328 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6328 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6329 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6329 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6330 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6330 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6331 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6331 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6332 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6332 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6333 #endif 6333 #endif
6334 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6334 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6335 6335
6336 if (sizeof(union cdu_context) != 1024) 6336 if (sizeof(union cdu_context) != 1024)
6337 /* we currently assume that a context is 1024 bytes */ 6337 /* we currently assume that a context is 1024 bytes */
6338 dev_alert(&bp->pdev->dev, "please adjust the size " 6338 dev_alert(&bp->pdev->dev, "please adjust the size "
6339 "of cdu_context(%ld)\n", 6339 "of cdu_context(%ld)\n",
6340 (long)sizeof(union cdu_context)); 6340 (long)sizeof(union cdu_context));
6341 6341
6342 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6342 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6343 val = (4 << 24) + (0 << 12) + 1024; 6343 val = (4 << 24) + (0 << 12) + 1024;
6344 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6344 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6345 6345
6346 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6346 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6347 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6347 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6348 /* enable context validation interrupt from CFC */ 6348 /* enable context validation interrupt from CFC */
6349 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6349 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6350 6350
6351 /* set the thresholds to prevent CFC/CDU race */ 6351 /* set the thresholds to prevent CFC/CDU race */
6352 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6352 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6353 6353
6354 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6354 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6355 6355
6356 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6356 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6357 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6357 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6358 6358
6359 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6359 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6360 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6360 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6361 6361
6362 /* Reset PCIE errors for debug */ 6362 /* Reset PCIE errors for debug */
6363 REG_WR(bp, 0x2814, 0xffffffff); 6363 REG_WR(bp, 0x2814, 0xffffffff);
6364 REG_WR(bp, 0x3820, 0xffffffff); 6364 REG_WR(bp, 0x3820, 0xffffffff);
6365 6365
6366 if (!CHIP_IS_E1x(bp)) { 6366 if (!CHIP_IS_E1x(bp)) {
6367 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6367 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6368 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6368 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6369 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6369 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6370 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6370 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6371 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6371 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6372 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6372 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6373 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6373 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6374 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6374 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6375 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6375 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6376 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6376 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6377 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6377 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6378 } 6378 }
6379 6379
6380 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6380 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6381 if (!CHIP_IS_E1(bp)) { 6381 if (!CHIP_IS_E1(bp)) {
6382 /* in E3 this done in per-port section */ 6382 /* in E3 this done in per-port section */
6383 if (!CHIP_IS_E3(bp)) 6383 if (!CHIP_IS_E3(bp))
6384 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6384 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6385 } 6385 }
6386 if (CHIP_IS_E1H(bp)) 6386 if (CHIP_IS_E1H(bp))
6387 /* not applicable for E2 (and above ...) */ 6387 /* not applicable for E2 (and above ...) */
6388 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6388 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6389 6389
6390 if (CHIP_REV_IS_SLOW(bp)) 6390 if (CHIP_REV_IS_SLOW(bp))
6391 msleep(200); 6391 msleep(200);
6392 6392
6393 /* finish CFC init */ 6393 /* finish CFC init */
6394 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6394 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6395 if (val != 1) { 6395 if (val != 1) {
6396 BNX2X_ERR("CFC LL_INIT failed\n"); 6396 BNX2X_ERR("CFC LL_INIT failed\n");
6397 return -EBUSY; 6397 return -EBUSY;
6398 } 6398 }
6399 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6399 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6400 if (val != 1) { 6400 if (val != 1) {
6401 BNX2X_ERR("CFC AC_INIT failed\n"); 6401 BNX2X_ERR("CFC AC_INIT failed\n");
6402 return -EBUSY; 6402 return -EBUSY;
6403 } 6403 }
6404 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6404 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6405 if (val != 1) { 6405 if (val != 1) {
6406 BNX2X_ERR("CFC CAM_INIT failed\n"); 6406 BNX2X_ERR("CFC CAM_INIT failed\n");
6407 return -EBUSY; 6407 return -EBUSY;
6408 } 6408 }
6409 REG_WR(bp, CFC_REG_DEBUG0, 0); 6409 REG_WR(bp, CFC_REG_DEBUG0, 0);
6410 6410
6411 if (CHIP_IS_E1(bp)) { 6411 if (CHIP_IS_E1(bp)) {
6412 /* read NIG statistic 6412 /* read NIG statistic
6413 to see if this is our first up since powerup */ 6413 to see if this is our first up since powerup */
6414 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6414 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6415 val = *bnx2x_sp(bp, wb_data[0]); 6415 val = *bnx2x_sp(bp, wb_data[0]);
6416 6416
6417 /* do internal memory self test */ 6417 /* do internal memory self test */
6418 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6418 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6419 BNX2X_ERR("internal mem self test failed\n"); 6419 BNX2X_ERR("internal mem self test failed\n");
6420 return -EBUSY; 6420 return -EBUSY;
6421 } 6421 }
6422 } 6422 }
6423 6423
6424 bnx2x_setup_fan_failure_detection(bp); 6424 bnx2x_setup_fan_failure_detection(bp);
6425 6425
6426 /* clear PXP2 attentions */ 6426 /* clear PXP2 attentions */
6427 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6427 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6428 6428
6429 bnx2x_enable_blocks_attention(bp); 6429 bnx2x_enable_blocks_attention(bp);
6430 bnx2x_enable_blocks_parity(bp); 6430 bnx2x_enable_blocks_parity(bp);
6431 6431
6432 if (!BP_NOMCP(bp)) { 6432 if (!BP_NOMCP(bp)) {
6433 if (CHIP_IS_E1x(bp)) 6433 if (CHIP_IS_E1x(bp))
6434 bnx2x__common_init_phy(bp); 6434 bnx2x__common_init_phy(bp);
6435 } else 6435 } else
6436 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6436 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6437 6437
6438 return 0; 6438 return 0;
6439 } 6439 }
6440 6440
6441 /** 6441 /**
6442 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6442 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6443 * 6443 *
6444 * @bp: driver handle 6444 * @bp: driver handle
6445 */ 6445 */
6446 static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6446 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6447 { 6447 {
6448 int rc = bnx2x_init_hw_common(bp); 6448 int rc = bnx2x_init_hw_common(bp);
6449 6449
6450 if (rc) 6450 if (rc)
6451 return rc; 6451 return rc;
6452 6452
6453 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6453 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6454 if (!BP_NOMCP(bp)) 6454 if (!BP_NOMCP(bp))
6455 bnx2x__common_init_phy(bp); 6455 bnx2x__common_init_phy(bp);
6456 6456
6457 return 0; 6457 return 0;
6458 } 6458 }
6459 6459
6460 static int bnx2x_init_hw_port(struct bnx2x *bp) 6460 static int bnx2x_init_hw_port(struct bnx2x *bp)
6461 { 6461 {
6462 int port = BP_PORT(bp); 6462 int port = BP_PORT(bp);
6463 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6463 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6464 u32 low, high; 6464 u32 low, high;
6465 u32 val; 6465 u32 val;
6466 6466
6467 bnx2x__link_reset(bp); 6467 bnx2x__link_reset(bp);
6468 6468
6469 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); 6469 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
6470 6470
6471 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6471 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6472 6472
6473 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6473 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6474 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6474 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6475 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6475 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6476 6476
6477 /* Timers bug workaround: disables the pf_master bit in pglue at 6477 /* Timers bug workaround: disables the pf_master bit in pglue at
6478 * common phase, we need to enable it here before any dmae access are 6478 * common phase, we need to enable it here before any dmae access are
6479 * attempted. Therefore we manually added the enable-master to the 6479 * attempted. Therefore we manually added the enable-master to the
6480 * port phase (it also happens in the function phase) 6480 * port phase (it also happens in the function phase)
6481 */ 6481 */
6482 if (!CHIP_IS_E1x(bp)) 6482 if (!CHIP_IS_E1x(bp))
6483 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6483 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6484 6484
6485 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6485 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6486 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6486 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6487 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6487 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6488 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6488 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6489 6489
6490 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6490 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6491 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6491 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6492 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6492 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6493 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6493 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6494 6494
6495 /* QM cid (connection) count */ 6495 /* QM cid (connection) count */
6496 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6496 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6497 6497
6498 #ifdef BCM_CNIC 6498 #ifdef BCM_CNIC
6499 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6499 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6500 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6500 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6501 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6501 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6502 #endif 6502 #endif
6503 6503
6504 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6504 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6505 6505
6506 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6506 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6507 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6507 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6508 6508
6509 if (IS_MF(bp)) 6509 if (IS_MF(bp))
6510 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6510 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6511 else if (bp->dev->mtu > 4096) { 6511 else if (bp->dev->mtu > 4096) {
6512 if (bp->flags & ONE_PORT_FLAG) 6512 if (bp->flags & ONE_PORT_FLAG)
6513 low = 160; 6513 low = 160;
6514 else { 6514 else {
6515 val = bp->dev->mtu; 6515 val = bp->dev->mtu;
6516 /* (24*1024 + val*4)/256 */ 6516 /* (24*1024 + val*4)/256 */
6517 low = 96 + (val/64) + 6517 low = 96 + (val/64) +
6518 ((val % 64) ? 1 : 0); 6518 ((val % 64) ? 1 : 0);
6519 } 6519 }
6520 } else 6520 } else
6521 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6521 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6522 high = low + 56; /* 14*1024/256 */ 6522 high = low + 56; /* 14*1024/256 */
6523 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6523 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6524 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6524 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6525 } 6525 }
6526 6526
6527 if (CHIP_MODE_IS_4_PORT(bp)) 6527 if (CHIP_MODE_IS_4_PORT(bp))
6528 REG_WR(bp, (BP_PORT(bp) ? 6528 REG_WR(bp, (BP_PORT(bp) ?
6529 BRB1_REG_MAC_GUARANTIED_1 : 6529 BRB1_REG_MAC_GUARANTIED_1 :
6530 BRB1_REG_MAC_GUARANTIED_0), 40); 6530 BRB1_REG_MAC_GUARANTIED_0), 40);
6531 6531
6532 6532
6533 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6533 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6534 if (CHIP_IS_E3B0(bp)) 6534 if (CHIP_IS_E3B0(bp))
6535 /* Ovlan exists only if we are in multi-function + 6535 /* Ovlan exists only if we are in multi-function +
6536 * switch-dependent mode, in switch-independent there 6536 * switch-dependent mode, in switch-independent there
6537 * is no ovlan headers 6537 * is no ovlan headers
6538 */ 6538 */
6539 REG_WR(bp, BP_PORT(bp) ? 6539 REG_WR(bp, BP_PORT(bp) ?
6540 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 6540 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6541 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 6541 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6542 (bp->path_has_ovlan ? 7 : 6)); 6542 (bp->path_has_ovlan ? 7 : 6));
6543 6543
6544 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6544 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6545 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6545 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6546 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6546 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6547 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6547 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6548 6548
6549 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6549 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6550 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6550 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6551 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6551 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6552 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6552 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6553 6553
6554 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6554 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6555 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6555 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6556 6556
6557 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6557 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6558 6558
6559 if (CHIP_IS_E1x(bp)) { 6559 if (CHIP_IS_E1x(bp)) {
6560 /* configure PBF to work without PAUSE mtu 9000 */ 6560 /* configure PBF to work without PAUSE mtu 9000 */
6561 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 6561 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6562 6562
6563 /* update threshold */ 6563 /* update threshold */
6564 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 6564 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6565 /* update init credit */ 6565 /* update init credit */
6566 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 6566 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6567 6567
6568 /* probe changes */ 6568 /* probe changes */
6569 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 6569 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6570 udelay(50); 6570 udelay(50);
6571 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 6571 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6572 } 6572 }
6573 6573
6574 #ifdef BCM_CNIC 6574 #ifdef BCM_CNIC
6575 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6575 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6576 #endif 6576 #endif
6577 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6577 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6578 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6578 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6579 6579
6580 if (CHIP_IS_E1(bp)) { 6580 if (CHIP_IS_E1(bp)) {
6581 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6581 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6582 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6582 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6583 } 6583 }
6584 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6584 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6585 6585
6586 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6586 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6587 6587
6588 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6588 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6589 /* init aeu_mask_attn_func_0/1: 6589 /* init aeu_mask_attn_func_0/1:
6590 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 6590 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6591 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 6591 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6592 * bits 4-7 are used for "per vn group attention" */ 6592 * bits 4-7 are used for "per vn group attention" */
6593 val = IS_MF(bp) ? 0xF7 : 0x7; 6593 val = IS_MF(bp) ? 0xF7 : 0x7;
6594 /* Enable DCBX attention for all but E1 */ 6594 /* Enable DCBX attention for all but E1 */
6595 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 6595 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6596 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 6596 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6597 6597
6598 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6598 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6599 6599
6600 if (!CHIP_IS_E1x(bp)) { 6600 if (!CHIP_IS_E1x(bp)) {
6601 /* Bit-map indicating which L2 hdrs may appear after the 6601 /* Bit-map indicating which L2 hdrs may appear after the
6602 * basic Ethernet header 6602 * basic Ethernet header
6603 */ 6603 */
6604 REG_WR(bp, BP_PORT(bp) ? 6604 REG_WR(bp, BP_PORT(bp) ?
6605 NIG_REG_P1_HDRS_AFTER_BASIC : 6605 NIG_REG_P1_HDRS_AFTER_BASIC :
6606 NIG_REG_P0_HDRS_AFTER_BASIC, 6606 NIG_REG_P0_HDRS_AFTER_BASIC,
6607 IS_MF_SD(bp) ? 7 : 6); 6607 IS_MF_SD(bp) ? 7 : 6);
6608 6608
6609 if (CHIP_IS_E3(bp)) 6609 if (CHIP_IS_E3(bp))
6610 REG_WR(bp, BP_PORT(bp) ? 6610 REG_WR(bp, BP_PORT(bp) ?
6611 NIG_REG_LLH1_MF_MODE : 6611 NIG_REG_LLH1_MF_MODE :
6612 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6612 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6613 } 6613 }
6614 if (!CHIP_IS_E3(bp)) 6614 if (!CHIP_IS_E3(bp))
6615 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 6615 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6616 6616
6617 if (!CHIP_IS_E1(bp)) { 6617 if (!CHIP_IS_E1(bp)) {
6618 /* 0x2 disable mf_ov, 0x1 enable */ 6618 /* 0x2 disable mf_ov, 0x1 enable */
6619 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 6619 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6620 (IS_MF_SD(bp) ? 0x1 : 0x2)); 6620 (IS_MF_SD(bp) ? 0x1 : 0x2));
6621 6621
6622 if (!CHIP_IS_E1x(bp)) { 6622 if (!CHIP_IS_E1x(bp)) {
6623 val = 0; 6623 val = 0;
6624 switch (bp->mf_mode) { 6624 switch (bp->mf_mode) {
6625 case MULTI_FUNCTION_SD: 6625 case MULTI_FUNCTION_SD:
6626 val = 1; 6626 val = 1;
6627 break; 6627 break;
6628 case MULTI_FUNCTION_SI: 6628 case MULTI_FUNCTION_SI:
6629 val = 2; 6629 val = 2;
6630 break; 6630 break;
6631 } 6631 }
6632 6632
6633 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 6633 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6634 NIG_REG_LLH0_CLS_TYPE), val); 6634 NIG_REG_LLH0_CLS_TYPE), val);
6635 } 6635 }
6636 { 6636 {
6637 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 6637 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6638 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 6638 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6639 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 6639 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6640 } 6640 }
6641 } 6641 }
6642 6642
6643 6643
6644 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6644 /* If SPIO5 is set to generate interrupts, enable it for this port */
6645 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6645 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6646 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6646 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6647 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6647 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6648 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6648 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6649 val = REG_RD(bp, reg_addr); 6649 val = REG_RD(bp, reg_addr);
6650 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 6650 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6651 REG_WR(bp, reg_addr, val); 6651 REG_WR(bp, reg_addr, val);
6652 } 6652 }
6653 6653
6654 return 0; 6654 return 0;
6655 } 6655 }
6656 6656
6657 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 6657 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6658 { 6658 {
6659 int reg; 6659 int reg;
6660 6660
6661 if (CHIP_IS_E1(bp)) 6661 if (CHIP_IS_E1(bp))
6662 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 6662 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6663 else 6663 else
6664 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 6664 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6665 6665
6666 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 6666 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6667 } 6667 }
6668 6668
6669 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 6669 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6670 { 6670 {
6671 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 6671 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6672 } 6672 }
6673 6673
6674 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 6674 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6675 { 6675 {
6676 u32 i, base = FUNC_ILT_BASE(func); 6676 u32 i, base = FUNC_ILT_BASE(func);
6677 for (i = base; i < base + ILT_PER_FUNC; i++) 6677 for (i = base; i < base + ILT_PER_FUNC; i++)
6678 bnx2x_ilt_wr(bp, i, 0); 6678 bnx2x_ilt_wr(bp, i, 0);
6679 } 6679 }
6680 6680
6681 static int bnx2x_init_hw_func(struct bnx2x *bp) 6681 static int bnx2x_init_hw_func(struct bnx2x *bp)
6682 { 6682 {
6683 int port = BP_PORT(bp); 6683 int port = BP_PORT(bp);
6684 int func = BP_FUNC(bp); 6684 int func = BP_FUNC(bp);
6685 int init_phase = PHASE_PF0 + func; 6685 int init_phase = PHASE_PF0 + func;
6686 struct bnx2x_ilt *ilt = BP_ILT(bp); 6686 struct bnx2x_ilt *ilt = BP_ILT(bp);
6687 u16 cdu_ilt_start; 6687 u16 cdu_ilt_start;
6688 u32 addr, val; 6688 u32 addr, val;
6689 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6689 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6690 int i, main_mem_width; 6690 int i, main_mem_width;
6691 6691
6692 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); 6692 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
6693 6693
6694 /* FLR cleanup - hmmm */ 6694 /* FLR cleanup - hmmm */
6695 if (!CHIP_IS_E1x(bp)) 6695 if (!CHIP_IS_E1x(bp))
6696 bnx2x_pf_flr_clnup(bp); 6696 bnx2x_pf_flr_clnup(bp);
6697 6697
6698 /* set MSI reconfigure capability */ 6698 /* set MSI reconfigure capability */
6699 if (bp->common.int_block == INT_BLOCK_HC) { 6699 if (bp->common.int_block == INT_BLOCK_HC) {
6700 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 6700 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6701 val = REG_RD(bp, addr); 6701 val = REG_RD(bp, addr);
6702 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 6702 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6703 REG_WR(bp, addr, val); 6703 REG_WR(bp, addr, val);
6704 } 6704 }
6705 6705
6706 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6706 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6707 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6707 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6708 6708
6709 ilt = BP_ILT(bp); 6709 ilt = BP_ILT(bp);
6710 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 6710 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6711 6711
6712 for (i = 0; i < L2_ILT_LINES(bp); i++) { 6712 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6713 ilt->lines[cdu_ilt_start + i].page = 6713 ilt->lines[cdu_ilt_start + i].page =
6714 bp->context.vcxt + (ILT_PAGE_CIDS * i); 6714 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6715 ilt->lines[cdu_ilt_start + i].page_mapping = 6715 ilt->lines[cdu_ilt_start + i].page_mapping =
6716 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); 6716 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6717 /* cdu ilt pages are allocated manually so there's no need to 6717 /* cdu ilt pages are allocated manually so there's no need to
6718 set the size */ 6718 set the size */
6719 } 6719 }
6720 bnx2x_ilt_init_op(bp, INITOP_SET); 6720 bnx2x_ilt_init_op(bp, INITOP_SET);
6721 6721
6722 #ifdef BCM_CNIC 6722 #ifdef BCM_CNIC
6723 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 6723 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6724 6724
6725 /* T1 hash bits value determines the T1 number of entries */ 6725 /* T1 hash bits value determines the T1 number of entries */
6726 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 6726 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6727 #endif 6727 #endif
6728 6728
6729 #ifndef BCM_CNIC 6729 #ifndef BCM_CNIC
6730 /* set NIC mode */ 6730 /* set NIC mode */
6731 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6731 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6732 #endif /* BCM_CNIC */ 6732 #endif /* BCM_CNIC */
6733 6733
6734 if (!CHIP_IS_E1x(bp)) { 6734 if (!CHIP_IS_E1x(bp)) {
6735 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 6735 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6736 6736
6737 /* Turn on a single ISR mode in IGU if driver is going to use 6737 /* Turn on a single ISR mode in IGU if driver is going to use
6738 * INT#x or MSI 6738 * INT#x or MSI
6739 */ 6739 */
6740 if (!(bp->flags & USING_MSIX_FLAG)) 6740 if (!(bp->flags & USING_MSIX_FLAG))
6741 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 6741 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6742 /* 6742 /*
6743 * Timers workaround bug: function init part. 6743 * Timers workaround bug: function init part.
6744 * Need to wait 20msec after initializing ILT, 6744 * Need to wait 20msec after initializing ILT,
6745 * needed to make sure there are no requests in 6745 * needed to make sure there are no requests in
6746 * one of the PXP internal queues with "old" ILT addresses 6746 * one of the PXP internal queues with "old" ILT addresses
6747 */ 6747 */
6748 msleep(20); 6748 msleep(20);
6749 /* 6749 /*
6750 * Master enable - Due to WB DMAE writes performed before this 6750 * Master enable - Due to WB DMAE writes performed before this
6751 * register is re-initialized as part of the regular function 6751 * register is re-initialized as part of the regular function
6752 * init 6752 * init
6753 */ 6753 */
6754 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6754 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6755 /* Enable the function in IGU */ 6755 /* Enable the function in IGU */
6756 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 6756 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6757 } 6757 }
6758 6758
6759 bp->dmae_ready = 1; 6759 bp->dmae_ready = 1;
6760 6760
6761 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6761 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6762 6762
6763 if (!CHIP_IS_E1x(bp)) 6763 if (!CHIP_IS_E1x(bp))
6764 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 6764 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6765 6765
6766 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6766 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6767 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6767 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6768 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6768 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6769 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6769 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6770 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6770 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6771 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6771 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6772 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6772 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6773 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6773 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6774 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6774 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6775 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6775 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6776 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6776 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6777 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6777 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6778 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6778 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6779 6779
6780 if (!CHIP_IS_E1x(bp)) 6780 if (!CHIP_IS_E1x(bp))
6781 REG_WR(bp, QM_REG_PF_EN, 1); 6781 REG_WR(bp, QM_REG_PF_EN, 1);
6782 6782
6783 if (!CHIP_IS_E1x(bp)) { 6783 if (!CHIP_IS_E1x(bp)) {
6784 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6784 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6785 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6785 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6786 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6786 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6787 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6787 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6788 } 6788 }
6789 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6789 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6790 6790
6791 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6791 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6792 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6792 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6793 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6793 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6794 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6794 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6795 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6795 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6796 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6796 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6797 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6797 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6798 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6798 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6799 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6799 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6800 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6800 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6801 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6801 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6802 if (!CHIP_IS_E1x(bp)) 6802 if (!CHIP_IS_E1x(bp))
6803 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 6803 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6804 6804
6805 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6805 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6806 6806
6807 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6807 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6808 6808
6809 if (!CHIP_IS_E1x(bp)) 6809 if (!CHIP_IS_E1x(bp))
6810 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 6810 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6811 6811
6812 if (IS_MF(bp)) { 6812 if (IS_MF(bp)) {
6813 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 6813 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6814 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 6814 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6815 } 6815 }
6816 6816
6817 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6817 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6818 6818
6819 /* HC init per function */ 6819 /* HC init per function */
6820 if (bp->common.int_block == INT_BLOCK_HC) { 6820 if (bp->common.int_block == INT_BLOCK_HC) {
6821 if (CHIP_IS_E1H(bp)) { 6821 if (CHIP_IS_E1H(bp)) {
6822 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6822 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6823 6823
6824 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6824 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6825 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6825 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6826 } 6826 }
6827 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6827 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6828 6828
6829 } else { 6829 } else {
6830 int num_segs, sb_idx, prod_offset; 6830 int num_segs, sb_idx, prod_offset;
6831 6831
6832 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6832 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6833 6833
6834 if (!CHIP_IS_E1x(bp)) { 6834 if (!CHIP_IS_E1x(bp)) {
6835 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 6835 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6836 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 6836 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6837 } 6837 }
6838 6838
6839 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6839 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6840 6840
6841 if (!CHIP_IS_E1x(bp)) { 6841 if (!CHIP_IS_E1x(bp)) {
6842 int dsb_idx = 0; 6842 int dsb_idx = 0;
6843 /** 6843 /**
6844 * Producer memory: 6844 * Producer memory:
6845 * E2 mode: address 0-135 match to the mapping memory; 6845 * E2 mode: address 0-135 match to the mapping memory;
6846 * 136 - PF0 default prod; 137 - PF1 default prod; 6846 * 136 - PF0 default prod; 137 - PF1 default prod;
6847 * 138 - PF2 default prod; 139 - PF3 default prod; 6847 * 138 - PF2 default prod; 139 - PF3 default prod;
6848 * 140 - PF0 attn prod; 141 - PF1 attn prod; 6848 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6849 * 142 - PF2 attn prod; 143 - PF3 attn prod; 6849 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6850 * 144-147 reserved. 6850 * 144-147 reserved.
6851 * 6851 *
6852 * E1.5 mode - In backward compatible mode; 6852 * E1.5 mode - In backward compatible mode;
6853 * for non default SB; each even line in the memory 6853 * for non default SB; each even line in the memory
6854 * holds the U producer and each odd line hold 6854 * holds the U producer and each odd line hold
6855 * the C producer. The first 128 producers are for 6855 * the C producer. The first 128 producers are for
6856 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 6856 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6857 * producers are for the DSB for each PF. 6857 * producers are for the DSB for each PF.
6858 * Each PF has five segments: (the order inside each 6858 * Each PF has five segments: (the order inside each
6859 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 6859 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6860 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 6860 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6861 * 144-147 attn prods; 6861 * 144-147 attn prods;
6862 */ 6862 */
6863 /* non-default-status-blocks */ 6863 /* non-default-status-blocks */
6864 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6864 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6865 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 6865 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6866 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 6866 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6867 prod_offset = (bp->igu_base_sb + sb_idx) * 6867 prod_offset = (bp->igu_base_sb + sb_idx) *
6868 num_segs; 6868 num_segs;
6869 6869
6870 for (i = 0; i < num_segs; i++) { 6870 for (i = 0; i < num_segs; i++) {
6871 addr = IGU_REG_PROD_CONS_MEMORY + 6871 addr = IGU_REG_PROD_CONS_MEMORY +
6872 (prod_offset + i) * 4; 6872 (prod_offset + i) * 4;
6873 REG_WR(bp, addr, 0); 6873 REG_WR(bp, addr, 0);
6874 } 6874 }
6875 /* send consumer update with value 0 */ 6875 /* send consumer update with value 0 */
6876 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 6876 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6877 USTORM_ID, 0, IGU_INT_NOP, 1); 6877 USTORM_ID, 0, IGU_INT_NOP, 1);
6878 bnx2x_igu_clear_sb(bp, 6878 bnx2x_igu_clear_sb(bp,
6879 bp->igu_base_sb + sb_idx); 6879 bp->igu_base_sb + sb_idx);
6880 } 6880 }
6881 6881
6882 /* default-status-blocks */ 6882 /* default-status-blocks */
6883 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6883 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6884 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 6884 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6885 6885
6886 if (CHIP_MODE_IS_4_PORT(bp)) 6886 if (CHIP_MODE_IS_4_PORT(bp))
6887 dsb_idx = BP_FUNC(bp); 6887 dsb_idx = BP_FUNC(bp);
6888 else 6888 else
6889 dsb_idx = BP_VN(bp); 6889 dsb_idx = BP_VN(bp);
6890 6890
6891 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6891 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6892 IGU_BC_BASE_DSB_PROD + dsb_idx : 6892 IGU_BC_BASE_DSB_PROD + dsb_idx :
6893 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6893 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6894 6894
6895 /* 6895 /*
6896 * igu prods come in chunks of E1HVN_MAX (4) - 6896 * igu prods come in chunks of E1HVN_MAX (4) -
6897 * does not matters what is the current chip mode 6897 * does not matters what is the current chip mode
6898 */ 6898 */
6899 for (i = 0; i < (num_segs * E1HVN_MAX); 6899 for (i = 0; i < (num_segs * E1HVN_MAX);
6900 i += E1HVN_MAX) { 6900 i += E1HVN_MAX) {
6901 addr = IGU_REG_PROD_CONS_MEMORY + 6901 addr = IGU_REG_PROD_CONS_MEMORY +
6902 (prod_offset + i)*4; 6902 (prod_offset + i)*4;
6903 REG_WR(bp, addr, 0); 6903 REG_WR(bp, addr, 0);
6904 } 6904 }
6905 /* send consumer update with 0 */ 6905 /* send consumer update with 0 */
6906 if (CHIP_INT_MODE_IS_BC(bp)) { 6906 if (CHIP_INT_MODE_IS_BC(bp)) {
6907 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6907 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6908 USTORM_ID, 0, IGU_INT_NOP, 1); 6908 USTORM_ID, 0, IGU_INT_NOP, 1);
6909 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6909 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6910 CSTORM_ID, 0, IGU_INT_NOP, 1); 6910 CSTORM_ID, 0, IGU_INT_NOP, 1);
6911 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6911 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6912 XSTORM_ID, 0, IGU_INT_NOP, 1); 6912 XSTORM_ID, 0, IGU_INT_NOP, 1);
6913 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6913 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6914 TSTORM_ID, 0, IGU_INT_NOP, 1); 6914 TSTORM_ID, 0, IGU_INT_NOP, 1);
6915 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6915 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6916 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6916 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6917 } else { 6917 } else {
6918 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6918 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6919 USTORM_ID, 0, IGU_INT_NOP, 1); 6919 USTORM_ID, 0, IGU_INT_NOP, 1);
6920 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6920 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6921 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6921 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6922 } 6922 }
6923 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 6923 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6924 6924
6925 /* !!! these should become driver const once 6925 /* !!! these should become driver const once
6926 rf-tool supports split-68 const */ 6926 rf-tool supports split-68 const */
6927 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 6927 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6928 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 6928 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6929 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 6929 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6930 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 6930 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6931 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 6931 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6932 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 6932 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6933 } 6933 }
6934 } 6934 }
6935 6935
6936 /* Reset PCIE errors for debug */ 6936 /* Reset PCIE errors for debug */
6937 REG_WR(bp, 0x2114, 0xffffffff); 6937 REG_WR(bp, 0x2114, 0xffffffff);
6938 REG_WR(bp, 0x2120, 0xffffffff); 6938 REG_WR(bp, 0x2120, 0xffffffff);
6939 6939
6940 if (CHIP_IS_E1x(bp)) { 6940 if (CHIP_IS_E1x(bp)) {
6941 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 6941 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6942 main_mem_base = HC_REG_MAIN_MEMORY + 6942 main_mem_base = HC_REG_MAIN_MEMORY +
6943 BP_PORT(bp) * (main_mem_size * 4); 6943 BP_PORT(bp) * (main_mem_size * 4);
6944 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 6944 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6945 main_mem_width = 8; 6945 main_mem_width = 8;
6946 6946
6947 val = REG_RD(bp, main_mem_prty_clr); 6947 val = REG_RD(bp, main_mem_prty_clr);
6948 if (val) 6948 if (val)
6949 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " 6949 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6950 "block during " 6950 "block during "
6951 "function init (0x%x)!\n", val); 6951 "function init (0x%x)!\n", val);
6952 6952
6953 /* Clear "false" parity errors in MSI-X table */ 6953 /* Clear "false" parity errors in MSI-X table */
6954 for (i = main_mem_base; 6954 for (i = main_mem_base;
6955 i < main_mem_base + main_mem_size * 4; 6955 i < main_mem_base + main_mem_size * 4;
6956 i += main_mem_width) { 6956 i += main_mem_width) {
6957 bnx2x_read_dmae(bp, i, main_mem_width / 4); 6957 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6958 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 6958 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6959 i, main_mem_width / 4); 6959 i, main_mem_width / 4);
6960 } 6960 }
6961 /* Clear HC parity attention */ 6961 /* Clear HC parity attention */
6962 REG_RD(bp, main_mem_prty_clr); 6962 REG_RD(bp, main_mem_prty_clr);
6963 } 6963 }
6964 6964
6965 #ifdef BNX2X_STOP_ON_ERROR 6965 #ifdef BNX2X_STOP_ON_ERROR
6966 /* Enable STORMs SP logging */ 6966 /* Enable STORMs SP logging */
6967 REG_WR8(bp, BAR_USTRORM_INTMEM + 6967 REG_WR8(bp, BAR_USTRORM_INTMEM +
6968 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6968 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6969 REG_WR8(bp, BAR_TSTRORM_INTMEM + 6969 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6970 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6970 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6971 REG_WR8(bp, BAR_CSTRORM_INTMEM + 6971 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6972 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6972 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6973 REG_WR8(bp, BAR_XSTRORM_INTMEM + 6973 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6974 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6974 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6975 #endif 6975 #endif
6976 6976
6977 bnx2x_phy_probe(&bp->link_params); 6977 bnx2x_phy_probe(&bp->link_params);
6978 6978
6979 return 0; 6979 return 0;
6980 } 6980 }
6981 6981
6982 6982
6983 void bnx2x_free_mem(struct bnx2x *bp) 6983 void bnx2x_free_mem(struct bnx2x *bp)
6984 { 6984 {
6985 /* fastpath */ 6985 /* fastpath */
6986 bnx2x_free_fp_mem(bp); 6986 bnx2x_free_fp_mem(bp);
6987 /* end of fastpath */ 6987 /* end of fastpath */
6988 6988
6989 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 6989 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6990 sizeof(struct host_sp_status_block)); 6990 sizeof(struct host_sp_status_block));
6991 6991
6992 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 6992 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6993 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6993 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6994 6994
6995 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 6995 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6996 sizeof(struct bnx2x_slowpath)); 6996 sizeof(struct bnx2x_slowpath));
6997 6997
6998 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, 6998 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6999 bp->context.size); 6999 bp->context.size);
7000 7000
7001 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 7001 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7002 7002
7003 BNX2X_FREE(bp->ilt->lines); 7003 BNX2X_FREE(bp->ilt->lines);
7004 7004
7005 #ifdef BCM_CNIC 7005 #ifdef BCM_CNIC
7006 if (!CHIP_IS_E1x(bp)) 7006 if (!CHIP_IS_E1x(bp))
7007 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 7007 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7008 sizeof(struct host_hc_status_block_e2)); 7008 sizeof(struct host_hc_status_block_e2));
7009 else 7009 else
7010 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 7010 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7011 sizeof(struct host_hc_status_block_e1x)); 7011 sizeof(struct host_hc_status_block_e1x));
7012 7012
7013 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 7013 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7014 #endif 7014 #endif
7015 7015
7016 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 7016 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7017 7017
7018 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 7018 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7019 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7019 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7020 } 7020 }
7021 7021
7022 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) 7022 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7023 { 7023 {
7024 int num_groups; 7024 int num_groups;
7025 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; 7025 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
7026 7026
7027 /* number of queues for statistics is number of eth queues + FCoE */ 7027 /* number of queues for statistics is number of eth queues + FCoE */
7028 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; 7028 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
7029 7029
7030 /* Total number of FW statistics requests = 7030 /* Total number of FW statistics requests =
7031 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + 7031 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7032 * num of queues 7032 * num of queues
7033 */ 7033 */
7034 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; 7034 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
7035 7035
7036 7036
7037 /* Request is built from stats_query_header and an array of 7037 /* Request is built from stats_query_header and an array of
7038 * stats_query_cmd_group each of which contains 7038 * stats_query_cmd_group each of which contains
7039 * STATS_QUERY_CMD_COUNT rules. The real number or requests is 7039 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7040 * configured in the stats_query_header. 7040 * configured in the stats_query_header.
7041 */ 7041 */
7042 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + 7042 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7043 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); 7043 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
7044 7044
7045 bp->fw_stats_req_sz = sizeof(struct stats_query_header) + 7045 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7046 num_groups * sizeof(struct stats_query_cmd_group); 7046 num_groups * sizeof(struct stats_query_cmd_group);
7047 7047
7048 /* Data for statistics requests + stats_conter 7048 /* Data for statistics requests + stats_conter
7049 * 7049 *
7050 * stats_counter holds per-STORM counters that are incremented 7050 * stats_counter holds per-STORM counters that are incremented
7051 * when STORM has finished with the current request. 7051 * when STORM has finished with the current request.
7052 * 7052 *
7053 * memory for FCoE offloaded statistics are counted anyway, 7053 * memory for FCoE offloaded statistics are counted anyway,
7054 * even if they will not be sent. 7054 * even if they will not be sent.
7055 */ 7055 */
7056 bp->fw_stats_data_sz = sizeof(struct per_port_stats) + 7056 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7057 sizeof(struct per_pf_stats) + 7057 sizeof(struct per_pf_stats) +
7058 sizeof(struct fcoe_statistics_params) + 7058 sizeof(struct fcoe_statistics_params) +
7059 sizeof(struct per_queue_stats) * num_queue_stats + 7059 sizeof(struct per_queue_stats) * num_queue_stats +
7060 sizeof(struct stats_counter); 7060 sizeof(struct stats_counter);
7061 7061
7062 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, 7062 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7063 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7063 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7064 7064
7065 /* Set shortcuts */ 7065 /* Set shortcuts */
7066 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; 7066 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7067 bp->fw_stats_req_mapping = bp->fw_stats_mapping; 7067 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7068 7068
7069 bp->fw_stats_data = (struct bnx2x_fw_stats_data *) 7069 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7070 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); 7070 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7071 7071
7072 bp->fw_stats_data_mapping = bp->fw_stats_mapping + 7072 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7073 bp->fw_stats_req_sz; 7073 bp->fw_stats_req_sz;
7074 return 0; 7074 return 0;
7075 7075
7076 alloc_mem_err: 7076 alloc_mem_err:
7077 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7077 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7078 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7078 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7079 return -ENOMEM; 7079 return -ENOMEM;
7080 } 7080 }
7081 7081
7082 7082
7083 int bnx2x_alloc_mem(struct bnx2x *bp) 7083 int bnx2x_alloc_mem(struct bnx2x *bp)
7084 { 7084 {
7085 #ifdef BCM_CNIC 7085 #ifdef BCM_CNIC
7086 if (!CHIP_IS_E1x(bp)) 7086 if (!CHIP_IS_E1x(bp))
7087 /* size = the status block + ramrod buffers */ 7087 /* size = the status block + ramrod buffers */
7088 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 7088 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7089 sizeof(struct host_hc_status_block_e2)); 7089 sizeof(struct host_hc_status_block_e2));
7090 else 7090 else
7091 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, 7091 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
7092 sizeof(struct host_hc_status_block_e1x)); 7092 sizeof(struct host_hc_status_block_e1x));
7093 7093
7094 /* allocate searcher T2 table */ 7094 /* allocate searcher T2 table */
7095 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7095 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7096 #endif 7096 #endif
7097 7097
7098 7098
7099 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 7099 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7100 sizeof(struct host_sp_status_block)); 7100 sizeof(struct host_sp_status_block));
7101 7101
7102 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 7102 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7103 sizeof(struct bnx2x_slowpath)); 7103 sizeof(struct bnx2x_slowpath));
7104 7104
7105 /* Allocated memory for FW statistics */ 7105 /* Allocated memory for FW statistics */
7106 if (bnx2x_alloc_fw_stats_mem(bp)) 7106 if (bnx2x_alloc_fw_stats_mem(bp))
7107 goto alloc_mem_err; 7107 goto alloc_mem_err;
7108 7108
7109 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 7109 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7110 7110
7111 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, 7111 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
7112 bp->context.size); 7112 bp->context.size);
7113 7113
7114 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 7114 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7115 7115
7116 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 7116 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7117 goto alloc_mem_err; 7117 goto alloc_mem_err;
7118 7118
7119 /* Slow path ring */ 7119 /* Slow path ring */
7120 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 7120 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7121 7121
7122 /* EQ */ 7122 /* EQ */
7123 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 7123 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7124 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7124 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7125 7125
7126 7126
7127 /* fastpath */ 7127 /* fastpath */
7128 /* need to be done at the end, since it's self adjusting to amount 7128 /* need to be done at the end, since it's self adjusting to amount
7129 * of memory available for RSS queues 7129 * of memory available for RSS queues
7130 */ 7130 */
7131 if (bnx2x_alloc_fp_mem(bp)) 7131 if (bnx2x_alloc_fp_mem(bp))
7132 goto alloc_mem_err; 7132 goto alloc_mem_err;
7133 return 0; 7133 return 0;
7134 7134
7135 alloc_mem_err: 7135 alloc_mem_err:
7136 bnx2x_free_mem(bp); 7136 bnx2x_free_mem(bp);
7137 return -ENOMEM; 7137 return -ENOMEM;
7138 } 7138 }
7139 7139
7140 /* 7140 /*
7141 * Init service functions 7141 * Init service functions
7142 */ 7142 */
7143 7143
7144 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 7144 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7145 struct bnx2x_vlan_mac_obj *obj, bool set, 7145 struct bnx2x_vlan_mac_obj *obj, bool set,
7146 int mac_type, unsigned long *ramrod_flags) 7146 int mac_type, unsigned long *ramrod_flags)
7147 { 7147 {
7148 int rc; 7148 int rc;
7149 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 7149 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7150 7150
7151 memset(&ramrod_param, 0, sizeof(ramrod_param)); 7151 memset(&ramrod_param, 0, sizeof(ramrod_param));
7152 7152
7153 /* Fill general parameters */ 7153 /* Fill general parameters */
7154 ramrod_param.vlan_mac_obj = obj; 7154 ramrod_param.vlan_mac_obj = obj;
7155 ramrod_param.ramrod_flags = *ramrod_flags; 7155 ramrod_param.ramrod_flags = *ramrod_flags;
7156 7156
7157 /* Fill a user request section if needed */ 7157 /* Fill a user request section if needed */
7158 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 7158 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7159 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 7159 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7160 7160
7161 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 7161 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7162 7162
7163 /* Set the command: ADD or DEL */ 7163 /* Set the command: ADD or DEL */
7164 if (set) 7164 if (set)
7165 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 7165 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7166 else 7166 else
7167 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 7167 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7168 } 7168 }
7169 7169
7170 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 7170 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7171 if (rc < 0) 7171 if (rc < 0)
7172 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 7172 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7173 return rc; 7173 return rc;
7174 } 7174 }
7175 7175
7176 int bnx2x_del_all_macs(struct bnx2x *bp, 7176 int bnx2x_del_all_macs(struct bnx2x *bp,
7177 struct bnx2x_vlan_mac_obj *mac_obj, 7177 struct bnx2x_vlan_mac_obj *mac_obj,
7178 int mac_type, bool wait_for_comp) 7178 int mac_type, bool wait_for_comp)
7179 { 7179 {
7180 int rc; 7180 int rc;
7181 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 7181 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7182 7182
7183 /* Wait for completion of requested */ 7183 /* Wait for completion of requested */
7184 if (wait_for_comp) 7184 if (wait_for_comp)
7185 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7185 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7186 7186
7187 /* Set the mac type of addresses we want to clear */ 7187 /* Set the mac type of addresses we want to clear */
7188 __set_bit(mac_type, &vlan_mac_flags); 7188 __set_bit(mac_type, &vlan_mac_flags);
7189 7189
7190 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 7190 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7191 if (rc < 0) 7191 if (rc < 0)
7192 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 7192 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7193 7193
7194 return rc; 7194 return rc;
7195 } 7195 }
7196 7196
7197 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 7197 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7198 { 7198 {
7199 unsigned long ramrod_flags = 0; 7199 unsigned long ramrod_flags = 0;
7200 7200
7201 #ifdef BCM_CNIC 7201 #ifdef BCM_CNIC
7202 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) { 7202 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) {
7203 DP(NETIF_MSG_IFUP, "Ignoring Zero MAC for iSCSI SD mode\n"); 7203 DP(NETIF_MSG_IFUP, "Ignoring Zero MAC for iSCSI SD mode\n");
7204 return 0; 7204 return 0;
7205 } 7205 }
7206 #endif 7206 #endif
7207 7207
7208 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 7208 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7209 7209
7210 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7210 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7211 /* Eth MAC is set on RSS leading client (fp[0]) */ 7211 /* Eth MAC is set on RSS leading client (fp[0]) */
7212 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, 7212 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
7213 BNX2X_ETH_MAC, &ramrod_flags); 7213 BNX2X_ETH_MAC, &ramrod_flags);
7214 } 7214 }
7215 7215
7216 int bnx2x_setup_leading(struct bnx2x *bp) 7216 int bnx2x_setup_leading(struct bnx2x *bp)
7217 { 7217 {
7218 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 7218 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7219 } 7219 }
7220 7220
7221 /** 7221 /**
7222 * bnx2x_set_int_mode - configure interrupt mode 7222 * bnx2x_set_int_mode - configure interrupt mode
7223 * 7223 *
7224 * @bp: driver handle 7224 * @bp: driver handle
7225 * 7225 *
7226 * In case of MSI-X it will also try to enable MSI-X. 7226 * In case of MSI-X it will also try to enable MSI-X.
7227 */ 7227 */
7228 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) 7228 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
7229 { 7229 {
7230 switch (int_mode) { 7230 switch (int_mode) {
7231 case INT_MODE_MSI: 7231 case INT_MODE_MSI:
7232 bnx2x_enable_msi(bp); 7232 bnx2x_enable_msi(bp);
7233 /* falling through... */ 7233 /* falling through... */
7234 case INT_MODE_INTx: 7234 case INT_MODE_INTx:
7235 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7235 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7236 DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); 7236 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
7237 break; 7237 break;
7238 default: 7238 default:
7239 /* Set number of queues according to bp->multi_mode value */ 7239 /* Set number of queues according to bp->multi_mode value */
7240 bnx2x_set_num_queues(bp); 7240 bnx2x_set_num_queues(bp);
7241 7241
7242 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", 7242 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7243 bp->num_queues); 7243 bp->num_queues);
7244 7244
7245 /* if we can't use MSI-X we only need one fp, 7245 /* if we can't use MSI-X we only need one fp,
7246 * so try to enable MSI-X with the requested number of fp's 7246 * so try to enable MSI-X with the requested number of fp's
7247 * and fallback to MSI or legacy INTx with one fp 7247 * and fallback to MSI or legacy INTx with one fp
7248 */ 7248 */
7249 if (bnx2x_enable_msix(bp)) { 7249 if (bnx2x_enable_msix(bp)) {
7250 /* failed to enable MSI-X */ 7250 /* failed to enable MSI-X */
7251 if (bp->multi_mode) 7251 if (bp->multi_mode)
7252 DP(NETIF_MSG_IFUP, 7252 DP(NETIF_MSG_IFUP,
7253 "Multi requested but failed to " 7253 "Multi requested but failed to "
7254 "enable MSI-X (%d), " 7254 "enable MSI-X (%d), "
7255 "set number of queues to %d\n", 7255 "set number of queues to %d\n",
7256 bp->num_queues, 7256 bp->num_queues,
7257 1 + NON_ETH_CONTEXT_USE); 7257 1 + NON_ETH_CONTEXT_USE);
7258 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7258 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7259 7259
7260 /* Try to enable MSI */ 7260 /* Try to enable MSI */
7261 if (!(bp->flags & DISABLE_MSI_FLAG)) 7261 if (!(bp->flags & DISABLE_MSI_FLAG))
7262 bnx2x_enable_msi(bp); 7262 bnx2x_enable_msi(bp);
7263 } 7263 }
7264 break; 7264 break;
7265 } 7265 }
7266 } 7266 }
7267 7267
7268 /* must be called prioir to any HW initializations */ 7268 /* must be called prioir to any HW initializations */
7269 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7269 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7270 { 7270 {
7271 return L2_ILT_LINES(bp); 7271 return L2_ILT_LINES(bp);
7272 } 7272 }
7273 7273
7274 void bnx2x_ilt_set_info(struct bnx2x *bp) 7274 void bnx2x_ilt_set_info(struct bnx2x *bp)
7275 { 7275 {
7276 struct ilt_client_info *ilt_client; 7276 struct ilt_client_info *ilt_client;
7277 struct bnx2x_ilt *ilt = BP_ILT(bp); 7277 struct bnx2x_ilt *ilt = BP_ILT(bp);
7278 u16 line = 0; 7278 u16 line = 0;
7279 7279
7280 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7280 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7281 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7281 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7282 7282
7283 /* CDU */ 7283 /* CDU */
7284 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7284 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7285 ilt_client->client_num = ILT_CLIENT_CDU; 7285 ilt_client->client_num = ILT_CLIENT_CDU;
7286 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7286 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7287 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7287 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7288 ilt_client->start = line; 7288 ilt_client->start = line;
7289 line += bnx2x_cid_ilt_lines(bp); 7289 line += bnx2x_cid_ilt_lines(bp);
7290 #ifdef BCM_CNIC 7290 #ifdef BCM_CNIC
7291 line += CNIC_ILT_LINES; 7291 line += CNIC_ILT_LINES;
7292 #endif 7292 #endif
7293 ilt_client->end = line - 1; 7293 ilt_client->end = line - 1;
7294 7294
7295 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " 7295 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7296 "flags 0x%x, hw psz %d\n", 7296 "flags 0x%x, hw psz %d\n",
7297 ilt_client->start, 7297 ilt_client->start,
7298 ilt_client->end, 7298 ilt_client->end,
7299 ilt_client->page_size, 7299 ilt_client->page_size,
7300 ilt_client->flags, 7300 ilt_client->flags,
7301 ilog2(ilt_client->page_size >> 12)); 7301 ilog2(ilt_client->page_size >> 12));
7302 7302
7303 /* QM */ 7303 /* QM */
7304 if (QM_INIT(bp->qm_cid_count)) { 7304 if (QM_INIT(bp->qm_cid_count)) {
7305 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7305 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7306 ilt_client->client_num = ILT_CLIENT_QM; 7306 ilt_client->client_num = ILT_CLIENT_QM;
7307 ilt_client->page_size = QM_ILT_PAGE_SZ; 7307 ilt_client->page_size = QM_ILT_PAGE_SZ;
7308 ilt_client->flags = 0; 7308 ilt_client->flags = 0;
7309 ilt_client->start = line; 7309 ilt_client->start = line;
7310 7310
7311 /* 4 bytes for each cid */ 7311 /* 4 bytes for each cid */
7312 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7312 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7313 QM_ILT_PAGE_SZ); 7313 QM_ILT_PAGE_SZ);
7314 7314
7315 ilt_client->end = line - 1; 7315 ilt_client->end = line - 1;
7316 7316
7317 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " 7317 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7318 "flags 0x%x, hw psz %d\n", 7318 "flags 0x%x, hw psz %d\n",
7319 ilt_client->start, 7319 ilt_client->start,
7320 ilt_client->end, 7320 ilt_client->end,
7321 ilt_client->page_size, 7321 ilt_client->page_size,
7322 ilt_client->flags, 7322 ilt_client->flags,
7323 ilog2(ilt_client->page_size >> 12)); 7323 ilog2(ilt_client->page_size >> 12));
7324 7324
7325 } 7325 }
7326 /* SRC */ 7326 /* SRC */
7327 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7327 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7328 #ifdef BCM_CNIC 7328 #ifdef BCM_CNIC
7329 ilt_client->client_num = ILT_CLIENT_SRC; 7329 ilt_client->client_num = ILT_CLIENT_SRC;
7330 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7330 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7331 ilt_client->flags = 0; 7331 ilt_client->flags = 0;
7332 ilt_client->start = line; 7332 ilt_client->start = line;
7333 line += SRC_ILT_LINES; 7333 line += SRC_ILT_LINES;
7334 ilt_client->end = line - 1; 7334 ilt_client->end = line - 1;
7335 7335
7336 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " 7336 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7337 "flags 0x%x, hw psz %d\n", 7337 "flags 0x%x, hw psz %d\n",
7338 ilt_client->start, 7338 ilt_client->start,
7339 ilt_client->end, 7339 ilt_client->end,
7340 ilt_client->page_size, 7340 ilt_client->page_size,
7341 ilt_client->flags, 7341 ilt_client->flags,
7342 ilog2(ilt_client->page_size >> 12)); 7342 ilog2(ilt_client->page_size >> 12));
7343 7343
7344 #else 7344 #else
7345 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7345 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7346 #endif 7346 #endif
7347 7347
7348 /* TM */ 7348 /* TM */
7349 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 7349 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7350 #ifdef BCM_CNIC 7350 #ifdef BCM_CNIC
7351 ilt_client->client_num = ILT_CLIENT_TM; 7351 ilt_client->client_num = ILT_CLIENT_TM;
7352 ilt_client->page_size = TM_ILT_PAGE_SZ; 7352 ilt_client->page_size = TM_ILT_PAGE_SZ;
7353 ilt_client->flags = 0; 7353 ilt_client->flags = 0;
7354 ilt_client->start = line; 7354 ilt_client->start = line;
7355 line += TM_ILT_LINES; 7355 line += TM_ILT_LINES;
7356 ilt_client->end = line - 1; 7356 ilt_client->end = line - 1;
7357 7357
7358 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " 7358 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7359 "flags 0x%x, hw psz %d\n", 7359 "flags 0x%x, hw psz %d\n",
7360 ilt_client->start, 7360 ilt_client->start,
7361 ilt_client->end, 7361 ilt_client->end,
7362 ilt_client->page_size, 7362 ilt_client->page_size,
7363 ilt_client->flags, 7363 ilt_client->flags,
7364 ilog2(ilt_client->page_size >> 12)); 7364 ilog2(ilt_client->page_size >> 12));
7365 7365
7366 #else 7366 #else
7367 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7367 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7368 #endif 7368 #endif
7369 BUG_ON(line > ILT_MAX_LINES); 7369 BUG_ON(line > ILT_MAX_LINES);
7370 } 7370 }
7371 7371
7372 /** 7372 /**
7373 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 7373 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7374 * 7374 *
7375 * @bp: driver handle 7375 * @bp: driver handle
7376 * @fp: pointer to fastpath 7376 * @fp: pointer to fastpath
7377 * @init_params: pointer to parameters structure 7377 * @init_params: pointer to parameters structure
7378 * 7378 *
7379 * parameters configured: 7379 * parameters configured:
7380 * - HC configuration 7380 * - HC configuration
7381 * - Queue's CDU context 7381 * - Queue's CDU context
7382 */ 7382 */
7383 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, 7383 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7384 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 7384 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7385 { 7385 {
7386 7386
7387 u8 cos; 7387 u8 cos;
7388 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 7388 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7389 if (!IS_FCOE_FP(fp)) { 7389 if (!IS_FCOE_FP(fp)) {
7390 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 7390 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7391 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 7391 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7392 7392
7393 /* If HC is supporterd, enable host coalescing in the transition 7393 /* If HC is supporterd, enable host coalescing in the transition
7394 * to INIT state. 7394 * to INIT state.
7395 */ 7395 */
7396 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 7396 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7397 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 7397 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7398 7398
7399 /* HC rate */ 7399 /* HC rate */
7400 init_params->rx.hc_rate = bp->rx_ticks ? 7400 init_params->rx.hc_rate = bp->rx_ticks ?
7401 (1000000 / bp->rx_ticks) : 0; 7401 (1000000 / bp->rx_ticks) : 0;
7402 init_params->tx.hc_rate = bp->tx_ticks ? 7402 init_params->tx.hc_rate = bp->tx_ticks ?
7403 (1000000 / bp->tx_ticks) : 0; 7403 (1000000 / bp->tx_ticks) : 0;
7404 7404
7405 /* FW SB ID */ 7405 /* FW SB ID */
7406 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 7406 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7407 fp->fw_sb_id; 7407 fp->fw_sb_id;
7408 7408
7409 /* 7409 /*
7410 * CQ index among the SB indices: FCoE clients uses the default 7410 * CQ index among the SB indices: FCoE clients uses the default
7411 * SB, therefore it's different. 7411 * SB, therefore it's different.
7412 */ 7412 */
7413 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 7413 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7414 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 7414 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7415 } 7415 }
7416 7416
7417 /* set maximum number of COSs supported by this queue */ 7417 /* set maximum number of COSs supported by this queue */
7418 init_params->max_cos = fp->max_cos; 7418 init_params->max_cos = fp->max_cos;
7419 7419
7420 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n", 7420 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n",
7421 fp->index, init_params->max_cos); 7421 fp->index, init_params->max_cos);
7422 7422
7423 /* set the context pointers queue object */ 7423 /* set the context pointers queue object */
7424 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) 7424 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7425 init_params->cxts[cos] = 7425 init_params->cxts[cos] =
7426 &bp->context.vcxt[fp->txdata[cos].cid].eth; 7426 &bp->context.vcxt[fp->txdata[cos].cid].eth;
7427 } 7427 }
7428 7428
7429 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7429 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7430 struct bnx2x_queue_state_params *q_params, 7430 struct bnx2x_queue_state_params *q_params,
7431 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 7431 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7432 int tx_index, bool leading) 7432 int tx_index, bool leading)
7433 { 7433 {
7434 memset(tx_only_params, 0, sizeof(*tx_only_params)); 7434 memset(tx_only_params, 0, sizeof(*tx_only_params));
7435 7435
7436 /* Set the command */ 7436 /* Set the command */
7437 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 7437 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7438 7438
7439 /* Set tx-only QUEUE flags: don't zero statistics */ 7439 /* Set tx-only QUEUE flags: don't zero statistics */
7440 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 7440 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7441 7441
7442 /* choose the index of the cid to send the slow path on */ 7442 /* choose the index of the cid to send the slow path on */
7443 tx_only_params->cid_index = tx_index; 7443 tx_only_params->cid_index = tx_index;
7444 7444
7445 /* Set general TX_ONLY_SETUP parameters */ 7445 /* Set general TX_ONLY_SETUP parameters */
7446 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 7446 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7447 7447
7448 /* Set Tx TX_ONLY_SETUP parameters */ 7448 /* Set Tx TX_ONLY_SETUP parameters */
7449 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7449 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7450 7450
7451 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" 7451 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7452 "cos %d, primary cid %d, cid %d, " 7452 "cos %d, primary cid %d, cid %d, "
7453 "client id %d, sp-client id %d, flags %lx\n", 7453 "client id %d, sp-client id %d, flags %lx\n",
7454 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7454 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7455 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7455 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7456 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7456 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7457 7457
7458 /* send the ramrod */ 7458 /* send the ramrod */
7459 return bnx2x_queue_state_change(bp, q_params); 7459 return bnx2x_queue_state_change(bp, q_params);
7460 } 7460 }
7461 7461
7462 7462
7463 /** 7463 /**
7464 * bnx2x_setup_queue - setup queue 7464 * bnx2x_setup_queue - setup queue
7465 * 7465 *
7466 * @bp: driver handle 7466 * @bp: driver handle
7467 * @fp: pointer to fastpath 7467 * @fp: pointer to fastpath
7468 * @leading: is leading 7468 * @leading: is leading
7469 * 7469 *
7470 * This function performs 2 steps in a Queue state machine 7470 * This function performs 2 steps in a Queue state machine
7471 * actually: 1) RESET->INIT 2) INIT->SETUP 7471 * actually: 1) RESET->INIT 2) INIT->SETUP
7472 */ 7472 */
7473 7473
7474 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7474 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7475 bool leading) 7475 bool leading)
7476 { 7476 {
7477 struct bnx2x_queue_state_params q_params = {0}; 7477 struct bnx2x_queue_state_params q_params = {0};
7478 struct bnx2x_queue_setup_params *setup_params = 7478 struct bnx2x_queue_setup_params *setup_params =
7479 &q_params.params.setup; 7479 &q_params.params.setup;
7480 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 7480 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7481 &q_params.params.tx_only; 7481 &q_params.params.tx_only;
7482 int rc; 7482 int rc;
7483 u8 tx_index; 7483 u8 tx_index;
7484 7484
7485 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index); 7485 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index);
7486 7486
7487 /* reset IGU state skip FCoE L2 queue */ 7487 /* reset IGU state skip FCoE L2 queue */
7488 if (!IS_FCOE_FP(fp)) 7488 if (!IS_FCOE_FP(fp))
7489 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 7489 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7490 IGU_INT_ENABLE, 0); 7490 IGU_INT_ENABLE, 0);
7491 7491
7492 q_params.q_obj = &fp->q_obj; 7492 q_params.q_obj = &fp->q_obj;
7493 /* We want to wait for completion in this context */ 7493 /* We want to wait for completion in this context */
7494 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7494 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7495 7495
7496 /* Prepare the INIT parameters */ 7496 /* Prepare the INIT parameters */
7497 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 7497 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7498 7498
7499 /* Set the command */ 7499 /* Set the command */
7500 q_params.cmd = BNX2X_Q_CMD_INIT; 7500 q_params.cmd = BNX2X_Q_CMD_INIT;
7501 7501
7502 /* Change the state to INIT */ 7502 /* Change the state to INIT */
7503 rc = bnx2x_queue_state_change(bp, &q_params); 7503 rc = bnx2x_queue_state_change(bp, &q_params);
7504 if (rc) { 7504 if (rc) {
7505 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 7505 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7506 return rc; 7506 return rc;
7507 } 7507 }
7508 7508
7509 DP(BNX2X_MSG_SP, "init complete\n"); 7509 DP(BNX2X_MSG_SP, "init complete\n");
7510 7510
7511 7511
7512 /* Now move the Queue to the SETUP state... */ 7512 /* Now move the Queue to the SETUP state... */
7513 memset(setup_params, 0, sizeof(*setup_params)); 7513 memset(setup_params, 0, sizeof(*setup_params));
7514 7514
7515 /* Set QUEUE flags */ 7515 /* Set QUEUE flags */
7516 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 7516 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7517 7517
7518 /* Set general SETUP parameters */ 7518 /* Set general SETUP parameters */
7519 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 7519 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7520 FIRST_TX_COS_INDEX); 7520 FIRST_TX_COS_INDEX);
7521 7521
7522 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 7522 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7523 &setup_params->rxq_params); 7523 &setup_params->rxq_params);
7524 7524
7525 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 7525 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7526 FIRST_TX_COS_INDEX); 7526 FIRST_TX_COS_INDEX);
7527 7527
7528 /* Set the command */ 7528 /* Set the command */
7529 q_params.cmd = BNX2X_Q_CMD_SETUP; 7529 q_params.cmd = BNX2X_Q_CMD_SETUP;
7530 7530
7531 /* Change the state to SETUP */ 7531 /* Change the state to SETUP */
7532 rc = bnx2x_queue_state_change(bp, &q_params); 7532 rc = bnx2x_queue_state_change(bp, &q_params);
7533 if (rc) { 7533 if (rc) {
7534 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 7534 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7535 return rc; 7535 return rc;
7536 } 7536 }
7537 7537
7538 /* loop through the relevant tx-only indices */ 7538 /* loop through the relevant tx-only indices */
7539 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7539 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7540 tx_index < fp->max_cos; 7540 tx_index < fp->max_cos;
7541 tx_index++) { 7541 tx_index++) {
7542 7542
7543 /* prepare and send tx-only ramrod*/ 7543 /* prepare and send tx-only ramrod*/
7544 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 7544 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7545 tx_only_params, tx_index, leading); 7545 tx_only_params, tx_index, leading);
7546 if (rc) { 7546 if (rc) {
7547 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 7547 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7548 fp->index, tx_index); 7548 fp->index, tx_index);
7549 return rc; 7549 return rc;
7550 } 7550 }
7551 } 7551 }
7552 7552
7553 return rc; 7553 return rc;
7554 } 7554 }
7555 7555
7556 static int bnx2x_stop_queue(struct bnx2x *bp, int index) 7556 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7557 { 7557 {
7558 struct bnx2x_fastpath *fp = &bp->fp[index]; 7558 struct bnx2x_fastpath *fp = &bp->fp[index];
7559 struct bnx2x_fp_txdata *txdata; 7559 struct bnx2x_fp_txdata *txdata;
7560 struct bnx2x_queue_state_params q_params = {0}; 7560 struct bnx2x_queue_state_params q_params = {0};
7561 int rc, tx_index; 7561 int rc, tx_index;
7562 7562
7563 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid); 7563 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid);
7564 7564
7565 q_params.q_obj = &fp->q_obj; 7565 q_params.q_obj = &fp->q_obj;
7566 /* We want to wait for completion in this context */ 7566 /* We want to wait for completion in this context */
7567 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7567 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7568 7568
7569 7569
7570 /* close tx-only connections */ 7570 /* close tx-only connections */
7571 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7571 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7572 tx_index < fp->max_cos; 7572 tx_index < fp->max_cos;
7573 tx_index++){ 7573 tx_index++){
7574 7574
7575 /* ascertain this is a normal queue*/ 7575 /* ascertain this is a normal queue*/
7576 txdata = &fp->txdata[tx_index]; 7576 txdata = &fp->txdata[tx_index];
7577 7577
7578 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n", 7578 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n",
7579 txdata->txq_index); 7579 txdata->txq_index);
7580 7580
7581 /* send halt terminate on tx-only connection */ 7581 /* send halt terminate on tx-only connection */
7582 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7582 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7583 memset(&q_params.params.terminate, 0, 7583 memset(&q_params.params.terminate, 0,
7584 sizeof(q_params.params.terminate)); 7584 sizeof(q_params.params.terminate));
7585 q_params.params.terminate.cid_index = tx_index; 7585 q_params.params.terminate.cid_index = tx_index;
7586 7586
7587 rc = bnx2x_queue_state_change(bp, &q_params); 7587 rc = bnx2x_queue_state_change(bp, &q_params);
7588 if (rc) 7588 if (rc)
7589 return rc; 7589 return rc;
7590 7590
7591 /* send halt terminate on tx-only connection */ 7591 /* send halt terminate on tx-only connection */
7592 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7592 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7593 memset(&q_params.params.cfc_del, 0, 7593 memset(&q_params.params.cfc_del, 0,
7594 sizeof(q_params.params.cfc_del)); 7594 sizeof(q_params.params.cfc_del));
7595 q_params.params.cfc_del.cid_index = tx_index; 7595 q_params.params.cfc_del.cid_index = tx_index;
7596 rc = bnx2x_queue_state_change(bp, &q_params); 7596 rc = bnx2x_queue_state_change(bp, &q_params);
7597 if (rc) 7597 if (rc)
7598 return rc; 7598 return rc;
7599 } 7599 }
7600 /* Stop the primary connection: */ 7600 /* Stop the primary connection: */
7601 /* ...halt the connection */ 7601 /* ...halt the connection */
7602 q_params.cmd = BNX2X_Q_CMD_HALT; 7602 q_params.cmd = BNX2X_Q_CMD_HALT;
7603 rc = bnx2x_queue_state_change(bp, &q_params); 7603 rc = bnx2x_queue_state_change(bp, &q_params);
7604 if (rc) 7604 if (rc)
7605 return rc; 7605 return rc;
7606 7606
7607 /* ...terminate the connection */ 7607 /* ...terminate the connection */
7608 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7608 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7609 memset(&q_params.params.terminate, 0, 7609 memset(&q_params.params.terminate, 0,
7610 sizeof(q_params.params.terminate)); 7610 sizeof(q_params.params.terminate));
7611 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 7611 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
7612 rc = bnx2x_queue_state_change(bp, &q_params); 7612 rc = bnx2x_queue_state_change(bp, &q_params);
7613 if (rc) 7613 if (rc)
7614 return rc; 7614 return rc;
7615 /* ...delete cfc entry */ 7615 /* ...delete cfc entry */
7616 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7616 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7617 memset(&q_params.params.cfc_del, 0, 7617 memset(&q_params.params.cfc_del, 0,
7618 sizeof(q_params.params.cfc_del)); 7618 sizeof(q_params.params.cfc_del));
7619 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 7619 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
7620 return bnx2x_queue_state_change(bp, &q_params); 7620 return bnx2x_queue_state_change(bp, &q_params);
7621 } 7621 }
7622 7622
7623 7623
7624 static void bnx2x_reset_func(struct bnx2x *bp) 7624 static void bnx2x_reset_func(struct bnx2x *bp)
7625 { 7625 {
7626 int port = BP_PORT(bp); 7626 int port = BP_PORT(bp);
7627 int func = BP_FUNC(bp); 7627 int func = BP_FUNC(bp);
7628 int i; 7628 int i;
7629 7629
7630 /* Disable the function in the FW */ 7630 /* Disable the function in the FW */
7631 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 7631 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7632 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 7632 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7633 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 7633 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7634 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 7634 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7635 7635
7636 /* FP SBs */ 7636 /* FP SBs */
7637 for_each_eth_queue(bp, i) { 7637 for_each_eth_queue(bp, i) {
7638 struct bnx2x_fastpath *fp = &bp->fp[i]; 7638 struct bnx2x_fastpath *fp = &bp->fp[i];
7639 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7639 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7640 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 7640 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7641 SB_DISABLED); 7641 SB_DISABLED);
7642 } 7642 }
7643 7643
7644 #ifdef BCM_CNIC 7644 #ifdef BCM_CNIC
7645 /* CNIC SB */ 7645 /* CNIC SB */
7646 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7646 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7647 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), 7647 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7648 SB_DISABLED); 7648 SB_DISABLED);
7649 #endif 7649 #endif
7650 /* SP SB */ 7650 /* SP SB */
7651 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7651 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7652 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 7652 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7653 SB_DISABLED); 7653 SB_DISABLED);
7654 7654
7655 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 7655 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7656 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 7656 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7657 0); 7657 0);
7658 7658
7659 /* Configure IGU */ 7659 /* Configure IGU */
7660 if (bp->common.int_block == INT_BLOCK_HC) { 7660 if (bp->common.int_block == INT_BLOCK_HC) {
7661 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7661 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7662 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7662 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7663 } else { 7663 } else {
7664 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7664 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7665 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7665 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7666 } 7666 }
7667 7667
7668 #ifdef BCM_CNIC 7668 #ifdef BCM_CNIC
7669 /* Disable Timer scan */ 7669 /* Disable Timer scan */
7670 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 7670 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7671 /* 7671 /*
7672 * Wait for at least 10ms and up to 2 second for the timers scan to 7672 * Wait for at least 10ms and up to 2 second for the timers scan to
7673 * complete 7673 * complete
7674 */ 7674 */
7675 for (i = 0; i < 200; i++) { 7675 for (i = 0; i < 200; i++) {
7676 msleep(10); 7676 msleep(10);
7677 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 7677 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7678 break; 7678 break;
7679 } 7679 }
7680 #endif 7680 #endif
7681 /* Clear ILT */ 7681 /* Clear ILT */
7682 bnx2x_clear_func_ilt(bp, func); 7682 bnx2x_clear_func_ilt(bp, func);
7683 7683
7684 /* Timers workaround bug for E2: if this is vnic-3, 7684 /* Timers workaround bug for E2: if this is vnic-3,
7685 * we need to set the entire ilt range for this timers. 7685 * we need to set the entire ilt range for this timers.
7686 */ 7686 */
7687 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 7687 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7688 struct ilt_client_info ilt_cli; 7688 struct ilt_client_info ilt_cli;
7689 /* use dummy TM client */ 7689 /* use dummy TM client */
7690 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7690 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7691 ilt_cli.start = 0; 7691 ilt_cli.start = 0;
7692 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7692 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7693 ilt_cli.client_num = ILT_CLIENT_TM; 7693 ilt_cli.client_num = ILT_CLIENT_TM;
7694 7694
7695 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 7695 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7696 } 7696 }
7697 7697
7698 /* this assumes that reset_port() called before reset_func()*/ 7698 /* this assumes that reset_port() called before reset_func()*/
7699 if (!CHIP_IS_E1x(bp)) 7699 if (!CHIP_IS_E1x(bp))
7700 bnx2x_pf_disable(bp); 7700 bnx2x_pf_disable(bp);
7701 7701
7702 bp->dmae_ready = 0; 7702 bp->dmae_ready = 0;
7703 } 7703 }
7704 7704
7705 static void bnx2x_reset_port(struct bnx2x *bp) 7705 static void bnx2x_reset_port(struct bnx2x *bp)
7706 { 7706 {
7707 int port = BP_PORT(bp); 7707 int port = BP_PORT(bp);
7708 u32 val; 7708 u32 val;
7709 7709
7710 /* Reset physical Link */ 7710 /* Reset physical Link */
7711 bnx2x__link_reset(bp); 7711 bnx2x__link_reset(bp);
7712 7712
7713 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7713 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7714 7714
7715 /* Do not rcv packets to BRB */ 7715 /* Do not rcv packets to BRB */
7716 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 7716 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7717 /* Do not direct rcv packets that are not for MCP to the BRB */ 7717 /* Do not direct rcv packets that are not for MCP to the BRB */
7718 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 7718 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7719 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 7719 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7720 7720
7721 /* Configure AEU */ 7721 /* Configure AEU */
7722 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 7722 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7723 7723
7724 msleep(100); 7724 msleep(100);
7725 /* Check for BRB port occupancy */ 7725 /* Check for BRB port occupancy */
7726 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 7726 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7727 if (val) 7727 if (val)
7728 DP(NETIF_MSG_IFDOWN, 7728 DP(NETIF_MSG_IFDOWN,
7729 "BRB1 is not empty %d blocks are occupied\n", val); 7729 "BRB1 is not empty %d blocks are occupied\n", val);
7730 7730
7731 /* TODO: Close Doorbell port? */ 7731 /* TODO: Close Doorbell port? */
7732 } 7732 }
7733 7733
7734 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 7734 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7735 { 7735 {
7736 struct bnx2x_func_state_params func_params = {0}; 7736 struct bnx2x_func_state_params func_params = {0};
7737 7737
7738 /* Prepare parameters for function state transitions */ 7738 /* Prepare parameters for function state transitions */
7739 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7739 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7740 7740
7741 func_params.f_obj = &bp->func_obj; 7741 func_params.f_obj = &bp->func_obj;
7742 func_params.cmd = BNX2X_F_CMD_HW_RESET; 7742 func_params.cmd = BNX2X_F_CMD_HW_RESET;
7743 7743
7744 func_params.params.hw_init.load_phase = load_code; 7744 func_params.params.hw_init.load_phase = load_code;
7745 7745
7746 return bnx2x_func_state_change(bp, &func_params); 7746 return bnx2x_func_state_change(bp, &func_params);
7747 } 7747 }
7748 7748
7749 static inline int bnx2x_func_stop(struct bnx2x *bp) 7749 static inline int bnx2x_func_stop(struct bnx2x *bp)
7750 { 7750 {
7751 struct bnx2x_func_state_params func_params = {0}; 7751 struct bnx2x_func_state_params func_params = {0};
7752 int rc; 7752 int rc;
7753 7753
7754 /* Prepare parameters for function state transitions */ 7754 /* Prepare parameters for function state transitions */
7755 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7755 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7756 func_params.f_obj = &bp->func_obj; 7756 func_params.f_obj = &bp->func_obj;
7757 func_params.cmd = BNX2X_F_CMD_STOP; 7757 func_params.cmd = BNX2X_F_CMD_STOP;
7758 7758
7759 /* 7759 /*
7760 * Try to stop the function the 'good way'. If fails (in case 7760 * Try to stop the function the 'good way'. If fails (in case
7761 * of a parity error during bnx2x_chip_cleanup()) and we are 7761 * of a parity error during bnx2x_chip_cleanup()) and we are
7762 * not in a debug mode, perform a state transaction in order to 7762 * not in a debug mode, perform a state transaction in order to
7763 * enable further HW_RESET transaction. 7763 * enable further HW_RESET transaction.
7764 */ 7764 */
7765 rc = bnx2x_func_state_change(bp, &func_params); 7765 rc = bnx2x_func_state_change(bp, &func_params);
7766 if (rc) { 7766 if (rc) {
7767 #ifdef BNX2X_STOP_ON_ERROR 7767 #ifdef BNX2X_STOP_ON_ERROR
7768 return rc; 7768 return rc;
7769 #else 7769 #else
7770 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " 7770 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7771 "transaction\n"); 7771 "transaction\n");
7772 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7772 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7773 return bnx2x_func_state_change(bp, &func_params); 7773 return bnx2x_func_state_change(bp, &func_params);
7774 #endif 7774 #endif
7775 } 7775 }
7776 7776
7777 return 0; 7777 return 0;
7778 } 7778 }
7779 7779
7780 /** 7780 /**
7781 * bnx2x_send_unload_req - request unload mode from the MCP. 7781 * bnx2x_send_unload_req - request unload mode from the MCP.
7782 * 7782 *
7783 * @bp: driver handle 7783 * @bp: driver handle
7784 * @unload_mode: requested function's unload mode 7784 * @unload_mode: requested function's unload mode
7785 * 7785 *
7786 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 7786 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7787 */ 7787 */
7788 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 7788 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7789 { 7789 {
7790 u32 reset_code = 0; 7790 u32 reset_code = 0;
7791 int port = BP_PORT(bp); 7791 int port = BP_PORT(bp);
7792 7792
7793 /* Select the UNLOAD request mode */ 7793 /* Select the UNLOAD request mode */
7794 if (unload_mode == UNLOAD_NORMAL) 7794 if (unload_mode == UNLOAD_NORMAL)
7795 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7795 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7796 7796
7797 else if (bp->flags & NO_WOL_FLAG) 7797 else if (bp->flags & NO_WOL_FLAG)
7798 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 7798 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7799 7799
7800 else if (bp->wol) { 7800 else if (bp->wol) {
7801 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7801 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7802 u8 *mac_addr = bp->dev->dev_addr; 7802 u8 *mac_addr = bp->dev->dev_addr;
7803 u32 val; 7803 u32 val;
7804 u16 pmc; 7804 u16 pmc;
7805 7805
7806 /* The mac address is written to entries 1-4 to 7806 /* The mac address is written to entries 1-4 to
7807 * preserve entry 0 which is used by the PMF 7807 * preserve entry 0 which is used by the PMF
7808 */ 7808 */
7809 u8 entry = (BP_VN(bp) + 1)*8; 7809 u8 entry = (BP_VN(bp) + 1)*8;
7810 7810
7811 val = (mac_addr[0] << 8) | mac_addr[1]; 7811 val = (mac_addr[0] << 8) | mac_addr[1];
7812 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7812 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7813 7813
7814 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 7814 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7815 (mac_addr[4] << 8) | mac_addr[5]; 7815 (mac_addr[4] << 8) | mac_addr[5];
7816 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 7816 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7817 7817
7818 /* Enable the PME and clear the status */ 7818 /* Enable the PME and clear the status */
7819 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 7819 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
7820 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 7820 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
7821 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 7821 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
7822 7822
7823 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 7823 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7824 7824
7825 } else 7825 } else
7826 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7826 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7827 7827
7828 /* Send the request to the MCP */ 7828 /* Send the request to the MCP */
7829 if (!BP_NOMCP(bp)) 7829 if (!BP_NOMCP(bp))
7830 reset_code = bnx2x_fw_command(bp, reset_code, 0); 7830 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7831 else { 7831 else {
7832 int path = BP_PATH(bp); 7832 int path = BP_PATH(bp);
7833 7833
7834 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " 7834 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7835 "%d, %d, %d\n", 7835 "%d, %d, %d\n",
7836 path, load_count[path][0], load_count[path][1], 7836 path, load_count[path][0], load_count[path][1],
7837 load_count[path][2]); 7837 load_count[path][2]);
7838 load_count[path][0]--; 7838 load_count[path][0]--;
7839 load_count[path][1 + port]--; 7839 load_count[path][1 + port]--;
7840 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " 7840 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7841 "%d, %d, %d\n", 7841 "%d, %d, %d\n",
7842 path, load_count[path][0], load_count[path][1], 7842 path, load_count[path][0], load_count[path][1],
7843 load_count[path][2]); 7843 load_count[path][2]);
7844 if (load_count[path][0] == 0) 7844 if (load_count[path][0] == 0)
7845 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7845 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7846 else if (load_count[path][1 + port] == 0) 7846 else if (load_count[path][1 + port] == 0)
7847 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7847 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7848 else 7848 else
7849 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7849 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7850 } 7850 }
7851 7851
7852 return reset_code; 7852 return reset_code;
7853 } 7853 }
7854 7854
7855 /** 7855 /**
7856 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 7856 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7857 * 7857 *
7858 * @bp: driver handle 7858 * @bp: driver handle
7859 */ 7859 */
7860 void bnx2x_send_unload_done(struct bnx2x *bp) 7860 void bnx2x_send_unload_done(struct bnx2x *bp)
7861 { 7861 {
7862 /* Report UNLOAD_DONE to MCP */ 7862 /* Report UNLOAD_DONE to MCP */
7863 if (!BP_NOMCP(bp)) 7863 if (!BP_NOMCP(bp))
7864 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 7864 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7865 } 7865 }
7866 7866
7867 static inline int bnx2x_func_wait_started(struct bnx2x *bp) 7867 static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7868 { 7868 {
7869 int tout = 50; 7869 int tout = 50;
7870 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 7870 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7871 7871
7872 if (!bp->port.pmf) 7872 if (!bp->port.pmf)
7873 return 0; 7873 return 0;
7874 7874
7875 /* 7875 /*
7876 * (assumption: No Attention from MCP at this stage) 7876 * (assumption: No Attention from MCP at this stage)
7877 * PMF probably in the middle of TXdisable/enable transaction 7877 * PMF probably in the middle of TXdisable/enable transaction
7878 * 1. Sync IRS for default SB 7878 * 1. Sync IRS for default SB
7879 * 2. Sync SP queue - this guarantes us that attention handling started 7879 * 2. Sync SP queue - this guarantes us that attention handling started
7880 * 3. Wait, that TXdisable/enable transaction completes 7880 * 3. Wait, that TXdisable/enable transaction completes
7881 * 7881 *
7882 * 1+2 guranty that if DCBx attention was scheduled it already changed 7882 * 1+2 guranty that if DCBx attention was scheduled it already changed
7883 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 7883 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7884 * received complettion for the transaction the state is TX_STOPPED. 7884 * received complettion for the transaction the state is TX_STOPPED.
7885 * State will return to STARTED after completion of TX_STOPPED-->STARTED 7885 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7886 * transaction. 7886 * transaction.
7887 */ 7887 */
7888 7888
7889 /* make sure default SB ISR is done */ 7889 /* make sure default SB ISR is done */
7890 if (msix) 7890 if (msix)
7891 synchronize_irq(bp->msix_table[0].vector); 7891 synchronize_irq(bp->msix_table[0].vector);
7892 else 7892 else
7893 synchronize_irq(bp->pdev->irq); 7893 synchronize_irq(bp->pdev->irq);
7894 7894
7895 flush_workqueue(bnx2x_wq); 7895 flush_workqueue(bnx2x_wq);
7896 7896
7897 while (bnx2x_func_get_state(bp, &bp->func_obj) != 7897 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7898 BNX2X_F_STATE_STARTED && tout--) 7898 BNX2X_F_STATE_STARTED && tout--)
7899 msleep(20); 7899 msleep(20);
7900 7900
7901 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7901 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7902 BNX2X_F_STATE_STARTED) { 7902 BNX2X_F_STATE_STARTED) {
7903 #ifdef BNX2X_STOP_ON_ERROR 7903 #ifdef BNX2X_STOP_ON_ERROR
7904 return -EBUSY; 7904 return -EBUSY;
7905 #else 7905 #else
7906 /* 7906 /*
7907 * Failed to complete the transaction in a "good way" 7907 * Failed to complete the transaction in a "good way"
7908 * Force both transactions with CLR bit 7908 * Force both transactions with CLR bit
7909 */ 7909 */
7910 struct bnx2x_func_state_params func_params = {0}; 7910 struct bnx2x_func_state_params func_params = {0};
7911 7911
7912 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " 7912 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7913 "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7913 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7914 7914
7915 func_params.f_obj = &bp->func_obj; 7915 func_params.f_obj = &bp->func_obj;
7916 __set_bit(RAMROD_DRV_CLR_ONLY, 7916 __set_bit(RAMROD_DRV_CLR_ONLY,
7917 &func_params.ramrod_flags); 7917 &func_params.ramrod_flags);
7918 7918
7919 /* STARTED-->TX_ST0PPED */ 7919 /* STARTED-->TX_ST0PPED */
7920 func_params.cmd = BNX2X_F_CMD_TX_STOP; 7920 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7921 bnx2x_func_state_change(bp, &func_params); 7921 bnx2x_func_state_change(bp, &func_params);
7922 7922
7923 /* TX_ST0PPED-->STARTED */ 7923 /* TX_ST0PPED-->STARTED */
7924 func_params.cmd = BNX2X_F_CMD_TX_START; 7924 func_params.cmd = BNX2X_F_CMD_TX_START;
7925 return bnx2x_func_state_change(bp, &func_params); 7925 return bnx2x_func_state_change(bp, &func_params);
7926 #endif 7926 #endif
7927 } 7927 }
7928 7928
7929 return 0; 7929 return 0;
7930 } 7930 }
7931 7931
7932 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7932 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7933 { 7933 {
7934 int port = BP_PORT(bp); 7934 int port = BP_PORT(bp);
7935 int i, rc = 0; 7935 int i, rc = 0;
7936 u8 cos; 7936 u8 cos;
7937 struct bnx2x_mcast_ramrod_params rparam = {0}; 7937 struct bnx2x_mcast_ramrod_params rparam = {0};
7938 u32 reset_code; 7938 u32 reset_code;
7939 7939
7940 /* Wait until tx fastpath tasks complete */ 7940 /* Wait until tx fastpath tasks complete */
7941 for_each_tx_queue(bp, i) { 7941 for_each_tx_queue(bp, i) {
7942 struct bnx2x_fastpath *fp = &bp->fp[i]; 7942 struct bnx2x_fastpath *fp = &bp->fp[i];
7943 7943
7944 for_each_cos_in_tx_queue(fp, cos) 7944 for_each_cos_in_tx_queue(fp, cos)
7945 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); 7945 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
7946 #ifdef BNX2X_STOP_ON_ERROR 7946 #ifdef BNX2X_STOP_ON_ERROR
7947 if (rc) 7947 if (rc)
7948 return; 7948 return;
7949 #endif 7949 #endif
7950 } 7950 }
7951 7951
7952 /* Give HW time to discard old tx messages */ 7952 /* Give HW time to discard old tx messages */
7953 usleep_range(1000, 1000); 7953 usleep_range(1000, 1000);
7954 7954
7955 /* Clean all ETH MACs */ 7955 /* Clean all ETH MACs */
7956 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); 7956 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7957 if (rc < 0) 7957 if (rc < 0)
7958 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 7958 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7959 7959
7960 /* Clean up UC list */ 7960 /* Clean up UC list */
7961 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7961 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7962 true); 7962 true);
7963 if (rc < 0) 7963 if (rc < 0)
7964 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " 7964 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7965 "%d\n", rc); 7965 "%d\n", rc);
7966 7966
7967 /* Disable LLH */ 7967 /* Disable LLH */
7968 if (!CHIP_IS_E1(bp)) 7968 if (!CHIP_IS_E1(bp))
7969 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7969 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7970 7970
7971 /* Set "drop all" (stop Rx). 7971 /* Set "drop all" (stop Rx).
7972 * We need to take a netif_addr_lock() here in order to prevent 7972 * We need to take a netif_addr_lock() here in order to prevent
7973 * a race between the completion code and this code. 7973 * a race between the completion code and this code.
7974 */ 7974 */
7975 netif_addr_lock_bh(bp->dev); 7975 netif_addr_lock_bh(bp->dev);
7976 /* Schedule the rx_mode command */ 7976 /* Schedule the rx_mode command */
7977 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 7977 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7978 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 7978 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7979 else 7979 else
7980 bnx2x_set_storm_rx_mode(bp); 7980 bnx2x_set_storm_rx_mode(bp);
7981 7981
7982 /* Cleanup multicast configuration */ 7982 /* Cleanup multicast configuration */
7983 rparam.mcast_obj = &bp->mcast_obj; 7983 rparam.mcast_obj = &bp->mcast_obj;
7984 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 7984 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7985 if (rc < 0) 7985 if (rc < 0)
7986 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 7986 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7987 7987
7988 netif_addr_unlock_bh(bp->dev); 7988 netif_addr_unlock_bh(bp->dev);
7989 7989
7990 7990
7991 7991
7992 /* 7992 /*
7993 * Send the UNLOAD_REQUEST to the MCP. This will return if 7993 * Send the UNLOAD_REQUEST to the MCP. This will return if
7994 * this function should perform FUNC, PORT or COMMON HW 7994 * this function should perform FUNC, PORT or COMMON HW
7995 * reset. 7995 * reset.
7996 */ 7996 */
7997 reset_code = bnx2x_send_unload_req(bp, unload_mode); 7997 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7998 7998
7999 /* 7999 /*
8000 * (assumption: No Attention from MCP at this stage) 8000 * (assumption: No Attention from MCP at this stage)
8001 * PMF probably in the middle of TXdisable/enable transaction 8001 * PMF probably in the middle of TXdisable/enable transaction
8002 */ 8002 */
8003 rc = bnx2x_func_wait_started(bp); 8003 rc = bnx2x_func_wait_started(bp);
8004 if (rc) { 8004 if (rc) {
8005 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 8005 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8006 #ifdef BNX2X_STOP_ON_ERROR 8006 #ifdef BNX2X_STOP_ON_ERROR
8007 return; 8007 return;
8008 #endif 8008 #endif
8009 } 8009 }
8010 8010
8011 /* Close multi and leading connections 8011 /* Close multi and leading connections
8012 * Completions for ramrods are collected in a synchronous way 8012 * Completions for ramrods are collected in a synchronous way
8013 */ 8013 */
8014 for_each_queue(bp, i) 8014 for_each_queue(bp, i)
8015 if (bnx2x_stop_queue(bp, i)) 8015 if (bnx2x_stop_queue(bp, i))
8016 #ifdef BNX2X_STOP_ON_ERROR 8016 #ifdef BNX2X_STOP_ON_ERROR
8017 return; 8017 return;
8018 #else 8018 #else
8019 goto unload_error; 8019 goto unload_error;
8020 #endif 8020 #endif
8021 /* If SP settings didn't get completed so far - something 8021 /* If SP settings didn't get completed so far - something
8022 * very wrong has happen. 8022 * very wrong has happen.
8023 */ 8023 */
8024 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 8024 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8025 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 8025 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8026 8026
8027 #ifndef BNX2X_STOP_ON_ERROR 8027 #ifndef BNX2X_STOP_ON_ERROR
8028 unload_error: 8028 unload_error:
8029 #endif 8029 #endif
8030 rc = bnx2x_func_stop(bp); 8030 rc = bnx2x_func_stop(bp);
8031 if (rc) { 8031 if (rc) {
8032 BNX2X_ERR("Function stop failed!\n"); 8032 BNX2X_ERR("Function stop failed!\n");
8033 #ifdef BNX2X_STOP_ON_ERROR 8033 #ifdef BNX2X_STOP_ON_ERROR
8034 return; 8034 return;
8035 #endif 8035 #endif
8036 } 8036 }
8037 8037
8038 /* Disable HW interrupts, NAPI */ 8038 /* Disable HW interrupts, NAPI */
8039 bnx2x_netif_stop(bp, 1); 8039 bnx2x_netif_stop(bp, 1);
8040 8040
8041 /* Release IRQs */ 8041 /* Release IRQs */
8042 bnx2x_free_irq(bp); 8042 bnx2x_free_irq(bp);
8043 8043
8044 /* Reset the chip */ 8044 /* Reset the chip */
8045 rc = bnx2x_reset_hw(bp, reset_code); 8045 rc = bnx2x_reset_hw(bp, reset_code);
8046 if (rc) 8046 if (rc)
8047 BNX2X_ERR("HW_RESET failed\n"); 8047 BNX2X_ERR("HW_RESET failed\n");
8048 8048
8049 8049
8050 /* Report UNLOAD_DONE to MCP */ 8050 /* Report UNLOAD_DONE to MCP */
8051 bnx2x_send_unload_done(bp); 8051 bnx2x_send_unload_done(bp);
8052 } 8052 }
8053 8053
8054 void bnx2x_disable_close_the_gate(struct bnx2x *bp) 8054 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8055 { 8055 {
8056 u32 val; 8056 u32 val;
8057 8057
8058 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); 8058 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
8059 8059
8060 if (CHIP_IS_E1(bp)) { 8060 if (CHIP_IS_E1(bp)) {
8061 int port = BP_PORT(bp); 8061 int port = BP_PORT(bp);
8062 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8062 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8063 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8063 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8064 8064
8065 val = REG_RD(bp, addr); 8065 val = REG_RD(bp, addr);
8066 val &= ~(0x300); 8066 val &= ~(0x300);
8067 REG_WR(bp, addr, val); 8067 REG_WR(bp, addr, val);
8068 } else { 8068 } else {
8069 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 8069 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8070 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 8070 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8071 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 8071 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8072 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 8072 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8073 } 8073 }
8074 } 8074 }
8075 8075
8076 /* Close gates #2, #3 and #4: */ 8076 /* Close gates #2, #3 and #4: */
8077 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 8077 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8078 { 8078 {
8079 u32 val; 8079 u32 val;
8080 8080
8081 /* Gates #2 and #4a are closed/opened for "not E1" only */ 8081 /* Gates #2 and #4a are closed/opened for "not E1" only */
8082 if (!CHIP_IS_E1(bp)) { 8082 if (!CHIP_IS_E1(bp)) {
8083 /* #4 */ 8083 /* #4 */
8084 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 8084 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8085 /* #2 */ 8085 /* #2 */
8086 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 8086 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8087 } 8087 }
8088 8088
8089 /* #3 */ 8089 /* #3 */
8090 if (CHIP_IS_E1x(bp)) { 8090 if (CHIP_IS_E1x(bp)) {
8091 /* Prevent interrupts from HC on both ports */ 8091 /* Prevent interrupts from HC on both ports */
8092 val = REG_RD(bp, HC_REG_CONFIG_1); 8092 val = REG_RD(bp, HC_REG_CONFIG_1);
8093 REG_WR(bp, HC_REG_CONFIG_1, 8093 REG_WR(bp, HC_REG_CONFIG_1,
8094 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 8094 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8095 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 8095 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8096 8096
8097 val = REG_RD(bp, HC_REG_CONFIG_0); 8097 val = REG_RD(bp, HC_REG_CONFIG_0);
8098 REG_WR(bp, HC_REG_CONFIG_0, 8098 REG_WR(bp, HC_REG_CONFIG_0,
8099 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 8099 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8100 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 8100 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8101 } else { 8101 } else {
8102 /* Prevent incomming interrupts in IGU */ 8102 /* Prevent incomming interrupts in IGU */
8103 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 8103 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8104 8104
8105 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 8105 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8106 (!close) ? 8106 (!close) ?
8107 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 8107 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8108 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 8108 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8109 } 8109 }
8110 8110
8111 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", 8111 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
8112 close ? "closing" : "opening"); 8112 close ? "closing" : "opening");
8113 mmiowb(); 8113 mmiowb();
8114 } 8114 }
8115 8115
8116 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 8116 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8117 8117
8118 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 8118 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8119 { 8119 {
8120 /* Do some magic... */ 8120 /* Do some magic... */
8121 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8121 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8122 *magic_val = val & SHARED_MF_CLP_MAGIC; 8122 *magic_val = val & SHARED_MF_CLP_MAGIC;
8123 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 8123 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8124 } 8124 }
8125 8125
8126 /** 8126 /**
8127 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 8127 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8128 * 8128 *
8129 * @bp: driver handle 8129 * @bp: driver handle
8130 * @magic_val: old value of the `magic' bit. 8130 * @magic_val: old value of the `magic' bit.
8131 */ 8131 */
8132 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 8132 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8133 { 8133 {
8134 /* Restore the `magic' bit value... */ 8134 /* Restore the `magic' bit value... */
8135 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8135 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8136 MF_CFG_WR(bp, shared_mf_config.clp_mb, 8136 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8137 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 8137 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8138 } 8138 }
8139 8139
8140 /** 8140 /**
8141 * bnx2x_reset_mcp_prep - prepare for MCP reset. 8141 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8142 * 8142 *
8143 * @bp: driver handle 8143 * @bp: driver handle
8144 * @magic_val: old value of 'magic' bit. 8144 * @magic_val: old value of 'magic' bit.
8145 * 8145 *
8146 * Takes care of CLP configurations. 8146 * Takes care of CLP configurations.
8147 */ 8147 */
8148 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 8148 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8149 { 8149 {
8150 u32 shmem; 8150 u32 shmem;
8151 u32 validity_offset; 8151 u32 validity_offset;
8152 8152
8153 DP(NETIF_MSG_HW, "Starting\n"); 8153 DP(NETIF_MSG_HW, "Starting\n");
8154 8154
8155 /* Set `magic' bit in order to save MF config */ 8155 /* Set `magic' bit in order to save MF config */
8156 if (!CHIP_IS_E1(bp)) 8156 if (!CHIP_IS_E1(bp))
8157 bnx2x_clp_reset_prep(bp, magic_val); 8157 bnx2x_clp_reset_prep(bp, magic_val);
8158 8158
8159 /* Get shmem offset */ 8159 /* Get shmem offset */
8160 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8160 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8161 validity_offset = offsetof(struct shmem_region, validity_map[0]); 8161 validity_offset = offsetof(struct shmem_region, validity_map[0]);
8162 8162
8163 /* Clear validity map flags */ 8163 /* Clear validity map flags */
8164 if (shmem > 0) 8164 if (shmem > 0)
8165 REG_WR(bp, shmem + validity_offset, 0); 8165 REG_WR(bp, shmem + validity_offset, 0);
8166 } 8166 }
8167 8167
8168 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 8168 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8169 #define MCP_ONE_TIMEOUT 100 /* 100 ms */ 8169 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8170 8170
8171 /** 8171 /**
8172 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 8172 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8173 * 8173 *
8174 * @bp: driver handle 8174 * @bp: driver handle
8175 */ 8175 */
8176 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 8176 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
8177 { 8177 {
8178 /* special handling for emulation and FPGA, 8178 /* special handling for emulation and FPGA,
8179 wait 10 times longer */ 8179 wait 10 times longer */
8180 if (CHIP_REV_IS_SLOW(bp)) 8180 if (CHIP_REV_IS_SLOW(bp))
8181 msleep(MCP_ONE_TIMEOUT*10); 8181 msleep(MCP_ONE_TIMEOUT*10);
8182 else 8182 else
8183 msleep(MCP_ONE_TIMEOUT); 8183 msleep(MCP_ONE_TIMEOUT);
8184 } 8184 }
8185 8185
8186 /* 8186 /*
8187 * initializes bp->common.shmem_base and waits for validity signature to appear 8187 * initializes bp->common.shmem_base and waits for validity signature to appear
8188 */ 8188 */
8189 static int bnx2x_init_shmem(struct bnx2x *bp) 8189 static int bnx2x_init_shmem(struct bnx2x *bp)
8190 { 8190 {
8191 int cnt = 0; 8191 int cnt = 0;
8192 u32 val = 0; 8192 u32 val = 0;
8193 8193
8194 do { 8194 do {
8195 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8195 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8196 if (bp->common.shmem_base) { 8196 if (bp->common.shmem_base) {
8197 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 8197 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8198 if (val & SHR_MEM_VALIDITY_MB) 8198 if (val & SHR_MEM_VALIDITY_MB)
8199 return 0; 8199 return 0;
8200 } 8200 }
8201 8201
8202 bnx2x_mcp_wait_one(bp); 8202 bnx2x_mcp_wait_one(bp);
8203 8203
8204 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 8204 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8205 8205
8206 BNX2X_ERR("BAD MCP validity signature\n"); 8206 BNX2X_ERR("BAD MCP validity signature\n");
8207 8207
8208 return -ENODEV; 8208 return -ENODEV;
8209 } 8209 }
8210 8210
8211 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 8211 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8212 { 8212 {
8213 int rc = bnx2x_init_shmem(bp); 8213 int rc = bnx2x_init_shmem(bp);
8214 8214
8215 /* Restore the `magic' bit value */ 8215 /* Restore the `magic' bit value */
8216 if (!CHIP_IS_E1(bp)) 8216 if (!CHIP_IS_E1(bp))
8217 bnx2x_clp_reset_done(bp, magic_val); 8217 bnx2x_clp_reset_done(bp, magic_val);
8218 8218
8219 return rc; 8219 return rc;
8220 } 8220 }
8221 8221
8222 static void bnx2x_pxp_prep(struct bnx2x *bp) 8222 static void bnx2x_pxp_prep(struct bnx2x *bp)
8223 { 8223 {
8224 if (!CHIP_IS_E1(bp)) { 8224 if (!CHIP_IS_E1(bp)) {
8225 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 8225 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8226 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 8226 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8227 mmiowb(); 8227 mmiowb();
8228 } 8228 }
8229 } 8229 }
8230 8230
8231 /* 8231 /*
8232 * Reset the whole chip except for: 8232 * Reset the whole chip except for:
8233 * - PCIE core 8233 * - PCIE core
8234 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 8234 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8235 * one reset bit) 8235 * one reset bit)
8236 * - IGU 8236 * - IGU
8237 * - MISC (including AEU) 8237 * - MISC (including AEU)
8238 * - GRC 8238 * - GRC
8239 * - RBCN, RBCP 8239 * - RBCN, RBCP
8240 */ 8240 */
8241 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 8241 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8242 { 8242 {
8243 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 8243 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8244 u32 global_bits2, stay_reset2; 8244 u32 global_bits2, stay_reset2;
8245 8245
8246 /* 8246 /*
8247 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8247 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8248 * (per chip) blocks. 8248 * (per chip) blocks.
8249 */ 8249 */
8250 global_bits2 = 8250 global_bits2 =
8251 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8251 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8252 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8252 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8253 8253
8254 /* Don't reset the following blocks */ 8254 /* Don't reset the following blocks */
8255 not_reset_mask1 = 8255 not_reset_mask1 =
8256 MISC_REGISTERS_RESET_REG_1_RST_HC | 8256 MISC_REGISTERS_RESET_REG_1_RST_HC |
8257 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8257 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8258 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8258 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8259 8259
8260 not_reset_mask2 = 8260 not_reset_mask2 =
8261 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8261 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8262 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8262 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8263 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8263 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8264 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8264 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8265 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8265 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8266 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8266 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8267 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8267 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8268 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8268 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8269 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8269 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8270 MISC_REGISTERS_RESET_REG_2_PGLC; 8270 MISC_REGISTERS_RESET_REG_2_PGLC;
8271 8271
8272 /* 8272 /*
8273 * Keep the following blocks in reset: 8273 * Keep the following blocks in reset:
8274 * - all xxMACs are handled by the bnx2x_link code. 8274 * - all xxMACs are handled by the bnx2x_link code.
8275 */ 8275 */
8276 stay_reset2 = 8276 stay_reset2 =
8277 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8277 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8278 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8278 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8279 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8279 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8280 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8280 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8281 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8281 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8282 MISC_REGISTERS_RESET_REG_2_UMAC1 | 8282 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8283 MISC_REGISTERS_RESET_REG_2_XMAC | 8283 MISC_REGISTERS_RESET_REG_2_XMAC |
8284 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8284 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8285 8285
8286 /* Full reset masks according to the chip */ 8286 /* Full reset masks according to the chip */
8287 reset_mask1 = 0xffffffff; 8287 reset_mask1 = 0xffffffff;
8288 8288
8289 if (CHIP_IS_E1(bp)) 8289 if (CHIP_IS_E1(bp))
8290 reset_mask2 = 0xffff; 8290 reset_mask2 = 0xffff;
8291 else if (CHIP_IS_E1H(bp)) 8291 else if (CHIP_IS_E1H(bp))
8292 reset_mask2 = 0x1ffff; 8292 reset_mask2 = 0x1ffff;
8293 else if (CHIP_IS_E2(bp)) 8293 else if (CHIP_IS_E2(bp))
8294 reset_mask2 = 0xfffff; 8294 reset_mask2 = 0xfffff;
8295 else /* CHIP_IS_E3 */ 8295 else /* CHIP_IS_E3 */
8296 reset_mask2 = 0x3ffffff; 8296 reset_mask2 = 0x3ffffff;
8297 8297
8298 /* Don't reset global blocks unless we need to */ 8298 /* Don't reset global blocks unless we need to */
8299 if (!global) 8299 if (!global)
8300 reset_mask2 &= ~global_bits2; 8300 reset_mask2 &= ~global_bits2;
8301 8301
8302 /* 8302 /*
8303 * In case of attention in the QM, we need to reset PXP 8303 * In case of attention in the QM, we need to reset PXP
8304 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8304 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8305 * because otherwise QM reset would release 'close the gates' shortly 8305 * because otherwise QM reset would release 'close the gates' shortly
8306 * before resetting the PXP, then the PSWRQ would send a write 8306 * before resetting the PXP, then the PSWRQ would send a write
8307 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8307 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8308 * read the payload data from PSWWR, but PSWWR would not 8308 * read the payload data from PSWWR, but PSWWR would not
8309 * respond. The write queue in PGLUE would stuck, dmae commands 8309 * respond. The write queue in PGLUE would stuck, dmae commands
8310 * would not return. Therefore it's important to reset the second 8310 * would not return. Therefore it's important to reset the second
8311 * reset register (containing the 8311 * reset register (containing the
8312 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 8312 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8313 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 8313 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8314 * bit). 8314 * bit).
8315 */ 8315 */
8316 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8316 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8317 reset_mask2 & (~not_reset_mask2)); 8317 reset_mask2 & (~not_reset_mask2));
8318 8318
8319 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8319 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8320 reset_mask1 & (~not_reset_mask1)); 8320 reset_mask1 & (~not_reset_mask1));
8321 8321
8322 barrier(); 8322 barrier();
8323 mmiowb(); 8323 mmiowb();
8324 8324
8325 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 8325 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8326 reset_mask2 & (~stay_reset2)); 8326 reset_mask2 & (~stay_reset2));
8327 8327
8328 barrier(); 8328 barrier();
8329 mmiowb(); 8329 mmiowb();
8330 8330
8331 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 8331 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8332 mmiowb(); 8332 mmiowb();
8333 } 8333 }
8334 8334
8335 /** 8335 /**
8336 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 8336 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8337 * It should get cleared in no more than 1s. 8337 * It should get cleared in no more than 1s.
8338 * 8338 *
8339 * @bp: driver handle 8339 * @bp: driver handle
8340 * 8340 *
8341 * It should get cleared in no more than 1s. Returns 0 if 8341 * It should get cleared in no more than 1s. Returns 0 if
8342 * pending writes bit gets cleared. 8342 * pending writes bit gets cleared.
8343 */ 8343 */
8344 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 8344 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8345 { 8345 {
8346 u32 cnt = 1000; 8346 u32 cnt = 1000;
8347 u32 pend_bits = 0; 8347 u32 pend_bits = 0;
8348 8348
8349 do { 8349 do {
8350 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 8350 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8351 8351
8352 if (pend_bits == 0) 8352 if (pend_bits == 0)
8353 break; 8353 break;
8354 8354
8355 usleep_range(1000, 1000); 8355 usleep_range(1000, 1000);
8356 } while (cnt-- > 0); 8356 } while (cnt-- > 0);
8357 8357
8358 if (cnt <= 0) { 8358 if (cnt <= 0) {
8359 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 8359 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8360 pend_bits); 8360 pend_bits);
8361 return -EBUSY; 8361 return -EBUSY;
8362 } 8362 }
8363 8363
8364 return 0; 8364 return 0;
8365 } 8365 }
8366 8366
8367 static int bnx2x_process_kill(struct bnx2x *bp, bool global) 8367 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8368 { 8368 {
8369 int cnt = 1000; 8369 int cnt = 1000;
8370 u32 val = 0; 8370 u32 val = 0;
8371 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 8371 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8372 8372
8373 8373
8374 /* Empty the Tetris buffer, wait for 1s */ 8374 /* Empty the Tetris buffer, wait for 1s */
8375 do { 8375 do {
8376 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 8376 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8377 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 8377 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8378 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 8378 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8379 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 8379 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8380 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 8380 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8381 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 8381 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8382 ((port_is_idle_0 & 0x1) == 0x1) && 8382 ((port_is_idle_0 & 0x1) == 0x1) &&
8383 ((port_is_idle_1 & 0x1) == 0x1) && 8383 ((port_is_idle_1 & 0x1) == 0x1) &&
8384 (pgl_exp_rom2 == 0xffffffff)) 8384 (pgl_exp_rom2 == 0xffffffff))
8385 break; 8385 break;
8386 usleep_range(1000, 1000); 8386 usleep_range(1000, 1000);
8387 } while (cnt-- > 0); 8387 } while (cnt-- > 0);
8388 8388
8389 if (cnt <= 0) { 8389 if (cnt <= 0) {
8390 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" 8390 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8391 " are still" 8391 " are still"
8392 " outstanding read requests after 1s!\n"); 8392 " outstanding read requests after 1s!\n");
8393 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," 8393 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8394 " port_is_idle_0=0x%08x," 8394 " port_is_idle_0=0x%08x,"
8395 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 8395 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8396 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8396 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8397 pgl_exp_rom2); 8397 pgl_exp_rom2);
8398 return -EAGAIN; 8398 return -EAGAIN;
8399 } 8399 }
8400 8400
8401 barrier(); 8401 barrier();
8402 8402
8403 /* Close gates #2, #3 and #4 */ 8403 /* Close gates #2, #3 and #4 */
8404 bnx2x_set_234_gates(bp, true); 8404 bnx2x_set_234_gates(bp, true);
8405 8405
8406 /* Poll for IGU VQs for 57712 and newer chips */ 8406 /* Poll for IGU VQs for 57712 and newer chips */
8407 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 8407 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8408 return -EAGAIN; 8408 return -EAGAIN;
8409 8409
8410 8410
8411 /* TBD: Indicate that "process kill" is in progress to MCP */ 8411 /* TBD: Indicate that "process kill" is in progress to MCP */
8412 8412
8413 /* Clear "unprepared" bit */ 8413 /* Clear "unprepared" bit */
8414 REG_WR(bp, MISC_REG_UNPREPARED, 0); 8414 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8415 barrier(); 8415 barrier();
8416 8416
8417 /* Make sure all is written to the chip before the reset */ 8417 /* Make sure all is written to the chip before the reset */
8418 mmiowb(); 8418 mmiowb();
8419 8419
8420 /* Wait for 1ms to empty GLUE and PCI-E core queues, 8420 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8421 * PSWHST, GRC and PSWRD Tetris buffer. 8421 * PSWHST, GRC and PSWRD Tetris buffer.
8422 */ 8422 */
8423 usleep_range(1000, 1000); 8423 usleep_range(1000, 1000);
8424 8424
8425 /* Prepare to chip reset: */ 8425 /* Prepare to chip reset: */
8426 /* MCP */ 8426 /* MCP */
8427 if (global) 8427 if (global)
8428 bnx2x_reset_mcp_prep(bp, &val); 8428 bnx2x_reset_mcp_prep(bp, &val);
8429 8429
8430 /* PXP */ 8430 /* PXP */
8431 bnx2x_pxp_prep(bp); 8431 bnx2x_pxp_prep(bp);
8432 barrier(); 8432 barrier();
8433 8433
8434 /* reset the chip */ 8434 /* reset the chip */
8435 bnx2x_process_kill_chip_reset(bp, global); 8435 bnx2x_process_kill_chip_reset(bp, global);
8436 barrier(); 8436 barrier();
8437 8437
8438 /* Recover after reset: */ 8438 /* Recover after reset: */
8439 /* MCP */ 8439 /* MCP */
8440 if (global && bnx2x_reset_mcp_comp(bp, val)) 8440 if (global && bnx2x_reset_mcp_comp(bp, val))
8441 return -EAGAIN; 8441 return -EAGAIN;
8442 8442
8443 /* TBD: Add resetting the NO_MCP mode DB here */ 8443 /* TBD: Add resetting the NO_MCP mode DB here */
8444 8444
8445 /* PXP */ 8445 /* PXP */
8446 bnx2x_pxp_prep(bp); 8446 bnx2x_pxp_prep(bp);
8447 8447
8448 /* Open the gates #2, #3 and #4 */ 8448 /* Open the gates #2, #3 and #4 */
8449 bnx2x_set_234_gates(bp, false); 8449 bnx2x_set_234_gates(bp, false);
8450 8450
8451 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 8451 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8452 * reset state, re-enable attentions. */ 8452 * reset state, re-enable attentions. */
8453 8453
8454 return 0; 8454 return 0;
8455 } 8455 }
8456 8456
8457 int bnx2x_leader_reset(struct bnx2x *bp) 8457 int bnx2x_leader_reset(struct bnx2x *bp)
8458 { 8458 {
8459 int rc = 0; 8459 int rc = 0;
8460 bool global = bnx2x_reset_is_global(bp); 8460 bool global = bnx2x_reset_is_global(bp);
8461 8461
8462 /* Try to recover after the failure */ 8462 /* Try to recover after the failure */
8463 if (bnx2x_process_kill(bp, global)) { 8463 if (bnx2x_process_kill(bp, global)) {
8464 netdev_err(bp->dev, "Something bad had happen on engine %d! " 8464 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8465 "Aii!\n", BP_PATH(bp)); 8465 "Aii!\n", BP_PATH(bp));
8466 rc = -EAGAIN; 8466 rc = -EAGAIN;
8467 goto exit_leader_reset; 8467 goto exit_leader_reset;
8468 } 8468 }
8469 8469
8470 /* 8470 /*
8471 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 8471 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8472 * state. 8472 * state.
8473 */ 8473 */
8474 bnx2x_set_reset_done(bp); 8474 bnx2x_set_reset_done(bp);
8475 if (global) 8475 if (global)
8476 bnx2x_clear_reset_global(bp); 8476 bnx2x_clear_reset_global(bp);
8477 8477
8478 exit_leader_reset: 8478 exit_leader_reset:
8479 bp->is_leader = 0; 8479 bp->is_leader = 0;
8480 bnx2x_release_leader_lock(bp); 8480 bnx2x_release_leader_lock(bp);
8481 smp_mb(); 8481 smp_mb();
8482 return rc; 8482 return rc;
8483 } 8483 }
8484 8484
8485 static inline void bnx2x_recovery_failed(struct bnx2x *bp) 8485 static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8486 { 8486 {
8487 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 8487 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8488 8488
8489 /* Disconnect this device */ 8489 /* Disconnect this device */
8490 netif_device_detach(bp->dev); 8490 netif_device_detach(bp->dev);
8491 8491
8492 /* 8492 /*
8493 * Block ifup for all function on this engine until "process kill" 8493 * Block ifup for all function on this engine until "process kill"
8494 * or power cycle. 8494 * or power cycle.
8495 */ 8495 */
8496 bnx2x_set_reset_in_progress(bp); 8496 bnx2x_set_reset_in_progress(bp);
8497 8497
8498 /* Shut down the power */ 8498 /* Shut down the power */
8499 bnx2x_set_power_state(bp, PCI_D3hot); 8499 bnx2x_set_power_state(bp, PCI_D3hot);
8500 8500
8501 bp->recovery_state = BNX2X_RECOVERY_FAILED; 8501 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8502 8502
8503 smp_mb(); 8503 smp_mb();
8504 } 8504 }
8505 8505
8506 /* 8506 /*
8507 * Assumption: runs under rtnl lock. This together with the fact 8507 * Assumption: runs under rtnl lock. This together with the fact
8508 * that it's called only from bnx2x_sp_rtnl() ensure that it 8508 * that it's called only from bnx2x_sp_rtnl() ensure that it
8509 * will never be called when netif_running(bp->dev) is false. 8509 * will never be called when netif_running(bp->dev) is false.
8510 */ 8510 */
8511 static void bnx2x_parity_recover(struct bnx2x *bp) 8511 static void bnx2x_parity_recover(struct bnx2x *bp)
8512 { 8512 {
8513 bool global = false; 8513 bool global = false;
8514 8514
8515 DP(NETIF_MSG_HW, "Handling parity\n"); 8515 DP(NETIF_MSG_HW, "Handling parity\n");
8516 while (1) { 8516 while (1) {
8517 switch (bp->recovery_state) { 8517 switch (bp->recovery_state) {
8518 case BNX2X_RECOVERY_INIT: 8518 case BNX2X_RECOVERY_INIT:
8519 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 8519 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8520 bnx2x_chk_parity_attn(bp, &global, false); 8520 bnx2x_chk_parity_attn(bp, &global, false);
8521 8521
8522 /* Try to get a LEADER_LOCK HW lock */ 8522 /* Try to get a LEADER_LOCK HW lock */
8523 if (bnx2x_trylock_leader_lock(bp)) { 8523 if (bnx2x_trylock_leader_lock(bp)) {
8524 bnx2x_set_reset_in_progress(bp); 8524 bnx2x_set_reset_in_progress(bp);
8525 /* 8525 /*
8526 * Check if there is a global attention and if 8526 * Check if there is a global attention and if
8527 * there was a global attention, set the global 8527 * there was a global attention, set the global
8528 * reset bit. 8528 * reset bit.
8529 */ 8529 */
8530 8530
8531 if (global) 8531 if (global)
8532 bnx2x_set_reset_global(bp); 8532 bnx2x_set_reset_global(bp);
8533 8533
8534 bp->is_leader = 1; 8534 bp->is_leader = 1;
8535 } 8535 }
8536 8536
8537 /* Stop the driver */ 8537 /* Stop the driver */
8538 /* If interface has been removed - break */ 8538 /* If interface has been removed - break */
8539 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) 8539 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8540 return; 8540 return;
8541 8541
8542 bp->recovery_state = BNX2X_RECOVERY_WAIT; 8542 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8543 8543
8544 /* 8544 /*
8545 * Reset MCP command sequence number and MCP mail box 8545 * Reset MCP command sequence number and MCP mail box
8546 * sequence as we are going to reset the MCP. 8546 * sequence as we are going to reset the MCP.
8547 */ 8547 */
8548 if (global) { 8548 if (global) {
8549 bp->fw_seq = 0; 8549 bp->fw_seq = 0;
8550 bp->fw_drv_pulse_wr_seq = 0; 8550 bp->fw_drv_pulse_wr_seq = 0;
8551 } 8551 }
8552 8552
8553 /* Ensure "is_leader", MCP command sequence and 8553 /* Ensure "is_leader", MCP command sequence and
8554 * "recovery_state" update values are seen on other 8554 * "recovery_state" update values are seen on other
8555 * CPUs. 8555 * CPUs.
8556 */ 8556 */
8557 smp_mb(); 8557 smp_mb();
8558 break; 8558 break;
8559 8559
8560 case BNX2X_RECOVERY_WAIT: 8560 case BNX2X_RECOVERY_WAIT:
8561 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 8561 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8562 if (bp->is_leader) { 8562 if (bp->is_leader) {
8563 int other_engine = BP_PATH(bp) ? 0 : 1; 8563 int other_engine = BP_PATH(bp) ? 0 : 1;
8564 u32 other_load_counter = 8564 u32 other_load_counter =
8565 bnx2x_get_load_cnt(bp, other_engine); 8565 bnx2x_get_load_cnt(bp, other_engine);
8566 u32 load_counter = 8566 u32 load_counter =
8567 bnx2x_get_load_cnt(bp, BP_PATH(bp)); 8567 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8568 global = bnx2x_reset_is_global(bp); 8568 global = bnx2x_reset_is_global(bp);
8569 8569
8570 /* 8570 /*
8571 * In case of a parity in a global block, let 8571 * In case of a parity in a global block, let
8572 * the first leader that performs a 8572 * the first leader that performs a
8573 * leader_reset() reset the global blocks in 8573 * leader_reset() reset the global blocks in
8574 * order to clear global attentions. Otherwise 8574 * order to clear global attentions. Otherwise
8575 * the the gates will remain closed for that 8575 * the the gates will remain closed for that
8576 * engine. 8576 * engine.
8577 */ 8577 */
8578 if (load_counter || 8578 if (load_counter ||
8579 (global && other_load_counter)) { 8579 (global && other_load_counter)) {
8580 /* Wait until all other functions get 8580 /* Wait until all other functions get
8581 * down. 8581 * down.
8582 */ 8582 */
8583 schedule_delayed_work(&bp->sp_rtnl_task, 8583 schedule_delayed_work(&bp->sp_rtnl_task,
8584 HZ/10); 8584 HZ/10);
8585 return; 8585 return;
8586 } else { 8586 } else {
8587 /* If all other functions got down - 8587 /* If all other functions got down -
8588 * try to bring the chip back to 8588 * try to bring the chip back to
8589 * normal. In any case it's an exit 8589 * normal. In any case it's an exit
8590 * point for a leader. 8590 * point for a leader.
8591 */ 8591 */
8592 if (bnx2x_leader_reset(bp)) { 8592 if (bnx2x_leader_reset(bp)) {
8593 bnx2x_recovery_failed(bp); 8593 bnx2x_recovery_failed(bp);
8594 return; 8594 return;
8595 } 8595 }
8596 8596
8597 /* If we are here, means that the 8597 /* If we are here, means that the
8598 * leader has succeeded and doesn't 8598 * leader has succeeded and doesn't
8599 * want to be a leader any more. Try 8599 * want to be a leader any more. Try
8600 * to continue as a none-leader. 8600 * to continue as a none-leader.
8601 */ 8601 */
8602 break; 8602 break;
8603 } 8603 }
8604 } else { /* non-leader */ 8604 } else { /* non-leader */
8605 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 8605 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
8606 /* Try to get a LEADER_LOCK HW lock as 8606 /* Try to get a LEADER_LOCK HW lock as
8607 * long as a former leader may have 8607 * long as a former leader may have
8608 * been unloaded by the user or 8608 * been unloaded by the user or
8609 * released a leadership by another 8609 * released a leadership by another
8610 * reason. 8610 * reason.
8611 */ 8611 */
8612 if (bnx2x_trylock_leader_lock(bp)) { 8612 if (bnx2x_trylock_leader_lock(bp)) {
8613 /* I'm a leader now! Restart a 8613 /* I'm a leader now! Restart a
8614 * switch case. 8614 * switch case.
8615 */ 8615 */
8616 bp->is_leader = 1; 8616 bp->is_leader = 1;
8617 break; 8617 break;
8618 } 8618 }
8619 8619
8620 schedule_delayed_work(&bp->sp_rtnl_task, 8620 schedule_delayed_work(&bp->sp_rtnl_task,
8621 HZ/10); 8621 HZ/10);
8622 return; 8622 return;
8623 8623
8624 } else { 8624 } else {
8625 /* 8625 /*
8626 * If there was a global attention, wait 8626 * If there was a global attention, wait
8627 * for it to be cleared. 8627 * for it to be cleared.
8628 */ 8628 */
8629 if (bnx2x_reset_is_global(bp)) { 8629 if (bnx2x_reset_is_global(bp)) {
8630 schedule_delayed_work( 8630 schedule_delayed_work(
8631 &bp->sp_rtnl_task, 8631 &bp->sp_rtnl_task,
8632 HZ/10); 8632 HZ/10);
8633 return; 8633 return;
8634 } 8634 }
8635 8635
8636 if (bnx2x_nic_load(bp, LOAD_NORMAL)) 8636 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8637 bnx2x_recovery_failed(bp); 8637 bnx2x_recovery_failed(bp);
8638 else { 8638 else {
8639 bp->recovery_state = 8639 bp->recovery_state =
8640 BNX2X_RECOVERY_DONE; 8640 BNX2X_RECOVERY_DONE;
8641 smp_mb(); 8641 smp_mb();
8642 } 8642 }
8643 8643
8644 return; 8644 return;
8645 } 8645 }
8646 } 8646 }
8647 default: 8647 default:
8648 return; 8648 return;
8649 } 8649 }
8650 } 8650 }
8651 } 8651 }
8652 8652
8653 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 8653 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8654 * scheduled on a general queue in order to prevent a dead lock. 8654 * scheduled on a general queue in order to prevent a dead lock.
8655 */ 8655 */
8656 static void bnx2x_sp_rtnl_task(struct work_struct *work) 8656 static void bnx2x_sp_rtnl_task(struct work_struct *work)
8657 { 8657 {
8658 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 8658 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
8659 8659
8660 rtnl_lock(); 8660 rtnl_lock();
8661 8661
8662 if (!netif_running(bp->dev)) 8662 if (!netif_running(bp->dev))
8663 goto sp_rtnl_exit; 8663 goto sp_rtnl_exit;
8664 8664
8665 /* if stop on error is defined no recovery flows should be executed */ 8665 /* if stop on error is defined no recovery flows should be executed */
8666 #ifdef BNX2X_STOP_ON_ERROR 8666 #ifdef BNX2X_STOP_ON_ERROR
8667 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " 8667 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8668 "so reset not done to allow debug dump,\n" 8668 "so reset not done to allow debug dump,\n"
8669 "you will need to reboot when done\n"); 8669 "you will need to reboot when done\n");
8670 goto sp_rtnl_not_reset; 8670 goto sp_rtnl_not_reset;
8671 #endif 8671 #endif
8672 8672
8673 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 8673 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8674 /* 8674 /*
8675 * Clear all pending SP commands as we are going to reset the 8675 * Clear all pending SP commands as we are going to reset the
8676 * function anyway. 8676 * function anyway.
8677 */ 8677 */
8678 bp->sp_rtnl_state = 0; 8678 bp->sp_rtnl_state = 0;
8679 smp_mb(); 8679 smp_mb();
8680 8680
8681 bnx2x_parity_recover(bp); 8681 bnx2x_parity_recover(bp);
8682 8682
8683 goto sp_rtnl_exit; 8683 goto sp_rtnl_exit;
8684 } 8684 }
8685 8685
8686 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 8686 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8687 /* 8687 /*
8688 * Clear all pending SP commands as we are going to reset the 8688 * Clear all pending SP commands as we are going to reset the
8689 * function anyway. 8689 * function anyway.
8690 */ 8690 */
8691 bp->sp_rtnl_state = 0; 8691 bp->sp_rtnl_state = 0;
8692 smp_mb(); 8692 smp_mb();
8693 8693
8694 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 8694 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8695 bnx2x_nic_load(bp, LOAD_NORMAL); 8695 bnx2x_nic_load(bp, LOAD_NORMAL);
8696 8696
8697 goto sp_rtnl_exit; 8697 goto sp_rtnl_exit;
8698 } 8698 }
8699 #ifdef BNX2X_STOP_ON_ERROR 8699 #ifdef BNX2X_STOP_ON_ERROR
8700 sp_rtnl_not_reset: 8700 sp_rtnl_not_reset:
8701 #endif 8701 #endif
8702 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 8702 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8703 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 8703 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8704 8704
8705 /* 8705 /*
8706 * in case of fan failure we need to reset id if the "stop on error" 8706 * in case of fan failure we need to reset id if the "stop on error"
8707 * debug flag is set, since we trying to prevent permanent overheating 8707 * debug flag is set, since we trying to prevent permanent overheating
8708 * damage 8708 * damage
8709 */ 8709 */
8710 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 8710 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
8711 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n"); 8711 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n");
8712 netif_device_detach(bp->dev); 8712 netif_device_detach(bp->dev);
8713 bnx2x_close(bp->dev); 8713 bnx2x_close(bp->dev);
8714 } 8714 }
8715 8715
8716 sp_rtnl_exit: 8716 sp_rtnl_exit:
8717 rtnl_unlock(); 8717 rtnl_unlock();
8718 } 8718 }
8719 8719
8720 /* end of nic load/unload */ 8720 /* end of nic load/unload */
8721 8721
8722 static void bnx2x_period_task(struct work_struct *work) 8722 static void bnx2x_period_task(struct work_struct *work)
8723 { 8723 {
8724 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 8724 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8725 8725
8726 if (!netif_running(bp->dev)) 8726 if (!netif_running(bp->dev))
8727 goto period_task_exit; 8727 goto period_task_exit;
8728 8728
8729 if (CHIP_REV_IS_SLOW(bp)) { 8729 if (CHIP_REV_IS_SLOW(bp)) {
8730 BNX2X_ERR("period task called on emulation, ignoring\n"); 8730 BNX2X_ERR("period task called on emulation, ignoring\n");
8731 goto period_task_exit; 8731 goto period_task_exit;
8732 } 8732 }
8733 8733
8734 bnx2x_acquire_phy_lock(bp); 8734 bnx2x_acquire_phy_lock(bp);
8735 /* 8735 /*
8736 * The barrier is needed to ensure the ordering between the writing to 8736 * The barrier is needed to ensure the ordering between the writing to
8737 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 8737 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8738 * the reading here. 8738 * the reading here.
8739 */ 8739 */
8740 smp_mb(); 8740 smp_mb();
8741 if (bp->port.pmf) { 8741 if (bp->port.pmf) {
8742 bnx2x_period_func(&bp->link_params, &bp->link_vars); 8742 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8743 8743
8744 /* Re-queue task in 1 sec */ 8744 /* Re-queue task in 1 sec */
8745 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 8745 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8746 } 8746 }
8747 8747
8748 bnx2x_release_phy_lock(bp); 8748 bnx2x_release_phy_lock(bp);
8749 period_task_exit: 8749 period_task_exit:
8750 return; 8750 return;
8751 } 8751 }
8752 8752
8753 /* 8753 /*
8754 * Init service functions 8754 * Init service functions
8755 */ 8755 */
8756 8756
8757 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 8757 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8758 { 8758 {
8759 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 8759 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8760 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 8760 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8761 return base + (BP_ABS_FUNC(bp)) * stride; 8761 return base + (BP_ABS_FUNC(bp)) * stride;
8762 } 8762 }
8763 8763
8764 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 8764 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8765 { 8765 {
8766 u32 reg = bnx2x_get_pretend_reg(bp); 8766 u32 reg = bnx2x_get_pretend_reg(bp);
8767 8767
8768 /* Flush all outstanding writes */ 8768 /* Flush all outstanding writes */
8769 mmiowb(); 8769 mmiowb();
8770 8770
8771 /* Pretend to be function 0 */ 8771 /* Pretend to be function 0 */
8772 REG_WR(bp, reg, 0); 8772 REG_WR(bp, reg, 0);
8773 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 8773 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8774 8774
8775 /* From now we are in the "like-E1" mode */ 8775 /* From now we are in the "like-E1" mode */
8776 bnx2x_int_disable(bp); 8776 bnx2x_int_disable(bp);
8777 8777
8778 /* Flush all outstanding writes */ 8778 /* Flush all outstanding writes */
8779 mmiowb(); 8779 mmiowb();
8780 8780
8781 /* Restore the original function */ 8781 /* Restore the original function */
8782 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 8782 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8783 REG_RD(bp, reg); 8783 REG_RD(bp, reg);
8784 } 8784 }
8785 8785
8786 static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 8786 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8787 { 8787 {
8788 if (CHIP_IS_E1(bp)) 8788 if (CHIP_IS_E1(bp))
8789 bnx2x_int_disable(bp); 8789 bnx2x_int_disable(bp);
8790 else 8790 else
8791 bnx2x_undi_int_disable_e1h(bp); 8791 bnx2x_undi_int_disable_e1h(bp);
8792 } 8792 }
8793 8793
8794 static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 8794 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8795 { 8795 {
8796 u32 val; 8796 u32 val;
8797 8797
8798 /* Check if there is any driver already loaded */ 8798 /* Check if there is any driver already loaded */
8799 val = REG_RD(bp, MISC_REG_UNPREPARED); 8799 val = REG_RD(bp, MISC_REG_UNPREPARED);
8800 if (val == 0x1) { 8800 if (val == 0x1) {
8801 8801
8802 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8802 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8803 /* 8803 /*
8804 * Check if it is the UNDI driver 8804 * Check if it is the UNDI driver
8805 * UNDI driver initializes CID offset for normal bell to 0x7 8805 * UNDI driver initializes CID offset for normal bell to 0x7
8806 */ 8806 */
8807 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 8807 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8808 if (val == 0x7) { 8808 if (val == 0x7) {
8809 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8809 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8810 /* save our pf_num */ 8810 /* save our pf_num */
8811 int orig_pf_num = bp->pf_num; 8811 int orig_pf_num = bp->pf_num;
8812 int port; 8812 int port;
8813 u32 swap_en, swap_val, value; 8813 u32 swap_en, swap_val, value;
8814 8814
8815 /* clear the UNDI indication */ 8815 /* clear the UNDI indication */
8816 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 8816 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8817 8817
8818 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 8818 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8819 8819
8820 /* try unload UNDI on port 0 */ 8820 /* try unload UNDI on port 0 */
8821 bp->pf_num = 0; 8821 bp->pf_num = 0;
8822 bp->fw_seq = 8822 bp->fw_seq =
8823 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8823 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8824 DRV_MSG_SEQ_NUMBER_MASK); 8824 DRV_MSG_SEQ_NUMBER_MASK);
8825 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8825 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8826 8826
8827 /* if UNDI is loaded on the other port */ 8827 /* if UNDI is loaded on the other port */
8828 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 8828 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8829 8829
8830 /* send "DONE" for previous unload */ 8830 /* send "DONE" for previous unload */
8831 bnx2x_fw_command(bp, 8831 bnx2x_fw_command(bp,
8832 DRV_MSG_CODE_UNLOAD_DONE, 0); 8832 DRV_MSG_CODE_UNLOAD_DONE, 0);
8833 8833
8834 /* unload UNDI on port 1 */ 8834 /* unload UNDI on port 1 */
8835 bp->pf_num = 1; 8835 bp->pf_num = 1;
8836 bp->fw_seq = 8836 bp->fw_seq =
8837 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8837 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8838 DRV_MSG_SEQ_NUMBER_MASK); 8838 DRV_MSG_SEQ_NUMBER_MASK);
8839 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8839 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8840 8840
8841 bnx2x_fw_command(bp, reset_code, 0); 8841 bnx2x_fw_command(bp, reset_code, 0);
8842 } 8842 }
8843 8843
8844 bnx2x_undi_int_disable(bp); 8844 bnx2x_undi_int_disable(bp);
8845 port = BP_PORT(bp); 8845 port = BP_PORT(bp);
8846 8846
8847 /* close input traffic and wait for it */ 8847 /* close input traffic and wait for it */
8848 /* Do not rcv packets to BRB */ 8848 /* Do not rcv packets to BRB */
8849 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : 8849 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8850 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); 8850 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8851 /* Do not direct rcv packets that are not for MCP to 8851 /* Do not direct rcv packets that are not for MCP to
8852 * the BRB */ 8852 * the BRB */
8853 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8853 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8854 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8854 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8855 /* clear AEU */ 8855 /* clear AEU */
8856 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8856 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8857 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); 8857 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8858 msleep(10); 8858 msleep(10);
8859 8859
8860 /* save NIG port swap info */ 8860 /* save NIG port swap info */
8861 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8861 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8862 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8862 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8863 /* reset device */ 8863 /* reset device */
8864 REG_WR(bp, 8864 REG_WR(bp,
8865 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8865 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8866 0xd3ffffff); 8866 0xd3ffffff);
8867 8867
8868 value = 0x1400; 8868 value = 0x1400;
8869 if (CHIP_IS_E3(bp)) { 8869 if (CHIP_IS_E3(bp)) {
8870 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 8870 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8871 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 8871 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8872 } 8872 }
8873 8873
8874 REG_WR(bp, 8874 REG_WR(bp,
8875 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8875 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8876 value); 8876 value);
8877 8877
8878 /* take the NIG out of reset and restore swap values */ 8878 /* take the NIG out of reset and restore swap values */
8879 REG_WR(bp, 8879 REG_WR(bp,
8880 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 8880 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8881 MISC_REGISTERS_RESET_REG_1_RST_NIG); 8881 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8882 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); 8882 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8883 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); 8883 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8884 8884
8885 /* send unload done to the MCP */ 8885 /* send unload done to the MCP */
8886 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8886 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8887 8887
8888 /* restore our func and fw_seq */ 8888 /* restore our func and fw_seq */
8889 bp->pf_num = orig_pf_num; 8889 bp->pf_num = orig_pf_num;
8890 bp->fw_seq = 8890 bp->fw_seq =
8891 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8891 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8892 DRV_MSG_SEQ_NUMBER_MASK); 8892 DRV_MSG_SEQ_NUMBER_MASK);
8893 } 8893 }
8894 8894
8895 /* now it's safe to release the lock */ 8895 /* now it's safe to release the lock */
8896 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8896 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8897 } 8897 }
8898 } 8898 }
8899 8899
8900 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 8900 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8901 { 8901 {
8902 u32 val, val2, val3, val4, id, boot_mode; 8902 u32 val, val2, val3, val4, id, boot_mode;
8903 u16 pmc; 8903 u16 pmc;
8904 8904
8905 /* Get the chip revision id and number. */ 8905 /* Get the chip revision id and number. */
8906 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 8906 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8907 val = REG_RD(bp, MISC_REG_CHIP_NUM); 8907 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8908 id = ((val & 0xffff) << 16); 8908 id = ((val & 0xffff) << 16);
8909 val = REG_RD(bp, MISC_REG_CHIP_REV); 8909 val = REG_RD(bp, MISC_REG_CHIP_REV);
8910 id |= ((val & 0xf) << 12); 8910 id |= ((val & 0xf) << 12);
8911 val = REG_RD(bp, MISC_REG_CHIP_METAL); 8911 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8912 id |= ((val & 0xff) << 4); 8912 id |= ((val & 0xff) << 4);
8913 val = REG_RD(bp, MISC_REG_BOND_ID); 8913 val = REG_RD(bp, MISC_REG_BOND_ID);
8914 id |= (val & 0xf); 8914 id |= (val & 0xf);
8915 bp->common.chip_id = id; 8915 bp->common.chip_id = id;
8916 8916
8917 /* Set doorbell size */ 8917 /* Set doorbell size */
8918 bp->db_size = (1 << BNX2X_DB_SHIFT); 8918 bp->db_size = (1 << BNX2X_DB_SHIFT);
8919 8919
8920 if (!CHIP_IS_E1x(bp)) { 8920 if (!CHIP_IS_E1x(bp)) {
8921 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 8921 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8922 if ((val & 1) == 0) 8922 if ((val & 1) == 0)
8923 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 8923 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8924 else 8924 else
8925 val = (val >> 1) & 1; 8925 val = (val >> 1) & 1;
8926 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 8926 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8927 "2_PORT_MODE"); 8927 "2_PORT_MODE");
8928 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 8928 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8929 CHIP_2_PORT_MODE; 8929 CHIP_2_PORT_MODE;
8930 8930
8931 if (CHIP_MODE_IS_4_PORT(bp)) 8931 if (CHIP_MODE_IS_4_PORT(bp))
8932 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 8932 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8933 else 8933 else
8934 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 8934 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8935 } else { 8935 } else {
8936 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 8936 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8937 bp->pfid = bp->pf_num; /* 0..7 */ 8937 bp->pfid = bp->pf_num; /* 0..7 */
8938 } 8938 }
8939 8939
8940 bp->link_params.chip_id = bp->common.chip_id; 8940 bp->link_params.chip_id = bp->common.chip_id;
8941 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 8941 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8942 8942
8943 val = (REG_RD(bp, 0x2874) & 0x55); 8943 val = (REG_RD(bp, 0x2874) & 0x55);
8944 if ((bp->common.chip_id & 0x1) || 8944 if ((bp->common.chip_id & 0x1) ||
8945 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 8945 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8946 bp->flags |= ONE_PORT_FLAG; 8946 bp->flags |= ONE_PORT_FLAG;
8947 BNX2X_DEV_INFO("single port device\n"); 8947 BNX2X_DEV_INFO("single port device\n");
8948 } 8948 }
8949 8949
8950 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 8950 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8951 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 8951 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8952 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 8952 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8953 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 8953 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8954 bp->common.flash_size, bp->common.flash_size); 8954 bp->common.flash_size, bp->common.flash_size);
8955 8955
8956 bnx2x_init_shmem(bp); 8956 bnx2x_init_shmem(bp);
8957 8957
8958 8958
8959 8959
8960 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 8960 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8961 MISC_REG_GENERIC_CR_1 : 8961 MISC_REG_GENERIC_CR_1 :
8962 MISC_REG_GENERIC_CR_0)); 8962 MISC_REG_GENERIC_CR_0));
8963 8963
8964 bp->link_params.shmem_base = bp->common.shmem_base; 8964 bp->link_params.shmem_base = bp->common.shmem_base;
8965 bp->link_params.shmem2_base = bp->common.shmem2_base; 8965 bp->link_params.shmem2_base = bp->common.shmem2_base;
8966 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 8966 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8967 bp->common.shmem_base, bp->common.shmem2_base); 8967 bp->common.shmem_base, bp->common.shmem2_base);
8968 8968
8969 if (!bp->common.shmem_base) { 8969 if (!bp->common.shmem_base) {
8970 BNX2X_DEV_INFO("MCP not active\n"); 8970 BNX2X_DEV_INFO("MCP not active\n");
8971 bp->flags |= NO_MCP_FLAG; 8971 bp->flags |= NO_MCP_FLAG;
8972 return; 8972 return;
8973 } 8973 }
8974 8974
8975 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 8975 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8976 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 8976 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8977 8977
8978 bp->link_params.hw_led_mode = ((bp->common.hw_config & 8978 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8979 SHARED_HW_CFG_LED_MODE_MASK) >> 8979 SHARED_HW_CFG_LED_MODE_MASK) >>
8980 SHARED_HW_CFG_LED_MODE_SHIFT); 8980 SHARED_HW_CFG_LED_MODE_SHIFT);
8981 8981
8982 bp->link_params.feature_config_flags = 0; 8982 bp->link_params.feature_config_flags = 0;
8983 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 8983 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8984 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 8984 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8985 bp->link_params.feature_config_flags |= 8985 bp->link_params.feature_config_flags |=
8986 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 8986 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8987 else 8987 else
8988 bp->link_params.feature_config_flags &= 8988 bp->link_params.feature_config_flags &=
8989 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 8989 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8990 8990
8991 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 8991 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8992 bp->common.bc_ver = val; 8992 bp->common.bc_ver = val;
8993 BNX2X_DEV_INFO("bc_ver %X\n", val); 8993 BNX2X_DEV_INFO("bc_ver %X\n", val);
8994 if (val < BNX2X_BC_VER) { 8994 if (val < BNX2X_BC_VER) {
8995 /* for now only warn 8995 /* for now only warn
8996 * later we might need to enforce this */ 8996 * later we might need to enforce this */
8997 BNX2X_ERR("This driver needs bc_ver %X but found %X, " 8997 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8998 "please upgrade BC\n", BNX2X_BC_VER, val); 8998 "please upgrade BC\n", BNX2X_BC_VER, val);
8999 } 8999 }
9000 bp->link_params.feature_config_flags |= 9000 bp->link_params.feature_config_flags |=
9001 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 9001 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
9002 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 9002 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9003 9003
9004 bp->link_params.feature_config_flags |= 9004 bp->link_params.feature_config_flags |=
9005 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 9005 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9006 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 9006 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
9007 9007
9008 bp->link_params.feature_config_flags |= 9008 bp->link_params.feature_config_flags |=
9009 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 9009 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9010 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 9010 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
9011 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 9011 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9012 BC_SUPPORTS_PFC_STATS : 0; 9012 BC_SUPPORTS_PFC_STATS : 0;
9013 9013
9014 boot_mode = SHMEM_RD(bp, 9014 boot_mode = SHMEM_RD(bp,
9015 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 9015 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9016 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 9016 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
9017 switch (boot_mode) { 9017 switch (boot_mode) {
9018 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 9018 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
9019 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 9019 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9020 break; 9020 break;
9021 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 9021 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
9022 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 9022 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9023 break; 9023 break;
9024 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 9024 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
9025 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 9025 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9026 break; 9026 break;
9027 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 9027 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
9028 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 9028 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9029 break; 9029 break;
9030 } 9030 }
9031 9031
9032 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 9032 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9033 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 9033 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9034 9034
9035 BNX2X_DEV_INFO("%sWoL capable\n", 9035 BNX2X_DEV_INFO("%sWoL capable\n",
9036 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 9036 (bp->flags & NO_WOL_FLAG) ? "not " : "");
9037 9037
9038 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 9038 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9039 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 9039 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9040 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 9040 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9041 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 9041 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9042 9042
9043 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 9043 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
9044 val, val2, val3, val4); 9044 val, val2, val3, val4);
9045 } 9045 }
9046 9046
9047 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 9047 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9048 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 9048 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9049 9049
9050 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 9050 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
9051 { 9051 {
9052 int pfid = BP_FUNC(bp); 9052 int pfid = BP_FUNC(bp);
9053 int igu_sb_id; 9053 int igu_sb_id;
9054 u32 val; 9054 u32 val;
9055 u8 fid, igu_sb_cnt = 0; 9055 u8 fid, igu_sb_cnt = 0;
9056 9056
9057 bp->igu_base_sb = 0xff; 9057 bp->igu_base_sb = 0xff;
9058 if (CHIP_INT_MODE_IS_BC(bp)) { 9058 if (CHIP_INT_MODE_IS_BC(bp)) {
9059 int vn = BP_VN(bp); 9059 int vn = BP_VN(bp);
9060 igu_sb_cnt = bp->igu_sb_cnt; 9060 igu_sb_cnt = bp->igu_sb_cnt;
9061 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 9061 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
9062 FP_SB_MAX_E1x; 9062 FP_SB_MAX_E1x;
9063 9063
9064 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 9064 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
9065 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 9065 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
9066 9066
9067 return; 9067 return;
9068 } 9068 }
9069 9069
9070 /* IGU in normal mode - read CAM */ 9070 /* IGU in normal mode - read CAM */
9071 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 9071 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
9072 igu_sb_id++) { 9072 igu_sb_id++) {
9073 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 9073 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
9074 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 9074 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
9075 continue; 9075 continue;
9076 fid = IGU_FID(val); 9076 fid = IGU_FID(val);
9077 if ((fid & IGU_FID_ENCODE_IS_PF)) { 9077 if ((fid & IGU_FID_ENCODE_IS_PF)) {
9078 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 9078 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
9079 continue; 9079 continue;
9080 if (IGU_VEC(val) == 0) 9080 if (IGU_VEC(val) == 0)
9081 /* default status block */ 9081 /* default status block */
9082 bp->igu_dsb_id = igu_sb_id; 9082 bp->igu_dsb_id = igu_sb_id;
9083 else { 9083 else {
9084 if (bp->igu_base_sb == 0xff) 9084 if (bp->igu_base_sb == 0xff)
9085 bp->igu_base_sb = igu_sb_id; 9085 bp->igu_base_sb = igu_sb_id;
9086 igu_sb_cnt++; 9086 igu_sb_cnt++;
9087 } 9087 }
9088 } 9088 }
9089 } 9089 }
9090 9090
9091 #ifdef CONFIG_PCI_MSI 9091 #ifdef CONFIG_PCI_MSI
9092 /* 9092 /*
9093 * It's expected that number of CAM entries for this functions is equal 9093 * It's expected that number of CAM entries for this functions is equal
9094 * to the number evaluated based on the MSI-X table size. We want a 9094 * to the number evaluated based on the MSI-X table size. We want a
9095 * harsh warning if these values are different! 9095 * harsh warning if these values are different!
9096 */ 9096 */
9097 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); 9097 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
9098 #endif 9098 #endif
9099 9099
9100 if (igu_sb_cnt == 0) 9100 if (igu_sb_cnt == 0)
9101 BNX2X_ERR("CAM configuration error\n"); 9101 BNX2X_ERR("CAM configuration error\n");
9102 } 9102 }
9103 9103
9104 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 9104 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9105 u32 switch_cfg) 9105 u32 switch_cfg)
9106 { 9106 {
9107 int cfg_size = 0, idx, port = BP_PORT(bp); 9107 int cfg_size = 0, idx, port = BP_PORT(bp);
9108 9108
9109 /* Aggregation of supported attributes of all external phys */ 9109 /* Aggregation of supported attributes of all external phys */
9110 bp->port.supported[0] = 0; 9110 bp->port.supported[0] = 0;
9111 bp->port.supported[1] = 0; 9111 bp->port.supported[1] = 0;
9112 switch (bp->link_params.num_phys) { 9112 switch (bp->link_params.num_phys) {
9113 case 1: 9113 case 1:
9114 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 9114 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
9115 cfg_size = 1; 9115 cfg_size = 1;
9116 break; 9116 break;
9117 case 2: 9117 case 2:
9118 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 9118 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
9119 cfg_size = 1; 9119 cfg_size = 1;
9120 break; 9120 break;
9121 case 3: 9121 case 3:
9122 if (bp->link_params.multi_phy_config & 9122 if (bp->link_params.multi_phy_config &
9123 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 9123 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
9124 bp->port.supported[1] = 9124 bp->port.supported[1] =
9125 bp->link_params.phy[EXT_PHY1].supported; 9125 bp->link_params.phy[EXT_PHY1].supported;
9126 bp->port.supported[0] = 9126 bp->port.supported[0] =
9127 bp->link_params.phy[EXT_PHY2].supported; 9127 bp->link_params.phy[EXT_PHY2].supported;
9128 } else { 9128 } else {
9129 bp->port.supported[0] = 9129 bp->port.supported[0] =
9130 bp->link_params.phy[EXT_PHY1].supported; 9130 bp->link_params.phy[EXT_PHY1].supported;
9131 bp->port.supported[1] = 9131 bp->port.supported[1] =
9132 bp->link_params.phy[EXT_PHY2].supported; 9132 bp->link_params.phy[EXT_PHY2].supported;
9133 } 9133 }
9134 cfg_size = 2; 9134 cfg_size = 2;
9135 break; 9135 break;
9136 } 9136 }
9137 9137
9138 if (!(bp->port.supported[0] || bp->port.supported[1])) { 9138 if (!(bp->port.supported[0] || bp->port.supported[1])) {
9139 BNX2X_ERR("NVRAM config error. BAD phy config." 9139 BNX2X_ERR("NVRAM config error. BAD phy config."
9140 "PHY1 config 0x%x, PHY2 config 0x%x\n", 9140 "PHY1 config 0x%x, PHY2 config 0x%x\n",
9141 SHMEM_RD(bp, 9141 SHMEM_RD(bp,
9142 dev_info.port_hw_config[port].external_phy_config), 9142 dev_info.port_hw_config[port].external_phy_config),
9143 SHMEM_RD(bp, 9143 SHMEM_RD(bp,
9144 dev_info.port_hw_config[port].external_phy_config2)); 9144 dev_info.port_hw_config[port].external_phy_config2));
9145 return; 9145 return;
9146 } 9146 }
9147 9147
9148 if (CHIP_IS_E3(bp)) 9148 if (CHIP_IS_E3(bp))
9149 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 9149 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
9150 else { 9150 else {
9151 switch (switch_cfg) { 9151 switch (switch_cfg) {
9152 case SWITCH_CFG_1G: 9152 case SWITCH_CFG_1G:
9153 bp->port.phy_addr = REG_RD( 9153 bp->port.phy_addr = REG_RD(
9154 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 9154 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
9155 break; 9155 break;
9156 case SWITCH_CFG_10G: 9156 case SWITCH_CFG_10G:
9157 bp->port.phy_addr = REG_RD( 9157 bp->port.phy_addr = REG_RD(
9158 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 9158 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
9159 break; 9159 break;
9160 default: 9160 default:
9161 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 9161 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9162 bp->port.link_config[0]); 9162 bp->port.link_config[0]);
9163 return; 9163 return;
9164 } 9164 }
9165 } 9165 }
9166 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 9166 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
9167 /* mask what we support according to speed_cap_mask per configuration */ 9167 /* mask what we support according to speed_cap_mask per configuration */
9168 for (idx = 0; idx < cfg_size; idx++) { 9168 for (idx = 0; idx < cfg_size; idx++) {
9169 if (!(bp->link_params.speed_cap_mask[idx] & 9169 if (!(bp->link_params.speed_cap_mask[idx] &
9170 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 9170 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
9171 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 9171 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
9172 9172
9173 if (!(bp->link_params.speed_cap_mask[idx] & 9173 if (!(bp->link_params.speed_cap_mask[idx] &
9174 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 9174 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
9175 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 9175 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
9176 9176
9177 if (!(bp->link_params.speed_cap_mask[idx] & 9177 if (!(bp->link_params.speed_cap_mask[idx] &
9178 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 9178 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
9179 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 9179 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
9180 9180
9181 if (!(bp->link_params.speed_cap_mask[idx] & 9181 if (!(bp->link_params.speed_cap_mask[idx] &
9182 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 9182 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
9183 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 9183 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
9184 9184
9185 if (!(bp->link_params.speed_cap_mask[idx] & 9185 if (!(bp->link_params.speed_cap_mask[idx] &
9186 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 9186 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
9187 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 9187 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
9188 SUPPORTED_1000baseT_Full); 9188 SUPPORTED_1000baseT_Full);
9189 9189
9190 if (!(bp->link_params.speed_cap_mask[idx] & 9190 if (!(bp->link_params.speed_cap_mask[idx] &
9191 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 9191 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
9192 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 9192 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
9193 9193
9194 if (!(bp->link_params.speed_cap_mask[idx] & 9194 if (!(bp->link_params.speed_cap_mask[idx] &
9195 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 9195 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
9196 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 9196 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
9197 9197
9198 } 9198 }
9199 9199
9200 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 9200 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
9201 bp->port.supported[1]); 9201 bp->port.supported[1]);
9202 } 9202 }
9203 9203
9204 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 9204 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9205 { 9205 {
9206 u32 link_config, idx, cfg_size = 0; 9206 u32 link_config, idx, cfg_size = 0;
9207 bp->port.advertising[0] = 0; 9207 bp->port.advertising[0] = 0;
9208 bp->port.advertising[1] = 0; 9208 bp->port.advertising[1] = 0;
9209 switch (bp->link_params.num_phys) { 9209 switch (bp->link_params.num_phys) {
9210 case 1: 9210 case 1:
9211 case 2: 9211 case 2:
9212 cfg_size = 1; 9212 cfg_size = 1;
9213 break; 9213 break;
9214 case 3: 9214 case 3:
9215 cfg_size = 2; 9215 cfg_size = 2;
9216 break; 9216 break;
9217 } 9217 }
9218 for (idx = 0; idx < cfg_size; idx++) { 9218 for (idx = 0; idx < cfg_size; idx++) {
9219 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 9219 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9220 link_config = bp->port.link_config[idx]; 9220 link_config = bp->port.link_config[idx];
9221 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 9221 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
9222 case PORT_FEATURE_LINK_SPEED_AUTO: 9222 case PORT_FEATURE_LINK_SPEED_AUTO:
9223 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 9223 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9224 bp->link_params.req_line_speed[idx] = 9224 bp->link_params.req_line_speed[idx] =
9225 SPEED_AUTO_NEG; 9225 SPEED_AUTO_NEG;
9226 bp->port.advertising[idx] |= 9226 bp->port.advertising[idx] |=
9227 bp->port.supported[idx]; 9227 bp->port.supported[idx];
9228 } else { 9228 } else {
9229 /* force 10G, no AN */ 9229 /* force 10G, no AN */
9230 bp->link_params.req_line_speed[idx] = 9230 bp->link_params.req_line_speed[idx] =
9231 SPEED_10000; 9231 SPEED_10000;
9232 bp->port.advertising[idx] |= 9232 bp->port.advertising[idx] |=
9233 (ADVERTISED_10000baseT_Full | 9233 (ADVERTISED_10000baseT_Full |
9234 ADVERTISED_FIBRE); 9234 ADVERTISED_FIBRE);
9235 continue; 9235 continue;
9236 } 9236 }
9237 break; 9237 break;
9238 9238
9239 case PORT_FEATURE_LINK_SPEED_10M_FULL: 9239 case PORT_FEATURE_LINK_SPEED_10M_FULL:
9240 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 9240 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9241 bp->link_params.req_line_speed[idx] = 9241 bp->link_params.req_line_speed[idx] =
9242 SPEED_10; 9242 SPEED_10;
9243 bp->port.advertising[idx] |= 9243 bp->port.advertising[idx] |=
9244 (ADVERTISED_10baseT_Full | 9244 (ADVERTISED_10baseT_Full |
9245 ADVERTISED_TP); 9245 ADVERTISED_TP);
9246 } else { 9246 } else {
9247 BNX2X_ERR("NVRAM config error. " 9247 BNX2X_ERR("NVRAM config error. "
9248 "Invalid link_config 0x%x" 9248 "Invalid link_config 0x%x"
9249 " speed_cap_mask 0x%x\n", 9249 " speed_cap_mask 0x%x\n",
9250 link_config, 9250 link_config,
9251 bp->link_params.speed_cap_mask[idx]); 9251 bp->link_params.speed_cap_mask[idx]);
9252 return; 9252 return;
9253 } 9253 }
9254 break; 9254 break;
9255 9255
9256 case PORT_FEATURE_LINK_SPEED_10M_HALF: 9256 case PORT_FEATURE_LINK_SPEED_10M_HALF:
9257 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 9257 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9258 bp->link_params.req_line_speed[idx] = 9258 bp->link_params.req_line_speed[idx] =
9259 SPEED_10; 9259 SPEED_10;
9260 bp->link_params.req_duplex[idx] = 9260 bp->link_params.req_duplex[idx] =
9261 DUPLEX_HALF; 9261 DUPLEX_HALF;
9262 bp->port.advertising[idx] |= 9262 bp->port.advertising[idx] |=
9263 (ADVERTISED_10baseT_Half | 9263 (ADVERTISED_10baseT_Half |
9264 ADVERTISED_TP); 9264 ADVERTISED_TP);
9265 } else { 9265 } else {
9266 BNX2X_ERR("NVRAM config error. " 9266 BNX2X_ERR("NVRAM config error. "
9267 "Invalid link_config 0x%x" 9267 "Invalid link_config 0x%x"
9268 " speed_cap_mask 0x%x\n", 9268 " speed_cap_mask 0x%x\n",
9269 link_config, 9269 link_config,
9270 bp->link_params.speed_cap_mask[idx]); 9270 bp->link_params.speed_cap_mask[idx]);
9271 return; 9271 return;
9272 } 9272 }
9273 break; 9273 break;
9274 9274
9275 case PORT_FEATURE_LINK_SPEED_100M_FULL: 9275 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9276 if (bp->port.supported[idx] & 9276 if (bp->port.supported[idx] &
9277 SUPPORTED_100baseT_Full) { 9277 SUPPORTED_100baseT_Full) {
9278 bp->link_params.req_line_speed[idx] = 9278 bp->link_params.req_line_speed[idx] =
9279 SPEED_100; 9279 SPEED_100;
9280 bp->port.advertising[idx] |= 9280 bp->port.advertising[idx] |=
9281 (ADVERTISED_100baseT_Full | 9281 (ADVERTISED_100baseT_Full |
9282 ADVERTISED_TP); 9282 ADVERTISED_TP);
9283 } else { 9283 } else {
9284 BNX2X_ERR("NVRAM config error. " 9284 BNX2X_ERR("NVRAM config error. "
9285 "Invalid link_config 0x%x" 9285 "Invalid link_config 0x%x"
9286 " speed_cap_mask 0x%x\n", 9286 " speed_cap_mask 0x%x\n",
9287 link_config, 9287 link_config,
9288 bp->link_params.speed_cap_mask[idx]); 9288 bp->link_params.speed_cap_mask[idx]);
9289 return; 9289 return;
9290 } 9290 }
9291 break; 9291 break;
9292 9292
9293 case PORT_FEATURE_LINK_SPEED_100M_HALF: 9293 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9294 if (bp->port.supported[idx] & 9294 if (bp->port.supported[idx] &
9295 SUPPORTED_100baseT_Half) { 9295 SUPPORTED_100baseT_Half) {
9296 bp->link_params.req_line_speed[idx] = 9296 bp->link_params.req_line_speed[idx] =
9297 SPEED_100; 9297 SPEED_100;
9298 bp->link_params.req_duplex[idx] = 9298 bp->link_params.req_duplex[idx] =
9299 DUPLEX_HALF; 9299 DUPLEX_HALF;
9300 bp->port.advertising[idx] |= 9300 bp->port.advertising[idx] |=
9301 (ADVERTISED_100baseT_Half | 9301 (ADVERTISED_100baseT_Half |
9302 ADVERTISED_TP); 9302 ADVERTISED_TP);
9303 } else { 9303 } else {
9304 BNX2X_ERR("NVRAM config error. " 9304 BNX2X_ERR("NVRAM config error. "
9305 "Invalid link_config 0x%x" 9305 "Invalid link_config 0x%x"
9306 " speed_cap_mask 0x%x\n", 9306 " speed_cap_mask 0x%x\n",
9307 link_config, 9307 link_config,
9308 bp->link_params.speed_cap_mask[idx]); 9308 bp->link_params.speed_cap_mask[idx]);
9309 return; 9309 return;
9310 } 9310 }
9311 break; 9311 break;
9312 9312
9313 case PORT_FEATURE_LINK_SPEED_1G: 9313 case PORT_FEATURE_LINK_SPEED_1G:
9314 if (bp->port.supported[idx] & 9314 if (bp->port.supported[idx] &
9315 SUPPORTED_1000baseT_Full) { 9315 SUPPORTED_1000baseT_Full) {
9316 bp->link_params.req_line_speed[idx] = 9316 bp->link_params.req_line_speed[idx] =
9317 SPEED_1000; 9317 SPEED_1000;
9318 bp->port.advertising[idx] |= 9318 bp->port.advertising[idx] |=
9319 (ADVERTISED_1000baseT_Full | 9319 (ADVERTISED_1000baseT_Full |
9320 ADVERTISED_TP); 9320 ADVERTISED_TP);
9321 } else { 9321 } else {
9322 BNX2X_ERR("NVRAM config error. " 9322 BNX2X_ERR("NVRAM config error. "
9323 "Invalid link_config 0x%x" 9323 "Invalid link_config 0x%x"
9324 " speed_cap_mask 0x%x\n", 9324 " speed_cap_mask 0x%x\n",
9325 link_config, 9325 link_config,
9326 bp->link_params.speed_cap_mask[idx]); 9326 bp->link_params.speed_cap_mask[idx]);
9327 return; 9327 return;
9328 } 9328 }
9329 break; 9329 break;
9330 9330
9331 case PORT_FEATURE_LINK_SPEED_2_5G: 9331 case PORT_FEATURE_LINK_SPEED_2_5G:
9332 if (bp->port.supported[idx] & 9332 if (bp->port.supported[idx] &
9333 SUPPORTED_2500baseX_Full) { 9333 SUPPORTED_2500baseX_Full) {
9334 bp->link_params.req_line_speed[idx] = 9334 bp->link_params.req_line_speed[idx] =
9335 SPEED_2500; 9335 SPEED_2500;
9336 bp->port.advertising[idx] |= 9336 bp->port.advertising[idx] |=
9337 (ADVERTISED_2500baseX_Full | 9337 (ADVERTISED_2500baseX_Full |
9338 ADVERTISED_TP); 9338 ADVERTISED_TP);
9339 } else { 9339 } else {
9340 BNX2X_ERR("NVRAM config error. " 9340 BNX2X_ERR("NVRAM config error. "
9341 "Invalid link_config 0x%x" 9341 "Invalid link_config 0x%x"
9342 " speed_cap_mask 0x%x\n", 9342 " speed_cap_mask 0x%x\n",
9343 link_config, 9343 link_config,
9344 bp->link_params.speed_cap_mask[idx]); 9344 bp->link_params.speed_cap_mask[idx]);
9345 return; 9345 return;
9346 } 9346 }
9347 break; 9347 break;
9348 9348
9349 case PORT_FEATURE_LINK_SPEED_10G_CX4: 9349 case PORT_FEATURE_LINK_SPEED_10G_CX4:
9350 if (bp->port.supported[idx] & 9350 if (bp->port.supported[idx] &
9351 SUPPORTED_10000baseT_Full) { 9351 SUPPORTED_10000baseT_Full) {
9352 bp->link_params.req_line_speed[idx] = 9352 bp->link_params.req_line_speed[idx] =
9353 SPEED_10000; 9353 SPEED_10000;
9354 bp->port.advertising[idx] |= 9354 bp->port.advertising[idx] |=
9355 (ADVERTISED_10000baseT_Full | 9355 (ADVERTISED_10000baseT_Full |
9356 ADVERTISED_FIBRE); 9356 ADVERTISED_FIBRE);
9357 } else { 9357 } else {
9358 BNX2X_ERR("NVRAM config error. " 9358 BNX2X_ERR("NVRAM config error. "
9359 "Invalid link_config 0x%x" 9359 "Invalid link_config 0x%x"
9360 " speed_cap_mask 0x%x\n", 9360 " speed_cap_mask 0x%x\n",
9361 link_config, 9361 link_config,
9362 bp->link_params.speed_cap_mask[idx]); 9362 bp->link_params.speed_cap_mask[idx]);
9363 return; 9363 return;
9364 } 9364 }
9365 break; 9365 break;
9366 case PORT_FEATURE_LINK_SPEED_20G: 9366 case PORT_FEATURE_LINK_SPEED_20G:
9367 bp->link_params.req_line_speed[idx] = SPEED_20000; 9367 bp->link_params.req_line_speed[idx] = SPEED_20000;
9368 9368
9369 break; 9369 break;
9370 default: 9370 default:
9371 BNX2X_ERR("NVRAM config error. " 9371 BNX2X_ERR("NVRAM config error. "
9372 "BAD link speed link_config 0x%x\n", 9372 "BAD link speed link_config 0x%x\n",
9373 link_config); 9373 link_config);
9374 bp->link_params.req_line_speed[idx] = 9374 bp->link_params.req_line_speed[idx] =
9375 SPEED_AUTO_NEG; 9375 SPEED_AUTO_NEG;
9376 bp->port.advertising[idx] = 9376 bp->port.advertising[idx] =
9377 bp->port.supported[idx]; 9377 bp->port.supported[idx];
9378 break; 9378 break;
9379 } 9379 }
9380 9380
9381 bp->link_params.req_flow_ctrl[idx] = (link_config & 9381 bp->link_params.req_flow_ctrl[idx] = (link_config &
9382 PORT_FEATURE_FLOW_CONTROL_MASK); 9382 PORT_FEATURE_FLOW_CONTROL_MASK);
9383 if ((bp->link_params.req_flow_ctrl[idx] == 9383 if ((bp->link_params.req_flow_ctrl[idx] ==
9384 BNX2X_FLOW_CTRL_AUTO) && 9384 BNX2X_FLOW_CTRL_AUTO) &&
9385 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { 9385 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9386 bp->link_params.req_flow_ctrl[idx] = 9386 bp->link_params.req_flow_ctrl[idx] =
9387 BNX2X_FLOW_CTRL_NONE; 9387 BNX2X_FLOW_CTRL_NONE;
9388 } 9388 }
9389 9389
9390 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" 9390 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9391 " 0x%x advertising 0x%x\n", 9391 " 0x%x advertising 0x%x\n",
9392 bp->link_params.req_line_speed[idx], 9392 bp->link_params.req_line_speed[idx],
9393 bp->link_params.req_duplex[idx], 9393 bp->link_params.req_duplex[idx],
9394 bp->link_params.req_flow_ctrl[idx], 9394 bp->link_params.req_flow_ctrl[idx],
9395 bp->port.advertising[idx]); 9395 bp->port.advertising[idx]);
9396 } 9396 }
9397 } 9397 }
9398 9398
9399 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 9399 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9400 { 9400 {
9401 mac_hi = cpu_to_be16(mac_hi); 9401 mac_hi = cpu_to_be16(mac_hi);
9402 mac_lo = cpu_to_be32(mac_lo); 9402 mac_lo = cpu_to_be32(mac_lo);
9403 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 9403 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9404 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 9404 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9405 } 9405 }
9406 9406
9407 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 9407 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
9408 { 9408 {
9409 int port = BP_PORT(bp); 9409 int port = BP_PORT(bp);
9410 u32 config; 9410 u32 config;
9411 u32 ext_phy_type, ext_phy_config; 9411 u32 ext_phy_type, ext_phy_config;
9412 9412
9413 bp->link_params.bp = bp; 9413 bp->link_params.bp = bp;
9414 bp->link_params.port = port; 9414 bp->link_params.port = port;
9415 9415
9416 bp->link_params.lane_config = 9416 bp->link_params.lane_config =
9417 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 9417 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
9418 9418
9419 bp->link_params.speed_cap_mask[0] = 9419 bp->link_params.speed_cap_mask[0] =
9420 SHMEM_RD(bp, 9420 SHMEM_RD(bp,
9421 dev_info.port_hw_config[port].speed_capability_mask); 9421 dev_info.port_hw_config[port].speed_capability_mask);
9422 bp->link_params.speed_cap_mask[1] = 9422 bp->link_params.speed_cap_mask[1] =
9423 SHMEM_RD(bp, 9423 SHMEM_RD(bp,
9424 dev_info.port_hw_config[port].speed_capability_mask2); 9424 dev_info.port_hw_config[port].speed_capability_mask2);
9425 bp->port.link_config[0] = 9425 bp->port.link_config[0] =
9426 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 9426 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9427 9427
9428 bp->port.link_config[1] = 9428 bp->port.link_config[1] =
9429 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 9429 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
9430 9430
9431 bp->link_params.multi_phy_config = 9431 bp->link_params.multi_phy_config =
9432 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 9432 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
9433 /* If the device is capable of WoL, set the default state according 9433 /* If the device is capable of WoL, set the default state according
9434 * to the HW 9434 * to the HW
9435 */ 9435 */
9436 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 9436 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
9437 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9437 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9438 (config & PORT_FEATURE_WOL_ENABLED)); 9438 (config & PORT_FEATURE_WOL_ENABLED));
9439 9439
9440 BNX2X_DEV_INFO("lane_config 0x%08x " 9440 BNX2X_DEV_INFO("lane_config 0x%08x "
9441 "speed_cap_mask0 0x%08x link_config0 0x%08x\n", 9441 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9442 bp->link_params.lane_config, 9442 bp->link_params.lane_config,
9443 bp->link_params.speed_cap_mask[0], 9443 bp->link_params.speed_cap_mask[0],
9444 bp->port.link_config[0]); 9444 bp->port.link_config[0]);
9445 9445
9446 bp->link_params.switch_cfg = (bp->port.link_config[0] & 9446 bp->link_params.switch_cfg = (bp->port.link_config[0] &
9447 PORT_FEATURE_CONNECTED_SWITCH_MASK); 9447 PORT_FEATURE_CONNECTED_SWITCH_MASK);
9448 bnx2x_phy_probe(&bp->link_params); 9448 bnx2x_phy_probe(&bp->link_params);
9449 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 9449 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
9450 9450
9451 bnx2x_link_settings_requested(bp); 9451 bnx2x_link_settings_requested(bp);
9452 9452
9453 /* 9453 /*
9454 * If connected directly, work with the internal PHY, otherwise, work 9454 * If connected directly, work with the internal PHY, otherwise, work
9455 * with the external PHY 9455 * with the external PHY
9456 */ 9456 */
9457 ext_phy_config = 9457 ext_phy_config =
9458 SHMEM_RD(bp, 9458 SHMEM_RD(bp,
9459 dev_info.port_hw_config[port].external_phy_config); 9459 dev_info.port_hw_config[port].external_phy_config);
9460 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 9460 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
9461 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9461 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9462 bp->mdio.prtad = bp->port.phy_addr; 9462 bp->mdio.prtad = bp->port.phy_addr;
9463 9463
9464 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 9464 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9465 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 9465 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9466 bp->mdio.prtad = 9466 bp->mdio.prtad =
9467 XGXS_EXT_PHY_ADDR(ext_phy_config); 9467 XGXS_EXT_PHY_ADDR(ext_phy_config);
9468 9468
9469 /* 9469 /*
9470 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) 9470 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9471 * In MF mode, it is set to cover self test cases 9471 * In MF mode, it is set to cover self test cases
9472 */ 9472 */
9473 if (IS_MF(bp)) 9473 if (IS_MF(bp))
9474 bp->port.need_hw_lock = 1; 9474 bp->port.need_hw_lock = 1;
9475 else 9475 else
9476 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, 9476 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9477 bp->common.shmem_base, 9477 bp->common.shmem_base,
9478 bp->common.shmem2_base); 9478 bp->common.shmem2_base);
9479 } 9479 }
9480 9480
9481 #ifdef BCM_CNIC 9481 #ifdef BCM_CNIC
9482 void bnx2x_get_iscsi_info(struct bnx2x *bp) 9482 void bnx2x_get_iscsi_info(struct bnx2x *bp)
9483 { 9483 {
9484 int port = BP_PORT(bp); 9484 int port = BP_PORT(bp);
9485 9485
9486 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9486 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9487 drv_lic_key[port].max_iscsi_conn); 9487 drv_lic_key[port].max_iscsi_conn);
9488 9488
9489 /* Get the number of maximum allowed iSCSI connections */ 9489 /* Get the number of maximum allowed iSCSI connections */
9490 bp->cnic_eth_dev.max_iscsi_conn = 9490 bp->cnic_eth_dev.max_iscsi_conn =
9491 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 9491 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9492 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 9492 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9493 9493
9494 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 9494 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
9495 bp->cnic_eth_dev.max_iscsi_conn); 9495 bp->cnic_eth_dev.max_iscsi_conn);
9496 9496
9497 /* 9497 /*
9498 * If maximum allowed number of connections is zero - 9498 * If maximum allowed number of connections is zero -
9499 * disable the feature. 9499 * disable the feature.
9500 */ 9500 */
9501 if (!bp->cnic_eth_dev.max_iscsi_conn) 9501 if (!bp->cnic_eth_dev.max_iscsi_conn)
9502 bp->flags |= NO_ISCSI_FLAG; 9502 bp->flags |= NO_ISCSI_FLAG;
9503 } 9503 }
9504 9504
9505 static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) 9505 static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
9506 { 9506 {
9507 int port = BP_PORT(bp); 9507 int port = BP_PORT(bp);
9508 int func = BP_ABS_FUNC(bp); 9508 int func = BP_ABS_FUNC(bp);
9509 9509
9510 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9510 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9511 drv_lic_key[port].max_fcoe_conn); 9511 drv_lic_key[port].max_fcoe_conn);
9512 9512
9513 /* Get the number of maximum allowed FCoE connections */ 9513 /* Get the number of maximum allowed FCoE connections */
9514 bp->cnic_eth_dev.max_fcoe_conn = 9514 bp->cnic_eth_dev.max_fcoe_conn =
9515 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 9515 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9516 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 9516 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9517 9517
9518 /* Read the WWN: */ 9518 /* Read the WWN: */
9519 if (!IS_MF(bp)) { 9519 if (!IS_MF(bp)) {
9520 /* Port info */ 9520 /* Port info */
9521 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9521 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9522 SHMEM_RD(bp, 9522 SHMEM_RD(bp,
9523 dev_info.port_hw_config[port]. 9523 dev_info.port_hw_config[port].
9524 fcoe_wwn_port_name_upper); 9524 fcoe_wwn_port_name_upper);
9525 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9525 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9526 SHMEM_RD(bp, 9526 SHMEM_RD(bp,
9527 dev_info.port_hw_config[port]. 9527 dev_info.port_hw_config[port].
9528 fcoe_wwn_port_name_lower); 9528 fcoe_wwn_port_name_lower);
9529 9529
9530 /* Node info */ 9530 /* Node info */
9531 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9531 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9532 SHMEM_RD(bp, 9532 SHMEM_RD(bp,
9533 dev_info.port_hw_config[port]. 9533 dev_info.port_hw_config[port].
9534 fcoe_wwn_node_name_upper); 9534 fcoe_wwn_node_name_upper);
9535 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9535 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9536 SHMEM_RD(bp, 9536 SHMEM_RD(bp,
9537 dev_info.port_hw_config[port]. 9537 dev_info.port_hw_config[port].
9538 fcoe_wwn_node_name_lower); 9538 fcoe_wwn_node_name_lower);
9539 } else if (!IS_MF_SD(bp)) { 9539 } else if (!IS_MF_SD(bp)) {
9540 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9540 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9541 9541
9542 /* 9542 /*
9543 * Read the WWN info only if the FCoE feature is enabled for 9543 * Read the WWN info only if the FCoE feature is enabled for
9544 * this function. 9544 * this function.
9545 */ 9545 */
9546 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9546 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9547 /* Port info */ 9547 /* Port info */
9548 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9548 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9549 MF_CFG_RD(bp, func_ext_config[func]. 9549 MF_CFG_RD(bp, func_ext_config[func].
9550 fcoe_wwn_port_name_upper); 9550 fcoe_wwn_port_name_upper);
9551 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9551 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9552 MF_CFG_RD(bp, func_ext_config[func]. 9552 MF_CFG_RD(bp, func_ext_config[func].
9553 fcoe_wwn_port_name_lower); 9553 fcoe_wwn_port_name_lower);
9554 9554
9555 /* Node info */ 9555 /* Node info */
9556 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9556 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9557 MF_CFG_RD(bp, func_ext_config[func]. 9557 MF_CFG_RD(bp, func_ext_config[func].
9558 fcoe_wwn_node_name_upper); 9558 fcoe_wwn_node_name_upper);
9559 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9559 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9560 MF_CFG_RD(bp, func_ext_config[func]. 9560 MF_CFG_RD(bp, func_ext_config[func].
9561 fcoe_wwn_node_name_lower); 9561 fcoe_wwn_node_name_lower);
9562 } 9562 }
9563 } 9563 }
9564 9564
9565 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 9565 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
9566 9566
9567 /* 9567 /*
9568 * If maximum allowed number of connections is zero - 9568 * If maximum allowed number of connections is zero -
9569 * disable the feature. 9569 * disable the feature.
9570 */ 9570 */
9571 if (!bp->cnic_eth_dev.max_fcoe_conn) 9571 if (!bp->cnic_eth_dev.max_fcoe_conn)
9572 bp->flags |= NO_FCOE_FLAG; 9572 bp->flags |= NO_FCOE_FLAG;
9573 } 9573 }
9574 9574
9575 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) 9575 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9576 { 9576 {
9577 /* 9577 /*
9578 * iSCSI may be dynamically disabled but reading 9578 * iSCSI may be dynamically disabled but reading
9579 * info here we will decrease memory usage by driver 9579 * info here we will decrease memory usage by driver
9580 * if the feature is disabled for good 9580 * if the feature is disabled for good
9581 */ 9581 */
9582 bnx2x_get_iscsi_info(bp); 9582 bnx2x_get_iscsi_info(bp);
9583 bnx2x_get_fcoe_info(bp); 9583 bnx2x_get_fcoe_info(bp);
9584 } 9584 }
9585 #endif 9585 #endif
9586 9586
9587 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) 9587 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9588 { 9588 {
9589 u32 val, val2; 9589 u32 val, val2;
9590 int func = BP_ABS_FUNC(bp); 9590 int func = BP_ABS_FUNC(bp);
9591 int port = BP_PORT(bp); 9591 int port = BP_PORT(bp);
9592 #ifdef BCM_CNIC 9592 #ifdef BCM_CNIC
9593 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 9593 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9594 u8 *fip_mac = bp->fip_mac; 9594 u8 *fip_mac = bp->fip_mac;
9595 #endif 9595 #endif
9596 9596
9597 /* Zero primary MAC configuration */ 9597 /* Zero primary MAC configuration */
9598 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9598 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9599 9599
9600 if (BP_NOMCP(bp)) { 9600 if (BP_NOMCP(bp)) {
9601 BNX2X_ERROR("warning: random MAC workaround active\n"); 9601 BNX2X_ERROR("warning: random MAC workaround active\n");
9602 random_ether_addr(bp->dev->dev_addr); 9602 random_ether_addr(bp->dev->dev_addr);
9603 } else if (IS_MF(bp)) { 9603 } else if (IS_MF(bp)) {
9604 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 9604 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9605 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 9605 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9606 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 9606 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9607 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 9607 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9608 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9608 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9609 9609
9610 #ifdef BCM_CNIC 9610 #ifdef BCM_CNIC
9611 /* 9611 /*
9612 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 9612 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9613 * FCoE MAC then the appropriate feature should be disabled. 9613 * FCoE MAC then the appropriate feature should be disabled.
9614 */ 9614 */
9615 if (IS_MF_SI(bp)) { 9615 if (IS_MF_SI(bp)) {
9616 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9616 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9617 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 9617 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9618 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9618 val2 = MF_CFG_RD(bp, func_ext_config[func].
9619 iscsi_mac_addr_upper); 9619 iscsi_mac_addr_upper);
9620 val = MF_CFG_RD(bp, func_ext_config[func]. 9620 val = MF_CFG_RD(bp, func_ext_config[func].
9621 iscsi_mac_addr_lower); 9621 iscsi_mac_addr_lower);
9622 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9622 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9623 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9623 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9624 iscsi_mac); 9624 iscsi_mac);
9625 } else 9625 } else
9626 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9626 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9627 9627
9628 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9628 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9629 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9629 val2 = MF_CFG_RD(bp, func_ext_config[func].
9630 fcoe_mac_addr_upper); 9630 fcoe_mac_addr_upper);
9631 val = MF_CFG_RD(bp, func_ext_config[func]. 9631 val = MF_CFG_RD(bp, func_ext_config[func].
9632 fcoe_mac_addr_lower); 9632 fcoe_mac_addr_lower);
9633 bnx2x_set_mac_buf(fip_mac, val, val2); 9633 bnx2x_set_mac_buf(fip_mac, val, val2);
9634 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", 9634 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
9635 fip_mac); 9635 fip_mac);
9636 9636
9637 } else 9637 } else
9638 bp->flags |= NO_FCOE_FLAG; 9638 bp->flags |= NO_FCOE_FLAG;
9639 } else { /* SD mode */ 9639 } else { /* SD mode */
9640 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) { 9640 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) {
9641 /* use primary mac as iscsi mac */ 9641 /* use primary mac as iscsi mac */
9642 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); 9642 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
9643 /* Zero primary MAC configuration */ 9643 /* Zero primary MAC configuration */
9644 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9644 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9645 9645
9646 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 9646 BNX2X_DEV_INFO("SD ISCSI MODE\n");
9647 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9647 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9648 iscsi_mac); 9648 iscsi_mac);
9649 } 9649 }
9650 } 9650 }
9651 #endif 9651 #endif
9652 } else { 9652 } else {
9653 /* in SF read MACs from port configuration */ 9653 /* in SF read MACs from port configuration */
9654 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 9654 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9655 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 9655 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9656 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9656 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9657 9657
9658 #ifdef BCM_CNIC 9658 #ifdef BCM_CNIC
9659 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9659 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9660 iscsi_mac_upper); 9660 iscsi_mac_upper);
9661 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9661 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9662 iscsi_mac_lower); 9662 iscsi_mac_lower);
9663 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9663 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9664 9664
9665 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9665 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9666 fcoe_fip_mac_upper); 9666 fcoe_fip_mac_upper);
9667 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9667 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9668 fcoe_fip_mac_lower); 9668 fcoe_fip_mac_lower);
9669 bnx2x_set_mac_buf(fip_mac, val, val2); 9669 bnx2x_set_mac_buf(fip_mac, val, val2);
9670 #endif 9670 #endif
9671 } 9671 }
9672 9672
9673 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 9673 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9674 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 9674 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9675 9675
9676 #ifdef BCM_CNIC 9676 #ifdef BCM_CNIC
9677 /* Set the FCoE MAC in MF_SD mode */ 9677 /* Set the FCoE MAC in MF_SD mode */
9678 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp)) 9678 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9679 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 9679 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
9680 9680
9681 /* Disable iSCSI if MAC configuration is 9681 /* Disable iSCSI if MAC configuration is
9682 * invalid. 9682 * invalid.
9683 */ 9683 */
9684 if (!is_valid_ether_addr(iscsi_mac)) { 9684 if (!is_valid_ether_addr(iscsi_mac)) {
9685 bp->flags |= NO_ISCSI_FLAG; 9685 bp->flags |= NO_ISCSI_FLAG;
9686 memset(iscsi_mac, 0, ETH_ALEN); 9686 memset(iscsi_mac, 0, ETH_ALEN);
9687 } 9687 }
9688 9688
9689 /* Disable FCoE if MAC configuration is 9689 /* Disable FCoE if MAC configuration is
9690 * invalid. 9690 * invalid.
9691 */ 9691 */
9692 if (!is_valid_ether_addr(fip_mac)) { 9692 if (!is_valid_ether_addr(fip_mac)) {
9693 bp->flags |= NO_FCOE_FLAG; 9693 bp->flags |= NO_FCOE_FLAG;
9694 memset(bp->fip_mac, 0, ETH_ALEN); 9694 memset(bp->fip_mac, 0, ETH_ALEN);
9695 } 9695 }
9696 #endif 9696 #endif
9697 9697
9698 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) 9698 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
9699 dev_err(&bp->pdev->dev, 9699 dev_err(&bp->pdev->dev,
9700 "bad Ethernet MAC address configuration: " 9700 "bad Ethernet MAC address configuration: "
9701 "%pM, change it manually before bringing up " 9701 "%pM, change it manually before bringing up "
9702 "the appropriate network interface\n", 9702 "the appropriate network interface\n",
9703 bp->dev->dev_addr); 9703 bp->dev->dev_addr);
9704 } 9704 }
9705 9705
9706 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 9706 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9707 { 9707 {
9708 int /*abs*/func = BP_ABS_FUNC(bp); 9708 int /*abs*/func = BP_ABS_FUNC(bp);
9709 int vn; 9709 int vn;
9710 u32 val = 0; 9710 u32 val = 0;
9711 int rc = 0; 9711 int rc = 0;
9712 9712
9713 bnx2x_get_common_hwinfo(bp); 9713 bnx2x_get_common_hwinfo(bp);
9714 9714
9715 /* 9715 /*
9716 * initialize IGU parameters 9716 * initialize IGU parameters
9717 */ 9717 */
9718 if (CHIP_IS_E1x(bp)) { 9718 if (CHIP_IS_E1x(bp)) {
9719 bp->common.int_block = INT_BLOCK_HC; 9719 bp->common.int_block = INT_BLOCK_HC;
9720 9720
9721 bp->igu_dsb_id = DEF_SB_IGU_ID; 9721 bp->igu_dsb_id = DEF_SB_IGU_ID;
9722 bp->igu_base_sb = 0; 9722 bp->igu_base_sb = 0;
9723 } else { 9723 } else {
9724 bp->common.int_block = INT_BLOCK_IGU; 9724 bp->common.int_block = INT_BLOCK_IGU;
9725 9725
9726 /* do not allow device reset during IGU info preocessing */ 9726 /* do not allow device reset during IGU info preocessing */
9727 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9727 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9728 9728
9729 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9729 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9730 9730
9731 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9731 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9732 int tout = 5000; 9732 int tout = 5000;
9733 9733
9734 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 9734 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9735 9735
9736 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 9736 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9737 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 9737 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9738 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 9738 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9739 9739
9740 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9740 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9741 tout--; 9741 tout--;
9742 usleep_range(1000, 1000); 9742 usleep_range(1000, 1000);
9743 } 9743 }
9744 9744
9745 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9745 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9746 dev_err(&bp->pdev->dev, 9746 dev_err(&bp->pdev->dev,
9747 "FORCING Normal Mode failed!!!\n"); 9747 "FORCING Normal Mode failed!!!\n");
9748 return -EPERM; 9748 return -EPERM;
9749 } 9749 }
9750 } 9750 }
9751 9751
9752 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9752 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9753 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 9753 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9754 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 9754 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9755 } else 9755 } else
9756 BNX2X_DEV_INFO("IGU Normal Mode\n"); 9756 BNX2X_DEV_INFO("IGU Normal Mode\n");
9757 9757
9758 bnx2x_get_igu_cam_info(bp); 9758 bnx2x_get_igu_cam_info(bp);
9759 9759
9760 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9760 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9761 } 9761 }
9762 9762
9763 /* 9763 /*
9764 * set base FW non-default (fast path) status block id, this value is 9764 * set base FW non-default (fast path) status block id, this value is
9765 * used to initialize the fw_sb_id saved on the fp/queue structure to 9765 * used to initialize the fw_sb_id saved on the fp/queue structure to
9766 * determine the id used by the FW. 9766 * determine the id used by the FW.
9767 */ 9767 */
9768 if (CHIP_IS_E1x(bp)) 9768 if (CHIP_IS_E1x(bp))
9769 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 9769 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9770 else /* 9770 else /*
9771 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 9771 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9772 * the same queue are indicated on the same IGU SB). So we prefer 9772 * the same queue are indicated on the same IGU SB). So we prefer
9773 * FW and IGU SBs to be the same value. 9773 * FW and IGU SBs to be the same value.
9774 */ 9774 */
9775 bp->base_fw_ndsb = bp->igu_base_sb; 9775 bp->base_fw_ndsb = bp->igu_base_sb;
9776 9776
9777 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 9777 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9778 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 9778 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9779 bp->igu_sb_cnt, bp->base_fw_ndsb); 9779 bp->igu_sb_cnt, bp->base_fw_ndsb);
9780 9780
9781 /* 9781 /*
9782 * Initialize MF configuration 9782 * Initialize MF configuration
9783 */ 9783 */
9784 9784
9785 bp->mf_ov = 0; 9785 bp->mf_ov = 0;
9786 bp->mf_mode = 0; 9786 bp->mf_mode = 0;
9787 vn = BP_VN(bp); 9787 vn = BP_VN(bp);
9788 9788
9789 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 9789 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
9790 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 9790 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9791 bp->common.shmem2_base, SHMEM2_RD(bp, size), 9791 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9792 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 9792 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9793 9793
9794 if (SHMEM2_HAS(bp, mf_cfg_addr)) 9794 if (SHMEM2_HAS(bp, mf_cfg_addr))
9795 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 9795 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9796 else 9796 else
9797 bp->common.mf_cfg_base = bp->common.shmem_base + 9797 bp->common.mf_cfg_base = bp->common.shmem_base +
9798 offsetof(struct shmem_region, func_mb) + 9798 offsetof(struct shmem_region, func_mb) +
9799 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 9799 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
9800 /* 9800 /*
9801 * get mf configuration: 9801 * get mf configuration:
9802 * 1. existence of MF configuration 9802 * 1. existence of MF configuration
9803 * 2. MAC address must be legal (check only upper bytes) 9803 * 2. MAC address must be legal (check only upper bytes)
9804 * for Switch-Independent mode; 9804 * for Switch-Independent mode;
9805 * OVLAN must be legal for Switch-Dependent mode 9805 * OVLAN must be legal for Switch-Dependent mode
9806 * 3. SF_MODE configures specific MF mode 9806 * 3. SF_MODE configures specific MF mode
9807 */ 9807 */
9808 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9808 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9809 /* get mf configuration */ 9809 /* get mf configuration */
9810 val = SHMEM_RD(bp, 9810 val = SHMEM_RD(bp,
9811 dev_info.shared_feature_config.config); 9811 dev_info.shared_feature_config.config);
9812 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 9812 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9813 9813
9814 switch (val) { 9814 switch (val) {
9815 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 9815 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9816 val = MF_CFG_RD(bp, func_mf_config[func]. 9816 val = MF_CFG_RD(bp, func_mf_config[func].
9817 mac_upper); 9817 mac_upper);
9818 /* check for legal mac (upper bytes)*/ 9818 /* check for legal mac (upper bytes)*/
9819 if (val != 0xffff) { 9819 if (val != 0xffff) {
9820 bp->mf_mode = MULTI_FUNCTION_SI; 9820 bp->mf_mode = MULTI_FUNCTION_SI;
9821 bp->mf_config[vn] = MF_CFG_RD(bp, 9821 bp->mf_config[vn] = MF_CFG_RD(bp,
9822 func_mf_config[func].config); 9822 func_mf_config[func].config);
9823 } else 9823 } else
9824 BNX2X_DEV_INFO("illegal MAC address " 9824 BNX2X_DEV_INFO("illegal MAC address "
9825 "for SI\n"); 9825 "for SI\n");
9826 break; 9826 break;
9827 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 9827 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9828 /* get OV configuration */ 9828 /* get OV configuration */
9829 val = MF_CFG_RD(bp, 9829 val = MF_CFG_RD(bp,
9830 func_mf_config[FUNC_0].e1hov_tag); 9830 func_mf_config[FUNC_0].e1hov_tag);
9831 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 9831 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9832 9832
9833 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9833 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9834 bp->mf_mode = MULTI_FUNCTION_SD; 9834 bp->mf_mode = MULTI_FUNCTION_SD;
9835 bp->mf_config[vn] = MF_CFG_RD(bp, 9835 bp->mf_config[vn] = MF_CFG_RD(bp,
9836 func_mf_config[func].config); 9836 func_mf_config[func].config);
9837 } else 9837 } else
9838 BNX2X_DEV_INFO("illegal OV for SD\n"); 9838 BNX2X_DEV_INFO("illegal OV for SD\n");
9839 break; 9839 break;
9840 default: 9840 default:
9841 /* Unknown configuration: reset mf_config */ 9841 /* Unknown configuration: reset mf_config */
9842 bp->mf_config[vn] = 0; 9842 bp->mf_config[vn] = 0;
9843 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); 9843 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
9844 } 9844 }
9845 } 9845 }
9846 9846
9847 BNX2X_DEV_INFO("%s function mode\n", 9847 BNX2X_DEV_INFO("%s function mode\n",
9848 IS_MF(bp) ? "multi" : "single"); 9848 IS_MF(bp) ? "multi" : "single");
9849 9849
9850 switch (bp->mf_mode) { 9850 switch (bp->mf_mode) {
9851 case MULTI_FUNCTION_SD: 9851 case MULTI_FUNCTION_SD:
9852 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 9852 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9853 FUNC_MF_CFG_E1HOV_TAG_MASK; 9853 FUNC_MF_CFG_E1HOV_TAG_MASK;
9854 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9854 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9855 bp->mf_ov = val; 9855 bp->mf_ov = val;
9856 bp->path_has_ovlan = true; 9856 bp->path_has_ovlan = true;
9857 9857
9858 BNX2X_DEV_INFO("MF OV for func %d is %d " 9858 BNX2X_DEV_INFO("MF OV for func %d is %d "
9859 "(0x%04x)\n", func, bp->mf_ov, 9859 "(0x%04x)\n", func, bp->mf_ov,
9860 bp->mf_ov); 9860 bp->mf_ov);
9861 } else { 9861 } else {
9862 dev_err(&bp->pdev->dev, 9862 dev_err(&bp->pdev->dev,
9863 "No valid MF OV for func %d, " 9863 "No valid MF OV for func %d, "
9864 "aborting\n", func); 9864 "aborting\n", func);
9865 return -EPERM; 9865 return -EPERM;
9866 } 9866 }
9867 break; 9867 break;
9868 case MULTI_FUNCTION_SI: 9868 case MULTI_FUNCTION_SI:
9869 BNX2X_DEV_INFO("func %d is in MF " 9869 BNX2X_DEV_INFO("func %d is in MF "
9870 "switch-independent mode\n", func); 9870 "switch-independent mode\n", func);
9871 break; 9871 break;
9872 default: 9872 default:
9873 if (vn) { 9873 if (vn) {
9874 dev_err(&bp->pdev->dev, 9874 dev_err(&bp->pdev->dev,
9875 "VN %d is in a single function mode, " 9875 "VN %d is in a single function mode, "
9876 "aborting\n", vn); 9876 "aborting\n", vn);
9877 return -EPERM; 9877 return -EPERM;
9878 } 9878 }
9879 break; 9879 break;
9880 } 9880 }
9881 9881
9882 /* check if other port on the path needs ovlan: 9882 /* check if other port on the path needs ovlan:
9883 * Since MF configuration is shared between ports 9883 * Since MF configuration is shared between ports
9884 * Possible mixed modes are only 9884 * Possible mixed modes are only
9885 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 9885 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9886 */ 9886 */
9887 if (CHIP_MODE_IS_4_PORT(bp) && 9887 if (CHIP_MODE_IS_4_PORT(bp) &&
9888 !bp->path_has_ovlan && 9888 !bp->path_has_ovlan &&
9889 !IS_MF(bp) && 9889 !IS_MF(bp) &&
9890 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9890 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9891 u8 other_port = !BP_PORT(bp); 9891 u8 other_port = !BP_PORT(bp);
9892 u8 other_func = BP_PATH(bp) + 2*other_port; 9892 u8 other_func = BP_PATH(bp) + 2*other_port;
9893 val = MF_CFG_RD(bp, 9893 val = MF_CFG_RD(bp,
9894 func_mf_config[other_func].e1hov_tag); 9894 func_mf_config[other_func].e1hov_tag);
9895 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 9895 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9896 bp->path_has_ovlan = true; 9896 bp->path_has_ovlan = true;
9897 } 9897 }
9898 } 9898 }
9899 9899
9900 /* adjust igu_sb_cnt to MF for E1x */ 9900 /* adjust igu_sb_cnt to MF for E1x */
9901 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 9901 if (CHIP_IS_E1x(bp) && IS_MF(bp))
9902 bp->igu_sb_cnt /= E1HVN_MAX; 9902 bp->igu_sb_cnt /= E1HVN_MAX;
9903 9903
9904 /* port info */ 9904 /* port info */
9905 bnx2x_get_port_hwinfo(bp); 9905 bnx2x_get_port_hwinfo(bp);
9906 9906
9907 /* Get MAC addresses */ 9907 /* Get MAC addresses */
9908 bnx2x_get_mac_hwinfo(bp); 9908 bnx2x_get_mac_hwinfo(bp);
9909 9909
9910 #ifdef BCM_CNIC 9910 #ifdef BCM_CNIC
9911 bnx2x_get_cnic_info(bp); 9911 bnx2x_get_cnic_info(bp);
9912 #endif 9912 #endif
9913 9913
9914 /* Get current FW pulse sequence */ 9914 /* Get current FW pulse sequence */
9915 if (!BP_NOMCP(bp)) { 9915 if (!BP_NOMCP(bp)) {
9916 int mb_idx = BP_FW_MB_IDX(bp); 9916 int mb_idx = BP_FW_MB_IDX(bp);
9917 9917
9918 bp->fw_drv_pulse_wr_seq = 9918 bp->fw_drv_pulse_wr_seq =
9919 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) & 9919 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9920 DRV_PULSE_SEQ_MASK); 9920 DRV_PULSE_SEQ_MASK);
9921 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); 9921 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9922 } 9922 }
9923 9923
9924 return rc; 9924 return rc;
9925 } 9925 }
9926 9926
9927 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) 9927 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9928 { 9928 {
9929 int cnt, i, block_end, rodi; 9929 int cnt, i, block_end, rodi;
9930 char vpd_data[BNX2X_VPD_LEN+1]; 9930 char vpd_data[BNX2X_VPD_LEN+1];
9931 char str_id_reg[VENDOR_ID_LEN+1]; 9931 char str_id_reg[VENDOR_ID_LEN+1];
9932 char str_id_cap[VENDOR_ID_LEN+1]; 9932 char str_id_cap[VENDOR_ID_LEN+1];
9933 u8 len; 9933 u8 len;
9934 9934
9935 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data); 9935 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9936 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 9936 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9937 9937
9938 if (cnt < BNX2X_VPD_LEN) 9938 if (cnt < BNX2X_VPD_LEN)
9939 goto out_not_found; 9939 goto out_not_found;
9940 9940
9941 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN, 9941 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9942 PCI_VPD_LRDT_RO_DATA); 9942 PCI_VPD_LRDT_RO_DATA);
9943 if (i < 0) 9943 if (i < 0)
9944 goto out_not_found; 9944 goto out_not_found;
9945 9945
9946 9946
9947 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 9947 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9948 pci_vpd_lrdt_size(&vpd_data[i]); 9948 pci_vpd_lrdt_size(&vpd_data[i]);
9949 9949
9950 i += PCI_VPD_LRDT_TAG_SIZE; 9950 i += PCI_VPD_LRDT_TAG_SIZE;
9951 9951
9952 if (block_end > BNX2X_VPD_LEN) 9952 if (block_end > BNX2X_VPD_LEN)
9953 goto out_not_found; 9953 goto out_not_found;
9954 9954
9955 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 9955 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9956 PCI_VPD_RO_KEYWORD_MFR_ID); 9956 PCI_VPD_RO_KEYWORD_MFR_ID);
9957 if (rodi < 0) 9957 if (rodi < 0)
9958 goto out_not_found; 9958 goto out_not_found;
9959 9959
9960 len = pci_vpd_info_field_size(&vpd_data[rodi]); 9960 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9961 9961
9962 if (len != VENDOR_ID_LEN) 9962 if (len != VENDOR_ID_LEN)
9963 goto out_not_found; 9963 goto out_not_found;
9964 9964
9965 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 9965 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9966 9966
9967 /* vendor specific info */ 9967 /* vendor specific info */
9968 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 9968 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9969 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 9969 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9970 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 9970 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9971 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 9971 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9972 9972
9973 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 9973 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9974 PCI_VPD_RO_KEYWORD_VENDOR0); 9974 PCI_VPD_RO_KEYWORD_VENDOR0);
9975 if (rodi >= 0) { 9975 if (rodi >= 0) {
9976 len = pci_vpd_info_field_size(&vpd_data[rodi]); 9976 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9977 9977
9978 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 9978 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9979 9979
9980 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 9980 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9981 memcpy(bp->fw_ver, &vpd_data[rodi], len); 9981 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9982 bp->fw_ver[len] = ' '; 9982 bp->fw_ver[len] = ' ';
9983 } 9983 }
9984 } 9984 }
9985 return; 9985 return;
9986 } 9986 }
9987 out_not_found: 9987 out_not_found:
9988 return; 9988 return;
9989 } 9989 }
9990 9990
9991 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) 9991 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9992 { 9992 {
9993 u32 flags = 0; 9993 u32 flags = 0;
9994 9994
9995 if (CHIP_REV_IS_FPGA(bp)) 9995 if (CHIP_REV_IS_FPGA(bp))
9996 SET_FLAGS(flags, MODE_FPGA); 9996 SET_FLAGS(flags, MODE_FPGA);
9997 else if (CHIP_REV_IS_EMUL(bp)) 9997 else if (CHIP_REV_IS_EMUL(bp))
9998 SET_FLAGS(flags, MODE_EMUL); 9998 SET_FLAGS(flags, MODE_EMUL);
9999 else 9999 else
10000 SET_FLAGS(flags, MODE_ASIC); 10000 SET_FLAGS(flags, MODE_ASIC);
10001 10001
10002 if (CHIP_MODE_IS_4_PORT(bp)) 10002 if (CHIP_MODE_IS_4_PORT(bp))
10003 SET_FLAGS(flags, MODE_PORT4); 10003 SET_FLAGS(flags, MODE_PORT4);
10004 else 10004 else
10005 SET_FLAGS(flags, MODE_PORT2); 10005 SET_FLAGS(flags, MODE_PORT2);
10006 10006
10007 if (CHIP_IS_E2(bp)) 10007 if (CHIP_IS_E2(bp))
10008 SET_FLAGS(flags, MODE_E2); 10008 SET_FLAGS(flags, MODE_E2);
10009 else if (CHIP_IS_E3(bp)) { 10009 else if (CHIP_IS_E3(bp)) {
10010 SET_FLAGS(flags, MODE_E3); 10010 SET_FLAGS(flags, MODE_E3);
10011 if (CHIP_REV(bp) == CHIP_REV_Ax) 10011 if (CHIP_REV(bp) == CHIP_REV_Ax)
10012 SET_FLAGS(flags, MODE_E3_A0); 10012 SET_FLAGS(flags, MODE_E3_A0);
10013 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 10013 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10014 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 10014 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
10015 } 10015 }
10016 10016
10017 if (IS_MF(bp)) { 10017 if (IS_MF(bp)) {
10018 SET_FLAGS(flags, MODE_MF); 10018 SET_FLAGS(flags, MODE_MF);
10019 switch (bp->mf_mode) { 10019 switch (bp->mf_mode) {
10020 case MULTI_FUNCTION_SD: 10020 case MULTI_FUNCTION_SD:
10021 SET_FLAGS(flags, MODE_MF_SD); 10021 SET_FLAGS(flags, MODE_MF_SD);
10022 break; 10022 break;
10023 case MULTI_FUNCTION_SI: 10023 case MULTI_FUNCTION_SI:
10024 SET_FLAGS(flags, MODE_MF_SI); 10024 SET_FLAGS(flags, MODE_MF_SI);
10025 break; 10025 break;
10026 } 10026 }
10027 } else 10027 } else
10028 SET_FLAGS(flags, MODE_SF); 10028 SET_FLAGS(flags, MODE_SF);
10029 10029
10030 #if defined(__LITTLE_ENDIAN) 10030 #if defined(__LITTLE_ENDIAN)
10031 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 10031 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
10032 #else /*(__BIG_ENDIAN)*/ 10032 #else /*(__BIG_ENDIAN)*/
10033 SET_FLAGS(flags, MODE_BIG_ENDIAN); 10033 SET_FLAGS(flags, MODE_BIG_ENDIAN);
10034 #endif 10034 #endif
10035 INIT_MODE_FLAGS(bp) = flags; 10035 INIT_MODE_FLAGS(bp) = flags;
10036 } 10036 }
10037 10037
10038 static int __devinit bnx2x_init_bp(struct bnx2x *bp) 10038 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10039 { 10039 {
10040 int func; 10040 int func;
10041 int timer_interval; 10041 int timer_interval;
10042 int rc; 10042 int rc;
10043 10043
10044 mutex_init(&bp->port.phy_mutex); 10044 mutex_init(&bp->port.phy_mutex);
10045 mutex_init(&bp->fw_mb_mutex); 10045 mutex_init(&bp->fw_mb_mutex);
10046 spin_lock_init(&bp->stats_lock); 10046 spin_lock_init(&bp->stats_lock);
10047 #ifdef BCM_CNIC 10047 #ifdef BCM_CNIC
10048 mutex_init(&bp->cnic_mutex); 10048 mutex_init(&bp->cnic_mutex);
10049 #endif 10049 #endif
10050 10050
10051 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 10051 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
10052 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 10052 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
10053 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 10053 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
10054 rc = bnx2x_get_hwinfo(bp); 10054 rc = bnx2x_get_hwinfo(bp);
10055 if (rc) 10055 if (rc)
10056 return rc; 10056 return rc;
10057 10057
10058 bnx2x_set_modes_bitmap(bp); 10058 bnx2x_set_modes_bitmap(bp);
10059 10059
10060 rc = bnx2x_alloc_mem_bp(bp); 10060 rc = bnx2x_alloc_mem_bp(bp);
10061 if (rc) 10061 if (rc)
10062 return rc; 10062 return rc;
10063 10063
10064 bnx2x_read_fwinfo(bp); 10064 bnx2x_read_fwinfo(bp);
10065 10065
10066 func = BP_FUNC(bp); 10066 func = BP_FUNC(bp);
10067 10067
10068 /* need to reset chip if undi was active */ 10068 /* need to reset chip if undi was active */
10069 if (!BP_NOMCP(bp)) 10069 if (!BP_NOMCP(bp))
10070 bnx2x_undi_unload(bp); 10070 bnx2x_undi_unload(bp);
10071 10071
10072 /* init fw_seq after undi_unload! */ 10072 /* init fw_seq after undi_unload! */
10073 if (!BP_NOMCP(bp)) { 10073 if (!BP_NOMCP(bp)) {
10074 bp->fw_seq = 10074 bp->fw_seq =
10075 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 10075 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10076 DRV_MSG_SEQ_NUMBER_MASK); 10076 DRV_MSG_SEQ_NUMBER_MASK);
10077 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 10077 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10078 } 10078 }
10079 10079
10080 if (CHIP_REV_IS_FPGA(bp)) 10080 if (CHIP_REV_IS_FPGA(bp))
10081 dev_err(&bp->pdev->dev, "FPGA detected\n"); 10081 dev_err(&bp->pdev->dev, "FPGA detected\n");
10082 10082
10083 if (BP_NOMCP(bp) && (func == 0)) 10083 if (BP_NOMCP(bp) && (func == 0))
10084 dev_err(&bp->pdev->dev, "MCP disabled, " 10084 dev_err(&bp->pdev->dev, "MCP disabled, "
10085 "must load devices in order!\n"); 10085 "must load devices in order!\n");
10086 10086
10087 bp->multi_mode = multi_mode; 10087 bp->multi_mode = multi_mode;
10088 10088
10089 bp->disable_tpa = disable_tpa; 10089 bp->disable_tpa = disable_tpa;
10090 10090
10091 #ifdef BCM_CNIC 10091 #ifdef BCM_CNIC
10092 bp->disable_tpa |= IS_MF_ISCSI_SD(bp); 10092 bp->disable_tpa |= IS_MF_ISCSI_SD(bp);
10093 #endif 10093 #endif
10094 10094
10095 /* Set TPA flags */ 10095 /* Set TPA flags */
10096 if (bp->disable_tpa) { 10096 if (bp->disable_tpa) {
10097 bp->flags &= ~TPA_ENABLE_FLAG; 10097 bp->flags &= ~TPA_ENABLE_FLAG;
10098 bp->dev->features &= ~NETIF_F_LRO; 10098 bp->dev->features &= ~NETIF_F_LRO;
10099 } else { 10099 } else {
10100 bp->flags |= TPA_ENABLE_FLAG; 10100 bp->flags |= TPA_ENABLE_FLAG;
10101 bp->dev->features |= NETIF_F_LRO; 10101 bp->dev->features |= NETIF_F_LRO;
10102 } 10102 }
10103 10103
10104 if (CHIP_IS_E1(bp)) 10104 if (CHIP_IS_E1(bp))
10105 bp->dropless_fc = 0; 10105 bp->dropless_fc = 0;
10106 else 10106 else
10107 bp->dropless_fc = dropless_fc; 10107 bp->dropless_fc = dropless_fc;
10108 10108
10109 bp->mrrs = mrrs; 10109 bp->mrrs = mrrs;
10110 10110
10111 bp->tx_ring_size = MAX_TX_AVAIL; 10111 bp->tx_ring_size = MAX_TX_AVAIL;
10112 10112
10113 /* make sure that the numbers are in the right granularity */ 10113 /* make sure that the numbers are in the right granularity */
10114 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 10114 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
10115 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 10115 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
10116 10116
10117 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); 10117 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
10118 bp->current_interval = (poll ? poll : timer_interval); 10118 bp->current_interval = (poll ? poll : timer_interval);
10119 10119
10120 init_timer(&bp->timer); 10120 init_timer(&bp->timer);
10121 bp->timer.expires = jiffies + bp->current_interval; 10121 bp->timer.expires = jiffies + bp->current_interval;
10122 bp->timer.data = (unsigned long) bp; 10122 bp->timer.data = (unsigned long) bp;
10123 bp->timer.function = bnx2x_timer; 10123 bp->timer.function = bnx2x_timer;
10124 10124
10125 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 10125 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
10126 bnx2x_dcbx_init_params(bp); 10126 bnx2x_dcbx_init_params(bp);
10127 10127
10128 #ifdef BCM_CNIC 10128 #ifdef BCM_CNIC
10129 if (CHIP_IS_E1x(bp)) 10129 if (CHIP_IS_E1x(bp))
10130 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 10130 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
10131 else 10131 else
10132 bp->cnic_base_cl_id = FP_SB_MAX_E2; 10132 bp->cnic_base_cl_id = FP_SB_MAX_E2;
10133 #endif 10133 #endif
10134 10134
10135 /* multiple tx priority */ 10135 /* multiple tx priority */
10136 if (CHIP_IS_E1x(bp)) 10136 if (CHIP_IS_E1x(bp))
10137 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 10137 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
10138 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 10138 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
10139 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 10139 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
10140 if (CHIP_IS_E3B0(bp)) 10140 if (CHIP_IS_E3B0(bp))
10141 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 10141 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
10142 10142
10143 return rc; 10143 return rc;
10144 } 10144 }
10145 10145
10146 10146
10147 /**************************************************************************** 10147 /****************************************************************************
10148 * General service functions 10148 * General service functions
10149 ****************************************************************************/ 10149 ****************************************************************************/
10150 10150
10151 /* 10151 /*
10152 * net_device service functions 10152 * net_device service functions
10153 */ 10153 */
10154 10154
10155 /* called with rtnl_lock */ 10155 /* called with rtnl_lock */
10156 static int bnx2x_open(struct net_device *dev) 10156 static int bnx2x_open(struct net_device *dev)
10157 { 10157 {
10158 struct bnx2x *bp = netdev_priv(dev); 10158 struct bnx2x *bp = netdev_priv(dev);
10159 bool global = false; 10159 bool global = false;
10160 int other_engine = BP_PATH(bp) ? 0 : 1; 10160 int other_engine = BP_PATH(bp) ? 0 : 1;
10161 u32 other_load_counter, load_counter; 10161 u32 other_load_counter, load_counter;
10162 10162
10163 netif_carrier_off(dev); 10163 netif_carrier_off(dev);
10164 10164
10165 bnx2x_set_power_state(bp, PCI_D0); 10165 bnx2x_set_power_state(bp, PCI_D0);
10166 10166
10167 other_load_counter = bnx2x_get_load_cnt(bp, other_engine); 10167 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
10168 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp)); 10168 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
10169 10169
10170 /* 10170 /*
10171 * If parity had happen during the unload, then attentions 10171 * If parity had happen during the unload, then attentions
10172 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 10172 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10173 * want the first function loaded on the current engine to 10173 * want the first function loaded on the current engine to
10174 * complete the recovery. 10174 * complete the recovery.
10175 */ 10175 */
10176 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 10176 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
10177 bnx2x_chk_parity_attn(bp, &global, true)) 10177 bnx2x_chk_parity_attn(bp, &global, true))
10178 do { 10178 do {
10179 /* 10179 /*
10180 * If there are attentions and they are in a global 10180 * If there are attentions and they are in a global
10181 * blocks, set the GLOBAL_RESET bit regardless whether 10181 * blocks, set the GLOBAL_RESET bit regardless whether
10182 * it will be this function that will complete the 10182 * it will be this function that will complete the
10183 * recovery or not. 10183 * recovery or not.
10184 */ 10184 */
10185 if (global) 10185 if (global)
10186 bnx2x_set_reset_global(bp); 10186 bnx2x_set_reset_global(bp);
10187 10187
10188 /* 10188 /*
10189 * Only the first function on the current engine should 10189 * Only the first function on the current engine should
10190 * try to recover in open. In case of attentions in 10190 * try to recover in open. In case of attentions in
10191 * global blocks only the first in the chip should try 10191 * global blocks only the first in the chip should try
10192 * to recover. 10192 * to recover.
10193 */ 10193 */
10194 if ((!load_counter && 10194 if ((!load_counter &&
10195 (!global || !other_load_counter)) && 10195 (!global || !other_load_counter)) &&
10196 bnx2x_trylock_leader_lock(bp) && 10196 bnx2x_trylock_leader_lock(bp) &&
10197 !bnx2x_leader_reset(bp)) { 10197 !bnx2x_leader_reset(bp)) {
10198 netdev_info(bp->dev, "Recovered in open\n"); 10198 netdev_info(bp->dev, "Recovered in open\n");
10199 break; 10199 break;
10200 } 10200 }
10201 10201
10202 /* recovery has failed... */ 10202 /* recovery has failed... */
10203 bnx2x_set_power_state(bp, PCI_D3hot); 10203 bnx2x_set_power_state(bp, PCI_D3hot);
10204 bp->recovery_state = BNX2X_RECOVERY_FAILED; 10204 bp->recovery_state = BNX2X_RECOVERY_FAILED;
10205 10205
10206 netdev_err(bp->dev, "Recovery flow hasn't been properly" 10206 netdev_err(bp->dev, "Recovery flow hasn't been properly"
10207 " completed yet. Try again later. If u still see this" 10207 " completed yet. Try again later. If u still see this"
10208 " message after a few retries then power cycle is" 10208 " message after a few retries then power cycle is"
10209 " required.\n"); 10209 " required.\n");
10210 10210
10211 return -EAGAIN; 10211 return -EAGAIN;
10212 } while (0); 10212 } while (0);
10213 10213
10214 bp->recovery_state = BNX2X_RECOVERY_DONE; 10214 bp->recovery_state = BNX2X_RECOVERY_DONE;
10215 return bnx2x_nic_load(bp, LOAD_OPEN); 10215 return bnx2x_nic_load(bp, LOAD_OPEN);
10216 } 10216 }
10217 10217
10218 /* called with rtnl_lock */ 10218 /* called with rtnl_lock */
10219 int bnx2x_close(struct net_device *dev) 10219 int bnx2x_close(struct net_device *dev)
10220 { 10220 {
10221 struct bnx2x *bp = netdev_priv(dev); 10221 struct bnx2x *bp = netdev_priv(dev);
10222 10222
10223 /* Unload the driver, release IRQs */ 10223 /* Unload the driver, release IRQs */
10224 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 10224 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
10225 10225
10226 /* Power off */ 10226 /* Power off */
10227 bnx2x_set_power_state(bp, PCI_D3hot); 10227 bnx2x_set_power_state(bp, PCI_D3hot);
10228 10228
10229 return 0; 10229 return 0;
10230 } 10230 }
10231 10231
10232 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 10232 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
10233 struct bnx2x_mcast_ramrod_params *p) 10233 struct bnx2x_mcast_ramrod_params *p)
10234 { 10234 {
10235 int mc_count = netdev_mc_count(bp->dev); 10235 int mc_count = netdev_mc_count(bp->dev);
10236 struct bnx2x_mcast_list_elem *mc_mac = 10236 struct bnx2x_mcast_list_elem *mc_mac =
10237 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 10237 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
10238 struct netdev_hw_addr *ha; 10238 struct netdev_hw_addr *ha;
10239 10239
10240 if (!mc_mac) 10240 if (!mc_mac)
10241 return -ENOMEM; 10241 return -ENOMEM;
10242 10242
10243 INIT_LIST_HEAD(&p->mcast_list); 10243 INIT_LIST_HEAD(&p->mcast_list);
10244 10244
10245 netdev_for_each_mc_addr(ha, bp->dev) { 10245 netdev_for_each_mc_addr(ha, bp->dev) {
10246 mc_mac->mac = bnx2x_mc_addr(ha); 10246 mc_mac->mac = bnx2x_mc_addr(ha);
10247 list_add_tail(&mc_mac->link, &p->mcast_list); 10247 list_add_tail(&mc_mac->link, &p->mcast_list);
10248 mc_mac++; 10248 mc_mac++;
10249 } 10249 }
10250 10250
10251 p->mcast_list_len = mc_count; 10251 p->mcast_list_len = mc_count;
10252 10252
10253 return 0; 10253 return 0;
10254 } 10254 }
10255 10255
10256 static inline void bnx2x_free_mcast_macs_list( 10256 static inline void bnx2x_free_mcast_macs_list(
10257 struct bnx2x_mcast_ramrod_params *p) 10257 struct bnx2x_mcast_ramrod_params *p)
10258 { 10258 {
10259 struct bnx2x_mcast_list_elem *mc_mac = 10259 struct bnx2x_mcast_list_elem *mc_mac =
10260 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 10260 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
10261 link); 10261 link);
10262 10262
10263 WARN_ON(!mc_mac); 10263 WARN_ON(!mc_mac);
10264 kfree(mc_mac); 10264 kfree(mc_mac);
10265 } 10265 }
10266 10266
10267 /** 10267 /**
10268 * bnx2x_set_uc_list - configure a new unicast MACs list. 10268 * bnx2x_set_uc_list - configure a new unicast MACs list.
10269 * 10269 *
10270 * @bp: driver handle 10270 * @bp: driver handle
10271 * 10271 *
10272 * We will use zero (0) as a MAC type for these MACs. 10272 * We will use zero (0) as a MAC type for these MACs.
10273 */ 10273 */
10274 static inline int bnx2x_set_uc_list(struct bnx2x *bp) 10274 static inline int bnx2x_set_uc_list(struct bnx2x *bp)
10275 { 10275 {
10276 int rc; 10276 int rc;
10277 struct net_device *dev = bp->dev; 10277 struct net_device *dev = bp->dev;
10278 struct netdev_hw_addr *ha; 10278 struct netdev_hw_addr *ha;
10279 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; 10279 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
10280 unsigned long ramrod_flags = 0; 10280 unsigned long ramrod_flags = 0;
10281 10281
10282 /* First schedule a cleanup up of old configuration */ 10282 /* First schedule a cleanup up of old configuration */
10283 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 10283 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
10284 if (rc < 0) { 10284 if (rc < 0) {
10285 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 10285 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
10286 return rc; 10286 return rc;
10287 } 10287 }
10288 10288
10289 netdev_for_each_uc_addr(ha, dev) { 10289 netdev_for_each_uc_addr(ha, dev) {
10290 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 10290 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
10291 BNX2X_UC_LIST_MAC, &ramrod_flags); 10291 BNX2X_UC_LIST_MAC, &ramrod_flags);
10292 if (rc < 0) { 10292 if (rc < 0) {
10293 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 10293 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10294 rc); 10294 rc);
10295 return rc; 10295 return rc;
10296 } 10296 }
10297 } 10297 }
10298 10298
10299 /* Execute the pending commands */ 10299 /* Execute the pending commands */
10300 __set_bit(RAMROD_CONT, &ramrod_flags); 10300 __set_bit(RAMROD_CONT, &ramrod_flags);
10301 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 10301 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
10302 BNX2X_UC_LIST_MAC, &ramrod_flags); 10302 BNX2X_UC_LIST_MAC, &ramrod_flags);
10303 } 10303 }
10304 10304
10305 static inline int bnx2x_set_mc_list(struct bnx2x *bp) 10305 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
10306 { 10306 {
10307 struct net_device *dev = bp->dev; 10307 struct net_device *dev = bp->dev;
10308 struct bnx2x_mcast_ramrod_params rparam = {0}; 10308 struct bnx2x_mcast_ramrod_params rparam = {0};
10309 int rc = 0; 10309 int rc = 0;
10310 10310
10311 rparam.mcast_obj = &bp->mcast_obj; 10311 rparam.mcast_obj = &bp->mcast_obj;
10312 10312
10313 /* first, clear all configured multicast MACs */ 10313 /* first, clear all configured multicast MACs */
10314 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 10314 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10315 if (rc < 0) { 10315 if (rc < 0) {
10316 BNX2X_ERR("Failed to clear multicast " 10316 BNX2X_ERR("Failed to clear multicast "
10317 "configuration: %d\n", rc); 10317 "configuration: %d\n", rc);
10318 return rc; 10318 return rc;
10319 } 10319 }
10320 10320
10321 /* then, configure a new MACs list */ 10321 /* then, configure a new MACs list */
10322 if (netdev_mc_count(dev)) { 10322 if (netdev_mc_count(dev)) {
10323 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10323 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10324 if (rc) { 10324 if (rc) {
10325 BNX2X_ERR("Failed to create multicast MACs " 10325 BNX2X_ERR("Failed to create multicast MACs "
10326 "list: %d\n", rc); 10326 "list: %d\n", rc);
10327 return rc; 10327 return rc;
10328 } 10328 }
10329 10329
10330 /* Now add the new MACs */ 10330 /* Now add the new MACs */
10331 rc = bnx2x_config_mcast(bp, &rparam, 10331 rc = bnx2x_config_mcast(bp, &rparam,
10332 BNX2X_MCAST_CMD_ADD); 10332 BNX2X_MCAST_CMD_ADD);
10333 if (rc < 0) 10333 if (rc < 0)
10334 BNX2X_ERR("Failed to set a new multicast " 10334 BNX2X_ERR("Failed to set a new multicast "
10335 "configuration: %d\n", rc); 10335 "configuration: %d\n", rc);
10336 10336
10337 bnx2x_free_mcast_macs_list(&rparam); 10337 bnx2x_free_mcast_macs_list(&rparam);
10338 } 10338 }
10339 10339
10340 return rc; 10340 return rc;
10341 } 10341 }
10342 10342
10343 10343
10344 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 10344 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
10345 void bnx2x_set_rx_mode(struct net_device *dev) 10345 void bnx2x_set_rx_mode(struct net_device *dev)
10346 { 10346 {
10347 struct bnx2x *bp = netdev_priv(dev); 10347 struct bnx2x *bp = netdev_priv(dev);
10348 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 10348 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
10349 10349
10350 if (bp->state != BNX2X_STATE_OPEN) { 10350 if (bp->state != BNX2X_STATE_OPEN) {
10351 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 10351 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10352 return; 10352 return;
10353 } 10353 }
10354 10354
10355 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 10355 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
10356 10356
10357 if (dev->flags & IFF_PROMISC) 10357 if (dev->flags & IFF_PROMISC)
10358 rx_mode = BNX2X_RX_MODE_PROMISC; 10358 rx_mode = BNX2X_RX_MODE_PROMISC;
10359 else if ((dev->flags & IFF_ALLMULTI) || 10359 else if ((dev->flags & IFF_ALLMULTI) ||
10360 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 10360 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10361 CHIP_IS_E1(bp))) 10361 CHIP_IS_E1(bp)))
10362 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10362 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10363 else { 10363 else {
10364 /* some multicasts */ 10364 /* some multicasts */
10365 if (bnx2x_set_mc_list(bp) < 0) 10365 if (bnx2x_set_mc_list(bp) < 0)
10366 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10366 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10367 10367
10368 if (bnx2x_set_uc_list(bp) < 0) 10368 if (bnx2x_set_uc_list(bp) < 0)
10369 rx_mode = BNX2X_RX_MODE_PROMISC; 10369 rx_mode = BNX2X_RX_MODE_PROMISC;
10370 } 10370 }
10371 10371
10372 bp->rx_mode = rx_mode; 10372 bp->rx_mode = rx_mode;
10373 #ifdef BCM_CNIC 10373 #ifdef BCM_CNIC
10374 /* handle ISCSI SD mode */ 10374 /* handle ISCSI SD mode */
10375 if (IS_MF_ISCSI_SD(bp)) 10375 if (IS_MF_ISCSI_SD(bp))
10376 bp->rx_mode = BNX2X_RX_MODE_NONE; 10376 bp->rx_mode = BNX2X_RX_MODE_NONE;
10377 #endif 10377 #endif
10378 10378
10379 /* Schedule the rx_mode command */ 10379 /* Schedule the rx_mode command */
10380 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 10380 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10381 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 10381 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10382 return; 10382 return;
10383 } 10383 }
10384 10384
10385 bnx2x_set_storm_rx_mode(bp); 10385 bnx2x_set_storm_rx_mode(bp);
10386 } 10386 }
10387 10387
10388 /* called with rtnl_lock */ 10388 /* called with rtnl_lock */
10389 static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 10389 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10390 int devad, u16 addr) 10390 int devad, u16 addr)
10391 { 10391 {
10392 struct bnx2x *bp = netdev_priv(netdev); 10392 struct bnx2x *bp = netdev_priv(netdev);
10393 u16 value; 10393 u16 value;
10394 int rc; 10394 int rc;
10395 10395
10396 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 10396 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10397 prtad, devad, addr); 10397 prtad, devad, addr);
10398 10398
10399 /* The HW expects different devad if CL22 is used */ 10399 /* The HW expects different devad if CL22 is used */
10400 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10400 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10401 10401
10402 bnx2x_acquire_phy_lock(bp); 10402 bnx2x_acquire_phy_lock(bp);
10403 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 10403 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
10404 bnx2x_release_phy_lock(bp); 10404 bnx2x_release_phy_lock(bp);
10405 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 10405 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
10406 10406
10407 if (!rc) 10407 if (!rc)
10408 rc = value; 10408 rc = value;
10409 return rc; 10409 return rc;
10410 } 10410 }
10411 10411
10412 /* called with rtnl_lock */ 10412 /* called with rtnl_lock */
10413 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 10413 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10414 u16 addr, u16 value) 10414 u16 addr, u16 value)
10415 { 10415 {
10416 struct bnx2x *bp = netdev_priv(netdev); 10416 struct bnx2x *bp = netdev_priv(netdev);
10417 int rc; 10417 int rc;
10418 10418
10419 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," 10419 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10420 " value 0x%x\n", prtad, devad, addr, value); 10420 " value 0x%x\n", prtad, devad, addr, value);
10421 10421
10422 /* The HW expects different devad if CL22 is used */ 10422 /* The HW expects different devad if CL22 is used */
10423 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10423 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10424 10424
10425 bnx2x_acquire_phy_lock(bp); 10425 bnx2x_acquire_phy_lock(bp);
10426 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 10426 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
10427 bnx2x_release_phy_lock(bp); 10427 bnx2x_release_phy_lock(bp);
10428 return rc; 10428 return rc;
10429 } 10429 }
10430 10430
10431 /* called with rtnl_lock */ 10431 /* called with rtnl_lock */
10432 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10432 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10433 { 10433 {
10434 struct bnx2x *bp = netdev_priv(dev); 10434 struct bnx2x *bp = netdev_priv(dev);
10435 struct mii_ioctl_data *mdio = if_mii(ifr); 10435 struct mii_ioctl_data *mdio = if_mii(ifr);
10436 10436
10437 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 10437 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10438 mdio->phy_id, mdio->reg_num, mdio->val_in); 10438 mdio->phy_id, mdio->reg_num, mdio->val_in);
10439 10439
10440 if (!netif_running(dev)) 10440 if (!netif_running(dev))
10441 return -EAGAIN; 10441 return -EAGAIN;
10442 10442
10443 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 10443 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
10444 } 10444 }
10445 10445
10446 #ifdef CONFIG_NET_POLL_CONTROLLER 10446 #ifdef CONFIG_NET_POLL_CONTROLLER
10447 static void poll_bnx2x(struct net_device *dev) 10447 static void poll_bnx2x(struct net_device *dev)
10448 { 10448 {
10449 struct bnx2x *bp = netdev_priv(dev); 10449 struct bnx2x *bp = netdev_priv(dev);
10450 10450
10451 disable_irq(bp->pdev->irq); 10451 disable_irq(bp->pdev->irq);
10452 bnx2x_interrupt(bp->pdev->irq, dev); 10452 bnx2x_interrupt(bp->pdev->irq, dev);
10453 enable_irq(bp->pdev->irq); 10453 enable_irq(bp->pdev->irq);
10454 } 10454 }
10455 #endif 10455 #endif
10456 10456
10457 static int bnx2x_validate_addr(struct net_device *dev) 10457 static int bnx2x_validate_addr(struct net_device *dev)
10458 { 10458 {
10459 struct bnx2x *bp = netdev_priv(dev); 10459 struct bnx2x *bp = netdev_priv(dev);
10460 10460
10461 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) 10461 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr))
10462 return -EADDRNOTAVAIL; 10462 return -EADDRNOTAVAIL;
10463 return 0; 10463 return 0;
10464 } 10464 }
10465 10465
10466 static const struct net_device_ops bnx2x_netdev_ops = { 10466 static const struct net_device_ops bnx2x_netdev_ops = {
10467 .ndo_open = bnx2x_open, 10467 .ndo_open = bnx2x_open,
10468 .ndo_stop = bnx2x_close, 10468 .ndo_stop = bnx2x_close,
10469 .ndo_start_xmit = bnx2x_start_xmit, 10469 .ndo_start_xmit = bnx2x_start_xmit,
10470 .ndo_select_queue = bnx2x_select_queue, 10470 .ndo_select_queue = bnx2x_select_queue,
10471 .ndo_set_rx_mode = bnx2x_set_rx_mode, 10471 .ndo_set_rx_mode = bnx2x_set_rx_mode,
10472 .ndo_set_mac_address = bnx2x_change_mac_addr, 10472 .ndo_set_mac_address = bnx2x_change_mac_addr,
10473 .ndo_validate_addr = bnx2x_validate_addr, 10473 .ndo_validate_addr = bnx2x_validate_addr,
10474 .ndo_do_ioctl = bnx2x_ioctl, 10474 .ndo_do_ioctl = bnx2x_ioctl,
10475 .ndo_change_mtu = bnx2x_change_mtu, 10475 .ndo_change_mtu = bnx2x_change_mtu,
10476 .ndo_fix_features = bnx2x_fix_features, 10476 .ndo_fix_features = bnx2x_fix_features,
10477 .ndo_set_features = bnx2x_set_features, 10477 .ndo_set_features = bnx2x_set_features,
10478 .ndo_tx_timeout = bnx2x_tx_timeout, 10478 .ndo_tx_timeout = bnx2x_tx_timeout,
10479 #ifdef CONFIG_NET_POLL_CONTROLLER 10479 #ifdef CONFIG_NET_POLL_CONTROLLER
10480 .ndo_poll_controller = poll_bnx2x, 10480 .ndo_poll_controller = poll_bnx2x,
10481 #endif 10481 #endif
10482 .ndo_setup_tc = bnx2x_setup_tc, 10482 .ndo_setup_tc = bnx2x_setup_tc,
10483 10483
10484 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 10484 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10485 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 10485 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10486 #endif 10486 #endif
10487 }; 10487 };
10488 10488
10489 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) 10489 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10490 { 10490 {
10491 struct device *dev = &bp->pdev->dev; 10491 struct device *dev = &bp->pdev->dev;
10492 10492
10493 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10493 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10494 bp->flags |= USING_DAC_FLAG; 10494 bp->flags |= USING_DAC_FLAG;
10495 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10495 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10496 dev_err(dev, "dma_set_coherent_mask failed, " 10496 dev_err(dev, "dma_set_coherent_mask failed, "
10497 "aborting\n"); 10497 "aborting\n");
10498 return -EIO; 10498 return -EIO;
10499 } 10499 }
10500 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10500 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10501 dev_err(dev, "System does not support DMA, aborting\n"); 10501 dev_err(dev, "System does not support DMA, aborting\n");
10502 return -EIO; 10502 return -EIO;
10503 } 10503 }
10504 10504
10505 return 0; 10505 return 0;
10506 } 10506 }
10507 10507
10508 static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 10508 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10509 struct net_device *dev, 10509 struct net_device *dev,
10510 unsigned long board_type) 10510 unsigned long board_type)
10511 { 10511 {
10512 struct bnx2x *bp; 10512 struct bnx2x *bp;
10513 int rc; 10513 int rc;
10514 10514
10515 SET_NETDEV_DEV(dev, &pdev->dev); 10515 SET_NETDEV_DEV(dev, &pdev->dev);
10516 bp = netdev_priv(dev); 10516 bp = netdev_priv(dev);
10517 10517
10518 bp->dev = dev; 10518 bp->dev = dev;
10519 bp->pdev = pdev; 10519 bp->pdev = pdev;
10520 bp->flags = 0; 10520 bp->flags = 0;
10521 bp->pf_num = PCI_FUNC(pdev->devfn); 10521 bp->pf_num = PCI_FUNC(pdev->devfn);
10522 10522
10523 rc = pci_enable_device(pdev); 10523 rc = pci_enable_device(pdev);
10524 if (rc) { 10524 if (rc) {
10525 dev_err(&bp->pdev->dev, 10525 dev_err(&bp->pdev->dev,
10526 "Cannot enable PCI device, aborting\n"); 10526 "Cannot enable PCI device, aborting\n");
10527 goto err_out; 10527 goto err_out;
10528 } 10528 }
10529 10529
10530 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10530 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10531 dev_err(&bp->pdev->dev, 10531 dev_err(&bp->pdev->dev,
10532 "Cannot find PCI device base address, aborting\n"); 10532 "Cannot find PCI device base address, aborting\n");
10533 rc = -ENODEV; 10533 rc = -ENODEV;
10534 goto err_out_disable; 10534 goto err_out_disable;
10535 } 10535 }
10536 10536
10537 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 10537 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
10538 dev_err(&bp->pdev->dev, "Cannot find second PCI device" 10538 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10539 " base address, aborting\n"); 10539 " base address, aborting\n");
10540 rc = -ENODEV; 10540 rc = -ENODEV;
10541 goto err_out_disable; 10541 goto err_out_disable;
10542 } 10542 }
10543 10543
10544 if (atomic_read(&pdev->enable_cnt) == 1) { 10544 if (atomic_read(&pdev->enable_cnt) == 1) {
10545 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10545 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10546 if (rc) { 10546 if (rc) {
10547 dev_err(&bp->pdev->dev, 10547 dev_err(&bp->pdev->dev,
10548 "Cannot obtain PCI resources, aborting\n"); 10548 "Cannot obtain PCI resources, aborting\n");
10549 goto err_out_disable; 10549 goto err_out_disable;
10550 } 10550 }
10551 10551
10552 pci_set_master(pdev); 10552 pci_set_master(pdev);
10553 pci_save_state(pdev); 10553 pci_save_state(pdev);
10554 } 10554 }
10555 10555
10556 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 10556 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10557 if (bp->pm_cap == 0) { 10557 if (bp->pm_cap == 0) {
10558 dev_err(&bp->pdev->dev, 10558 dev_err(&bp->pdev->dev,
10559 "Cannot find power management capability, aborting\n"); 10559 "Cannot find power management capability, aborting\n");
10560 rc = -EIO; 10560 rc = -EIO;
10561 goto err_out_release; 10561 goto err_out_release;
10562 } 10562 }
10563 10563
10564 if (!pci_is_pcie(pdev)) { 10564 if (!pci_is_pcie(pdev)) {
10565 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10565 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
10566 rc = -EIO; 10566 rc = -EIO;
10567 goto err_out_release; 10567 goto err_out_release;
10568 } 10568 }
10569 10569
10570 rc = bnx2x_set_coherency_mask(bp); 10570 rc = bnx2x_set_coherency_mask(bp);
10571 if (rc) 10571 if (rc)
10572 goto err_out_release; 10572 goto err_out_release;
10573 10573
10574 dev->mem_start = pci_resource_start(pdev, 0); 10574 dev->mem_start = pci_resource_start(pdev, 0);
10575 dev->base_addr = dev->mem_start; 10575 dev->base_addr = dev->mem_start;
10576 dev->mem_end = pci_resource_end(pdev, 0); 10576 dev->mem_end = pci_resource_end(pdev, 0);
10577 10577
10578 dev->irq = pdev->irq; 10578 dev->irq = pdev->irq;
10579 10579
10580 bp->regview = pci_ioremap_bar(pdev, 0); 10580 bp->regview = pci_ioremap_bar(pdev, 0);
10581 if (!bp->regview) { 10581 if (!bp->regview) {
10582 dev_err(&bp->pdev->dev, 10582 dev_err(&bp->pdev->dev,
10583 "Cannot map register space, aborting\n"); 10583 "Cannot map register space, aborting\n");
10584 rc = -ENOMEM; 10584 rc = -ENOMEM;
10585 goto err_out_release; 10585 goto err_out_release;
10586 } 10586 }
10587 10587
10588 bnx2x_set_power_state(bp, PCI_D0); 10588 bnx2x_set_power_state(bp, PCI_D0);
10589 10589
10590 /* clean indirect addresses */ 10590 /* clean indirect addresses */
10591 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 10591 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10592 PCICFG_VENDOR_ID_OFFSET); 10592 PCICFG_VENDOR_ID_OFFSET);
10593 /* 10593 /*
10594 * Clean the following indirect addresses for all functions since it 10594 * Clean the following indirect addresses for all functions since it
10595 * is not used by the driver. 10595 * is not used by the driver.
10596 */ 10596 */
10597 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 10597 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10598 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 10598 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10599 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10599 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10600 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10600 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
10601 10601
10602 if (CHIP_IS_E1x(bp)) { 10602 if (CHIP_IS_E1x(bp)) {
10603 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10603 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10604 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10604 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10605 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10605 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10606 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 10606 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
10607 } 10607 }
10608 10608
10609 /* 10609 /*
10610 * Enable internal target-read (in case we are probed after PF FLR). 10610 * Enable internal target-read (in case we are probed after PF FLR).
10611 * Must be done prior to any BAR read access. Only for 57712 and up 10611 * Must be done prior to any BAR read access. Only for 57712 and up
10612 */ 10612 */
10613 if (board_type != BCM57710 && 10613 if (board_type != BCM57710 &&
10614 board_type != BCM57711 && 10614 board_type != BCM57711 &&
10615 board_type != BCM57711E) 10615 board_type != BCM57711E)
10616 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10616 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10617 10617
10618 /* Reset the load counter */ 10618 /* Reset the load counter */
10619 bnx2x_clear_load_cnt(bp); 10619 bnx2x_clear_load_cnt(bp);
10620 10620
10621 dev->watchdog_timeo = TX_TIMEOUT; 10621 dev->watchdog_timeo = TX_TIMEOUT;
10622 10622
10623 dev->netdev_ops = &bnx2x_netdev_ops; 10623 dev->netdev_ops = &bnx2x_netdev_ops;
10624 bnx2x_set_ethtool_ops(dev); 10624 bnx2x_set_ethtool_ops(dev);
10625 10625
10626 dev->priv_flags |= IFF_UNICAST_FLT; 10626 dev->priv_flags |= IFF_UNICAST_FLT;
10627 10627
10628 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10628 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10629 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO | 10629 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO |
10630 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 10630 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
10631 10631
10632 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10632 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10633 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 10633 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10634 10634
10635 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 10635 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
10636 if (bp->flags & USING_DAC_FLAG) 10636 if (bp->flags & USING_DAC_FLAG)
10637 dev->features |= NETIF_F_HIGHDMA; 10637 dev->features |= NETIF_F_HIGHDMA;
10638 10638
10639 /* Add Loopback capability to the device */ 10639 /* Add Loopback capability to the device */
10640 dev->hw_features |= NETIF_F_LOOPBACK; 10640 dev->hw_features |= NETIF_F_LOOPBACK;
10641 10641
10642 #ifdef BCM_DCBNL 10642 #ifdef BCM_DCBNL
10643 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 10643 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10644 #endif 10644 #endif
10645 10645
10646 /* get_port_hwinfo() will set prtad and mmds properly */ 10646 /* get_port_hwinfo() will set prtad and mmds properly */
10647 bp->mdio.prtad = MDIO_PRTAD_NONE; 10647 bp->mdio.prtad = MDIO_PRTAD_NONE;
10648 bp->mdio.mmds = 0; 10648 bp->mdio.mmds = 0;
10649 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10649 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10650 bp->mdio.dev = dev; 10650 bp->mdio.dev = dev;
10651 bp->mdio.mdio_read = bnx2x_mdio_read; 10651 bp->mdio.mdio_read = bnx2x_mdio_read;
10652 bp->mdio.mdio_write = bnx2x_mdio_write; 10652 bp->mdio.mdio_write = bnx2x_mdio_write;
10653 10653
10654 return 0; 10654 return 0;
10655 10655
10656 err_out_release: 10656 err_out_release:
10657 if (atomic_read(&pdev->enable_cnt) == 1) 10657 if (atomic_read(&pdev->enable_cnt) == 1)
10658 pci_release_regions(pdev); 10658 pci_release_regions(pdev);
10659 10659
10660 err_out_disable: 10660 err_out_disable:
10661 pci_disable_device(pdev); 10661 pci_disable_device(pdev);
10662 pci_set_drvdata(pdev, NULL); 10662 pci_set_drvdata(pdev, NULL);
10663 10663
10664 err_out: 10664 err_out:
10665 return rc; 10665 return rc;
10666 } 10666 }
10667 10667
10668 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, 10668 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10669 int *width, int *speed) 10669 int *width, int *speed)
10670 { 10670 {
10671 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); 10671 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10672 10672
10673 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 10673 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10674 10674
10675 /* return value of 1=2.5GHz 2=5GHz */ 10675 /* return value of 1=2.5GHz 2=5GHz */
10676 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 10676 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10677 } 10677 }
10678 10678
10679 static int bnx2x_check_firmware(struct bnx2x *bp) 10679 static int bnx2x_check_firmware(struct bnx2x *bp)
10680 { 10680 {
10681 const struct firmware *firmware = bp->firmware; 10681 const struct firmware *firmware = bp->firmware;
10682 struct bnx2x_fw_file_hdr *fw_hdr; 10682 struct bnx2x_fw_file_hdr *fw_hdr;
10683 struct bnx2x_fw_file_section *sections; 10683 struct bnx2x_fw_file_section *sections;
10684 u32 offset, len, num_ops; 10684 u32 offset, len, num_ops;
10685 u16 *ops_offsets; 10685 u16 *ops_offsets;
10686 int i; 10686 int i;
10687 const u8 *fw_ver; 10687 const u8 *fw_ver;
10688 10688
10689 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) 10689 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10690 return -EINVAL; 10690 return -EINVAL;
10691 10691
10692 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 10692 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10693 sections = (struct bnx2x_fw_file_section *)fw_hdr; 10693 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10694 10694
10695 /* Make sure none of the offsets and sizes make us read beyond 10695 /* Make sure none of the offsets and sizes make us read beyond
10696 * the end of the firmware data */ 10696 * the end of the firmware data */
10697 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 10697 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10698 offset = be32_to_cpu(sections[i].offset); 10698 offset = be32_to_cpu(sections[i].offset);
10699 len = be32_to_cpu(sections[i].len); 10699 len = be32_to_cpu(sections[i].len);
10700 if (offset + len > firmware->size) { 10700 if (offset + len > firmware->size) {
10701 dev_err(&bp->pdev->dev, 10701 dev_err(&bp->pdev->dev,
10702 "Section %d length is out of bounds\n", i); 10702 "Section %d length is out of bounds\n", i);
10703 return -EINVAL; 10703 return -EINVAL;
10704 } 10704 }
10705 } 10705 }
10706 10706
10707 /* Likewise for the init_ops offsets */ 10707 /* Likewise for the init_ops offsets */
10708 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 10708 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10709 ops_offsets = (u16 *)(firmware->data + offset); 10709 ops_offsets = (u16 *)(firmware->data + offset);
10710 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 10710 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10711 10711
10712 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 10712 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10713 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 10713 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
10714 dev_err(&bp->pdev->dev, 10714 dev_err(&bp->pdev->dev,
10715 "Section offset %d is out of bounds\n", i); 10715 "Section offset %d is out of bounds\n", i);
10716 return -EINVAL; 10716 return -EINVAL;
10717 } 10717 }
10718 } 10718 }
10719 10719
10720 /* Check FW version */ 10720 /* Check FW version */
10721 offset = be32_to_cpu(fw_hdr->fw_version.offset); 10721 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10722 fw_ver = firmware->data + offset; 10722 fw_ver = firmware->data + offset;
10723 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 10723 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10724 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 10724 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10725 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 10725 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10726 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 10726 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
10727 dev_err(&bp->pdev->dev, 10727 dev_err(&bp->pdev->dev,
10728 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 10728 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10729 fw_ver[0], fw_ver[1], fw_ver[2], 10729 fw_ver[0], fw_ver[1], fw_ver[2],
10730 fw_ver[3], BCM_5710_FW_MAJOR_VERSION, 10730 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10731 BCM_5710_FW_MINOR_VERSION, 10731 BCM_5710_FW_MINOR_VERSION,
10732 BCM_5710_FW_REVISION_VERSION, 10732 BCM_5710_FW_REVISION_VERSION,
10733 BCM_5710_FW_ENGINEERING_VERSION); 10733 BCM_5710_FW_ENGINEERING_VERSION);
10734 return -EINVAL; 10734 return -EINVAL;
10735 } 10735 }
10736 10736
10737 return 0; 10737 return 0;
10738 } 10738 }
10739 10739
10740 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10740 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10741 { 10741 {
10742 const __be32 *source = (const __be32 *)_source; 10742 const __be32 *source = (const __be32 *)_source;
10743 u32 *target = (u32 *)_target; 10743 u32 *target = (u32 *)_target;
10744 u32 i; 10744 u32 i;
10745 10745
10746 for (i = 0; i < n/4; i++) 10746 for (i = 0; i < n/4; i++)
10747 target[i] = be32_to_cpu(source[i]); 10747 target[i] = be32_to_cpu(source[i]);
10748 } 10748 }
10749 10749
10750 /* 10750 /*
10751 Ops array is stored in the following format: 10751 Ops array is stored in the following format:
10752 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 10752 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10753 */ 10753 */
10754 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 10754 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
10755 { 10755 {
10756 const __be32 *source = (const __be32 *)_source; 10756 const __be32 *source = (const __be32 *)_source;
10757 struct raw_op *target = (struct raw_op *)_target; 10757 struct raw_op *target = (struct raw_op *)_target;
10758 u32 i, j, tmp; 10758 u32 i, j, tmp;
10759 10759
10760 for (i = 0, j = 0; i < n/8; i++, j += 2) { 10760 for (i = 0, j = 0; i < n/8; i++, j += 2) {
10761 tmp = be32_to_cpu(source[j]); 10761 tmp = be32_to_cpu(source[j]);
10762 target[i].op = (tmp >> 24) & 0xff; 10762 target[i].op = (tmp >> 24) & 0xff;
10763 target[i].offset = tmp & 0xffffff; 10763 target[i].offset = tmp & 0xffffff;
10764 target[i].raw_data = be32_to_cpu(source[j + 1]); 10764 target[i].raw_data = be32_to_cpu(source[j + 1]);
10765 } 10765 }
10766 } 10766 }
10767 10767
10768 /** 10768 /**
10769 * IRO array is stored in the following format: 10769 * IRO array is stored in the following format:
10770 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 10770 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10771 */ 10771 */
10772 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 10772 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10773 { 10773 {
10774 const __be32 *source = (const __be32 *)_source; 10774 const __be32 *source = (const __be32 *)_source;
10775 struct iro *target = (struct iro *)_target; 10775 struct iro *target = (struct iro *)_target;
10776 u32 i, j, tmp; 10776 u32 i, j, tmp;
10777 10777
10778 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 10778 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10779 target[i].base = be32_to_cpu(source[j]); 10779 target[i].base = be32_to_cpu(source[j]);
10780 j++; 10780 j++;
10781 tmp = be32_to_cpu(source[j]); 10781 tmp = be32_to_cpu(source[j]);
10782 target[i].m1 = (tmp >> 16) & 0xffff; 10782 target[i].m1 = (tmp >> 16) & 0xffff;
10783 target[i].m2 = tmp & 0xffff; 10783 target[i].m2 = tmp & 0xffff;
10784 j++; 10784 j++;
10785 tmp = be32_to_cpu(source[j]); 10785 tmp = be32_to_cpu(source[j]);
10786 target[i].m3 = (tmp >> 16) & 0xffff; 10786 target[i].m3 = (tmp >> 16) & 0xffff;
10787 target[i].size = tmp & 0xffff; 10787 target[i].size = tmp & 0xffff;
10788 j++; 10788 j++;
10789 } 10789 }
10790 } 10790 }
10791 10791
10792 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10792 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10793 { 10793 {
10794 const __be16 *source = (const __be16 *)_source; 10794 const __be16 *source = (const __be16 *)_source;
10795 u16 *target = (u16 *)_target; 10795 u16 *target = (u16 *)_target;
10796 u32 i; 10796 u32 i;
10797 10797
10798 for (i = 0; i < n/2; i++) 10798 for (i = 0; i < n/2; i++)
10799 target[i] = be16_to_cpu(source[i]); 10799 target[i] = be16_to_cpu(source[i]);
10800 } 10800 }
10801 10801
10802 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 10802 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10803 do { \ 10803 do { \
10804 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 10804 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10805 bp->arr = kmalloc(len, GFP_KERNEL); \ 10805 bp->arr = kmalloc(len, GFP_KERNEL); \
10806 if (!bp->arr) { \ 10806 if (!bp->arr) { \
10807 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \ 10807 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10808 goto lbl; \ 10808 goto lbl; \
10809 } \ 10809 } \
10810 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 10810 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10811 (u8 *)bp->arr, len); \ 10811 (u8 *)bp->arr, len); \
10812 } while (0) 10812 } while (0)
10813 10813
10814 int bnx2x_init_firmware(struct bnx2x *bp) 10814 int bnx2x_init_firmware(struct bnx2x *bp)
10815 { 10815 {
10816 struct bnx2x_fw_file_hdr *fw_hdr; 10816 struct bnx2x_fw_file_hdr *fw_hdr;
10817 int rc; 10817 int rc;
10818 10818
10819 10819
10820 if (!bp->firmware) { 10820 if (!bp->firmware) {
10821 const char *fw_file_name; 10821 const char *fw_file_name;
10822 10822
10823 if (CHIP_IS_E1(bp)) 10823 if (CHIP_IS_E1(bp))
10824 fw_file_name = FW_FILE_NAME_E1; 10824 fw_file_name = FW_FILE_NAME_E1;
10825 else if (CHIP_IS_E1H(bp)) 10825 else if (CHIP_IS_E1H(bp))
10826 fw_file_name = FW_FILE_NAME_E1H; 10826 fw_file_name = FW_FILE_NAME_E1H;
10827 else if (!CHIP_IS_E1x(bp)) 10827 else if (!CHIP_IS_E1x(bp))
10828 fw_file_name = FW_FILE_NAME_E2; 10828 fw_file_name = FW_FILE_NAME_E2;
10829 else { 10829 else {
10830 BNX2X_ERR("Unsupported chip revision\n"); 10830 BNX2X_ERR("Unsupported chip revision\n");
10831 return -EINVAL; 10831 return -EINVAL;
10832 } 10832 }
10833 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 10833 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
10834 10834
10835 rc = request_firmware(&bp->firmware, fw_file_name, 10835 rc = request_firmware(&bp->firmware, fw_file_name,
10836 &bp->pdev->dev); 10836 &bp->pdev->dev);
10837 if (rc) { 10837 if (rc) {
10838 BNX2X_ERR("Can't load firmware file %s\n", 10838 BNX2X_ERR("Can't load firmware file %s\n",
10839 fw_file_name); 10839 fw_file_name);
10840 goto request_firmware_exit; 10840 goto request_firmware_exit;
10841 } 10841 }
10842 10842
10843 rc = bnx2x_check_firmware(bp); 10843 rc = bnx2x_check_firmware(bp);
10844 if (rc) { 10844 if (rc) {
10845 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 10845 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10846 goto request_firmware_exit; 10846 goto request_firmware_exit;
10847 } 10847 }
10848 } 10848 }
10849 10849
10850 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 10850 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10851 10851
10852 /* Initialize the pointers to the init arrays */ 10852 /* Initialize the pointers to the init arrays */
10853 /* Blob */ 10853 /* Blob */
10854 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 10854 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10855 10855
10856 /* Opcodes */ 10856 /* Opcodes */
10857 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 10857 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10858 10858
10859 /* Offsets */ 10859 /* Offsets */
10860 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 10860 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10861 be16_to_cpu_n); 10861 be16_to_cpu_n);
10862 10862
10863 /* STORMs firmware */ 10863 /* STORMs firmware */
10864 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10864 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10865 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 10865 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10866 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 10866 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10867 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 10867 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10868 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10868 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10869 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 10869 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10870 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 10870 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10871 be32_to_cpu(fw_hdr->usem_pram_data.offset); 10871 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10872 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10872 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10873 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 10873 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10874 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 10874 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10875 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 10875 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10876 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10876 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10877 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 10877 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10878 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 10878 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10879 be32_to_cpu(fw_hdr->csem_pram_data.offset); 10879 be32_to_cpu(fw_hdr->csem_pram_data.offset);
10880 /* IRO */ 10880 /* IRO */
10881 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 10881 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
10882 10882
10883 return 0; 10883 return 0;
10884 10884
10885 iro_alloc_err: 10885 iro_alloc_err:
10886 kfree(bp->init_ops_offsets); 10886 kfree(bp->init_ops_offsets);
10887 init_offsets_alloc_err: 10887 init_offsets_alloc_err:
10888 kfree(bp->init_ops); 10888 kfree(bp->init_ops);
10889 init_ops_alloc_err: 10889 init_ops_alloc_err:
10890 kfree(bp->init_data); 10890 kfree(bp->init_data);
10891 request_firmware_exit: 10891 request_firmware_exit:
10892 release_firmware(bp->firmware); 10892 release_firmware(bp->firmware);
10893 10893
10894 return rc; 10894 return rc;
10895 } 10895 }
10896 10896
10897 static void bnx2x_release_firmware(struct bnx2x *bp) 10897 static void bnx2x_release_firmware(struct bnx2x *bp)
10898 { 10898 {
10899 kfree(bp->init_ops_offsets); 10899 kfree(bp->init_ops_offsets);
10900 kfree(bp->init_ops); 10900 kfree(bp->init_ops);
10901 kfree(bp->init_data); 10901 kfree(bp->init_data);
10902 release_firmware(bp->firmware); 10902 release_firmware(bp->firmware);
10903 bp->firmware = NULL; 10903 bp->firmware = NULL;
10904 } 10904 }
10905 10905
10906 10906
10907 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 10907 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10908 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 10908 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10909 .init_hw_cmn = bnx2x_init_hw_common, 10909 .init_hw_cmn = bnx2x_init_hw_common,
10910 .init_hw_port = bnx2x_init_hw_port, 10910 .init_hw_port = bnx2x_init_hw_port,
10911 .init_hw_func = bnx2x_init_hw_func, 10911 .init_hw_func = bnx2x_init_hw_func,
10912 10912
10913 .reset_hw_cmn = bnx2x_reset_common, 10913 .reset_hw_cmn = bnx2x_reset_common,
10914 .reset_hw_port = bnx2x_reset_port, 10914 .reset_hw_port = bnx2x_reset_port,
10915 .reset_hw_func = bnx2x_reset_func, 10915 .reset_hw_func = bnx2x_reset_func,
10916 10916
10917 .gunzip_init = bnx2x_gunzip_init, 10917 .gunzip_init = bnx2x_gunzip_init,
10918 .gunzip_end = bnx2x_gunzip_end, 10918 .gunzip_end = bnx2x_gunzip_end,
10919 10919
10920 .init_fw = bnx2x_init_firmware, 10920 .init_fw = bnx2x_init_firmware,
10921 .release_fw = bnx2x_release_firmware, 10921 .release_fw = bnx2x_release_firmware,
10922 }; 10922 };
10923 10923
10924 void bnx2x__init_func_obj(struct bnx2x *bp) 10924 void bnx2x__init_func_obj(struct bnx2x *bp)
10925 { 10925 {
10926 /* Prepare DMAE related driver resources */ 10926 /* Prepare DMAE related driver resources */
10927 bnx2x_setup_dmae(bp); 10927 bnx2x_setup_dmae(bp);
10928 10928
10929 bnx2x_init_func_obj(bp, &bp->func_obj, 10929 bnx2x_init_func_obj(bp, &bp->func_obj,
10930 bnx2x_sp(bp, func_rdata), 10930 bnx2x_sp(bp, func_rdata),
10931 bnx2x_sp_mapping(bp, func_rdata), 10931 bnx2x_sp_mapping(bp, func_rdata),
10932 &bnx2x_func_sp_drv); 10932 &bnx2x_func_sp_drv);
10933 } 10933 }
10934 10934
10935 /* must be called after sriov-enable */ 10935 /* must be called after sriov-enable */
10936 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) 10936 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
10937 { 10937 {
10938 int cid_count = BNX2X_L2_CID_COUNT(bp); 10938 int cid_count = BNX2X_L2_CID_COUNT(bp);
10939 10939
10940 #ifdef BCM_CNIC 10940 #ifdef BCM_CNIC
10941 cid_count += CNIC_CID_MAX; 10941 cid_count += CNIC_CID_MAX;
10942 #endif 10942 #endif
10943 return roundup(cid_count, QM_CID_ROUND); 10943 return roundup(cid_count, QM_CID_ROUND);
10944 } 10944 }
10945 10945
10946 /** 10946 /**
10947 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 10947 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
10948 * 10948 *
10949 * @dev: pci device 10949 * @dev: pci device
10950 * 10950 *
10951 */ 10951 */
10952 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) 10952 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
10953 { 10953 {
10954 int pos; 10954 int pos;
10955 u16 control; 10955 u16 control;
10956 10956
10957 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 10957 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10958 10958
10959 /* 10959 /*
10960 * If MSI-X is not supported - return number of SBs needed to support 10960 * If MSI-X is not supported - return number of SBs needed to support
10961 * one fast path queue: one FP queue + SB for CNIC 10961 * one fast path queue: one FP queue + SB for CNIC
10962 */ 10962 */
10963 if (!pos) 10963 if (!pos)
10964 return 1 + CNIC_PRESENT; 10964 return 1 + CNIC_PRESENT;
10965 10965
10966 /* 10966 /*
10967 * The value in the PCI configuration space is the index of the last 10967 * The value in the PCI configuration space is the index of the last
10968 * entry, namely one less than the actual size of the table, which is 10968 * entry, namely one less than the actual size of the table, which is
10969 * exactly what we want to return from this function: number of all SBs 10969 * exactly what we want to return from this function: number of all SBs
10970 * without the default SB. 10970 * without the default SB.
10971 */ 10971 */
10972 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 10972 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10973 return control & PCI_MSIX_FLAGS_QSIZE; 10973 return control & PCI_MSIX_FLAGS_QSIZE;
10974 } 10974 }
10975 10975
10976 static int __devinit bnx2x_init_one(struct pci_dev *pdev, 10976 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10977 const struct pci_device_id *ent) 10977 const struct pci_device_id *ent)
10978 { 10978 {
10979 struct net_device *dev = NULL; 10979 struct net_device *dev = NULL;
10980 struct bnx2x *bp; 10980 struct bnx2x *bp;
10981 int pcie_width, pcie_speed; 10981 int pcie_width, pcie_speed;
10982 int rc, max_non_def_sbs; 10982 int rc, max_non_def_sbs;
10983 int rx_count, tx_count, rss_count; 10983 int rx_count, tx_count, rss_count;
10984 /* 10984 /*
10985 * An estimated maximum supported CoS number according to the chip 10985 * An estimated maximum supported CoS number according to the chip
10986 * version. 10986 * version.
10987 * We will try to roughly estimate the maximum number of CoSes this chip 10987 * We will try to roughly estimate the maximum number of CoSes this chip
10988 * may support in order to minimize the memory allocated for Tx 10988 * may support in order to minimize the memory allocated for Tx
10989 * netdev_queue's. This number will be accurately calculated during the 10989 * netdev_queue's. This number will be accurately calculated during the
10990 * initialization of bp->max_cos based on the chip versions AND chip 10990 * initialization of bp->max_cos based on the chip versions AND chip
10991 * revision in the bnx2x_init_bp(). 10991 * revision in the bnx2x_init_bp().
10992 */ 10992 */
10993 u8 max_cos_est = 0; 10993 u8 max_cos_est = 0;
10994 10994
10995 switch (ent->driver_data) { 10995 switch (ent->driver_data) {
10996 case BCM57710: 10996 case BCM57710:
10997 case BCM57711: 10997 case BCM57711:
10998 case BCM57711E: 10998 case BCM57711E:
10999 max_cos_est = BNX2X_MULTI_TX_COS_E1X; 10999 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
11000 break; 11000 break;
11001 11001
11002 case BCM57712: 11002 case BCM57712:
11003 case BCM57712_MF: 11003 case BCM57712_MF:
11004 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; 11004 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
11005 break; 11005 break;
11006 11006
11007 case BCM57800: 11007 case BCM57800:
11008 case BCM57800_MF: 11008 case BCM57800_MF:
11009 case BCM57810: 11009 case BCM57810:
11010 case BCM57810_MF: 11010 case BCM57810_MF:
11011 case BCM57840: 11011 case BCM57840:
11012 case BCM57840_MF: 11012 case BCM57840_MF:
11013 max_cos_est = BNX2X_MULTI_TX_COS_E3B0; 11013 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
11014 break; 11014 break;
11015 11015
11016 default: 11016 default:
11017 pr_err("Unknown board_type (%ld), aborting\n", 11017 pr_err("Unknown board_type (%ld), aborting\n",
11018 ent->driver_data); 11018 ent->driver_data);
11019 return -ENODEV; 11019 return -ENODEV;
11020 } 11020 }
11021 11021
11022 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); 11022 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
11023 11023
11024 /* !!! FIXME !!! 11024 /* !!! FIXME !!!
11025 * Do not allow the maximum SB count to grow above 16 11025 * Do not allow the maximum SB count to grow above 16
11026 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. 11026 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
11027 * We will use the FP_SB_MAX_E1x macro for this matter. 11027 * We will use the FP_SB_MAX_E1x macro for this matter.
11028 */ 11028 */
11029 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); 11029 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
11030 11030
11031 WARN_ON(!max_non_def_sbs); 11031 WARN_ON(!max_non_def_sbs);
11032 11032
11033 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 11033 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11034 rss_count = max_non_def_sbs - CNIC_PRESENT; 11034 rss_count = max_non_def_sbs - CNIC_PRESENT;
11035 11035
11036 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 11036 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11037 rx_count = rss_count + FCOE_PRESENT; 11037 rx_count = rss_count + FCOE_PRESENT;
11038 11038
11039 /* 11039 /*
11040 * Maximum number of netdev Tx queues: 11040 * Maximum number of netdev Tx queues:
11041 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 11041 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11042 */ 11042 */
11043 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; 11043 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
11044 11044
11045 /* dev zeroed in init_etherdev */ 11045 /* dev zeroed in init_etherdev */
11046 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 11046 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
11047 if (!dev) { 11047 if (!dev) {
11048 dev_err(&pdev->dev, "Cannot allocate net device\n"); 11048 dev_err(&pdev->dev, "Cannot allocate net device\n");
11049 return -ENOMEM; 11049 return -ENOMEM;
11050 } 11050 }
11051 11051
11052 bp = netdev_priv(dev); 11052 bp = netdev_priv(dev);
11053 11053
11054 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", 11054 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
11055 tx_count, rx_count); 11055 tx_count, rx_count);
11056 11056
11057 bp->igu_sb_cnt = max_non_def_sbs; 11057 bp->igu_sb_cnt = max_non_def_sbs;
11058 bp->msg_enable = debug; 11058 bp->msg_enable = debug;
11059 pci_set_drvdata(pdev, dev); 11059 pci_set_drvdata(pdev, dev);
11060 11060
11061 rc = bnx2x_init_dev(pdev, dev, ent->driver_data); 11061 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
11062 if (rc < 0) { 11062 if (rc < 0) {
11063 free_netdev(dev); 11063 free_netdev(dev);
11064 return rc; 11064 return rc;
11065 } 11065 }
11066 11066
11067 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs); 11067 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs);
11068 11068
11069 rc = bnx2x_init_bp(bp); 11069 rc = bnx2x_init_bp(bp);
11070 if (rc) 11070 if (rc)
11071 goto init_one_exit; 11071 goto init_one_exit;
11072 11072
11073 /* 11073 /*
11074 * Map doorbels here as we need the real value of bp->max_cos which 11074 * Map doorbels here as we need the real value of bp->max_cos which
11075 * is initialized in bnx2x_init_bp(). 11075 * is initialized in bnx2x_init_bp().
11076 */ 11076 */
11077 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 11077 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
11078 min_t(u64, BNX2X_DB_SIZE(bp), 11078 min_t(u64, BNX2X_DB_SIZE(bp),
11079 pci_resource_len(pdev, 2))); 11079 pci_resource_len(pdev, 2)));
11080 if (!bp->doorbells) { 11080 if (!bp->doorbells) {
11081 dev_err(&bp->pdev->dev, 11081 dev_err(&bp->pdev->dev,
11082 "Cannot map doorbell space, aborting\n"); 11082 "Cannot map doorbell space, aborting\n");
11083 rc = -ENOMEM; 11083 rc = -ENOMEM;
11084 goto init_one_exit; 11084 goto init_one_exit;
11085 } 11085 }
11086 11086
11087 /* calc qm_cid_count */ 11087 /* calc qm_cid_count */
11088 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 11088 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
11089 11089
11090 #ifdef BCM_CNIC 11090 #ifdef BCM_CNIC
11091 /* disable FCOE L2 queue for E1x */ 11091 /* disable FCOE L2 queue for E1x */
11092 if (CHIP_IS_E1x(bp)) 11092 if (CHIP_IS_E1x(bp))
11093 bp->flags |= NO_FCOE_FLAG; 11093 bp->flags |= NO_FCOE_FLAG;
11094 11094
11095 #endif 11095 #endif
11096 11096
11097 /* Configure interrupt mode: try to enable MSI-X/MSI if 11097 /* Configure interrupt mode: try to enable MSI-X/MSI if
11098 * needed, set bp->num_queues appropriately. 11098 * needed, set bp->num_queues appropriately.
11099 */ 11099 */
11100 bnx2x_set_int_mode(bp); 11100 bnx2x_set_int_mode(bp);
11101 11101
11102 /* Add all NAPI objects */ 11102 /* Add all NAPI objects */
11103 bnx2x_add_all_napi(bp); 11103 bnx2x_add_all_napi(bp);
11104 11104
11105 rc = register_netdev(dev); 11105 rc = register_netdev(dev);
11106 if (rc) { 11106 if (rc) {
11107 dev_err(&pdev->dev, "Cannot register net device\n"); 11107 dev_err(&pdev->dev, "Cannot register net device\n");
11108 goto init_one_exit; 11108 goto init_one_exit;
11109 } 11109 }
11110 11110
11111 #ifdef BCM_CNIC 11111 #ifdef BCM_CNIC
11112 if (!NO_FCOE(bp)) { 11112 if (!NO_FCOE(bp)) {
11113 /* Add storage MAC address */ 11113 /* Add storage MAC address */
11114 rtnl_lock(); 11114 rtnl_lock();
11115 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11115 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11116 rtnl_unlock(); 11116 rtnl_unlock();
11117 } 11117 }
11118 #endif 11118 #endif
11119 11119
11120 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 11120 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
11121 11121
11122 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 11122 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11123 board_info[ent->driver_data].name, 11123 board_info[ent->driver_data].name,
11124 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 11124 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11125 pcie_width, 11125 pcie_width,
11126 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 11126 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
11127 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 11127 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
11128 "5GHz (Gen2)" : "2.5GHz", 11128 "5GHz (Gen2)" : "2.5GHz",
11129 dev->base_addr, bp->pdev->irq, dev->dev_addr); 11129 dev->base_addr, bp->pdev->irq, dev->dev_addr);
11130 11130
11131 return 0; 11131 return 0;
11132 11132
11133 init_one_exit: 11133 init_one_exit:
11134 if (bp->regview) 11134 if (bp->regview)
11135 iounmap(bp->regview); 11135 iounmap(bp->regview);
11136 11136
11137 if (bp->doorbells) 11137 if (bp->doorbells)
11138 iounmap(bp->doorbells); 11138 iounmap(bp->doorbells);
11139 11139
11140 free_netdev(dev); 11140 free_netdev(dev);
11141 11141
11142 if (atomic_read(&pdev->enable_cnt) == 1) 11142 if (atomic_read(&pdev->enable_cnt) == 1)
11143 pci_release_regions(pdev); 11143 pci_release_regions(pdev);
11144 11144
11145 pci_disable_device(pdev); 11145 pci_disable_device(pdev);
11146 pci_set_drvdata(pdev, NULL); 11146 pci_set_drvdata(pdev, NULL);
11147 11147
11148 return rc; 11148 return rc;
11149 } 11149 }
11150 11150
11151 static void __devexit bnx2x_remove_one(struct pci_dev *pdev) 11151 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
11152 { 11152 {
11153 struct net_device *dev = pci_get_drvdata(pdev); 11153 struct net_device *dev = pci_get_drvdata(pdev);
11154 struct bnx2x *bp; 11154 struct bnx2x *bp;
11155 11155
11156 if (!dev) { 11156 if (!dev) {
11157 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 11157 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
11158 return; 11158 return;
11159 } 11159 }
11160 bp = netdev_priv(dev); 11160 bp = netdev_priv(dev);
11161 11161
11162 #ifdef BCM_CNIC 11162 #ifdef BCM_CNIC
11163 /* Delete storage MAC address */ 11163 /* Delete storage MAC address */
11164 if (!NO_FCOE(bp)) { 11164 if (!NO_FCOE(bp)) {
11165 rtnl_lock(); 11165 rtnl_lock();
11166 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11166 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11167 rtnl_unlock(); 11167 rtnl_unlock();
11168 } 11168 }
11169 #endif 11169 #endif
11170 11170
11171 #ifdef BCM_DCBNL 11171 #ifdef BCM_DCBNL
11172 /* Delete app tlvs from dcbnl */ 11172 /* Delete app tlvs from dcbnl */
11173 bnx2x_dcbnl_update_applist(bp, true); 11173 bnx2x_dcbnl_update_applist(bp, true);
11174 #endif 11174 #endif
11175 11175
11176 unregister_netdev(dev); 11176 unregister_netdev(dev);
11177 11177
11178 /* Delete all NAPI objects */ 11178 /* Delete all NAPI objects */
11179 bnx2x_del_all_napi(bp); 11179 bnx2x_del_all_napi(bp);
11180 11180
11181 /* Power on: we can't let PCI layer write to us while we are in D3 */ 11181 /* Power on: we can't let PCI layer write to us while we are in D3 */
11182 bnx2x_set_power_state(bp, PCI_D0); 11182 bnx2x_set_power_state(bp, PCI_D0);
11183 11183
11184 /* Disable MSI/MSI-X */ 11184 /* Disable MSI/MSI-X */
11185 bnx2x_disable_msi(bp); 11185 bnx2x_disable_msi(bp);
11186 11186
11187 /* Power off */ 11187 /* Power off */
11188 bnx2x_set_power_state(bp, PCI_D3hot); 11188 bnx2x_set_power_state(bp, PCI_D3hot);
11189 11189
11190 /* Make sure RESET task is not scheduled before continuing */ 11190 /* Make sure RESET task is not scheduled before continuing */
11191 cancel_delayed_work_sync(&bp->sp_rtnl_task); 11191 cancel_delayed_work_sync(&bp->sp_rtnl_task);
11192 11192
11193 if (bp->regview) 11193 if (bp->regview)
11194 iounmap(bp->regview); 11194 iounmap(bp->regview);
11195 11195
11196 if (bp->doorbells) 11196 if (bp->doorbells)
11197 iounmap(bp->doorbells); 11197 iounmap(bp->doorbells);
11198 11198
11199 bnx2x_release_firmware(bp); 11199 bnx2x_release_firmware(bp);
11200 11200
11201 bnx2x_free_mem_bp(bp); 11201 bnx2x_free_mem_bp(bp);
11202 11202
11203 free_netdev(dev); 11203 free_netdev(dev);
11204 11204
11205 if (atomic_read(&pdev->enable_cnt) == 1) 11205 if (atomic_read(&pdev->enable_cnt) == 1)
11206 pci_release_regions(pdev); 11206 pci_release_regions(pdev);
11207 11207
11208 pci_disable_device(pdev); 11208 pci_disable_device(pdev);
11209 pci_set_drvdata(pdev, NULL); 11209 pci_set_drvdata(pdev, NULL);
11210 } 11210 }
11211 11211
11212 static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 11212 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
11213 { 11213 {
11214 int i; 11214 int i;
11215 11215
11216 bp->state = BNX2X_STATE_ERROR; 11216 bp->state = BNX2X_STATE_ERROR;
11217 11217
11218 bp->rx_mode = BNX2X_RX_MODE_NONE; 11218 bp->rx_mode = BNX2X_RX_MODE_NONE;
11219 11219
11220 #ifdef BCM_CNIC 11220 #ifdef BCM_CNIC
11221 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 11221 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
11222 #endif 11222 #endif
11223 /* Stop Tx */ 11223 /* Stop Tx */
11224 bnx2x_tx_disable(bp); 11224 bnx2x_tx_disable(bp);
11225 11225
11226 bnx2x_netif_stop(bp, 0); 11226 bnx2x_netif_stop(bp, 0);
11227 11227
11228 del_timer_sync(&bp->timer); 11228 del_timer_sync(&bp->timer);
11229 11229
11230 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11230 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
11231 11231
11232 /* Release IRQs */ 11232 /* Release IRQs */
11233 bnx2x_free_irq(bp); 11233 bnx2x_free_irq(bp);
11234 11234
11235 /* Free SKBs, SGEs, TPA pool and driver internals */ 11235 /* Free SKBs, SGEs, TPA pool and driver internals */
11236 bnx2x_free_skbs(bp); 11236 bnx2x_free_skbs(bp);
11237 11237
11238 for_each_rx_queue(bp, i) 11238 for_each_rx_queue(bp, i)
11239 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 11239 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
11240 11240
11241 bnx2x_free_mem(bp); 11241 bnx2x_free_mem(bp);
11242 11242
11243 bp->state = BNX2X_STATE_CLOSED; 11243 bp->state = BNX2X_STATE_CLOSED;
11244 11244
11245 netif_carrier_off(bp->dev); 11245 netif_carrier_off(bp->dev);
11246 11246
11247 return 0; 11247 return 0;
11248 } 11248 }
11249 11249
11250 static void bnx2x_eeh_recover(struct bnx2x *bp) 11250 static void bnx2x_eeh_recover(struct bnx2x *bp)
11251 { 11251 {
11252 u32 val; 11252 u32 val;
11253 11253
11254 mutex_init(&bp->port.phy_mutex); 11254 mutex_init(&bp->port.phy_mutex);
11255 11255
11256 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 11256 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
11257 bp->link_params.shmem_base = bp->common.shmem_base; 11257 bp->link_params.shmem_base = bp->common.shmem_base;
11258 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base); 11258 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
11259 11259
11260 if (!bp->common.shmem_base || 11260 if (!bp->common.shmem_base ||
11261 (bp->common.shmem_base < 0xA0000) || 11261 (bp->common.shmem_base < 0xA0000) ||
11262 (bp->common.shmem_base >= 0xC0000)) { 11262 (bp->common.shmem_base >= 0xC0000)) {
11263 BNX2X_DEV_INFO("MCP not active\n"); 11263 BNX2X_DEV_INFO("MCP not active\n");
11264 bp->flags |= NO_MCP_FLAG; 11264 bp->flags |= NO_MCP_FLAG;
11265 return; 11265 return;
11266 } 11266 }
11267 11267
11268 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 11268 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
11269 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11269 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11270 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11270 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11271 BNX2X_ERR("BAD MCP validity signature\n"); 11271 BNX2X_ERR("BAD MCP validity signature\n");
11272 11272
11273 if (!BP_NOMCP(bp)) { 11273 if (!BP_NOMCP(bp)) {
11274 bp->fw_seq = 11274 bp->fw_seq =
11275 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 11275 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11276 DRV_MSG_SEQ_NUMBER_MASK); 11276 DRV_MSG_SEQ_NUMBER_MASK);
11277 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 11277 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11278 } 11278 }
11279 } 11279 }
11280 11280
11281 /** 11281 /**
11282 * bnx2x_io_error_detected - called when PCI error is detected 11282 * bnx2x_io_error_detected - called when PCI error is detected
11283 * @pdev: Pointer to PCI device 11283 * @pdev: Pointer to PCI device
11284 * @state: The current pci connection state 11284 * @state: The current pci connection state
11285 * 11285 *
11286 * This function is called after a PCI bus error affecting 11286 * This function is called after a PCI bus error affecting
11287 * this device has been detected. 11287 * this device has been detected.
11288 */ 11288 */
11289 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 11289 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
11290 pci_channel_state_t state) 11290 pci_channel_state_t state)
11291 { 11291 {
11292 struct net_device *dev = pci_get_drvdata(pdev); 11292 struct net_device *dev = pci_get_drvdata(pdev);
11293 struct bnx2x *bp = netdev_priv(dev); 11293 struct bnx2x *bp = netdev_priv(dev);
11294 11294
11295 rtnl_lock(); 11295 rtnl_lock();
11296 11296
11297 netif_device_detach(dev); 11297 netif_device_detach(dev);
11298 11298
11299 if (state == pci_channel_io_perm_failure) { 11299 if (state == pci_channel_io_perm_failure) {
11300 rtnl_unlock(); 11300 rtnl_unlock();
11301 return PCI_ERS_RESULT_DISCONNECT; 11301 return PCI_ERS_RESULT_DISCONNECT;
11302 } 11302 }
11303 11303
11304 if (netif_running(dev)) 11304 if (netif_running(dev))
11305 bnx2x_eeh_nic_unload(bp); 11305 bnx2x_eeh_nic_unload(bp);
11306 11306
11307 pci_disable_device(pdev); 11307 pci_disable_device(pdev);
11308 11308
11309 rtnl_unlock(); 11309 rtnl_unlock();
11310 11310
11311 /* Request a slot reset */ 11311 /* Request a slot reset */
11312 return PCI_ERS_RESULT_NEED_RESET; 11312 return PCI_ERS_RESULT_NEED_RESET;
11313 } 11313 }
11314 11314
11315 /** 11315 /**
11316 * bnx2x_io_slot_reset - called after the PCI bus has been reset 11316 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11317 * @pdev: Pointer to PCI device 11317 * @pdev: Pointer to PCI device
11318 * 11318 *
11319 * Restart the card from scratch, as if from a cold-boot. 11319 * Restart the card from scratch, as if from a cold-boot.
11320 */ 11320 */
11321 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 11321 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11322 { 11322 {
11323 struct net_device *dev = pci_get_drvdata(pdev); 11323 struct net_device *dev = pci_get_drvdata(pdev);
11324 struct bnx2x *bp = netdev_priv(dev); 11324 struct bnx2x *bp = netdev_priv(dev);
11325 11325
11326 rtnl_lock(); 11326 rtnl_lock();
11327 11327
11328 if (pci_enable_device(pdev)) { 11328 if (pci_enable_device(pdev)) {
11329 dev_err(&pdev->dev, 11329 dev_err(&pdev->dev,
11330 "Cannot re-enable PCI device after reset\n"); 11330 "Cannot re-enable PCI device after reset\n");
11331 rtnl_unlock(); 11331 rtnl_unlock();
11332 return PCI_ERS_RESULT_DISCONNECT; 11332 return PCI_ERS_RESULT_DISCONNECT;
11333 } 11333 }
11334 11334
11335 pci_set_master(pdev); 11335 pci_set_master(pdev);
11336 pci_restore_state(pdev); 11336 pci_restore_state(pdev);
11337 11337
11338 if (netif_running(dev)) 11338 if (netif_running(dev))
11339 bnx2x_set_power_state(bp, PCI_D0); 11339 bnx2x_set_power_state(bp, PCI_D0);
11340 11340
11341 rtnl_unlock(); 11341 rtnl_unlock();
11342 11342
11343 return PCI_ERS_RESULT_RECOVERED; 11343 return PCI_ERS_RESULT_RECOVERED;
11344 } 11344 }
11345 11345
11346 /** 11346 /**
11347 * bnx2x_io_resume - called when traffic can start flowing again 11347 * bnx2x_io_resume - called when traffic can start flowing again
11348 * @pdev: Pointer to PCI device 11348 * @pdev: Pointer to PCI device
11349 * 11349 *
11350 * This callback is called when the error recovery driver tells us that 11350 * This callback is called when the error recovery driver tells us that
11351 * its OK to resume normal operation. 11351 * its OK to resume normal operation.
11352 */ 11352 */
11353 static void bnx2x_io_resume(struct pci_dev *pdev) 11353 static void bnx2x_io_resume(struct pci_dev *pdev)
11354 { 11354 {
11355 struct net_device *dev = pci_get_drvdata(pdev); 11355 struct net_device *dev = pci_get_drvdata(pdev);
11356 struct bnx2x *bp = netdev_priv(dev); 11356 struct bnx2x *bp = netdev_priv(dev);
11357 11357
11358 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11358 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
11359 netdev_err(bp->dev, "Handling parity error recovery. " 11359 netdev_err(bp->dev, "Handling parity error recovery. "
11360 "Try again later\n"); 11360 "Try again later\n");
11361 return; 11361 return;
11362 } 11362 }
11363 11363
11364 rtnl_lock(); 11364 rtnl_lock();
11365 11365
11366 bnx2x_eeh_recover(bp); 11366 bnx2x_eeh_recover(bp);
11367 11367
11368 if (netif_running(dev)) 11368 if (netif_running(dev))
11369 bnx2x_nic_load(bp, LOAD_NORMAL); 11369 bnx2x_nic_load(bp, LOAD_NORMAL);
11370 11370
11371 netif_device_attach(dev); 11371 netif_device_attach(dev);
11372 11372
11373 rtnl_unlock(); 11373 rtnl_unlock();
11374 } 11374 }
11375 11375
11376 static struct pci_error_handlers bnx2x_err_handler = { 11376 static struct pci_error_handlers bnx2x_err_handler = {
11377 .error_detected = bnx2x_io_error_detected, 11377 .error_detected = bnx2x_io_error_detected,
11378 .slot_reset = bnx2x_io_slot_reset, 11378 .slot_reset = bnx2x_io_slot_reset,
11379 .resume = bnx2x_io_resume, 11379 .resume = bnx2x_io_resume,
11380 }; 11380 };
11381 11381
11382 static struct pci_driver bnx2x_pci_driver = { 11382 static struct pci_driver bnx2x_pci_driver = {
11383 .name = DRV_MODULE_NAME, 11383 .name = DRV_MODULE_NAME,
11384 .id_table = bnx2x_pci_tbl, 11384 .id_table = bnx2x_pci_tbl,
11385 .probe = bnx2x_init_one, 11385 .probe = bnx2x_init_one,
11386 .remove = __devexit_p(bnx2x_remove_one), 11386 .remove = __devexit_p(bnx2x_remove_one),
11387 .suspend = bnx2x_suspend, 11387 .suspend = bnx2x_suspend,
11388 .resume = bnx2x_resume, 11388 .resume = bnx2x_resume,
11389 .err_handler = &bnx2x_err_handler, 11389 .err_handler = &bnx2x_err_handler,
11390 }; 11390 };
11391 11391
11392 static int __init bnx2x_init(void) 11392 static int __init bnx2x_init(void)
11393 { 11393 {
11394 int ret; 11394 int ret;
11395 11395
11396 pr_info("%s", version); 11396 pr_info("%s", version);
11397 11397
11398 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 11398 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11399 if (bnx2x_wq == NULL) { 11399 if (bnx2x_wq == NULL) {
11400 pr_err("Cannot create workqueue\n"); 11400 pr_err("Cannot create workqueue\n");
11401 return -ENOMEM; 11401 return -ENOMEM;
11402 } 11402 }
11403 11403
11404 ret = pci_register_driver(&bnx2x_pci_driver); 11404 ret = pci_register_driver(&bnx2x_pci_driver);
11405 if (ret) { 11405 if (ret) {
11406 pr_err("Cannot register driver\n"); 11406 pr_err("Cannot register driver\n");
11407 destroy_workqueue(bnx2x_wq); 11407 destroy_workqueue(bnx2x_wq);
11408 } 11408 }
11409 return ret; 11409 return ret;
11410 } 11410 }
11411 11411
11412 static void __exit bnx2x_cleanup(void) 11412 static void __exit bnx2x_cleanup(void)
11413 { 11413 {
11414 pci_unregister_driver(&bnx2x_pci_driver); 11414 pci_unregister_driver(&bnx2x_pci_driver);
11415 11415
11416 destroy_workqueue(bnx2x_wq); 11416 destroy_workqueue(bnx2x_wq);
11417 } 11417 }
11418 11418
11419 void bnx2x_notify_link_changed(struct bnx2x *bp) 11419 void bnx2x_notify_link_changed(struct bnx2x *bp)
11420 { 11420 {
11421 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 11421 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11422 } 11422 }
11423 11423
11424 module_init(bnx2x_init); 11424 module_init(bnx2x_init);
11425 module_exit(bnx2x_cleanup); 11425 module_exit(bnx2x_cleanup);
11426 11426
11427 #ifdef BCM_CNIC 11427 #ifdef BCM_CNIC
11428 /** 11428 /**
11429 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 11429 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11430 * 11430 *
11431 * @bp: driver handle 11431 * @bp: driver handle
11432 * @set: set or clear the CAM entry 11432 * @set: set or clear the CAM entry
11433 * 11433 *
11434 * This function will wait until the ramdord completion returns. 11434 * This function will wait until the ramdord completion returns.
11435 * Return 0 if success, -ENODEV if ramrod doesn't return. 11435 * Return 0 if success, -ENODEV if ramrod doesn't return.
11436 */ 11436 */
11437 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 11437 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11438 { 11438 {
11439 unsigned long ramrod_flags = 0; 11439 unsigned long ramrod_flags = 0;
11440 11440
11441 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11441 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11442 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 11442 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11443 &bp->iscsi_l2_mac_obj, true, 11443 &bp->iscsi_l2_mac_obj, true,
11444 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 11444 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11445 } 11445 }
11446 11446
11447 /* count denotes the number of new completions we have seen */ 11447 /* count denotes the number of new completions we have seen */
11448 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 11448 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11449 { 11449 {
11450 struct eth_spe *spe; 11450 struct eth_spe *spe;
11451 11451
11452 #ifdef BNX2X_STOP_ON_ERROR 11452 #ifdef BNX2X_STOP_ON_ERROR
11453 if (unlikely(bp->panic)) 11453 if (unlikely(bp->panic))
11454 return; 11454 return;
11455 #endif 11455 #endif
11456 11456
11457 spin_lock_bh(&bp->spq_lock); 11457 spin_lock_bh(&bp->spq_lock);
11458 BUG_ON(bp->cnic_spq_pending < count); 11458 BUG_ON(bp->cnic_spq_pending < count);
11459 bp->cnic_spq_pending -= count; 11459 bp->cnic_spq_pending -= count;
11460 11460
11461 11461
11462 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 11462 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11463 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 11463 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11464 & SPE_HDR_CONN_TYPE) >> 11464 & SPE_HDR_CONN_TYPE) >>
11465 SPE_HDR_CONN_TYPE_SHIFT; 11465 SPE_HDR_CONN_TYPE_SHIFT;
11466 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 11466 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11467 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 11467 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
11468 11468
11469 /* Set validation for iSCSI L2 client before sending SETUP 11469 /* Set validation for iSCSI L2 client before sending SETUP
11470 * ramrod 11470 * ramrod
11471 */ 11471 */
11472 if (type == ETH_CONNECTION_TYPE) { 11472 if (type == ETH_CONNECTION_TYPE) {
11473 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) 11473 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
11474 bnx2x_set_ctx_validation(bp, &bp->context. 11474 bnx2x_set_ctx_validation(bp, &bp->context.
11475 vcxt[BNX2X_ISCSI_ETH_CID].eth, 11475 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11476 BNX2X_ISCSI_ETH_CID); 11476 BNX2X_ISCSI_ETH_CID);
11477 } 11477 }
11478 11478
11479 /* 11479 /*
11480 * There may be not more than 8 L2, not more than 8 L5 SPEs 11480 * There may be not more than 8 L2, not more than 8 L5 SPEs
11481 * and in the air. We also check that number of outstanding 11481 * and in the air. We also check that number of outstanding
11482 * COMMON ramrods is not more than the EQ and SPQ can 11482 * COMMON ramrods is not more than the EQ and SPQ can
11483 * accommodate. 11483 * accommodate.
11484 */ 11484 */
11485 if (type == ETH_CONNECTION_TYPE) { 11485 if (type == ETH_CONNECTION_TYPE) {
11486 if (!atomic_read(&bp->cq_spq_left)) 11486 if (!atomic_read(&bp->cq_spq_left))
11487 break; 11487 break;
11488 else 11488 else
11489 atomic_dec(&bp->cq_spq_left); 11489 atomic_dec(&bp->cq_spq_left);
11490 } else if (type == NONE_CONNECTION_TYPE) { 11490 } else if (type == NONE_CONNECTION_TYPE) {
11491 if (!atomic_read(&bp->eq_spq_left)) 11491 if (!atomic_read(&bp->eq_spq_left))
11492 break; 11492 break;
11493 else 11493 else
11494 atomic_dec(&bp->eq_spq_left); 11494 atomic_dec(&bp->eq_spq_left);
11495 } else if ((type == ISCSI_CONNECTION_TYPE) || 11495 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11496 (type == FCOE_CONNECTION_TYPE)) { 11496 (type == FCOE_CONNECTION_TYPE)) {
11497 if (bp->cnic_spq_pending >= 11497 if (bp->cnic_spq_pending >=
11498 bp->cnic_eth_dev.max_kwqe_pending) 11498 bp->cnic_eth_dev.max_kwqe_pending)
11499 break; 11499 break;
11500 else 11500 else
11501 bp->cnic_spq_pending++; 11501 bp->cnic_spq_pending++;
11502 } else { 11502 } else {
11503 BNX2X_ERR("Unknown SPE type: %d\n", type); 11503 BNX2X_ERR("Unknown SPE type: %d\n", type);
11504 bnx2x_panic(); 11504 bnx2x_panic();
11505 break; 11505 break;
11506 } 11506 }
11507 11507
11508 spe = bnx2x_sp_get_next(bp); 11508 spe = bnx2x_sp_get_next(bp);
11509 *spe = *bp->cnic_kwq_cons; 11509 *spe = *bp->cnic_kwq_cons;
11510 11510
11511 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", 11511 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11512 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11512 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11513 11513
11514 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11514 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11515 bp->cnic_kwq_cons = bp->cnic_kwq; 11515 bp->cnic_kwq_cons = bp->cnic_kwq;
11516 else 11516 else
11517 bp->cnic_kwq_cons++; 11517 bp->cnic_kwq_cons++;
11518 } 11518 }
11519 bnx2x_sp_prod_update(bp); 11519 bnx2x_sp_prod_update(bp);
11520 spin_unlock_bh(&bp->spq_lock); 11520 spin_unlock_bh(&bp->spq_lock);
11521 } 11521 }
11522 11522
11523 static int bnx2x_cnic_sp_queue(struct net_device *dev, 11523 static int bnx2x_cnic_sp_queue(struct net_device *dev,
11524 struct kwqe_16 *kwqes[], u32 count) 11524 struct kwqe_16 *kwqes[], u32 count)
11525 { 11525 {
11526 struct bnx2x *bp = netdev_priv(dev); 11526 struct bnx2x *bp = netdev_priv(dev);
11527 int i; 11527 int i;
11528 11528
11529 #ifdef BNX2X_STOP_ON_ERROR 11529 #ifdef BNX2X_STOP_ON_ERROR
11530 if (unlikely(bp->panic)) 11530 if (unlikely(bp->panic))
11531 return -EIO; 11531 return -EIO;
11532 #endif 11532 #endif
11533 11533
11534 spin_lock_bh(&bp->spq_lock); 11534 spin_lock_bh(&bp->spq_lock);
11535 11535
11536 for (i = 0; i < count; i++) { 11536 for (i = 0; i < count; i++) {
11537 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 11537 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11538 11538
11539 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 11539 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11540 break; 11540 break;
11541 11541
11542 *bp->cnic_kwq_prod = *spe; 11542 *bp->cnic_kwq_prod = *spe;
11543 11543
11544 bp->cnic_kwq_pending++; 11544 bp->cnic_kwq_pending++;
11545 11545
11546 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", 11546 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11547 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11547 spe->hdr.conn_and_cmd_data, spe->hdr.type,
11548 spe->data.update_data_addr.hi, 11548 spe->data.update_data_addr.hi,
11549 spe->data.update_data_addr.lo, 11549 spe->data.update_data_addr.lo,
11550 bp->cnic_kwq_pending); 11550 bp->cnic_kwq_pending);
11551 11551
11552 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 11552 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11553 bp->cnic_kwq_prod = bp->cnic_kwq; 11553 bp->cnic_kwq_prod = bp->cnic_kwq;
11554 else 11554 else
11555 bp->cnic_kwq_prod++; 11555 bp->cnic_kwq_prod++;
11556 } 11556 }
11557 11557
11558 spin_unlock_bh(&bp->spq_lock); 11558 spin_unlock_bh(&bp->spq_lock);
11559 11559
11560 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 11560 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11561 bnx2x_cnic_sp_post(bp, 0); 11561 bnx2x_cnic_sp_post(bp, 0);
11562 11562
11563 return i; 11563 return i;
11564 } 11564 }
11565 11565
11566 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11566 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11567 { 11567 {
11568 struct cnic_ops *c_ops; 11568 struct cnic_ops *c_ops;
11569 int rc = 0; 11569 int rc = 0;
11570 11570
11571 mutex_lock(&bp->cnic_mutex); 11571 mutex_lock(&bp->cnic_mutex);
11572 c_ops = rcu_dereference_protected(bp->cnic_ops, 11572 c_ops = rcu_dereference_protected(bp->cnic_ops,
11573 lockdep_is_held(&bp->cnic_mutex)); 11573 lockdep_is_held(&bp->cnic_mutex));
11574 if (c_ops) 11574 if (c_ops)
11575 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11575 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11576 mutex_unlock(&bp->cnic_mutex); 11576 mutex_unlock(&bp->cnic_mutex);
11577 11577
11578 return rc; 11578 return rc;
11579 } 11579 }
11580 11580
11581 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11581 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11582 { 11582 {
11583 struct cnic_ops *c_ops; 11583 struct cnic_ops *c_ops;
11584 int rc = 0; 11584 int rc = 0;
11585 11585
11586 rcu_read_lock(); 11586 rcu_read_lock();
11587 c_ops = rcu_dereference(bp->cnic_ops); 11587 c_ops = rcu_dereference(bp->cnic_ops);
11588 if (c_ops) 11588 if (c_ops)
11589 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11589 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11590 rcu_read_unlock(); 11590 rcu_read_unlock();
11591 11591
11592 return rc; 11592 return rc;
11593 } 11593 }
11594 11594
11595 /* 11595 /*
11596 * for commands that have no data 11596 * for commands that have no data
11597 */ 11597 */
11598 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 11598 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
11599 { 11599 {
11600 struct cnic_ctl_info ctl = {0}; 11600 struct cnic_ctl_info ctl = {0};
11601 11601
11602 ctl.cmd = cmd; 11602 ctl.cmd = cmd;
11603 11603
11604 return bnx2x_cnic_ctl_send(bp, &ctl); 11604 return bnx2x_cnic_ctl_send(bp, &ctl);
11605 } 11605 }
11606 11606
11607 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 11607 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
11608 { 11608 {
11609 struct cnic_ctl_info ctl = {0}; 11609 struct cnic_ctl_info ctl = {0};
11610 11610
11611 /* first we tell CNIC and only then we count this as a completion */ 11611 /* first we tell CNIC and only then we count this as a completion */
11612 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 11612 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11613 ctl.data.comp.cid = cid; 11613 ctl.data.comp.cid = cid;
11614 ctl.data.comp.error = err; 11614 ctl.data.comp.error = err;
11615 11615
11616 bnx2x_cnic_ctl_send_bh(bp, &ctl); 11616 bnx2x_cnic_ctl_send_bh(bp, &ctl);
11617 bnx2x_cnic_sp_post(bp, 0); 11617 bnx2x_cnic_sp_post(bp, 0);
11618 } 11618 }
11619 11619
11620 11620
11621 /* Called with netif_addr_lock_bh() taken. 11621 /* Called with netif_addr_lock_bh() taken.
11622 * Sets an rx_mode config for an iSCSI ETH client. 11622 * Sets an rx_mode config for an iSCSI ETH client.
11623 * Doesn't block. 11623 * Doesn't block.
11624 * Completion should be checked outside. 11624 * Completion should be checked outside.
11625 */ 11625 */
11626 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 11626 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11627 { 11627 {
11628 unsigned long accept_flags = 0, ramrod_flags = 0; 11628 unsigned long accept_flags = 0, ramrod_flags = 0;
11629 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11629 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11630 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 11630 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11631 11631
11632 if (start) { 11632 if (start) {
11633 /* Start accepting on iSCSI L2 ring. Accept all multicasts 11633 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11634 * because it's the only way for UIO Queue to accept 11634 * because it's the only way for UIO Queue to accept
11635 * multicasts (in non-promiscuous mode only one Queue per 11635 * multicasts (in non-promiscuous mode only one Queue per
11636 * function will receive multicast packets (leading in our 11636 * function will receive multicast packets (leading in our
11637 * case). 11637 * case).
11638 */ 11638 */
11639 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 11639 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11640 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 11640 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11641 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 11641 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11642 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 11642 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11643 11643
11644 /* Clear STOP_PENDING bit if START is requested */ 11644 /* Clear STOP_PENDING bit if START is requested */
11645 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 11645 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11646 11646
11647 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 11647 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11648 } else 11648 } else
11649 /* Clear START_PENDING bit if STOP is requested */ 11649 /* Clear START_PENDING bit if STOP is requested */
11650 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 11650 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11651 11651
11652 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 11652 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11653 set_bit(sched_state, &bp->sp_state); 11653 set_bit(sched_state, &bp->sp_state);
11654 else { 11654 else {
11655 __set_bit(RAMROD_RX, &ramrod_flags); 11655 __set_bit(RAMROD_RX, &ramrod_flags);
11656 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 11656 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11657 ramrod_flags); 11657 ramrod_flags);
11658 } 11658 }
11659 } 11659 }
11660 11660
11661 11661
11662 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 11662 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11663 { 11663 {
11664 struct bnx2x *bp = netdev_priv(dev); 11664 struct bnx2x *bp = netdev_priv(dev);
11665 int rc = 0; 11665 int rc = 0;
11666 11666
11667 switch (ctl->cmd) { 11667 switch (ctl->cmd) {
11668 case DRV_CTL_CTXTBL_WR_CMD: { 11668 case DRV_CTL_CTXTBL_WR_CMD: {
11669 u32 index = ctl->data.io.offset; 11669 u32 index = ctl->data.io.offset;
11670 dma_addr_t addr = ctl->data.io.dma_addr; 11670 dma_addr_t addr = ctl->data.io.dma_addr;
11671 11671
11672 bnx2x_ilt_wr(bp, index, addr); 11672 bnx2x_ilt_wr(bp, index, addr);
11673 break; 11673 break;
11674 } 11674 }
11675 11675
11676 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 11676 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11677 int count = ctl->data.credit.credit_count; 11677 int count = ctl->data.credit.credit_count;
11678 11678
11679 bnx2x_cnic_sp_post(bp, count); 11679 bnx2x_cnic_sp_post(bp, count);
11680 break; 11680 break;
11681 } 11681 }
11682 11682
11683 /* rtnl_lock is held. */ 11683 /* rtnl_lock is held. */
11684 case DRV_CTL_START_L2_CMD: { 11684 case DRV_CTL_START_L2_CMD: {
11685 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11685 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11686 unsigned long sp_bits = 0; 11686 unsigned long sp_bits = 0;
11687 11687
11688 /* Configure the iSCSI classification object */ 11688 /* Configure the iSCSI classification object */
11689 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 11689 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11690 cp->iscsi_l2_client_id, 11690 cp->iscsi_l2_client_id,
11691 cp->iscsi_l2_cid, BP_FUNC(bp), 11691 cp->iscsi_l2_cid, BP_FUNC(bp),
11692 bnx2x_sp(bp, mac_rdata), 11692 bnx2x_sp(bp, mac_rdata),
11693 bnx2x_sp_mapping(bp, mac_rdata), 11693 bnx2x_sp_mapping(bp, mac_rdata),
11694 BNX2X_FILTER_MAC_PENDING, 11694 BNX2X_FILTER_MAC_PENDING,
11695 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 11695 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11696 &bp->macs_pool); 11696 &bp->macs_pool);
11697 11697
11698 /* Set iSCSI MAC address */ 11698 /* Set iSCSI MAC address */
11699 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 11699 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11700 if (rc) 11700 if (rc)
11701 break; 11701 break;
11702 11702
11703 mmiowb(); 11703 mmiowb();
11704 barrier(); 11704 barrier();
11705 11705
11706 /* Start accepting on iSCSI L2 ring */ 11706 /* Start accepting on iSCSI L2 ring */
11707 11707
11708 netif_addr_lock_bh(dev); 11708 netif_addr_lock_bh(dev);
11709 bnx2x_set_iscsi_eth_rx_mode(bp, true); 11709 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11710 netif_addr_unlock_bh(dev); 11710 netif_addr_unlock_bh(dev);
11711 11711
11712 /* bits to wait on */ 11712 /* bits to wait on */
11713 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11713 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11714 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 11714 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11715 11715
11716 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11716 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11717 BNX2X_ERR("rx_mode completion timed out!\n"); 11717 BNX2X_ERR("rx_mode completion timed out!\n");
11718 11718
11719 break; 11719 break;
11720 } 11720 }
11721 11721
11722 /* rtnl_lock is held. */ 11722 /* rtnl_lock is held. */
11723 case DRV_CTL_STOP_L2_CMD: { 11723 case DRV_CTL_STOP_L2_CMD: {
11724 unsigned long sp_bits = 0; 11724 unsigned long sp_bits = 0;
11725 11725
11726 /* Stop accepting on iSCSI L2 ring */ 11726 /* Stop accepting on iSCSI L2 ring */
11727 netif_addr_lock_bh(dev); 11727 netif_addr_lock_bh(dev);
11728 bnx2x_set_iscsi_eth_rx_mode(bp, false); 11728 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11729 netif_addr_unlock_bh(dev); 11729 netif_addr_unlock_bh(dev);
11730 11730
11731 /* bits to wait on */ 11731 /* bits to wait on */
11732 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11732 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11733 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 11733 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11734 11734
11735 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11735 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11736 BNX2X_ERR("rx_mode completion timed out!\n"); 11736 BNX2X_ERR("rx_mode completion timed out!\n");
11737 11737
11738 mmiowb(); 11738 mmiowb();
11739 barrier(); 11739 barrier();
11740 11740
11741 /* Unset iSCSI L2 MAC */ 11741 /* Unset iSCSI L2 MAC */
11742 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 11742 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11743 BNX2X_ISCSI_ETH_MAC, true); 11743 BNX2X_ISCSI_ETH_MAC, true);
11744 break; 11744 break;
11745 } 11745 }
11746 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 11746 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11747 int count = ctl->data.credit.credit_count; 11747 int count = ctl->data.credit.credit_count;
11748 11748
11749 smp_mb__before_atomic_inc(); 11749 smp_mb__before_atomic_inc();
11750 atomic_add(count, &bp->cq_spq_left); 11750 atomic_add(count, &bp->cq_spq_left);
11751 smp_mb__after_atomic_inc(); 11751 smp_mb__after_atomic_inc();
11752 break; 11752 break;
11753 } 11753 }
11754 case DRV_CTL_ULP_REGISTER_CMD: { 11754 case DRV_CTL_ULP_REGISTER_CMD: {
11755 int ulp_type = ctl->data.ulp_type; 11755 int ulp_type = ctl->data.ulp_type;
11756 11756
11757 if (CHIP_IS_E3(bp)) { 11757 if (CHIP_IS_E3(bp)) {
11758 int idx = BP_FW_MB_IDX(bp); 11758 int idx = BP_FW_MB_IDX(bp);
11759 u32 cap; 11759 u32 cap;
11760 11760
11761 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11761 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
11762 if (ulp_type == CNIC_ULP_ISCSI) 11762 if (ulp_type == CNIC_ULP_ISCSI)
11763 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11763 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
11764 else if (ulp_type == CNIC_ULP_FCOE) 11764 else if (ulp_type == CNIC_ULP_FCOE)
11765 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11765 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
11766 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11766 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
11767 } 11767 }
11768 break; 11768 break;
11769 } 11769 }
11770 case DRV_CTL_ULP_UNREGISTER_CMD: { 11770 case DRV_CTL_ULP_UNREGISTER_CMD: {
11771 int ulp_type = ctl->data.ulp_type; 11771 int ulp_type = ctl->data.ulp_type;
11772 11772
11773 if (CHIP_IS_E3(bp)) { 11773 if (CHIP_IS_E3(bp)) {
11774 int idx = BP_FW_MB_IDX(bp); 11774 int idx = BP_FW_MB_IDX(bp);
11775 u32 cap; 11775 u32 cap;
11776 11776
11777 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11777 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
11778 if (ulp_type == CNIC_ULP_ISCSI) 11778 if (ulp_type == CNIC_ULP_ISCSI)
11779 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11779 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
11780 else if (ulp_type == CNIC_ULP_FCOE) 11780 else if (ulp_type == CNIC_ULP_FCOE)
11781 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11781 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
11782 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11782 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
11783 } 11783 }
11784 break; 11784 break;
11785 } 11785 }
11786 11786
11787 default: 11787 default:
11788 BNX2X_ERR("unknown command %x\n", ctl->cmd); 11788 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11789 rc = -EINVAL; 11789 rc = -EINVAL;
11790 } 11790 }
11791 11791
11792 return rc; 11792 return rc;
11793 } 11793 }
11794 11794
11795 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 11795 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
11796 { 11796 {
11797 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11797 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11798 11798
11799 if (bp->flags & USING_MSIX_FLAG) { 11799 if (bp->flags & USING_MSIX_FLAG) {
11800 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 11800 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11801 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 11801 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11802 cp->irq_arr[0].vector = bp->msix_table[1].vector; 11802 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11803 } else { 11803 } else {
11804 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 11804 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11805 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 11805 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11806 } 11806 }
11807 if (!CHIP_IS_E1x(bp)) 11807 if (!CHIP_IS_E1x(bp))
11808 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 11808 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11809 else 11809 else
11810 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 11810 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11811 11811
11812 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 11812 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11813 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 11813 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
11814 cp->irq_arr[1].status_blk = bp->def_status_blk; 11814 cp->irq_arr[1].status_blk = bp->def_status_blk;
11815 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 11815 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
11816 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 11816 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
11817 11817
11818 cp->num_irq = 2; 11818 cp->num_irq = 2;
11819 } 11819 }
11820 11820
11821 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 11821 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11822 void *data) 11822 void *data)
11823 { 11823 {
11824 struct bnx2x *bp = netdev_priv(dev); 11824 struct bnx2x *bp = netdev_priv(dev);
11825 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11825 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11826 11826
11827 if (ops == NULL) 11827 if (ops == NULL)
11828 return -EINVAL; 11828 return -EINVAL;
11829 11829
11830 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 11830 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11831 if (!bp->cnic_kwq) 11831 if (!bp->cnic_kwq)
11832 return -ENOMEM; 11832 return -ENOMEM;
11833 11833
11834 bp->cnic_kwq_cons = bp->cnic_kwq; 11834 bp->cnic_kwq_cons = bp->cnic_kwq;
11835 bp->cnic_kwq_prod = bp->cnic_kwq; 11835 bp->cnic_kwq_prod = bp->cnic_kwq;
11836 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 11836 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11837 11837
11838 bp->cnic_spq_pending = 0; 11838 bp->cnic_spq_pending = 0;
11839 bp->cnic_kwq_pending = 0; 11839 bp->cnic_kwq_pending = 0;
11840 11840
11841 bp->cnic_data = data; 11841 bp->cnic_data = data;
11842 11842
11843 cp->num_irq = 0; 11843 cp->num_irq = 0;
11844 cp->drv_state |= CNIC_DRV_STATE_REGD; 11844 cp->drv_state |= CNIC_DRV_STATE_REGD;
11845 cp->iro_arr = bp->iro_arr; 11845 cp->iro_arr = bp->iro_arr;
11846 11846
11847 bnx2x_setup_cnic_irq_info(bp); 11847 bnx2x_setup_cnic_irq_info(bp);
11848 11848
11849 rcu_assign_pointer(bp->cnic_ops, ops); 11849 rcu_assign_pointer(bp->cnic_ops, ops);
11850 11850
11851 return 0; 11851 return 0;
11852 } 11852 }
11853 11853
11854 static int bnx2x_unregister_cnic(struct net_device *dev) 11854 static int bnx2x_unregister_cnic(struct net_device *dev)
11855 { 11855 {
11856 struct bnx2x *bp = netdev_priv(dev); 11856 struct bnx2x *bp = netdev_priv(dev);
11857 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11857 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11858 11858
11859 mutex_lock(&bp->cnic_mutex); 11859 mutex_lock(&bp->cnic_mutex);
11860 cp->drv_state = 0; 11860 cp->drv_state = 0;
11861 RCU_INIT_POINTER(bp->cnic_ops, NULL); 11861 RCU_INIT_POINTER(bp->cnic_ops, NULL);
11862 mutex_unlock(&bp->cnic_mutex); 11862 mutex_unlock(&bp->cnic_mutex);
11863 synchronize_rcu(); 11863 synchronize_rcu();
11864 kfree(bp->cnic_kwq); 11864 kfree(bp->cnic_kwq);
11865 bp->cnic_kwq = NULL; 11865 bp->cnic_kwq = NULL;
11866 11866
11867 return 0; 11867 return 0;
11868 } 11868 }
11869 11869
11870 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 11870 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11871 { 11871 {
11872 struct bnx2x *bp = netdev_priv(dev); 11872 struct bnx2x *bp = netdev_priv(dev);
11873 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11873 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11874 11874
11875 /* If both iSCSI and FCoE are disabled - return NULL in 11875 /* If both iSCSI and FCoE are disabled - return NULL in
11876 * order to indicate CNIC that it should not try to work 11876 * order to indicate CNIC that it should not try to work
11877 * with this device. 11877 * with this device.
11878 */ 11878 */
11879 if (NO_ISCSI(bp) && NO_FCOE(bp)) 11879 if (NO_ISCSI(bp) && NO_FCOE(bp))
11880 return NULL; 11880 return NULL;
11881 11881
11882 cp->drv_owner = THIS_MODULE; 11882 cp->drv_owner = THIS_MODULE;
11883 cp->chip_id = CHIP_ID(bp); 11883 cp->chip_id = CHIP_ID(bp);
11884 cp->pdev = bp->pdev; 11884 cp->pdev = bp->pdev;
11885 cp->io_base = bp->regview; 11885 cp->io_base = bp->regview;
11886 cp->io_base2 = bp->doorbells; 11886 cp->io_base2 = bp->doorbells;
11887 cp->max_kwqe_pending = 8; 11887 cp->max_kwqe_pending = 8;
11888 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 11888 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
11889 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 11889 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11890 bnx2x_cid_ilt_lines(bp); 11890 bnx2x_cid_ilt_lines(bp);
11891 cp->ctx_tbl_len = CNIC_ILT_LINES; 11891 cp->ctx_tbl_len = CNIC_ILT_LINES;
11892 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 11892 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
11893 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 11893 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11894 cp->drv_ctl = bnx2x_drv_ctl; 11894 cp->drv_ctl = bnx2x_drv_ctl;
11895 cp->drv_register_cnic = bnx2x_register_cnic; 11895 cp->drv_register_cnic = bnx2x_register_cnic;
11896 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 11896 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
11897 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; 11897 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
11898 cp->iscsi_l2_client_id = 11898 cp->iscsi_l2_client_id =
11899 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11899 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11900 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; 11900 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11901 11901
11902 if (NO_ISCSI_OOO(bp)) 11902 if (NO_ISCSI_OOO(bp))
11903 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 11903 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11904 11904
11905 if (NO_ISCSI(bp)) 11905 if (NO_ISCSI(bp))
11906 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 11906 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11907 11907
11908 if (NO_FCOE(bp)) 11908 if (NO_FCOE(bp))
11909 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 11909 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11910 11910
11911 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " 11911 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11912 "starting cid %d\n", 11912 "starting cid %d\n",
11913 cp->ctx_blk_size, 11913 cp->ctx_blk_size,
11914 cp->ctx_tbl_offset, 11914 cp->ctx_tbl_offset,
11915 cp->ctx_tbl_len, 11915 cp->ctx_tbl_len,
11916 cp->starting_cid); 11916 cp->starting_cid);
11917 return cp; 11917 return cp;
11918 } 11918 }
11919 EXPORT_SYMBOL(bnx2x_cnic_probe); 11919 EXPORT_SYMBOL(bnx2x_cnic_probe);
11920 11920
11921 #endif /* BCM_CNIC */ 11921 #endif /* BCM_CNIC */
11922 11922
11923 11923