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Commit f90f54b3f3c4d1c9168d5f8e97c6ac5b9ad25f5e

Authored by Bill Pemberton
Committed by Greg Kroah-Hartman
1 parent 84db00ba1e
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

pinctrl: remove use of __devexit 

CONFIG_HOTPLUG is going away as an option so __devexit is no
longer needed.

Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Showing 16 changed files with 16 additions and 16 deletions Inline Diff

drivers/pinctrl/pinctrl-bcm2835.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO) 2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
3 * 3 *
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren 4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
5 * 5 *
6 * This driver is inspired by: 6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information 7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information 8 * pinctrl-tegra.c, please see original file for copyright information
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or 12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version. 13 * (at your option) any later version.
14 * 14 *
15 * This program is distributed in the hope that it will be useful, 15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details. 18 * GNU General Public License for more details.
19 */ 19 */
20 20
21 #include <linux/bitmap.h> 21 #include <linux/bitmap.h>
22 #include <linux/bug.h> 22 #include <linux/bug.h>
23 #include <linux/delay.h> 23 #include <linux/delay.h>
24 #include <linux/device.h> 24 #include <linux/device.h>
25 #include <linux/err.h> 25 #include <linux/err.h>
26 #include <linux/gpio.h> 26 #include <linux/gpio.h>
27 #include <linux/interrupt.h> 27 #include <linux/interrupt.h>
28 #include <linux/io.h> 28 #include <linux/io.h>
29 #include <linux/irq.h> 29 #include <linux/irq.h>
30 #include <linux/irqdesc.h> 30 #include <linux/irqdesc.h>
31 #include <linux/irqdomain.h> 31 #include <linux/irqdomain.h>
32 #include <linux/module.h> 32 #include <linux/module.h>
33 #include <linux/of_address.h> 33 #include <linux/of_address.h>
34 #include <linux/of.h> 34 #include <linux/of.h>
35 #include <linux/of_irq.h> 35 #include <linux/of_irq.h>
36 #include <linux/pinctrl/consumer.h> 36 #include <linux/pinctrl/consumer.h>
37 #include <linux/pinctrl/machine.h> 37 #include <linux/pinctrl/machine.h>
38 #include <linux/pinctrl/pinconf.h> 38 #include <linux/pinctrl/pinconf.h>
39 #include <linux/pinctrl/pinctrl.h> 39 #include <linux/pinctrl/pinctrl.h>
40 #include <linux/pinctrl/pinmux.h> 40 #include <linux/pinctrl/pinmux.h>
41 #include <linux/platform_device.h> 41 #include <linux/platform_device.h>
42 #include <linux/seq_file.h> 42 #include <linux/seq_file.h>
43 #include <linux/slab.h> 43 #include <linux/slab.h>
44 #include <linux/spinlock.h> 44 #include <linux/spinlock.h>
45 #include <linux/types.h> 45 #include <linux/types.h>
46 46
47 #define MODULE_NAME "pinctrl-bcm2835" 47 #define MODULE_NAME "pinctrl-bcm2835"
48 #define BCM2835_NUM_GPIOS 54 48 #define BCM2835_NUM_GPIOS 54
49 #define BCM2835_NUM_BANKS 2 49 #define BCM2835_NUM_BANKS 2
50 50
51 #define BCM2835_PIN_BITMAP_SZ \ 51 #define BCM2835_PIN_BITMAP_SZ \
52 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8) 52 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
53 53
54 /* GPIO register offsets */ 54 /* GPIO register offsets */
55 #define GPFSEL0 0x0 /* Function Select */ 55 #define GPFSEL0 0x0 /* Function Select */
56 #define GPSET0 0x1c /* Pin Output Set */ 56 #define GPSET0 0x1c /* Pin Output Set */
57 #define GPCLR0 0x28 /* Pin Output Clear */ 57 #define GPCLR0 0x28 /* Pin Output Clear */
58 #define GPLEV0 0x34 /* Pin Level */ 58 #define GPLEV0 0x34 /* Pin Level */
59 #define GPEDS0 0x40 /* Pin Event Detect Status */ 59 #define GPEDS0 0x40 /* Pin Event Detect Status */
60 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */ 60 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
61 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */ 61 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
62 #define GPHEN0 0x64 /* Pin High Detect Enable */ 62 #define GPHEN0 0x64 /* Pin High Detect Enable */
63 #define GPLEN0 0x70 /* Pin Low Detect Enable */ 63 #define GPLEN0 0x70 /* Pin Low Detect Enable */
64 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */ 64 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
65 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */ 65 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
66 #define GPPUD 0x94 /* Pin Pull-up/down Enable */ 66 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
67 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */ 67 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
68 68
69 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4)) 69 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
70 #define FSEL_SHIFT(p) (((p) % 10) * 3) 70 #define FSEL_SHIFT(p) (((p) % 10) * 3)
71 #define GPIO_REG_OFFSET(p) ((p) / 32) 71 #define GPIO_REG_OFFSET(p) ((p) / 32)
72 #define GPIO_REG_SHIFT(p) ((p) % 32) 72 #define GPIO_REG_SHIFT(p) ((p) % 32)
73 73
74 enum bcm2835_pinconf_param { 74 enum bcm2835_pinconf_param {
75 /* argument: bcm2835_pinconf_pull */ 75 /* argument: bcm2835_pinconf_pull */
76 BCM2835_PINCONF_PARAM_PULL, 76 BCM2835_PINCONF_PARAM_PULL,
77 }; 77 };
78 78
79 enum bcm2835_pinconf_pull { 79 enum bcm2835_pinconf_pull {
80 BCM2835_PINCONFIG_PULL_NONE, 80 BCM2835_PINCONFIG_PULL_NONE,
81 BCM2835_PINCONFIG_PULL_DOWN, 81 BCM2835_PINCONFIG_PULL_DOWN,
82 BCM2835_PINCONFIG_PULL_UP, 82 BCM2835_PINCONFIG_PULL_UP,
83 }; 83 };
84 84
85 #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_)) 85 #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
86 #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16) 86 #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
87 #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff) 87 #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
88 88
89 struct bcm2835_gpio_irqdata { 89 struct bcm2835_gpio_irqdata {
90 struct bcm2835_pinctrl *pc; 90 struct bcm2835_pinctrl *pc;
91 int bank; 91 int bank;
92 }; 92 };
93 93
94 struct bcm2835_pinctrl { 94 struct bcm2835_pinctrl {
95 struct device *dev; 95 struct device *dev;
96 void __iomem *base; 96 void __iomem *base;
97 int irq[BCM2835_NUM_BANKS]; 97 int irq[BCM2835_NUM_BANKS];
98 98
99 /* note: locking assumes each bank will have its own unsigned long */ 99 /* note: locking assumes each bank will have its own unsigned long */
100 unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; 100 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
101 unsigned int irq_type[BCM2835_NUM_GPIOS]; 101 unsigned int irq_type[BCM2835_NUM_GPIOS];
102 102
103 struct pinctrl_dev *pctl_dev; 103 struct pinctrl_dev *pctl_dev;
104 struct irq_domain *irq_domain; 104 struct irq_domain *irq_domain;
105 struct gpio_chip gpio_chip; 105 struct gpio_chip gpio_chip;
106 struct pinctrl_gpio_range gpio_range; 106 struct pinctrl_gpio_range gpio_range;
107 107
108 struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS]; 108 struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
109 spinlock_t irq_lock[BCM2835_NUM_BANKS]; 109 spinlock_t irq_lock[BCM2835_NUM_BANKS];
110 }; 110 };
111 111
112 static struct lock_class_key gpio_lock_class; 112 static struct lock_class_key gpio_lock_class;
113 113
114 /* pins are just named GPIO0..GPIO53 */ 114 /* pins are just named GPIO0..GPIO53 */
115 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) 115 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
116 struct pinctrl_pin_desc bcm2835_gpio_pins[] = { 116 struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
117 BCM2835_GPIO_PIN(0), 117 BCM2835_GPIO_PIN(0),
118 BCM2835_GPIO_PIN(1), 118 BCM2835_GPIO_PIN(1),
119 BCM2835_GPIO_PIN(2), 119 BCM2835_GPIO_PIN(2),
120 BCM2835_GPIO_PIN(3), 120 BCM2835_GPIO_PIN(3),
121 BCM2835_GPIO_PIN(4), 121 BCM2835_GPIO_PIN(4),
122 BCM2835_GPIO_PIN(5), 122 BCM2835_GPIO_PIN(5),
123 BCM2835_GPIO_PIN(6), 123 BCM2835_GPIO_PIN(6),
124 BCM2835_GPIO_PIN(7), 124 BCM2835_GPIO_PIN(7),
125 BCM2835_GPIO_PIN(8), 125 BCM2835_GPIO_PIN(8),
126 BCM2835_GPIO_PIN(9), 126 BCM2835_GPIO_PIN(9),
127 BCM2835_GPIO_PIN(10), 127 BCM2835_GPIO_PIN(10),
128 BCM2835_GPIO_PIN(11), 128 BCM2835_GPIO_PIN(11),
129 BCM2835_GPIO_PIN(12), 129 BCM2835_GPIO_PIN(12),
130 BCM2835_GPIO_PIN(13), 130 BCM2835_GPIO_PIN(13),
131 BCM2835_GPIO_PIN(14), 131 BCM2835_GPIO_PIN(14),
132 BCM2835_GPIO_PIN(15), 132 BCM2835_GPIO_PIN(15),
133 BCM2835_GPIO_PIN(16), 133 BCM2835_GPIO_PIN(16),
134 BCM2835_GPIO_PIN(17), 134 BCM2835_GPIO_PIN(17),
135 BCM2835_GPIO_PIN(18), 135 BCM2835_GPIO_PIN(18),
136 BCM2835_GPIO_PIN(19), 136 BCM2835_GPIO_PIN(19),
137 BCM2835_GPIO_PIN(20), 137 BCM2835_GPIO_PIN(20),
138 BCM2835_GPIO_PIN(21), 138 BCM2835_GPIO_PIN(21),
139 BCM2835_GPIO_PIN(22), 139 BCM2835_GPIO_PIN(22),
140 BCM2835_GPIO_PIN(23), 140 BCM2835_GPIO_PIN(23),
141 BCM2835_GPIO_PIN(24), 141 BCM2835_GPIO_PIN(24),
142 BCM2835_GPIO_PIN(25), 142 BCM2835_GPIO_PIN(25),
143 BCM2835_GPIO_PIN(26), 143 BCM2835_GPIO_PIN(26),
144 BCM2835_GPIO_PIN(27), 144 BCM2835_GPIO_PIN(27),
145 BCM2835_GPIO_PIN(28), 145 BCM2835_GPIO_PIN(28),
146 BCM2835_GPIO_PIN(29), 146 BCM2835_GPIO_PIN(29),
147 BCM2835_GPIO_PIN(30), 147 BCM2835_GPIO_PIN(30),
148 BCM2835_GPIO_PIN(31), 148 BCM2835_GPIO_PIN(31),
149 BCM2835_GPIO_PIN(32), 149 BCM2835_GPIO_PIN(32),
150 BCM2835_GPIO_PIN(33), 150 BCM2835_GPIO_PIN(33),
151 BCM2835_GPIO_PIN(34), 151 BCM2835_GPIO_PIN(34),
152 BCM2835_GPIO_PIN(35), 152 BCM2835_GPIO_PIN(35),
153 BCM2835_GPIO_PIN(36), 153 BCM2835_GPIO_PIN(36),
154 BCM2835_GPIO_PIN(37), 154 BCM2835_GPIO_PIN(37),
155 BCM2835_GPIO_PIN(38), 155 BCM2835_GPIO_PIN(38),
156 BCM2835_GPIO_PIN(39), 156 BCM2835_GPIO_PIN(39),
157 BCM2835_GPIO_PIN(40), 157 BCM2835_GPIO_PIN(40),
158 BCM2835_GPIO_PIN(41), 158 BCM2835_GPIO_PIN(41),
159 BCM2835_GPIO_PIN(42), 159 BCM2835_GPIO_PIN(42),
160 BCM2835_GPIO_PIN(43), 160 BCM2835_GPIO_PIN(43),
161 BCM2835_GPIO_PIN(44), 161 BCM2835_GPIO_PIN(44),
162 BCM2835_GPIO_PIN(45), 162 BCM2835_GPIO_PIN(45),
163 BCM2835_GPIO_PIN(46), 163 BCM2835_GPIO_PIN(46),
164 BCM2835_GPIO_PIN(47), 164 BCM2835_GPIO_PIN(47),
165 BCM2835_GPIO_PIN(48), 165 BCM2835_GPIO_PIN(48),
166 BCM2835_GPIO_PIN(49), 166 BCM2835_GPIO_PIN(49),
167 BCM2835_GPIO_PIN(50), 167 BCM2835_GPIO_PIN(50),
168 BCM2835_GPIO_PIN(51), 168 BCM2835_GPIO_PIN(51),
169 BCM2835_GPIO_PIN(52), 169 BCM2835_GPIO_PIN(52),
170 BCM2835_GPIO_PIN(53), 170 BCM2835_GPIO_PIN(53),
171 }; 171 };
172 172
173 /* one pin per group */ 173 /* one pin per group */
174 static const char * const bcm2835_gpio_groups[] = { 174 static const char * const bcm2835_gpio_groups[] = {
175 "gpio0", 175 "gpio0",
176 "gpio1", 176 "gpio1",
177 "gpio2", 177 "gpio2",
178 "gpio3", 178 "gpio3",
179 "gpio4", 179 "gpio4",
180 "gpio5", 180 "gpio5",
181 "gpio6", 181 "gpio6",
182 "gpio7", 182 "gpio7",
183 "gpio8", 183 "gpio8",
184 "gpio9", 184 "gpio9",
185 "gpio10", 185 "gpio10",
186 "gpio11", 186 "gpio11",
187 "gpio12", 187 "gpio12",
188 "gpio13", 188 "gpio13",
189 "gpio14", 189 "gpio14",
190 "gpio15", 190 "gpio15",
191 "gpio16", 191 "gpio16",
192 "gpio17", 192 "gpio17",
193 "gpio18", 193 "gpio18",
194 "gpio19", 194 "gpio19",
195 "gpio20", 195 "gpio20",
196 "gpio21", 196 "gpio21",
197 "gpio22", 197 "gpio22",
198 "gpio23", 198 "gpio23",
199 "gpio24", 199 "gpio24",
200 "gpio25", 200 "gpio25",
201 "gpio26", 201 "gpio26",
202 "gpio27", 202 "gpio27",
203 "gpio28", 203 "gpio28",
204 "gpio29", 204 "gpio29",
205 "gpio30", 205 "gpio30",
206 "gpio31", 206 "gpio31",
207 "gpio32", 207 "gpio32",
208 "gpio33", 208 "gpio33",
209 "gpio34", 209 "gpio34",
210 "gpio35", 210 "gpio35",
211 "gpio36", 211 "gpio36",
212 "gpio37", 212 "gpio37",
213 "gpio38", 213 "gpio38",
214 "gpio39", 214 "gpio39",
215 "gpio40", 215 "gpio40",
216 "gpio41", 216 "gpio41",
217 "gpio42", 217 "gpio42",
218 "gpio43", 218 "gpio43",
219 "gpio44", 219 "gpio44",
220 "gpio45", 220 "gpio45",
221 "gpio46", 221 "gpio46",
222 "gpio47", 222 "gpio47",
223 "gpio48", 223 "gpio48",
224 "gpio49", 224 "gpio49",
225 "gpio50", 225 "gpio50",
226 "gpio51", 226 "gpio51",
227 "gpio52", 227 "gpio52",
228 "gpio53", 228 "gpio53",
229 }; 229 };
230 230
231 enum bcm2835_fsel { 231 enum bcm2835_fsel {
232 BCM2835_FSEL_GPIO_IN = 0, 232 BCM2835_FSEL_GPIO_IN = 0,
233 BCM2835_FSEL_GPIO_OUT = 1, 233 BCM2835_FSEL_GPIO_OUT = 1,
234 BCM2835_FSEL_ALT0 = 4, 234 BCM2835_FSEL_ALT0 = 4,
235 BCM2835_FSEL_ALT1 = 5, 235 BCM2835_FSEL_ALT1 = 5,
236 BCM2835_FSEL_ALT2 = 6, 236 BCM2835_FSEL_ALT2 = 6,
237 BCM2835_FSEL_ALT3 = 7, 237 BCM2835_FSEL_ALT3 = 7,
238 BCM2835_FSEL_ALT4 = 3, 238 BCM2835_FSEL_ALT4 = 3,
239 BCM2835_FSEL_ALT5 = 2, 239 BCM2835_FSEL_ALT5 = 2,
240 BCM2835_FSEL_COUNT = 8, 240 BCM2835_FSEL_COUNT = 8,
241 BCM2835_FSEL_MASK = 0x7, 241 BCM2835_FSEL_MASK = 0x7,
242 }; 242 };
243 243
244 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = { 244 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
245 [BCM2835_FSEL_GPIO_IN] = "gpio_in", 245 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
246 [BCM2835_FSEL_GPIO_OUT] = "gpio_out", 246 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
247 [BCM2835_FSEL_ALT0] = "alt0", 247 [BCM2835_FSEL_ALT0] = "alt0",
248 [BCM2835_FSEL_ALT1] = "alt1", 248 [BCM2835_FSEL_ALT1] = "alt1",
249 [BCM2835_FSEL_ALT2] = "alt2", 249 [BCM2835_FSEL_ALT2] = "alt2",
250 [BCM2835_FSEL_ALT3] = "alt3", 250 [BCM2835_FSEL_ALT3] = "alt3",
251 [BCM2835_FSEL_ALT4] = "alt4", 251 [BCM2835_FSEL_ALT4] = "alt4",
252 [BCM2835_FSEL_ALT5] = "alt5", 252 [BCM2835_FSEL_ALT5] = "alt5",
253 }; 253 };
254 254
255 static const char * const irq_type_names[] = { 255 static const char * const irq_type_names[] = {
256 [IRQ_TYPE_NONE] = "none", 256 [IRQ_TYPE_NONE] = "none",
257 [IRQ_TYPE_EDGE_RISING] = "edge-rising", 257 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
258 [IRQ_TYPE_EDGE_FALLING] = "edge-falling", 258 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
259 [IRQ_TYPE_EDGE_BOTH] = "edge-both", 259 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
260 [IRQ_TYPE_LEVEL_HIGH] = "level-high", 260 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
261 [IRQ_TYPE_LEVEL_LOW] = "level-low", 261 [IRQ_TYPE_LEVEL_LOW] = "level-low",
262 }; 262 };
263 263
264 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg) 264 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
265 { 265 {
266 return readl(pc->base + reg); 266 return readl(pc->base + reg);
267 } 267 }
268 268
269 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg, 269 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
270 u32 val) 270 u32 val)
271 { 271 {
272 writel(val, pc->base + reg); 272 writel(val, pc->base + reg);
273 } 273 }
274 274
275 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg, 275 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
276 unsigned bit) 276 unsigned bit)
277 { 277 {
278 reg += GPIO_REG_OFFSET(bit) * 4; 278 reg += GPIO_REG_OFFSET(bit) * 4;
279 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1; 279 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
280 } 280 }
281 281
282 /* note NOT a read/modify/write cycle */ 282 /* note NOT a read/modify/write cycle */
283 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc, 283 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
284 unsigned reg, unsigned bit) 284 unsigned reg, unsigned bit)
285 { 285 {
286 reg += GPIO_REG_OFFSET(bit) * 4; 286 reg += GPIO_REG_OFFSET(bit) * 4;
287 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit))); 287 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
288 } 288 }
289 289
290 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get( 290 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
291 struct bcm2835_pinctrl *pc, unsigned pin) 291 struct bcm2835_pinctrl *pc, unsigned pin)
292 { 292 {
293 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 293 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
294 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 294 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
295 295
296 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin, 296 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
297 bcm2835_functions[status]); 297 bcm2835_functions[status]);
298 298
299 return status; 299 return status;
300 } 300 }
301 301
302 static inline void bcm2835_pinctrl_fsel_set( 302 static inline void bcm2835_pinctrl_fsel_set(
303 struct bcm2835_pinctrl *pc, unsigned pin, 303 struct bcm2835_pinctrl *pc, unsigned pin,
304 enum bcm2835_fsel fsel) 304 enum bcm2835_fsel fsel)
305 { 305 {
306 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 306 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
307 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 307 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
308 308
309 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin, 309 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
310 bcm2835_functions[cur]); 310 bcm2835_functions[cur]);
311 311
312 if (cur == fsel) 312 if (cur == fsel)
313 return; 313 return;
314 314
315 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) { 315 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
316 /* always transition through GPIO_IN */ 316 /* always transition through GPIO_IN */
317 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 317 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
318 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin); 318 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
319 319
320 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin, 320 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
321 bcm2835_functions[BCM2835_FSEL_GPIO_IN]); 321 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
322 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 322 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
323 } 323 }
324 324
325 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 325 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
326 val |= fsel << FSEL_SHIFT(pin); 326 val |= fsel << FSEL_SHIFT(pin);
327 327
328 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin, 328 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
329 bcm2835_functions[fsel]); 329 bcm2835_functions[fsel]);
330 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 330 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
331 } 331 }
332 332
333 static int bcm2835_gpio_request(struct gpio_chip *chip, unsigned offset) 333 static int bcm2835_gpio_request(struct gpio_chip *chip, unsigned offset)
334 { 334 {
335 return pinctrl_request_gpio(chip->base + offset); 335 return pinctrl_request_gpio(chip->base + offset);
336 } 336 }
337 337
338 static void bcm2835_gpio_free(struct gpio_chip *chip, unsigned offset) 338 static void bcm2835_gpio_free(struct gpio_chip *chip, unsigned offset)
339 { 339 {
340 pinctrl_free_gpio(chip->base + offset); 340 pinctrl_free_gpio(chip->base + offset);
341 } 341 }
342 342
343 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 343 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
344 { 344 {
345 return pinctrl_gpio_direction_input(chip->base + offset); 345 return pinctrl_gpio_direction_input(chip->base + offset);
346 } 346 }
347 347
348 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) 348 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
349 { 349 {
350 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); 350 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
351 351
352 return bcm2835_gpio_get_bit(pc, GPLEV0, offset); 352 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
353 } 353 }
354 354
355 static int bcm2835_gpio_direction_output(struct gpio_chip *chip, 355 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
356 unsigned offset, int value) 356 unsigned offset, int value)
357 { 357 {
358 return pinctrl_gpio_direction_output(chip->base + offset); 358 return pinctrl_gpio_direction_output(chip->base + offset);
359 } 359 }
360 360
361 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 361 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
362 { 362 {
363 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); 363 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
364 364
365 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); 365 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
366 } 366 }
367 367
368 static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 368 static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
369 { 369 {
370 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); 370 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
371 371
372 return irq_linear_revmap(pc->irq_domain, offset); 372 return irq_linear_revmap(pc->irq_domain, offset);
373 } 373 }
374 374
375 static struct gpio_chip bcm2835_gpio_chip = { 375 static struct gpio_chip bcm2835_gpio_chip = {
376 .label = MODULE_NAME, 376 .label = MODULE_NAME,
377 .owner = THIS_MODULE, 377 .owner = THIS_MODULE,
378 .request = bcm2835_gpio_request, 378 .request = bcm2835_gpio_request,
379 .free = bcm2835_gpio_free, 379 .free = bcm2835_gpio_free,
380 .direction_input = bcm2835_gpio_direction_input, 380 .direction_input = bcm2835_gpio_direction_input,
381 .direction_output = bcm2835_gpio_direction_output, 381 .direction_output = bcm2835_gpio_direction_output,
382 .get = bcm2835_gpio_get, 382 .get = bcm2835_gpio_get,
383 .set = bcm2835_gpio_set, 383 .set = bcm2835_gpio_set,
384 .to_irq = bcm2835_gpio_to_irq, 384 .to_irq = bcm2835_gpio_to_irq,
385 .base = -1, 385 .base = -1,
386 .ngpio = BCM2835_NUM_GPIOS, 386 .ngpio = BCM2835_NUM_GPIOS,
387 .can_sleep = 0, 387 .can_sleep = 0,
388 }; 388 };
389 389
390 static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) 390 static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
391 { 391 {
392 struct bcm2835_gpio_irqdata *irqdata = dev_id; 392 struct bcm2835_gpio_irqdata *irqdata = dev_id;
393 struct bcm2835_pinctrl *pc = irqdata->pc; 393 struct bcm2835_pinctrl *pc = irqdata->pc;
394 int bank = irqdata->bank; 394 int bank = irqdata->bank;
395 unsigned long events; 395 unsigned long events;
396 unsigned offset; 396 unsigned offset;
397 unsigned gpio; 397 unsigned gpio;
398 unsigned int type; 398 unsigned int type;
399 399
400 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); 400 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
401 events &= pc->enabled_irq_map[bank]; 401 events &= pc->enabled_irq_map[bank];
402 for_each_set_bit(offset, &events, 32) { 402 for_each_set_bit(offset, &events, 32) {
403 gpio = (32 * bank) + offset; 403 gpio = (32 * bank) + offset;
404 type = pc->irq_type[gpio]; 404 type = pc->irq_type[gpio];
405 405
406 /* ack edge triggered IRQs immediately */ 406 /* ack edge triggered IRQs immediately */
407 if (!(type & IRQ_TYPE_LEVEL_MASK)) 407 if (!(type & IRQ_TYPE_LEVEL_MASK))
408 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 408 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
409 409
410 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio)); 410 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
411 411
412 /* ack level triggered IRQ after handling them */ 412 /* ack level triggered IRQ after handling them */
413 if (type & IRQ_TYPE_LEVEL_MASK) 413 if (type & IRQ_TYPE_LEVEL_MASK)
414 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 414 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
415 } 415 }
416 return events ? IRQ_HANDLED : IRQ_NONE; 416 return events ? IRQ_HANDLED : IRQ_NONE;
417 } 417 }
418 418
419 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 419 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
420 unsigned reg, unsigned offset, bool enable) 420 unsigned reg, unsigned offset, bool enable)
421 { 421 {
422 u32 value; 422 u32 value;
423 reg += GPIO_REG_OFFSET(offset) * 4; 423 reg += GPIO_REG_OFFSET(offset) * 4;
424 value = bcm2835_gpio_rd(pc, reg); 424 value = bcm2835_gpio_rd(pc, reg);
425 if (enable) 425 if (enable)
426 value |= BIT(GPIO_REG_SHIFT(offset)); 426 value |= BIT(GPIO_REG_SHIFT(offset));
427 else 427 else
428 value &= ~(BIT(GPIO_REG_SHIFT(offset))); 428 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
429 bcm2835_gpio_wr(pc, reg, value); 429 bcm2835_gpio_wr(pc, reg, value);
430 } 430 }
431 431
432 /* fast path for IRQ handler */ 432 /* fast path for IRQ handler */
433 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 433 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
434 unsigned offset, bool enable) 434 unsigned offset, bool enable)
435 { 435 {
436 switch (pc->irq_type[offset]) { 436 switch (pc->irq_type[offset]) {
437 case IRQ_TYPE_EDGE_RISING: 437 case IRQ_TYPE_EDGE_RISING:
438 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 438 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
439 break; 439 break;
440 440
441 case IRQ_TYPE_EDGE_FALLING: 441 case IRQ_TYPE_EDGE_FALLING:
442 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 442 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
443 break; 443 break;
444 444
445 case IRQ_TYPE_EDGE_BOTH: 445 case IRQ_TYPE_EDGE_BOTH:
446 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 446 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
447 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 447 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
448 break; 448 break;
449 449
450 case IRQ_TYPE_LEVEL_HIGH: 450 case IRQ_TYPE_LEVEL_HIGH:
451 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable); 451 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
452 break; 452 break;
453 453
454 case IRQ_TYPE_LEVEL_LOW: 454 case IRQ_TYPE_LEVEL_LOW:
455 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable); 455 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
456 break; 456 break;
457 } 457 }
458 } 458 }
459 459
460 static void bcm2835_gpio_irq_enable(struct irq_data *data) 460 static void bcm2835_gpio_irq_enable(struct irq_data *data)
461 { 461 {
462 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data); 462 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
463 unsigned gpio = irqd_to_hwirq(data); 463 unsigned gpio = irqd_to_hwirq(data);
464 unsigned offset = GPIO_REG_SHIFT(gpio); 464 unsigned offset = GPIO_REG_SHIFT(gpio);
465 unsigned bank = GPIO_REG_OFFSET(gpio); 465 unsigned bank = GPIO_REG_OFFSET(gpio);
466 unsigned long flags; 466 unsigned long flags;
467 467
468 spin_lock_irqsave(&pc->irq_lock[bank], flags); 468 spin_lock_irqsave(&pc->irq_lock[bank], flags);
469 set_bit(offset, &pc->enabled_irq_map[bank]); 469 set_bit(offset, &pc->enabled_irq_map[bank]);
470 bcm2835_gpio_irq_config(pc, gpio, true); 470 bcm2835_gpio_irq_config(pc, gpio, true);
471 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 471 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
472 } 472 }
473 473
474 static void bcm2835_gpio_irq_disable(struct irq_data *data) 474 static void bcm2835_gpio_irq_disable(struct irq_data *data)
475 { 475 {
476 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data); 476 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
477 unsigned gpio = irqd_to_hwirq(data); 477 unsigned gpio = irqd_to_hwirq(data);
478 unsigned offset = GPIO_REG_SHIFT(gpio); 478 unsigned offset = GPIO_REG_SHIFT(gpio);
479 unsigned bank = GPIO_REG_OFFSET(gpio); 479 unsigned bank = GPIO_REG_OFFSET(gpio);
480 unsigned long flags; 480 unsigned long flags;
481 481
482 spin_lock_irqsave(&pc->irq_lock[bank], flags); 482 spin_lock_irqsave(&pc->irq_lock[bank], flags);
483 bcm2835_gpio_irq_config(pc, gpio, false); 483 bcm2835_gpio_irq_config(pc, gpio, false);
484 clear_bit(offset, &pc->enabled_irq_map[bank]); 484 clear_bit(offset, &pc->enabled_irq_map[bank]);
485 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 485 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
486 } 486 }
487 487
488 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc, 488 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
489 unsigned offset, unsigned int type) 489 unsigned offset, unsigned int type)
490 { 490 {
491 switch (type) { 491 switch (type) {
492 case IRQ_TYPE_NONE: 492 case IRQ_TYPE_NONE:
493 case IRQ_TYPE_EDGE_RISING: 493 case IRQ_TYPE_EDGE_RISING:
494 case IRQ_TYPE_EDGE_FALLING: 494 case IRQ_TYPE_EDGE_FALLING:
495 case IRQ_TYPE_EDGE_BOTH: 495 case IRQ_TYPE_EDGE_BOTH:
496 case IRQ_TYPE_LEVEL_HIGH: 496 case IRQ_TYPE_LEVEL_HIGH:
497 case IRQ_TYPE_LEVEL_LOW: 497 case IRQ_TYPE_LEVEL_LOW:
498 pc->irq_type[offset] = type; 498 pc->irq_type[offset] = type;
499 break; 499 break;
500 500
501 default: 501 default:
502 return -EINVAL; 502 return -EINVAL;
503 } 503 }
504 return 0; 504 return 0;
505 } 505 }
506 506
507 /* slower path for reconfiguring IRQ type */ 507 /* slower path for reconfiguring IRQ type */
508 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc, 508 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
509 unsigned offset, unsigned int type) 509 unsigned offset, unsigned int type)
510 { 510 {
511 switch (type) { 511 switch (type) {
512 case IRQ_TYPE_NONE: 512 case IRQ_TYPE_NONE:
513 if (pc->irq_type[offset] != type) { 513 if (pc->irq_type[offset] != type) {
514 bcm2835_gpio_irq_config(pc, offset, false); 514 bcm2835_gpio_irq_config(pc, offset, false);
515 pc->irq_type[offset] = type; 515 pc->irq_type[offset] = type;
516 } 516 }
517 break; 517 break;
518 518
519 case IRQ_TYPE_EDGE_RISING: 519 case IRQ_TYPE_EDGE_RISING:
520 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 520 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
521 /* RISING already enabled, disable FALLING */ 521 /* RISING already enabled, disable FALLING */
522 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 522 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
523 bcm2835_gpio_irq_config(pc, offset, false); 523 bcm2835_gpio_irq_config(pc, offset, false);
524 pc->irq_type[offset] = type; 524 pc->irq_type[offset] = type;
525 } else if (pc->irq_type[offset] != type) { 525 } else if (pc->irq_type[offset] != type) {
526 bcm2835_gpio_irq_config(pc, offset, false); 526 bcm2835_gpio_irq_config(pc, offset, false);
527 pc->irq_type[offset] = type; 527 pc->irq_type[offset] = type;
528 bcm2835_gpio_irq_config(pc, offset, true); 528 bcm2835_gpio_irq_config(pc, offset, true);
529 } 529 }
530 break; 530 break;
531 531
532 case IRQ_TYPE_EDGE_FALLING: 532 case IRQ_TYPE_EDGE_FALLING:
533 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 533 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
534 /* FALLING already enabled, disable RISING */ 534 /* FALLING already enabled, disable RISING */
535 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 535 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
536 bcm2835_gpio_irq_config(pc, offset, false); 536 bcm2835_gpio_irq_config(pc, offset, false);
537 pc->irq_type[offset] = type; 537 pc->irq_type[offset] = type;
538 } else if (pc->irq_type[offset] != type) { 538 } else if (pc->irq_type[offset] != type) {
539 bcm2835_gpio_irq_config(pc, offset, false); 539 bcm2835_gpio_irq_config(pc, offset, false);
540 pc->irq_type[offset] = type; 540 pc->irq_type[offset] = type;
541 bcm2835_gpio_irq_config(pc, offset, true); 541 bcm2835_gpio_irq_config(pc, offset, true);
542 } 542 }
543 break; 543 break;
544 544
545 case IRQ_TYPE_EDGE_BOTH: 545 case IRQ_TYPE_EDGE_BOTH:
546 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) { 546 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
547 /* RISING already enabled, enable FALLING too */ 547 /* RISING already enabled, enable FALLING too */
548 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 548 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
549 bcm2835_gpio_irq_config(pc, offset, true); 549 bcm2835_gpio_irq_config(pc, offset, true);
550 pc->irq_type[offset] = type; 550 pc->irq_type[offset] = type;
551 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) { 551 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
552 /* FALLING already enabled, enable RISING too */ 552 /* FALLING already enabled, enable RISING too */
553 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 553 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
554 bcm2835_gpio_irq_config(pc, offset, true); 554 bcm2835_gpio_irq_config(pc, offset, true);
555 pc->irq_type[offset] = type; 555 pc->irq_type[offset] = type;
556 } else if (pc->irq_type[offset] != type) { 556 } else if (pc->irq_type[offset] != type) {
557 bcm2835_gpio_irq_config(pc, offset, false); 557 bcm2835_gpio_irq_config(pc, offset, false);
558 pc->irq_type[offset] = type; 558 pc->irq_type[offset] = type;
559 bcm2835_gpio_irq_config(pc, offset, true); 559 bcm2835_gpio_irq_config(pc, offset, true);
560 } 560 }
561 break; 561 break;
562 562
563 case IRQ_TYPE_LEVEL_HIGH: 563 case IRQ_TYPE_LEVEL_HIGH:
564 case IRQ_TYPE_LEVEL_LOW: 564 case IRQ_TYPE_LEVEL_LOW:
565 if (pc->irq_type[offset] != type) { 565 if (pc->irq_type[offset] != type) {
566 bcm2835_gpio_irq_config(pc, offset, false); 566 bcm2835_gpio_irq_config(pc, offset, false);
567 pc->irq_type[offset] = type; 567 pc->irq_type[offset] = type;
568 bcm2835_gpio_irq_config(pc, offset, true); 568 bcm2835_gpio_irq_config(pc, offset, true);
569 } 569 }
570 break; 570 break;
571 571
572 default: 572 default:
573 return -EINVAL; 573 return -EINVAL;
574 } 574 }
575 return 0; 575 return 0;
576 } 576 }
577 577
578 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) 578 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
579 { 579 {
580 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data); 580 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
581 unsigned gpio = irqd_to_hwirq(data); 581 unsigned gpio = irqd_to_hwirq(data);
582 unsigned offset = GPIO_REG_SHIFT(gpio); 582 unsigned offset = GPIO_REG_SHIFT(gpio);
583 unsigned bank = GPIO_REG_OFFSET(gpio); 583 unsigned bank = GPIO_REG_OFFSET(gpio);
584 unsigned long flags; 584 unsigned long flags;
585 int ret; 585 int ret;
586 586
587 spin_lock_irqsave(&pc->irq_lock[bank], flags); 587 spin_lock_irqsave(&pc->irq_lock[bank], flags);
588 588
589 if (test_bit(offset, &pc->enabled_irq_map[bank])) 589 if (test_bit(offset, &pc->enabled_irq_map[bank]))
590 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type); 590 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
591 else 591 else
592 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); 592 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
593 593
594 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 594 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
595 595
596 return ret; 596 return ret;
597 } 597 }
598 598
599 static struct irq_chip bcm2835_gpio_irq_chip = { 599 static struct irq_chip bcm2835_gpio_irq_chip = {
600 .name = MODULE_NAME, 600 .name = MODULE_NAME,
601 .irq_enable = bcm2835_gpio_irq_enable, 601 .irq_enable = bcm2835_gpio_irq_enable,
602 .irq_disable = bcm2835_gpio_irq_disable, 602 .irq_disable = bcm2835_gpio_irq_disable,
603 .irq_set_type = bcm2835_gpio_irq_set_type, 603 .irq_set_type = bcm2835_gpio_irq_set_type,
604 }; 604 };
605 605
606 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) 606 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
607 { 607 {
608 return ARRAY_SIZE(bcm2835_gpio_groups); 608 return ARRAY_SIZE(bcm2835_gpio_groups);
609 } 609 }
610 610
611 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev, 611 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
612 unsigned selector) 612 unsigned selector)
613 { 613 {
614 return bcm2835_gpio_groups[selector]; 614 return bcm2835_gpio_groups[selector];
615 } 615 }
616 616
617 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev, 617 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
618 unsigned selector, 618 unsigned selector,
619 const unsigned **pins, 619 const unsigned **pins,
620 unsigned *num_pins) 620 unsigned *num_pins)
621 { 621 {
622 *pins = &bcm2835_gpio_pins[selector].number; 622 *pins = &bcm2835_gpio_pins[selector].number;
623 *num_pins = 1; 623 *num_pins = 1;
624 624
625 return 0; 625 return 0;
626 } 626 }
627 627
628 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, 628 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
629 struct seq_file *s, 629 struct seq_file *s,
630 unsigned offset) 630 unsigned offset)
631 { 631 {
632 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 632 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
633 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 633 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
634 const char *fname = bcm2835_functions[fsel]; 634 const char *fname = bcm2835_functions[fsel];
635 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset); 635 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
636 int irq = irq_find_mapping(pc->irq_domain, offset); 636 int irq = irq_find_mapping(pc->irq_domain, offset);
637 637
638 seq_printf(s, "function %s in %s; irq %d (%s)", 638 seq_printf(s, "function %s in %s; irq %d (%s)",
639 fname, value ? "hi" : "lo", 639 fname, value ? "hi" : "lo",
640 irq, irq_type_names[pc->irq_type[offset]]); 640 irq, irq_type_names[pc->irq_type[offset]]);
641 } 641 }
642 642
643 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev, 643 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
644 struct pinctrl_map *maps, unsigned num_maps) 644 struct pinctrl_map *maps, unsigned num_maps)
645 { 645 {
646 int i; 646 int i;
647 647
648 for (i = 0; i < num_maps; i++) 648 for (i = 0; i < num_maps; i++)
649 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 649 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
650 kfree(maps[i].data.configs.configs); 650 kfree(maps[i].data.configs.configs);
651 651
652 kfree(maps); 652 kfree(maps);
653 } 653 }
654 654
655 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc, 655 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
656 struct device_node *np, u32 pin, u32 fnum, 656 struct device_node *np, u32 pin, u32 fnum,
657 struct pinctrl_map **maps) 657 struct pinctrl_map **maps)
658 { 658 {
659 struct pinctrl_map *map = *maps; 659 struct pinctrl_map *map = *maps;
660 660
661 if (fnum >= ARRAY_SIZE(bcm2835_functions)) { 661 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
662 dev_err(pc->dev, "%s: invalid brcm,function %d\n", 662 dev_err(pc->dev, "%s: invalid brcm,function %d\n",
663 of_node_full_name(np), fnum); 663 of_node_full_name(np), fnum);
664 return -EINVAL; 664 return -EINVAL;
665 } 665 }
666 666
667 map->type = PIN_MAP_TYPE_MUX_GROUP; 667 map->type = PIN_MAP_TYPE_MUX_GROUP;
668 map->data.mux.group = bcm2835_gpio_groups[pin]; 668 map->data.mux.group = bcm2835_gpio_groups[pin];
669 map->data.mux.function = bcm2835_functions[fnum]; 669 map->data.mux.function = bcm2835_functions[fnum];
670 (*maps)++; 670 (*maps)++;
671 671
672 return 0; 672 return 0;
673 } 673 }
674 674
675 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc, 675 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
676 struct device_node *np, u32 pin, u32 pull, 676 struct device_node *np, u32 pin, u32 pull,
677 struct pinctrl_map **maps) 677 struct pinctrl_map **maps)
678 { 678 {
679 struct pinctrl_map *map = *maps; 679 struct pinctrl_map *map = *maps;
680 unsigned long *configs; 680 unsigned long *configs;
681 681
682 if (pull > 2) { 682 if (pull > 2) {
683 dev_err(pc->dev, "%s: invalid brcm,pull %d\n", 683 dev_err(pc->dev, "%s: invalid brcm,pull %d\n",
684 of_node_full_name(np), pull); 684 of_node_full_name(np), pull);
685 return -EINVAL; 685 return -EINVAL;
686 } 686 }
687 687
688 configs = kzalloc(sizeof(*configs), GFP_KERNEL); 688 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
689 if (!configs) 689 if (!configs)
690 return -ENOMEM; 690 return -ENOMEM;
691 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull); 691 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
692 692
693 map->type = PIN_MAP_TYPE_CONFIGS_PIN; 693 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
694 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name; 694 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
695 map->data.configs.configs = configs; 695 map->data.configs.configs = configs;
696 map->data.configs.num_configs = 1; 696 map->data.configs.num_configs = 1;
697 (*maps)++; 697 (*maps)++;
698 698
699 return 0; 699 return 0;
700 } 700 }
701 701
702 static inline u32 prop_u32(struct property *p, int i) 702 static inline u32 prop_u32(struct property *p, int i)
703 { 703 {
704 return be32_to_cpup(((__be32 *)p->value) + i); 704 return be32_to_cpup(((__be32 *)p->value) + i);
705 } 705 }
706 706
707 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 707 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
708 struct device_node *np, 708 struct device_node *np,
709 struct pinctrl_map **map, unsigned *num_maps) 709 struct pinctrl_map **map, unsigned *num_maps)
710 { 710 {
711 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 711 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
712 struct property *pins, *funcs, *pulls; 712 struct property *pins, *funcs, *pulls;
713 int num_pins, num_funcs, num_pulls, maps_per_pin; 713 int num_pins, num_funcs, num_pulls, maps_per_pin;
714 struct pinctrl_map *maps, *cur_map; 714 struct pinctrl_map *maps, *cur_map;
715 int i, err; 715 int i, err;
716 u32 pin, func, pull; 716 u32 pin, func, pull;
717 717
718 pins = of_find_property(np, "brcm,pins", NULL); 718 pins = of_find_property(np, "brcm,pins", NULL);
719 if (!pins) { 719 if (!pins) {
720 dev_err(pc->dev, "%s: missing brcm,pins property\n", 720 dev_err(pc->dev, "%s: missing brcm,pins property\n",
721 of_node_full_name(np)); 721 of_node_full_name(np));
722 return -EINVAL; 722 return -EINVAL;
723 } 723 }
724 724
725 funcs = of_find_property(np, "brcm,function", NULL); 725 funcs = of_find_property(np, "brcm,function", NULL);
726 pulls = of_find_property(np, "brcm,pull", NULL); 726 pulls = of_find_property(np, "brcm,pull", NULL);
727 727
728 if (!funcs && !pulls) { 728 if (!funcs && !pulls) {
729 dev_err(pc->dev, 729 dev_err(pc->dev,
730 "%s: neither brcm,function nor brcm,pull specified\n", 730 "%s: neither brcm,function nor brcm,pull specified\n",
731 of_node_full_name(np)); 731 of_node_full_name(np));
732 return -EINVAL; 732 return -EINVAL;
733 } 733 }
734 734
735 num_pins = pins->length / 4; 735 num_pins = pins->length / 4;
736 num_funcs = funcs ? (funcs->length / 4) : 0; 736 num_funcs = funcs ? (funcs->length / 4) : 0;
737 num_pulls = pulls ? (pulls->length / 4) : 0; 737 num_pulls = pulls ? (pulls->length / 4) : 0;
738 738
739 if (num_funcs > 1 && num_funcs != num_pins) { 739 if (num_funcs > 1 && num_funcs != num_pins) {
740 dev_err(pc->dev, 740 dev_err(pc->dev,
741 "%s: brcm,function must have 1 or %d entries\n", 741 "%s: brcm,function must have 1 or %d entries\n",
742 of_node_full_name(np), num_pins); 742 of_node_full_name(np), num_pins);
743 return -EINVAL; 743 return -EINVAL;
744 } 744 }
745 745
746 if (num_pulls > 1 && num_pulls != num_pins) { 746 if (num_pulls > 1 && num_pulls != num_pins) {
747 dev_err(pc->dev, 747 dev_err(pc->dev,
748 "%s: brcm,pull must have 1 or %d entries\n", 748 "%s: brcm,pull must have 1 or %d entries\n",
749 of_node_full_name(np), num_pins); 749 of_node_full_name(np), num_pins);
750 return -EINVAL; 750 return -EINVAL;
751 } 751 }
752 752
753 maps_per_pin = 0; 753 maps_per_pin = 0;
754 if (num_funcs) 754 if (num_funcs)
755 maps_per_pin++; 755 maps_per_pin++;
756 if (num_pulls) 756 if (num_pulls)
757 maps_per_pin++; 757 maps_per_pin++;
758 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps), 758 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
759 GFP_KERNEL); 759 GFP_KERNEL);
760 if (!maps) 760 if (!maps)
761 return -ENOMEM; 761 return -ENOMEM;
762 762
763 for (i = 0; i < num_pins; i++) { 763 for (i = 0; i < num_pins; i++) {
764 pin = prop_u32(pins, i); 764 pin = prop_u32(pins, i);
765 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) { 765 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
766 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n", 766 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
767 of_node_full_name(np), pin); 767 of_node_full_name(np), pin);
768 err = -EINVAL; 768 err = -EINVAL;
769 goto out; 769 goto out;
770 } 770 }
771 771
772 if (num_funcs) { 772 if (num_funcs) {
773 func = prop_u32(funcs, (num_funcs > 1) ? i : 0); 773 func = prop_u32(funcs, (num_funcs > 1) ? i : 0);
774 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin, 774 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
775 func, &cur_map); 775 func, &cur_map);
776 if (err) 776 if (err)
777 goto out; 777 goto out;
778 } 778 }
779 if (num_pulls) { 779 if (num_pulls) {
780 pull = prop_u32(pulls, (num_pulls > 1) ? i : 0); 780 pull = prop_u32(pulls, (num_pulls > 1) ? i : 0);
781 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin, 781 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
782 pull, &cur_map); 782 pull, &cur_map);
783 if (err) 783 if (err)
784 goto out; 784 goto out;
785 } 785 }
786 } 786 }
787 787
788 *map = maps; 788 *map = maps;
789 *num_maps = num_pins * maps_per_pin; 789 *num_maps = num_pins * maps_per_pin;
790 790
791 return 0; 791 return 0;
792 792
793 out: 793 out:
794 kfree(maps); 794 kfree(maps);
795 return err; 795 return err;
796 } 796 }
797 797
798 static struct pinctrl_ops bcm2835_pctl_ops = { 798 static struct pinctrl_ops bcm2835_pctl_ops = {
799 .get_groups_count = bcm2835_pctl_get_groups_count, 799 .get_groups_count = bcm2835_pctl_get_groups_count,
800 .get_group_name = bcm2835_pctl_get_group_name, 800 .get_group_name = bcm2835_pctl_get_group_name,
801 .get_group_pins = bcm2835_pctl_get_group_pins, 801 .get_group_pins = bcm2835_pctl_get_group_pins,
802 .pin_dbg_show = bcm2835_pctl_pin_dbg_show, 802 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
803 .dt_node_to_map = bcm2835_pctl_dt_node_to_map, 803 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
804 .dt_free_map = bcm2835_pctl_dt_free_map, 804 .dt_free_map = bcm2835_pctl_dt_free_map,
805 }; 805 };
806 806
807 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev) 807 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
808 { 808 {
809 return BCM2835_FSEL_COUNT; 809 return BCM2835_FSEL_COUNT;
810 } 810 }
811 811
812 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev, 812 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
813 unsigned selector) 813 unsigned selector)
814 { 814 {
815 return bcm2835_functions[selector]; 815 return bcm2835_functions[selector];
816 } 816 }
817 817
818 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev, 818 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
819 unsigned selector, 819 unsigned selector,
820 const char * const **groups, 820 const char * const **groups,
821 unsigned * const num_groups) 821 unsigned * const num_groups)
822 { 822 {
823 /* every pin can do every function */ 823 /* every pin can do every function */
824 *groups = bcm2835_gpio_groups; 824 *groups = bcm2835_gpio_groups;
825 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups); 825 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
826 826
827 return 0; 827 return 0;
828 } 828 }
829 829
830 static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev, 830 static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev,
831 unsigned func_selector, 831 unsigned func_selector,
832 unsigned group_selector) 832 unsigned group_selector)
833 { 833 {
834 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 834 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
835 835
836 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector); 836 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
837 837
838 return 0; 838 return 0;
839 } 839 }
840 840
841 static void bcm2835_pmx_disable(struct pinctrl_dev *pctldev, 841 static void bcm2835_pmx_disable(struct pinctrl_dev *pctldev,
842 unsigned func_selector, 842 unsigned func_selector,
843 unsigned group_selector) 843 unsigned group_selector)
844 { 844 {
845 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 845 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
846 846
847 /* disable by setting to GPIO_IN */ 847 /* disable by setting to GPIO_IN */
848 bcm2835_pinctrl_fsel_set(pc, group_selector, BCM2835_FSEL_GPIO_IN); 848 bcm2835_pinctrl_fsel_set(pc, group_selector, BCM2835_FSEL_GPIO_IN);
849 } 849 }
850 850
851 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 851 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
852 struct pinctrl_gpio_range *range, 852 struct pinctrl_gpio_range *range,
853 unsigned offset) 853 unsigned offset)
854 { 854 {
855 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 855 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
856 856
857 /* disable by setting to GPIO_IN */ 857 /* disable by setting to GPIO_IN */
858 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 858 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
859 } 859 }
860 860
861 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 861 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
862 struct pinctrl_gpio_range *range, 862 struct pinctrl_gpio_range *range,
863 unsigned offset, 863 unsigned offset,
864 bool input) 864 bool input)
865 { 865 {
866 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 866 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
867 enum bcm2835_fsel fsel = input ? 867 enum bcm2835_fsel fsel = input ?
868 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT; 868 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
869 869
870 bcm2835_pinctrl_fsel_set(pc, offset, fsel); 870 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
871 871
872 return 0; 872 return 0;
873 } 873 }
874 874
875 static struct pinmux_ops bcm2835_pmx_ops = { 875 static struct pinmux_ops bcm2835_pmx_ops = {
876 .get_functions_count = bcm2835_pmx_get_functions_count, 876 .get_functions_count = bcm2835_pmx_get_functions_count,
877 .get_function_name = bcm2835_pmx_get_function_name, 877 .get_function_name = bcm2835_pmx_get_function_name,
878 .get_function_groups = bcm2835_pmx_get_function_groups, 878 .get_function_groups = bcm2835_pmx_get_function_groups,
879 .enable = bcm2835_pmx_enable, 879 .enable = bcm2835_pmx_enable,
880 .disable = bcm2835_pmx_disable, 880 .disable = bcm2835_pmx_disable,
881 .gpio_disable_free = bcm2835_pmx_gpio_disable_free, 881 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
882 .gpio_set_direction = bcm2835_pmx_gpio_set_direction, 882 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
883 }; 883 };
884 884
885 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev, 885 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
886 unsigned pin, unsigned long *config) 886 unsigned pin, unsigned long *config)
887 { 887 {
888 /* No way to read back config in HW */ 888 /* No way to read back config in HW */
889 return -ENOTSUPP; 889 return -ENOTSUPP;
890 } 890 }
891 891
892 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, 892 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
893 unsigned pin, unsigned long config) 893 unsigned pin, unsigned long config)
894 { 894 {
895 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 895 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
896 enum bcm2835_pinconf_param param = BCM2835_PINCONF_UNPACK_PARAM(config); 896 enum bcm2835_pinconf_param param = BCM2835_PINCONF_UNPACK_PARAM(config);
897 u16 arg = BCM2835_PINCONF_UNPACK_ARG(config); 897 u16 arg = BCM2835_PINCONF_UNPACK_ARG(config);
898 u32 off, bit; 898 u32 off, bit;
899 899
900 if (param != BCM2835_PINCONF_PARAM_PULL) 900 if (param != BCM2835_PINCONF_PARAM_PULL)
901 return -EINVAL; 901 return -EINVAL;
902 902
903 off = GPIO_REG_OFFSET(pin); 903 off = GPIO_REG_OFFSET(pin);
904 bit = GPIO_REG_SHIFT(pin); 904 bit = GPIO_REG_SHIFT(pin);
905 905
906 bcm2835_gpio_wr(pc, GPPUD, arg & 3); 906 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
907 /* 907 /*
908 * Docs say to wait 150 cycles, but not of what. We assume a 908 * Docs say to wait 150 cycles, but not of what. We assume a
909 * 1 MHz clock here, which is pretty slow... 909 * 1 MHz clock here, which is pretty slow...
910 */ 910 */
911 udelay(150); 911 udelay(150);
912 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); 912 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
913 udelay(150); 913 udelay(150);
914 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); 914 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
915 915
916 return 0; 916 return 0;
917 } 917 }
918 918
919 struct pinconf_ops bcm2835_pinconf_ops = { 919 struct pinconf_ops bcm2835_pinconf_ops = {
920 .pin_config_get = bcm2835_pinconf_get, 920 .pin_config_get = bcm2835_pinconf_get,
921 .pin_config_set = bcm2835_pinconf_set, 921 .pin_config_set = bcm2835_pinconf_set,
922 }; 922 };
923 923
924 static struct pinctrl_desc bcm2835_pinctrl_desc = { 924 static struct pinctrl_desc bcm2835_pinctrl_desc = {
925 .name = MODULE_NAME, 925 .name = MODULE_NAME,
926 .pins = bcm2835_gpio_pins, 926 .pins = bcm2835_gpio_pins,
927 .npins = ARRAY_SIZE(bcm2835_gpio_pins), 927 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
928 .pctlops = &bcm2835_pctl_ops, 928 .pctlops = &bcm2835_pctl_ops,
929 .pmxops = &bcm2835_pmx_ops, 929 .pmxops = &bcm2835_pmx_ops,
930 .confops = &bcm2835_pinconf_ops, 930 .confops = &bcm2835_pinconf_ops,
931 .owner = THIS_MODULE, 931 .owner = THIS_MODULE,
932 }; 932 };
933 933
934 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = { 934 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
935 .name = MODULE_NAME, 935 .name = MODULE_NAME,
936 .npins = BCM2835_NUM_GPIOS, 936 .npins = BCM2835_NUM_GPIOS,
937 }; 937 };
938 938
939 static int __devinit bcm2835_pinctrl_probe(struct platform_device *pdev) 939 static int __devinit bcm2835_pinctrl_probe(struct platform_device *pdev)
940 { 940 {
941 struct device *dev = &pdev->dev; 941 struct device *dev = &pdev->dev;
942 struct device_node *np = dev->of_node; 942 struct device_node *np = dev->of_node;
943 struct bcm2835_pinctrl *pc; 943 struct bcm2835_pinctrl *pc;
944 struct resource iomem; 944 struct resource iomem;
945 int err, i; 945 int err, i;
946 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS); 946 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
947 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS); 947 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
948 948
949 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); 949 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
950 if (!pc) 950 if (!pc)
951 return -ENOMEM; 951 return -ENOMEM;
952 952
953 platform_set_drvdata(pdev, pc); 953 platform_set_drvdata(pdev, pc);
954 pc->dev = dev; 954 pc->dev = dev;
955 955
956 err = of_address_to_resource(np, 0, &iomem); 956 err = of_address_to_resource(np, 0, &iomem);
957 if (err) { 957 if (err) {
958 dev_err(dev, "could not get IO memory\n"); 958 dev_err(dev, "could not get IO memory\n");
959 return err; 959 return err;
960 } 960 }
961 961
962 pc->base = devm_request_and_ioremap(dev, &iomem); 962 pc->base = devm_request_and_ioremap(dev, &iomem);
963 if (!pc->base) 963 if (!pc->base)
964 return -EADDRNOTAVAIL; 964 return -EADDRNOTAVAIL;
965 965
966 pc->gpio_chip = bcm2835_gpio_chip; 966 pc->gpio_chip = bcm2835_gpio_chip;
967 pc->gpio_chip.dev = dev; 967 pc->gpio_chip.dev = dev;
968 pc->gpio_chip.of_node = np; 968 pc->gpio_chip.of_node = np;
969 969
970 pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS, 970 pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS,
971 &irq_domain_simple_ops, NULL); 971 &irq_domain_simple_ops, NULL);
972 if (!pc->irq_domain) { 972 if (!pc->irq_domain) {
973 dev_err(dev, "could not create IRQ domain\n"); 973 dev_err(dev, "could not create IRQ domain\n");
974 return -ENOMEM; 974 return -ENOMEM;
975 } 975 }
976 976
977 for (i = 0; i < BCM2835_NUM_GPIOS; i++) { 977 for (i = 0; i < BCM2835_NUM_GPIOS; i++) {
978 int irq = irq_create_mapping(pc->irq_domain, i); 978 int irq = irq_create_mapping(pc->irq_domain, i);
979 irq_set_lockdep_class(irq, &gpio_lock_class); 979 irq_set_lockdep_class(irq, &gpio_lock_class);
980 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip, 980 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
981 handle_simple_irq); 981 handle_simple_irq);
982 irq_set_chip_data(irq, pc); 982 irq_set_chip_data(irq, pc);
983 set_irq_flags(irq, IRQF_VALID); 983 set_irq_flags(irq, IRQF_VALID);
984 } 984 }
985 985
986 for (i = 0; i < BCM2835_NUM_BANKS; i++) { 986 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
987 unsigned long events; 987 unsigned long events;
988 unsigned offset; 988 unsigned offset;
989 int len; 989 int len;
990 char *name; 990 char *name;
991 991
992 /* clear event detection flags */ 992 /* clear event detection flags */
993 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); 993 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
994 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0); 994 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
995 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0); 995 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
996 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0); 996 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
997 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0); 997 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
998 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0); 998 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
999 999
1000 /* clear all the events */ 1000 /* clear all the events */
1001 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4); 1001 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1002 for_each_set_bit(offset, &events, 32) 1002 for_each_set_bit(offset, &events, 32)
1003 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); 1003 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1004 1004
1005 pc->irq[i] = irq_of_parse_and_map(np, i); 1005 pc->irq[i] = irq_of_parse_and_map(np, i);
1006 pc->irq_data[i].pc = pc; 1006 pc->irq_data[i].pc = pc;
1007 pc->irq_data[i].bank = i; 1007 pc->irq_data[i].bank = i;
1008 spin_lock_init(&pc->irq_lock[i]); 1008 spin_lock_init(&pc->irq_lock[i]);
1009 1009
1010 len = strlen(dev_name(pc->dev)) + 16; 1010 len = strlen(dev_name(pc->dev)) + 16;
1011 name = devm_kzalloc(pc->dev, len, GFP_KERNEL); 1011 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1012 if (!name) 1012 if (!name)
1013 return -ENOMEM; 1013 return -ENOMEM;
1014 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i); 1014 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1015 1015
1016 err = devm_request_irq(dev, pc->irq[i], 1016 err = devm_request_irq(dev, pc->irq[i],
1017 bcm2835_gpio_irq_handler, IRQF_SHARED, 1017 bcm2835_gpio_irq_handler, IRQF_SHARED,
1018 name, &pc->irq_data[i]); 1018 name, &pc->irq_data[i]);
1019 if (err) { 1019 if (err) {
1020 dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]); 1020 dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]);
1021 return err; 1021 return err;
1022 } 1022 }
1023 } 1023 }
1024 1024
1025 err = gpiochip_add(&pc->gpio_chip); 1025 err = gpiochip_add(&pc->gpio_chip);
1026 if (err) { 1026 if (err) {
1027 dev_err(dev, "could not add GPIO chip\n"); 1027 dev_err(dev, "could not add GPIO chip\n");
1028 return err; 1028 return err;
1029 } 1029 }
1030 1030
1031 pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc); 1031 pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc);
1032 if (!pc->pctl_dev) { 1032 if (!pc->pctl_dev) {
1033 gpiochip_remove(&pc->gpio_chip); 1033 gpiochip_remove(&pc->gpio_chip);
1034 return -EINVAL; 1034 return -EINVAL;
1035 } 1035 }
1036 1036
1037 pc->gpio_range = bcm2835_pinctrl_gpio_range; 1037 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1038 pc->gpio_range.base = pc->gpio_chip.base; 1038 pc->gpio_range.base = pc->gpio_chip.base;
1039 pc->gpio_range.gc = &pc->gpio_chip; 1039 pc->gpio_range.gc = &pc->gpio_chip;
1040 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range); 1040 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1041 1041
1042 return 0; 1042 return 0;
1043 } 1043 }
1044 1044
1045 static int __devexit bcm2835_pinctrl_remove(struct platform_device *pdev) 1045 static int bcm2835_pinctrl_remove(struct platform_device *pdev)
1046 { 1046 {
1047 struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev); 1047 struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev);
1048 1048
1049 pinctrl_unregister(pc->pctl_dev); 1049 pinctrl_unregister(pc->pctl_dev);
1050 gpiochip_remove(&pc->gpio_chip); 1050 gpiochip_remove(&pc->gpio_chip);
1051 1051
1052 return 0; 1052 return 0;
1053 } 1053 }
1054 1054
1055 static struct of_device_id bcm2835_pinctrl_match[] = { 1055 static struct of_device_id bcm2835_pinctrl_match[] = {
1056 { .compatible = "brcm,bcm2835-gpio" }, 1056 { .compatible = "brcm,bcm2835-gpio" },
1057 {} 1057 {}
1058 }; 1058 };
1059 MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match); 1059 MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
1060 1060
1061 static struct platform_driver bcm2835_pinctrl_driver = { 1061 static struct platform_driver bcm2835_pinctrl_driver = {
1062 .probe = bcm2835_pinctrl_probe, 1062 .probe = bcm2835_pinctrl_probe,
1063 .remove = bcm2835_pinctrl_remove, 1063 .remove = bcm2835_pinctrl_remove,
1064 .driver = { 1064 .driver = {
1065 .name = MODULE_NAME, 1065 .name = MODULE_NAME,
1066 .owner = THIS_MODULE, 1066 .owner = THIS_MODULE,
1067 .of_match_table = bcm2835_pinctrl_match, 1067 .of_match_table = bcm2835_pinctrl_match,
1068 }, 1068 },
1069 }; 1069 };
1070 module_platform_driver(bcm2835_pinctrl_driver); 1070 module_platform_driver(bcm2835_pinctrl_driver);
1071 1071
1072 MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren"); 1072 MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren");
1073 MODULE_DESCRIPTION("BCM2835 Pin control driver"); 1073 MODULE_DESCRIPTION("BCM2835 Pin control driver");
1074 MODULE_LICENSE("GPL"); 1074 MODULE_LICENSE("GPL");
1075 1075
drivers/pinctrl/pinctrl-imx.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Core driver for the imx pin controller 2 * Core driver for the imx pin controller
3 * 3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc. 4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro Ltd. 5 * Copyright (C) 2012 Linaro Ltd.
6 * 6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org> 7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 */ 13 */
14 14
15 #include <linux/err.h> 15 #include <linux/err.h>
16 #include <linux/init.h> 16 #include <linux/init.h>
17 #include <linux/io.h> 17 #include <linux/io.h>
18 #include <linux/module.h> 18 #include <linux/module.h>
19 #include <linux/of.h> 19 #include <linux/of.h>
20 #include <linux/of_device.h> 20 #include <linux/of_device.h>
21 #include <linux/pinctrl/machine.h> 21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinmux.h>
25 #include <linux/slab.h> 25 #include <linux/slab.h>
26 26
27 #include "core.h" 27 #include "core.h"
28 #include "pinctrl-imx.h" 28 #include "pinctrl-imx.h"
29 29
30 #define IMX_PMX_DUMP(info, p, m, c, n) \ 30 #define IMX_PMX_DUMP(info, p, m, c, n) \
31 { \ 31 { \
32 int i, j; \ 32 int i, j; \
33 printk(KERN_DEBUG "Format: Pin Mux Config\n"); \ 33 printk(KERN_DEBUG "Format: Pin Mux Config\n"); \
34 for (i = 0; i < n; i++) { \ 34 for (i = 0; i < n; i++) { \
35 j = p[i]; \ 35 j = p[i]; \
36 printk(KERN_DEBUG "%s %d 0x%lx\n", \ 36 printk(KERN_DEBUG "%s %d 0x%lx\n", \
37 info->pins[j].name, \ 37 info->pins[j].name, \
38 m[i], c[i]); \ 38 m[i], c[i]); \
39 } \ 39 } \
40 } 40 }
41 41
42 /* The bits in CONFIG cell defined in binding doc*/ 42 /* The bits in CONFIG cell defined in binding doc*/
43 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ 43 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
44 #define IMX_PAD_SION 0x40000000 /* set SION */ 44 #define IMX_PAD_SION 0x40000000 /* set SION */
45 45
46 /** 46 /**
47 * @dev: a pointer back to containing device 47 * @dev: a pointer back to containing device
48 * @base: the offset to the controller in virtual memory 48 * @base: the offset to the controller in virtual memory
49 */ 49 */
50 struct imx_pinctrl { 50 struct imx_pinctrl {
51 struct device *dev; 51 struct device *dev;
52 struct pinctrl_dev *pctl; 52 struct pinctrl_dev *pctl;
53 void __iomem *base; 53 void __iomem *base;
54 const struct imx_pinctrl_soc_info *info; 54 const struct imx_pinctrl_soc_info *info;
55 }; 55 };
56 56
57 static const struct imx_pin_reg *imx_find_pin_reg( 57 static const struct imx_pin_reg *imx_find_pin_reg(
58 const struct imx_pinctrl_soc_info *info, 58 const struct imx_pinctrl_soc_info *info,
59 unsigned pin, bool is_mux, unsigned mux) 59 unsigned pin, bool is_mux, unsigned mux)
60 { 60 {
61 const struct imx_pin_reg *pin_reg = NULL; 61 const struct imx_pin_reg *pin_reg = NULL;
62 int i; 62 int i;
63 63
64 for (i = 0; i < info->npin_regs; i++) { 64 for (i = 0; i < info->npin_regs; i++) {
65 pin_reg = &info->pin_regs[i]; 65 pin_reg = &info->pin_regs[i];
66 if (pin_reg->pid != pin) 66 if (pin_reg->pid != pin)
67 continue; 67 continue;
68 if (!is_mux) 68 if (!is_mux)
69 break; 69 break;
70 else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK)) 70 else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK))
71 break; 71 break;
72 } 72 }
73 73
74 if (!pin_reg) { 74 if (!pin_reg) {
75 dev_err(info->dev, "Pin(%s): unable to find pin reg map\n", 75 dev_err(info->dev, "Pin(%s): unable to find pin reg map\n",
76 info->pins[pin].name); 76 info->pins[pin].name);
77 return NULL; 77 return NULL;
78 } 78 }
79 79
80 return pin_reg; 80 return pin_reg;
81 } 81 }
82 82
83 static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name( 83 static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
84 const struct imx_pinctrl_soc_info *info, 84 const struct imx_pinctrl_soc_info *info,
85 const char *name) 85 const char *name)
86 { 86 {
87 const struct imx_pin_group *grp = NULL; 87 const struct imx_pin_group *grp = NULL;
88 int i; 88 int i;
89 89
90 for (i = 0; i < info->ngroups; i++) { 90 for (i = 0; i < info->ngroups; i++) {
91 if (!strcmp(info->groups[i].name, name)) { 91 if (!strcmp(info->groups[i].name, name)) {
92 grp = &info->groups[i]; 92 grp = &info->groups[i];
93 break; 93 break;
94 } 94 }
95 } 95 }
96 96
97 return grp; 97 return grp;
98 } 98 }
99 99
100 static int imx_get_groups_count(struct pinctrl_dev *pctldev) 100 static int imx_get_groups_count(struct pinctrl_dev *pctldev)
101 { 101 {
102 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 102 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
103 const struct imx_pinctrl_soc_info *info = ipctl->info; 103 const struct imx_pinctrl_soc_info *info = ipctl->info;
104 104
105 return info->ngroups; 105 return info->ngroups;
106 } 106 }
107 107
108 static const char *imx_get_group_name(struct pinctrl_dev *pctldev, 108 static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
109 unsigned selector) 109 unsigned selector)
110 { 110 {
111 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 111 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
112 const struct imx_pinctrl_soc_info *info = ipctl->info; 112 const struct imx_pinctrl_soc_info *info = ipctl->info;
113 113
114 return info->groups[selector].name; 114 return info->groups[selector].name;
115 } 115 }
116 116
117 static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 117 static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
118 const unsigned **pins, 118 const unsigned **pins,
119 unsigned *npins) 119 unsigned *npins)
120 { 120 {
121 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 121 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
122 const struct imx_pinctrl_soc_info *info = ipctl->info; 122 const struct imx_pinctrl_soc_info *info = ipctl->info;
123 123
124 if (selector >= info->ngroups) 124 if (selector >= info->ngroups)
125 return -EINVAL; 125 return -EINVAL;
126 126
127 *pins = info->groups[selector].pins; 127 *pins = info->groups[selector].pins;
128 *npins = info->groups[selector].npins; 128 *npins = info->groups[selector].npins;
129 129
130 return 0; 130 return 0;
131 } 131 }
132 132
133 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 133 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
134 unsigned offset) 134 unsigned offset)
135 { 135 {
136 seq_printf(s, "%s", dev_name(pctldev->dev)); 136 seq_printf(s, "%s", dev_name(pctldev->dev));
137 } 137 }
138 138
139 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, 139 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
140 struct device_node *np, 140 struct device_node *np,
141 struct pinctrl_map **map, unsigned *num_maps) 141 struct pinctrl_map **map, unsigned *num_maps)
142 { 142 {
143 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 143 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
144 const struct imx_pinctrl_soc_info *info = ipctl->info; 144 const struct imx_pinctrl_soc_info *info = ipctl->info;
145 const struct imx_pin_group *grp; 145 const struct imx_pin_group *grp;
146 struct pinctrl_map *new_map; 146 struct pinctrl_map *new_map;
147 struct device_node *parent; 147 struct device_node *parent;
148 int map_num = 1; 148 int map_num = 1;
149 int i, j; 149 int i, j;
150 150
151 /* 151 /*
152 * first find the group of this node and check if we need create 152 * first find the group of this node and check if we need create
153 * config maps for pins 153 * config maps for pins
154 */ 154 */
155 grp = imx_pinctrl_find_group_by_name(info, np->name); 155 grp = imx_pinctrl_find_group_by_name(info, np->name);
156 if (!grp) { 156 if (!grp) {
157 dev_err(info->dev, "unable to find group for node %s\n", 157 dev_err(info->dev, "unable to find group for node %s\n",
158 np->name); 158 np->name);
159 return -EINVAL; 159 return -EINVAL;
160 } 160 }
161 161
162 for (i = 0; i < grp->npins; i++) { 162 for (i = 0; i < grp->npins; i++) {
163 if (!(grp->configs[i] & IMX_NO_PAD_CTL)) 163 if (!(grp->configs[i] & IMX_NO_PAD_CTL))
164 map_num++; 164 map_num++;
165 } 165 }
166 166
167 new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); 167 new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
168 if (!new_map) 168 if (!new_map)
169 return -ENOMEM; 169 return -ENOMEM;
170 170
171 *map = new_map; 171 *map = new_map;
172 *num_maps = map_num; 172 *num_maps = map_num;
173 173
174 /* create mux map */ 174 /* create mux map */
175 parent = of_get_parent(np); 175 parent = of_get_parent(np);
176 if (!parent) { 176 if (!parent) {
177 kfree(new_map); 177 kfree(new_map);
178 return -EINVAL; 178 return -EINVAL;
179 } 179 }
180 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 180 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
181 new_map[0].data.mux.function = parent->name; 181 new_map[0].data.mux.function = parent->name;
182 new_map[0].data.mux.group = np->name; 182 new_map[0].data.mux.group = np->name;
183 of_node_put(parent); 183 of_node_put(parent);
184 184
185 /* create config map */ 185 /* create config map */
186 new_map++; 186 new_map++;
187 for (i = j = 0; i < grp->npins; i++) { 187 for (i = j = 0; i < grp->npins; i++) {
188 if (!(grp->configs[i] & IMX_NO_PAD_CTL)) { 188 if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
189 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; 189 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
190 new_map[j].data.configs.group_or_pin = 190 new_map[j].data.configs.group_or_pin =
191 pin_get_name(pctldev, grp->pins[i]); 191 pin_get_name(pctldev, grp->pins[i]);
192 new_map[j].data.configs.configs = &grp->configs[i]; 192 new_map[j].data.configs.configs = &grp->configs[i];
193 new_map[j].data.configs.num_configs = 1; 193 new_map[j].data.configs.num_configs = 1;
194 j++; 194 j++;
195 } 195 }
196 } 196 }
197 197
198 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 198 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
199 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 199 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
200 200
201 return 0; 201 return 0;
202 } 202 }
203 203
204 static void imx_dt_free_map(struct pinctrl_dev *pctldev, 204 static void imx_dt_free_map(struct pinctrl_dev *pctldev,
205 struct pinctrl_map *map, unsigned num_maps) 205 struct pinctrl_map *map, unsigned num_maps)
206 { 206 {
207 kfree(map); 207 kfree(map);
208 } 208 }
209 209
210 static struct pinctrl_ops imx_pctrl_ops = { 210 static struct pinctrl_ops imx_pctrl_ops = {
211 .get_groups_count = imx_get_groups_count, 211 .get_groups_count = imx_get_groups_count,
212 .get_group_name = imx_get_group_name, 212 .get_group_name = imx_get_group_name,
213 .get_group_pins = imx_get_group_pins, 213 .get_group_pins = imx_get_group_pins,
214 .pin_dbg_show = imx_pin_dbg_show, 214 .pin_dbg_show = imx_pin_dbg_show,
215 .dt_node_to_map = imx_dt_node_to_map, 215 .dt_node_to_map = imx_dt_node_to_map,
216 .dt_free_map = imx_dt_free_map, 216 .dt_free_map = imx_dt_free_map,
217 217
218 }; 218 };
219 219
220 static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 220 static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
221 unsigned group) 221 unsigned group)
222 { 222 {
223 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 223 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
224 const struct imx_pinctrl_soc_info *info = ipctl->info; 224 const struct imx_pinctrl_soc_info *info = ipctl->info;
225 const struct imx_pin_reg *pin_reg; 225 const struct imx_pin_reg *pin_reg;
226 const unsigned *pins, *mux; 226 const unsigned *pins, *mux;
227 unsigned int npins, pin_id; 227 unsigned int npins, pin_id;
228 int i; 228 int i;
229 229
230 /* 230 /*
231 * Configure the mux mode for each pin in the group for a specific 231 * Configure the mux mode for each pin in the group for a specific
232 * function. 232 * function.
233 */ 233 */
234 pins = info->groups[group].pins; 234 pins = info->groups[group].pins;
235 npins = info->groups[group].npins; 235 npins = info->groups[group].npins;
236 mux = info->groups[group].mux_mode; 236 mux = info->groups[group].mux_mode;
237 237
238 WARN_ON(!pins || !npins || !mux); 238 WARN_ON(!pins || !npins || !mux);
239 239
240 dev_dbg(ipctl->dev, "enable function %s group %s\n", 240 dev_dbg(ipctl->dev, "enable function %s group %s\n",
241 info->functions[selector].name, info->groups[group].name); 241 info->functions[selector].name, info->groups[group].name);
242 242
243 for (i = 0; i < npins; i++) { 243 for (i = 0; i < npins; i++) {
244 pin_id = pins[i]; 244 pin_id = pins[i];
245 245
246 pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]); 246 pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]);
247 if (!pin_reg) 247 if (!pin_reg)
248 return -EINVAL; 248 return -EINVAL;
249 249
250 if (!pin_reg->mux_reg) { 250 if (!pin_reg->mux_reg) {
251 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", 251 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
252 info->pins[pin_id].name); 252 info->pins[pin_id].name);
253 return -EINVAL; 253 return -EINVAL;
254 } 254 }
255 255
256 writel(mux[i], ipctl->base + pin_reg->mux_reg); 256 writel(mux[i], ipctl->base + pin_reg->mux_reg);
257 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 257 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
258 pin_reg->mux_reg, mux[i]); 258 pin_reg->mux_reg, mux[i]);
259 259
260 /* some pins also need select input setting, set it if found */ 260 /* some pins also need select input setting, set it if found */
261 if (pin_reg->input_reg) { 261 if (pin_reg->input_reg) {
262 writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg); 262 writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg);
263 dev_dbg(ipctl->dev, 263 dev_dbg(ipctl->dev,
264 "==>select_input: offset 0x%x val 0x%x\n", 264 "==>select_input: offset 0x%x val 0x%x\n",
265 pin_reg->input_reg, pin_reg->input_val); 265 pin_reg->input_reg, pin_reg->input_val);
266 } 266 }
267 } 267 }
268 268
269 return 0; 269 return 0;
270 } 270 }
271 271
272 static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 272 static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
273 { 273 {
274 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 274 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
275 const struct imx_pinctrl_soc_info *info = ipctl->info; 275 const struct imx_pinctrl_soc_info *info = ipctl->info;
276 276
277 return info->nfunctions; 277 return info->nfunctions;
278 } 278 }
279 279
280 static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev, 280 static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
281 unsigned selector) 281 unsigned selector)
282 { 282 {
283 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 283 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
284 const struct imx_pinctrl_soc_info *info = ipctl->info; 284 const struct imx_pinctrl_soc_info *info = ipctl->info;
285 285
286 return info->functions[selector].name; 286 return info->functions[selector].name;
287 } 287 }
288 288
289 static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 289 static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
290 const char * const **groups, 290 const char * const **groups,
291 unsigned * const num_groups) 291 unsigned * const num_groups)
292 { 292 {
293 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 293 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
294 const struct imx_pinctrl_soc_info *info = ipctl->info; 294 const struct imx_pinctrl_soc_info *info = ipctl->info;
295 295
296 *groups = info->functions[selector].groups; 296 *groups = info->functions[selector].groups;
297 *num_groups = info->functions[selector].num_groups; 297 *num_groups = info->functions[selector].num_groups;
298 298
299 return 0; 299 return 0;
300 } 300 }
301 301
302 static struct pinmux_ops imx_pmx_ops = { 302 static struct pinmux_ops imx_pmx_ops = {
303 .get_functions_count = imx_pmx_get_funcs_count, 303 .get_functions_count = imx_pmx_get_funcs_count,
304 .get_function_name = imx_pmx_get_func_name, 304 .get_function_name = imx_pmx_get_func_name,
305 .get_function_groups = imx_pmx_get_groups, 305 .get_function_groups = imx_pmx_get_groups,
306 .enable = imx_pmx_enable, 306 .enable = imx_pmx_enable,
307 }; 307 };
308 308
309 static int imx_pinconf_get(struct pinctrl_dev *pctldev, 309 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
310 unsigned pin_id, unsigned long *config) 310 unsigned pin_id, unsigned long *config)
311 { 311 {
312 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 312 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
313 const struct imx_pinctrl_soc_info *info = ipctl->info; 313 const struct imx_pinctrl_soc_info *info = ipctl->info;
314 const struct imx_pin_reg *pin_reg; 314 const struct imx_pin_reg *pin_reg;
315 315
316 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); 316 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
317 if (!pin_reg) 317 if (!pin_reg)
318 return -EINVAL; 318 return -EINVAL;
319 319
320 if (!pin_reg->conf_reg) { 320 if (!pin_reg->conf_reg) {
321 dev_err(info->dev, "Pin(%s) does not support config function\n", 321 dev_err(info->dev, "Pin(%s) does not support config function\n",
322 info->pins[pin_id].name); 322 info->pins[pin_id].name);
323 return -EINVAL; 323 return -EINVAL;
324 } 324 }
325 325
326 *config = readl(ipctl->base + pin_reg->conf_reg); 326 *config = readl(ipctl->base + pin_reg->conf_reg);
327 327
328 return 0; 328 return 0;
329 } 329 }
330 330
331 static int imx_pinconf_set(struct pinctrl_dev *pctldev, 331 static int imx_pinconf_set(struct pinctrl_dev *pctldev,
332 unsigned pin_id, unsigned long config) 332 unsigned pin_id, unsigned long config)
333 { 333 {
334 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 334 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
335 const struct imx_pinctrl_soc_info *info = ipctl->info; 335 const struct imx_pinctrl_soc_info *info = ipctl->info;
336 const struct imx_pin_reg *pin_reg; 336 const struct imx_pin_reg *pin_reg;
337 337
338 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); 338 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
339 if (!pin_reg) 339 if (!pin_reg)
340 return -EINVAL; 340 return -EINVAL;
341 341
342 if (!pin_reg->conf_reg) { 342 if (!pin_reg->conf_reg) {
343 dev_err(info->dev, "Pin(%s) does not support config function\n", 343 dev_err(info->dev, "Pin(%s) does not support config function\n",
344 info->pins[pin_id].name); 344 info->pins[pin_id].name);
345 return -EINVAL; 345 return -EINVAL;
346 } 346 }
347 347
348 dev_dbg(ipctl->dev, "pinconf set pin %s\n", 348 dev_dbg(ipctl->dev, "pinconf set pin %s\n",
349 info->pins[pin_id].name); 349 info->pins[pin_id].name);
350 350
351 writel(config, ipctl->base + pin_reg->conf_reg); 351 writel(config, ipctl->base + pin_reg->conf_reg);
352 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", 352 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
353 pin_reg->conf_reg, config); 353 pin_reg->conf_reg, config);
354 354
355 return 0; 355 return 0;
356 } 356 }
357 357
358 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 358 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
359 struct seq_file *s, unsigned pin_id) 359 struct seq_file *s, unsigned pin_id)
360 { 360 {
361 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 361 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
362 const struct imx_pinctrl_soc_info *info = ipctl->info; 362 const struct imx_pinctrl_soc_info *info = ipctl->info;
363 const struct imx_pin_reg *pin_reg; 363 const struct imx_pin_reg *pin_reg;
364 unsigned long config; 364 unsigned long config;
365 365
366 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); 366 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
367 if (!pin_reg || !pin_reg->conf_reg) { 367 if (!pin_reg || !pin_reg->conf_reg) {
368 seq_printf(s, "N/A"); 368 seq_printf(s, "N/A");
369 return; 369 return;
370 } 370 }
371 371
372 config = readl(ipctl->base + pin_reg->conf_reg); 372 config = readl(ipctl->base + pin_reg->conf_reg);
373 seq_printf(s, "0x%lx", config); 373 seq_printf(s, "0x%lx", config);
374 } 374 }
375 375
376 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 376 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
377 struct seq_file *s, unsigned group) 377 struct seq_file *s, unsigned group)
378 { 378 {
379 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 379 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
380 const struct imx_pinctrl_soc_info *info = ipctl->info; 380 const struct imx_pinctrl_soc_info *info = ipctl->info;
381 struct imx_pin_group *grp; 381 struct imx_pin_group *grp;
382 unsigned long config; 382 unsigned long config;
383 const char *name; 383 const char *name;
384 int i, ret; 384 int i, ret;
385 385
386 if (group > info->ngroups) 386 if (group > info->ngroups)
387 return; 387 return;
388 388
389 seq_printf(s, "\n"); 389 seq_printf(s, "\n");
390 grp = &info->groups[group]; 390 grp = &info->groups[group];
391 for (i = 0; i < grp->npins; i++) { 391 for (i = 0; i < grp->npins; i++) {
392 name = pin_get_name(pctldev, grp->pins[i]); 392 name = pin_get_name(pctldev, grp->pins[i]);
393 ret = imx_pinconf_get(pctldev, grp->pins[i], &config); 393 ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
394 if (ret) 394 if (ret)
395 return; 395 return;
396 seq_printf(s, "%s: 0x%lx", name, config); 396 seq_printf(s, "%s: 0x%lx", name, config);
397 } 397 }
398 } 398 }
399 399
400 struct pinconf_ops imx_pinconf_ops = { 400 struct pinconf_ops imx_pinconf_ops = {
401 .pin_config_get = imx_pinconf_get, 401 .pin_config_get = imx_pinconf_get,
402 .pin_config_set = imx_pinconf_set, 402 .pin_config_set = imx_pinconf_set,
403 .pin_config_dbg_show = imx_pinconf_dbg_show, 403 .pin_config_dbg_show = imx_pinconf_dbg_show,
404 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, 404 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
405 }; 405 };
406 406
407 static struct pinctrl_desc imx_pinctrl_desc = { 407 static struct pinctrl_desc imx_pinctrl_desc = {
408 .pctlops = &imx_pctrl_ops, 408 .pctlops = &imx_pctrl_ops,
409 .pmxops = &imx_pmx_ops, 409 .pmxops = &imx_pmx_ops,
410 .confops = &imx_pinconf_ops, 410 .confops = &imx_pinconf_ops,
411 .owner = THIS_MODULE, 411 .owner = THIS_MODULE,
412 }; 412 };
413 413
414 /* decode pin id and mux from pin function id got from device tree*/ 414 /* decode pin id and mux from pin function id got from device tree*/
415 static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info, 415 static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info,
416 unsigned int pin_func_id, unsigned int *pin_id, 416 unsigned int pin_func_id, unsigned int *pin_id,
417 unsigned int *mux) 417 unsigned int *mux)
418 { 418 {
419 if (pin_func_id > info->npin_regs) 419 if (pin_func_id > info->npin_regs)
420 return -EINVAL; 420 return -EINVAL;
421 421
422 *pin_id = info->pin_regs[pin_func_id].pid; 422 *pin_id = info->pin_regs[pin_func_id].pid;
423 *mux = info->pin_regs[pin_func_id].mux_mode; 423 *mux = info->pin_regs[pin_func_id].mux_mode;
424 424
425 return 0; 425 return 0;
426 } 426 }
427 427
428 static int __devinit imx_pinctrl_parse_groups(struct device_node *np, 428 static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
429 struct imx_pin_group *grp, 429 struct imx_pin_group *grp,
430 struct imx_pinctrl_soc_info *info, 430 struct imx_pinctrl_soc_info *info,
431 u32 index) 431 u32 index)
432 { 432 {
433 unsigned int pin_func_id; 433 unsigned int pin_func_id;
434 int ret, size; 434 int ret, size;
435 const __be32 *list; 435 const __be32 *list;
436 int i, j; 436 int i, j;
437 u32 config; 437 u32 config;
438 438
439 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 439 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
440 440
441 /* Initialise group */ 441 /* Initialise group */
442 grp->name = np->name; 442 grp->name = np->name;
443 443
444 /* 444 /*
445 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, 445 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
446 * do sanity check and calculate pins number 446 * do sanity check and calculate pins number
447 */ 447 */
448 list = of_get_property(np, "fsl,pins", &size); 448 list = of_get_property(np, "fsl,pins", &size);
449 /* we do not check return since it's safe node passed down */ 449 /* we do not check return since it's safe node passed down */
450 size /= sizeof(*list); 450 size /= sizeof(*list);
451 if (!size || size % 2) { 451 if (!size || size % 2) {
452 dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n"); 452 dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n");
453 return -EINVAL; 453 return -EINVAL;
454 } 454 }
455 455
456 grp->npins = size / 2; 456 grp->npins = size / 2;
457 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 457 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
458 GFP_KERNEL); 458 GFP_KERNEL);
459 grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 459 grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
460 GFP_KERNEL); 460 GFP_KERNEL);
461 grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long), 461 grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
462 GFP_KERNEL); 462 GFP_KERNEL);
463 for (i = 0, j = 0; i < size; i += 2, j++) { 463 for (i = 0, j = 0; i < size; i += 2, j++) {
464 pin_func_id = be32_to_cpu(*list++); 464 pin_func_id = be32_to_cpu(*list++);
465 ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id, 465 ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id,
466 &grp->pins[j], &grp->mux_mode[j]); 466 &grp->pins[j], &grp->mux_mode[j]);
467 if (ret) { 467 if (ret) {
468 dev_err(info->dev, "get invalid pin function id\n"); 468 dev_err(info->dev, "get invalid pin function id\n");
469 return -EINVAL; 469 return -EINVAL;
470 } 470 }
471 /* SION bit is in mux register */ 471 /* SION bit is in mux register */
472 config = be32_to_cpu(*list++); 472 config = be32_to_cpu(*list++);
473 if (config & IMX_PAD_SION) 473 if (config & IMX_PAD_SION)
474 grp->mux_mode[j] |= IOMUXC_CONFIG_SION; 474 grp->mux_mode[j] |= IOMUXC_CONFIG_SION;
475 grp->configs[j] = config & ~IMX_PAD_SION; 475 grp->configs[j] = config & ~IMX_PAD_SION;
476 } 476 }
477 477
478 #ifdef DEBUG 478 #ifdef DEBUG
479 IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins); 479 IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
480 #endif 480 #endif
481 481
482 return 0; 482 return 0;
483 } 483 }
484 484
485 static int __devinit imx_pinctrl_parse_functions(struct device_node *np, 485 static int __devinit imx_pinctrl_parse_functions(struct device_node *np,
486 struct imx_pinctrl_soc_info *info, u32 index) 486 struct imx_pinctrl_soc_info *info, u32 index)
487 { 487 {
488 struct device_node *child; 488 struct device_node *child;
489 struct imx_pmx_func *func; 489 struct imx_pmx_func *func;
490 struct imx_pin_group *grp; 490 struct imx_pin_group *grp;
491 int ret; 491 int ret;
492 static u32 grp_index; 492 static u32 grp_index;
493 u32 i = 0; 493 u32 i = 0;
494 494
495 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 495 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
496 496
497 func = &info->functions[index]; 497 func = &info->functions[index];
498 498
499 /* Initialise function */ 499 /* Initialise function */
500 func->name = np->name; 500 func->name = np->name;
501 func->num_groups = of_get_child_count(np); 501 func->num_groups = of_get_child_count(np);
502 if (func->num_groups <= 0) { 502 if (func->num_groups <= 0) {
503 dev_err(info->dev, "no groups defined\n"); 503 dev_err(info->dev, "no groups defined\n");
504 return -EINVAL; 504 return -EINVAL;
505 } 505 }
506 func->groups = devm_kzalloc(info->dev, 506 func->groups = devm_kzalloc(info->dev,
507 func->num_groups * sizeof(char *), GFP_KERNEL); 507 func->num_groups * sizeof(char *), GFP_KERNEL);
508 508
509 for_each_child_of_node(np, child) { 509 for_each_child_of_node(np, child) {
510 func->groups[i] = child->name; 510 func->groups[i] = child->name;
511 grp = &info->groups[grp_index++]; 511 grp = &info->groups[grp_index++];
512 ret = imx_pinctrl_parse_groups(child, grp, info, i++); 512 ret = imx_pinctrl_parse_groups(child, grp, info, i++);
513 if (ret) 513 if (ret)
514 return ret; 514 return ret;
515 } 515 }
516 516
517 return 0; 517 return 0;
518 } 518 }
519 519
520 static int __devinit imx_pinctrl_probe_dt(struct platform_device *pdev, 520 static int __devinit imx_pinctrl_probe_dt(struct platform_device *pdev,
521 struct imx_pinctrl_soc_info *info) 521 struct imx_pinctrl_soc_info *info)
522 { 522 {
523 struct device_node *np = pdev->dev.of_node; 523 struct device_node *np = pdev->dev.of_node;
524 struct device_node *child; 524 struct device_node *child;
525 int ret; 525 int ret;
526 u32 nfuncs = 0; 526 u32 nfuncs = 0;
527 u32 i = 0; 527 u32 i = 0;
528 528
529 if (!np) 529 if (!np)
530 return -ENODEV; 530 return -ENODEV;
531 531
532 nfuncs = of_get_child_count(np); 532 nfuncs = of_get_child_count(np);
533 if (nfuncs <= 0) { 533 if (nfuncs <= 0) {
534 dev_err(&pdev->dev, "no functions defined\n"); 534 dev_err(&pdev->dev, "no functions defined\n");
535 return -EINVAL; 535 return -EINVAL;
536 } 536 }
537 537
538 info->nfunctions = nfuncs; 538 info->nfunctions = nfuncs;
539 info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func), 539 info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
540 GFP_KERNEL); 540 GFP_KERNEL);
541 if (!info->functions) 541 if (!info->functions)
542 return -ENOMEM; 542 return -ENOMEM;
543 543
544 info->ngroups = 0; 544 info->ngroups = 0;
545 for_each_child_of_node(np, child) 545 for_each_child_of_node(np, child)
546 info->ngroups += of_get_child_count(child); 546 info->ngroups += of_get_child_count(child);
547 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group), 547 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
548 GFP_KERNEL); 548 GFP_KERNEL);
549 if (!info->groups) 549 if (!info->groups)
550 return -ENOMEM; 550 return -ENOMEM;
551 551
552 for_each_child_of_node(np, child) { 552 for_each_child_of_node(np, child) {
553 ret = imx_pinctrl_parse_functions(child, info, i++); 553 ret = imx_pinctrl_parse_functions(child, info, i++);
554 if (ret) { 554 if (ret) {
555 dev_err(&pdev->dev, "failed to parse function\n"); 555 dev_err(&pdev->dev, "failed to parse function\n");
556 return ret; 556 return ret;
557 } 557 }
558 } 558 }
559 559
560 return 0; 560 return 0;
561 } 561 }
562 562
563 int __devinit imx_pinctrl_probe(struct platform_device *pdev, 563 int __devinit imx_pinctrl_probe(struct platform_device *pdev,
564 struct imx_pinctrl_soc_info *info) 564 struct imx_pinctrl_soc_info *info)
565 { 565 {
566 struct imx_pinctrl *ipctl; 566 struct imx_pinctrl *ipctl;
567 struct resource *res; 567 struct resource *res;
568 int ret; 568 int ret;
569 569
570 if (!info || !info->pins || !info->npins 570 if (!info || !info->pins || !info->npins
571 || !info->pin_regs || !info->npin_regs) { 571 || !info->pin_regs || !info->npin_regs) {
572 dev_err(&pdev->dev, "wrong pinctrl info\n"); 572 dev_err(&pdev->dev, "wrong pinctrl info\n");
573 return -EINVAL; 573 return -EINVAL;
574 } 574 }
575 info->dev = &pdev->dev; 575 info->dev = &pdev->dev;
576 576
577 /* Create state holders etc for this driver */ 577 /* Create state holders etc for this driver */
578 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 578 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
579 if (!ipctl) 579 if (!ipctl)
580 return -ENOMEM; 580 return -ENOMEM;
581 581
582 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 582 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
583 if (!res) 583 if (!res)
584 return -ENOENT; 584 return -ENOENT;
585 585
586 ipctl->base = devm_request_and_ioremap(&pdev->dev, res); 586 ipctl->base = devm_request_and_ioremap(&pdev->dev, res);
587 if (!ipctl->base) 587 if (!ipctl->base)
588 return -EBUSY; 588 return -EBUSY;
589 589
590 imx_pinctrl_desc.name = dev_name(&pdev->dev); 590 imx_pinctrl_desc.name = dev_name(&pdev->dev);
591 imx_pinctrl_desc.pins = info->pins; 591 imx_pinctrl_desc.pins = info->pins;
592 imx_pinctrl_desc.npins = info->npins; 592 imx_pinctrl_desc.npins = info->npins;
593 593
594 ret = imx_pinctrl_probe_dt(pdev, info); 594 ret = imx_pinctrl_probe_dt(pdev, info);
595 if (ret) { 595 if (ret) {
596 dev_err(&pdev->dev, "fail to probe dt properties\n"); 596 dev_err(&pdev->dev, "fail to probe dt properties\n");
597 return ret; 597 return ret;
598 } 598 }
599 599
600 ipctl->info = info; 600 ipctl->info = info;
601 ipctl->dev = info->dev; 601 ipctl->dev = info->dev;
602 platform_set_drvdata(pdev, ipctl); 602 platform_set_drvdata(pdev, ipctl);
603 ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl); 603 ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
604 if (!ipctl->pctl) { 604 if (!ipctl->pctl) {
605 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); 605 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
606 return -EINVAL; 606 return -EINVAL;
607 } 607 }
608 608
609 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 609 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
610 610
611 return 0; 611 return 0;
612 } 612 }
613 613
614 int __devexit imx_pinctrl_remove(struct platform_device *pdev) 614 int imx_pinctrl_remove(struct platform_device *pdev)
615 { 615 {
616 struct imx_pinctrl *ipctl = platform_get_drvdata(pdev); 616 struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
617 617
618 pinctrl_unregister(ipctl->pctl); 618 pinctrl_unregister(ipctl->pctl);
619 619
620 return 0; 620 return 0;
621 } 621 }
622 622
drivers/pinctrl/pinctrl-mmp2.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * linux/drivers/pinctrl/pinmux-mmp2.c 2 * linux/drivers/pinctrl/pinmux-mmp2.c
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * publishhed by the Free Software Foundation. 6 * publishhed by the Free Software Foundation.
7 * 7 *
8 * Copyright (C) 2011, Marvell Technology Group Ltd. 8 * Copyright (C) 2011, Marvell Technology Group Ltd.
9 * 9 *
10 * Author: Haojian Zhuang <haojian.zhuang@marvell.com> 10 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
11 * 11 *
12 */ 12 */
13 13
14 #include <linux/device.h> 14 #include <linux/device.h>
15 #include <linux/module.h> 15 #include <linux/module.h>
16 #include <linux/io.h> 16 #include <linux/io.h>
17 #include <linux/platform_device.h> 17 #include <linux/platform_device.h>
18 #include "pinctrl-pxa3xx.h" 18 #include "pinctrl-pxa3xx.h"
19 19
20 #define MMP2_DS_MASK 0x1800 20 #define MMP2_DS_MASK 0x1800
21 #define MMP2_DS_SHIFT 11 21 #define MMP2_DS_SHIFT 11
22 #define MMP2_SLEEP_MASK 0x38 22 #define MMP2_SLEEP_MASK 0x38
23 #define MMP2_SLEEP_SELECT (1 << 9) 23 #define MMP2_SLEEP_SELECT (1 << 9)
24 #define MMP2_SLEEP_DATA (1 << 8) 24 #define MMP2_SLEEP_DATA (1 << 8)
25 #define MMP2_SLEEP_DIR (1 << 7) 25 #define MMP2_SLEEP_DIR (1 << 7)
26 26
27 #define MFPR_MMP2(a, r, f0, f1, f2, f3, f4, f5, f6, f7) \ 27 #define MFPR_MMP2(a, r, f0, f1, f2, f3, f4, f5, f6, f7) \
28 { \ 28 { \
29 .name = #a, \ 29 .name = #a, \
30 .pin = a, \ 30 .pin = a, \
31 .mfpr = r, \ 31 .mfpr = r, \
32 .func = { \ 32 .func = { \
33 MMP2_MUX_##f0, \ 33 MMP2_MUX_##f0, \
34 MMP2_MUX_##f1, \ 34 MMP2_MUX_##f1, \
35 MMP2_MUX_##f2, \ 35 MMP2_MUX_##f2, \
36 MMP2_MUX_##f3, \ 36 MMP2_MUX_##f3, \
37 MMP2_MUX_##f4, \ 37 MMP2_MUX_##f4, \
38 MMP2_MUX_##f5, \ 38 MMP2_MUX_##f5, \
39 MMP2_MUX_##f6, \ 39 MMP2_MUX_##f6, \
40 MMP2_MUX_##f7, \ 40 MMP2_MUX_##f7, \
41 }, \ 41 }, \
42 } 42 }
43 43
44 #define GRP_MMP2(a, m, p) \ 44 #define GRP_MMP2(a, m, p) \
45 { .name = a, .mux = MMP2_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), } 45 { .name = a, .mux = MMP2_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
46 46
47 /* 174 pins */ 47 /* 174 pins */
48 enum mmp2_pin_list { 48 enum mmp2_pin_list {
49 /* 0~168: GPIO0~GPIO168 */ 49 /* 0~168: GPIO0~GPIO168 */
50 TWSI4_SCL = 169, 50 TWSI4_SCL = 169,
51 TWSI4_SDA, /* 170 */ 51 TWSI4_SDA, /* 170 */
52 G_CLKREQ, 52 G_CLKREQ,
53 VCXO_REQ, 53 VCXO_REQ,
54 VCXO_OUT, 54 VCXO_OUT,
55 }; 55 };
56 56
57 enum mmp2_mux { 57 enum mmp2_mux {
58 /* PXA3xx_MUX_GPIO = 0 (predefined in pinctrl-pxa3xx.h) */ 58 /* PXA3xx_MUX_GPIO = 0 (predefined in pinctrl-pxa3xx.h) */
59 MMP2_MUX_GPIO = 0, 59 MMP2_MUX_GPIO = 0,
60 MMP2_MUX_G_CLKREQ, 60 MMP2_MUX_G_CLKREQ,
61 MMP2_MUX_VCXO_REQ, 61 MMP2_MUX_VCXO_REQ,
62 MMP2_MUX_VCXO_OUT, 62 MMP2_MUX_VCXO_OUT,
63 MMP2_MUX_KP_MK, 63 MMP2_MUX_KP_MK,
64 MMP2_MUX_KP_DK, 64 MMP2_MUX_KP_DK,
65 MMP2_MUX_CCIC1, 65 MMP2_MUX_CCIC1,
66 MMP2_MUX_CCIC2, 66 MMP2_MUX_CCIC2,
67 MMP2_MUX_SPI, 67 MMP2_MUX_SPI,
68 MMP2_MUX_SSPA2, 68 MMP2_MUX_SSPA2,
69 MMP2_MUX_ROT, 69 MMP2_MUX_ROT,
70 MMP2_MUX_I2S, 70 MMP2_MUX_I2S,
71 MMP2_MUX_TB, 71 MMP2_MUX_TB,
72 MMP2_MUX_CAM2, 72 MMP2_MUX_CAM2,
73 MMP2_MUX_HDMI, 73 MMP2_MUX_HDMI,
74 MMP2_MUX_TWSI2, 74 MMP2_MUX_TWSI2,
75 MMP2_MUX_TWSI3, 75 MMP2_MUX_TWSI3,
76 MMP2_MUX_TWSI4, 76 MMP2_MUX_TWSI4,
77 MMP2_MUX_TWSI5, 77 MMP2_MUX_TWSI5,
78 MMP2_MUX_TWSI6, 78 MMP2_MUX_TWSI6,
79 MMP2_MUX_UART1, 79 MMP2_MUX_UART1,
80 MMP2_MUX_UART2, 80 MMP2_MUX_UART2,
81 MMP2_MUX_UART3, 81 MMP2_MUX_UART3,
82 MMP2_MUX_UART4, 82 MMP2_MUX_UART4,
83 MMP2_MUX_SSP1_RX, 83 MMP2_MUX_SSP1_RX,
84 MMP2_MUX_SSP1_FRM, 84 MMP2_MUX_SSP1_FRM,
85 MMP2_MUX_SSP1_TXRX, 85 MMP2_MUX_SSP1_TXRX,
86 MMP2_MUX_SSP2_RX, 86 MMP2_MUX_SSP2_RX,
87 MMP2_MUX_SSP2_FRM, 87 MMP2_MUX_SSP2_FRM,
88 MMP2_MUX_SSP1, 88 MMP2_MUX_SSP1,
89 MMP2_MUX_SSP2, 89 MMP2_MUX_SSP2,
90 MMP2_MUX_SSP3, 90 MMP2_MUX_SSP3,
91 MMP2_MUX_SSP4, 91 MMP2_MUX_SSP4,
92 MMP2_MUX_MMC1, 92 MMP2_MUX_MMC1,
93 MMP2_MUX_MMC2, 93 MMP2_MUX_MMC2,
94 MMP2_MUX_MMC3, 94 MMP2_MUX_MMC3,
95 MMP2_MUX_MMC4, 95 MMP2_MUX_MMC4,
96 MMP2_MUX_ULPI, 96 MMP2_MUX_ULPI,
97 MMP2_MUX_AC, 97 MMP2_MUX_AC,
98 MMP2_MUX_CA, 98 MMP2_MUX_CA,
99 MMP2_MUX_PWM, 99 MMP2_MUX_PWM,
100 MMP2_MUX_USIM, 100 MMP2_MUX_USIM,
101 MMP2_MUX_TIPU, 101 MMP2_MUX_TIPU,
102 MMP2_MUX_PLL, 102 MMP2_MUX_PLL,
103 MMP2_MUX_NAND, 103 MMP2_MUX_NAND,
104 MMP2_MUX_FSIC, 104 MMP2_MUX_FSIC,
105 MMP2_MUX_SLEEP_IND, 105 MMP2_MUX_SLEEP_IND,
106 MMP2_MUX_EXT_DMA, 106 MMP2_MUX_EXT_DMA,
107 MMP2_MUX_ONE_WIRE, 107 MMP2_MUX_ONE_WIRE,
108 MMP2_MUX_LCD, 108 MMP2_MUX_LCD,
109 MMP2_MUX_SMC, 109 MMP2_MUX_SMC,
110 MMP2_MUX_SMC_INT, 110 MMP2_MUX_SMC_INT,
111 MMP2_MUX_MSP, 111 MMP2_MUX_MSP,
112 MMP2_MUX_G_CLKOUT, 112 MMP2_MUX_G_CLKOUT,
113 MMP2_MUX_32K_CLKOUT, 113 MMP2_MUX_32K_CLKOUT,
114 MMP2_MUX_PRI_JTAG, 114 MMP2_MUX_PRI_JTAG,
115 MMP2_MUX_AAS_JTAG, 115 MMP2_MUX_AAS_JTAG,
116 MMP2_MUX_AAS_GPIO, 116 MMP2_MUX_AAS_GPIO,
117 MMP2_MUX_AAS_SPI, 117 MMP2_MUX_AAS_SPI,
118 MMP2_MUX_AAS_TWSI, 118 MMP2_MUX_AAS_TWSI,
119 MMP2_MUX_AAS_DEU_EX, 119 MMP2_MUX_AAS_DEU_EX,
120 MMP2_MUX_NONE = 0xffff, 120 MMP2_MUX_NONE = 0xffff,
121 }; 121 };
122 122
123 static struct pinctrl_pin_desc mmp2_pads[] = { 123 static struct pinctrl_pin_desc mmp2_pads[] = {
124 /* 124 /*
125 * The name indicates function 0 of this pin. 125 * The name indicates function 0 of this pin.
126 * After reset, function 0 is the default function of pin. 126 * After reset, function 0 is the default function of pin.
127 */ 127 */
128 PINCTRL_PIN(GPIO0, "GPIO0"), 128 PINCTRL_PIN(GPIO0, "GPIO0"),
129 PINCTRL_PIN(GPIO1, "GPIO1"), 129 PINCTRL_PIN(GPIO1, "GPIO1"),
130 PINCTRL_PIN(GPIO2, "GPIO2"), 130 PINCTRL_PIN(GPIO2, "GPIO2"),
131 PINCTRL_PIN(GPIO3, "GPIO3"), 131 PINCTRL_PIN(GPIO3, "GPIO3"),
132 PINCTRL_PIN(GPIO4, "GPIO4"), 132 PINCTRL_PIN(GPIO4, "GPIO4"),
133 PINCTRL_PIN(GPIO5, "GPIO5"), 133 PINCTRL_PIN(GPIO5, "GPIO5"),
134 PINCTRL_PIN(GPIO6, "GPIO6"), 134 PINCTRL_PIN(GPIO6, "GPIO6"),
135 PINCTRL_PIN(GPIO7, "GPIO7"), 135 PINCTRL_PIN(GPIO7, "GPIO7"),
136 PINCTRL_PIN(GPIO8, "GPIO8"), 136 PINCTRL_PIN(GPIO8, "GPIO8"),
137 PINCTRL_PIN(GPIO9, "GPIO9"), 137 PINCTRL_PIN(GPIO9, "GPIO9"),
138 PINCTRL_PIN(GPIO10, "GPIO10"), 138 PINCTRL_PIN(GPIO10, "GPIO10"),
139 PINCTRL_PIN(GPIO11, "GPIO11"), 139 PINCTRL_PIN(GPIO11, "GPIO11"),
140 PINCTRL_PIN(GPIO12, "GPIO12"), 140 PINCTRL_PIN(GPIO12, "GPIO12"),
141 PINCTRL_PIN(GPIO13, "GPIO13"), 141 PINCTRL_PIN(GPIO13, "GPIO13"),
142 PINCTRL_PIN(GPIO14, "GPIO14"), 142 PINCTRL_PIN(GPIO14, "GPIO14"),
143 PINCTRL_PIN(GPIO15, "GPIO15"), 143 PINCTRL_PIN(GPIO15, "GPIO15"),
144 PINCTRL_PIN(GPIO16, "GPIO16"), 144 PINCTRL_PIN(GPIO16, "GPIO16"),
145 PINCTRL_PIN(GPIO17, "GPIO17"), 145 PINCTRL_PIN(GPIO17, "GPIO17"),
146 PINCTRL_PIN(GPIO18, "GPIO18"), 146 PINCTRL_PIN(GPIO18, "GPIO18"),
147 PINCTRL_PIN(GPIO19, "GPIO19"), 147 PINCTRL_PIN(GPIO19, "GPIO19"),
148 PINCTRL_PIN(GPIO20, "GPIO20"), 148 PINCTRL_PIN(GPIO20, "GPIO20"),
149 PINCTRL_PIN(GPIO21, "GPIO21"), 149 PINCTRL_PIN(GPIO21, "GPIO21"),
150 PINCTRL_PIN(GPIO22, "GPIO22"), 150 PINCTRL_PIN(GPIO22, "GPIO22"),
151 PINCTRL_PIN(GPIO23, "GPIO23"), 151 PINCTRL_PIN(GPIO23, "GPIO23"),
152 PINCTRL_PIN(GPIO24, "GPIO24"), 152 PINCTRL_PIN(GPIO24, "GPIO24"),
153 PINCTRL_PIN(GPIO25, "GPIO25"), 153 PINCTRL_PIN(GPIO25, "GPIO25"),
154 PINCTRL_PIN(GPIO26, "GPIO26"), 154 PINCTRL_PIN(GPIO26, "GPIO26"),
155 PINCTRL_PIN(GPIO27, "GPIO27"), 155 PINCTRL_PIN(GPIO27, "GPIO27"),
156 PINCTRL_PIN(GPIO28, "GPIO28"), 156 PINCTRL_PIN(GPIO28, "GPIO28"),
157 PINCTRL_PIN(GPIO29, "GPIO29"), 157 PINCTRL_PIN(GPIO29, "GPIO29"),
158 PINCTRL_PIN(GPIO30, "GPIO30"), 158 PINCTRL_PIN(GPIO30, "GPIO30"),
159 PINCTRL_PIN(GPIO31, "GPIO31"), 159 PINCTRL_PIN(GPIO31, "GPIO31"),
160 PINCTRL_PIN(GPIO32, "GPIO32"), 160 PINCTRL_PIN(GPIO32, "GPIO32"),
161 PINCTRL_PIN(GPIO33, "GPIO33"), 161 PINCTRL_PIN(GPIO33, "GPIO33"),
162 PINCTRL_PIN(GPIO34, "GPIO34"), 162 PINCTRL_PIN(GPIO34, "GPIO34"),
163 PINCTRL_PIN(GPIO35, "GPIO35"), 163 PINCTRL_PIN(GPIO35, "GPIO35"),
164 PINCTRL_PIN(GPIO36, "GPIO36"), 164 PINCTRL_PIN(GPIO36, "GPIO36"),
165 PINCTRL_PIN(GPIO37, "GPIO37"), 165 PINCTRL_PIN(GPIO37, "GPIO37"),
166 PINCTRL_PIN(GPIO38, "GPIO38"), 166 PINCTRL_PIN(GPIO38, "GPIO38"),
167 PINCTRL_PIN(GPIO39, "GPIO39"), 167 PINCTRL_PIN(GPIO39, "GPIO39"),
168 PINCTRL_PIN(GPIO40, "GPIO40"), 168 PINCTRL_PIN(GPIO40, "GPIO40"),
169 PINCTRL_PIN(GPIO41, "GPIO41"), 169 PINCTRL_PIN(GPIO41, "GPIO41"),
170 PINCTRL_PIN(GPIO42, "GPIO42"), 170 PINCTRL_PIN(GPIO42, "GPIO42"),
171 PINCTRL_PIN(GPIO43, "GPIO43"), 171 PINCTRL_PIN(GPIO43, "GPIO43"),
172 PINCTRL_PIN(GPIO44, "GPIO44"), 172 PINCTRL_PIN(GPIO44, "GPIO44"),
173 PINCTRL_PIN(GPIO45, "GPIO45"), 173 PINCTRL_PIN(GPIO45, "GPIO45"),
174 PINCTRL_PIN(GPIO46, "GPIO46"), 174 PINCTRL_PIN(GPIO46, "GPIO46"),
175 PINCTRL_PIN(GPIO47, "GPIO47"), 175 PINCTRL_PIN(GPIO47, "GPIO47"),
176 PINCTRL_PIN(GPIO48, "GPIO48"), 176 PINCTRL_PIN(GPIO48, "GPIO48"),
177 PINCTRL_PIN(GPIO49, "GPIO49"), 177 PINCTRL_PIN(GPIO49, "GPIO49"),
178 PINCTRL_PIN(GPIO50, "GPIO50"), 178 PINCTRL_PIN(GPIO50, "GPIO50"),
179 PINCTRL_PIN(GPIO51, "GPIO51"), 179 PINCTRL_PIN(GPIO51, "GPIO51"),
180 PINCTRL_PIN(GPIO52, "GPIO52"), 180 PINCTRL_PIN(GPIO52, "GPIO52"),
181 PINCTRL_PIN(GPIO53, "GPIO53"), 181 PINCTRL_PIN(GPIO53, "GPIO53"),
182 PINCTRL_PIN(GPIO54, "GPIO54"), 182 PINCTRL_PIN(GPIO54, "GPIO54"),
183 PINCTRL_PIN(GPIO55, "GPIO55"), 183 PINCTRL_PIN(GPIO55, "GPIO55"),
184 PINCTRL_PIN(GPIO56, "GPIO56"), 184 PINCTRL_PIN(GPIO56, "GPIO56"),
185 PINCTRL_PIN(GPIO57, "GPIO57"), 185 PINCTRL_PIN(GPIO57, "GPIO57"),
186 PINCTRL_PIN(GPIO58, "GPIO58"), 186 PINCTRL_PIN(GPIO58, "GPIO58"),
187 PINCTRL_PIN(GPIO59, "GPIO59"), 187 PINCTRL_PIN(GPIO59, "GPIO59"),
188 PINCTRL_PIN(GPIO60, "GPIO60"), 188 PINCTRL_PIN(GPIO60, "GPIO60"),
189 PINCTRL_PIN(GPIO61, "GPIO61"), 189 PINCTRL_PIN(GPIO61, "GPIO61"),
190 PINCTRL_PIN(GPIO62, "GPIO62"), 190 PINCTRL_PIN(GPIO62, "GPIO62"),
191 PINCTRL_PIN(GPIO63, "GPIO63"), 191 PINCTRL_PIN(GPIO63, "GPIO63"),
192 PINCTRL_PIN(GPIO64, "GPIO64"), 192 PINCTRL_PIN(GPIO64, "GPIO64"),
193 PINCTRL_PIN(GPIO65, "GPIO65"), 193 PINCTRL_PIN(GPIO65, "GPIO65"),
194 PINCTRL_PIN(GPIO66, "GPIO66"), 194 PINCTRL_PIN(GPIO66, "GPIO66"),
195 PINCTRL_PIN(GPIO67, "GPIO67"), 195 PINCTRL_PIN(GPIO67, "GPIO67"),
196 PINCTRL_PIN(GPIO68, "GPIO68"), 196 PINCTRL_PIN(GPIO68, "GPIO68"),
197 PINCTRL_PIN(GPIO69, "GPIO69"), 197 PINCTRL_PIN(GPIO69, "GPIO69"),
198 PINCTRL_PIN(GPIO70, "GPIO70"), 198 PINCTRL_PIN(GPIO70, "GPIO70"),
199 PINCTRL_PIN(GPIO71, "GPIO71"), 199 PINCTRL_PIN(GPIO71, "GPIO71"),
200 PINCTRL_PIN(GPIO72, "GPIO72"), 200 PINCTRL_PIN(GPIO72, "GPIO72"),
201 PINCTRL_PIN(GPIO73, "GPIO73"), 201 PINCTRL_PIN(GPIO73, "GPIO73"),
202 PINCTRL_PIN(GPIO74, "GPIO74"), 202 PINCTRL_PIN(GPIO74, "GPIO74"),
203 PINCTRL_PIN(GPIO75, "GPIO75"), 203 PINCTRL_PIN(GPIO75, "GPIO75"),
204 PINCTRL_PIN(GPIO76, "GPIO76"), 204 PINCTRL_PIN(GPIO76, "GPIO76"),
205 PINCTRL_PIN(GPIO77, "GPIO77"), 205 PINCTRL_PIN(GPIO77, "GPIO77"),
206 PINCTRL_PIN(GPIO78, "GPIO78"), 206 PINCTRL_PIN(GPIO78, "GPIO78"),
207 PINCTRL_PIN(GPIO79, "GPIO79"), 207 PINCTRL_PIN(GPIO79, "GPIO79"),
208 PINCTRL_PIN(GPIO80, "GPIO80"), 208 PINCTRL_PIN(GPIO80, "GPIO80"),
209 PINCTRL_PIN(GPIO81, "GPIO81"), 209 PINCTRL_PIN(GPIO81, "GPIO81"),
210 PINCTRL_PIN(GPIO82, "GPIO82"), 210 PINCTRL_PIN(GPIO82, "GPIO82"),
211 PINCTRL_PIN(GPIO83, "GPIO83"), 211 PINCTRL_PIN(GPIO83, "GPIO83"),
212 PINCTRL_PIN(GPIO84, "GPIO84"), 212 PINCTRL_PIN(GPIO84, "GPIO84"),
213 PINCTRL_PIN(GPIO85, "GPIO85"), 213 PINCTRL_PIN(GPIO85, "GPIO85"),
214 PINCTRL_PIN(GPIO86, "GPIO86"), 214 PINCTRL_PIN(GPIO86, "GPIO86"),
215 PINCTRL_PIN(GPIO87, "GPIO87"), 215 PINCTRL_PIN(GPIO87, "GPIO87"),
216 PINCTRL_PIN(GPIO88, "GPIO88"), 216 PINCTRL_PIN(GPIO88, "GPIO88"),
217 PINCTRL_PIN(GPIO89, "GPIO89"), 217 PINCTRL_PIN(GPIO89, "GPIO89"),
218 PINCTRL_PIN(GPIO90, "GPIO90"), 218 PINCTRL_PIN(GPIO90, "GPIO90"),
219 PINCTRL_PIN(GPIO91, "GPIO91"), 219 PINCTRL_PIN(GPIO91, "GPIO91"),
220 PINCTRL_PIN(GPIO92, "GPIO92"), 220 PINCTRL_PIN(GPIO92, "GPIO92"),
221 PINCTRL_PIN(GPIO93, "GPIO93"), 221 PINCTRL_PIN(GPIO93, "GPIO93"),
222 PINCTRL_PIN(GPIO94, "GPIO94"), 222 PINCTRL_PIN(GPIO94, "GPIO94"),
223 PINCTRL_PIN(GPIO95, "GPIO95"), 223 PINCTRL_PIN(GPIO95, "GPIO95"),
224 PINCTRL_PIN(GPIO96, "GPIO96"), 224 PINCTRL_PIN(GPIO96, "GPIO96"),
225 PINCTRL_PIN(GPIO97, "GPIO97"), 225 PINCTRL_PIN(GPIO97, "GPIO97"),
226 PINCTRL_PIN(GPIO98, "GPIO98"), 226 PINCTRL_PIN(GPIO98, "GPIO98"),
227 PINCTRL_PIN(GPIO99, "GPIO99"), 227 PINCTRL_PIN(GPIO99, "GPIO99"),
228 PINCTRL_PIN(GPIO100, "GPIO100"), 228 PINCTRL_PIN(GPIO100, "GPIO100"),
229 PINCTRL_PIN(GPIO101, "GPIO101"), 229 PINCTRL_PIN(GPIO101, "GPIO101"),
230 PINCTRL_PIN(GPIO102, "GPIO102"), 230 PINCTRL_PIN(GPIO102, "GPIO102"),
231 PINCTRL_PIN(GPIO103, "GPIO103"), 231 PINCTRL_PIN(GPIO103, "GPIO103"),
232 PINCTRL_PIN(GPIO104, "GPIO104"), 232 PINCTRL_PIN(GPIO104, "GPIO104"),
233 PINCTRL_PIN(GPIO105, "GPIO105"), 233 PINCTRL_PIN(GPIO105, "GPIO105"),
234 PINCTRL_PIN(GPIO106, "GPIO106"), 234 PINCTRL_PIN(GPIO106, "GPIO106"),
235 PINCTRL_PIN(GPIO107, "GPIO107"), 235 PINCTRL_PIN(GPIO107, "GPIO107"),
236 PINCTRL_PIN(GPIO108, "GPIO108"), 236 PINCTRL_PIN(GPIO108, "GPIO108"),
237 PINCTRL_PIN(GPIO109, "GPIO109"), 237 PINCTRL_PIN(GPIO109, "GPIO109"),
238 PINCTRL_PIN(GPIO110, "GPIO110"), 238 PINCTRL_PIN(GPIO110, "GPIO110"),
239 PINCTRL_PIN(GPIO111, "GPIO111"), 239 PINCTRL_PIN(GPIO111, "GPIO111"),
240 PINCTRL_PIN(GPIO112, "GPIO112"), 240 PINCTRL_PIN(GPIO112, "GPIO112"),
241 PINCTRL_PIN(GPIO113, "GPIO113"), 241 PINCTRL_PIN(GPIO113, "GPIO113"),
242 PINCTRL_PIN(GPIO114, "GPIO114"), 242 PINCTRL_PIN(GPIO114, "GPIO114"),
243 PINCTRL_PIN(GPIO115, "GPIO115"), 243 PINCTRL_PIN(GPIO115, "GPIO115"),
244 PINCTRL_PIN(GPIO116, "GPIO116"), 244 PINCTRL_PIN(GPIO116, "GPIO116"),
245 PINCTRL_PIN(GPIO117, "GPIO117"), 245 PINCTRL_PIN(GPIO117, "GPIO117"),
246 PINCTRL_PIN(GPIO118, "GPIO118"), 246 PINCTRL_PIN(GPIO118, "GPIO118"),
247 PINCTRL_PIN(GPIO119, "GPIO119"), 247 PINCTRL_PIN(GPIO119, "GPIO119"),
248 PINCTRL_PIN(GPIO120, "GPIO120"), 248 PINCTRL_PIN(GPIO120, "GPIO120"),
249 PINCTRL_PIN(GPIO121, "GPIO121"), 249 PINCTRL_PIN(GPIO121, "GPIO121"),
250 PINCTRL_PIN(GPIO122, "GPIO122"), 250 PINCTRL_PIN(GPIO122, "GPIO122"),
251 PINCTRL_PIN(GPIO123, "GPIO123"), 251 PINCTRL_PIN(GPIO123, "GPIO123"),
252 PINCTRL_PIN(GPIO124, "GPIO124"), 252 PINCTRL_PIN(GPIO124, "GPIO124"),
253 PINCTRL_PIN(GPIO125, "GPIO125"), 253 PINCTRL_PIN(GPIO125, "GPIO125"),
254 PINCTRL_PIN(GPIO126, "GPIO126"), 254 PINCTRL_PIN(GPIO126, "GPIO126"),
255 PINCTRL_PIN(GPIO127, "GPIO127"), 255 PINCTRL_PIN(GPIO127, "GPIO127"),
256 PINCTRL_PIN(GPIO128, "GPIO128"), 256 PINCTRL_PIN(GPIO128, "GPIO128"),
257 PINCTRL_PIN(GPIO129, "GPIO129"), 257 PINCTRL_PIN(GPIO129, "GPIO129"),
258 PINCTRL_PIN(GPIO130, "GPIO130"), 258 PINCTRL_PIN(GPIO130, "GPIO130"),
259 PINCTRL_PIN(GPIO131, "GPIO131"), 259 PINCTRL_PIN(GPIO131, "GPIO131"),
260 PINCTRL_PIN(GPIO132, "GPIO132"), 260 PINCTRL_PIN(GPIO132, "GPIO132"),
261 PINCTRL_PIN(GPIO133, "GPIO133"), 261 PINCTRL_PIN(GPIO133, "GPIO133"),
262 PINCTRL_PIN(GPIO134, "GPIO134"), 262 PINCTRL_PIN(GPIO134, "GPIO134"),
263 PINCTRL_PIN(GPIO135, "GPIO135"), 263 PINCTRL_PIN(GPIO135, "GPIO135"),
264 PINCTRL_PIN(GPIO136, "GPIO136"), 264 PINCTRL_PIN(GPIO136, "GPIO136"),
265 PINCTRL_PIN(GPIO137, "GPIO137"), 265 PINCTRL_PIN(GPIO137, "GPIO137"),
266 PINCTRL_PIN(GPIO138, "GPIO138"), 266 PINCTRL_PIN(GPIO138, "GPIO138"),
267 PINCTRL_PIN(GPIO139, "GPIO139"), 267 PINCTRL_PIN(GPIO139, "GPIO139"),
268 PINCTRL_PIN(GPIO140, "GPIO140"), 268 PINCTRL_PIN(GPIO140, "GPIO140"),
269 PINCTRL_PIN(GPIO141, "GPIO141"), 269 PINCTRL_PIN(GPIO141, "GPIO141"),
270 PINCTRL_PIN(GPIO142, "GPIO142"), 270 PINCTRL_PIN(GPIO142, "GPIO142"),
271 PINCTRL_PIN(GPIO143, "GPIO143"), 271 PINCTRL_PIN(GPIO143, "GPIO143"),
272 PINCTRL_PIN(GPIO144, "GPIO144"), 272 PINCTRL_PIN(GPIO144, "GPIO144"),
273 PINCTRL_PIN(GPIO145, "GPIO145"), 273 PINCTRL_PIN(GPIO145, "GPIO145"),
274 PINCTRL_PIN(GPIO146, "GPIO146"), 274 PINCTRL_PIN(GPIO146, "GPIO146"),
275 PINCTRL_PIN(GPIO147, "GPIO147"), 275 PINCTRL_PIN(GPIO147, "GPIO147"),
276 PINCTRL_PIN(GPIO148, "GPIO148"), 276 PINCTRL_PIN(GPIO148, "GPIO148"),
277 PINCTRL_PIN(GPIO149, "GPIO149"), 277 PINCTRL_PIN(GPIO149, "GPIO149"),
278 PINCTRL_PIN(GPIO150, "GPIO150"), 278 PINCTRL_PIN(GPIO150, "GPIO150"),
279 PINCTRL_PIN(GPIO151, "GPIO151"), 279 PINCTRL_PIN(GPIO151, "GPIO151"),
280 PINCTRL_PIN(GPIO152, "GPIO152"), 280 PINCTRL_PIN(GPIO152, "GPIO152"),
281 PINCTRL_PIN(GPIO153, "GPIO153"), 281 PINCTRL_PIN(GPIO153, "GPIO153"),
282 PINCTRL_PIN(GPIO154, "GPIO154"), 282 PINCTRL_PIN(GPIO154, "GPIO154"),
283 PINCTRL_PIN(GPIO155, "GPIO155"), 283 PINCTRL_PIN(GPIO155, "GPIO155"),
284 PINCTRL_PIN(GPIO156, "GPIO156"), 284 PINCTRL_PIN(GPIO156, "GPIO156"),
285 PINCTRL_PIN(GPIO157, "GPIO157"), 285 PINCTRL_PIN(GPIO157, "GPIO157"),
286 PINCTRL_PIN(GPIO158, "GPIO158"), 286 PINCTRL_PIN(GPIO158, "GPIO158"),
287 PINCTRL_PIN(GPIO159, "GPIO159"), 287 PINCTRL_PIN(GPIO159, "GPIO159"),
288 PINCTRL_PIN(GPIO160, "GPIO160"), 288 PINCTRL_PIN(GPIO160, "GPIO160"),
289 PINCTRL_PIN(GPIO161, "GPIO161"), 289 PINCTRL_PIN(GPIO161, "GPIO161"),
290 PINCTRL_PIN(GPIO162, "GPIO162"), 290 PINCTRL_PIN(GPIO162, "GPIO162"),
291 PINCTRL_PIN(GPIO163, "GPIO163"), 291 PINCTRL_PIN(GPIO163, "GPIO163"),
292 PINCTRL_PIN(GPIO164, "GPIO164"), 292 PINCTRL_PIN(GPIO164, "GPIO164"),
293 PINCTRL_PIN(GPIO165, "GPIO165"), 293 PINCTRL_PIN(GPIO165, "GPIO165"),
294 PINCTRL_PIN(GPIO166, "GPIO166"), 294 PINCTRL_PIN(GPIO166, "GPIO166"),
295 PINCTRL_PIN(GPIO167, "GPIO167"), 295 PINCTRL_PIN(GPIO167, "GPIO167"),
296 PINCTRL_PIN(GPIO168, "GPIO168"), 296 PINCTRL_PIN(GPIO168, "GPIO168"),
297 PINCTRL_PIN(TWSI4_SCL, "TWSI4_SCL"), 297 PINCTRL_PIN(TWSI4_SCL, "TWSI4_SCL"),
298 PINCTRL_PIN(TWSI4_SDA, "TWSI4_SDA"), 298 PINCTRL_PIN(TWSI4_SDA, "TWSI4_SDA"),
299 PINCTRL_PIN(G_CLKREQ, "G_CLKREQ"), 299 PINCTRL_PIN(G_CLKREQ, "G_CLKREQ"),
300 PINCTRL_PIN(VCXO_REQ, "VCXO_REQ"), 300 PINCTRL_PIN(VCXO_REQ, "VCXO_REQ"),
301 PINCTRL_PIN(VCXO_OUT, "VCXO_OUT"), 301 PINCTRL_PIN(VCXO_OUT, "VCXO_OUT"),
302 }; 302 };
303 303
304 struct pxa3xx_mfp_pin mmp2_mfp[] = { 304 struct pxa3xx_mfp_pin mmp2_mfp[] = {
305 /* pin offs f0 f1 f2 f3 f4 f5 f6 f7 */ 305 /* pin offs f0 f1 f2 f3 f4 f5 f6 f7 */
306 MFPR_MMP2(GPIO0, 0x054, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE), 306 MFPR_MMP2(GPIO0, 0x054, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE),
307 MFPR_MMP2(GPIO1, 0x058, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE), 307 MFPR_MMP2(GPIO1, 0x058, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE),
308 MFPR_MMP2(GPIO2, 0x05C, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE), 308 MFPR_MMP2(GPIO2, 0x05C, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE),
309 MFPR_MMP2(GPIO3, 0x060, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE), 309 MFPR_MMP2(GPIO3, 0x060, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE),
310 MFPR_MMP2(GPIO4, 0x064, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 310 MFPR_MMP2(GPIO4, 0x064, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
311 MFPR_MMP2(GPIO5, 0x068, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE), 311 MFPR_MMP2(GPIO5, 0x068, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE),
312 MFPR_MMP2(GPIO6, 0x06C, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE), 312 MFPR_MMP2(GPIO6, 0x06C, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE),
313 MFPR_MMP2(GPIO7, 0x070, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE), 313 MFPR_MMP2(GPIO7, 0x070, GPIO, KP_MK, NONE, SPI, NONE, NONE, NONE, NONE),
314 MFPR_MMP2(GPIO8, 0x074, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 314 MFPR_MMP2(GPIO8, 0x074, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
315 MFPR_MMP2(GPIO9, 0x078, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 315 MFPR_MMP2(GPIO9, 0x078, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
316 MFPR_MMP2(GPIO10, 0x07C, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 316 MFPR_MMP2(GPIO10, 0x07C, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
317 MFPR_MMP2(GPIO11, 0x080, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 317 MFPR_MMP2(GPIO11, 0x080, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
318 MFPR_MMP2(GPIO12, 0x084, GPIO, KP_MK, NONE, CCIC1, NONE, NONE, NONE, NONE), 318 MFPR_MMP2(GPIO12, 0x084, GPIO, KP_MK, NONE, CCIC1, NONE, NONE, NONE, NONE),
319 MFPR_MMP2(GPIO13, 0x088, GPIO, KP_MK, NONE, CCIC1, NONE, NONE, NONE, NONE), 319 MFPR_MMP2(GPIO13, 0x088, GPIO, KP_MK, NONE, CCIC1, NONE, NONE, NONE, NONE),
320 MFPR_MMP2(GPIO14, 0x08C, GPIO, KP_MK, NONE, CCIC1, NONE, NONE, NONE, NONE), 320 MFPR_MMP2(GPIO14, 0x08C, GPIO, KP_MK, NONE, CCIC1, NONE, NONE, NONE, NONE),
321 MFPR_MMP2(GPIO15, 0x090, GPIO, KP_MK, KP_DK, CCIC1, NONE, NONE, NONE, NONE), 321 MFPR_MMP2(GPIO15, 0x090, GPIO, KP_MK, KP_DK, CCIC1, NONE, NONE, NONE, NONE),
322 MFPR_MMP2(GPIO16, 0x094, GPIO, KP_DK, ROT, CCIC1, NONE, NONE, NONE, NONE), 322 MFPR_MMP2(GPIO16, 0x094, GPIO, KP_DK, ROT, CCIC1, NONE, NONE, NONE, NONE),
323 MFPR_MMP2(GPIO17, 0x098, GPIO, KP_DK, ROT, CCIC1, NONE, NONE, NONE, NONE), 323 MFPR_MMP2(GPIO17, 0x098, GPIO, KP_DK, ROT, CCIC1, NONE, NONE, NONE, NONE),
324 MFPR_MMP2(GPIO18, 0x09C, GPIO, KP_DK, ROT, CCIC1, NONE, NONE, NONE, NONE), 324 MFPR_MMP2(GPIO18, 0x09C, GPIO, KP_DK, ROT, CCIC1, NONE, NONE, NONE, NONE),
325 MFPR_MMP2(GPIO19, 0x0A0, GPIO, KP_DK, ROT, CCIC1, NONE, NONE, NONE, NONE), 325 MFPR_MMP2(GPIO19, 0x0A0, GPIO, KP_DK, ROT, CCIC1, NONE, NONE, NONE, NONE),
326 MFPR_MMP2(GPIO20, 0x0A4, GPIO, KP_DK, TB, CCIC1, NONE, NONE, NONE, NONE), 326 MFPR_MMP2(GPIO20, 0x0A4, GPIO, KP_DK, TB, CCIC1, NONE, NONE, NONE, NONE),
327 MFPR_MMP2(GPIO21, 0x0A8, GPIO, KP_DK, TB, CCIC1, NONE, NONE, NONE, NONE), 327 MFPR_MMP2(GPIO21, 0x0A8, GPIO, KP_DK, TB, CCIC1, NONE, NONE, NONE, NONE),
328 MFPR_MMP2(GPIO22, 0x0AC, GPIO, KP_DK, TB, CCIC1, NONE, NONE, NONE, NONE), 328 MFPR_MMP2(GPIO22, 0x0AC, GPIO, KP_DK, TB, CCIC1, NONE, NONE, NONE, NONE),
329 MFPR_MMP2(GPIO23, 0x0B0, GPIO, KP_DK, TB, CCIC1, NONE, NONE, NONE, NONE), 329 MFPR_MMP2(GPIO23, 0x0B0, GPIO, KP_DK, TB, CCIC1, NONE, NONE, NONE, NONE),
330 MFPR_MMP2(GPIO24, 0x0B4, GPIO, I2S, VCXO_OUT, NONE, NONE, NONE, NONE, NONE), 330 MFPR_MMP2(GPIO24, 0x0B4, GPIO, I2S, VCXO_OUT, NONE, NONE, NONE, NONE, NONE),
331 MFPR_MMP2(GPIO25, 0x0B8, GPIO, I2S, HDMI, SSPA2, NONE, NONE, NONE, NONE), 331 MFPR_MMP2(GPIO25, 0x0B8, GPIO, I2S, HDMI, SSPA2, NONE, NONE, NONE, NONE),
332 MFPR_MMP2(GPIO26, 0x0BC, GPIO, I2S, HDMI, SSPA2, NONE, NONE, NONE, NONE), 332 MFPR_MMP2(GPIO26, 0x0BC, GPIO, I2S, HDMI, SSPA2, NONE, NONE, NONE, NONE),
333 MFPR_MMP2(GPIO27, 0x0C0, GPIO, I2S, HDMI, SSPA2, NONE, NONE, NONE, NONE), 333 MFPR_MMP2(GPIO27, 0x0C0, GPIO, I2S, HDMI, SSPA2, NONE, NONE, NONE, NONE),
334 MFPR_MMP2(GPIO28, 0x0C4, GPIO, I2S, NONE, SSPA2, NONE, NONE, NONE, NONE), 334 MFPR_MMP2(GPIO28, 0x0C4, GPIO, I2S, NONE, SSPA2, NONE, NONE, NONE, NONE),
335 MFPR_MMP2(GPIO29, 0x0C8, GPIO, UART1, KP_MK, NONE, NONE, NONE, AAS_SPI, NONE), 335 MFPR_MMP2(GPIO29, 0x0C8, GPIO, UART1, KP_MK, NONE, NONE, NONE, AAS_SPI, NONE),
336 MFPR_MMP2(GPIO30, 0x0CC, GPIO, UART1, KP_MK, NONE, NONE, NONE, AAS_SPI, NONE), 336 MFPR_MMP2(GPIO30, 0x0CC, GPIO, UART1, KP_MK, NONE, NONE, NONE, AAS_SPI, NONE),
337 MFPR_MMP2(GPIO31, 0x0D0, GPIO, UART1, KP_MK, NONE, NONE, NONE, AAS_SPI, NONE), 337 MFPR_MMP2(GPIO31, 0x0D0, GPIO, UART1, KP_MK, NONE, NONE, NONE, AAS_SPI, NONE),
338 MFPR_MMP2(GPIO32, 0x0D4, GPIO, UART1, KP_MK, NONE, NONE, NONE, AAS_SPI, NONE), 338 MFPR_MMP2(GPIO32, 0x0D4, GPIO, UART1, KP_MK, NONE, NONE, NONE, AAS_SPI, NONE),
339 MFPR_MMP2(GPIO33, 0x0D8, GPIO, SSPA2, I2S, NONE, NONE, NONE, NONE, NONE), 339 MFPR_MMP2(GPIO33, 0x0D8, GPIO, SSPA2, I2S, NONE, NONE, NONE, NONE, NONE),
340 MFPR_MMP2(GPIO34, 0x0DC, GPIO, SSPA2, I2S, NONE, NONE, NONE, NONE, NONE), 340 MFPR_MMP2(GPIO34, 0x0DC, GPIO, SSPA2, I2S, NONE, NONE, NONE, NONE, NONE),
341 MFPR_MMP2(GPIO35, 0x0E0, GPIO, SSPA2, I2S, NONE, NONE, NONE, NONE, NONE), 341 MFPR_MMP2(GPIO35, 0x0E0, GPIO, SSPA2, I2S, NONE, NONE, NONE, NONE, NONE),
342 MFPR_MMP2(GPIO36, 0x0E4, GPIO, SSPA2, I2S, NONE, NONE, NONE, NONE, NONE), 342 MFPR_MMP2(GPIO36, 0x0E4, GPIO, SSPA2, I2S, NONE, NONE, NONE, NONE, NONE),
343 MFPR_MMP2(GPIO37, 0x0E8, GPIO, MMC2, SSP1, TWSI2, UART2, UART3, AAS_SPI, AAS_TWSI), 343 MFPR_MMP2(GPIO37, 0x0E8, GPIO, MMC2, SSP1, TWSI2, UART2, UART3, AAS_SPI, AAS_TWSI),
344 MFPR_MMP2(GPIO38, 0x0EC, GPIO, MMC2, SSP1, TWSI2, UART2, UART3, AAS_SPI, AAS_TWSI), 344 MFPR_MMP2(GPIO38, 0x0EC, GPIO, MMC2, SSP1, TWSI2, UART2, UART3, AAS_SPI, AAS_TWSI),
345 MFPR_MMP2(GPIO39, 0x0F0, GPIO, MMC2, SSP1, TWSI2, UART2, UART3, AAS_SPI, AAS_TWSI), 345 MFPR_MMP2(GPIO39, 0x0F0, GPIO, MMC2, SSP1, TWSI2, UART2, UART3, AAS_SPI, AAS_TWSI),
346 MFPR_MMP2(GPIO40, 0x0F4, GPIO, MMC2, SSP1, TWSI2, UART2, UART3, AAS_SPI, AAS_TWSI), 346 MFPR_MMP2(GPIO40, 0x0F4, GPIO, MMC2, SSP1, TWSI2, UART2, UART3, AAS_SPI, AAS_TWSI),
347 MFPR_MMP2(GPIO41, 0x0F8, GPIO, MMC2, TWSI5, NONE, NONE, NONE, NONE, NONE), 347 MFPR_MMP2(GPIO41, 0x0F8, GPIO, MMC2, TWSI5, NONE, NONE, NONE, NONE, NONE),
348 MFPR_MMP2(GPIO42, 0x0FC, GPIO, MMC2, TWSI5, NONE, NONE, NONE, NONE, NONE), 348 MFPR_MMP2(GPIO42, 0x0FC, GPIO, MMC2, TWSI5, NONE, NONE, NONE, NONE, NONE),
349 MFPR_MMP2(GPIO43, 0x100, GPIO, TWSI2, UART4, SSP1, UART2, UART3, NONE, AAS_TWSI), 349 MFPR_MMP2(GPIO43, 0x100, GPIO, TWSI2, UART4, SSP1, UART2, UART3, NONE, AAS_TWSI),
350 MFPR_MMP2(GPIO44, 0x104, GPIO, TWSI2, UART4, SSP1, UART2, UART3, NONE, AAS_TWSI), 350 MFPR_MMP2(GPIO44, 0x104, GPIO, TWSI2, UART4, SSP1, UART2, UART3, NONE, AAS_TWSI),
351 MFPR_MMP2(GPIO45, 0x108, GPIO, UART1, UART4, SSP1, UART2, UART3, NONE, NONE), 351 MFPR_MMP2(GPIO45, 0x108, GPIO, UART1, UART4, SSP1, UART2, UART3, NONE, NONE),
352 MFPR_MMP2(GPIO46, 0x10C, GPIO, UART1, UART4, SSP1, UART2, UART3, NONE, NONE), 352 MFPR_MMP2(GPIO46, 0x10C, GPIO, UART1, UART4, SSP1, UART2, UART3, NONE, NONE),
353 MFPR_MMP2(GPIO47, 0x110, GPIO, UART2, SSP2, TWSI6, CAM2, AAS_SPI, AAS_GPIO, NONE), 353 MFPR_MMP2(GPIO47, 0x110, GPIO, UART2, SSP2, TWSI6, CAM2, AAS_SPI, AAS_GPIO, NONE),
354 MFPR_MMP2(GPIO48, 0x114, GPIO, UART2, SSP2, TWSI6, CAM2, AAS_SPI, AAS_GPIO, NONE), 354 MFPR_MMP2(GPIO48, 0x114, GPIO, UART2, SSP2, TWSI6, CAM2, AAS_SPI, AAS_GPIO, NONE),
355 MFPR_MMP2(GPIO49, 0x118, GPIO, UART2, SSP2, PWM, CCIC2, AAS_SPI, NONE, NONE), 355 MFPR_MMP2(GPIO49, 0x118, GPIO, UART2, SSP2, PWM, CCIC2, AAS_SPI, NONE, NONE),
356 MFPR_MMP2(GPIO50, 0x11C, GPIO, UART2, SSP2, PWM, CCIC2, AAS_SPI, NONE, NONE), 356 MFPR_MMP2(GPIO50, 0x11C, GPIO, UART2, SSP2, PWM, CCIC2, AAS_SPI, NONE, NONE),
357 MFPR_MMP2(GPIO51, 0x120, GPIO, UART3, ROT, AAS_GPIO, PWM, NONE, NONE, NONE), 357 MFPR_MMP2(GPIO51, 0x120, GPIO, UART3, ROT, AAS_GPIO, PWM, NONE, NONE, NONE),
358 MFPR_MMP2(GPIO52, 0x124, GPIO, UART3, ROT, AAS_GPIO, PWM, NONE, NONE, NONE), 358 MFPR_MMP2(GPIO52, 0x124, GPIO, UART3, ROT, AAS_GPIO, PWM, NONE, NONE, NONE),
359 MFPR_MMP2(GPIO53, 0x128, GPIO, UART3, TWSI2, VCXO_REQ, NONE, PWM, NONE, AAS_TWSI), 359 MFPR_MMP2(GPIO53, 0x128, GPIO, UART3, TWSI2, VCXO_REQ, NONE, PWM, NONE, AAS_TWSI),
360 MFPR_MMP2(GPIO54, 0x12C, GPIO, UART3, TWSI2, VCXO_OUT, HDMI, PWM, NONE, AAS_TWSI), 360 MFPR_MMP2(GPIO54, 0x12C, GPIO, UART3, TWSI2, VCXO_OUT, HDMI, PWM, NONE, AAS_TWSI),
361 MFPR_MMP2(GPIO55, 0x130, GPIO, SSP2, SSP1, UART2, ROT, TWSI2, SSP3, AAS_TWSI), 361 MFPR_MMP2(GPIO55, 0x130, GPIO, SSP2, SSP1, UART2, ROT, TWSI2, SSP3, AAS_TWSI),
362 MFPR_MMP2(GPIO56, 0x134, GPIO, SSP2, SSP1, UART2, ROT, TWSI2, KP_DK, AAS_TWSI), 362 MFPR_MMP2(GPIO56, 0x134, GPIO, SSP2, SSP1, UART2, ROT, TWSI2, KP_DK, AAS_TWSI),
363 MFPR_MMP2(GPIO57, 0x138, GPIO, SSP2_RX, SSP1_TXRX, SSP2_FRM, SSP1_RX, VCXO_REQ, KP_DK, NONE), 363 MFPR_MMP2(GPIO57, 0x138, GPIO, SSP2_RX, SSP1_TXRX, SSP2_FRM, SSP1_RX, VCXO_REQ, KP_DK, NONE),
364 MFPR_MMP2(GPIO58, 0x13C, GPIO, SSP2, SSP1_RX, SSP1_FRM, SSP1_TXRX, VCXO_REQ, KP_DK, NONE), 364 MFPR_MMP2(GPIO58, 0x13C, GPIO, SSP2, SSP1_RX, SSP1_FRM, SSP1_TXRX, VCXO_REQ, KP_DK, NONE),
365 MFPR_MMP2(GPIO59, 0x280, GPIO, CCIC1, ULPI, MMC3, CCIC2, UART3, UART4, NONE), 365 MFPR_MMP2(GPIO59, 0x280, GPIO, CCIC1, ULPI, MMC3, CCIC2, UART3, UART4, NONE),
366 MFPR_MMP2(GPIO60, 0x284, GPIO, CCIC1, ULPI, MMC3, CCIC2, UART3, UART4, NONE), 366 MFPR_MMP2(GPIO60, 0x284, GPIO, CCIC1, ULPI, MMC3, CCIC2, UART3, UART4, NONE),
367 MFPR_MMP2(GPIO61, 0x288, GPIO, CCIC1, ULPI, MMC3, CCIC2, UART3, HDMI, NONE), 367 MFPR_MMP2(GPIO61, 0x288, GPIO, CCIC1, ULPI, MMC3, CCIC2, UART3, HDMI, NONE),
368 MFPR_MMP2(GPIO62, 0x28C, GPIO, CCIC1, ULPI, MMC3, CCIC2, UART3, NONE, NONE), 368 MFPR_MMP2(GPIO62, 0x28C, GPIO, CCIC1, ULPI, MMC3, CCIC2, UART3, NONE, NONE),
369 MFPR_MMP2(GPIO63, 0x290, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, UART4, NONE), 369 MFPR_MMP2(GPIO63, 0x290, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, UART4, NONE),
370 MFPR_MMP2(GPIO64, 0x294, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, UART4, NONE), 370 MFPR_MMP2(GPIO64, 0x294, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, UART4, NONE),
371 MFPR_MMP2(GPIO65, 0x298, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, UART4, NONE), 371 MFPR_MMP2(GPIO65, 0x298, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, UART4, NONE),
372 MFPR_MMP2(GPIO66, 0x29C, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, UART4, NONE), 372 MFPR_MMP2(GPIO66, 0x29C, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, UART4, NONE),
373 MFPR_MMP2(GPIO67, 0x2A0, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, NONE, NONE), 373 MFPR_MMP2(GPIO67, 0x2A0, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, NONE, NONE),
374 MFPR_MMP2(GPIO68, 0x2A4, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, LCD, NONE), 374 MFPR_MMP2(GPIO68, 0x2A4, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, LCD, NONE),
375 MFPR_MMP2(GPIO69, 0x2A8, GPIO, CCIC1, ULPI, MMC3, CCIC2, NONE, LCD, NONE), 375 MFPR_MMP2(GPIO69, 0x2A8, GPIO, CCIC1, ULPI, MMC3, CCIC2, NONE, LCD, NONE),
376 MFPR_MMP2(GPIO70, 0x2AC, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, LCD, NONE), 376 MFPR_MMP2(GPIO70, 0x2AC, GPIO, CCIC1, ULPI, MMC3, CCIC2, MSP, LCD, NONE),
377 MFPR_MMP2(GPIO71, 0x2B0, GPIO, TWSI3, NONE, PWM, NONE, NONE, LCD, AAS_TWSI), 377 MFPR_MMP2(GPIO71, 0x2B0, GPIO, TWSI3, NONE, PWM, NONE, NONE, LCD, AAS_TWSI),
378 MFPR_MMP2(GPIO72, 0x2B4, GPIO, TWSI3, HDMI, PWM, NONE, NONE, LCD, AAS_TWSI), 378 MFPR_MMP2(GPIO72, 0x2B4, GPIO, TWSI3, HDMI, PWM, NONE, NONE, LCD, AAS_TWSI),
379 MFPR_MMP2(GPIO73, 0x2B8, GPIO, VCXO_REQ, 32K_CLKOUT, PWM, VCXO_OUT, NONE, LCD, NONE), 379 MFPR_MMP2(GPIO73, 0x2B8, GPIO, VCXO_REQ, 32K_CLKOUT, PWM, VCXO_OUT, NONE, LCD, NONE),
380 MFPR_MMP2(GPIO74, 0x170, GPIO, LCD, SMC, MMC4, SSP3, UART2, UART4, TIPU), 380 MFPR_MMP2(GPIO74, 0x170, GPIO, LCD, SMC, MMC4, SSP3, UART2, UART4, TIPU),
381 MFPR_MMP2(GPIO75, 0x174, GPIO, LCD, SMC, MMC4, SSP3, UART2, UART4, TIPU), 381 MFPR_MMP2(GPIO75, 0x174, GPIO, LCD, SMC, MMC4, SSP3, UART2, UART4, TIPU),
382 MFPR_MMP2(GPIO76, 0x178, GPIO, LCD, SMC, MMC4, SSP3, UART2, UART4, TIPU), 382 MFPR_MMP2(GPIO76, 0x178, GPIO, LCD, SMC, MMC4, SSP3, UART2, UART4, TIPU),
383 MFPR_MMP2(GPIO77, 0x17C, GPIO, LCD, SMC, MMC4, SSP3, UART2, UART4, TIPU), 383 MFPR_MMP2(GPIO77, 0x17C, GPIO, LCD, SMC, MMC4, SSP3, UART2, UART4, TIPU),
384 MFPR_MMP2(GPIO78, 0x180, GPIO, LCD, HDMI, MMC4, NONE, SSP4, AAS_SPI, TIPU), 384 MFPR_MMP2(GPIO78, 0x180, GPIO, LCD, HDMI, MMC4, NONE, SSP4, AAS_SPI, TIPU),
385 MFPR_MMP2(GPIO79, 0x184, GPIO, LCD, AAS_GPIO, MMC4, NONE, SSP4, AAS_SPI, TIPU), 385 MFPR_MMP2(GPIO79, 0x184, GPIO, LCD, AAS_GPIO, MMC4, NONE, SSP4, AAS_SPI, TIPU),
386 MFPR_MMP2(GPIO80, 0x188, GPIO, LCD, AAS_GPIO, MMC4, NONE, SSP4, AAS_SPI, TIPU), 386 MFPR_MMP2(GPIO80, 0x188, GPIO, LCD, AAS_GPIO, MMC4, NONE, SSP4, AAS_SPI, TIPU),
387 MFPR_MMP2(GPIO81, 0x18C, GPIO, LCD, AAS_GPIO, MMC4, NONE, SSP4, AAS_SPI, TIPU), 387 MFPR_MMP2(GPIO81, 0x18C, GPIO, LCD, AAS_GPIO, MMC4, NONE, SSP4, AAS_SPI, TIPU),
388 MFPR_MMP2(GPIO82, 0x190, GPIO, LCD, NONE, MMC4, NONE, NONE, CCIC2, TIPU), 388 MFPR_MMP2(GPIO82, 0x190, GPIO, LCD, NONE, MMC4, NONE, NONE, CCIC2, TIPU),
389 MFPR_MMP2(GPIO83, 0x194, GPIO, LCD, NONE, MMC4, NONE, NONE, CCIC2, TIPU), 389 MFPR_MMP2(GPIO83, 0x194, GPIO, LCD, NONE, MMC4, NONE, NONE, CCIC2, TIPU),
390 MFPR_MMP2(GPIO84, 0x198, GPIO, LCD, SMC, MMC2, NONE, TWSI5, AAS_TWSI, TIPU), 390 MFPR_MMP2(GPIO84, 0x198, GPIO, LCD, SMC, MMC2, NONE, TWSI5, AAS_TWSI, TIPU),
391 MFPR_MMP2(GPIO85, 0x19C, GPIO, LCD, SMC, MMC2, NONE, TWSI5, AAS_TWSI, TIPU), 391 MFPR_MMP2(GPIO85, 0x19C, GPIO, LCD, SMC, MMC2, NONE, TWSI5, AAS_TWSI, TIPU),
392 MFPR_MMP2(GPIO86, 0x1A0, GPIO, LCD, SMC, MMC2, NONE, TWSI6, CCIC2, TIPU), 392 MFPR_MMP2(GPIO86, 0x1A0, GPIO, LCD, SMC, MMC2, NONE, TWSI6, CCIC2, TIPU),
393 MFPR_MMP2(GPIO87, 0x1A4, GPIO, LCD, SMC, MMC2, NONE, TWSI6, CCIC2, TIPU), 393 MFPR_MMP2(GPIO87, 0x1A4, GPIO, LCD, SMC, MMC2, NONE, TWSI6, CCIC2, TIPU),
394 MFPR_MMP2(GPIO88, 0x1A8, GPIO, LCD, AAS_GPIO, MMC2, NONE, NONE, CCIC2, TIPU), 394 MFPR_MMP2(GPIO88, 0x1A8, GPIO, LCD, AAS_GPIO, MMC2, NONE, NONE, CCIC2, TIPU),
395 MFPR_MMP2(GPIO89, 0x1AC, GPIO, LCD, AAS_GPIO, MMC2, NONE, NONE, CCIC2, TIPU), 395 MFPR_MMP2(GPIO89, 0x1AC, GPIO, LCD, AAS_GPIO, MMC2, NONE, NONE, CCIC2, TIPU),
396 MFPR_MMP2(GPIO90, 0x1B0, GPIO, LCD, AAS_GPIO, MMC2, NONE, NONE, CCIC2, TIPU), 396 MFPR_MMP2(GPIO90, 0x1B0, GPIO, LCD, AAS_GPIO, MMC2, NONE, NONE, CCIC2, TIPU),
397 MFPR_MMP2(GPIO91, 0x1B4, GPIO, LCD, AAS_GPIO, MMC2, NONE, NONE, CCIC2, TIPU), 397 MFPR_MMP2(GPIO91, 0x1B4, GPIO, LCD, AAS_GPIO, MMC2, NONE, NONE, CCIC2, TIPU),
398 MFPR_MMP2(GPIO92, 0x1B8, GPIO, LCD, AAS_GPIO, MMC2, NONE, NONE, CCIC2, TIPU), 398 MFPR_MMP2(GPIO92, 0x1B8, GPIO, LCD, AAS_GPIO, MMC2, NONE, NONE, CCIC2, TIPU),
399 MFPR_MMP2(GPIO93, 0x1BC, GPIO, LCD, AAS_GPIO, MMC2, NONE, NONE, CCIC2, TIPU), 399 MFPR_MMP2(GPIO93, 0x1BC, GPIO, LCD, AAS_GPIO, MMC2, NONE, NONE, CCIC2, TIPU),
400 MFPR_MMP2(GPIO94, 0x1C0, GPIO, LCD, AAS_GPIO, SPI, NONE, AAS_SPI, CCIC2, TIPU), 400 MFPR_MMP2(GPIO94, 0x1C0, GPIO, LCD, AAS_GPIO, SPI, NONE, AAS_SPI, CCIC2, TIPU),
401 MFPR_MMP2(GPIO95, 0x1C4, GPIO, LCD, TWSI3, SPI, AAS_DEU_EX, AAS_SPI, CCIC2, TIPU), 401 MFPR_MMP2(GPIO95, 0x1C4, GPIO, LCD, TWSI3, SPI, AAS_DEU_EX, AAS_SPI, CCIC2, TIPU),
402 MFPR_MMP2(GPIO96, 0x1C8, GPIO, LCD, TWSI3, SPI, AAS_DEU_EX, AAS_SPI, NONE, TIPU), 402 MFPR_MMP2(GPIO96, 0x1C8, GPIO, LCD, TWSI3, SPI, AAS_DEU_EX, AAS_SPI, NONE, TIPU),
403 MFPR_MMP2(GPIO97, 0x1CC, GPIO, LCD, TWSI6, SPI, AAS_DEU_EX, AAS_SPI, NONE, TIPU), 403 MFPR_MMP2(GPIO97, 0x1CC, GPIO, LCD, TWSI6, SPI, AAS_DEU_EX, AAS_SPI, NONE, TIPU),
404 MFPR_MMP2(GPIO98, 0x1D0, GPIO, LCD, TWSI6, SPI, ONE_WIRE, NONE, NONE, TIPU), 404 MFPR_MMP2(GPIO98, 0x1D0, GPIO, LCD, TWSI6, SPI, ONE_WIRE, NONE, NONE, TIPU),
405 MFPR_MMP2(GPIO99, 0x1D4, GPIO, LCD, SMC, SPI, TWSI5, NONE, NONE, TIPU), 405 MFPR_MMP2(GPIO99, 0x1D4, GPIO, LCD, SMC, SPI, TWSI5, NONE, NONE, TIPU),
406 MFPR_MMP2(GPIO100, 0x1D8, GPIO, LCD, SMC, SPI, TWSI5, NONE, NONE, TIPU), 406 MFPR_MMP2(GPIO100, 0x1D8, GPIO, LCD, SMC, SPI, TWSI5, NONE, NONE, TIPU),
407 MFPR_MMP2(GPIO101, 0x1DC, GPIO, LCD, SMC, SPI, NONE, NONE, NONE, TIPU), 407 MFPR_MMP2(GPIO101, 0x1DC, GPIO, LCD, SMC, SPI, NONE, NONE, NONE, TIPU),
408 MFPR_MMP2(GPIO102, 0x000, USIM, GPIO, FSIC, KP_DK, LCD, NONE, NONE, NONE), 408 MFPR_MMP2(GPIO102, 0x000, USIM, GPIO, FSIC, KP_DK, LCD, NONE, NONE, NONE),
409 MFPR_MMP2(GPIO103, 0x004, USIM, GPIO, FSIC, KP_DK, LCD, NONE, NONE, NONE), 409 MFPR_MMP2(GPIO103, 0x004, USIM, GPIO, FSIC, KP_DK, LCD, NONE, NONE, NONE),
410 MFPR_MMP2(GPIO104, 0x1FC, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE), 410 MFPR_MMP2(GPIO104, 0x1FC, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE),
411 MFPR_MMP2(GPIO105, 0x1F8, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE), 411 MFPR_MMP2(GPIO105, 0x1F8, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE),
412 MFPR_MMP2(GPIO106, 0x1F4, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE), 412 MFPR_MMP2(GPIO106, 0x1F4, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE),
413 MFPR_MMP2(GPIO107, 0x1F0, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE), 413 MFPR_MMP2(GPIO107, 0x1F0, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE),
414 MFPR_MMP2(GPIO108, 0x21C, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE), 414 MFPR_MMP2(GPIO108, 0x21C, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE),
415 MFPR_MMP2(GPIO109, 0x218, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE), 415 MFPR_MMP2(GPIO109, 0x218, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE),
416 MFPR_MMP2(GPIO110, 0x214, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE), 416 MFPR_MMP2(GPIO110, 0x214, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE),
417 MFPR_MMP2(GPIO111, 0x200, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE), 417 MFPR_MMP2(GPIO111, 0x200, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE),
418 MFPR_MMP2(GPIO112, 0x244, NAND, GPIO, MMC3, SMC, NONE, NONE, NONE, NONE), 418 MFPR_MMP2(GPIO112, 0x244, NAND, GPIO, MMC3, SMC, NONE, NONE, NONE, NONE),
419 MFPR_MMP2(GPIO113, 0x25C, SMC, GPIO, EXT_DMA, MMC3, SMC, HDMI, NONE, NONE), 419 MFPR_MMP2(GPIO113, 0x25C, SMC, GPIO, EXT_DMA, MMC3, SMC, HDMI, NONE, NONE),
420 MFPR_MMP2(GPIO114, 0x164, G_CLKOUT, 32K_CLKOUT, HDMI, NONE, NONE, NONE, NONE, NONE), 420 MFPR_MMP2(GPIO114, 0x164, G_CLKOUT, 32K_CLKOUT, HDMI, NONE, NONE, NONE, NONE, NONE),
421 MFPR_MMP2(GPIO115, 0x260, GPIO, NONE, AC, UART4, UART3, SSP1, NONE, NONE), 421 MFPR_MMP2(GPIO115, 0x260, GPIO, NONE, AC, UART4, UART3, SSP1, NONE, NONE),
422 MFPR_MMP2(GPIO116, 0x264, GPIO, NONE, AC, UART4, UART3, SSP1, NONE, NONE), 422 MFPR_MMP2(GPIO116, 0x264, GPIO, NONE, AC, UART4, UART3, SSP1, NONE, NONE),
423 MFPR_MMP2(GPIO117, 0x268, GPIO, NONE, AC, UART4, UART3, SSP1, NONE, NONE), 423 MFPR_MMP2(GPIO117, 0x268, GPIO, NONE, AC, UART4, UART3, SSP1, NONE, NONE),
424 MFPR_MMP2(GPIO118, 0x26C, GPIO, NONE, AC, UART4, UART3, SSP1, NONE, NONE), 424 MFPR_MMP2(GPIO118, 0x26C, GPIO, NONE, AC, UART4, UART3, SSP1, NONE, NONE),
425 MFPR_MMP2(GPIO119, 0x270, GPIO, NONE, CA, SSP3, NONE, NONE, NONE, NONE), 425 MFPR_MMP2(GPIO119, 0x270, GPIO, NONE, CA, SSP3, NONE, NONE, NONE, NONE),
426 MFPR_MMP2(GPIO120, 0x274, GPIO, NONE, CA, SSP3, NONE, NONE, NONE, NONE), 426 MFPR_MMP2(GPIO120, 0x274, GPIO, NONE, CA, SSP3, NONE, NONE, NONE, NONE),
427 MFPR_MMP2(GPIO121, 0x278, GPIO, NONE, CA, SSP3, NONE, NONE, NONE, NONE), 427 MFPR_MMP2(GPIO121, 0x278, GPIO, NONE, CA, SSP3, NONE, NONE, NONE, NONE),
428 MFPR_MMP2(GPIO122, 0x27C, GPIO, NONE, CA, SSP3, NONE, NONE, NONE, NONE), 428 MFPR_MMP2(GPIO122, 0x27C, GPIO, NONE, CA, SSP3, NONE, NONE, NONE, NONE),
429 MFPR_MMP2(GPIO123, 0x148, GPIO, SLEEP_IND, ONE_WIRE, 32K_CLKOUT, NONE, NONE, NONE, NONE), 429 MFPR_MMP2(GPIO123, 0x148, GPIO, SLEEP_IND, ONE_WIRE, 32K_CLKOUT, NONE, NONE, NONE, NONE),
430 MFPR_MMP2(GPIO124, 0x00C, GPIO, MMC1, LCD, MMC3, NAND, NONE, NONE, NONE), 430 MFPR_MMP2(GPIO124, 0x00C, GPIO, MMC1, LCD, MMC3, NAND, NONE, NONE, NONE),
431 MFPR_MMP2(GPIO125, 0x010, GPIO, MMC1, LCD, MMC3, NAND, NONE, NONE, NONE), 431 MFPR_MMP2(GPIO125, 0x010, GPIO, MMC1, LCD, MMC3, NAND, NONE, NONE, NONE),
432 MFPR_MMP2(GPIO126, 0x014, GPIO, MMC1, LCD, MMC3, NAND, NONE, NONE, NONE), 432 MFPR_MMP2(GPIO126, 0x014, GPIO, MMC1, LCD, MMC3, NAND, NONE, NONE, NONE),
433 MFPR_MMP2(GPIO127, 0x018, GPIO, NONE, LCD, MMC3, NAND, NONE, NONE, NONE), 433 MFPR_MMP2(GPIO127, 0x018, GPIO, NONE, LCD, MMC3, NAND, NONE, NONE, NONE),
434 MFPR_MMP2(GPIO128, 0x01C, GPIO, NONE, LCD, MMC3, NAND, NONE, NONE, NONE), 434 MFPR_MMP2(GPIO128, 0x01C, GPIO, NONE, LCD, MMC3, NAND, NONE, NONE, NONE),
435 MFPR_MMP2(GPIO129, 0x020, GPIO, MMC1, LCD, MMC3, NAND, NONE, NONE, NONE), 435 MFPR_MMP2(GPIO129, 0x020, GPIO, MMC1, LCD, MMC3, NAND, NONE, NONE, NONE),
436 MFPR_MMP2(GPIO130, 0x024, GPIO, MMC1, LCD, MMC3, NAND, NONE, NONE, NONE), 436 MFPR_MMP2(GPIO130, 0x024, GPIO, MMC1, LCD, MMC3, NAND, NONE, NONE, NONE),
437 MFPR_MMP2(GPIO131, 0x028, GPIO, MMC1, NONE, MSP, NONE, NONE, NONE, NONE), 437 MFPR_MMP2(GPIO131, 0x028, GPIO, MMC1, NONE, MSP, NONE, NONE, NONE, NONE),
438 MFPR_MMP2(GPIO132, 0x02C, GPIO, MMC1, PRI_JTAG, MSP, SSP3, AAS_JTAG, NONE, NONE), 438 MFPR_MMP2(GPIO132, 0x02C, GPIO, MMC1, PRI_JTAG, MSP, SSP3, AAS_JTAG, NONE, NONE),
439 MFPR_MMP2(GPIO133, 0x030, GPIO, MMC1, PRI_JTAG, MSP, SSP3, AAS_JTAG, NONE, NONE), 439 MFPR_MMP2(GPIO133, 0x030, GPIO, MMC1, PRI_JTAG, MSP, SSP3, AAS_JTAG, NONE, NONE),
440 MFPR_MMP2(GPIO134, 0x034, GPIO, MMC1, PRI_JTAG, MSP, SSP3, AAS_JTAG, NONE, NONE), 440 MFPR_MMP2(GPIO134, 0x034, GPIO, MMC1, PRI_JTAG, MSP, SSP3, AAS_JTAG, NONE, NONE),
441 MFPR_MMP2(GPIO135, 0x038, GPIO, NONE, LCD, MMC3, NAND, NONE, NONE, NONE), 441 MFPR_MMP2(GPIO135, 0x038, GPIO, NONE, LCD, MMC3, NAND, NONE, NONE, NONE),
442 MFPR_MMP2(GPIO136, 0x03C, GPIO, MMC1, PRI_JTAG, MSP, SSP3, AAS_JTAG, NONE, NONE), 442 MFPR_MMP2(GPIO136, 0x03C, GPIO, MMC1, PRI_JTAG, MSP, SSP3, AAS_JTAG, NONE, NONE),
443 MFPR_MMP2(GPIO137, 0x040, GPIO, HDMI, LCD, MSP, NONE, NONE, NONE, NONE), 443 MFPR_MMP2(GPIO137, 0x040, GPIO, HDMI, LCD, MSP, NONE, NONE, NONE, NONE),
444 MFPR_MMP2(GPIO138, 0x044, GPIO, NONE, LCD, MMC3, SMC, NONE, NONE, NONE), 444 MFPR_MMP2(GPIO138, 0x044, GPIO, NONE, LCD, MMC3, SMC, NONE, NONE, NONE),
445 MFPR_MMP2(GPIO139, 0x048, GPIO, MMC1, PRI_JTAG, MSP, NONE, AAS_JTAG, NONE, NONE), 445 MFPR_MMP2(GPIO139, 0x048, GPIO, MMC1, PRI_JTAG, MSP, NONE, AAS_JTAG, NONE, NONE),
446 MFPR_MMP2(GPIO140, 0x04C, GPIO, MMC1, LCD, NONE, NONE, UART2, UART1, NONE), 446 MFPR_MMP2(GPIO140, 0x04C, GPIO, MMC1, LCD, NONE, NONE, UART2, UART1, NONE),
447 MFPR_MMP2(GPIO141, 0x050, GPIO, MMC1, LCD, NONE, NONE, UART2, UART1, NONE), 447 MFPR_MMP2(GPIO141, 0x050, GPIO, MMC1, LCD, NONE, NONE, UART2, UART1, NONE),
448 MFPR_MMP2(GPIO142, 0x008, USIM, GPIO, FSIC, KP_DK, NONE, NONE, NONE, NONE), 448 MFPR_MMP2(GPIO142, 0x008, USIM, GPIO, FSIC, KP_DK, NONE, NONE, NONE, NONE),
449 MFPR_MMP2(GPIO143, 0x220, NAND, GPIO, SMC, NONE, NAND, NONE, NONE, NONE), 449 MFPR_MMP2(GPIO143, 0x220, NAND, GPIO, SMC, NONE, NAND, NONE, NONE, NONE),
450 MFPR_MMP2(GPIO144, 0x224, NAND, GPIO, SMC_INT, SMC, NAND, NONE, NONE, NONE), 450 MFPR_MMP2(GPIO144, 0x224, NAND, GPIO, SMC_INT, SMC, NAND, NONE, NONE, NONE),
451 MFPR_MMP2(GPIO145, 0x228, SMC, GPIO, NONE, NONE, SMC, NONE, NONE, NONE), 451 MFPR_MMP2(GPIO145, 0x228, SMC, GPIO, NONE, NONE, SMC, NONE, NONE, NONE),
452 MFPR_MMP2(GPIO146, 0x22C, SMC, GPIO, NONE, NONE, SMC, NONE, NONE, NONE), 452 MFPR_MMP2(GPIO146, 0x22C, SMC, GPIO, NONE, NONE, SMC, NONE, NONE, NONE),
453 MFPR_MMP2(GPIO147, 0x230, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE), 453 MFPR_MMP2(GPIO147, 0x230, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE),
454 MFPR_MMP2(GPIO148, 0x234, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE), 454 MFPR_MMP2(GPIO148, 0x234, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE),
455 MFPR_MMP2(GPIO149, 0x238, NAND, GPIO, NONE, NONE, NONE, NONE, NONE, NONE), 455 MFPR_MMP2(GPIO149, 0x238, NAND, GPIO, NONE, NONE, NONE, NONE, NONE, NONE),
456 MFPR_MMP2(GPIO150, 0x23C, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE), 456 MFPR_MMP2(GPIO150, 0x23C, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE),
457 MFPR_MMP2(GPIO151, 0x240, SMC, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE), 457 MFPR_MMP2(GPIO151, 0x240, SMC, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE),
458 MFPR_MMP2(GPIO152, 0x248, SMC, GPIO, NONE, NONE, SMC, NONE, NONE, NONE), 458 MFPR_MMP2(GPIO152, 0x248, SMC, GPIO, NONE, NONE, SMC, NONE, NONE, NONE),
459 MFPR_MMP2(GPIO153, 0x24C, SMC, GPIO, NONE, NONE, SMC, NONE, NONE, NONE), 459 MFPR_MMP2(GPIO153, 0x24C, SMC, GPIO, NONE, NONE, SMC, NONE, NONE, NONE),
460 MFPR_MMP2(GPIO154, 0x254, SMC_INT, GPIO, SMC, NONE, NAND, NONE, NONE, NONE), 460 MFPR_MMP2(GPIO154, 0x254, SMC_INT, GPIO, SMC, NONE, NAND, NONE, NONE, NONE),
461 MFPR_MMP2(GPIO155, 0x258, EXT_DMA, GPIO, SMC, NONE, EXT_DMA, NONE, NONE, NONE), 461 MFPR_MMP2(GPIO155, 0x258, EXT_DMA, GPIO, SMC, NONE, EXT_DMA, NONE, NONE, NONE),
462 MFPR_MMP2(GPIO156, 0x14C, PRI_JTAG, GPIO, PWM, NONE, NONE, NONE, NONE, NONE), 462 MFPR_MMP2(GPIO156, 0x14C, PRI_JTAG, GPIO, PWM, NONE, NONE, NONE, NONE, NONE),
463 MFPR_MMP2(GPIO157, 0x150, PRI_JTAG, GPIO, PWM, NONE, NONE, NONE, NONE, NONE), 463 MFPR_MMP2(GPIO157, 0x150, PRI_JTAG, GPIO, PWM, NONE, NONE, NONE, NONE, NONE),
464 MFPR_MMP2(GPIO158, 0x154, PRI_JTAG, GPIO, PWM, NONE, NONE, NONE, NONE, NONE), 464 MFPR_MMP2(GPIO158, 0x154, PRI_JTAG, GPIO, PWM, NONE, NONE, NONE, NONE, NONE),
465 MFPR_MMP2(GPIO159, 0x158, PRI_JTAG, GPIO, PWM, NONE, NONE, NONE, NONE, NONE), 465 MFPR_MMP2(GPIO159, 0x158, PRI_JTAG, GPIO, PWM, NONE, NONE, NONE, NONE, NONE),
466 MFPR_MMP2(GPIO160, 0x250, NAND, GPIO, SMC, NONE, NAND, NONE, NONE, NONE), 466 MFPR_MMP2(GPIO160, 0x250, NAND, GPIO, SMC, NONE, NAND, NONE, NONE, NONE),
467 MFPR_MMP2(GPIO161, 0x210, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE), 467 MFPR_MMP2(GPIO161, 0x210, NAND, GPIO, NONE, NONE, NAND, NONE, NONE, NONE),
468 MFPR_MMP2(GPIO162, 0x20C, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE), 468 MFPR_MMP2(GPIO162, 0x20C, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE),
469 MFPR_MMP2(GPIO163, 0x208, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE), 469 MFPR_MMP2(GPIO163, 0x208, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE),
470 MFPR_MMP2(GPIO164, 0x204, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE), 470 MFPR_MMP2(GPIO164, 0x204, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE),
471 MFPR_MMP2(GPIO165, 0x1EC, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE), 471 MFPR_MMP2(GPIO165, 0x1EC, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE),
472 MFPR_MMP2(GPIO166, 0x1E8, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE), 472 MFPR_MMP2(GPIO166, 0x1E8, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE),
473 MFPR_MMP2(GPIO167, 0x1E4, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE), 473 MFPR_MMP2(GPIO167, 0x1E4, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE),
474 MFPR_MMP2(GPIO168, 0x1E0, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE), 474 MFPR_MMP2(GPIO168, 0x1E0, NAND, GPIO, MMC3, NONE, NONE, NONE, NONE, NONE),
475 MFPR_MMP2(TWSI4_SCL, 0x2BC, TWSI4, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 475 MFPR_MMP2(TWSI4_SCL, 0x2BC, TWSI4, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
476 MFPR_MMP2(TWSI4_SDA, 0x2C0, TWSI4, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 476 MFPR_MMP2(TWSI4_SDA, 0x2C0, TWSI4, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
477 MFPR_MMP2(G_CLKREQ, 0x160, G_CLKREQ, ONE_WIRE, NONE, NONE, NONE, NONE, NONE, NONE), 477 MFPR_MMP2(G_CLKREQ, 0x160, G_CLKREQ, ONE_WIRE, NONE, NONE, NONE, NONE, NONE, NONE),
478 MFPR_MMP2(VCXO_REQ, 0x168, VCXO_REQ, ONE_WIRE, PLL, NONE, NONE, NONE, NONE, NONE), 478 MFPR_MMP2(VCXO_REQ, 0x168, VCXO_REQ, ONE_WIRE, PLL, NONE, NONE, NONE, NONE, NONE),
479 MFPR_MMP2(VCXO_OUT, 0x16C, VCXO_OUT, 32K_CLKOUT, NONE, NONE, NONE, NONE, NONE, NONE), 479 MFPR_MMP2(VCXO_OUT, 0x16C, VCXO_OUT, 32K_CLKOUT, NONE, NONE, NONE, NONE, NONE, NONE),
480 }; 480 };
481 481
482 static const unsigned mmp2_uart1_pin1[] = {GPIO29, GPIO30, GPIO31, GPIO32}; 482 static const unsigned mmp2_uart1_pin1[] = {GPIO29, GPIO30, GPIO31, GPIO32};
483 static const unsigned mmp2_uart1_pin2[] = {GPIO45, GPIO46}; 483 static const unsigned mmp2_uart1_pin2[] = {GPIO45, GPIO46};
484 static const unsigned mmp2_uart1_pin3[] = {GPIO140, GPIO141}; 484 static const unsigned mmp2_uart1_pin3[] = {GPIO140, GPIO141};
485 static const unsigned mmp2_uart2_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40}; 485 static const unsigned mmp2_uart2_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40};
486 static const unsigned mmp2_uart2_pin2[] = {GPIO43, GPIO44, GPIO45, GPIO46}; 486 static const unsigned mmp2_uart2_pin2[] = {GPIO43, GPIO44, GPIO45, GPIO46};
487 static const unsigned mmp2_uart2_pin3[] = {GPIO47, GPIO48, GPIO49, GPIO50}; 487 static const unsigned mmp2_uart2_pin3[] = {GPIO47, GPIO48, GPIO49, GPIO50};
488 static const unsigned mmp2_uart2_pin4[] = {GPIO74, GPIO75, GPIO76, GPIO77}; 488 static const unsigned mmp2_uart2_pin4[] = {GPIO74, GPIO75, GPIO76, GPIO77};
489 static const unsigned mmp2_uart2_pin5[] = {GPIO55, GPIO56}; 489 static const unsigned mmp2_uart2_pin5[] = {GPIO55, GPIO56};
490 static const unsigned mmp2_uart2_pin6[] = {GPIO140, GPIO141}; 490 static const unsigned mmp2_uart2_pin6[] = {GPIO140, GPIO141};
491 static const unsigned mmp2_uart3_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40}; 491 static const unsigned mmp2_uart3_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40};
492 static const unsigned mmp2_uart3_pin2[] = {GPIO43, GPIO44, GPIO45, GPIO46}; 492 static const unsigned mmp2_uart3_pin2[] = {GPIO43, GPIO44, GPIO45, GPIO46};
493 static const unsigned mmp2_uart3_pin3[] = {GPIO51, GPIO52, GPIO53, GPIO54}; 493 static const unsigned mmp2_uart3_pin3[] = {GPIO51, GPIO52, GPIO53, GPIO54};
494 static const unsigned mmp2_uart3_pin4[] = {GPIO59, GPIO60, GPIO61, GPIO62}; 494 static const unsigned mmp2_uart3_pin4[] = {GPIO59, GPIO60, GPIO61, GPIO62};
495 static const unsigned mmp2_uart3_pin5[] = {GPIO115, GPIO116, GPIO117, GPIO118}; 495 static const unsigned mmp2_uart3_pin5[] = {GPIO115, GPIO116, GPIO117, GPIO118};
496 static const unsigned mmp2_uart3_pin6[] = {GPIO51, GPIO52}; 496 static const unsigned mmp2_uart3_pin6[] = {GPIO51, GPIO52};
497 static const unsigned mmp2_uart4_pin1[] = {GPIO43, GPIO44, GPIO45, GPIO46}; 497 static const unsigned mmp2_uart4_pin1[] = {GPIO43, GPIO44, GPIO45, GPIO46};
498 static const unsigned mmp2_uart4_pin2[] = {GPIO63, GPIO64, GPIO65, GPIO66}; 498 static const unsigned mmp2_uart4_pin2[] = {GPIO63, GPIO64, GPIO65, GPIO66};
499 static const unsigned mmp2_uart4_pin3[] = {GPIO74, GPIO75, GPIO76, GPIO77}; 499 static const unsigned mmp2_uart4_pin3[] = {GPIO74, GPIO75, GPIO76, GPIO77};
500 static const unsigned mmp2_uart4_pin4[] = {GPIO115, GPIO116, GPIO117, GPIO118}; 500 static const unsigned mmp2_uart4_pin4[] = {GPIO115, GPIO116, GPIO117, GPIO118};
501 static const unsigned mmp2_uart4_pin5[] = {GPIO59, GPIO60}; 501 static const unsigned mmp2_uart4_pin5[] = {GPIO59, GPIO60};
502 static const unsigned mmp2_kpdk_pin1[] = {GPIO16, GPIO17, GPIO18, GPIO19}; 502 static const unsigned mmp2_kpdk_pin1[] = {GPIO16, GPIO17, GPIO18, GPIO19};
503 static const unsigned mmp2_kpdk_pin2[] = {GPIO16, GPIO17}; 503 static const unsigned mmp2_kpdk_pin2[] = {GPIO16, GPIO17};
504 static const unsigned mmp2_twsi2_pin1[] = {GPIO37, GPIO38}; 504 static const unsigned mmp2_twsi2_pin1[] = {GPIO37, GPIO38};
505 static const unsigned mmp2_twsi2_pin2[] = {GPIO39, GPIO40}; 505 static const unsigned mmp2_twsi2_pin2[] = {GPIO39, GPIO40};
506 static const unsigned mmp2_twsi2_pin3[] = {GPIO43, GPIO44}; 506 static const unsigned mmp2_twsi2_pin3[] = {GPIO43, GPIO44};
507 static const unsigned mmp2_twsi2_pin4[] = {GPIO53, GPIO54}; 507 static const unsigned mmp2_twsi2_pin4[] = {GPIO53, GPIO54};
508 static const unsigned mmp2_twsi2_pin5[] = {GPIO55, GPIO56}; 508 static const unsigned mmp2_twsi2_pin5[] = {GPIO55, GPIO56};
509 static const unsigned mmp2_twsi3_pin1[] = {GPIO71, GPIO72}; 509 static const unsigned mmp2_twsi3_pin1[] = {GPIO71, GPIO72};
510 static const unsigned mmp2_twsi3_pin2[] = {GPIO95, GPIO96}; 510 static const unsigned mmp2_twsi3_pin2[] = {GPIO95, GPIO96};
511 static const unsigned mmp2_twsi4_pin1[] = {TWSI4_SCL, TWSI4_SDA}; 511 static const unsigned mmp2_twsi4_pin1[] = {TWSI4_SCL, TWSI4_SDA};
512 static const unsigned mmp2_twsi5_pin1[] = {GPIO41, GPIO42}; 512 static const unsigned mmp2_twsi5_pin1[] = {GPIO41, GPIO42};
513 static const unsigned mmp2_twsi5_pin2[] = {GPIO84, GPIO85}; 513 static const unsigned mmp2_twsi5_pin2[] = {GPIO84, GPIO85};
514 static const unsigned mmp2_twsi5_pin3[] = {GPIO99, GPIO100}; 514 static const unsigned mmp2_twsi5_pin3[] = {GPIO99, GPIO100};
515 static const unsigned mmp2_twsi6_pin1[] = {GPIO47, GPIO48}; 515 static const unsigned mmp2_twsi6_pin1[] = {GPIO47, GPIO48};
516 static const unsigned mmp2_twsi6_pin2[] = {GPIO86, GPIO87}; 516 static const unsigned mmp2_twsi6_pin2[] = {GPIO86, GPIO87};
517 static const unsigned mmp2_twsi6_pin3[] = {GPIO97, GPIO98}; 517 static const unsigned mmp2_twsi6_pin3[] = {GPIO97, GPIO98};
518 static const unsigned mmp2_ccic1_pin1[] = {GPIO12, GPIO13, GPIO14, GPIO15, 518 static const unsigned mmp2_ccic1_pin1[] = {GPIO12, GPIO13, GPIO14, GPIO15,
519 GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23}; 519 GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23};
520 static const unsigned mmp2_ccic1_pin2[] = {GPIO59, GPIO60, GPIO61, GPIO62, 520 static const unsigned mmp2_ccic1_pin2[] = {GPIO59, GPIO60, GPIO61, GPIO62,
521 GPIO63, GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70}; 521 GPIO63, GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70};
522 static const unsigned mmp2_ccic2_pin1[] = {GPIO59, GPIO60, GPIO61, GPIO62, 522 static const unsigned mmp2_ccic2_pin1[] = {GPIO59, GPIO60, GPIO61, GPIO62,
523 GPIO63, GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70}; 523 GPIO63, GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70};
524 static const unsigned mmp2_ccic2_pin2[] = {GPIO82, GPIO83, GPIO86, GPIO87, 524 static const unsigned mmp2_ccic2_pin2[] = {GPIO82, GPIO83, GPIO86, GPIO87,
525 GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95}; 525 GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95};
526 static const unsigned mmp2_ulpi_pin1[] = {GPIO59, GPIO60, GPIO61, GPIO62, 526 static const unsigned mmp2_ulpi_pin1[] = {GPIO59, GPIO60, GPIO61, GPIO62,
527 GPIO63, GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70}; 527 GPIO63, GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70};
528 static const unsigned mmp2_ro_pin1[] = {GPIO16, GPIO17}; 528 static const unsigned mmp2_ro_pin1[] = {GPIO16, GPIO17};
529 static const unsigned mmp2_ro_pin2[] = {GPIO18, GPIO19}; 529 static const unsigned mmp2_ro_pin2[] = {GPIO18, GPIO19};
530 static const unsigned mmp2_ro_pin3[] = {GPIO51, GPIO52}; 530 static const unsigned mmp2_ro_pin3[] = {GPIO51, GPIO52};
531 static const unsigned mmp2_ro_pin4[] = {GPIO55, GPIO56}; 531 static const unsigned mmp2_ro_pin4[] = {GPIO55, GPIO56};
532 static const unsigned mmp2_i2s_pin1[] = {GPIO24, GPIO25, GPIO26, GPIO27, 532 static const unsigned mmp2_i2s_pin1[] = {GPIO24, GPIO25, GPIO26, GPIO27,
533 GPIO28}; 533 GPIO28};
534 static const unsigned mmp2_i2s_pin2[] = {GPIO33, GPIO34, GPIO35, GPIO36}; 534 static const unsigned mmp2_i2s_pin2[] = {GPIO33, GPIO34, GPIO35, GPIO36};
535 static const unsigned mmp2_ssp1_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40}; 535 static const unsigned mmp2_ssp1_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40};
536 static const unsigned mmp2_ssp1_pin2[] = {GPIO43, GPIO44, GPIO45, GPIO46}; 536 static const unsigned mmp2_ssp1_pin2[] = {GPIO43, GPIO44, GPIO45, GPIO46};
537 static const unsigned mmp2_ssp1_pin3[] = {GPIO115, GPIO116, GPIO117, GPIO118}; 537 static const unsigned mmp2_ssp1_pin3[] = {GPIO115, GPIO116, GPIO117, GPIO118};
538 static const unsigned mmp2_ssp2_pin1[] = {GPIO47, GPIO48, GPIO49, GPIO50}; 538 static const unsigned mmp2_ssp2_pin1[] = {GPIO47, GPIO48, GPIO49, GPIO50};
539 static const unsigned mmp2_ssp3_pin1[] = {GPIO119, GPIO120, GPIO121, GPIO122}; 539 static const unsigned mmp2_ssp3_pin1[] = {GPIO119, GPIO120, GPIO121, GPIO122};
540 static const unsigned mmp2_ssp3_pin2[] = {GPIO132, GPIO133, GPIO133, GPIO136}; 540 static const unsigned mmp2_ssp3_pin2[] = {GPIO132, GPIO133, GPIO133, GPIO136};
541 static const unsigned mmp2_sspa2_pin1[] = {GPIO25, GPIO26, GPIO27, GPIO28}; 541 static const unsigned mmp2_sspa2_pin1[] = {GPIO25, GPIO26, GPIO27, GPIO28};
542 static const unsigned mmp2_sspa2_pin2[] = {GPIO33, GPIO34, GPIO35, GPIO36}; 542 static const unsigned mmp2_sspa2_pin2[] = {GPIO33, GPIO34, GPIO35, GPIO36};
543 static const unsigned mmp2_mmc1_pin1[] = {GPIO131, GPIO132, GPIO133, GPIO134, 543 static const unsigned mmp2_mmc1_pin1[] = {GPIO131, GPIO132, GPIO133, GPIO134,
544 GPIO136, GPIO139, GPIO140, GPIO141}; 544 GPIO136, GPIO139, GPIO140, GPIO141};
545 static const unsigned mmp2_mmc2_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40, 545 static const unsigned mmp2_mmc2_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40,
546 GPIO41, GPIO42}; 546 GPIO41, GPIO42};
547 static const unsigned mmp2_mmc3_pin1[] = {GPIO111, GPIO112, GPIO151, GPIO162, 547 static const unsigned mmp2_mmc3_pin1[] = {GPIO111, GPIO112, GPIO151, GPIO162,
548 GPIO163, GPIO164, GPIO165, GPIO166, GPIO167, GPIO168}; 548 GPIO163, GPIO164, GPIO165, GPIO166, GPIO167, GPIO168};
549 549
550 static struct pxa3xx_pin_group mmp2_grps[] = { 550 static struct pxa3xx_pin_group mmp2_grps[] = {
551 GRP_MMP2("uart1 4p1", UART1, mmp2_uart1_pin1), 551 GRP_MMP2("uart1 4p1", UART1, mmp2_uart1_pin1),
552 GRP_MMP2("uart1 2p2", UART1, mmp2_uart1_pin2), 552 GRP_MMP2("uart1 2p2", UART1, mmp2_uart1_pin2),
553 GRP_MMP2("uart1 2p3", UART1, mmp2_uart1_pin3), 553 GRP_MMP2("uart1 2p3", UART1, mmp2_uart1_pin3),
554 GRP_MMP2("uart2 4p1", UART2, mmp2_uart2_pin1), 554 GRP_MMP2("uart2 4p1", UART2, mmp2_uart2_pin1),
555 GRP_MMP2("uart2 4p2", UART2, mmp2_uart2_pin2), 555 GRP_MMP2("uart2 4p2", UART2, mmp2_uart2_pin2),
556 GRP_MMP2("uart2 4p3", UART2, mmp2_uart2_pin3), 556 GRP_MMP2("uart2 4p3", UART2, mmp2_uart2_pin3),
557 GRP_MMP2("uart2 4p4", UART2, mmp2_uart2_pin4), 557 GRP_MMP2("uart2 4p4", UART2, mmp2_uart2_pin4),
558 GRP_MMP2("uart2 2p5", UART2, mmp2_uart2_pin5), 558 GRP_MMP2("uart2 2p5", UART2, mmp2_uart2_pin5),
559 GRP_MMP2("uart2 2p6", UART2, mmp2_uart2_pin6), 559 GRP_MMP2("uart2 2p6", UART2, mmp2_uart2_pin6),
560 GRP_MMP2("uart3 4p1", UART3, mmp2_uart3_pin1), 560 GRP_MMP2("uart3 4p1", UART3, mmp2_uart3_pin1),
561 GRP_MMP2("uart3 4p2", UART3, mmp2_uart3_pin2), 561 GRP_MMP2("uart3 4p2", UART3, mmp2_uart3_pin2),
562 GRP_MMP2("uart3 4p3", UART3, mmp2_uart3_pin3), 562 GRP_MMP2("uart3 4p3", UART3, mmp2_uart3_pin3),
563 GRP_MMP2("uart3 4p4", UART3, mmp2_uart3_pin4), 563 GRP_MMP2("uart3 4p4", UART3, mmp2_uart3_pin4),
564 GRP_MMP2("uart3 4p5", UART3, mmp2_uart3_pin5), 564 GRP_MMP2("uart3 4p5", UART3, mmp2_uart3_pin5),
565 GRP_MMP2("uart3 2p6", UART3, mmp2_uart3_pin6), 565 GRP_MMP2("uart3 2p6", UART3, mmp2_uart3_pin6),
566 GRP_MMP2("uart4 4p1", UART4, mmp2_uart4_pin1), 566 GRP_MMP2("uart4 4p1", UART4, mmp2_uart4_pin1),
567 GRP_MMP2("uart4 4p2", UART4, mmp2_uart4_pin2), 567 GRP_MMP2("uart4 4p2", UART4, mmp2_uart4_pin2),
568 GRP_MMP2("uart4 4p3", UART4, mmp2_uart4_pin3), 568 GRP_MMP2("uart4 4p3", UART4, mmp2_uart4_pin3),
569 GRP_MMP2("uart4 4p4", UART4, mmp2_uart4_pin4), 569 GRP_MMP2("uart4 4p4", UART4, mmp2_uart4_pin4),
570 GRP_MMP2("uart4 2p5", UART4, mmp2_uart4_pin5), 570 GRP_MMP2("uart4 2p5", UART4, mmp2_uart4_pin5),
571 GRP_MMP2("kpdk 4p1", KP_DK, mmp2_kpdk_pin1), 571 GRP_MMP2("kpdk 4p1", KP_DK, mmp2_kpdk_pin1),
572 GRP_MMP2("kpdk 4p2", KP_DK, mmp2_kpdk_pin2), 572 GRP_MMP2("kpdk 4p2", KP_DK, mmp2_kpdk_pin2),
573 GRP_MMP2("twsi2-1", TWSI2, mmp2_twsi2_pin1), 573 GRP_MMP2("twsi2-1", TWSI2, mmp2_twsi2_pin1),
574 GRP_MMP2("twsi2-2", TWSI2, mmp2_twsi2_pin2), 574 GRP_MMP2("twsi2-2", TWSI2, mmp2_twsi2_pin2),
575 GRP_MMP2("twsi2-3", TWSI2, mmp2_twsi2_pin3), 575 GRP_MMP2("twsi2-3", TWSI2, mmp2_twsi2_pin3),
576 GRP_MMP2("twsi2-4", TWSI2, mmp2_twsi2_pin4), 576 GRP_MMP2("twsi2-4", TWSI2, mmp2_twsi2_pin4),
577 GRP_MMP2("twsi2-5", TWSI2, mmp2_twsi2_pin5), 577 GRP_MMP2("twsi2-5", TWSI2, mmp2_twsi2_pin5),
578 GRP_MMP2("twsi3-1", TWSI3, mmp2_twsi3_pin1), 578 GRP_MMP2("twsi3-1", TWSI3, mmp2_twsi3_pin1),
579 GRP_MMP2("twsi3-2", TWSI3, mmp2_twsi3_pin2), 579 GRP_MMP2("twsi3-2", TWSI3, mmp2_twsi3_pin2),
580 GRP_MMP2("twsi4", TWSI4, mmp2_twsi4_pin1), 580 GRP_MMP2("twsi4", TWSI4, mmp2_twsi4_pin1),
581 GRP_MMP2("twsi5-1", TWSI5, mmp2_twsi5_pin1), 581 GRP_MMP2("twsi5-1", TWSI5, mmp2_twsi5_pin1),
582 GRP_MMP2("twsi5-2", TWSI5, mmp2_twsi5_pin2), 582 GRP_MMP2("twsi5-2", TWSI5, mmp2_twsi5_pin2),
583 GRP_MMP2("twsi5-3", TWSI5, mmp2_twsi5_pin3), 583 GRP_MMP2("twsi5-3", TWSI5, mmp2_twsi5_pin3),
584 GRP_MMP2("twsi6-1", TWSI6, mmp2_twsi6_pin1), 584 GRP_MMP2("twsi6-1", TWSI6, mmp2_twsi6_pin1),
585 GRP_MMP2("twsi6-2", TWSI6, mmp2_twsi6_pin2), 585 GRP_MMP2("twsi6-2", TWSI6, mmp2_twsi6_pin2),
586 GRP_MMP2("twsi6-3", TWSI6, mmp2_twsi6_pin3), 586 GRP_MMP2("twsi6-3", TWSI6, mmp2_twsi6_pin3),
587 GRP_MMP2("ccic1-1", CCIC1, mmp2_ccic1_pin1), 587 GRP_MMP2("ccic1-1", CCIC1, mmp2_ccic1_pin1),
588 GRP_MMP2("ccic1-2", CCIC1, mmp2_ccic1_pin2), 588 GRP_MMP2("ccic1-2", CCIC1, mmp2_ccic1_pin2),
589 GRP_MMP2("ccic2-1", CCIC2, mmp2_ccic2_pin1), 589 GRP_MMP2("ccic2-1", CCIC2, mmp2_ccic2_pin1),
590 GRP_MMP2("ccic2-1", CCIC2, mmp2_ccic2_pin2), 590 GRP_MMP2("ccic2-1", CCIC2, mmp2_ccic2_pin2),
591 GRP_MMP2("ulpi", ULPI, mmp2_ulpi_pin1), 591 GRP_MMP2("ulpi", ULPI, mmp2_ulpi_pin1),
592 GRP_MMP2("ro-1", ROT, mmp2_ro_pin1), 592 GRP_MMP2("ro-1", ROT, mmp2_ro_pin1),
593 GRP_MMP2("ro-2", ROT, mmp2_ro_pin2), 593 GRP_MMP2("ro-2", ROT, mmp2_ro_pin2),
594 GRP_MMP2("ro-3", ROT, mmp2_ro_pin3), 594 GRP_MMP2("ro-3", ROT, mmp2_ro_pin3),
595 GRP_MMP2("ro-4", ROT, mmp2_ro_pin4), 595 GRP_MMP2("ro-4", ROT, mmp2_ro_pin4),
596 GRP_MMP2("i2s 5p1", I2S, mmp2_i2s_pin1), 596 GRP_MMP2("i2s 5p1", I2S, mmp2_i2s_pin1),
597 GRP_MMP2("i2s 4p2", I2S, mmp2_i2s_pin2), 597 GRP_MMP2("i2s 4p2", I2S, mmp2_i2s_pin2),
598 GRP_MMP2("ssp1 4p1", SSP1, mmp2_ssp1_pin1), 598 GRP_MMP2("ssp1 4p1", SSP1, mmp2_ssp1_pin1),
599 GRP_MMP2("ssp1 4p2", SSP1, mmp2_ssp1_pin2), 599 GRP_MMP2("ssp1 4p2", SSP1, mmp2_ssp1_pin2),
600 GRP_MMP2("ssp1 4p3", SSP1, mmp2_ssp1_pin3), 600 GRP_MMP2("ssp1 4p3", SSP1, mmp2_ssp1_pin3),
601 GRP_MMP2("ssp2 4p1", SSP2, mmp2_ssp2_pin1), 601 GRP_MMP2("ssp2 4p1", SSP2, mmp2_ssp2_pin1),
602 GRP_MMP2("ssp3 4p1", SSP3, mmp2_ssp3_pin1), 602 GRP_MMP2("ssp3 4p1", SSP3, mmp2_ssp3_pin1),
603 GRP_MMP2("ssp3 4p2", SSP3, mmp2_ssp3_pin2), 603 GRP_MMP2("ssp3 4p2", SSP3, mmp2_ssp3_pin2),
604 GRP_MMP2("sspa2 4p1", SSPA2, mmp2_sspa2_pin1), 604 GRP_MMP2("sspa2 4p1", SSPA2, mmp2_sspa2_pin1),
605 GRP_MMP2("sspa2 4p2", SSPA2, mmp2_sspa2_pin2), 605 GRP_MMP2("sspa2 4p2", SSPA2, mmp2_sspa2_pin2),
606 GRP_MMP2("mmc1 8p1", MMC1, mmp2_mmc1_pin1), 606 GRP_MMP2("mmc1 8p1", MMC1, mmp2_mmc1_pin1),
607 GRP_MMP2("mmc2 6p1", MMC2, mmp2_mmc2_pin1), 607 GRP_MMP2("mmc2 6p1", MMC2, mmp2_mmc2_pin1),
608 GRP_MMP2("mmc3 10p1", MMC3, mmp2_mmc3_pin1), 608 GRP_MMP2("mmc3 10p1", MMC3, mmp2_mmc3_pin1),
609 }; 609 };
610 610
611 static const char * const mmp2_uart1_grps[] = {"uart1 4p1", "uart1 2p2", 611 static const char * const mmp2_uart1_grps[] = {"uart1 4p1", "uart1 2p2",
612 "uart1 2p3"}; 612 "uart1 2p3"};
613 static const char * const mmp2_uart2_grps[] = {"uart2 4p1", "uart2 4p2", 613 static const char * const mmp2_uart2_grps[] = {"uart2 4p1", "uart2 4p2",
614 "uart2 4p3", "uart2 4p4", "uart2 4p5", "uart2 4p6"}; 614 "uart2 4p3", "uart2 4p4", "uart2 4p5", "uart2 4p6"};
615 static const char * const mmp2_uart3_grps[] = {"uart3 4p1", "uart3 4p2", 615 static const char * const mmp2_uart3_grps[] = {"uart3 4p1", "uart3 4p2",
616 "uart3 4p3", "uart3 4p4", "uart3 4p5", "uart3 2p6"}; 616 "uart3 4p3", "uart3 4p4", "uart3 4p5", "uart3 2p6"};
617 static const char * const mmp2_uart4_grps[] = {"uart4 4p1", "uart4 4p2", 617 static const char * const mmp2_uart4_grps[] = {"uart4 4p1", "uart4 4p2",
618 "uart4 4p3", "uart4 4p4", "uart4 2p5"}; 618 "uart4 4p3", "uart4 4p4", "uart4 2p5"};
619 static const char * const mmp2_kpdk_grps[] = {"kpdk 4p1", "kpdk 4p2"}; 619 static const char * const mmp2_kpdk_grps[] = {"kpdk 4p1", "kpdk 4p2"};
620 static const char * const mmp2_twsi2_grps[] = {"twsi2-1", "twsi2-2", 620 static const char * const mmp2_twsi2_grps[] = {"twsi2-1", "twsi2-2",
621 "twsi2-3", "twsi2-4", "twsi2-5"}; 621 "twsi2-3", "twsi2-4", "twsi2-5"};
622 static const char * const mmp2_twsi3_grps[] = {"twsi3-1", "twsi3-2"}; 622 static const char * const mmp2_twsi3_grps[] = {"twsi3-1", "twsi3-2"};
623 static const char * const mmp2_twsi4_grps[] = {"twsi4"}; 623 static const char * const mmp2_twsi4_grps[] = {"twsi4"};
624 static const char * const mmp2_twsi5_grps[] = {"twsi5-1", "twsi5-2", 624 static const char * const mmp2_twsi5_grps[] = {"twsi5-1", "twsi5-2",
625 "twsi5-3"}; 625 "twsi5-3"};
626 static const char * const mmp2_twsi6_grps[] = {"twsi6-1", "twsi6-2", 626 static const char * const mmp2_twsi6_grps[] = {"twsi6-1", "twsi6-2",
627 "twsi6-3"}; 627 "twsi6-3"};
628 static const char * const mmp2_ccic1_grps[] = {"ccic1-1", "ccic1-2"}; 628 static const char * const mmp2_ccic1_grps[] = {"ccic1-1", "ccic1-2"};
629 static const char * const mmp2_ccic2_grps[] = {"ccic2-1", "ccic2-2"}; 629 static const char * const mmp2_ccic2_grps[] = {"ccic2-1", "ccic2-2"};
630 static const char * const mmp2_ulpi_grps[] = {"ulpi"}; 630 static const char * const mmp2_ulpi_grps[] = {"ulpi"};
631 static const char * const mmp2_ro_grps[] = {"ro-1", "ro-2", "ro-3", "ro-4"}; 631 static const char * const mmp2_ro_grps[] = {"ro-1", "ro-2", "ro-3", "ro-4"};
632 static const char * const mmp2_i2s_grps[] = {"i2s 5p1", "i2s 4p2"}; 632 static const char * const mmp2_i2s_grps[] = {"i2s 5p1", "i2s 4p2"};
633 static const char * const mmp2_ssp1_grps[] = {"ssp1 4p1", "ssp1 4p2", 633 static const char * const mmp2_ssp1_grps[] = {"ssp1 4p1", "ssp1 4p2",
634 "ssp1 4p3"}; 634 "ssp1 4p3"};
635 static const char * const mmp2_ssp2_grps[] = {"ssp2 4p1"}; 635 static const char * const mmp2_ssp2_grps[] = {"ssp2 4p1"};
636 static const char * const mmp2_ssp3_grps[] = {"ssp3 4p1", "ssp3 4p2"}; 636 static const char * const mmp2_ssp3_grps[] = {"ssp3 4p1", "ssp3 4p2"};
637 static const char * const mmp2_sspa2_grps[] = {"sspa2 4p1", "sspa2 4p2"}; 637 static const char * const mmp2_sspa2_grps[] = {"sspa2 4p1", "sspa2 4p2"};
638 static const char * const mmp2_mmc1_grps[] = {"mmc1 8p1"}; 638 static const char * const mmp2_mmc1_grps[] = {"mmc1 8p1"};
639 static const char * const mmp2_mmc2_grps[] = {"mmc2 6p1"}; 639 static const char * const mmp2_mmc2_grps[] = {"mmc2 6p1"};
640 static const char * const mmp2_mmc3_grps[] = {"mmc3 10p1"}; 640 static const char * const mmp2_mmc3_grps[] = {"mmc3 10p1"};
641 641
642 static struct pxa3xx_pmx_func mmp2_funcs[] = { 642 static struct pxa3xx_pmx_func mmp2_funcs[] = {
643 {"uart1", ARRAY_AND_SIZE(mmp2_uart1_grps)}, 643 {"uart1", ARRAY_AND_SIZE(mmp2_uart1_grps)},
644 {"uart2", ARRAY_AND_SIZE(mmp2_uart2_grps)}, 644 {"uart2", ARRAY_AND_SIZE(mmp2_uart2_grps)},
645 {"uart3", ARRAY_AND_SIZE(mmp2_uart3_grps)}, 645 {"uart3", ARRAY_AND_SIZE(mmp2_uart3_grps)},
646 {"uart4", ARRAY_AND_SIZE(mmp2_uart4_grps)}, 646 {"uart4", ARRAY_AND_SIZE(mmp2_uart4_grps)},
647 {"kpdk", ARRAY_AND_SIZE(mmp2_kpdk_grps)}, 647 {"kpdk", ARRAY_AND_SIZE(mmp2_kpdk_grps)},
648 {"twsi2", ARRAY_AND_SIZE(mmp2_twsi2_grps)}, 648 {"twsi2", ARRAY_AND_SIZE(mmp2_twsi2_grps)},
649 {"twsi3", ARRAY_AND_SIZE(mmp2_twsi3_grps)}, 649 {"twsi3", ARRAY_AND_SIZE(mmp2_twsi3_grps)},
650 {"twsi4", ARRAY_AND_SIZE(mmp2_twsi4_grps)}, 650 {"twsi4", ARRAY_AND_SIZE(mmp2_twsi4_grps)},
651 {"twsi5", ARRAY_AND_SIZE(mmp2_twsi5_grps)}, 651 {"twsi5", ARRAY_AND_SIZE(mmp2_twsi5_grps)},
652 {"twsi6", ARRAY_AND_SIZE(mmp2_twsi6_grps)}, 652 {"twsi6", ARRAY_AND_SIZE(mmp2_twsi6_grps)},
653 {"ccic1", ARRAY_AND_SIZE(mmp2_ccic1_grps)}, 653 {"ccic1", ARRAY_AND_SIZE(mmp2_ccic1_grps)},
654 {"ccic2", ARRAY_AND_SIZE(mmp2_ccic2_grps)}, 654 {"ccic2", ARRAY_AND_SIZE(mmp2_ccic2_grps)},
655 {"ulpi", ARRAY_AND_SIZE(mmp2_ulpi_grps)}, 655 {"ulpi", ARRAY_AND_SIZE(mmp2_ulpi_grps)},
656 {"ro", ARRAY_AND_SIZE(mmp2_ro_grps)}, 656 {"ro", ARRAY_AND_SIZE(mmp2_ro_grps)},
657 {"i2s", ARRAY_AND_SIZE(mmp2_i2s_grps)}, 657 {"i2s", ARRAY_AND_SIZE(mmp2_i2s_grps)},
658 {"ssp1", ARRAY_AND_SIZE(mmp2_ssp1_grps)}, 658 {"ssp1", ARRAY_AND_SIZE(mmp2_ssp1_grps)},
659 {"ssp2", ARRAY_AND_SIZE(mmp2_ssp2_grps)}, 659 {"ssp2", ARRAY_AND_SIZE(mmp2_ssp2_grps)},
660 {"ssp3", ARRAY_AND_SIZE(mmp2_ssp3_grps)}, 660 {"ssp3", ARRAY_AND_SIZE(mmp2_ssp3_grps)},
661 {"sspa2", ARRAY_AND_SIZE(mmp2_sspa2_grps)}, 661 {"sspa2", ARRAY_AND_SIZE(mmp2_sspa2_grps)},
662 {"mmc1", ARRAY_AND_SIZE(mmp2_mmc1_grps)}, 662 {"mmc1", ARRAY_AND_SIZE(mmp2_mmc1_grps)},
663 {"mmc2", ARRAY_AND_SIZE(mmp2_mmc2_grps)}, 663 {"mmc2", ARRAY_AND_SIZE(mmp2_mmc2_grps)},
664 {"mmc3", ARRAY_AND_SIZE(mmp2_mmc3_grps)}, 664 {"mmc3", ARRAY_AND_SIZE(mmp2_mmc3_grps)},
665 }; 665 };
666 666
667 static struct pinctrl_desc mmp2_pctrl_desc = { 667 static struct pinctrl_desc mmp2_pctrl_desc = {
668 .name = "mmp2-pinctrl", 668 .name = "mmp2-pinctrl",
669 .owner = THIS_MODULE, 669 .owner = THIS_MODULE,
670 }; 670 };
671 671
672 static struct pxa3xx_pinmux_info mmp2_info = { 672 static struct pxa3xx_pinmux_info mmp2_info = {
673 .mfp = mmp2_mfp, 673 .mfp = mmp2_mfp,
674 .num_mfp = ARRAY_SIZE(mmp2_mfp), 674 .num_mfp = ARRAY_SIZE(mmp2_mfp),
675 .grps = mmp2_grps, 675 .grps = mmp2_grps,
676 .num_grps = ARRAY_SIZE(mmp2_grps), 676 .num_grps = ARRAY_SIZE(mmp2_grps),
677 .funcs = mmp2_funcs, 677 .funcs = mmp2_funcs,
678 .num_funcs = ARRAY_SIZE(mmp2_funcs), 678 .num_funcs = ARRAY_SIZE(mmp2_funcs),
679 .num_gpio = 169, 679 .num_gpio = 169,
680 .desc = &mmp2_pctrl_desc, 680 .desc = &mmp2_pctrl_desc,
681 .pads = mmp2_pads, 681 .pads = mmp2_pads,
682 .num_pads = ARRAY_SIZE(mmp2_pads), 682 .num_pads = ARRAY_SIZE(mmp2_pads),
683 683
684 .cputype = PINCTRL_MMP2, 684 .cputype = PINCTRL_MMP2,
685 .ds_mask = MMP2_DS_MASK, 685 .ds_mask = MMP2_DS_MASK,
686 .ds_shift = MMP2_DS_SHIFT, 686 .ds_shift = MMP2_DS_SHIFT,
687 }; 687 };
688 688
689 static int __devinit mmp2_pinmux_probe(struct platform_device *pdev) 689 static int __devinit mmp2_pinmux_probe(struct platform_device *pdev)
690 { 690 {
691 return pxa3xx_pinctrl_register(pdev, &mmp2_info); 691 return pxa3xx_pinctrl_register(pdev, &mmp2_info);
692 } 692 }
693 693
694 static int __devexit mmp2_pinmux_remove(struct platform_device *pdev) 694 static int mmp2_pinmux_remove(struct platform_device *pdev)
695 { 695 {
696 return pxa3xx_pinctrl_unregister(pdev); 696 return pxa3xx_pinctrl_unregister(pdev);
697 } 697 }
698 698
699 static struct platform_driver mmp2_pinmux_driver = { 699 static struct platform_driver mmp2_pinmux_driver = {
700 .driver = { 700 .driver = {
701 .name = "mmp2-pinmux", 701 .name = "mmp2-pinmux",
702 .owner = THIS_MODULE, 702 .owner = THIS_MODULE,
703 }, 703 },
704 .probe = mmp2_pinmux_probe, 704 .probe = mmp2_pinmux_probe,
705 .remove = mmp2_pinmux_remove, 705 .remove = mmp2_pinmux_remove,
706 }; 706 };
707 707
708 static int __init mmp2_pinmux_init(void) 708 static int __init mmp2_pinmux_init(void)
709 { 709 {
710 return platform_driver_register(&mmp2_pinmux_driver); 710 return platform_driver_register(&mmp2_pinmux_driver);
711 } 711 }
712 core_initcall_sync(mmp2_pinmux_init); 712 core_initcall_sync(mmp2_pinmux_init);
713 713
714 static void __exit mmp2_pinmux_exit(void) 714 static void __exit mmp2_pinmux_exit(void)
715 { 715 {
716 platform_driver_unregister(&mmp2_pinmux_driver); 716 platform_driver_unregister(&mmp2_pinmux_driver);
717 } 717 }
718 module_exit(mmp2_pinmux_exit); 718 module_exit(mmp2_pinmux_exit);
719 719
720 MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com>"); 720 MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com>");
721 MODULE_DESCRIPTION("PXA3xx pin control driver"); 721 MODULE_DESCRIPTION("PXA3xx pin control driver");
722 MODULE_LICENSE("GPL v2"); 722 MODULE_LICENSE("GPL v2");
723 723
drivers/pinctrl/pinctrl-mxs.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc. 2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License 5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations: 6 * Version 2 or later at the following locations:
7 * 7 *
8 * http://www.opensource.org/licenses/gpl-license.html 8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12 #include <linux/err.h> 12 #include <linux/err.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/io.h> 14 #include <linux/io.h>
15 #include <linux/module.h> 15 #include <linux/module.h>
16 #include <linux/of.h> 16 #include <linux/of.h>
17 #include <linux/of_address.h> 17 #include <linux/of_address.h>
18 #include <linux/pinctrl/machine.h> 18 #include <linux/pinctrl/machine.h>
19 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h> 21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/platform_device.h> 22 #include <linux/platform_device.h>
23 #include <linux/slab.h> 23 #include <linux/slab.h>
24 #include "core.h" 24 #include "core.h"
25 #include "pinctrl-mxs.h" 25 #include "pinctrl-mxs.h"
26 26
27 #define SUFFIX_LEN 4 27 #define SUFFIX_LEN 4
28 28
29 struct mxs_pinctrl_data { 29 struct mxs_pinctrl_data {
30 struct device *dev; 30 struct device *dev;
31 struct pinctrl_dev *pctl; 31 struct pinctrl_dev *pctl;
32 void __iomem *base; 32 void __iomem *base;
33 struct mxs_pinctrl_soc_data *soc; 33 struct mxs_pinctrl_soc_data *soc;
34 }; 34 };
35 35
36 static int mxs_get_groups_count(struct pinctrl_dev *pctldev) 36 static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
37 { 37 {
38 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); 38 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
39 39
40 return d->soc->ngroups; 40 return d->soc->ngroups;
41 } 41 }
42 42
43 static const char *mxs_get_group_name(struct pinctrl_dev *pctldev, 43 static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
44 unsigned group) 44 unsigned group)
45 { 45 {
46 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); 46 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
47 47
48 return d->soc->groups[group].name; 48 return d->soc->groups[group].name;
49 } 49 }
50 50
51 static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 51 static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
52 const unsigned **pins, unsigned *num_pins) 52 const unsigned **pins, unsigned *num_pins)
53 { 53 {
54 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); 54 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
55 55
56 *pins = d->soc->groups[group].pins; 56 *pins = d->soc->groups[group].pins;
57 *num_pins = d->soc->groups[group].npins; 57 *num_pins = d->soc->groups[group].npins;
58 58
59 return 0; 59 return 0;
60 } 60 }
61 61
62 static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 62 static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
63 unsigned offset) 63 unsigned offset)
64 { 64 {
65 seq_printf(s, " %s", dev_name(pctldev->dev)); 65 seq_printf(s, " %s", dev_name(pctldev->dev));
66 } 66 }
67 67
68 static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev, 68 static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
69 struct device_node *np, 69 struct device_node *np,
70 struct pinctrl_map **map, unsigned *num_maps) 70 struct pinctrl_map **map, unsigned *num_maps)
71 { 71 {
72 struct pinctrl_map *new_map; 72 struct pinctrl_map *new_map;
73 char *group = NULL; 73 char *group = NULL;
74 unsigned new_num = 1; 74 unsigned new_num = 1;
75 unsigned long config = 0; 75 unsigned long config = 0;
76 unsigned long *pconfig; 76 unsigned long *pconfig;
77 int length = strlen(np->name) + SUFFIX_LEN; 77 int length = strlen(np->name) + SUFFIX_LEN;
78 bool purecfg = false; 78 bool purecfg = false;
79 u32 val, reg; 79 u32 val, reg;
80 int ret, i = 0; 80 int ret, i = 0;
81 81
82 /* Check for pin config node which has no 'reg' property */ 82 /* Check for pin config node which has no 'reg' property */
83 if (of_property_read_u32(np, "reg", &reg)) 83 if (of_property_read_u32(np, "reg", &reg))
84 purecfg = true; 84 purecfg = true;
85 85
86 ret = of_property_read_u32(np, "fsl,drive-strength", &val); 86 ret = of_property_read_u32(np, "fsl,drive-strength", &val);
87 if (!ret) 87 if (!ret)
88 config = val | MA_PRESENT; 88 config = val | MA_PRESENT;
89 ret = of_property_read_u32(np, "fsl,voltage", &val); 89 ret = of_property_read_u32(np, "fsl,voltage", &val);
90 if (!ret) 90 if (!ret)
91 config |= val << VOL_SHIFT | VOL_PRESENT; 91 config |= val << VOL_SHIFT | VOL_PRESENT;
92 ret = of_property_read_u32(np, "fsl,pull-up", &val); 92 ret = of_property_read_u32(np, "fsl,pull-up", &val);
93 if (!ret) 93 if (!ret)
94 config |= val << PULL_SHIFT | PULL_PRESENT; 94 config |= val << PULL_SHIFT | PULL_PRESENT;
95 95
96 /* Check for group node which has both mux and config settings */ 96 /* Check for group node which has both mux and config settings */
97 if (!purecfg && config) 97 if (!purecfg && config)
98 new_num = 2; 98 new_num = 2;
99 99
100 new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL); 100 new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
101 if (!new_map) 101 if (!new_map)
102 return -ENOMEM; 102 return -ENOMEM;
103 103
104 if (!purecfg) { 104 if (!purecfg) {
105 new_map[i].type = PIN_MAP_TYPE_MUX_GROUP; 105 new_map[i].type = PIN_MAP_TYPE_MUX_GROUP;
106 new_map[i].data.mux.function = np->name; 106 new_map[i].data.mux.function = np->name;
107 107
108 /* Compose group name */ 108 /* Compose group name */
109 group = kzalloc(length, GFP_KERNEL); 109 group = kzalloc(length, GFP_KERNEL);
110 if (!group) { 110 if (!group) {
111 ret = -ENOMEM; 111 ret = -ENOMEM;
112 goto free; 112 goto free;
113 } 113 }
114 snprintf(group, length, "%s.%d", np->name, reg); 114 snprintf(group, length, "%s.%d", np->name, reg);
115 new_map[i].data.mux.group = group; 115 new_map[i].data.mux.group = group;
116 i++; 116 i++;
117 } 117 }
118 118
119 if (config) { 119 if (config) {
120 pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL); 120 pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
121 if (!pconfig) { 121 if (!pconfig) {
122 ret = -ENOMEM; 122 ret = -ENOMEM;
123 goto free_group; 123 goto free_group;
124 } 124 }
125 125
126 new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 126 new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
127 new_map[i].data.configs.group_or_pin = purecfg ? np->name : 127 new_map[i].data.configs.group_or_pin = purecfg ? np->name :
128 group; 128 group;
129 new_map[i].data.configs.configs = pconfig; 129 new_map[i].data.configs.configs = pconfig;
130 new_map[i].data.configs.num_configs = 1; 130 new_map[i].data.configs.num_configs = 1;
131 } 131 }
132 132
133 *map = new_map; 133 *map = new_map;
134 *num_maps = new_num; 134 *num_maps = new_num;
135 135
136 return 0; 136 return 0;
137 137
138 free_group: 138 free_group:
139 if (!purecfg) 139 if (!purecfg)
140 kfree(group); 140 kfree(group);
141 free: 141 free:
142 kfree(new_map); 142 kfree(new_map);
143 return ret; 143 return ret;
144 } 144 }
145 145
146 static void mxs_dt_free_map(struct pinctrl_dev *pctldev, 146 static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
147 struct pinctrl_map *map, unsigned num_maps) 147 struct pinctrl_map *map, unsigned num_maps)
148 { 148 {
149 int i; 149 int i;
150 150
151 for (i = 0; i < num_maps; i++) { 151 for (i = 0; i < num_maps; i++) {
152 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) 152 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
153 kfree(map[i].data.mux.group); 153 kfree(map[i].data.mux.group);
154 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) 154 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
155 kfree(map[i].data.configs.configs); 155 kfree(map[i].data.configs.configs);
156 } 156 }
157 157
158 kfree(map); 158 kfree(map);
159 } 159 }
160 160
161 static struct pinctrl_ops mxs_pinctrl_ops = { 161 static struct pinctrl_ops mxs_pinctrl_ops = {
162 .get_groups_count = mxs_get_groups_count, 162 .get_groups_count = mxs_get_groups_count,
163 .get_group_name = mxs_get_group_name, 163 .get_group_name = mxs_get_group_name,
164 .get_group_pins = mxs_get_group_pins, 164 .get_group_pins = mxs_get_group_pins,
165 .pin_dbg_show = mxs_pin_dbg_show, 165 .pin_dbg_show = mxs_pin_dbg_show,
166 .dt_node_to_map = mxs_dt_node_to_map, 166 .dt_node_to_map = mxs_dt_node_to_map,
167 .dt_free_map = mxs_dt_free_map, 167 .dt_free_map = mxs_dt_free_map,
168 }; 168 };
169 169
170 static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) 170 static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
171 { 171 {
172 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); 172 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
173 173
174 return d->soc->nfunctions; 174 return d->soc->nfunctions;
175 } 175 }
176 176
177 static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 177 static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
178 unsigned function) 178 unsigned function)
179 { 179 {
180 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); 180 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
181 181
182 return d->soc->functions[function].name; 182 return d->soc->functions[function].name;
183 } 183 }
184 184
185 static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, 185 static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
186 unsigned group, 186 unsigned group,
187 const char * const **groups, 187 const char * const **groups,
188 unsigned * const num_groups) 188 unsigned * const num_groups)
189 { 189 {
190 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); 190 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
191 191
192 *groups = d->soc->functions[group].groups; 192 *groups = d->soc->functions[group].groups;
193 *num_groups = d->soc->functions[group].ngroups; 193 *num_groups = d->soc->functions[group].ngroups;
194 194
195 return 0; 195 return 0;
196 } 196 }
197 197
198 static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector, 198 static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
199 unsigned group) 199 unsigned group)
200 { 200 {
201 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); 201 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
202 struct mxs_group *g = &d->soc->groups[group]; 202 struct mxs_group *g = &d->soc->groups[group];
203 void __iomem *reg; 203 void __iomem *reg;
204 u8 bank, shift; 204 u8 bank, shift;
205 u16 pin; 205 u16 pin;
206 int i; 206 int i;
207 207
208 for (i = 0; i < g->npins; i++) { 208 for (i = 0; i < g->npins; i++) {
209 bank = PINID_TO_BANK(g->pins[i]); 209 bank = PINID_TO_BANK(g->pins[i]);
210 pin = PINID_TO_PIN(g->pins[i]); 210 pin = PINID_TO_PIN(g->pins[i]);
211 reg = d->base + d->soc->regs->muxsel; 211 reg = d->base + d->soc->regs->muxsel;
212 reg += bank * 0x20 + pin / 16 * 0x10; 212 reg += bank * 0x20 + pin / 16 * 0x10;
213 shift = pin % 16 * 2; 213 shift = pin % 16 * 2;
214 214
215 writel(0x3 << shift, reg + CLR); 215 writel(0x3 << shift, reg + CLR);
216 writel(g->muxsel[i] << shift, reg + SET); 216 writel(g->muxsel[i] << shift, reg + SET);
217 } 217 }
218 218
219 return 0; 219 return 0;
220 } 220 }
221 221
222 static struct pinmux_ops mxs_pinmux_ops = { 222 static struct pinmux_ops mxs_pinmux_ops = {
223 .get_functions_count = mxs_pinctrl_get_funcs_count, 223 .get_functions_count = mxs_pinctrl_get_funcs_count,
224 .get_function_name = mxs_pinctrl_get_func_name, 224 .get_function_name = mxs_pinctrl_get_func_name,
225 .get_function_groups = mxs_pinctrl_get_func_groups, 225 .get_function_groups = mxs_pinctrl_get_func_groups,
226 .enable = mxs_pinctrl_enable, 226 .enable = mxs_pinctrl_enable,
227 }; 227 };
228 228
229 static int mxs_pinconf_get(struct pinctrl_dev *pctldev, 229 static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
230 unsigned pin, unsigned long *config) 230 unsigned pin, unsigned long *config)
231 { 231 {
232 return -ENOTSUPP; 232 return -ENOTSUPP;
233 } 233 }
234 234
235 static int mxs_pinconf_set(struct pinctrl_dev *pctldev, 235 static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
236 unsigned pin, unsigned long config) 236 unsigned pin, unsigned long config)
237 { 237 {
238 return -ENOTSUPP; 238 return -ENOTSUPP;
239 } 239 }
240 240
241 static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev, 241 static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
242 unsigned group, unsigned long *config) 242 unsigned group, unsigned long *config)
243 { 243 {
244 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); 244 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
245 245
246 *config = d->soc->groups[group].config; 246 *config = d->soc->groups[group].config;
247 247
248 return 0; 248 return 0;
249 } 249 }
250 250
251 static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev, 251 static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
252 unsigned group, unsigned long config) 252 unsigned group, unsigned long config)
253 { 253 {
254 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); 254 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
255 struct mxs_group *g = &d->soc->groups[group]; 255 struct mxs_group *g = &d->soc->groups[group];
256 void __iomem *reg; 256 void __iomem *reg;
257 u8 ma, vol, pull, bank, shift; 257 u8 ma, vol, pull, bank, shift;
258 u16 pin; 258 u16 pin;
259 int i; 259 int i;
260 260
261 ma = CONFIG_TO_MA(config); 261 ma = CONFIG_TO_MA(config);
262 vol = CONFIG_TO_VOL(config); 262 vol = CONFIG_TO_VOL(config);
263 pull = CONFIG_TO_PULL(config); 263 pull = CONFIG_TO_PULL(config);
264 264
265 for (i = 0; i < g->npins; i++) { 265 for (i = 0; i < g->npins; i++) {
266 bank = PINID_TO_BANK(g->pins[i]); 266 bank = PINID_TO_BANK(g->pins[i]);
267 pin = PINID_TO_PIN(g->pins[i]); 267 pin = PINID_TO_PIN(g->pins[i]);
268 268
269 /* drive */ 269 /* drive */
270 reg = d->base + d->soc->regs->drive; 270 reg = d->base + d->soc->regs->drive;
271 reg += bank * 0x40 + pin / 8 * 0x10; 271 reg += bank * 0x40 + pin / 8 * 0x10;
272 272
273 /* mA */ 273 /* mA */
274 if (config & MA_PRESENT) { 274 if (config & MA_PRESENT) {
275 shift = pin % 8 * 4; 275 shift = pin % 8 * 4;
276 writel(0x3 << shift, reg + CLR); 276 writel(0x3 << shift, reg + CLR);
277 writel(ma << shift, reg + SET); 277 writel(ma << shift, reg + SET);
278 } 278 }
279 279
280 /* vol */ 280 /* vol */
281 if (config & VOL_PRESENT) { 281 if (config & VOL_PRESENT) {
282 shift = pin % 8 * 4 + 2; 282 shift = pin % 8 * 4 + 2;
283 if (vol) 283 if (vol)
284 writel(1 << shift, reg + SET); 284 writel(1 << shift, reg + SET);
285 else 285 else
286 writel(1 << shift, reg + CLR); 286 writel(1 << shift, reg + CLR);
287 } 287 }
288 288
289 /* pull */ 289 /* pull */
290 if (config & PULL_PRESENT) { 290 if (config & PULL_PRESENT) {
291 reg = d->base + d->soc->regs->pull; 291 reg = d->base + d->soc->regs->pull;
292 reg += bank * 0x10; 292 reg += bank * 0x10;
293 shift = pin; 293 shift = pin;
294 if (pull) 294 if (pull)
295 writel(1 << shift, reg + SET); 295 writel(1 << shift, reg + SET);
296 else 296 else
297 writel(1 << shift, reg + CLR); 297 writel(1 << shift, reg + CLR);
298 } 298 }
299 } 299 }
300 300
301 /* cache the config value for mxs_pinconf_group_get() */ 301 /* cache the config value for mxs_pinconf_group_get() */
302 g->config = config; 302 g->config = config;
303 303
304 return 0; 304 return 0;
305 } 305 }
306 306
307 static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev, 307 static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
308 struct seq_file *s, unsigned pin) 308 struct seq_file *s, unsigned pin)
309 { 309 {
310 /* Not support */ 310 /* Not support */
311 } 311 }
312 312
313 static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 313 static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
314 struct seq_file *s, unsigned group) 314 struct seq_file *s, unsigned group)
315 { 315 {
316 unsigned long config; 316 unsigned long config;
317 317
318 if (!mxs_pinconf_group_get(pctldev, group, &config)) 318 if (!mxs_pinconf_group_get(pctldev, group, &config))
319 seq_printf(s, "0x%lx", config); 319 seq_printf(s, "0x%lx", config);
320 } 320 }
321 321
322 struct pinconf_ops mxs_pinconf_ops = { 322 struct pinconf_ops mxs_pinconf_ops = {
323 .pin_config_get = mxs_pinconf_get, 323 .pin_config_get = mxs_pinconf_get,
324 .pin_config_set = mxs_pinconf_set, 324 .pin_config_set = mxs_pinconf_set,
325 .pin_config_group_get = mxs_pinconf_group_get, 325 .pin_config_group_get = mxs_pinconf_group_get,
326 .pin_config_group_set = mxs_pinconf_group_set, 326 .pin_config_group_set = mxs_pinconf_group_set,
327 .pin_config_dbg_show = mxs_pinconf_dbg_show, 327 .pin_config_dbg_show = mxs_pinconf_dbg_show,
328 .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show, 328 .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
329 }; 329 };
330 330
331 static struct pinctrl_desc mxs_pinctrl_desc = { 331 static struct pinctrl_desc mxs_pinctrl_desc = {
332 .pctlops = &mxs_pinctrl_ops, 332 .pctlops = &mxs_pinctrl_ops,
333 .pmxops = &mxs_pinmux_ops, 333 .pmxops = &mxs_pinmux_ops,
334 .confops = &mxs_pinconf_ops, 334 .confops = &mxs_pinconf_ops,
335 .owner = THIS_MODULE, 335 .owner = THIS_MODULE,
336 }; 336 };
337 337
338 static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev, 338 static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev,
339 struct device_node *np, int idx, 339 struct device_node *np, int idx,
340 const char **out_name) 340 const char **out_name)
341 { 341 {
342 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); 342 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
343 struct mxs_group *g = &d->soc->groups[idx]; 343 struct mxs_group *g = &d->soc->groups[idx];
344 struct property *prop; 344 struct property *prop;
345 const char *propname = "fsl,pinmux-ids"; 345 const char *propname = "fsl,pinmux-ids";
346 char *group; 346 char *group;
347 int length = strlen(np->name) + SUFFIX_LEN; 347 int length = strlen(np->name) + SUFFIX_LEN;
348 int i; 348 int i;
349 u32 val; 349 u32 val;
350 350
351 group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL); 351 group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
352 if (!group) 352 if (!group)
353 return -ENOMEM; 353 return -ENOMEM;
354 if (of_property_read_u32(np, "reg", &val)) 354 if (of_property_read_u32(np, "reg", &val))
355 snprintf(group, length, "%s", np->name); 355 snprintf(group, length, "%s", np->name);
356 else 356 else
357 snprintf(group, length, "%s.%d", np->name, val); 357 snprintf(group, length, "%s.%d", np->name, val);
358 g->name = group; 358 g->name = group;
359 359
360 prop = of_find_property(np, propname, &length); 360 prop = of_find_property(np, propname, &length);
361 if (!prop) 361 if (!prop)
362 return -EINVAL; 362 return -EINVAL;
363 g->npins = length / sizeof(u32); 363 g->npins = length / sizeof(u32);
364 364
365 g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins), 365 g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
366 GFP_KERNEL); 366 GFP_KERNEL);
367 if (!g->pins) 367 if (!g->pins)
368 return -ENOMEM; 368 return -ENOMEM;
369 369
370 g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel), 370 g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
371 GFP_KERNEL); 371 GFP_KERNEL);
372 if (!g->muxsel) 372 if (!g->muxsel)
373 return -ENOMEM; 373 return -ENOMEM;
374 374
375 of_property_read_u32_array(np, propname, g->pins, g->npins); 375 of_property_read_u32_array(np, propname, g->pins, g->npins);
376 for (i = 0; i < g->npins; i++) { 376 for (i = 0; i < g->npins; i++) {
377 g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]); 377 g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
378 g->pins[i] = MUXID_TO_PINID(g->pins[i]); 378 g->pins[i] = MUXID_TO_PINID(g->pins[i]);
379 } 379 }
380 380
381 if (out_name) 381 if (out_name)
382 *out_name = g->name; 382 *out_name = g->name;
383 383
384 return 0; 384 return 0;
385 } 385 }
386 386
387 static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev, 387 static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev,
388 struct mxs_pinctrl_data *d) 388 struct mxs_pinctrl_data *d)
389 { 389 {
390 struct mxs_pinctrl_soc_data *soc = d->soc; 390 struct mxs_pinctrl_soc_data *soc = d->soc;
391 struct device_node *np = pdev->dev.of_node; 391 struct device_node *np = pdev->dev.of_node;
392 struct device_node *child; 392 struct device_node *child;
393 struct mxs_function *f; 393 struct mxs_function *f;
394 const char *gpio_compat = "fsl,mxs-gpio"; 394 const char *gpio_compat = "fsl,mxs-gpio";
395 const char *fn, *fnull = ""; 395 const char *fn, *fnull = "";
396 int i = 0, idxf = 0, idxg = 0; 396 int i = 0, idxf = 0, idxg = 0;
397 int ret; 397 int ret;
398 u32 val; 398 u32 val;
399 399
400 child = of_get_next_child(np, NULL); 400 child = of_get_next_child(np, NULL);
401 if (!child) { 401 if (!child) {
402 dev_err(&pdev->dev, "no group is defined\n"); 402 dev_err(&pdev->dev, "no group is defined\n");
403 return -ENOENT; 403 return -ENOENT;
404 } 404 }
405 405
406 /* Count total functions and groups */ 406 /* Count total functions and groups */
407 fn = fnull; 407 fn = fnull;
408 for_each_child_of_node(np, child) { 408 for_each_child_of_node(np, child) {
409 if (of_device_is_compatible(child, gpio_compat)) 409 if (of_device_is_compatible(child, gpio_compat))
410 continue; 410 continue;
411 soc->ngroups++; 411 soc->ngroups++;
412 /* Skip pure pinconf node */ 412 /* Skip pure pinconf node */
413 if (of_property_read_u32(child, "reg", &val)) 413 if (of_property_read_u32(child, "reg", &val))
414 continue; 414 continue;
415 if (strcmp(fn, child->name)) { 415 if (strcmp(fn, child->name)) {
416 fn = child->name; 416 fn = child->name;
417 soc->nfunctions++; 417 soc->nfunctions++;
418 } 418 }
419 } 419 }
420 420
421 soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions * 421 soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
422 sizeof(*soc->functions), GFP_KERNEL); 422 sizeof(*soc->functions), GFP_KERNEL);
423 if (!soc->functions) 423 if (!soc->functions)
424 return -ENOMEM; 424 return -ENOMEM;
425 425
426 soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups * 426 soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
427 sizeof(*soc->groups), GFP_KERNEL); 427 sizeof(*soc->groups), GFP_KERNEL);
428 if (!soc->groups) 428 if (!soc->groups)
429 return -ENOMEM; 429 return -ENOMEM;
430 430
431 /* Count groups for each function */ 431 /* Count groups for each function */
432 fn = fnull; 432 fn = fnull;
433 f = &soc->functions[idxf]; 433 f = &soc->functions[idxf];
434 for_each_child_of_node(np, child) { 434 for_each_child_of_node(np, child) {
435 if (of_device_is_compatible(child, gpio_compat)) 435 if (of_device_is_compatible(child, gpio_compat))
436 continue; 436 continue;
437 if (of_property_read_u32(child, "reg", &val)) 437 if (of_property_read_u32(child, "reg", &val))
438 continue; 438 continue;
439 if (strcmp(fn, child->name)) { 439 if (strcmp(fn, child->name)) {
440 f = &soc->functions[idxf++]; 440 f = &soc->functions[idxf++];
441 f->name = fn = child->name; 441 f->name = fn = child->name;
442 } 442 }
443 f->ngroups++; 443 f->ngroups++;
444 }; 444 };
445 445
446 /* Get groups for each function */ 446 /* Get groups for each function */
447 idxf = 0; 447 idxf = 0;
448 fn = fnull; 448 fn = fnull;
449 for_each_child_of_node(np, child) { 449 for_each_child_of_node(np, child) {
450 if (of_device_is_compatible(child, gpio_compat)) 450 if (of_device_is_compatible(child, gpio_compat))
451 continue; 451 continue;
452 if (of_property_read_u32(child, "reg", &val)) { 452 if (of_property_read_u32(child, "reg", &val)) {
453 ret = mxs_pinctrl_parse_group(pdev, child, 453 ret = mxs_pinctrl_parse_group(pdev, child,
454 idxg++, NULL); 454 idxg++, NULL);
455 if (ret) 455 if (ret)
456 return ret; 456 return ret;
457 continue; 457 continue;
458 } 458 }
459 459
460 if (strcmp(fn, child->name)) { 460 if (strcmp(fn, child->name)) {
461 f = &soc->functions[idxf++]; 461 f = &soc->functions[idxf++];
462 f->groups = devm_kzalloc(&pdev->dev, f->ngroups * 462 f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
463 sizeof(*f->groups), 463 sizeof(*f->groups),
464 GFP_KERNEL); 464 GFP_KERNEL);
465 if (!f->groups) 465 if (!f->groups)
466 return -ENOMEM; 466 return -ENOMEM;
467 fn = child->name; 467 fn = child->name;
468 i = 0; 468 i = 0;
469 } 469 }
470 ret = mxs_pinctrl_parse_group(pdev, child, idxg++, 470 ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
471 &f->groups[i++]); 471 &f->groups[i++]);
472 if (ret) 472 if (ret)
473 return ret; 473 return ret;
474 } 474 }
475 475
476 return 0; 476 return 0;
477 } 477 }
478 478
479 int __devinit mxs_pinctrl_probe(struct platform_device *pdev, 479 int __devinit mxs_pinctrl_probe(struct platform_device *pdev,
480 struct mxs_pinctrl_soc_data *soc) 480 struct mxs_pinctrl_soc_data *soc)
481 { 481 {
482 struct device_node *np = pdev->dev.of_node; 482 struct device_node *np = pdev->dev.of_node;
483 struct mxs_pinctrl_data *d; 483 struct mxs_pinctrl_data *d;
484 int ret; 484 int ret;
485 485
486 d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL); 486 d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
487 if (!d) 487 if (!d)
488 return -ENOMEM; 488 return -ENOMEM;
489 489
490 d->dev = &pdev->dev; 490 d->dev = &pdev->dev;
491 d->soc = soc; 491 d->soc = soc;
492 492
493 d->base = of_iomap(np, 0); 493 d->base = of_iomap(np, 0);
494 if (!d->base) 494 if (!d->base)
495 return -EADDRNOTAVAIL; 495 return -EADDRNOTAVAIL;
496 496
497 mxs_pinctrl_desc.pins = d->soc->pins; 497 mxs_pinctrl_desc.pins = d->soc->pins;
498 mxs_pinctrl_desc.npins = d->soc->npins; 498 mxs_pinctrl_desc.npins = d->soc->npins;
499 mxs_pinctrl_desc.name = dev_name(&pdev->dev); 499 mxs_pinctrl_desc.name = dev_name(&pdev->dev);
500 500
501 platform_set_drvdata(pdev, d); 501 platform_set_drvdata(pdev, d);
502 502
503 ret = mxs_pinctrl_probe_dt(pdev, d); 503 ret = mxs_pinctrl_probe_dt(pdev, d);
504 if (ret) { 504 if (ret) {
505 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 505 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
506 goto err; 506 goto err;
507 } 507 }
508 508
509 d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d); 509 d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
510 if (!d->pctl) { 510 if (!d->pctl) {
511 dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n"); 511 dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
512 ret = -EINVAL; 512 ret = -EINVAL;
513 goto err; 513 goto err;
514 } 514 }
515 515
516 return 0; 516 return 0;
517 517
518 err: 518 err:
519 platform_set_drvdata(pdev, NULL); 519 platform_set_drvdata(pdev, NULL);
520 iounmap(d->base); 520 iounmap(d->base);
521 return ret; 521 return ret;
522 } 522 }
523 EXPORT_SYMBOL_GPL(mxs_pinctrl_probe); 523 EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
524 524
525 int __devexit mxs_pinctrl_remove(struct platform_device *pdev) 525 int mxs_pinctrl_remove(struct platform_device *pdev)
526 { 526 {
527 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); 527 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
528 528
529 platform_set_drvdata(pdev, NULL); 529 platform_set_drvdata(pdev, NULL);
530 pinctrl_unregister(d->pctl); 530 pinctrl_unregister(d->pctl);
531 iounmap(d->base); 531 iounmap(d->base);
532 532
533 return 0; 533 return 0;
534 } 534 }
535 EXPORT_SYMBOL_GPL(mxs_pinctrl_remove); 535 EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
536 536
drivers/pinctrl/pinctrl-pxa168.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * linux/drivers/pinctrl/pinmux-pxa168.c 2 * linux/drivers/pinctrl/pinmux-pxa168.c
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * publishhed by the Free Software Foundation. 6 * publishhed by the Free Software Foundation.
7 * 7 *
8 * Copyright (C) 2011, Marvell Technology Group Ltd. 8 * Copyright (C) 2011, Marvell Technology Group Ltd.
9 * 9 *
10 * Author: Haojian Zhuang <haojian.zhuang@marvell.com> 10 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
11 * 11 *
12 */ 12 */
13 13
14 #include <linux/device.h> 14 #include <linux/device.h>
15 #include <linux/module.h> 15 #include <linux/module.h>
16 #include <linux/io.h> 16 #include <linux/io.h>
17 #include <linux/platform_device.h> 17 #include <linux/platform_device.h>
18 #include "pinctrl-pxa3xx.h" 18 #include "pinctrl-pxa3xx.h"
19 19
20 #define PXA168_DS_MASK 0x1800 20 #define PXA168_DS_MASK 0x1800
21 #define PXA168_DS_SHIFT 11 21 #define PXA168_DS_SHIFT 11
22 #define PXA168_SLEEP_MASK 0x38 22 #define PXA168_SLEEP_MASK 0x38
23 #define PXA168_SLEEP_SELECT (1 << 9) 23 #define PXA168_SLEEP_SELECT (1 << 9)
24 #define PXA168_SLEEP_DATA (1 << 8) 24 #define PXA168_SLEEP_DATA (1 << 8)
25 #define PXA168_SLEEP_DIR (1 << 7) 25 #define PXA168_SLEEP_DIR (1 << 7)
26 26
27 #define MFPR_168(a, r, f0, f1, f2, f3, f4, f5, f6, f7) \ 27 #define MFPR_168(a, r, f0, f1, f2, f3, f4, f5, f6, f7) \
28 { \ 28 { \
29 .name = #a, \ 29 .name = #a, \
30 .pin = a, \ 30 .pin = a, \
31 .mfpr = r, \ 31 .mfpr = r, \
32 .func = { \ 32 .func = { \
33 PXA168_MUX_##f0, \ 33 PXA168_MUX_##f0, \
34 PXA168_MUX_##f1, \ 34 PXA168_MUX_##f1, \
35 PXA168_MUX_##f2, \ 35 PXA168_MUX_##f2, \
36 PXA168_MUX_##f3, \ 36 PXA168_MUX_##f3, \
37 PXA168_MUX_##f4, \ 37 PXA168_MUX_##f4, \
38 PXA168_MUX_##f5, \ 38 PXA168_MUX_##f5, \
39 PXA168_MUX_##f6, \ 39 PXA168_MUX_##f6, \
40 PXA168_MUX_##f7, \ 40 PXA168_MUX_##f7, \
41 }, \ 41 }, \
42 } 42 }
43 43
44 #define GRP_168(a, m, p) \ 44 #define GRP_168(a, m, p) \
45 { .name = a, .mux = PXA168_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), } 45 { .name = a, .mux = PXA168_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
46 46
47 /* 131 pins */ 47 /* 131 pins */
48 enum pxa168_pin_list { 48 enum pxa168_pin_list {
49 /* 0~122: GPIO0~GPIO122 */ 49 /* 0~122: GPIO0~GPIO122 */
50 PWR_SCL = 123, 50 PWR_SCL = 123,
51 PWR_SDA, 51 PWR_SDA,
52 TDI, 52 TDI,
53 TMS, 53 TMS,
54 TCK, 54 TCK,
55 TDO, 55 TDO,
56 TRST, 56 TRST,
57 WAKEUP = 130, 57 WAKEUP = 130,
58 }; 58 };
59 59
60 enum pxa168_mux { 60 enum pxa168_mux {
61 /* PXA3xx_MUX_GPIO = 0 (predefined in pinctrl-pxa3xx.h) */ 61 /* PXA3xx_MUX_GPIO = 0 (predefined in pinctrl-pxa3xx.h) */
62 PXA168_MUX_GPIO = 0, 62 PXA168_MUX_GPIO = 0,
63 PXA168_MUX_DFIO, 63 PXA168_MUX_DFIO,
64 PXA168_MUX_NAND, 64 PXA168_MUX_NAND,
65 PXA168_MUX_SMC, 65 PXA168_MUX_SMC,
66 PXA168_MUX_SMC_CS0, 66 PXA168_MUX_SMC_CS0,
67 PXA168_MUX_SMC_CS1, 67 PXA168_MUX_SMC_CS1,
68 PXA168_MUX_SMC_INT, 68 PXA168_MUX_SMC_INT,
69 PXA168_MUX_SMC_RDY, 69 PXA168_MUX_SMC_RDY,
70 PXA168_MUX_MMC1, 70 PXA168_MUX_MMC1,
71 PXA168_MUX_MMC2, 71 PXA168_MUX_MMC2,
72 PXA168_MUX_MMC2_CMD, 72 PXA168_MUX_MMC2_CMD,
73 PXA168_MUX_MMC2_CLK, 73 PXA168_MUX_MMC2_CLK,
74 PXA168_MUX_MMC3, 74 PXA168_MUX_MMC3,
75 PXA168_MUX_MMC3_CMD, 75 PXA168_MUX_MMC3_CMD,
76 PXA168_MUX_MMC3_CLK, 76 PXA168_MUX_MMC3_CLK,
77 PXA168_MUX_MMC4, 77 PXA168_MUX_MMC4,
78 PXA168_MUX_MSP, 78 PXA168_MUX_MSP,
79 PXA168_MUX_MSP_DAT3, 79 PXA168_MUX_MSP_DAT3,
80 PXA168_MUX_MSP_INS, 80 PXA168_MUX_MSP_INS,
81 PXA168_MUX_I2C, 81 PXA168_MUX_I2C,
82 PXA168_MUX_PWRI2C, 82 PXA168_MUX_PWRI2C,
83 PXA168_MUX_AC97, 83 PXA168_MUX_AC97,
84 PXA168_MUX_AC97_SYSCLK, 84 PXA168_MUX_AC97_SYSCLK,
85 PXA168_MUX_PWM, 85 PXA168_MUX_PWM,
86 PXA168_MUX_PWM1, 86 PXA168_MUX_PWM1,
87 PXA168_MUX_XD, 87 PXA168_MUX_XD,
88 PXA168_MUX_XP, 88 PXA168_MUX_XP,
89 PXA168_MUX_LCD, 89 PXA168_MUX_LCD,
90 PXA168_MUX_CCIC, 90 PXA168_MUX_CCIC,
91 PXA168_MUX_CF, 91 PXA168_MUX_CF,
92 PXA168_MUX_CF_RDY, 92 PXA168_MUX_CF_RDY,
93 PXA168_MUX_CF_nINPACK, 93 PXA168_MUX_CF_nINPACK,
94 PXA168_MUX_CF_nWAIT, 94 PXA168_MUX_CF_nWAIT,
95 PXA168_MUX_KP_MKOUT, 95 PXA168_MUX_KP_MKOUT,
96 PXA168_MUX_KP_MKIN, 96 PXA168_MUX_KP_MKIN,
97 PXA168_MUX_KP_DK, 97 PXA168_MUX_KP_DK,
98 PXA168_MUX_ETH, 98 PXA168_MUX_ETH,
99 PXA168_MUX_ETH_TX, 99 PXA168_MUX_ETH_TX,
100 PXA168_MUX_ETH_RX, 100 PXA168_MUX_ETH_RX,
101 PXA168_MUX_ONE_WIRE, 101 PXA168_MUX_ONE_WIRE,
102 PXA168_MUX_UART1, 102 PXA168_MUX_UART1,
103 PXA168_MUX_UART1_TX, 103 PXA168_MUX_UART1_TX,
104 PXA168_MUX_UART1_CTS, 104 PXA168_MUX_UART1_CTS,
105 PXA168_MUX_UART1_nRI, 105 PXA168_MUX_UART1_nRI,
106 PXA168_MUX_UART1_DTR, 106 PXA168_MUX_UART1_DTR,
107 PXA168_MUX_UART2, 107 PXA168_MUX_UART2,
108 PXA168_MUX_UART2_TX, 108 PXA168_MUX_UART2_TX,
109 PXA168_MUX_UART3, 109 PXA168_MUX_UART3,
110 PXA168_MUX_UART3_TX, 110 PXA168_MUX_UART3_TX,
111 PXA168_MUX_UART3_CTS, 111 PXA168_MUX_UART3_CTS,
112 PXA168_MUX_SSP1, 112 PXA168_MUX_SSP1,
113 PXA168_MUX_SSP1_TX, 113 PXA168_MUX_SSP1_TX,
114 PXA168_MUX_SSP2, 114 PXA168_MUX_SSP2,
115 PXA168_MUX_SSP2_TX, 115 PXA168_MUX_SSP2_TX,
116 PXA168_MUX_SSP3, 116 PXA168_MUX_SSP3,
117 PXA168_MUX_SSP3_TX, 117 PXA168_MUX_SSP3_TX,
118 PXA168_MUX_SSP4, 118 PXA168_MUX_SSP4,
119 PXA168_MUX_SSP4_TX, 119 PXA168_MUX_SSP4_TX,
120 PXA168_MUX_SSP5, 120 PXA168_MUX_SSP5,
121 PXA168_MUX_SSP5_TX, 121 PXA168_MUX_SSP5_TX,
122 PXA168_MUX_USB, 122 PXA168_MUX_USB,
123 PXA168_MUX_JTAG, 123 PXA168_MUX_JTAG,
124 PXA168_MUX_RESET, 124 PXA168_MUX_RESET,
125 PXA168_MUX_WAKEUP, 125 PXA168_MUX_WAKEUP,
126 PXA168_MUX_EXT_32K_IN, 126 PXA168_MUX_EXT_32K_IN,
127 PXA168_MUX_NONE = 0xffff, 127 PXA168_MUX_NONE = 0xffff,
128 }; 128 };
129 129
130 static struct pinctrl_pin_desc pxa168_pads[] = { 130 static struct pinctrl_pin_desc pxa168_pads[] = {
131 PINCTRL_PIN(GPIO0, "GPIO0"), 131 PINCTRL_PIN(GPIO0, "GPIO0"),
132 PINCTRL_PIN(GPIO1, "GPIO1"), 132 PINCTRL_PIN(GPIO1, "GPIO1"),
133 PINCTRL_PIN(GPIO2, "GPIO2"), 133 PINCTRL_PIN(GPIO2, "GPIO2"),
134 PINCTRL_PIN(GPIO3, "GPIO3"), 134 PINCTRL_PIN(GPIO3, "GPIO3"),
135 PINCTRL_PIN(GPIO4, "GPIO4"), 135 PINCTRL_PIN(GPIO4, "GPIO4"),
136 PINCTRL_PIN(GPIO5, "GPIO5"), 136 PINCTRL_PIN(GPIO5, "GPIO5"),
137 PINCTRL_PIN(GPIO6, "GPIO6"), 137 PINCTRL_PIN(GPIO6, "GPIO6"),
138 PINCTRL_PIN(GPIO7, "GPIO7"), 138 PINCTRL_PIN(GPIO7, "GPIO7"),
139 PINCTRL_PIN(GPIO8, "GPIO8"), 139 PINCTRL_PIN(GPIO8, "GPIO8"),
140 PINCTRL_PIN(GPIO9, "GPIO9"), 140 PINCTRL_PIN(GPIO9, "GPIO9"),
141 PINCTRL_PIN(GPIO10, "GPIO10"), 141 PINCTRL_PIN(GPIO10, "GPIO10"),
142 PINCTRL_PIN(GPIO11, "GPIO11"), 142 PINCTRL_PIN(GPIO11, "GPIO11"),
143 PINCTRL_PIN(GPIO12, "GPIO12"), 143 PINCTRL_PIN(GPIO12, "GPIO12"),
144 PINCTRL_PIN(GPIO13, "GPIO13"), 144 PINCTRL_PIN(GPIO13, "GPIO13"),
145 PINCTRL_PIN(GPIO14, "GPIO14"), 145 PINCTRL_PIN(GPIO14, "GPIO14"),
146 PINCTRL_PIN(GPIO15, "GPIO15"), 146 PINCTRL_PIN(GPIO15, "GPIO15"),
147 PINCTRL_PIN(GPIO16, "GPIO16"), 147 PINCTRL_PIN(GPIO16, "GPIO16"),
148 PINCTRL_PIN(GPIO17, "GPIO17"), 148 PINCTRL_PIN(GPIO17, "GPIO17"),
149 PINCTRL_PIN(GPIO18, "GPIO18"), 149 PINCTRL_PIN(GPIO18, "GPIO18"),
150 PINCTRL_PIN(GPIO19, "GPIO19"), 150 PINCTRL_PIN(GPIO19, "GPIO19"),
151 PINCTRL_PIN(GPIO20, "GPIO20"), 151 PINCTRL_PIN(GPIO20, "GPIO20"),
152 PINCTRL_PIN(GPIO21, "GPIO21"), 152 PINCTRL_PIN(GPIO21, "GPIO21"),
153 PINCTRL_PIN(GPIO22, "GPIO22"), 153 PINCTRL_PIN(GPIO22, "GPIO22"),
154 PINCTRL_PIN(GPIO23, "GPIO23"), 154 PINCTRL_PIN(GPIO23, "GPIO23"),
155 PINCTRL_PIN(GPIO24, "GPIO24"), 155 PINCTRL_PIN(GPIO24, "GPIO24"),
156 PINCTRL_PIN(GPIO25, "GPIO25"), 156 PINCTRL_PIN(GPIO25, "GPIO25"),
157 PINCTRL_PIN(GPIO26, "GPIO26"), 157 PINCTRL_PIN(GPIO26, "GPIO26"),
158 PINCTRL_PIN(GPIO27, "GPIO27"), 158 PINCTRL_PIN(GPIO27, "GPIO27"),
159 PINCTRL_PIN(GPIO28, "GPIO28"), 159 PINCTRL_PIN(GPIO28, "GPIO28"),
160 PINCTRL_PIN(GPIO29, "GPIO29"), 160 PINCTRL_PIN(GPIO29, "GPIO29"),
161 PINCTRL_PIN(GPIO30, "GPIO30"), 161 PINCTRL_PIN(GPIO30, "GPIO30"),
162 PINCTRL_PIN(GPIO31, "GPIO31"), 162 PINCTRL_PIN(GPIO31, "GPIO31"),
163 PINCTRL_PIN(GPIO32, "GPIO32"), 163 PINCTRL_PIN(GPIO32, "GPIO32"),
164 PINCTRL_PIN(GPIO33, "GPIO33"), 164 PINCTRL_PIN(GPIO33, "GPIO33"),
165 PINCTRL_PIN(GPIO34, "GPIO34"), 165 PINCTRL_PIN(GPIO34, "GPIO34"),
166 PINCTRL_PIN(GPIO35, "GPIO35"), 166 PINCTRL_PIN(GPIO35, "GPIO35"),
167 PINCTRL_PIN(GPIO36, "GPIO36"), 167 PINCTRL_PIN(GPIO36, "GPIO36"),
168 PINCTRL_PIN(GPIO37, "GPIO37"), 168 PINCTRL_PIN(GPIO37, "GPIO37"),
169 PINCTRL_PIN(GPIO38, "GPIO38"), 169 PINCTRL_PIN(GPIO38, "GPIO38"),
170 PINCTRL_PIN(GPIO39, "GPIO39"), 170 PINCTRL_PIN(GPIO39, "GPIO39"),
171 PINCTRL_PIN(GPIO40, "GPIO40"), 171 PINCTRL_PIN(GPIO40, "GPIO40"),
172 PINCTRL_PIN(GPIO41, "GPIO41"), 172 PINCTRL_PIN(GPIO41, "GPIO41"),
173 PINCTRL_PIN(GPIO42, "GPIO42"), 173 PINCTRL_PIN(GPIO42, "GPIO42"),
174 PINCTRL_PIN(GPIO43, "GPIO43"), 174 PINCTRL_PIN(GPIO43, "GPIO43"),
175 PINCTRL_PIN(GPIO44, "GPIO44"), 175 PINCTRL_PIN(GPIO44, "GPIO44"),
176 PINCTRL_PIN(GPIO45, "GPIO45"), 176 PINCTRL_PIN(GPIO45, "GPIO45"),
177 PINCTRL_PIN(GPIO46, "GPIO46"), 177 PINCTRL_PIN(GPIO46, "GPIO46"),
178 PINCTRL_PIN(GPIO47, "GPIO47"), 178 PINCTRL_PIN(GPIO47, "GPIO47"),
179 PINCTRL_PIN(GPIO48, "GPIO48"), 179 PINCTRL_PIN(GPIO48, "GPIO48"),
180 PINCTRL_PIN(GPIO49, "GPIO49"), 180 PINCTRL_PIN(GPIO49, "GPIO49"),
181 PINCTRL_PIN(GPIO50, "GPIO50"), 181 PINCTRL_PIN(GPIO50, "GPIO50"),
182 PINCTRL_PIN(GPIO51, "GPIO51"), 182 PINCTRL_PIN(GPIO51, "GPIO51"),
183 PINCTRL_PIN(GPIO52, "GPIO52"), 183 PINCTRL_PIN(GPIO52, "GPIO52"),
184 PINCTRL_PIN(GPIO53, "GPIO53"), 184 PINCTRL_PIN(GPIO53, "GPIO53"),
185 PINCTRL_PIN(GPIO54, "GPIO54"), 185 PINCTRL_PIN(GPIO54, "GPIO54"),
186 PINCTRL_PIN(GPIO55, "GPIO55"), 186 PINCTRL_PIN(GPIO55, "GPIO55"),
187 PINCTRL_PIN(GPIO56, "GPIO56"), 187 PINCTRL_PIN(GPIO56, "GPIO56"),
188 PINCTRL_PIN(GPIO57, "GPIO57"), 188 PINCTRL_PIN(GPIO57, "GPIO57"),
189 PINCTRL_PIN(GPIO58, "GPIO58"), 189 PINCTRL_PIN(GPIO58, "GPIO58"),
190 PINCTRL_PIN(GPIO59, "GPIO59"), 190 PINCTRL_PIN(GPIO59, "GPIO59"),
191 PINCTRL_PIN(GPIO60, "GPIO60"), 191 PINCTRL_PIN(GPIO60, "GPIO60"),
192 PINCTRL_PIN(GPIO61, "GPIO61"), 192 PINCTRL_PIN(GPIO61, "GPIO61"),
193 PINCTRL_PIN(GPIO62, "GPIO62"), 193 PINCTRL_PIN(GPIO62, "GPIO62"),
194 PINCTRL_PIN(GPIO63, "GPIO63"), 194 PINCTRL_PIN(GPIO63, "GPIO63"),
195 PINCTRL_PIN(GPIO64, "GPIO64"), 195 PINCTRL_PIN(GPIO64, "GPIO64"),
196 PINCTRL_PIN(GPIO65, "GPIO65"), 196 PINCTRL_PIN(GPIO65, "GPIO65"),
197 PINCTRL_PIN(GPIO66, "GPIO66"), 197 PINCTRL_PIN(GPIO66, "GPIO66"),
198 PINCTRL_PIN(GPIO67, "GPIO67"), 198 PINCTRL_PIN(GPIO67, "GPIO67"),
199 PINCTRL_PIN(GPIO68, "GPIO68"), 199 PINCTRL_PIN(GPIO68, "GPIO68"),
200 PINCTRL_PIN(GPIO69, "GPIO69"), 200 PINCTRL_PIN(GPIO69, "GPIO69"),
201 PINCTRL_PIN(GPIO70, "GPIO70"), 201 PINCTRL_PIN(GPIO70, "GPIO70"),
202 PINCTRL_PIN(GPIO71, "GPIO71"), 202 PINCTRL_PIN(GPIO71, "GPIO71"),
203 PINCTRL_PIN(GPIO72, "GPIO72"), 203 PINCTRL_PIN(GPIO72, "GPIO72"),
204 PINCTRL_PIN(GPIO73, "GPIO73"), 204 PINCTRL_PIN(GPIO73, "GPIO73"),
205 PINCTRL_PIN(GPIO74, "GPIO74"), 205 PINCTRL_PIN(GPIO74, "GPIO74"),
206 PINCTRL_PIN(GPIO75, "GPIO75"), 206 PINCTRL_PIN(GPIO75, "GPIO75"),
207 PINCTRL_PIN(GPIO76, "GPIO76"), 207 PINCTRL_PIN(GPIO76, "GPIO76"),
208 PINCTRL_PIN(GPIO77, "GPIO77"), 208 PINCTRL_PIN(GPIO77, "GPIO77"),
209 PINCTRL_PIN(GPIO78, "GPIO78"), 209 PINCTRL_PIN(GPIO78, "GPIO78"),
210 PINCTRL_PIN(GPIO79, "GPIO79"), 210 PINCTRL_PIN(GPIO79, "GPIO79"),
211 PINCTRL_PIN(GPIO80, "GPIO80"), 211 PINCTRL_PIN(GPIO80, "GPIO80"),
212 PINCTRL_PIN(GPIO81, "GPIO81"), 212 PINCTRL_PIN(GPIO81, "GPIO81"),
213 PINCTRL_PIN(GPIO82, "GPIO82"), 213 PINCTRL_PIN(GPIO82, "GPIO82"),
214 PINCTRL_PIN(GPIO83, "GPIO83"), 214 PINCTRL_PIN(GPIO83, "GPIO83"),
215 PINCTRL_PIN(GPIO84, "GPIO84"), 215 PINCTRL_PIN(GPIO84, "GPIO84"),
216 PINCTRL_PIN(GPIO85, "GPIO85"), 216 PINCTRL_PIN(GPIO85, "GPIO85"),
217 PINCTRL_PIN(GPIO86, "GPIO86"), 217 PINCTRL_PIN(GPIO86, "GPIO86"),
218 PINCTRL_PIN(GPIO87, "GPIO87"), 218 PINCTRL_PIN(GPIO87, "GPIO87"),
219 PINCTRL_PIN(GPIO88, "GPIO88"), 219 PINCTRL_PIN(GPIO88, "GPIO88"),
220 PINCTRL_PIN(GPIO89, "GPIO89"), 220 PINCTRL_PIN(GPIO89, "GPIO89"),
221 PINCTRL_PIN(GPIO90, "GPIO90"), 221 PINCTRL_PIN(GPIO90, "GPIO90"),
222 PINCTRL_PIN(GPIO91, "GPIO91"), 222 PINCTRL_PIN(GPIO91, "GPIO91"),
223 PINCTRL_PIN(GPIO92, "GPIO92"), 223 PINCTRL_PIN(GPIO92, "GPIO92"),
224 PINCTRL_PIN(GPIO93, "GPIO93"), 224 PINCTRL_PIN(GPIO93, "GPIO93"),
225 PINCTRL_PIN(GPIO94, "GPIO94"), 225 PINCTRL_PIN(GPIO94, "GPIO94"),
226 PINCTRL_PIN(GPIO95, "GPIO95"), 226 PINCTRL_PIN(GPIO95, "GPIO95"),
227 PINCTRL_PIN(GPIO96, "GPIO96"), 227 PINCTRL_PIN(GPIO96, "GPIO96"),
228 PINCTRL_PIN(GPIO97, "GPIO97"), 228 PINCTRL_PIN(GPIO97, "GPIO97"),
229 PINCTRL_PIN(GPIO98, "GPIO98"), 229 PINCTRL_PIN(GPIO98, "GPIO98"),
230 PINCTRL_PIN(GPIO99, "GPIO99"), 230 PINCTRL_PIN(GPIO99, "GPIO99"),
231 PINCTRL_PIN(GPIO100, "GPIO100"), 231 PINCTRL_PIN(GPIO100, "GPIO100"),
232 PINCTRL_PIN(GPIO101, "GPIO101"), 232 PINCTRL_PIN(GPIO101, "GPIO101"),
233 PINCTRL_PIN(GPIO102, "GPIO102"), 233 PINCTRL_PIN(GPIO102, "GPIO102"),
234 PINCTRL_PIN(GPIO103, "GPIO103"), 234 PINCTRL_PIN(GPIO103, "GPIO103"),
235 PINCTRL_PIN(GPIO104, "GPIO104"), 235 PINCTRL_PIN(GPIO104, "GPIO104"),
236 PINCTRL_PIN(GPIO105, "GPIO105"), 236 PINCTRL_PIN(GPIO105, "GPIO105"),
237 PINCTRL_PIN(GPIO106, "GPIO106"), 237 PINCTRL_PIN(GPIO106, "GPIO106"),
238 PINCTRL_PIN(GPIO107, "GPIO107"), 238 PINCTRL_PIN(GPIO107, "GPIO107"),
239 PINCTRL_PIN(GPIO108, "GPIO108"), 239 PINCTRL_PIN(GPIO108, "GPIO108"),
240 PINCTRL_PIN(GPIO109, "GPIO109"), 240 PINCTRL_PIN(GPIO109, "GPIO109"),
241 PINCTRL_PIN(GPIO110, "GPIO110"), 241 PINCTRL_PIN(GPIO110, "GPIO110"),
242 PINCTRL_PIN(GPIO111, "GPIO111"), 242 PINCTRL_PIN(GPIO111, "GPIO111"),
243 PINCTRL_PIN(GPIO112, "GPIO112"), 243 PINCTRL_PIN(GPIO112, "GPIO112"),
244 PINCTRL_PIN(GPIO113, "GPIO113"), 244 PINCTRL_PIN(GPIO113, "GPIO113"),
245 PINCTRL_PIN(GPIO114, "GPIO114"), 245 PINCTRL_PIN(GPIO114, "GPIO114"),
246 PINCTRL_PIN(GPIO115, "GPIO115"), 246 PINCTRL_PIN(GPIO115, "GPIO115"),
247 PINCTRL_PIN(GPIO116, "GPIO116"), 247 PINCTRL_PIN(GPIO116, "GPIO116"),
248 PINCTRL_PIN(GPIO117, "GPIO117"), 248 PINCTRL_PIN(GPIO117, "GPIO117"),
249 PINCTRL_PIN(GPIO118, "GPIO118"), 249 PINCTRL_PIN(GPIO118, "GPIO118"),
250 PINCTRL_PIN(GPIO119, "GPIO119"), 250 PINCTRL_PIN(GPIO119, "GPIO119"),
251 PINCTRL_PIN(GPIO120, "GPIO120"), 251 PINCTRL_PIN(GPIO120, "GPIO120"),
252 PINCTRL_PIN(GPIO121, "GPIO121"), 252 PINCTRL_PIN(GPIO121, "GPIO121"),
253 PINCTRL_PIN(GPIO122, "GPIO122"), 253 PINCTRL_PIN(GPIO122, "GPIO122"),
254 PINCTRL_PIN(PWR_SCL, "PWR_SCL"), 254 PINCTRL_PIN(PWR_SCL, "PWR_SCL"),
255 PINCTRL_PIN(PWR_SDA, "PWR_SDA"), 255 PINCTRL_PIN(PWR_SDA, "PWR_SDA"),
256 PINCTRL_PIN(TDI, "TDI"), 256 PINCTRL_PIN(TDI, "TDI"),
257 PINCTRL_PIN(TMS, "TMS"), 257 PINCTRL_PIN(TMS, "TMS"),
258 PINCTRL_PIN(TCK, "TCK"), 258 PINCTRL_PIN(TCK, "TCK"),
259 PINCTRL_PIN(TDO, "TDO"), 259 PINCTRL_PIN(TDO, "TDO"),
260 PINCTRL_PIN(TRST, "TRST"), 260 PINCTRL_PIN(TRST, "TRST"),
261 PINCTRL_PIN(WAKEUP, "WAKEUP"), 261 PINCTRL_PIN(WAKEUP, "WAKEUP"),
262 }; 262 };
263 263
264 struct pxa3xx_mfp_pin pxa168_mfp[] = { 264 struct pxa3xx_mfp_pin pxa168_mfp[] = {
265 /* pin offs f0 f1 f2 f3 f4 f5 f6 f7 */ 265 /* pin offs f0 f1 f2 f3 f4 f5 f6 f7 */
266 MFPR_168(GPIO0, 0x04C, DFIO, NONE, NONE, MSP, MMC3_CMD, GPIO, MMC3, NONE), 266 MFPR_168(GPIO0, 0x04C, DFIO, NONE, NONE, MSP, MMC3_CMD, GPIO, MMC3, NONE),
267 MFPR_168(GPIO1, 0x050, DFIO, NONE, NONE, MSP, MMC3_CLK, GPIO, MMC3, NONE), 267 MFPR_168(GPIO1, 0x050, DFIO, NONE, NONE, MSP, MMC3_CLK, GPIO, MMC3, NONE),
268 MFPR_168(GPIO2, 0x054, DFIO, NONE, NONE, MSP, NONE, GPIO, MMC3, NONE), 268 MFPR_168(GPIO2, 0x054, DFIO, NONE, NONE, MSP, NONE, GPIO, MMC3, NONE),
269 MFPR_168(GPIO3, 0x058, DFIO, NONE, NONE, NONE, NONE, GPIO, MMC3, NONE), 269 MFPR_168(GPIO3, 0x058, DFIO, NONE, NONE, NONE, NONE, GPIO, MMC3, NONE),
270 MFPR_168(GPIO4, 0x05C, DFIO, NONE, NONE, MSP_DAT3, NONE, GPIO, MMC3, NONE), 270 MFPR_168(GPIO4, 0x05C, DFIO, NONE, NONE, MSP_DAT3, NONE, GPIO, MMC3, NONE),
271 MFPR_168(GPIO5, 0x060, DFIO, NONE, NONE, MSP, NONE, GPIO, MMC3, NONE), 271 MFPR_168(GPIO5, 0x060, DFIO, NONE, NONE, MSP, NONE, GPIO, MMC3, NONE),
272 MFPR_168(GPIO6, 0x064, DFIO, NONE, NONE, MSP, NONE, GPIO, MMC3, NONE), 272 MFPR_168(GPIO6, 0x064, DFIO, NONE, NONE, MSP, NONE, GPIO, MMC3, NONE),
273 MFPR_168(GPIO7, 0x068, DFIO, NONE, NONE, MSP, NONE, GPIO, MMC3, NONE), 273 MFPR_168(GPIO7, 0x068, DFIO, NONE, NONE, MSP, NONE, GPIO, MMC3, NONE),
274 MFPR_168(GPIO8, 0x06C, DFIO, MMC2, UART3_TX, NONE, MMC2_CMD, GPIO, MMC3_CLK, NONE), 274 MFPR_168(GPIO8, 0x06C, DFIO, MMC2, UART3_TX, NONE, MMC2_CMD, GPIO, MMC3_CLK, NONE),
275 MFPR_168(GPIO9, 0x070, DFIO, MMC2, UART3, NONE, MMC2_CLK, GPIO, MMC3_CMD, NONE), 275 MFPR_168(GPIO9, 0x070, DFIO, MMC2, UART3, NONE, MMC2_CLK, GPIO, MMC3_CMD, NONE),
276 MFPR_168(GPIO10, 0x074, DFIO, MMC2, UART3, NONE, NONE, GPIO, MSP_DAT3, NONE), 276 MFPR_168(GPIO10, 0x074, DFIO, MMC2, UART3, NONE, NONE, GPIO, MSP_DAT3, NONE),
277 MFPR_168(GPIO11, 0x078, DFIO, MMC2, UART3, NONE, NONE, GPIO, MSP, NONE), 277 MFPR_168(GPIO11, 0x078, DFIO, MMC2, UART3, NONE, NONE, GPIO, MSP, NONE),
278 MFPR_168(GPIO12, 0x07C, DFIO, MMC2, UART3, NONE, NONE, GPIO, MSP, NONE), 278 MFPR_168(GPIO12, 0x07C, DFIO, MMC2, UART3, NONE, NONE, GPIO, MSP, NONE),
279 MFPR_168(GPIO13, 0x080, DFIO, MMC2, UART3, NONE, NONE, GPIO, MSP, NONE), 279 MFPR_168(GPIO13, 0x080, DFIO, MMC2, UART3, NONE, NONE, GPIO, MSP, NONE),
280 MFPR_168(GPIO14, 0x084, DFIO, MMC2, NONE, NONE, NONE, GPIO, MSP, NONE), 280 MFPR_168(GPIO14, 0x084, DFIO, MMC2, NONE, NONE, NONE, GPIO, MSP, NONE),
281 MFPR_168(GPIO15, 0x088, DFIO, MMC2, NONE, NONE, NONE, GPIO, MSP, NONE), 281 MFPR_168(GPIO15, 0x088, DFIO, MMC2, NONE, NONE, NONE, GPIO, MSP, NONE),
282 MFPR_168(GPIO16, 0x08C, GPIO, NAND, SMC_CS0, SMC_CS1, NONE, NONE, MMC3, NONE), 282 MFPR_168(GPIO16, 0x08C, GPIO, NAND, SMC_CS0, SMC_CS1, NONE, NONE, MMC3, NONE),
283 MFPR_168(GPIO17, 0x090, NAND, NONE, NONE, NONE, NONE, GPIO, MSP, NONE), 283 MFPR_168(GPIO17, 0x090, NAND, NONE, NONE, NONE, NONE, GPIO, MSP, NONE),
284 MFPR_168(GPIO18, 0x094, GPIO, NAND, SMC_CS1, SMC_CS0, NONE, NONE, NONE, NONE), 284 MFPR_168(GPIO18, 0x094, GPIO, NAND, SMC_CS1, SMC_CS0, NONE, NONE, NONE, NONE),
285 MFPR_168(GPIO19, 0x098, SMC_CS0, NONE, NONE, CF, NONE, GPIO, NONE, NONE), 285 MFPR_168(GPIO19, 0x098, SMC_CS0, NONE, NONE, CF, NONE, GPIO, NONE, NONE),
286 MFPR_168(GPIO20, 0x09C, GPIO, NONE, SMC_CS1, CF, CF_RDY, NONE, NONE, NONE), 286 MFPR_168(GPIO20, 0x09C, GPIO, NONE, SMC_CS1, CF, CF_RDY, NONE, NONE, NONE),
287 MFPR_168(GPIO21, 0x0A0, NAND, MMC2_CLK, NONE, NONE, NONE, GPIO, NONE, NONE), 287 MFPR_168(GPIO21, 0x0A0, NAND, MMC2_CLK, NONE, NONE, NONE, GPIO, NONE, NONE),
288 MFPR_168(GPIO22, 0x0A4, NAND, MMC2_CMD, NONE, NONE, NONE, GPIO, NONE, NONE), 288 MFPR_168(GPIO22, 0x0A4, NAND, MMC2_CMD, NONE, NONE, NONE, GPIO, NONE, NONE),
289 MFPR_168(GPIO23, 0x0A8, SMC, NAND, NONE, CF, NONE, GPIO, NONE, NONE), 289 MFPR_168(GPIO23, 0x0A8, SMC, NAND, NONE, CF, NONE, GPIO, NONE, NONE),
290 MFPR_168(GPIO24, 0x0AC, NAND, NONE, NONE, NONE, NONE, GPIO, NONE, NONE), 290 MFPR_168(GPIO24, 0x0AC, NAND, NONE, NONE, NONE, NONE, GPIO, NONE, NONE),
291 MFPR_168(GPIO25, 0x0B0, SMC, NAND, NONE, CF, NONE, GPIO, NONE, NONE), 291 MFPR_168(GPIO25, 0x0B0, SMC, NAND, NONE, CF, NONE, GPIO, NONE, NONE),
292 MFPR_168(GPIO26, 0x0B4, GPIO, NAND, NONE, NONE, CF, NONE, NONE, NONE), 292 MFPR_168(GPIO26, 0x0B4, GPIO, NAND, NONE, NONE, CF, NONE, NONE, NONE),
293 MFPR_168(GPIO27, 0x0B8, SMC_INT, NAND, SMC, NONE, SMC_RDY, GPIO, NONE, NONE), 293 MFPR_168(GPIO27, 0x0B8, SMC_INT, NAND, SMC, NONE, SMC_RDY, GPIO, NONE, NONE),
294 MFPR_168(GPIO28, 0x0BC, SMC_RDY, MMC4, SMC, CF_RDY, NONE, GPIO, MMC2_CMD, NONE), 294 MFPR_168(GPIO28, 0x0BC, SMC_RDY, MMC4, SMC, CF_RDY, NONE, GPIO, MMC2_CMD, NONE),
295 MFPR_168(GPIO29, 0x0C0, SMC, MMC4, NONE, CF, NONE, GPIO, MMC2_CLK, KP_DK), 295 MFPR_168(GPIO29, 0x0C0, SMC, MMC4, NONE, CF, NONE, GPIO, MMC2_CLK, KP_DK),
296 MFPR_168(GPIO30, 0x0C4, SMC, MMC4, UART3_TX, CF, NONE, GPIO, MMC2, KP_DK), 296 MFPR_168(GPIO30, 0x0C4, SMC, MMC4, UART3_TX, CF, NONE, GPIO, MMC2, KP_DK),
297 MFPR_168(GPIO31, 0x0C8, SMC, MMC4, UART3, CF, NONE, GPIO, MMC2, KP_DK), 297 MFPR_168(GPIO31, 0x0C8, SMC, MMC4, UART3, CF, NONE, GPIO, MMC2, KP_DK),
298 MFPR_168(GPIO32, 0x0CC, SMC, MMC4, UART3, CF, NONE, GPIO, MMC2, KP_DK), 298 MFPR_168(GPIO32, 0x0CC, SMC, MMC4, UART3, CF, NONE, GPIO, MMC2, KP_DK),
299 MFPR_168(GPIO33, 0x0D0, SMC, MMC4, UART3, CF, CF_nINPACK, GPIO, MMC2, KP_DK), 299 MFPR_168(GPIO33, 0x0D0, SMC, MMC4, UART3, CF, CF_nINPACK, GPIO, MMC2, KP_DK),
300 MFPR_168(GPIO34, 0x0D4, GPIO, NONE, SMC_CS1, CF, CF_nWAIT, NONE, MMC3, KP_DK), 300 MFPR_168(GPIO34, 0x0D4, GPIO, NONE, SMC_CS1, CF, CF_nWAIT, NONE, MMC3, KP_DK),
301 MFPR_168(GPIO35, 0x0D8, GPIO, NONE, SMC, CF_nINPACK, NONE, NONE, MMC3_CMD, KP_DK), 301 MFPR_168(GPIO35, 0x0D8, GPIO, NONE, SMC, CF_nINPACK, NONE, NONE, MMC3_CMD, KP_DK),
302 MFPR_168(GPIO36, 0x0DC, GPIO, NONE, SMC, CF_nWAIT, NONE, NONE, MMC3_CLK, KP_DK), 302 MFPR_168(GPIO36, 0x0DC, GPIO, NONE, SMC, CF_nWAIT, NONE, NONE, MMC3_CLK, KP_DK),
303 MFPR_168(GPIO37, 0x000, GPIO, MMC1, NONE, KP_MKOUT, CCIC, XP, KP_MKIN, KP_DK), 303 MFPR_168(GPIO37, 0x000, GPIO, MMC1, NONE, KP_MKOUT, CCIC, XP, KP_MKIN, KP_DK),
304 MFPR_168(GPIO38, 0x004, GPIO, MMC1, NONE, KP_MKOUT, CCIC, XP, KP_MKIN, KP_DK), 304 MFPR_168(GPIO38, 0x004, GPIO, MMC1, NONE, KP_MKOUT, CCIC, XP, KP_MKIN, KP_DK),
305 MFPR_168(GPIO39, 0x008, GPIO, NONE, NONE, KP_MKOUT, CCIC, XP, KP_MKIN, KP_DK), 305 MFPR_168(GPIO39, 0x008, GPIO, NONE, NONE, KP_MKOUT, CCIC, XP, KP_MKIN, KP_DK),
306 MFPR_168(GPIO40, 0x00C, GPIO, MMC1, MSP, KP_MKOUT, CCIC, XP, KP_MKIN, KP_DK), 306 MFPR_168(GPIO40, 0x00C, GPIO, MMC1, MSP, KP_MKOUT, CCIC, XP, KP_MKIN, KP_DK),
307 MFPR_168(GPIO41, 0x010, GPIO, MMC1, MSP, NONE, CCIC, XP, KP_MKIN, KP_DK), 307 MFPR_168(GPIO41, 0x010, GPIO, MMC1, MSP, NONE, CCIC, XP, KP_MKIN, KP_DK),
308 MFPR_168(GPIO42, 0x014, GPIO, I2C, NONE, MSP, CCIC, XP, KP_MKIN, KP_DK), 308 MFPR_168(GPIO42, 0x014, GPIO, I2C, NONE, MSP, CCIC, XP, KP_MKIN, KP_DK),
309 MFPR_168(GPIO43, 0x018, GPIO, MMC1, MSP, MSP_INS, NONE, NONE, KP_MKIN, KP_DK), 309 MFPR_168(GPIO43, 0x018, GPIO, MMC1, MSP, MSP_INS, NONE, NONE, KP_MKIN, KP_DK),
310 MFPR_168(GPIO44, 0x01C, GPIO, MMC1, MSP_DAT3, MSP, CCIC, XP, KP_MKIN, KP_DK), 310 MFPR_168(GPIO44, 0x01C, GPIO, MMC1, MSP_DAT3, MSP, CCIC, XP, KP_MKIN, KP_DK),
311 MFPR_168(GPIO45, 0x020, GPIO, NONE, NONE, MSP, CCIC, XP, NONE, KP_DK), 311 MFPR_168(GPIO45, 0x020, GPIO, NONE, NONE, MSP, CCIC, XP, NONE, KP_DK),
312 MFPR_168(GPIO46, 0x024, GPIO, MMC1, MSP_INS, MSP, CCIC, NONE, KP_MKOUT, KP_DK), 312 MFPR_168(GPIO46, 0x024, GPIO, MMC1, MSP_INS, MSP, CCIC, NONE, KP_MKOUT, KP_DK),
313 MFPR_168(GPIO47, 0x028, GPIO, NONE, NONE, MSP_INS, NONE, XP, NONE, KP_DK), 313 MFPR_168(GPIO47, 0x028, GPIO, NONE, NONE, MSP_INS, NONE, XP, NONE, KP_DK),
314 MFPR_168(GPIO48, 0x02C, GPIO, MMC1, NONE, MSP_DAT3, CCIC, NONE, NONE, KP_DK), 314 MFPR_168(GPIO48, 0x02C, GPIO, MMC1, NONE, MSP_DAT3, CCIC, NONE, NONE, KP_DK),
315 MFPR_168(GPIO49, 0x030, GPIO, MMC1, NONE, MSP, NONE, XD, KP_MKOUT, NONE), 315 MFPR_168(GPIO49, 0x030, GPIO, MMC1, NONE, MSP, NONE, XD, KP_MKOUT, NONE),
316 MFPR_168(GPIO50, 0x034, GPIO, I2C, NONE, MSP, CCIC, XD, KP_MKOUT, NONE), 316 MFPR_168(GPIO50, 0x034, GPIO, I2C, NONE, MSP, CCIC, XD, KP_MKOUT, NONE),
317 MFPR_168(GPIO51, 0x038, GPIO, MMC1, NONE, MSP, NONE, XD, KP_MKOUT, NONE), 317 MFPR_168(GPIO51, 0x038, GPIO, MMC1, NONE, MSP, NONE, XD, KP_MKOUT, NONE),
318 MFPR_168(GPIO52, 0x03C, GPIO, MMC1, NONE, MSP, NONE, XD, KP_MKOUT, NONE), 318 MFPR_168(GPIO52, 0x03C, GPIO, MMC1, NONE, MSP, NONE, XD, KP_MKOUT, NONE),
319 MFPR_168(GPIO53, 0x040, GPIO, MMC1, NONE, NONE, NONE, XD, KP_MKOUT, NONE), 319 MFPR_168(GPIO53, 0x040, GPIO, MMC1, NONE, NONE, NONE, XD, KP_MKOUT, NONE),
320 MFPR_168(GPIO54, 0x044, GPIO, MMC1, NONE, NONE, CCIC, XD, KP_MKOUT, NONE), 320 MFPR_168(GPIO54, 0x044, GPIO, MMC1, NONE, NONE, CCIC, XD, KP_MKOUT, NONE),
321 MFPR_168(GPIO55, 0x048, GPIO, NONE, NONE, MSP, CCIC, XD, KP_MKOUT, NONE), 321 MFPR_168(GPIO55, 0x048, GPIO, NONE, NONE, MSP, CCIC, XD, KP_MKOUT, NONE),
322 MFPR_168(GPIO56, 0x0E0, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 322 MFPR_168(GPIO56, 0x0E0, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
323 MFPR_168(GPIO57, 0x0E4, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 323 MFPR_168(GPIO57, 0x0E4, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
324 MFPR_168(GPIO58, 0x0E8, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 324 MFPR_168(GPIO58, 0x0E8, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
325 MFPR_168(GPIO59, 0x0EC, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 325 MFPR_168(GPIO59, 0x0EC, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
326 MFPR_168(GPIO60, 0x0F0, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 326 MFPR_168(GPIO60, 0x0F0, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
327 MFPR_168(GPIO61, 0x0F4, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 327 MFPR_168(GPIO61, 0x0F4, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
328 MFPR_168(GPIO62, 0x0F8, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 328 MFPR_168(GPIO62, 0x0F8, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
329 MFPR_168(GPIO63, 0x0FC, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 329 MFPR_168(GPIO63, 0x0FC, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
330 MFPR_168(GPIO64, 0x100, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 330 MFPR_168(GPIO64, 0x100, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
331 MFPR_168(GPIO65, 0x104, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 331 MFPR_168(GPIO65, 0x104, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
332 MFPR_168(GPIO66, 0x108, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 332 MFPR_168(GPIO66, 0x108, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
333 MFPR_168(GPIO67, 0x10C, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 333 MFPR_168(GPIO67, 0x10C, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
334 MFPR_168(GPIO68, 0x110, GPIO, LCD, NONE, XD, NONE, NONE, NONE, NONE), 334 MFPR_168(GPIO68, 0x110, GPIO, LCD, NONE, XD, NONE, NONE, NONE, NONE),
335 MFPR_168(GPIO69, 0x114, GPIO, LCD, NONE, XD, NONE, NONE, NONE, NONE), 335 MFPR_168(GPIO69, 0x114, GPIO, LCD, NONE, XD, NONE, NONE, NONE, NONE),
336 MFPR_168(GPIO70, 0x118, GPIO, LCD, NONE, XD, NONE, NONE, NONE, NONE), 336 MFPR_168(GPIO70, 0x118, GPIO, LCD, NONE, XD, NONE, NONE, NONE, NONE),
337 MFPR_168(GPIO71, 0x11C, GPIO, LCD, NONE, XD, NONE, NONE, NONE, NONE), 337 MFPR_168(GPIO71, 0x11C, GPIO, LCD, NONE, XD, NONE, NONE, NONE, NONE),
338 MFPR_168(GPIO72, 0x120, GPIO, LCD, NONE, XD, NONE, NONE, NONE, NONE), 338 MFPR_168(GPIO72, 0x120, GPIO, LCD, NONE, XD, NONE, NONE, NONE, NONE),
339 MFPR_168(GPIO73, 0x124, GPIO, LCD, NONE, XD, NONE, NONE, NONE, NONE), 339 MFPR_168(GPIO73, 0x124, GPIO, LCD, NONE, XD, NONE, NONE, NONE, NONE),
340 MFPR_168(GPIO74, 0x128, GPIO, LCD, PWM, XD, NONE, NONE, NONE, NONE), 340 MFPR_168(GPIO74, 0x128, GPIO, LCD, PWM, XD, NONE, NONE, NONE, NONE),
341 MFPR_168(GPIO75, 0x12C, GPIO, LCD, PWM, XD, ONE_WIRE, NONE, NONE, NONE), 341 MFPR_168(GPIO75, 0x12C, GPIO, LCD, PWM, XD, ONE_WIRE, NONE, NONE, NONE),
342 MFPR_168(GPIO76, 0x130, GPIO, LCD, PWM, I2C, NONE, NONE, MSP_INS, NONE), 342 MFPR_168(GPIO76, 0x130, GPIO, LCD, PWM, I2C, NONE, NONE, MSP_INS, NONE),
343 MFPR_168(GPIO77, 0x134, GPIO, LCD, PWM1, I2C, ONE_WIRE, NONE, XD, NONE), 343 MFPR_168(GPIO77, 0x134, GPIO, LCD, PWM1, I2C, ONE_WIRE, NONE, XD, NONE),
344 MFPR_168(GPIO78, 0x138, GPIO, LCD, NONE, NONE, NONE, MMC4, NONE, NONE), 344 MFPR_168(GPIO78, 0x138, GPIO, LCD, NONE, NONE, NONE, MMC4, NONE, NONE),
345 MFPR_168(GPIO79, 0x13C, GPIO, LCD, NONE, NONE, ONE_WIRE, MMC4, NONE, NONE), 345 MFPR_168(GPIO79, 0x13C, GPIO, LCD, NONE, NONE, ONE_WIRE, MMC4, NONE, NONE),
346 MFPR_168(GPIO80, 0x140, GPIO, LCD, NONE, I2C, NONE, MMC4, NONE, NONE), 346 MFPR_168(GPIO80, 0x140, GPIO, LCD, NONE, I2C, NONE, MMC4, NONE, NONE),
347 MFPR_168(GPIO81, 0x144, GPIO, LCD, NONE, I2C, ONE_WIRE, MMC4, NONE, NONE), 347 MFPR_168(GPIO81, 0x144, GPIO, LCD, NONE, I2C, ONE_WIRE, MMC4, NONE, NONE),
348 MFPR_168(GPIO82, 0x148, GPIO, LCD, PWM, NONE, NONE, MMC4, NONE, NONE), 348 MFPR_168(GPIO82, 0x148, GPIO, LCD, PWM, NONE, NONE, MMC4, NONE, NONE),
349 MFPR_168(GPIO83, 0x14C, GPIO, LCD, PWM, NONE, RESET, MMC4, NONE, NONE), 349 MFPR_168(GPIO83, 0x14C, GPIO, LCD, PWM, NONE, RESET, MMC4, NONE, NONE),
350 MFPR_168(GPIO84, 0x150, GPIO, NONE, PWM, ONE_WIRE, PWM1, NONE, NONE, EXT_32K_IN), 350 MFPR_168(GPIO84, 0x150, GPIO, NONE, PWM, ONE_WIRE, PWM1, NONE, NONE, EXT_32K_IN),
351 MFPR_168(GPIO85, 0x154, GPIO, NONE, PWM1, NONE, NONE, NONE, NONE, USB), 351 MFPR_168(GPIO85, 0x154, GPIO, NONE, PWM1, NONE, NONE, NONE, NONE, USB),
352 MFPR_168(GPIO86, 0x158, GPIO, MMC2, UART2, NONE, JTAG, ETH_TX, SSP5_TX, SSP5), 352 MFPR_168(GPIO86, 0x158, GPIO, MMC2, UART2, NONE, JTAG, ETH_TX, SSP5_TX, SSP5),
353 MFPR_168(GPIO87, 0x15C, GPIO, MMC2, UART2, NONE, JTAG, ETH_TX, SSP5, SSP5_TX), 353 MFPR_168(GPIO87, 0x15C, GPIO, MMC2, UART2, NONE, JTAG, ETH_TX, SSP5, SSP5_TX),
354 MFPR_168(GPIO88, 0x160, GPIO, MMC2, UART2, UART2_TX, JTAG, ETH_TX, ETH_RX, SSP5), 354 MFPR_168(GPIO88, 0x160, GPIO, MMC2, UART2, UART2_TX, JTAG, ETH_TX, ETH_RX, SSP5),
355 MFPR_168(GPIO89, 0x164, GPIO, MMC2, UART2_TX, UART2, JTAG, ETH_TX, ETH_RX, SSP5), 355 MFPR_168(GPIO89, 0x164, GPIO, MMC2, UART2_TX, UART2, JTAG, ETH_TX, ETH_RX, SSP5),
356 MFPR_168(GPIO90, 0x168, GPIO, MMC2, NONE, SSP3, JTAG, ETH_TX, ETH_RX, NONE), 356 MFPR_168(GPIO90, 0x168, GPIO, MMC2, NONE, SSP3, JTAG, ETH_TX, ETH_RX, NONE),
357 MFPR_168(GPIO91, 0x16C, GPIO, MMC2, NONE, SSP3, SSP4, ETH_TX, ETH_RX, NONE), 357 MFPR_168(GPIO91, 0x16C, GPIO, MMC2, NONE, SSP3, SSP4, ETH_TX, ETH_RX, NONE),
358 MFPR_168(GPIO92, 0x170, GPIO, MMC2, NONE, SSP3, SSP3_TX, ETH, NONE, NONE), 358 MFPR_168(GPIO92, 0x170, GPIO, MMC2, NONE, SSP3, SSP3_TX, ETH, NONE, NONE),
359 MFPR_168(GPIO93, 0x174, GPIO, MMC2, NONE, SSP3_TX, SSP3, ETH, NONE, NONE), 359 MFPR_168(GPIO93, 0x174, GPIO, MMC2, NONE, SSP3_TX, SSP3, ETH, NONE, NONE),
360 MFPR_168(GPIO94, 0x178, GPIO, MMC2_CMD, SSP3, AC97_SYSCLK, AC97, ETH, NONE, NONE), 360 MFPR_168(GPIO94, 0x178, GPIO, MMC2_CMD, SSP3, AC97_SYSCLK, AC97, ETH, NONE, NONE),
361 MFPR_168(GPIO95, 0x17C, GPIO, MMC2_CLK, NONE, NONE, AC97, ETH, NONE, NONE), 361 MFPR_168(GPIO95, 0x17C, GPIO, MMC2_CLK, NONE, NONE, AC97, ETH, NONE, NONE),
362 MFPR_168(GPIO96, 0x180, GPIO, PWM, NONE, MMC2, NONE, ETH_RX, ETH_TX, NONE), 362 MFPR_168(GPIO96, 0x180, GPIO, PWM, NONE, MMC2, NONE, ETH_RX, ETH_TX, NONE),
363 MFPR_168(GPIO97, 0x184, GPIO, PWM, ONE_WIRE, NONE, NONE, ETH_RX, ETH_TX, NONE), 363 MFPR_168(GPIO97, 0x184, GPIO, PWM, ONE_WIRE, NONE, NONE, ETH_RX, ETH_TX, NONE),
364 MFPR_168(GPIO98, 0x188, GPIO, PWM1, UART3_TX, UART3, NONE, ETH_RX, ETH_TX, NONE), 364 MFPR_168(GPIO98, 0x188, GPIO, PWM1, UART3_TX, UART3, NONE, ETH_RX, ETH_TX, NONE),
365 MFPR_168(GPIO99, 0x18C, GPIO, ONE_WIRE, UART3, UART3_TX, NONE, ETH_RX, ETH_TX, NONE), 365 MFPR_168(GPIO99, 0x18C, GPIO, ONE_WIRE, UART3, UART3_TX, NONE, ETH_RX, ETH_TX, NONE),
366 MFPR_168(GPIO100, 0x190, GPIO, NONE, UART3_CTS, UART3, NONE, ETH, NONE, NONE), 366 MFPR_168(GPIO100, 0x190, GPIO, NONE, UART3_CTS, UART3, NONE, ETH, NONE, NONE),
367 MFPR_168(GPIO101, 0x194, GPIO, NONE, UART3, UART3_CTS, NONE, ETH, NONE, NONE), 367 MFPR_168(GPIO101, 0x194, GPIO, NONE, UART3, UART3_CTS, NONE, ETH, NONE, NONE),
368 MFPR_168(GPIO102, 0x198, GPIO, I2C, UART3, SSP4, NONE, NONE, NONE, NONE), 368 MFPR_168(GPIO102, 0x198, GPIO, I2C, UART3, SSP4, NONE, NONE, NONE, NONE),
369 MFPR_168(GPIO103, 0x19C, GPIO, I2C, UART3, SSP4, SSP2, ETH, NONE, NONE), 369 MFPR_168(GPIO103, 0x19C, GPIO, I2C, UART3, SSP4, SSP2, ETH, NONE, NONE),
370 MFPR_168(GPIO104, 0x1A0, GPIO, PWM, UART1, SSP4, SSP4_TX, AC97, KP_MKOUT, NONE), 370 MFPR_168(GPIO104, 0x1A0, GPIO, PWM, UART1, SSP4, SSP4_TX, AC97, KP_MKOUT, NONE),
371 MFPR_168(GPIO105, 0x1A4, GPIO, I2C, UART1, SSP4_TX, SSP4, AC97, KP_MKOUT, NONE), 371 MFPR_168(GPIO105, 0x1A4, GPIO, I2C, UART1, SSP4_TX, SSP4, AC97, KP_MKOUT, NONE),
372 MFPR_168(GPIO106, 0x1A8, GPIO, I2C, PWM1, AC97_SYSCLK, MMC2, NONE, KP_MKOUT, NONE), 372 MFPR_168(GPIO106, 0x1A8, GPIO, I2C, PWM1, AC97_SYSCLK, MMC2, NONE, KP_MKOUT, NONE),
373 MFPR_168(GPIO107, 0x1AC, GPIO, UART1_TX, UART1, NONE, SSP2, MSP_DAT3, NONE, KP_MKIN), 373 MFPR_168(GPIO107, 0x1AC, GPIO, UART1_TX, UART1, NONE, SSP2, MSP_DAT3, NONE, KP_MKIN),
374 MFPR_168(GPIO108, 0x1B0, GPIO, UART1, UART1_TX, NONE, SSP2_TX, MSP, NONE, KP_MKIN), 374 MFPR_168(GPIO108, 0x1B0, GPIO, UART1, UART1_TX, NONE, SSP2_TX, MSP, NONE, KP_MKIN),
375 MFPR_168(GPIO109, 0x1B4, GPIO, UART1_CTS, UART1, NONE, AC97_SYSCLK, MSP, NONE, KP_MKIN), 375 MFPR_168(GPIO109, 0x1B4, GPIO, UART1_CTS, UART1, NONE, AC97_SYSCLK, MSP, NONE, KP_MKIN),
376 MFPR_168(GPIO110, 0x1B8, GPIO, UART1, UART1_CTS, NONE, SMC_RDY, MSP, NONE, KP_MKIN), 376 MFPR_168(GPIO110, 0x1B8, GPIO, UART1, UART1_CTS, NONE, SMC_RDY, MSP, NONE, KP_MKIN),
377 MFPR_168(GPIO111, 0x1BC, GPIO, UART1_nRI, UART1, SSP3, SSP2, MSP, XD, KP_MKOUT), 377 MFPR_168(GPIO111, 0x1BC, GPIO, UART1_nRI, UART1, SSP3, SSP2, MSP, XD, KP_MKOUT),
378 MFPR_168(GPIO112, 0x1C0, GPIO, UART1_DTR, UART1, ONE_WIRE, SSP2, MSP, XD, KP_MKOUT), 378 MFPR_168(GPIO112, 0x1C0, GPIO, UART1_DTR, UART1, ONE_WIRE, SSP2, MSP, XD, KP_MKOUT),
379 MFPR_168(GPIO113, 0x1C4, GPIO, NONE, NONE, NONE, NONE, NONE, AC97_SYSCLK, NONE), 379 MFPR_168(GPIO113, 0x1C4, GPIO, NONE, NONE, NONE, NONE, NONE, AC97_SYSCLK, NONE),
380 MFPR_168(GPIO114, 0x1C8, GPIO, SSP1, NONE, NONE, NONE, NONE, AC97, NONE), 380 MFPR_168(GPIO114, 0x1C8, GPIO, SSP1, NONE, NONE, NONE, NONE, AC97, NONE),
381 MFPR_168(GPIO115, 0x1CC, GPIO, SSP1, NONE, NONE, NONE, NONE, AC97, NONE), 381 MFPR_168(GPIO115, 0x1CC, GPIO, SSP1, NONE, NONE, NONE, NONE, AC97, NONE),
382 MFPR_168(GPIO116, 0x1D0, GPIO, SSP1_TX, SSP1, NONE, NONE, NONE, AC97, NONE), 382 MFPR_168(GPIO116, 0x1D0, GPIO, SSP1_TX, SSP1, NONE, NONE, NONE, AC97, NONE),
383 MFPR_168(GPIO117, 0x1D4, GPIO, SSP1, SSP1_TX, NONE, MMC2_CMD, NONE, AC97, NONE), 383 MFPR_168(GPIO117, 0x1D4, GPIO, SSP1, SSP1_TX, NONE, MMC2_CMD, NONE, AC97, NONE),
384 MFPR_168(GPIO118, 0x1D8, GPIO, SSP2, NONE, NONE, MMC2_CLK, NONE, AC97, KP_MKIN), 384 MFPR_168(GPIO118, 0x1D8, GPIO, SSP2, NONE, NONE, MMC2_CLK, NONE, AC97, KP_MKIN),
385 MFPR_168(GPIO119, 0x1DC, GPIO, SSP2, NONE, NONE, MMC2, NONE, AC97, KP_MKIN), 385 MFPR_168(GPIO119, 0x1DC, GPIO, SSP2, NONE, NONE, MMC2, NONE, AC97, KP_MKIN),
386 MFPR_168(GPIO120, 0x1E0, GPIO, SSP2, SSP2_TX, NONE, MMC2, NONE, NONE, KP_MKIN), 386 MFPR_168(GPIO120, 0x1E0, GPIO, SSP2, SSP2_TX, NONE, MMC2, NONE, NONE, KP_MKIN),
387 MFPR_168(GPIO121, 0x1E4, GPIO, SSP2_TX, SSP2, NONE, MMC2, NONE, NONE, KP_MKIN), 387 MFPR_168(GPIO121, 0x1E4, GPIO, SSP2_TX, SSP2, NONE, MMC2, NONE, NONE, KP_MKIN),
388 MFPR_168(GPIO122, 0x1E8, GPIO, AC97_SYSCLK, SSP2, PWM, MMC2, NONE, NONE, NONE), 388 MFPR_168(GPIO122, 0x1E8, GPIO, AC97_SYSCLK, SSP2, PWM, MMC2, NONE, NONE, NONE),
389 MFPR_168(PWR_SCL, 0x1EC, PWRI2C, NONE, NONE, NONE, NONE, NONE, GPIO, MMC4), 389 MFPR_168(PWR_SCL, 0x1EC, PWRI2C, NONE, NONE, NONE, NONE, NONE, GPIO, MMC4),
390 MFPR_168(PWR_SDA, 0x1F0, PWRI2C, NONE, NONE, NONE, NONE, NONE, GPIO, NONE), 390 MFPR_168(PWR_SDA, 0x1F0, PWRI2C, NONE, NONE, NONE, NONE, NONE, GPIO, NONE),
391 MFPR_168(TDI, 0x1F4, JTAG, PWM1, UART2, MMC4, SSP5, NONE, XD, MMC4), 391 MFPR_168(TDI, 0x1F4, JTAG, PWM1, UART2, MMC4, SSP5, NONE, XD, MMC4),
392 MFPR_168(TMS, 0x1F8, JTAG, PWM, UART2, NONE, SSP5, NONE, XD, MMC4), 392 MFPR_168(TMS, 0x1F8, JTAG, PWM, UART2, NONE, SSP5, NONE, XD, MMC4),
393 MFPR_168(TCK, 0x1FC, JTAG, PWM, UART2, UART2_TX, SSP5, NONE, XD, MMC4), 393 MFPR_168(TCK, 0x1FC, JTAG, PWM, UART2, UART2_TX, SSP5, NONE, XD, MMC4),
394 MFPR_168(TDO, 0x200, JTAG, PWM, UART2_TX, UART2, SSP5_TX, NONE, XD, MMC4), 394 MFPR_168(TDO, 0x200, JTAG, PWM, UART2_TX, UART2, SSP5_TX, NONE, XD, MMC4),
395 MFPR_168(TRST, 0x204, JTAG, ONE_WIRE, SSP2, SSP3, AC97_SYSCLK, NONE, XD, MMC4), 395 MFPR_168(TRST, 0x204, JTAG, ONE_WIRE, SSP2, SSP3, AC97_SYSCLK, NONE, XD, MMC4),
396 MFPR_168(WAKEUP, 0x208, WAKEUP, ONE_WIRE, PWM1, PWM, SSP2, NONE, GPIO, MMC4), 396 MFPR_168(WAKEUP, 0x208, WAKEUP, ONE_WIRE, PWM1, PWM, SSP2, NONE, GPIO, MMC4),
397 }; 397 };
398 398
399 static const unsigned p168_jtag_pin1[] = {TDI, TMS, TCK, TDO, TRST}; 399 static const unsigned p168_jtag_pin1[] = {TDI, TMS, TCK, TDO, TRST};
400 static const unsigned p168_wakeup_pin1[] = {WAKEUP}; 400 static const unsigned p168_wakeup_pin1[] = {WAKEUP};
401 static const unsigned p168_ssp1rx_pin1[] = {GPIO114, GPIO115, GPIO116}; 401 static const unsigned p168_ssp1rx_pin1[] = {GPIO114, GPIO115, GPIO116};
402 static const unsigned p168_ssp1tx_pin1[] = {GPIO117}; 402 static const unsigned p168_ssp1tx_pin1[] = {GPIO117};
403 static const unsigned p168_ssp4rx_pin1[] = {GPIO102, GPIO103, GPIO104}; 403 static const unsigned p168_ssp4rx_pin1[] = {GPIO102, GPIO103, GPIO104};
404 static const unsigned p168_ssp4tx_pin1[] = {GPIO105}; 404 static const unsigned p168_ssp4tx_pin1[] = {GPIO105};
405 static const unsigned p168_ssp5rx_pin1[] = {GPIO86, GPIO88, GPIO89}; 405 static const unsigned p168_ssp5rx_pin1[] = {GPIO86, GPIO88, GPIO89};
406 static const unsigned p168_ssp5tx_pin1[] = {GPIO87}; 406 static const unsigned p168_ssp5tx_pin1[] = {GPIO87};
407 static const unsigned p168_i2c_pin1[] = {GPIO105, GPIO106}; 407 static const unsigned p168_i2c_pin1[] = {GPIO105, GPIO106};
408 static const unsigned p168_pwri2c_pin1[] = {PWR_SCL, PWR_SDA}; 408 static const unsigned p168_pwri2c_pin1[] = {PWR_SCL, PWR_SDA};
409 static const unsigned p168_mmc1_pin1[] = {GPIO40, GPIO41, GPIO43, GPIO46, 409 static const unsigned p168_mmc1_pin1[] = {GPIO40, GPIO41, GPIO43, GPIO46,
410 GPIO49, GPIO51, GPIO52, GPIO53}; 410 GPIO49, GPIO51, GPIO52, GPIO53};
411 static const unsigned p168_mmc2_data_pin1[] = {GPIO90, GPIO91, GPIO92, GPIO93}; 411 static const unsigned p168_mmc2_data_pin1[] = {GPIO90, GPIO91, GPIO92, GPIO93};
412 static const unsigned p168_mmc2_cmd_pin1[] = {GPIO94}; 412 static const unsigned p168_mmc2_cmd_pin1[] = {GPIO94};
413 static const unsigned p168_mmc2_clk_pin1[] = {GPIO95}; 413 static const unsigned p168_mmc2_clk_pin1[] = {GPIO95};
414 static const unsigned p168_mmc3_data_pin1[] = {GPIO0, GPIO1, GPIO2, GPIO3, 414 static const unsigned p168_mmc3_data_pin1[] = {GPIO0, GPIO1, GPIO2, GPIO3,
415 GPIO4, GPIO5, GPIO6, GPIO7}; 415 GPIO4, GPIO5, GPIO6, GPIO7};
416 static const unsigned p168_mmc3_cmd_pin1[] = {GPIO9}; 416 static const unsigned p168_mmc3_cmd_pin1[] = {GPIO9};
417 static const unsigned p168_mmc3_clk_pin1[] = {GPIO8}; 417 static const unsigned p168_mmc3_clk_pin1[] = {GPIO8};
418 static const unsigned p168_eth_pin1[] = {GPIO92, GPIO93, GPIO100, GPIO101, 418 static const unsigned p168_eth_pin1[] = {GPIO92, GPIO93, GPIO100, GPIO101,
419 GPIO103}; 419 GPIO103};
420 static const unsigned p168_ethtx_pin1[] = {GPIO86, GPIO87, GPIO88, GPIO89, 420 static const unsigned p168_ethtx_pin1[] = {GPIO86, GPIO87, GPIO88, GPIO89,
421 GPIO90, GPIO91}; 421 GPIO90, GPIO91};
422 static const unsigned p168_ethrx_pin1[] = {GPIO94, GPIO95, GPIO96, GPIO97, 422 static const unsigned p168_ethrx_pin1[] = {GPIO94, GPIO95, GPIO96, GPIO97,
423 GPIO98, GPIO99}; 423 GPIO98, GPIO99};
424 static const unsigned p168_uart1rx_pin1[] = {GPIO107}; 424 static const unsigned p168_uart1rx_pin1[] = {GPIO107};
425 static const unsigned p168_uart1tx_pin1[] = {GPIO108}; 425 static const unsigned p168_uart1tx_pin1[] = {GPIO108};
426 static const unsigned p168_uart3rx_pin1[] = {GPIO98, GPIO100, GPIO101}; 426 static const unsigned p168_uart3rx_pin1[] = {GPIO98, GPIO100, GPIO101};
427 static const unsigned p168_uart3tx_pin1[] = {GPIO99}; 427 static const unsigned p168_uart3tx_pin1[] = {GPIO99};
428 static const unsigned p168_msp_pin1[] = {GPIO40, GPIO41, GPIO42, GPIO43, 428 static const unsigned p168_msp_pin1[] = {GPIO40, GPIO41, GPIO42, GPIO43,
429 GPIO44, GPIO50}; 429 GPIO44, GPIO50};
430 static const unsigned p168_ccic_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40, 430 static const unsigned p168_ccic_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40,
431 GPIO41, GPIO42, GPIO44, GPIO45, GPIO46, GPIO48, GPIO54, GPIO55}; 431 GPIO41, GPIO42, GPIO44, GPIO45, GPIO46, GPIO48, GPIO54, GPIO55};
432 static const unsigned p168_xd_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40, 432 static const unsigned p168_xd_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40,
433 GPIO41, GPIO42, GPIO44, GPIO45, GPIO47, GPIO48, GPIO49, GPIO50, 433 GPIO41, GPIO42, GPIO44, GPIO45, GPIO47, GPIO48, GPIO49, GPIO50,
434 GPIO51, GPIO52}; 434 GPIO51, GPIO52};
435 static const unsigned p168_lcd_pin1[] = {GPIO56, GPIO57, GPIO58, GPIO59, 435 static const unsigned p168_lcd_pin1[] = {GPIO56, GPIO57, GPIO58, GPIO59,
436 GPIO60, GPIO61, GPIO62, GPIO63, GPIO64, GPIO65, GPIO66, GPIO67, 436 GPIO60, GPIO61, GPIO62, GPIO63, GPIO64, GPIO65, GPIO66, GPIO67,
437 GPIO68, GPIO69, GPIO70, GPIO71, GPIO72, GPIO73, GPIO74, GPIO75, 437 GPIO68, GPIO69, GPIO70, GPIO71, GPIO72, GPIO73, GPIO74, GPIO75,
438 GPIO76, GPIO77, GPIO78, GPIO79, GPIO80, GPIO81, GPIO82, GPIO83}; 438 GPIO76, GPIO77, GPIO78, GPIO79, GPIO80, GPIO81, GPIO82, GPIO83};
439 static const unsigned p168_dfio_pin1[] = {GPIO0, GPIO1, GPIO2, GPIO3, 439 static const unsigned p168_dfio_pin1[] = {GPIO0, GPIO1, GPIO2, GPIO3,
440 GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, 440 GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12,
441 GPIO13, GPIO14, GPIO15}; 441 GPIO13, GPIO14, GPIO15};
442 static const unsigned p168_nand_pin1[] = {GPIO16, GPIO17, GPIO21, GPIO22, 442 static const unsigned p168_nand_pin1[] = {GPIO16, GPIO17, GPIO21, GPIO22,
443 GPIO24, GPIO26}; 443 GPIO24, GPIO26};
444 static const unsigned p168_smc_pin1[] = {GPIO23, GPIO25, GPIO29, GPIO35, 444 static const unsigned p168_smc_pin1[] = {GPIO23, GPIO25, GPIO29, GPIO35,
445 GPIO36}; 445 GPIO36};
446 static const unsigned p168_smccs0_pin1[] = {GPIO18}; 446 static const unsigned p168_smccs0_pin1[] = {GPIO18};
447 static const unsigned p168_smccs1_pin1[] = {GPIO34}; 447 static const unsigned p168_smccs1_pin1[] = {GPIO34};
448 static const unsigned p168_smcrdy_pin1[] = {GPIO28}; 448 static const unsigned p168_smcrdy_pin1[] = {GPIO28};
449 static const unsigned p168_ac97sysclk_pin1[] = {GPIO113}; 449 static const unsigned p168_ac97sysclk_pin1[] = {GPIO113};
450 static const unsigned p168_ac97_pin1[] = {GPIO114, GPIO115, GPIO117, GPIO118, 450 static const unsigned p168_ac97_pin1[] = {GPIO114, GPIO115, GPIO117, GPIO118,
451 GPIO119}; 451 GPIO119};
452 static const unsigned p168_cf_pin1[] = {GPIO19, GPIO20, GPIO23, GPIO25, 452 static const unsigned p168_cf_pin1[] = {GPIO19, GPIO20, GPIO23, GPIO25,
453 GPIO28, GPIO29, GPIO30, GPIO31, GPIO32, GPIO33, GPIO34, GPIO35, 453 GPIO28, GPIO29, GPIO30, GPIO31, GPIO32, GPIO33, GPIO34, GPIO35,
454 GPIO36}; 454 GPIO36};
455 static const unsigned p168_kpmkin_pin1[] = {GPIO109, GPIO110, GPIO121}; 455 static const unsigned p168_kpmkin_pin1[] = {GPIO109, GPIO110, GPIO121};
456 static const unsigned p168_kpmkout_pin1[] = {GPIO111, GPIO112}; 456 static const unsigned p168_kpmkout_pin1[] = {GPIO111, GPIO112};
457 static const unsigned p168_gpio86_pin1[] = {WAKEUP}; 457 static const unsigned p168_gpio86_pin1[] = {WAKEUP};
458 static const unsigned p168_gpio86_pin2[] = {GPIO86}; 458 static const unsigned p168_gpio86_pin2[] = {GPIO86};
459 static const unsigned p168_gpio87_pin1[] = {GPIO87}; 459 static const unsigned p168_gpio87_pin1[] = {GPIO87};
460 static const unsigned p168_gpio87_pin2[] = {PWR_SDA}; 460 static const unsigned p168_gpio87_pin2[] = {PWR_SDA};
461 static const unsigned p168_gpio88_pin1[] = {GPIO88}; 461 static const unsigned p168_gpio88_pin1[] = {GPIO88};
462 static const unsigned p168_gpio88_pin2[] = {PWR_SCL}; 462 static const unsigned p168_gpio88_pin2[] = {PWR_SCL};
463 463
464 static struct pxa3xx_pin_group pxa168_grps[] = { 464 static struct pxa3xx_pin_group pxa168_grps[] = {
465 GRP_168("uart1rx-1", UART1, p168_uart1rx_pin1), 465 GRP_168("uart1rx-1", UART1, p168_uart1rx_pin1),
466 GRP_168("uart1tx-1", UART1_TX, p168_uart1tx_pin1), 466 GRP_168("uart1tx-1", UART1_TX, p168_uart1tx_pin1),
467 GRP_168("uart3rx-1", UART3, p168_uart3rx_pin1), 467 GRP_168("uart3rx-1", UART3, p168_uart3rx_pin1),
468 GRP_168("uart3tx-1", UART3_TX, p168_uart3tx_pin1), 468 GRP_168("uart3tx-1", UART3_TX, p168_uart3tx_pin1),
469 GRP_168("ssp1rx-1", SSP1, p168_ssp1rx_pin1), 469 GRP_168("ssp1rx-1", SSP1, p168_ssp1rx_pin1),
470 GRP_168("ssp1tx-1", SSP1_TX, p168_ssp1tx_pin1), 470 GRP_168("ssp1tx-1", SSP1_TX, p168_ssp1tx_pin1),
471 GRP_168("ssp4rx-1", SSP4, p168_ssp4rx_pin1), 471 GRP_168("ssp4rx-1", SSP4, p168_ssp4rx_pin1),
472 GRP_168("ssp4tx-1", SSP4_TX, p168_ssp4tx_pin1), 472 GRP_168("ssp4tx-1", SSP4_TX, p168_ssp4tx_pin1),
473 GRP_168("ssp5rx-1", SSP5, p168_ssp5rx_pin1), 473 GRP_168("ssp5rx-1", SSP5, p168_ssp5rx_pin1),
474 GRP_168("ssp5tx-1", SSP5_TX, p168_ssp5tx_pin1), 474 GRP_168("ssp5tx-1", SSP5_TX, p168_ssp5tx_pin1),
475 GRP_168("jtag", JTAG, p168_jtag_pin1), 475 GRP_168("jtag", JTAG, p168_jtag_pin1),
476 GRP_168("wakeup", WAKEUP, p168_wakeup_pin1), 476 GRP_168("wakeup", WAKEUP, p168_wakeup_pin1),
477 GRP_168("i2c", I2C, p168_i2c_pin1), 477 GRP_168("i2c", I2C, p168_i2c_pin1),
478 GRP_168("pwri2c", PWRI2C, p168_pwri2c_pin1), 478 GRP_168("pwri2c", PWRI2C, p168_pwri2c_pin1),
479 GRP_168("mmc1 8p1", MMC1, p168_mmc1_pin1), 479 GRP_168("mmc1 8p1", MMC1, p168_mmc1_pin1),
480 GRP_168("mmc2 4p1", MMC2, p168_mmc2_data_pin1), 480 GRP_168("mmc2 4p1", MMC2, p168_mmc2_data_pin1),
481 GRP_168("mmc2 cmd1", MMC2_CMD, p168_mmc2_cmd_pin1), 481 GRP_168("mmc2 cmd1", MMC2_CMD, p168_mmc2_cmd_pin1),
482 GRP_168("mmc2 clk1", MMC2_CLK, p168_mmc2_clk_pin1), 482 GRP_168("mmc2 clk1", MMC2_CLK, p168_mmc2_clk_pin1),
483 GRP_168("mmc3 8p1", MMC3, p168_mmc3_data_pin1), 483 GRP_168("mmc3 8p1", MMC3, p168_mmc3_data_pin1),
484 GRP_168("mmc3 cmd1", MMC3_CMD, p168_mmc3_cmd_pin1), 484 GRP_168("mmc3 cmd1", MMC3_CMD, p168_mmc3_cmd_pin1),
485 GRP_168("mmc3 clk1", MMC3_CLK, p168_mmc3_clk_pin1), 485 GRP_168("mmc3 clk1", MMC3_CLK, p168_mmc3_clk_pin1),
486 GRP_168("eth", ETH, p168_eth_pin1), 486 GRP_168("eth", ETH, p168_eth_pin1),
487 GRP_168("eth rx", ETH_RX, p168_ethrx_pin1), 487 GRP_168("eth rx", ETH_RX, p168_ethrx_pin1),
488 GRP_168("eth tx", ETH_TX, p168_ethtx_pin1), 488 GRP_168("eth tx", ETH_TX, p168_ethtx_pin1),
489 GRP_168("msp", MSP, p168_msp_pin1), 489 GRP_168("msp", MSP, p168_msp_pin1),
490 GRP_168("ccic", CCIC, p168_ccic_pin1), 490 GRP_168("ccic", CCIC, p168_ccic_pin1),
491 GRP_168("xd", XD, p168_xd_pin1), 491 GRP_168("xd", XD, p168_xd_pin1),
492 GRP_168("lcd", LCD, p168_lcd_pin1), 492 GRP_168("lcd", LCD, p168_lcd_pin1),
493 GRP_168("dfio", DFIO, p168_dfio_pin1), 493 GRP_168("dfio", DFIO, p168_dfio_pin1),
494 GRP_168("nand", NAND, p168_nand_pin1), 494 GRP_168("nand", NAND, p168_nand_pin1),
495 GRP_168("smc", SMC, p168_smc_pin1), 495 GRP_168("smc", SMC, p168_smc_pin1),
496 GRP_168("smc cs0", SMC_CS0, p168_smccs0_pin1), 496 GRP_168("smc cs0", SMC_CS0, p168_smccs0_pin1),
497 GRP_168("smc cs1", SMC_CS1, p168_smccs1_pin1), 497 GRP_168("smc cs1", SMC_CS1, p168_smccs1_pin1),
498 GRP_168("smc rdy", SMC_RDY, p168_smcrdy_pin1), 498 GRP_168("smc rdy", SMC_RDY, p168_smcrdy_pin1),
499 GRP_168("ac97 sysclk", AC97_SYSCLK, p168_ac97sysclk_pin1), 499 GRP_168("ac97 sysclk", AC97_SYSCLK, p168_ac97sysclk_pin1),
500 GRP_168("ac97", AC97, p168_ac97_pin1), 500 GRP_168("ac97", AC97, p168_ac97_pin1),
501 GRP_168("cf", CF, p168_cf_pin1), 501 GRP_168("cf", CF, p168_cf_pin1),
502 GRP_168("kp mkin 3p1", KP_MKIN, p168_kpmkin_pin1), 502 GRP_168("kp mkin 3p1", KP_MKIN, p168_kpmkin_pin1),
503 GRP_168("kp mkout 2p1", KP_MKOUT, p168_kpmkout_pin1), 503 GRP_168("kp mkout 2p1", KP_MKOUT, p168_kpmkout_pin1),
504 GRP_168("gpio86-1", GPIO, p168_gpio86_pin1), 504 GRP_168("gpio86-1", GPIO, p168_gpio86_pin1),
505 GRP_168("gpio86-2", GPIO, p168_gpio86_pin2), 505 GRP_168("gpio86-2", GPIO, p168_gpio86_pin2),
506 GRP_168("gpio87-1", GPIO, p168_gpio87_pin1), 506 GRP_168("gpio87-1", GPIO, p168_gpio87_pin1),
507 GRP_168("gpio87-2", GPIO, p168_gpio87_pin2), 507 GRP_168("gpio87-2", GPIO, p168_gpio87_pin2),
508 GRP_168("gpio88-1", GPIO, p168_gpio88_pin1), 508 GRP_168("gpio88-1", GPIO, p168_gpio88_pin1),
509 GRP_168("gpio88-2", GPIO, p168_gpio88_pin2), 509 GRP_168("gpio88-2", GPIO, p168_gpio88_pin2),
510 }; 510 };
511 511
512 static const char * const p168_uart1rx_grps[] = {"uart1rx-1"}; 512 static const char * const p168_uart1rx_grps[] = {"uart1rx-1"};
513 static const char * const p168_uart1tx_grps[] = {"uart1tx-1"}; 513 static const char * const p168_uart1tx_grps[] = {"uart1tx-1"};
514 static const char * const p168_uart3rx_grps[] = {"uart3rx-1"}; 514 static const char * const p168_uart3rx_grps[] = {"uart3rx-1"};
515 static const char * const p168_uart3tx_grps[] = {"uart3tx-1"}; 515 static const char * const p168_uart3tx_grps[] = {"uart3tx-1"};
516 static const char * const p168_ssp1rx_grps[] = {"ssp1rx-1"}; 516 static const char * const p168_ssp1rx_grps[] = {"ssp1rx-1"};
517 static const char * const p168_ssp1tx_grps[] = {"ssp1tx-1"}; 517 static const char * const p168_ssp1tx_grps[] = {"ssp1tx-1"};
518 static const char * const p168_ssp4rx_grps[] = {"ssp4rx-1"}; 518 static const char * const p168_ssp4rx_grps[] = {"ssp4rx-1"};
519 static const char * const p168_ssp4tx_grps[] = {"ssp4tx-1"}; 519 static const char * const p168_ssp4tx_grps[] = {"ssp4tx-1"};
520 static const char * const p168_ssp5rx_grps[] = {"ssp5rx-1"}; 520 static const char * const p168_ssp5rx_grps[] = {"ssp5rx-1"};
521 static const char * const p168_ssp5tx_grps[] = {"ssp5tx-1"}; 521 static const char * const p168_ssp5tx_grps[] = {"ssp5tx-1"};
522 static const char * const p168_i2c_grps[] = {"i2c"}; 522 static const char * const p168_i2c_grps[] = {"i2c"};
523 static const char * const p168_pwri2c_grps[] = {"pwri2c"}; 523 static const char * const p168_pwri2c_grps[] = {"pwri2c"};
524 static const char * const p168_mmc1_grps[] = {"mmc1 8p1"}; 524 static const char * const p168_mmc1_grps[] = {"mmc1 8p1"};
525 static const char * const p168_mmc2_data_grps[] = {"mmc2 4p1"}; 525 static const char * const p168_mmc2_data_grps[] = {"mmc2 4p1"};
526 static const char * const p168_mmc2_cmd_grps[] = {"mmc2 cmd1"}; 526 static const char * const p168_mmc2_cmd_grps[] = {"mmc2 cmd1"};
527 static const char * const p168_mmc2_clk_grps[] = {"mmc2 clk1"}; 527 static const char * const p168_mmc2_clk_grps[] = {"mmc2 clk1"};
528 static const char * const p168_mmc3_data_grps[] = {"mmc3 8p1"}; 528 static const char * const p168_mmc3_data_grps[] = {"mmc3 8p1"};
529 static const char * const p168_mmc3_cmd_grps[] = {"mmc3 cmd1"}; 529 static const char * const p168_mmc3_cmd_grps[] = {"mmc3 cmd1"};
530 static const char * const p168_mmc3_clk_grps[] = {"mmc3 clk1"}; 530 static const char * const p168_mmc3_clk_grps[] = {"mmc3 clk1"};
531 static const char * const p168_eth_grps[] = {"eth"}; 531 static const char * const p168_eth_grps[] = {"eth"};
532 static const char * const p168_ethrx_grps[] = {"eth rx"}; 532 static const char * const p168_ethrx_grps[] = {"eth rx"};
533 static const char * const p168_ethtx_grps[] = {"eth tx"}; 533 static const char * const p168_ethtx_grps[] = {"eth tx"};
534 static const char * const p168_msp_grps[] = {"msp"}; 534 static const char * const p168_msp_grps[] = {"msp"};
535 static const char * const p168_ccic_grps[] = {"ccic"}; 535 static const char * const p168_ccic_grps[] = {"ccic"};
536 static const char * const p168_xd_grps[] = {"xd"}; 536 static const char * const p168_xd_grps[] = {"xd"};
537 static const char * const p168_lcd_grps[] = {"lcd"}; 537 static const char * const p168_lcd_grps[] = {"lcd"};
538 static const char * const p168_dfio_grps[] = {"dfio"}; 538 static const char * const p168_dfio_grps[] = {"dfio"};
539 static const char * const p168_nand_grps[] = {"nand"}; 539 static const char * const p168_nand_grps[] = {"nand"};
540 static const char * const p168_smc_grps[] = {"smc"}; 540 static const char * const p168_smc_grps[] = {"smc"};
541 static const char * const p168_smccs0_grps[] = {"smc cs0"}; 541 static const char * const p168_smccs0_grps[] = {"smc cs0"};
542 static const char * const p168_smccs1_grps[] = {"smc cs1"}; 542 static const char * const p168_smccs1_grps[] = {"smc cs1"};
543 static const char * const p168_smcrdy_grps[] = {"smc rdy"}; 543 static const char * const p168_smcrdy_grps[] = {"smc rdy"};
544 static const char * const p168_ac97sysclk_grps[] = {"ac97 sysclk"}; 544 static const char * const p168_ac97sysclk_grps[] = {"ac97 sysclk"};
545 static const char * const p168_ac97_grps[] = {"ac97"}; 545 static const char * const p168_ac97_grps[] = {"ac97"};
546 static const char * const p168_cf_grps[] = {"cf"}; 546 static const char * const p168_cf_grps[] = {"cf"};
547 static const char * const p168_kpmkin_grps[] = {"kp mkin 3p1"}; 547 static const char * const p168_kpmkin_grps[] = {"kp mkin 3p1"};
548 static const char * const p168_kpmkout_grps[] = {"kp mkout 2p1"}; 548 static const char * const p168_kpmkout_grps[] = {"kp mkout 2p1"};
549 static const char * const p168_gpio86_grps[] = {"gpio86-1", "gpio86-2"}; 549 static const char * const p168_gpio86_grps[] = {"gpio86-1", "gpio86-2"};
550 static const char * const p168_gpio87_grps[] = {"gpio87-1", "gpio87-2"}; 550 static const char * const p168_gpio87_grps[] = {"gpio87-1", "gpio87-2"};
551 static const char * const p168_gpio88_grps[] = {"gpio88-1", "gpio88-2"}; 551 static const char * const p168_gpio88_grps[] = {"gpio88-1", "gpio88-2"};
552 552
553 static struct pxa3xx_pmx_func pxa168_funcs[] = { 553 static struct pxa3xx_pmx_func pxa168_funcs[] = {
554 {"uart1 rx", ARRAY_AND_SIZE(p168_uart1rx_grps)}, 554 {"uart1 rx", ARRAY_AND_SIZE(p168_uart1rx_grps)},
555 {"uart1 tx", ARRAY_AND_SIZE(p168_uart1tx_grps)}, 555 {"uart1 tx", ARRAY_AND_SIZE(p168_uart1tx_grps)},
556 {"uart3 rx", ARRAY_AND_SIZE(p168_uart3rx_grps)}, 556 {"uart3 rx", ARRAY_AND_SIZE(p168_uart3rx_grps)},
557 {"uart3 tx", ARRAY_AND_SIZE(p168_uart3tx_grps)}, 557 {"uart3 tx", ARRAY_AND_SIZE(p168_uart3tx_grps)},
558 {"ssp1 rx", ARRAY_AND_SIZE(p168_ssp1rx_grps)}, 558 {"ssp1 rx", ARRAY_AND_SIZE(p168_ssp1rx_grps)},
559 {"ssp1 tx", ARRAY_AND_SIZE(p168_ssp1tx_grps)}, 559 {"ssp1 tx", ARRAY_AND_SIZE(p168_ssp1tx_grps)},
560 {"ssp4 rx", ARRAY_AND_SIZE(p168_ssp4rx_grps)}, 560 {"ssp4 rx", ARRAY_AND_SIZE(p168_ssp4rx_grps)},
561 {"ssp4 tx", ARRAY_AND_SIZE(p168_ssp4tx_grps)}, 561 {"ssp4 tx", ARRAY_AND_SIZE(p168_ssp4tx_grps)},
562 {"ssp5 rx", ARRAY_AND_SIZE(p168_ssp5rx_grps)}, 562 {"ssp5 rx", ARRAY_AND_SIZE(p168_ssp5rx_grps)},
563 {"ssp5 tx", ARRAY_AND_SIZE(p168_ssp5tx_grps)}, 563 {"ssp5 tx", ARRAY_AND_SIZE(p168_ssp5tx_grps)},
564 {"i2c", ARRAY_AND_SIZE(p168_i2c_grps)}, 564 {"i2c", ARRAY_AND_SIZE(p168_i2c_grps)},
565 {"pwri2c", ARRAY_AND_SIZE(p168_pwri2c_grps)}, 565 {"pwri2c", ARRAY_AND_SIZE(p168_pwri2c_grps)},
566 {"mmc1", ARRAY_AND_SIZE(p168_mmc1_grps)}, 566 {"mmc1", ARRAY_AND_SIZE(p168_mmc1_grps)},
567 {"mmc2", ARRAY_AND_SIZE(p168_mmc2_data_grps)}, 567 {"mmc2", ARRAY_AND_SIZE(p168_mmc2_data_grps)},
568 {"mmc2 cmd", ARRAY_AND_SIZE(p168_mmc2_cmd_grps)}, 568 {"mmc2 cmd", ARRAY_AND_SIZE(p168_mmc2_cmd_grps)},
569 {"mmc2 clk", ARRAY_AND_SIZE(p168_mmc2_clk_grps)}, 569 {"mmc2 clk", ARRAY_AND_SIZE(p168_mmc2_clk_grps)},
570 {"mmc3", ARRAY_AND_SIZE(p168_mmc3_data_grps)}, 570 {"mmc3", ARRAY_AND_SIZE(p168_mmc3_data_grps)},
571 {"mmc3 cmd", ARRAY_AND_SIZE(p168_mmc3_cmd_grps)}, 571 {"mmc3 cmd", ARRAY_AND_SIZE(p168_mmc3_cmd_grps)},
572 {"mmc3 clk", ARRAY_AND_SIZE(p168_mmc3_clk_grps)}, 572 {"mmc3 clk", ARRAY_AND_SIZE(p168_mmc3_clk_grps)},
573 {"eth", ARRAY_AND_SIZE(p168_eth_grps)}, 573 {"eth", ARRAY_AND_SIZE(p168_eth_grps)},
574 {"eth rx", ARRAY_AND_SIZE(p168_ethrx_grps)}, 574 {"eth rx", ARRAY_AND_SIZE(p168_ethrx_grps)},
575 {"eth tx", ARRAY_AND_SIZE(p168_ethtx_grps)}, 575 {"eth tx", ARRAY_AND_SIZE(p168_ethtx_grps)},
576 {"msp", ARRAY_AND_SIZE(p168_msp_grps)}, 576 {"msp", ARRAY_AND_SIZE(p168_msp_grps)},
577 {"ccic", ARRAY_AND_SIZE(p168_ccic_grps)}, 577 {"ccic", ARRAY_AND_SIZE(p168_ccic_grps)},
578 {"xd", ARRAY_AND_SIZE(p168_xd_grps)}, 578 {"xd", ARRAY_AND_SIZE(p168_xd_grps)},
579 {"lcd", ARRAY_AND_SIZE(p168_lcd_grps)}, 579 {"lcd", ARRAY_AND_SIZE(p168_lcd_grps)},
580 {"dfio", ARRAY_AND_SIZE(p168_dfio_grps)}, 580 {"dfio", ARRAY_AND_SIZE(p168_dfio_grps)},
581 {"nand", ARRAY_AND_SIZE(p168_nand_grps)}, 581 {"nand", ARRAY_AND_SIZE(p168_nand_grps)},
582 {"smc", ARRAY_AND_SIZE(p168_smc_grps)}, 582 {"smc", ARRAY_AND_SIZE(p168_smc_grps)},
583 {"smc cs0", ARRAY_AND_SIZE(p168_smccs0_grps)}, 583 {"smc cs0", ARRAY_AND_SIZE(p168_smccs0_grps)},
584 {"smc cs1", ARRAY_AND_SIZE(p168_smccs1_grps)}, 584 {"smc cs1", ARRAY_AND_SIZE(p168_smccs1_grps)},
585 {"smc rdy", ARRAY_AND_SIZE(p168_smcrdy_grps)}, 585 {"smc rdy", ARRAY_AND_SIZE(p168_smcrdy_grps)},
586 {"ac97", ARRAY_AND_SIZE(p168_ac97_grps)}, 586 {"ac97", ARRAY_AND_SIZE(p168_ac97_grps)},
587 {"ac97 sysclk", ARRAY_AND_SIZE(p168_ac97sysclk_grps)}, 587 {"ac97 sysclk", ARRAY_AND_SIZE(p168_ac97sysclk_grps)},
588 {"cf", ARRAY_AND_SIZE(p168_cf_grps)}, 588 {"cf", ARRAY_AND_SIZE(p168_cf_grps)},
589 {"kpmkin", ARRAY_AND_SIZE(p168_kpmkin_grps)}, 589 {"kpmkin", ARRAY_AND_SIZE(p168_kpmkin_grps)},
590 {"kpmkout", ARRAY_AND_SIZE(p168_kpmkout_grps)}, 590 {"kpmkout", ARRAY_AND_SIZE(p168_kpmkout_grps)},
591 {"gpio86", ARRAY_AND_SIZE(p168_gpio86_grps)}, 591 {"gpio86", ARRAY_AND_SIZE(p168_gpio86_grps)},
592 {"gpio87", ARRAY_AND_SIZE(p168_gpio87_grps)}, 592 {"gpio87", ARRAY_AND_SIZE(p168_gpio87_grps)},
593 {"gpio88", ARRAY_AND_SIZE(p168_gpio88_grps)}, 593 {"gpio88", ARRAY_AND_SIZE(p168_gpio88_grps)},
594 }; 594 };
595 595
596 static struct pinctrl_desc pxa168_pctrl_desc = { 596 static struct pinctrl_desc pxa168_pctrl_desc = {
597 .name = "pxa168-pinctrl", 597 .name = "pxa168-pinctrl",
598 .owner = THIS_MODULE, 598 .owner = THIS_MODULE,
599 }; 599 };
600 600
601 static struct pxa3xx_pinmux_info pxa168_info = { 601 static struct pxa3xx_pinmux_info pxa168_info = {
602 .mfp = pxa168_mfp, 602 .mfp = pxa168_mfp,
603 .num_mfp = ARRAY_SIZE(pxa168_mfp), 603 .num_mfp = ARRAY_SIZE(pxa168_mfp),
604 .grps = pxa168_grps, 604 .grps = pxa168_grps,
605 .num_grps = ARRAY_SIZE(pxa168_grps), 605 .num_grps = ARRAY_SIZE(pxa168_grps),
606 .funcs = pxa168_funcs, 606 .funcs = pxa168_funcs,
607 .num_funcs = ARRAY_SIZE(pxa168_funcs), 607 .num_funcs = ARRAY_SIZE(pxa168_funcs),
608 .num_gpio = 128, 608 .num_gpio = 128,
609 .desc = &pxa168_pctrl_desc, 609 .desc = &pxa168_pctrl_desc,
610 .pads = pxa168_pads, 610 .pads = pxa168_pads,
611 .num_pads = ARRAY_SIZE(pxa168_pads), 611 .num_pads = ARRAY_SIZE(pxa168_pads),
612 612
613 .cputype = PINCTRL_PXA168, 613 .cputype = PINCTRL_PXA168,
614 .ds_mask = PXA168_DS_MASK, 614 .ds_mask = PXA168_DS_MASK,
615 .ds_shift = PXA168_DS_SHIFT, 615 .ds_shift = PXA168_DS_SHIFT,
616 }; 616 };
617 617
618 static int __devinit pxa168_pinmux_probe(struct platform_device *pdev) 618 static int __devinit pxa168_pinmux_probe(struct platform_device *pdev)
619 { 619 {
620 return pxa3xx_pinctrl_register(pdev, &pxa168_info); 620 return pxa3xx_pinctrl_register(pdev, &pxa168_info);
621 } 621 }
622 622
623 static int __devexit pxa168_pinmux_remove(struct platform_device *pdev) 623 static int pxa168_pinmux_remove(struct platform_device *pdev)
624 { 624 {
625 return pxa3xx_pinctrl_unregister(pdev); 625 return pxa3xx_pinctrl_unregister(pdev);
626 } 626 }
627 627
628 static struct platform_driver pxa168_pinmux_driver = { 628 static struct platform_driver pxa168_pinmux_driver = {
629 .driver = { 629 .driver = {
630 .name = "pxa168-pinmux", 630 .name = "pxa168-pinmux",
631 .owner = THIS_MODULE, 631 .owner = THIS_MODULE,
632 }, 632 },
633 .probe = pxa168_pinmux_probe, 633 .probe = pxa168_pinmux_probe,
634 .remove = pxa168_pinmux_remove, 634 .remove = pxa168_pinmux_remove,
635 }; 635 };
636 636
637 static int __init pxa168_pinmux_init(void) 637 static int __init pxa168_pinmux_init(void)
638 { 638 {
639 return platform_driver_register(&pxa168_pinmux_driver); 639 return platform_driver_register(&pxa168_pinmux_driver);
640 } 640 }
641 core_initcall_sync(pxa168_pinmux_init); 641 core_initcall_sync(pxa168_pinmux_init);
642 642
643 static void __exit pxa168_pinmux_exit(void) 643 static void __exit pxa168_pinmux_exit(void)
644 { 644 {
645 platform_driver_unregister(&pxa168_pinmux_driver); 645 platform_driver_unregister(&pxa168_pinmux_driver);
646 } 646 }
647 module_exit(pxa168_pinmux_exit); 647 module_exit(pxa168_pinmux_exit);
648 648
649 MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com>"); 649 MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com>");
650 MODULE_DESCRIPTION("PXA3xx pin control driver"); 650 MODULE_DESCRIPTION("PXA3xx pin control driver");
651 MODULE_LICENSE("GPL v2"); 651 MODULE_LICENSE("GPL v2");
652 652
drivers/pinctrl/pinctrl-pxa910.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * linux/drivers/pinctrl/pinmux-pxa910.c 2 * linux/drivers/pinctrl/pinmux-pxa910.c
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * publishhed by the Free Software Foundation. 6 * publishhed by the Free Software Foundation.
7 * 7 *
8 * Copyright (C) 2011, Marvell Technology Group Ltd. 8 * Copyright (C) 2011, Marvell Technology Group Ltd.
9 * 9 *
10 * Author: Haojian Zhuang <haojian.zhuang@marvell.com> 10 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
11 * 11 *
12 */ 12 */
13 13
14 #include <linux/device.h> 14 #include <linux/device.h>
15 #include <linux/module.h> 15 #include <linux/module.h>
16 #include <linux/io.h> 16 #include <linux/io.h>
17 #include <linux/platform_device.h> 17 #include <linux/platform_device.h>
18 #include "pinctrl-pxa3xx.h" 18 #include "pinctrl-pxa3xx.h"
19 19
20 #define PXA910_DS_MASK 0x1800 20 #define PXA910_DS_MASK 0x1800
21 #define PXA910_DS_SHIFT 11 21 #define PXA910_DS_SHIFT 11
22 #define PXA910_SLEEP_MASK 0x38 22 #define PXA910_SLEEP_MASK 0x38
23 #define PXA910_SLEEP_SELECT (1 << 9) 23 #define PXA910_SLEEP_SELECT (1 << 9)
24 #define PXA910_SLEEP_DATA (1 << 8) 24 #define PXA910_SLEEP_DATA (1 << 8)
25 #define PXA910_SLEEP_DIR (1 << 7) 25 #define PXA910_SLEEP_DIR (1 << 7)
26 26
27 #define MFPR_910(a, r, f0, f1, f2, f3, f4, f5, f6, f7) \ 27 #define MFPR_910(a, r, f0, f1, f2, f3, f4, f5, f6, f7) \
28 { \ 28 { \
29 .name = #a, \ 29 .name = #a, \
30 .pin = a, \ 30 .pin = a, \
31 .mfpr = r, \ 31 .mfpr = r, \
32 .func = { \ 32 .func = { \
33 PXA910_MUX_##f0, \ 33 PXA910_MUX_##f0, \
34 PXA910_MUX_##f1, \ 34 PXA910_MUX_##f1, \
35 PXA910_MUX_##f2, \ 35 PXA910_MUX_##f2, \
36 PXA910_MUX_##f3, \ 36 PXA910_MUX_##f3, \
37 PXA910_MUX_##f4, \ 37 PXA910_MUX_##f4, \
38 PXA910_MUX_##f5, \ 38 PXA910_MUX_##f5, \
39 PXA910_MUX_##f6, \ 39 PXA910_MUX_##f6, \
40 PXA910_MUX_##f7, \ 40 PXA910_MUX_##f7, \
41 }, \ 41 }, \
42 } 42 }
43 43
44 #define GRP_910(a, m, p) \ 44 #define GRP_910(a, m, p) \
45 { .name = a, .mux = PXA910_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), } 45 { .name = a, .mux = PXA910_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
46 46
47 /* 170 pins */ 47 /* 170 pins */
48 enum pxa910_pin_list { 48 enum pxa910_pin_list {
49 /* 0~127: GPIO0~GPIO127 */ 49 /* 0~127: GPIO0~GPIO127 */
50 ND_IO15 = 128, 50 ND_IO15 = 128,
51 ND_IO14, 51 ND_IO14,
52 ND_IO13, /* 130 */ 52 ND_IO13, /* 130 */
53 ND_IO12, 53 ND_IO12,
54 ND_IO11, 54 ND_IO11,
55 ND_IO10, 55 ND_IO10,
56 ND_IO9, 56 ND_IO9,
57 ND_IO8, 57 ND_IO8,
58 ND_IO7, 58 ND_IO7,
59 ND_IO6, 59 ND_IO6,
60 ND_IO5, 60 ND_IO5,
61 ND_IO4, 61 ND_IO4,
62 ND_IO3, /* 140 */ 62 ND_IO3, /* 140 */
63 ND_IO2, 63 ND_IO2,
64 ND_IO1, 64 ND_IO1,
65 ND_IO0, 65 ND_IO0,
66 ND_NCS0, 66 ND_NCS0,
67 ND_NCS1, 67 ND_NCS1,
68 SM_NCS0, 68 SM_NCS0,
69 SM_NCS1, 69 SM_NCS1,
70 ND_NWE, 70 ND_NWE,
71 ND_NRE, 71 ND_NRE,
72 ND_CLE, /* 150 */ 72 ND_CLE, /* 150 */
73 ND_ALE, 73 ND_ALE,
74 SM_SCLK, 74 SM_SCLK,
75 ND_RDY0, 75 ND_RDY0,
76 SM_ADV, 76 SM_ADV,
77 ND_RDY1, 77 ND_RDY1,
78 SM_ADVMUX, 78 SM_ADVMUX,
79 SM_RDY, 79 SM_RDY,
80 MMC1_DAT7, 80 MMC1_DAT7,
81 MMC1_DAT6, 81 MMC1_DAT6,
82 MMC1_DAT5, /* 160 */ 82 MMC1_DAT5, /* 160 */
83 MMC1_DAT4, 83 MMC1_DAT4,
84 MMC1_DAT3, 84 MMC1_DAT3,
85 MMC1_DAT2, 85 MMC1_DAT2,
86 MMC1_DAT1, 86 MMC1_DAT1,
87 MMC1_DAT0, 87 MMC1_DAT0,
88 MMC1_CMD, 88 MMC1_CMD,
89 MMC1_CLK, 89 MMC1_CLK,
90 MMC1_CD, 90 MMC1_CD,
91 VCXO_OUT, 91 VCXO_OUT,
92 }; 92 };
93 93
94 enum pxa910_mux { 94 enum pxa910_mux {
95 /* PXA3xx_MUX_GPIO = 0 (predefined in pinctrl-pxa3xx.h) */ 95 /* PXA3xx_MUX_GPIO = 0 (predefined in pinctrl-pxa3xx.h) */
96 PXA910_MUX_GPIO = 0, 96 PXA910_MUX_GPIO = 0,
97 PXA910_MUX_NAND, 97 PXA910_MUX_NAND,
98 PXA910_MUX_USIM2, 98 PXA910_MUX_USIM2,
99 PXA910_MUX_EXT_DMA, 99 PXA910_MUX_EXT_DMA,
100 PXA910_MUX_EXT_INT, 100 PXA910_MUX_EXT_INT,
101 PXA910_MUX_MMC1, 101 PXA910_MUX_MMC1,
102 PXA910_MUX_MMC2, 102 PXA910_MUX_MMC2,
103 PXA910_MUX_MMC3, 103 PXA910_MUX_MMC3,
104 PXA910_MUX_SM_INT, 104 PXA910_MUX_SM_INT,
105 PXA910_MUX_PRI_JTAG, 105 PXA910_MUX_PRI_JTAG,
106 PXA910_MUX_SEC1_JTAG, 106 PXA910_MUX_SEC1_JTAG,
107 PXA910_MUX_SEC2_JTAG, 107 PXA910_MUX_SEC2_JTAG,
108 PXA910_MUX_RESET, /* SLAVE RESET OUT */ 108 PXA910_MUX_RESET, /* SLAVE RESET OUT */
109 PXA910_MUX_CLK_REQ, 109 PXA910_MUX_CLK_REQ,
110 PXA910_MUX_VCXO_REQ, 110 PXA910_MUX_VCXO_REQ,
111 PXA910_MUX_VCXO_OUT, 111 PXA910_MUX_VCXO_OUT,
112 PXA910_MUX_VCXO_REQ2, 112 PXA910_MUX_VCXO_REQ2,
113 PXA910_MUX_VCXO_OUT2, 113 PXA910_MUX_VCXO_OUT2,
114 PXA910_MUX_SPI, 114 PXA910_MUX_SPI,
115 PXA910_MUX_SPI2, 115 PXA910_MUX_SPI2,
116 PXA910_MUX_GSSP, 116 PXA910_MUX_GSSP,
117 PXA910_MUX_SSP0, 117 PXA910_MUX_SSP0,
118 PXA910_MUX_SSP1, 118 PXA910_MUX_SSP1,
119 PXA910_MUX_SSP2, 119 PXA910_MUX_SSP2,
120 PXA910_MUX_DSSP2, 120 PXA910_MUX_DSSP2,
121 PXA910_MUX_DSSP3, 121 PXA910_MUX_DSSP3,
122 PXA910_MUX_UART0, 122 PXA910_MUX_UART0,
123 PXA910_MUX_UART1, 123 PXA910_MUX_UART1,
124 PXA910_MUX_UART2, 124 PXA910_MUX_UART2,
125 PXA910_MUX_TWSI, 125 PXA910_MUX_TWSI,
126 PXA910_MUX_CCIC, 126 PXA910_MUX_CCIC,
127 PXA910_MUX_PWM0, 127 PXA910_MUX_PWM0,
128 PXA910_MUX_PWM1, 128 PXA910_MUX_PWM1,
129 PXA910_MUX_PWM2, 129 PXA910_MUX_PWM2,
130 PXA910_MUX_PWM3, 130 PXA910_MUX_PWM3,
131 PXA910_MUX_HSL, 131 PXA910_MUX_HSL,
132 PXA910_MUX_ONE_WIRE, 132 PXA910_MUX_ONE_WIRE,
133 PXA910_MUX_LCD, 133 PXA910_MUX_LCD,
134 PXA910_MUX_DAC_ST23, 134 PXA910_MUX_DAC_ST23,
135 PXA910_MUX_ULPI, 135 PXA910_MUX_ULPI,
136 PXA910_MUX_TB, 136 PXA910_MUX_TB,
137 PXA910_MUX_KP_MK, 137 PXA910_MUX_KP_MK,
138 PXA910_MUX_KP_DK, 138 PXA910_MUX_KP_DK,
139 PXA910_MUX_TCU_GPOA, 139 PXA910_MUX_TCU_GPOA,
140 PXA910_MUX_TCU_GPOB, 140 PXA910_MUX_TCU_GPOB,
141 PXA910_MUX_ROT, 141 PXA910_MUX_ROT,
142 PXA910_MUX_TDS, 142 PXA910_MUX_TDS,
143 PXA910_MUX_32K_CLK, /* 32KHz CLK OUT */ 143 PXA910_MUX_32K_CLK, /* 32KHz CLK OUT */
144 PXA910_MUX_MN_CLK, /* MN CLK OUT */ 144 PXA910_MUX_MN_CLK, /* MN CLK OUT */
145 PXA910_MUX_SMC, 145 PXA910_MUX_SMC,
146 PXA910_MUX_SM_ADDR18, 146 PXA910_MUX_SM_ADDR18,
147 PXA910_MUX_SM_ADDR19, 147 PXA910_MUX_SM_ADDR19,
148 PXA910_MUX_SM_ADDR20, 148 PXA910_MUX_SM_ADDR20,
149 PXA910_MUX_NONE = 0xffff, 149 PXA910_MUX_NONE = 0xffff,
150 }; 150 };
151 151
152 152
153 static struct pinctrl_pin_desc pxa910_pads[] = { 153 static struct pinctrl_pin_desc pxa910_pads[] = {
154 PINCTRL_PIN(GPIO0, "GPIO0"), 154 PINCTRL_PIN(GPIO0, "GPIO0"),
155 PINCTRL_PIN(GPIO1, "GPIO1"), 155 PINCTRL_PIN(GPIO1, "GPIO1"),
156 PINCTRL_PIN(GPIO2, "GPIO2"), 156 PINCTRL_PIN(GPIO2, "GPIO2"),
157 PINCTRL_PIN(GPIO3, "GPIO3"), 157 PINCTRL_PIN(GPIO3, "GPIO3"),
158 PINCTRL_PIN(GPIO4, "GPIO4"), 158 PINCTRL_PIN(GPIO4, "GPIO4"),
159 PINCTRL_PIN(GPIO5, "GPIO5"), 159 PINCTRL_PIN(GPIO5, "GPIO5"),
160 PINCTRL_PIN(GPIO6, "GPIO6"), 160 PINCTRL_PIN(GPIO6, "GPIO6"),
161 PINCTRL_PIN(GPIO7, "GPIO7"), 161 PINCTRL_PIN(GPIO7, "GPIO7"),
162 PINCTRL_PIN(GPIO8, "GPIO8"), 162 PINCTRL_PIN(GPIO8, "GPIO8"),
163 PINCTRL_PIN(GPIO9, "GPIO9"), 163 PINCTRL_PIN(GPIO9, "GPIO9"),
164 PINCTRL_PIN(GPIO10, "GPIO10"), 164 PINCTRL_PIN(GPIO10, "GPIO10"),
165 PINCTRL_PIN(GPIO11, "GPIO11"), 165 PINCTRL_PIN(GPIO11, "GPIO11"),
166 PINCTRL_PIN(GPIO12, "GPIO12"), 166 PINCTRL_PIN(GPIO12, "GPIO12"),
167 PINCTRL_PIN(GPIO13, "GPIO13"), 167 PINCTRL_PIN(GPIO13, "GPIO13"),
168 PINCTRL_PIN(GPIO14, "GPIO14"), 168 PINCTRL_PIN(GPIO14, "GPIO14"),
169 PINCTRL_PIN(GPIO15, "GPIO15"), 169 PINCTRL_PIN(GPIO15, "GPIO15"),
170 PINCTRL_PIN(GPIO16, "GPIO16"), 170 PINCTRL_PIN(GPIO16, "GPIO16"),
171 PINCTRL_PIN(GPIO17, "GPIO17"), 171 PINCTRL_PIN(GPIO17, "GPIO17"),
172 PINCTRL_PIN(GPIO18, "GPIO18"), 172 PINCTRL_PIN(GPIO18, "GPIO18"),
173 PINCTRL_PIN(GPIO19, "GPIO19"), 173 PINCTRL_PIN(GPIO19, "GPIO19"),
174 PINCTRL_PIN(GPIO20, "GPIO20"), 174 PINCTRL_PIN(GPIO20, "GPIO20"),
175 PINCTRL_PIN(GPIO21, "GPIO21"), 175 PINCTRL_PIN(GPIO21, "GPIO21"),
176 PINCTRL_PIN(GPIO22, "GPIO22"), 176 PINCTRL_PIN(GPIO22, "GPIO22"),
177 PINCTRL_PIN(GPIO23, "GPIO23"), 177 PINCTRL_PIN(GPIO23, "GPIO23"),
178 PINCTRL_PIN(GPIO24, "GPIO24"), 178 PINCTRL_PIN(GPIO24, "GPIO24"),
179 PINCTRL_PIN(GPIO25, "GPIO25"), 179 PINCTRL_PIN(GPIO25, "GPIO25"),
180 PINCTRL_PIN(GPIO26, "GPIO26"), 180 PINCTRL_PIN(GPIO26, "GPIO26"),
181 PINCTRL_PIN(GPIO27, "GPIO27"), 181 PINCTRL_PIN(GPIO27, "GPIO27"),
182 PINCTRL_PIN(GPIO28, "GPIO28"), 182 PINCTRL_PIN(GPIO28, "GPIO28"),
183 PINCTRL_PIN(GPIO29, "GPIO29"), 183 PINCTRL_PIN(GPIO29, "GPIO29"),
184 PINCTRL_PIN(GPIO30, "GPIO30"), 184 PINCTRL_PIN(GPIO30, "GPIO30"),
185 PINCTRL_PIN(GPIO31, "GPIO31"), 185 PINCTRL_PIN(GPIO31, "GPIO31"),
186 PINCTRL_PIN(GPIO32, "GPIO32"), 186 PINCTRL_PIN(GPIO32, "GPIO32"),
187 PINCTRL_PIN(GPIO33, "GPIO33"), 187 PINCTRL_PIN(GPIO33, "GPIO33"),
188 PINCTRL_PIN(GPIO34, "GPIO34"), 188 PINCTRL_PIN(GPIO34, "GPIO34"),
189 PINCTRL_PIN(GPIO35, "GPIO35"), 189 PINCTRL_PIN(GPIO35, "GPIO35"),
190 PINCTRL_PIN(GPIO36, "GPIO36"), 190 PINCTRL_PIN(GPIO36, "GPIO36"),
191 PINCTRL_PIN(GPIO37, "GPIO37"), 191 PINCTRL_PIN(GPIO37, "GPIO37"),
192 PINCTRL_PIN(GPIO38, "GPIO38"), 192 PINCTRL_PIN(GPIO38, "GPIO38"),
193 PINCTRL_PIN(GPIO39, "GPIO39"), 193 PINCTRL_PIN(GPIO39, "GPIO39"),
194 PINCTRL_PIN(GPIO40, "GPIO40"), 194 PINCTRL_PIN(GPIO40, "GPIO40"),
195 PINCTRL_PIN(GPIO41, "GPIO41"), 195 PINCTRL_PIN(GPIO41, "GPIO41"),
196 PINCTRL_PIN(GPIO42, "GPIO42"), 196 PINCTRL_PIN(GPIO42, "GPIO42"),
197 PINCTRL_PIN(GPIO43, "GPIO43"), 197 PINCTRL_PIN(GPIO43, "GPIO43"),
198 PINCTRL_PIN(GPIO44, "GPIO44"), 198 PINCTRL_PIN(GPIO44, "GPIO44"),
199 PINCTRL_PIN(GPIO45, "GPIO45"), 199 PINCTRL_PIN(GPIO45, "GPIO45"),
200 PINCTRL_PIN(GPIO46, "GPIO46"), 200 PINCTRL_PIN(GPIO46, "GPIO46"),
201 PINCTRL_PIN(GPIO47, "GPIO47"), 201 PINCTRL_PIN(GPIO47, "GPIO47"),
202 PINCTRL_PIN(GPIO48, "GPIO48"), 202 PINCTRL_PIN(GPIO48, "GPIO48"),
203 PINCTRL_PIN(GPIO49, "GPIO49"), 203 PINCTRL_PIN(GPIO49, "GPIO49"),
204 PINCTRL_PIN(GPIO50, "GPIO50"), 204 PINCTRL_PIN(GPIO50, "GPIO50"),
205 PINCTRL_PIN(GPIO51, "GPIO51"), 205 PINCTRL_PIN(GPIO51, "GPIO51"),
206 PINCTRL_PIN(GPIO52, "GPIO52"), 206 PINCTRL_PIN(GPIO52, "GPIO52"),
207 PINCTRL_PIN(GPIO53, "GPIO53"), 207 PINCTRL_PIN(GPIO53, "GPIO53"),
208 PINCTRL_PIN(GPIO54, "GPIO54"), 208 PINCTRL_PIN(GPIO54, "GPIO54"),
209 PINCTRL_PIN(GPIO55, "GPIO55"), 209 PINCTRL_PIN(GPIO55, "GPIO55"),
210 PINCTRL_PIN(GPIO56, "GPIO56"), 210 PINCTRL_PIN(GPIO56, "GPIO56"),
211 PINCTRL_PIN(GPIO57, "GPIO57"), 211 PINCTRL_PIN(GPIO57, "GPIO57"),
212 PINCTRL_PIN(GPIO58, "GPIO58"), 212 PINCTRL_PIN(GPIO58, "GPIO58"),
213 PINCTRL_PIN(GPIO59, "GPIO59"), 213 PINCTRL_PIN(GPIO59, "GPIO59"),
214 PINCTRL_PIN(GPIO60, "GPIO60"), 214 PINCTRL_PIN(GPIO60, "GPIO60"),
215 PINCTRL_PIN(GPIO61, "GPIO61"), 215 PINCTRL_PIN(GPIO61, "GPIO61"),
216 PINCTRL_PIN(GPIO62, "GPIO62"), 216 PINCTRL_PIN(GPIO62, "GPIO62"),
217 PINCTRL_PIN(GPIO63, "GPIO63"), 217 PINCTRL_PIN(GPIO63, "GPIO63"),
218 PINCTRL_PIN(GPIO64, "GPIO64"), 218 PINCTRL_PIN(GPIO64, "GPIO64"),
219 PINCTRL_PIN(GPIO65, "GPIO65"), 219 PINCTRL_PIN(GPIO65, "GPIO65"),
220 PINCTRL_PIN(GPIO66, "GPIO66"), 220 PINCTRL_PIN(GPIO66, "GPIO66"),
221 PINCTRL_PIN(GPIO67, "GPIO67"), 221 PINCTRL_PIN(GPIO67, "GPIO67"),
222 PINCTRL_PIN(GPIO68, "GPIO68"), 222 PINCTRL_PIN(GPIO68, "GPIO68"),
223 PINCTRL_PIN(GPIO69, "GPIO69"), 223 PINCTRL_PIN(GPIO69, "GPIO69"),
224 PINCTRL_PIN(GPIO70, "GPIO70"), 224 PINCTRL_PIN(GPIO70, "GPIO70"),
225 PINCTRL_PIN(GPIO71, "GPIO71"), 225 PINCTRL_PIN(GPIO71, "GPIO71"),
226 PINCTRL_PIN(GPIO72, "GPIO72"), 226 PINCTRL_PIN(GPIO72, "GPIO72"),
227 PINCTRL_PIN(GPIO73, "GPIO73"), 227 PINCTRL_PIN(GPIO73, "GPIO73"),
228 PINCTRL_PIN(GPIO74, "GPIO74"), 228 PINCTRL_PIN(GPIO74, "GPIO74"),
229 PINCTRL_PIN(GPIO75, "GPIO75"), 229 PINCTRL_PIN(GPIO75, "GPIO75"),
230 PINCTRL_PIN(GPIO76, "GPIO76"), 230 PINCTRL_PIN(GPIO76, "GPIO76"),
231 PINCTRL_PIN(GPIO77, "GPIO77"), 231 PINCTRL_PIN(GPIO77, "GPIO77"),
232 PINCTRL_PIN(GPIO78, "GPIO78"), 232 PINCTRL_PIN(GPIO78, "GPIO78"),
233 PINCTRL_PIN(GPIO79, "GPIO79"), 233 PINCTRL_PIN(GPIO79, "GPIO79"),
234 PINCTRL_PIN(GPIO80, "GPIO80"), 234 PINCTRL_PIN(GPIO80, "GPIO80"),
235 PINCTRL_PIN(GPIO81, "GPIO81"), 235 PINCTRL_PIN(GPIO81, "GPIO81"),
236 PINCTRL_PIN(GPIO82, "GPIO82"), 236 PINCTRL_PIN(GPIO82, "GPIO82"),
237 PINCTRL_PIN(GPIO83, "GPIO83"), 237 PINCTRL_PIN(GPIO83, "GPIO83"),
238 PINCTRL_PIN(GPIO84, "GPIO84"), 238 PINCTRL_PIN(GPIO84, "GPIO84"),
239 PINCTRL_PIN(GPIO85, "GPIO85"), 239 PINCTRL_PIN(GPIO85, "GPIO85"),
240 PINCTRL_PIN(GPIO86, "GPIO86"), 240 PINCTRL_PIN(GPIO86, "GPIO86"),
241 PINCTRL_PIN(GPIO87, "GPIO87"), 241 PINCTRL_PIN(GPIO87, "GPIO87"),
242 PINCTRL_PIN(GPIO88, "GPIO88"), 242 PINCTRL_PIN(GPIO88, "GPIO88"),
243 PINCTRL_PIN(GPIO89, "GPIO89"), 243 PINCTRL_PIN(GPIO89, "GPIO89"),
244 PINCTRL_PIN(GPIO90, "GPIO90"), 244 PINCTRL_PIN(GPIO90, "GPIO90"),
245 PINCTRL_PIN(GPIO91, "GPIO91"), 245 PINCTRL_PIN(GPIO91, "GPIO91"),
246 PINCTRL_PIN(GPIO92, "GPIO92"), 246 PINCTRL_PIN(GPIO92, "GPIO92"),
247 PINCTRL_PIN(GPIO93, "GPIO93"), 247 PINCTRL_PIN(GPIO93, "GPIO93"),
248 PINCTRL_PIN(GPIO94, "GPIO94"), 248 PINCTRL_PIN(GPIO94, "GPIO94"),
249 PINCTRL_PIN(GPIO95, "GPIO95"), 249 PINCTRL_PIN(GPIO95, "GPIO95"),
250 PINCTRL_PIN(GPIO96, "GPIO96"), 250 PINCTRL_PIN(GPIO96, "GPIO96"),
251 PINCTRL_PIN(GPIO97, "GPIO97"), 251 PINCTRL_PIN(GPIO97, "GPIO97"),
252 PINCTRL_PIN(GPIO98, "GPIO98"), 252 PINCTRL_PIN(GPIO98, "GPIO98"),
253 PINCTRL_PIN(GPIO99, "GPIO99"), 253 PINCTRL_PIN(GPIO99, "GPIO99"),
254 PINCTRL_PIN(GPIO100, "GPIO100"), 254 PINCTRL_PIN(GPIO100, "GPIO100"),
255 PINCTRL_PIN(GPIO101, "GPIO101"), 255 PINCTRL_PIN(GPIO101, "GPIO101"),
256 PINCTRL_PIN(GPIO102, "GPIO102"), 256 PINCTRL_PIN(GPIO102, "GPIO102"),
257 PINCTRL_PIN(GPIO103, "GPIO103"), 257 PINCTRL_PIN(GPIO103, "GPIO103"),
258 PINCTRL_PIN(GPIO104, "GPIO104"), 258 PINCTRL_PIN(GPIO104, "GPIO104"),
259 PINCTRL_PIN(GPIO105, "GPIO105"), 259 PINCTRL_PIN(GPIO105, "GPIO105"),
260 PINCTRL_PIN(GPIO106, "GPIO106"), 260 PINCTRL_PIN(GPIO106, "GPIO106"),
261 PINCTRL_PIN(GPIO107, "GPIO107"), 261 PINCTRL_PIN(GPIO107, "GPIO107"),
262 PINCTRL_PIN(GPIO108, "GPIO108"), 262 PINCTRL_PIN(GPIO108, "GPIO108"),
263 PINCTRL_PIN(GPIO109, "GPIO109"), 263 PINCTRL_PIN(GPIO109, "GPIO109"),
264 PINCTRL_PIN(GPIO110, "GPIO110"), 264 PINCTRL_PIN(GPIO110, "GPIO110"),
265 PINCTRL_PIN(GPIO111, "GPIO111"), 265 PINCTRL_PIN(GPIO111, "GPIO111"),
266 PINCTRL_PIN(GPIO112, "GPIO112"), 266 PINCTRL_PIN(GPIO112, "GPIO112"),
267 PINCTRL_PIN(GPIO113, "GPIO113"), 267 PINCTRL_PIN(GPIO113, "GPIO113"),
268 PINCTRL_PIN(GPIO114, "GPIO114"), 268 PINCTRL_PIN(GPIO114, "GPIO114"),
269 PINCTRL_PIN(GPIO115, "GPIO115"), 269 PINCTRL_PIN(GPIO115, "GPIO115"),
270 PINCTRL_PIN(GPIO116, "GPIO116"), 270 PINCTRL_PIN(GPIO116, "GPIO116"),
271 PINCTRL_PIN(GPIO117, "GPIO117"), 271 PINCTRL_PIN(GPIO117, "GPIO117"),
272 PINCTRL_PIN(GPIO118, "GPIO118"), 272 PINCTRL_PIN(GPIO118, "GPIO118"),
273 PINCTRL_PIN(GPIO119, "GPIO119"), 273 PINCTRL_PIN(GPIO119, "GPIO119"),
274 PINCTRL_PIN(GPIO120, "GPIO120"), 274 PINCTRL_PIN(GPIO120, "GPIO120"),
275 PINCTRL_PIN(GPIO121, "GPIO121"), 275 PINCTRL_PIN(GPIO121, "GPIO121"),
276 PINCTRL_PIN(GPIO122, "GPIO122"), 276 PINCTRL_PIN(GPIO122, "GPIO122"),
277 PINCTRL_PIN(GPIO123, "GPIO123"), 277 PINCTRL_PIN(GPIO123, "GPIO123"),
278 PINCTRL_PIN(GPIO124, "GPIO124"), 278 PINCTRL_PIN(GPIO124, "GPIO124"),
279 PINCTRL_PIN(GPIO125, "GPIO125"), 279 PINCTRL_PIN(GPIO125, "GPIO125"),
280 PINCTRL_PIN(GPIO126, "GPIO126"), 280 PINCTRL_PIN(GPIO126, "GPIO126"),
281 PINCTRL_PIN(GPIO127, "GPIO127"), 281 PINCTRL_PIN(GPIO127, "GPIO127"),
282 PINCTRL_PIN(ND_IO15, "ND_IO15"), 282 PINCTRL_PIN(ND_IO15, "ND_IO15"),
283 PINCTRL_PIN(ND_IO14, "ND_IO14"), 283 PINCTRL_PIN(ND_IO14, "ND_IO14"),
284 PINCTRL_PIN(ND_IO13, "ND_IO13"), 284 PINCTRL_PIN(ND_IO13, "ND_IO13"),
285 PINCTRL_PIN(ND_IO12, "ND_IO12"), 285 PINCTRL_PIN(ND_IO12, "ND_IO12"),
286 PINCTRL_PIN(ND_IO11, "ND_IO11"), 286 PINCTRL_PIN(ND_IO11, "ND_IO11"),
287 PINCTRL_PIN(ND_IO10, "ND_IO10"), 287 PINCTRL_PIN(ND_IO10, "ND_IO10"),
288 PINCTRL_PIN(ND_IO9, "ND_IO9"), 288 PINCTRL_PIN(ND_IO9, "ND_IO9"),
289 PINCTRL_PIN(ND_IO8, "ND_IO8"), 289 PINCTRL_PIN(ND_IO8, "ND_IO8"),
290 PINCTRL_PIN(ND_IO7, "ND_IO7"), 290 PINCTRL_PIN(ND_IO7, "ND_IO7"),
291 PINCTRL_PIN(ND_IO6, "ND_IO6"), 291 PINCTRL_PIN(ND_IO6, "ND_IO6"),
292 PINCTRL_PIN(ND_IO5, "ND_IO5"), 292 PINCTRL_PIN(ND_IO5, "ND_IO5"),
293 PINCTRL_PIN(ND_IO4, "ND_IO4"), 293 PINCTRL_PIN(ND_IO4, "ND_IO4"),
294 PINCTRL_PIN(ND_IO3, "ND_IO3"), 294 PINCTRL_PIN(ND_IO3, "ND_IO3"),
295 PINCTRL_PIN(ND_IO2, "ND_IO2"), 295 PINCTRL_PIN(ND_IO2, "ND_IO2"),
296 PINCTRL_PIN(ND_IO1, "ND_IO1"), 296 PINCTRL_PIN(ND_IO1, "ND_IO1"),
297 PINCTRL_PIN(ND_IO0, "ND_IO0"), 297 PINCTRL_PIN(ND_IO0, "ND_IO0"),
298 PINCTRL_PIN(ND_NCS0, "ND_NCS0_SM_NCS2"), 298 PINCTRL_PIN(ND_NCS0, "ND_NCS0_SM_NCS2"),
299 PINCTRL_PIN(ND_NCS1, "ND_NCS1_SM_NCS3"), 299 PINCTRL_PIN(ND_NCS1, "ND_NCS1_SM_NCS3"),
300 PINCTRL_PIN(SM_NCS0, "SM_NCS0"), 300 PINCTRL_PIN(SM_NCS0, "SM_NCS0"),
301 PINCTRL_PIN(SM_NCS1, "SM_NCS1"), 301 PINCTRL_PIN(SM_NCS1, "SM_NCS1"),
302 PINCTRL_PIN(ND_NWE, "ND_NWE"), 302 PINCTRL_PIN(ND_NWE, "ND_NWE"),
303 PINCTRL_PIN(ND_NRE, "ND_NRE"), 303 PINCTRL_PIN(ND_NRE, "ND_NRE"),
304 PINCTRL_PIN(ND_CLE, "ND_CLE_SM_NOE"), 304 PINCTRL_PIN(ND_CLE, "ND_CLE_SM_NOE"),
305 PINCTRL_PIN(ND_ALE, "ND_ALE_SM_NWE"), 305 PINCTRL_PIN(ND_ALE, "ND_ALE_SM_NWE"),
306 PINCTRL_PIN(SM_SCLK, "SM_SCLK"), 306 PINCTRL_PIN(SM_SCLK, "SM_SCLK"),
307 PINCTRL_PIN(ND_RDY0, "ND_RDY0"), 307 PINCTRL_PIN(ND_RDY0, "ND_RDY0"),
308 PINCTRL_PIN(SM_ADV, "SM_ADV"), 308 PINCTRL_PIN(SM_ADV, "SM_ADV"),
309 PINCTRL_PIN(ND_RDY1, "ND_RDY1"), 309 PINCTRL_PIN(ND_RDY1, "ND_RDY1"),
310 PINCTRL_PIN(SM_RDY, "SM_RDY"), 310 PINCTRL_PIN(SM_RDY, "SM_RDY"),
311 PINCTRL_PIN(MMC1_DAT7, "MMC1_DAT7"), 311 PINCTRL_PIN(MMC1_DAT7, "MMC1_DAT7"),
312 PINCTRL_PIN(MMC1_DAT6, "MMC1_DAT6"), 312 PINCTRL_PIN(MMC1_DAT6, "MMC1_DAT6"),
313 PINCTRL_PIN(MMC1_DAT5, "MMC1_DAT5"), 313 PINCTRL_PIN(MMC1_DAT5, "MMC1_DAT5"),
314 PINCTRL_PIN(MMC1_DAT4, "MMC1_DAT4"), 314 PINCTRL_PIN(MMC1_DAT4, "MMC1_DAT4"),
315 PINCTRL_PIN(MMC1_DAT3, "MMC1_DAT3"), 315 PINCTRL_PIN(MMC1_DAT3, "MMC1_DAT3"),
316 PINCTRL_PIN(MMC1_DAT2, "MMC1_DAT2"), 316 PINCTRL_PIN(MMC1_DAT2, "MMC1_DAT2"),
317 PINCTRL_PIN(MMC1_DAT1, "MMC1_DAT1"), 317 PINCTRL_PIN(MMC1_DAT1, "MMC1_DAT1"),
318 PINCTRL_PIN(MMC1_DAT0, "MMC1_DAT0"), 318 PINCTRL_PIN(MMC1_DAT0, "MMC1_DAT0"),
319 PINCTRL_PIN(MMC1_CMD, "MMC1 CMD"), 319 PINCTRL_PIN(MMC1_CMD, "MMC1 CMD"),
320 PINCTRL_PIN(MMC1_CLK, "MMC1 CLK"), 320 PINCTRL_PIN(MMC1_CLK, "MMC1 CLK"),
321 PINCTRL_PIN(MMC1_CD, "MMC1 CD"), 321 PINCTRL_PIN(MMC1_CD, "MMC1 CD"),
322 PINCTRL_PIN(VCXO_OUT, "VCXO_OUT"), 322 PINCTRL_PIN(VCXO_OUT, "VCXO_OUT"),
323 }; 323 };
324 324
325 struct pxa3xx_mfp_pin pxa910_mfp[] = { 325 struct pxa3xx_mfp_pin pxa910_mfp[] = {
326 /* pin offs f0 f1 f2 f3 f4 f5 f6 f7 */ 326 /* pin offs f0 f1 f2 f3 f4 f5 f6 f7 */
327 MFPR_910(GPIO0, 0x0DC, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 327 MFPR_910(GPIO0, 0x0DC, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
328 MFPR_910(GPIO1, 0x0E0, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 328 MFPR_910(GPIO1, 0x0E0, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
329 MFPR_910(GPIO2, 0x0E4, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 329 MFPR_910(GPIO2, 0x0E4, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
330 MFPR_910(GPIO3, 0x0E8, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 330 MFPR_910(GPIO3, 0x0E8, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
331 MFPR_910(GPIO4, 0x0EC, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 331 MFPR_910(GPIO4, 0x0EC, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
332 MFPR_910(GPIO5, 0x0F0, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 332 MFPR_910(GPIO5, 0x0F0, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
333 MFPR_910(GPIO6, 0x0F4, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 333 MFPR_910(GPIO6, 0x0F4, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
334 MFPR_910(GPIO7, 0x0F8, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 334 MFPR_910(GPIO7, 0x0F8, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
335 MFPR_910(GPIO8, 0x0FC, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 335 MFPR_910(GPIO8, 0x0FC, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
336 MFPR_910(GPIO9, 0x100, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 336 MFPR_910(GPIO9, 0x100, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
337 MFPR_910(GPIO10, 0x104, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 337 MFPR_910(GPIO10, 0x104, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
338 MFPR_910(GPIO11, 0x108, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE), 338 MFPR_910(GPIO11, 0x108, GPIO, KP_MK, NONE, NONE, NONE, NONE, NONE, NONE),
339 MFPR_910(GPIO12, 0x10C, GPIO, KP_MK, NONE, NONE, KP_DK, NONE, NONE, NONE), 339 MFPR_910(GPIO12, 0x10C, GPIO, KP_MK, NONE, NONE, KP_DK, NONE, NONE, NONE),
340 MFPR_910(GPIO13, 0x110, GPIO, KP_MK, NONE, NONE, KP_DK, NONE, NONE, NONE), 340 MFPR_910(GPIO13, 0x110, GPIO, KP_MK, NONE, NONE, KP_DK, NONE, NONE, NONE),
341 MFPR_910(GPIO14, 0x114, GPIO, KP_MK, NONE, NONE, KP_DK, TB, NONE, NONE), 341 MFPR_910(GPIO14, 0x114, GPIO, KP_MK, NONE, NONE, KP_DK, TB, NONE, NONE),
342 MFPR_910(GPIO15, 0x118, GPIO, KP_MK, NONE, NONE, KP_DK, TB, NONE, NONE), 342 MFPR_910(GPIO15, 0x118, GPIO, KP_MK, NONE, NONE, KP_DK, TB, NONE, NONE),
343 MFPR_910(GPIO16, 0x11C, GPIO, KP_DK, NONE, NONE, NONE, TB, NONE, NONE), 343 MFPR_910(GPIO16, 0x11C, GPIO, KP_DK, NONE, NONE, NONE, TB, NONE, NONE),
344 MFPR_910(GPIO17, 0x120, GPIO, KP_DK, NONE, NONE, NONE, TB, NONE, NONE), 344 MFPR_910(GPIO17, 0x120, GPIO, KP_DK, NONE, NONE, NONE, TB, NONE, NONE),
345 MFPR_910(GPIO18, 0x124, GPIO, KP_DK, NONE, NONE, ROT, NONE, NONE, NONE), 345 MFPR_910(GPIO18, 0x124, GPIO, KP_DK, NONE, NONE, ROT, NONE, NONE, NONE),
346 MFPR_910(GPIO19, 0x128, GPIO, KP_DK, NONE, NONE, ROT, NONE, NONE, NONE), 346 MFPR_910(GPIO19, 0x128, GPIO, KP_DK, NONE, NONE, ROT, NONE, NONE, NONE),
347 MFPR_910(GPIO20, 0x12C, GPIO, SSP1, NONE, NONE, VCXO_OUT, NONE, NONE, NONE), 347 MFPR_910(GPIO20, 0x12C, GPIO, SSP1, NONE, NONE, VCXO_OUT, NONE, NONE, NONE),
348 MFPR_910(GPIO21, 0x130, GPIO, SSP1, NONE, NONE, NONE, NONE, NONE, NONE), 348 MFPR_910(GPIO21, 0x130, GPIO, SSP1, NONE, NONE, NONE, NONE, NONE, NONE),
349 MFPR_910(GPIO22, 0x134, GPIO, SSP1, NONE, NONE, NONE, NONE, NONE, NONE), 349 MFPR_910(GPIO22, 0x134, GPIO, SSP1, NONE, NONE, NONE, NONE, NONE, NONE),
350 MFPR_910(GPIO23, 0x138, GPIO, SSP1, NONE, NONE, NONE, NONE, NONE, NONE), 350 MFPR_910(GPIO23, 0x138, GPIO, SSP1, NONE, NONE, NONE, NONE, NONE, NONE),
351 MFPR_910(GPIO24, 0x13C, GPIO, SSP1, NONE, NONE, NONE, NONE, NONE, NONE), 351 MFPR_910(GPIO24, 0x13C, GPIO, SSP1, NONE, NONE, NONE, NONE, NONE, NONE),
352 MFPR_910(GPIO25, 0x140, GPIO, GSSP, NONE, NONE, NONE, NONE, NONE, NONE), 352 MFPR_910(GPIO25, 0x140, GPIO, GSSP, NONE, NONE, NONE, NONE, NONE, NONE),
353 MFPR_910(GPIO26, 0x144, GPIO, GSSP, NONE, NONE, NONE, NONE, NONE, NONE), 353 MFPR_910(GPIO26, 0x144, GPIO, GSSP, NONE, NONE, NONE, NONE, NONE, NONE),
354 MFPR_910(GPIO27, 0x148, GPIO, GSSP, NONE, NONE, NONE, NONE, NONE, NONE), 354 MFPR_910(GPIO27, 0x148, GPIO, GSSP, NONE, NONE, NONE, NONE, NONE, NONE),
355 MFPR_910(GPIO28, 0x14C, GPIO, GSSP, NONE, NONE, NONE, NONE, NONE, NONE), 355 MFPR_910(GPIO28, 0x14C, GPIO, GSSP, NONE, NONE, NONE, NONE, NONE, NONE),
356 MFPR_910(GPIO29, 0x150, GPIO, UART0, NONE, NONE, UART1, NONE, NONE, NONE), 356 MFPR_910(GPIO29, 0x150, GPIO, UART0, NONE, NONE, UART1, NONE, NONE, NONE),
357 MFPR_910(GPIO30, 0x154, GPIO, UART0, NONE, NONE, UART1, NONE, NONE, NONE), 357 MFPR_910(GPIO30, 0x154, GPIO, UART0, NONE, NONE, UART1, NONE, NONE, NONE),
358 MFPR_910(GPIO31, 0x158, GPIO, UART0, NONE, NONE, UART1, NONE, NONE, NONE), 358 MFPR_910(GPIO31, 0x158, GPIO, UART0, NONE, NONE, UART1, NONE, NONE, NONE),
359 MFPR_910(GPIO32, 0x15C, GPIO, UART0, DAC_ST23, NONE, UART1, NONE, NONE, NONE), 359 MFPR_910(GPIO32, 0x15C, GPIO, UART0, DAC_ST23, NONE, UART1, NONE, NONE, NONE),
360 MFPR_910(GPIO33, 0x160, GPIO, MMC2, SSP0, SSP2, NONE, SPI, NONE, MMC3), 360 MFPR_910(GPIO33, 0x160, GPIO, MMC2, SSP0, SSP2, NONE, SPI, NONE, MMC3),
361 MFPR_910(GPIO34, 0x164, GPIO, MMC2, SSP0, SSP2, NONE, SPI, NONE, MMC3), 361 MFPR_910(GPIO34, 0x164, GPIO, MMC2, SSP0, SSP2, NONE, SPI, NONE, MMC3),
362 MFPR_910(GPIO35, 0x168, GPIO, MMC2, SSP0, SSP2, NONE, SPI, NONE, MMC3), 362 MFPR_910(GPIO35, 0x168, GPIO, MMC2, SSP0, SSP2, NONE, SPI, NONE, MMC3),
363 MFPR_910(GPIO36, 0x16C, GPIO, MMC2, SSP0, SSP2, NONE, SPI, NONE, MMC3), 363 MFPR_910(GPIO36, 0x16C, GPIO, MMC2, SSP0, SSP2, NONE, SPI, NONE, MMC3),
364 MFPR_910(GPIO37, 0x170, GPIO, MMC2, NONE, NONE, NONE, SPI, HSL, NONE), 364 MFPR_910(GPIO37, 0x170, GPIO, MMC2, NONE, NONE, NONE, SPI, HSL, NONE),
365 MFPR_910(GPIO38, 0x174, GPIO, MMC2, NONE, NONE, NONE, NONE, HSL, NONE), 365 MFPR_910(GPIO38, 0x174, GPIO, MMC2, NONE, NONE, NONE, NONE, HSL, NONE),
366 MFPR_910(GPIO39, 0x178, GPIO, MMC2, NONE, NONE, NONE, NONE, HSL, NONE), 366 MFPR_910(GPIO39, 0x178, GPIO, MMC2, NONE, NONE, NONE, NONE, HSL, NONE),
367 MFPR_910(GPIO40, 0x17C, GPIO, MMC2, NONE, NONE, NONE, NONE, HSL, NONE), 367 MFPR_910(GPIO40, 0x17C, GPIO, MMC2, NONE, NONE, NONE, NONE, HSL, NONE),
368 MFPR_910(GPIO41, 0x180, GPIO, MMC2, NONE, NONE, NONE, NONE, HSL, NONE), 368 MFPR_910(GPIO41, 0x180, GPIO, MMC2, NONE, NONE, NONE, NONE, HSL, NONE),
369 MFPR_910(GPIO42, 0x184, GPIO, MMC2, NONE, NONE, NONE, NONE, HSL, NONE), 369 MFPR_910(GPIO42, 0x184, GPIO, MMC2, NONE, NONE, NONE, NONE, HSL, NONE),
370 MFPR_910(GPIO43, 0x188, GPIO, UART1, NONE, DAC_ST23, NONE, DSSP2, SPI, UART2), 370 MFPR_910(GPIO43, 0x188, GPIO, UART1, NONE, DAC_ST23, NONE, DSSP2, SPI, UART2),
371 MFPR_910(GPIO44, 0x18C, GPIO, UART1, NONE, EXT_INT, NONE, DSSP2, SPI, UART2), 371 MFPR_910(GPIO44, 0x18C, GPIO, UART1, NONE, EXT_INT, NONE, DSSP2, SPI, UART2),
372 MFPR_910(GPIO45, 0x190, GPIO, UART1, NONE, EXT_INT, NONE, DSSP2, SPI, UART2), 372 MFPR_910(GPIO45, 0x190, GPIO, UART1, NONE, EXT_INT, NONE, DSSP2, SPI, UART2),
373 MFPR_910(GPIO46, 0x194, GPIO, UART1, NONE, EXT_INT, NONE, DSSP2, SPI, UART2), 373 MFPR_910(GPIO46, 0x194, GPIO, UART1, NONE, EXT_INT, NONE, DSSP2, SPI, UART2),
374 MFPR_910(GPIO47, 0x198, GPIO, SSP0, NONE, NONE, NONE, SSP2, UART1, NONE), 374 MFPR_910(GPIO47, 0x198, GPIO, SSP0, NONE, NONE, NONE, SSP2, UART1, NONE),
375 MFPR_910(GPIO48, 0x19C, GPIO, SSP0, NONE, NONE, NONE, SSP2, UART1, NONE), 375 MFPR_910(GPIO48, 0x19C, GPIO, SSP0, NONE, NONE, NONE, SSP2, UART1, NONE),
376 MFPR_910(GPIO49, 0x1A0, GPIO, SSP0, UART0, VCXO_REQ, NONE, SSP2, NONE, MMC3), 376 MFPR_910(GPIO49, 0x1A0, GPIO, SSP0, UART0, VCXO_REQ, NONE, SSP2, NONE, MMC3),
377 MFPR_910(GPIO50, 0x1A4, GPIO, SSP0, UART0, VCXO_OUT, NONE, SSP2, NONE, MMC3), 377 MFPR_910(GPIO50, 0x1A4, GPIO, SSP0, UART0, VCXO_OUT, NONE, SSP2, NONE, MMC3),
378 MFPR_910(GPIO51, 0x1A8, GPIO, UART2, PWM1, TWSI, SSP0, NONE, DSSP3, NONE), 378 MFPR_910(GPIO51, 0x1A8, GPIO, UART2, PWM1, TWSI, SSP0, NONE, DSSP3, NONE),
379 MFPR_910(GPIO52, 0x1AC, GPIO, UART2, DAC_ST23, TWSI, SSP0, NONE, DSSP3, NONE), 379 MFPR_910(GPIO52, 0x1AC, GPIO, UART2, DAC_ST23, TWSI, SSP0, NONE, DSSP3, NONE),
380 MFPR_910(GPIO53, 0x1B0, GPIO, UART2, TWSI, NONE, SSP0, NONE, DSSP3, NONE), 380 MFPR_910(GPIO53, 0x1B0, GPIO, UART2, TWSI, NONE, SSP0, NONE, DSSP3, NONE),
381 MFPR_910(GPIO54, 0x1B4, GPIO, UART2, TWSI, SSP0, NONE, NONE, DSSP3, NONE), 381 MFPR_910(GPIO54, 0x1B4, GPIO, UART2, TWSI, SSP0, NONE, NONE, DSSP3, NONE),
382 MFPR_910(GPIO55, 0x2F0, TDS, GPIO, TB, NONE, NONE, NONE, NONE, NONE), 382 MFPR_910(GPIO55, 0x2F0, TDS, GPIO, TB, NONE, NONE, NONE, NONE, NONE),
383 MFPR_910(GPIO56, 0x2F4, TDS, GPIO, TB, NONE, NONE, NONE, NONE, NONE), 383 MFPR_910(GPIO56, 0x2F4, TDS, GPIO, TB, NONE, NONE, NONE, NONE, NONE),
384 MFPR_910(GPIO57, 0x2F8, TDS, GPIO, TB, NONE, NONE, NONE, NONE, NONE), 384 MFPR_910(GPIO57, 0x2F8, TDS, GPIO, TB, NONE, NONE, NONE, NONE, NONE),
385 MFPR_910(GPIO58, 0x2FC, TDS, GPIO, TB, NONE, NONE, NONE, NONE, NONE), 385 MFPR_910(GPIO58, 0x2FC, TDS, GPIO, TB, NONE, NONE, NONE, NONE, NONE),
386 MFPR_910(GPIO59, 0x300, TDS, GPIO, TCU_GPOA, TCU_GPOB, ONE_WIRE, NONE, NONE, NONE), 386 MFPR_910(GPIO59, 0x300, TDS, GPIO, TCU_GPOA, TCU_GPOB, ONE_WIRE, NONE, NONE, NONE),
387 MFPR_910(GPIO60, 0x304, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, NONE), 387 MFPR_910(GPIO60, 0x304, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, NONE),
388 MFPR_910(GPIO61, 0x308, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, HSL), 388 MFPR_910(GPIO61, 0x308, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, HSL),
389 MFPR_910(GPIO62, 0x30C, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, HSL), 389 MFPR_910(GPIO62, 0x30C, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, HSL),
390 MFPR_910(GPIO63, 0x310, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, HSL), 390 MFPR_910(GPIO63, 0x310, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, HSL),
391 MFPR_910(GPIO64, 0x314, GPIO, SPI2, NONE, NONE, NONE, NONE, NONE, HSL), 391 MFPR_910(GPIO64, 0x314, GPIO, SPI2, NONE, NONE, NONE, NONE, NONE, HSL),
392 MFPR_910(GPIO65, 0x318, GPIO, SPI2, NONE, NONE, NONE, NONE, ONE_WIRE, HSL), 392 MFPR_910(GPIO65, 0x318, GPIO, SPI2, NONE, NONE, NONE, NONE, ONE_WIRE, HSL),
393 MFPR_910(GPIO66, 0x31C, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, HSL), 393 MFPR_910(GPIO66, 0x31C, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, HSL),
394 MFPR_910(GPIO67, 0x1B8, GPIO, CCIC, SPI, NONE, NONE, ULPI, NONE, USIM2), 394 MFPR_910(GPIO67, 0x1B8, GPIO, CCIC, SPI, NONE, NONE, ULPI, NONE, USIM2),
395 MFPR_910(GPIO68, 0x1BC, GPIO, CCIC, SPI, NONE, NONE, ULPI, NONE, USIM2), 395 MFPR_910(GPIO68, 0x1BC, GPIO, CCIC, SPI, NONE, NONE, ULPI, NONE, USIM2),
396 MFPR_910(GPIO69, 0x1C0, GPIO, CCIC, SPI, NONE, NONE, ULPI, NONE, USIM2), 396 MFPR_910(GPIO69, 0x1C0, GPIO, CCIC, SPI, NONE, NONE, ULPI, NONE, USIM2),
397 MFPR_910(GPIO70, 0x1C4, GPIO, CCIC, SPI, NONE, NONE, ULPI, NONE, NONE), 397 MFPR_910(GPIO70, 0x1C4, GPIO, CCIC, SPI, NONE, NONE, ULPI, NONE, NONE),
398 MFPR_910(GPIO71, 0x1C8, GPIO, CCIC, SPI, NONE, NONE, ULPI, NONE, NONE), 398 MFPR_910(GPIO71, 0x1C8, GPIO, CCIC, SPI, NONE, NONE, ULPI, NONE, NONE),
399 MFPR_910(GPIO72, 0x1CC, GPIO, CCIC, EXT_DMA, NONE, NONE, ULPI, NONE, NONE), 399 MFPR_910(GPIO72, 0x1CC, GPIO, CCIC, EXT_DMA, NONE, NONE, ULPI, NONE, NONE),
400 MFPR_910(GPIO73, 0x1D0, GPIO, CCIC, EXT_DMA, NONE, NONE, ULPI, NONE, NONE), 400 MFPR_910(GPIO73, 0x1D0, GPIO, CCIC, EXT_DMA, NONE, NONE, ULPI, NONE, NONE),
401 MFPR_910(GPIO74, 0x1D4, GPIO, CCIC, EXT_DMA, NONE, NONE, ULPI, NONE, NONE), 401 MFPR_910(GPIO74, 0x1D4, GPIO, CCIC, EXT_DMA, NONE, NONE, ULPI, NONE, NONE),
402 MFPR_910(GPIO75, 0x1D8, GPIO, CCIC, NONE, NONE, NONE, ULPI, NONE, NONE), 402 MFPR_910(GPIO75, 0x1D8, GPIO, CCIC, NONE, NONE, NONE, ULPI, NONE, NONE),
403 MFPR_910(GPIO76, 0x1DC, GPIO, CCIC, NONE, NONE, NONE, ULPI, NONE, NONE), 403 MFPR_910(GPIO76, 0x1DC, GPIO, CCIC, NONE, NONE, NONE, ULPI, NONE, NONE),
404 MFPR_910(GPIO77, 0x1E0, GPIO, CCIC, NONE, NONE, NONE, ULPI, NONE, NONE), 404 MFPR_910(GPIO77, 0x1E0, GPIO, CCIC, NONE, NONE, NONE, ULPI, NONE, NONE),
405 MFPR_910(GPIO78, 0x1E4, GPIO, CCIC, NONE, NONE, NONE, ULPI, NONE, NONE), 405 MFPR_910(GPIO78, 0x1E4, GPIO, CCIC, NONE, NONE, NONE, ULPI, NONE, NONE),
406 MFPR_910(GPIO79, 0x1E8, GPIO, TWSI, NONE, NONE, NONE, NONE, NONE, NONE), 406 MFPR_910(GPIO79, 0x1E8, GPIO, TWSI, NONE, NONE, NONE, NONE, NONE, NONE),
407 MFPR_910(GPIO80, 0x1EC, GPIO, TWSI, NONE, NONE, NONE, NONE, NONE, NONE), 407 MFPR_910(GPIO80, 0x1EC, GPIO, TWSI, NONE, NONE, NONE, NONE, NONE, NONE),
408 MFPR_910(GPIO81, 0x1F0, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 408 MFPR_910(GPIO81, 0x1F0, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
409 MFPR_910(GPIO82, 0x1F4, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 409 MFPR_910(GPIO82, 0x1F4, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
410 MFPR_910(GPIO83, 0x1F8, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 410 MFPR_910(GPIO83, 0x1F8, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
411 MFPR_910(GPIO84, 0x1FC, GPIO, LCD, VCXO_REQ2, NONE, NONE, NONE, NONE, NONE), 411 MFPR_910(GPIO84, 0x1FC, GPIO, LCD, VCXO_REQ2, NONE, NONE, NONE, NONE, NONE),
412 MFPR_910(GPIO85, 0x200, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 412 MFPR_910(GPIO85, 0x200, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
413 MFPR_910(GPIO86, 0x204, GPIO, LCD, VCXO_OUT2, NONE, NONE, NONE, NONE, NONE), 413 MFPR_910(GPIO86, 0x204, GPIO, LCD, VCXO_OUT2, NONE, NONE, NONE, NONE, NONE),
414 MFPR_910(GPIO87, 0x208, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 414 MFPR_910(GPIO87, 0x208, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
415 MFPR_910(GPIO88, 0x20C, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 415 MFPR_910(GPIO88, 0x20C, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
416 MFPR_910(GPIO89, 0x210, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 416 MFPR_910(GPIO89, 0x210, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
417 MFPR_910(GPIO90, 0x214, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 417 MFPR_910(GPIO90, 0x214, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
418 MFPR_910(GPIO91, 0x218, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 418 MFPR_910(GPIO91, 0x218, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
419 MFPR_910(GPIO92, 0x21C, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 419 MFPR_910(GPIO92, 0x21C, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
420 MFPR_910(GPIO93, 0x220, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 420 MFPR_910(GPIO93, 0x220, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
421 MFPR_910(GPIO94, 0x224, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 421 MFPR_910(GPIO94, 0x224, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
422 MFPR_910(GPIO95, 0x228, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 422 MFPR_910(GPIO95, 0x228, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
423 MFPR_910(GPIO96, 0x22C, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 423 MFPR_910(GPIO96, 0x22C, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
424 MFPR_910(GPIO97, 0x230, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 424 MFPR_910(GPIO97, 0x230, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
425 MFPR_910(GPIO98, 0x234, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 425 MFPR_910(GPIO98, 0x234, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
426 MFPR_910(GPIO99, 0x0B0, MMC1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE), 426 MFPR_910(GPIO99, 0x0B0, MMC1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE),
427 MFPR_910(GPIO100, 0x238, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 427 MFPR_910(GPIO100, 0x238, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
428 MFPR_910(GPIO101, 0x23C, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE), 428 MFPR_910(GPIO101, 0x23C, GPIO, LCD, NONE, NONE, NONE, NONE, NONE, NONE),
429 MFPR_910(GPIO102, 0x240, GPIO, LCD, DSSP2, SPI, NONE, NONE, NONE, SPI2), 429 MFPR_910(GPIO102, 0x240, GPIO, LCD, DSSP2, SPI, NONE, NONE, NONE, SPI2),
430 MFPR_910(GPIO103, 0x244, GPIO, LCD, DSSP2, SPI, NONE, NONE, NONE, SPI2), 430 MFPR_910(GPIO103, 0x244, GPIO, LCD, DSSP2, SPI, NONE, NONE, NONE, SPI2),
431 MFPR_910(GPIO104, 0x248, GPIO, LCD, DSSP2, SPI, NONE, NONE, NONE, NONE), 431 MFPR_910(GPIO104, 0x248, GPIO, LCD, DSSP2, SPI, NONE, NONE, NONE, NONE),
432 MFPR_910(GPIO105, 0x24C, GPIO, LCD, DSSP2, SPI, NONE, NONE, NONE, NONE), 432 MFPR_910(GPIO105, 0x24C, GPIO, LCD, DSSP2, SPI, NONE, NONE, NONE, NONE),
433 MFPR_910(GPIO106, 0x250, GPIO, LCD, DSSP3, ONE_WIRE, NONE, NONE, NONE, NONE), 433 MFPR_910(GPIO106, 0x250, GPIO, LCD, DSSP3, ONE_WIRE, NONE, NONE, NONE, NONE),
434 MFPR_910(GPIO107, 0x254, GPIO, LCD, DSSP3, SPI, NONE, NONE, NONE, NONE), 434 MFPR_910(GPIO107, 0x254, GPIO, LCD, DSSP3, SPI, NONE, NONE, NONE, NONE),
435 MFPR_910(GPIO108, 0x258, GPIO, LCD, DSSP3, SPI, NONE, NONE, NONE, NONE), 435 MFPR_910(GPIO108, 0x258, GPIO, LCD, DSSP3, SPI, NONE, NONE, NONE, NONE),
436 MFPR_910(GPIO109, 0x25C, GPIO, LCD, DSSP3, SPI, NONE, NONE, NONE, NONE), 436 MFPR_910(GPIO109, 0x25C, GPIO, LCD, DSSP3, SPI, NONE, NONE, NONE, NONE),
437 MFPR_910(GPIO110, 0x298, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, NONE), 437 MFPR_910(GPIO110, 0x298, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, NONE),
438 MFPR_910(GPIO111, 0x29C, GPIO, NONE, DSSP2, NONE, NONE, NONE, NONE, NONE), 438 MFPR_910(GPIO111, 0x29C, GPIO, NONE, DSSP2, NONE, NONE, NONE, NONE, NONE),
439 MFPR_910(GPIO112, 0x2A0, GPIO, NONE, DSSP2, NONE, NONE, NONE, NONE, NONE), 439 MFPR_910(GPIO112, 0x2A0, GPIO, NONE, DSSP2, NONE, NONE, NONE, NONE, NONE),
440 MFPR_910(GPIO113, 0x2A4, GPIO, NONE, DSSP2, NONE, NONE, NONE, NONE, NONE), 440 MFPR_910(GPIO113, 0x2A4, GPIO, NONE, DSSP2, NONE, NONE, NONE, NONE, NONE),
441 MFPR_910(GPIO114, 0x2A8, GPIO, NONE, DSSP3, NONE, NONE, NONE, NONE, NONE), 441 MFPR_910(GPIO114, 0x2A8, GPIO, NONE, DSSP3, NONE, NONE, NONE, NONE, NONE),
442 MFPR_910(GPIO115, 0x2AC, GPIO, NONE, DSSP3, NONE, NONE, NONE, NONE, NONE), 442 MFPR_910(GPIO115, 0x2AC, GPIO, NONE, DSSP3, NONE, NONE, NONE, NONE, NONE),
443 MFPR_910(GPIO116, 0x2B0, GPIO, NONE, DSSP3, NONE, NONE, NONE, NONE, NONE), 443 MFPR_910(GPIO116, 0x2B0, GPIO, NONE, DSSP3, NONE, NONE, NONE, NONE, NONE),
444 MFPR_910(GPIO117, 0x0B4, PRI_JTAG, GPIO, PWM0, NONE, NONE, NONE, NONE, NONE), 444 MFPR_910(GPIO117, 0x0B4, PRI_JTAG, GPIO, PWM0, NONE, NONE, NONE, NONE, NONE),
445 MFPR_910(GPIO118, 0x0B8, PRI_JTAG, GPIO, PWM1, NONE, NONE, NONE, NONE, NONE), 445 MFPR_910(GPIO118, 0x0B8, PRI_JTAG, GPIO, PWM1, NONE, NONE, NONE, NONE, NONE),
446 MFPR_910(GPIO119, 0x0BC, PRI_JTAG, GPIO, PWM2, NONE, NONE, NONE, NONE, NONE), 446 MFPR_910(GPIO119, 0x0BC, PRI_JTAG, GPIO, PWM2, NONE, NONE, NONE, NONE, NONE),
447 MFPR_910(GPIO120, 0x0C0, PRI_JTAG, GPIO, PWM3, NONE, NONE, NONE, NONE, NONE), 447 MFPR_910(GPIO120, 0x0C0, PRI_JTAG, GPIO, PWM3, NONE, NONE, NONE, NONE, NONE),
448 MFPR_910(GPIO121, 0x32C, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, NONE), 448 MFPR_910(GPIO121, 0x32C, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, NONE),
449 MFPR_910(GPIO122, 0x0C8, RESET, GPIO, 32K_CLK, NONE, NONE, NONE, NONE, NONE), 449 MFPR_910(GPIO122, 0x0C8, RESET, GPIO, 32K_CLK, NONE, NONE, NONE, NONE, NONE),
450 MFPR_910(GPIO123, 0x0CC, CLK_REQ, GPIO, ONE_WIRE, EXT_DMA, NONE, NONE, NONE, NONE), 450 MFPR_910(GPIO123, 0x0CC, CLK_REQ, GPIO, ONE_WIRE, EXT_DMA, NONE, NONE, NONE, NONE),
451 MFPR_910(GPIO124, 0x0D0, GPIO, MN_CLK, DAC_ST23, NONE, NONE, NONE, NONE, NONE), 451 MFPR_910(GPIO124, 0x0D0, GPIO, MN_CLK, DAC_ST23, NONE, NONE, NONE, NONE, NONE),
452 MFPR_910(GPIO125, 0x0D4, VCXO_REQ, GPIO, NONE, EXT_INT, NONE, NONE, NONE, NONE), 452 MFPR_910(GPIO125, 0x0D4, VCXO_REQ, GPIO, NONE, EXT_INT, NONE, NONE, NONE, NONE),
453 MFPR_910(GPIO126, 0x06C, GPIO, SMC, NONE, SM_ADDR18, NONE, EXT_DMA, NONE, NONE), 453 MFPR_910(GPIO126, 0x06C, GPIO, SMC, NONE, SM_ADDR18, NONE, EXT_DMA, NONE, NONE),
454 MFPR_910(GPIO127, 0x070, GPIO, SMC, NONE, NONE, NONE, NONE, NONE, NONE), 454 MFPR_910(GPIO127, 0x070, GPIO, SMC, NONE, NONE, NONE, NONE, NONE, NONE),
455 MFPR_910(ND_IO15, 0x004, NAND, GPIO, USIM2, EXT_DMA, NONE, NONE, NONE, NONE), 455 MFPR_910(ND_IO15, 0x004, NAND, GPIO, USIM2, EXT_DMA, NONE, NONE, NONE, NONE),
456 MFPR_910(ND_IO14, 0x008, NAND, GPIO, USIM2, NONE, NONE, NONE, NONE, NONE), 456 MFPR_910(ND_IO14, 0x008, NAND, GPIO, USIM2, NONE, NONE, NONE, NONE, NONE),
457 MFPR_910(ND_IO13, 0x00C, NAND, GPIO, USIM2, EXT_INT, NONE, NONE, NONE, NONE), 457 MFPR_910(ND_IO13, 0x00C, NAND, GPIO, USIM2, EXT_INT, NONE, NONE, NONE, NONE),
458 MFPR_910(ND_IO12, 0x010, NAND, GPIO, SSP2, EXT_INT, NONE, NONE, NONE, NONE), 458 MFPR_910(ND_IO12, 0x010, NAND, GPIO, SSP2, EXT_INT, NONE, NONE, NONE, NONE),
459 MFPR_910(ND_IO11, 0x014, NAND, GPIO, SSP2, NONE, NONE, NONE, NONE, NONE), 459 MFPR_910(ND_IO11, 0x014, NAND, GPIO, SSP2, NONE, NONE, NONE, NONE, NONE),
460 MFPR_910(ND_IO10, 0x018, NAND, GPIO, SSP2, NONE, NONE, NONE, NONE, NONE), 460 MFPR_910(ND_IO10, 0x018, NAND, GPIO, SSP2, NONE, NONE, NONE, NONE, NONE),
461 MFPR_910(ND_IO9, 0x01C, NAND, GPIO, SSP2, NONE, VCXO_OUT2, NONE, NONE, NONE), 461 MFPR_910(ND_IO9, 0x01C, NAND, GPIO, SSP2, NONE, VCXO_OUT2, NONE, NONE, NONE),
462 MFPR_910(ND_IO8, 0x020, NAND, GPIO, NONE, NONE, PWM3, NONE, NONE, NONE), 462 MFPR_910(ND_IO8, 0x020, NAND, GPIO, NONE, NONE, PWM3, NONE, NONE, NONE),
463 MFPR_910(ND_IO7, 0x024, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE), 463 MFPR_910(ND_IO7, 0x024, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE),
464 MFPR_910(ND_IO6, 0x028, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE), 464 MFPR_910(ND_IO6, 0x028, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE),
465 MFPR_910(ND_IO5, 0x02C, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE), 465 MFPR_910(ND_IO5, 0x02C, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE),
466 MFPR_910(ND_IO4, 0x030, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE), 466 MFPR_910(ND_IO4, 0x030, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE),
467 MFPR_910(ND_IO3, 0x034, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE), 467 MFPR_910(ND_IO3, 0x034, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE),
468 MFPR_910(ND_IO2, 0x038, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE), 468 MFPR_910(ND_IO2, 0x038, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE),
469 MFPR_910(ND_IO1, 0x03C, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE), 469 MFPR_910(ND_IO1, 0x03C, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE),
470 MFPR_910(ND_IO0, 0x040, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE), 470 MFPR_910(ND_IO0, 0x040, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE),
471 MFPR_910(ND_NCS0, 0x044, NAND, GPIO, NONE, NONE, NONE, NONE, NONE, NONE), 471 MFPR_910(ND_NCS0, 0x044, NAND, GPIO, NONE, NONE, NONE, NONE, NONE, NONE),
472 MFPR_910(ND_NCS1, 0x048, NAND, GPIO, NONE, NONE, NONE, NONE, NONE, NONE), 472 MFPR_910(ND_NCS1, 0x048, NAND, GPIO, NONE, NONE, NONE, NONE, NONE, NONE),
473 MFPR_910(SM_NCS0, 0x04C, SMC, GPIO, NONE, NONE, NONE, NONE, NONE, NONE), 473 MFPR_910(SM_NCS0, 0x04C, SMC, GPIO, NONE, NONE, NONE, NONE, NONE, NONE),
474 MFPR_910(SM_NCS1, 0x050, SMC, GPIO, NONE, NONE, NONE, NONE, NONE, NONE), 474 MFPR_910(SM_NCS1, 0x050, SMC, GPIO, NONE, NONE, NONE, NONE, NONE, NONE),
475 MFPR_910(ND_NWE, 0x054, GPIO, NAND, NONE, SM_ADDR20, NONE, SMC, NONE, NONE), 475 MFPR_910(ND_NWE, 0x054, GPIO, NAND, NONE, SM_ADDR20, NONE, SMC, NONE, NONE),
476 MFPR_910(ND_NRE, 0x058, GPIO, NAND, NONE, SMC, NONE, EXT_DMA, NONE, NONE), 476 MFPR_910(ND_NRE, 0x058, GPIO, NAND, NONE, SMC, NONE, EXT_DMA, NONE, NONE),
477 MFPR_910(ND_CLE, 0x05C, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE), 477 MFPR_910(ND_CLE, 0x05C, NAND, MMC3, NONE, NONE, NONE, NONE, NONE, NONE),
478 MFPR_910(ND_ALE, 0x060, GPIO, NAND, NONE, NONE, NONE, NONE, NONE, NONE), 478 MFPR_910(ND_ALE, 0x060, GPIO, NAND, NONE, NONE, NONE, NONE, NONE, NONE),
479 MFPR_910(SM_SCLK, 0x064, MMC3, NONE, NONE, NONE, NONE, NONE, NONE, NONE), 479 MFPR_910(SM_SCLK, 0x064, MMC3, NONE, NONE, NONE, NONE, NONE, NONE, NONE),
480 MFPR_910(ND_RDY0, 0x068, NAND, GPIO, NONE, SMC, NONE, NONE, NONE, NONE), 480 MFPR_910(ND_RDY0, 0x068, NAND, GPIO, NONE, SMC, NONE, NONE, NONE, NONE),
481 MFPR_910(SM_ADV, 0x074, SMC, GPIO, NONE, NONE, NONE, NONE, NONE, NONE), 481 MFPR_910(SM_ADV, 0x074, SMC, GPIO, NONE, NONE, NONE, NONE, NONE, NONE),
482 MFPR_910(ND_RDY1, 0x078, NAND, GPIO, NONE, SMC, NONE, NONE, NONE, NONE), 482 MFPR_910(ND_RDY1, 0x078, NAND, GPIO, NONE, SMC, NONE, NONE, NONE, NONE),
483 MFPR_910(SM_ADVMUX, 0x07C, SMC, GPIO, NONE, SM_ADDR19, NONE, NONE, NONE, NONE), 483 MFPR_910(SM_ADVMUX, 0x07C, SMC, GPIO, NONE, SM_ADDR19, NONE, NONE, NONE, NONE),
484 MFPR_910(SM_RDY, 0x080, SMC, GPIO, NONE, NONE, NONE, NONE, NONE, NONE), 484 MFPR_910(SM_RDY, 0x080, SMC, GPIO, NONE, NONE, NONE, NONE, NONE, NONE),
485 MFPR_910(MMC1_DAT7, 0x084, MMC1, GPIO, SEC1_JTAG, TB, NONE, NONE, NONE, NONE), 485 MFPR_910(MMC1_DAT7, 0x084, MMC1, GPIO, SEC1_JTAG, TB, NONE, NONE, NONE, NONE),
486 MFPR_910(MMC1_DAT6, 0x088, MMC1, GPIO, SEC1_JTAG, TB, NONE, NONE, NONE, NONE), 486 MFPR_910(MMC1_DAT6, 0x088, MMC1, GPIO, SEC1_JTAG, TB, NONE, NONE, NONE, NONE),
487 MFPR_910(MMC1_DAT5, 0x08C, MMC1, GPIO, SEC1_JTAG, TB, NONE, NONE, NONE, NONE), 487 MFPR_910(MMC1_DAT5, 0x08C, MMC1, GPIO, SEC1_JTAG, TB, NONE, NONE, NONE, NONE),
488 MFPR_910(MMC1_DAT4, 0x090, MMC1, GPIO, NONE, TB, NONE, NONE, NONE, NONE), 488 MFPR_910(MMC1_DAT4, 0x090, MMC1, GPIO, NONE, TB, NONE, NONE, NONE, NONE),
489 MFPR_910(MMC1_DAT3, 0x094, MMC1, HSL, SEC2_JTAG, SSP0, NONE, NONE, NONE, NONE), 489 MFPR_910(MMC1_DAT3, 0x094, MMC1, HSL, SEC2_JTAG, SSP0, NONE, NONE, NONE, NONE),
490 MFPR_910(MMC1_DAT2, 0x098, MMC1, HSL, SEC2_JTAG, SSP2, SSP0, NONE, NONE, NONE), 490 MFPR_910(MMC1_DAT2, 0x098, MMC1, HSL, SEC2_JTAG, SSP2, SSP0, NONE, NONE, NONE),
491 MFPR_910(MMC1_DAT1, 0x09C, MMC1, HSL, SEC2_JTAG, SSP2, SSP0, NONE, NONE, NONE), 491 MFPR_910(MMC1_DAT1, 0x09C, MMC1, HSL, SEC2_JTAG, SSP2, SSP0, NONE, NONE, NONE),
492 MFPR_910(MMC1_DAT0, 0x0A0, MMC1, HSL, SEC2_JTAG, SSP2, NONE, NONE, NONE, NONE), 492 MFPR_910(MMC1_DAT0, 0x0A0, MMC1, HSL, SEC2_JTAG, SSP2, NONE, NONE, NONE, NONE),
493 MFPR_910(MMC1_CMD, 0x0A4, MMC1, HSL, SEC1_JTAG, SSP2, NONE, NONE, NONE, NONE), 493 MFPR_910(MMC1_CMD, 0x0A4, MMC1, HSL, SEC1_JTAG, SSP2, NONE, NONE, NONE, NONE),
494 MFPR_910(MMC1_CLK, 0x0A8, MMC1, HSL, SEC2_JTAG, SSP0, NONE, NONE, NONE, NONE), 494 MFPR_910(MMC1_CLK, 0x0A8, MMC1, HSL, SEC2_JTAG, SSP0, NONE, NONE, NONE, NONE),
495 MFPR_910(MMC1_CD, 0x0AC, MMC1, GPIO, SEC1_JTAG, NONE, NONE, NONE, NONE, NONE), 495 MFPR_910(MMC1_CD, 0x0AC, MMC1, GPIO, SEC1_JTAG, NONE, NONE, NONE, NONE, NONE),
496 MFPR_910(VCXO_OUT, 0x0D8, VCXO_OUT, PWM3, NONE, NONE, NONE, NONE, NONE, NONE), 496 MFPR_910(VCXO_OUT, 0x0D8, VCXO_OUT, PWM3, NONE, NONE, NONE, NONE, NONE, NONE),
497 }; 497 };
498 498
499 499
500 static const unsigned p910_usim2_pin1[] = {GPIO67, GPIO68, GPIO69}; 500 static const unsigned p910_usim2_pin1[] = {GPIO67, GPIO68, GPIO69};
501 static const unsigned p910_usim2_pin2[] = {ND_IO15, ND_IO14, ND_IO13}; 501 static const unsigned p910_usim2_pin2[] = {ND_IO15, ND_IO14, ND_IO13};
502 static const unsigned p910_mmc1_pin1[] = {MMC1_DAT7, MMC1_DAT6, MMC1_DAT5, 502 static const unsigned p910_mmc1_pin1[] = {MMC1_DAT7, MMC1_DAT6, MMC1_DAT5,
503 MMC1_DAT4, MMC1_DAT3, MMC1_DAT2, MMC1_DAT1, MMC1_DAT0, MMC1_CMD, 503 MMC1_DAT4, MMC1_DAT3, MMC1_DAT2, MMC1_DAT1, MMC1_DAT0, MMC1_CMD,
504 MMC1_CLK, MMC1_CD, GPIO99}; 504 MMC1_CLK, MMC1_CD, GPIO99};
505 static const unsigned p910_mmc2_pin1[] = {GPIO33, GPIO34, GPIO35, GPIO36, 505 static const unsigned p910_mmc2_pin1[] = {GPIO33, GPIO34, GPIO35, GPIO36,
506 GPIO37, GPIO38, GPIO39, GPIO40, GPIO41, GPIO42}; 506 GPIO37, GPIO38, GPIO39, GPIO40, GPIO41, GPIO42};
507 static const unsigned p910_mmc3_pin1[] = {GPIO33, GPIO34, GPIO35, GPIO36, 507 static const unsigned p910_mmc3_pin1[] = {GPIO33, GPIO34, GPIO35, GPIO36,
508 GPIO49, GPIO50}; 508 GPIO49, GPIO50};
509 static const unsigned p910_mmc3_pin2[] = {ND_IO7, ND_IO6, ND_IO5, ND_IO4, 509 static const unsigned p910_mmc3_pin2[] = {ND_IO7, ND_IO6, ND_IO5, ND_IO4,
510 ND_IO3, ND_IO2, ND_IO1, ND_IO0, ND_CLE, SM_SCLK}; 510 ND_IO3, ND_IO2, ND_IO1, ND_IO0, ND_CLE, SM_SCLK};
511 static const unsigned p910_uart0_pin1[] = {GPIO29, GPIO30, GPIO31, GPIO32}; 511 static const unsigned p910_uart0_pin1[] = {GPIO29, GPIO30, GPIO31, GPIO32};
512 static const unsigned p910_uart1_pin1[] = {GPIO47, GPIO48}; 512 static const unsigned p910_uart1_pin1[] = {GPIO47, GPIO48};
513 static const unsigned p910_uart1_pin2[] = {GPIO31, GPIO32}; 513 static const unsigned p910_uart1_pin2[] = {GPIO31, GPIO32};
514 static const unsigned p910_uart1_pin3[] = {GPIO45, GPIO46}; 514 static const unsigned p910_uart1_pin3[] = {GPIO45, GPIO46};
515 static const unsigned p910_uart1_pin4[] = {GPIO29, GPIO30, GPIO31, GPIO32}; 515 static const unsigned p910_uart1_pin4[] = {GPIO29, GPIO30, GPIO31, GPIO32};
516 static const unsigned p910_uart1_pin5[] = {GPIO43, GPIO44, GPIO45, GPIO46}; 516 static const unsigned p910_uart1_pin5[] = {GPIO43, GPIO44, GPIO45, GPIO46};
517 static const unsigned p910_uart2_pin1[] = {GPIO43, GPIO44}; 517 static const unsigned p910_uart2_pin1[] = {GPIO43, GPIO44};
518 static const unsigned p910_uart2_pin2[] = {GPIO51, GPIO52}; 518 static const unsigned p910_uart2_pin2[] = {GPIO51, GPIO52};
519 static const unsigned p910_uart2_pin3[] = {GPIO43, GPIO44, GPIO45, GPIO46}; 519 static const unsigned p910_uart2_pin3[] = {GPIO43, GPIO44, GPIO45, GPIO46};
520 static const unsigned p910_uart2_pin4[] = {GPIO51, GPIO52, GPIO53, GPIO54}; 520 static const unsigned p910_uart2_pin4[] = {GPIO51, GPIO52, GPIO53, GPIO54};
521 static const unsigned p910_twsi_pin1[] = {GPIO51, GPIO52}; 521 static const unsigned p910_twsi_pin1[] = {GPIO51, GPIO52};
522 static const unsigned p910_twsi_pin2[] = {GPIO53, GPIO54}; 522 static const unsigned p910_twsi_pin2[] = {GPIO53, GPIO54};
523 static const unsigned p910_twsi_pin3[] = {GPIO79, GPIO80}; 523 static const unsigned p910_twsi_pin3[] = {GPIO79, GPIO80};
524 static const unsigned p910_ccic_pin1[] = {GPIO67, GPIO68, GPIO69, GPIO70, 524 static const unsigned p910_ccic_pin1[] = {GPIO67, GPIO68, GPIO69, GPIO70,
525 GPIO71, GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78}; 525 GPIO71, GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78};
526 static const unsigned p910_lcd_pin1[] = {GPIO81, GPIO82, GPIO83, GPIO84, 526 static const unsigned p910_lcd_pin1[] = {GPIO81, GPIO82, GPIO83, GPIO84,
527 GPIO85, GPIO86, GPIO87, GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, 527 GPIO85, GPIO86, GPIO87, GPIO88, GPIO89, GPIO90, GPIO91, GPIO92,
528 GPIO93, GPIO94, GPIO95, GPIO96, GPIO97, GPIO98, GPIO100, GPIO101, 528 GPIO93, GPIO94, GPIO95, GPIO96, GPIO97, GPIO98, GPIO100, GPIO101,
529 GPIO102, GPIO103}; 529 GPIO102, GPIO103};
530 static const unsigned p910_spi_pin1[] = {GPIO104, GPIO105, GPIO107, GPIO108}; 530 static const unsigned p910_spi_pin1[] = {GPIO104, GPIO105, GPIO107, GPIO108};
531 static const unsigned p910_spi_pin2[] = {GPIO43, GPIO44, GPIO45, GPIO46}; 531 static const unsigned p910_spi_pin2[] = {GPIO43, GPIO44, GPIO45, GPIO46};
532 static const unsigned p910_spi_pin3[] = {GPIO33, GPIO34, GPIO35, GPIO36, 532 static const unsigned p910_spi_pin3[] = {GPIO33, GPIO34, GPIO35, GPIO36,
533 GPIO37}; 533 GPIO37};
534 static const unsigned p910_spi_pin4[] = {GPIO67, GPIO68, GPIO69, GPIO70, 534 static const unsigned p910_spi_pin4[] = {GPIO67, GPIO68, GPIO69, GPIO70,
535 GPIO71}; 535 GPIO71};
536 static const unsigned p910_spi2_pin1[] = {GPIO64, GPIO65}; 536 static const unsigned p910_spi2_pin1[] = {GPIO64, GPIO65};
537 static const unsigned p910_spi2_pin2[] = {GPIO102, GPIO103}; 537 static const unsigned p910_spi2_pin2[] = {GPIO102, GPIO103};
538 static const unsigned p910_dssp2_pin1[] = {GPIO102, GPIO103, GPIO104, GPIO105}; 538 static const unsigned p910_dssp2_pin1[] = {GPIO102, GPIO103, GPIO104, GPIO105};
539 static const unsigned p910_dssp2_pin2[] = {GPIO43, GPIO44, GPIO45, GPIO46}; 539 static const unsigned p910_dssp2_pin2[] = {GPIO43, GPIO44, GPIO45, GPIO46};
540 static const unsigned p910_dssp2_pin3[] = {GPIO111, GPIO112, GPIO113}; 540 static const unsigned p910_dssp2_pin3[] = {GPIO111, GPIO112, GPIO113};
541 static const unsigned p910_dssp3_pin1[] = {GPIO106, GPIO107, GPIO108, GPIO109}; 541 static const unsigned p910_dssp3_pin1[] = {GPIO106, GPIO107, GPIO108, GPIO109};
542 static const unsigned p910_dssp3_pin2[] = {GPIO51, GPIO52, GPIO53, GPIO54}; 542 static const unsigned p910_dssp3_pin2[] = {GPIO51, GPIO52, GPIO53, GPIO54};
543 static const unsigned p910_dssp3_pin3[] = {GPIO114, GPIO115, GPIO116}; 543 static const unsigned p910_dssp3_pin3[] = {GPIO114, GPIO115, GPIO116};
544 static const unsigned p910_ssp0_pin1[] = {MMC1_DAT3, MMC1_DAT2, MMC1_DAT1, 544 static const unsigned p910_ssp0_pin1[] = {MMC1_DAT3, MMC1_DAT2, MMC1_DAT1,
545 MMC1_CLK}; 545 MMC1_CLK};
546 static const unsigned p910_ssp0_pin2[] = {GPIO33, GPIO34, GPIO35, GPIO36}; 546 static const unsigned p910_ssp0_pin2[] = {GPIO33, GPIO34, GPIO35, GPIO36};
547 static const unsigned p910_ssp0_pin3[] = {GPIO47, GPIO48, GPIO49, GPIO50}; 547 static const unsigned p910_ssp0_pin3[] = {GPIO47, GPIO48, GPIO49, GPIO50};
548 static const unsigned p910_ssp0_pin4[] = {GPIO51, GPIO52, GPIO53, GPIO54}; 548 static const unsigned p910_ssp0_pin4[] = {GPIO51, GPIO52, GPIO53, GPIO54};
549 static const unsigned p910_ssp1_pin1[] = {GPIO21, GPIO22, GPIO23, GPIO24}; 549 static const unsigned p910_ssp1_pin1[] = {GPIO21, GPIO22, GPIO23, GPIO24};
550 static const unsigned p910_ssp1_pin2[] = {GPIO20, GPIO21, GPIO22, GPIO23, 550 static const unsigned p910_ssp1_pin2[] = {GPIO20, GPIO21, GPIO22, GPIO23,
551 GPIO24}; 551 GPIO24};
552 static const unsigned p910_ssp2_pin1[] = {MMC1_DAT2, MMC1_DAT1, MMC1_DAT0, 552 static const unsigned p910_ssp2_pin1[] = {MMC1_DAT2, MMC1_DAT1, MMC1_DAT0,
553 MMC1_CMD}; 553 MMC1_CMD};
554 static const unsigned p910_ssp2_pin2[] = {GPIO33, GPIO34, GPIO35, GPIO36}; 554 static const unsigned p910_ssp2_pin2[] = {GPIO33, GPIO34, GPIO35, GPIO36};
555 static const unsigned p910_ssp2_pin3[] = {GPIO47, GPIO48, GPIO49, GPIO50}; 555 static const unsigned p910_ssp2_pin3[] = {GPIO47, GPIO48, GPIO49, GPIO50};
556 static const unsigned p910_ssp2_pin4[] = {ND_IO12, ND_IO11, ND_IO10, ND_IO9}; 556 static const unsigned p910_ssp2_pin4[] = {ND_IO12, ND_IO11, ND_IO10, ND_IO9};
557 static const unsigned p910_gssp_pin1[] = {GPIO25, GPIO26, GPIO27, GPIO28}; 557 static const unsigned p910_gssp_pin1[] = {GPIO25, GPIO26, GPIO27, GPIO28};
558 static const unsigned p910_pwm0_pin1[] = {GPIO117}; 558 static const unsigned p910_pwm0_pin1[] = {GPIO117};
559 static const unsigned p910_pwm1_pin1[] = {GPIO118}; 559 static const unsigned p910_pwm1_pin1[] = {GPIO118};
560 static const unsigned p910_pwm1_pin2[] = {GPIO51}; 560 static const unsigned p910_pwm1_pin2[] = {GPIO51};
561 static const unsigned p910_pwm2_pin1[] = {GPIO119}; 561 static const unsigned p910_pwm2_pin1[] = {GPIO119};
562 static const unsigned p910_pwm3_pin1[] = {GPIO120}; 562 static const unsigned p910_pwm3_pin1[] = {GPIO120};
563 static const unsigned p910_pwm3_pin2[] = {ND_IO8}; 563 static const unsigned p910_pwm3_pin2[] = {ND_IO8};
564 static const unsigned p910_pwm3_pin3[] = {VCXO_OUT}; 564 static const unsigned p910_pwm3_pin3[] = {VCXO_OUT};
565 static const unsigned p910_pri_jtag_pin1[] = {GPIO117, GPIO118, GPIO119, 565 static const unsigned p910_pri_jtag_pin1[] = {GPIO117, GPIO118, GPIO119,
566 GPIO120}; 566 GPIO120};
567 static const unsigned p910_sec1_jtag_pin1[] = {MMC1_DAT7, MMC1_DAT6, MMC1_DAT5, 567 static const unsigned p910_sec1_jtag_pin1[] = {MMC1_DAT7, MMC1_DAT6, MMC1_DAT5,
568 MMC1_CMD, MMC1_CD}; 568 MMC1_CMD, MMC1_CD};
569 static const unsigned p910_sec2_jtag_pin1[] = {MMC1_DAT3, MMC1_DAT2, MMC1_DAT1, 569 static const unsigned p910_sec2_jtag_pin1[] = {MMC1_DAT3, MMC1_DAT2, MMC1_DAT1,
570 MMC1_DAT0, MMC1_CLK}; 570 MMC1_DAT0, MMC1_CLK};
571 static const unsigned p910_hsl_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40, 571 static const unsigned p910_hsl_pin1[] = {GPIO37, GPIO38, GPIO39, GPIO40,
572 GPIO41, GPIO42}; 572 GPIO41, GPIO42};
573 static const unsigned p910_hsl_pin2[] = {GPIO61, GPIO62, GPIO63, GPIO64, 573 static const unsigned p910_hsl_pin2[] = {GPIO61, GPIO62, GPIO63, GPIO64,
574 GPIO65, GPIO66}; 574 GPIO65, GPIO66};
575 static const unsigned p910_hsl_pin3[] = {MMC1_DAT3, MMC1_DAT2, MMC1_DAT1, 575 static const unsigned p910_hsl_pin3[] = {MMC1_DAT3, MMC1_DAT2, MMC1_DAT1,
576 MMC1_DAT0, MMC1_CMD, MMC1_CLK}; 576 MMC1_DAT0, MMC1_CMD, MMC1_CLK};
577 static const unsigned p910_w1_pin1[] = {GPIO59}; 577 static const unsigned p910_w1_pin1[] = {GPIO59};
578 static const unsigned p910_w1_pin2[] = {GPIO65}; 578 static const unsigned p910_w1_pin2[] = {GPIO65};
579 static const unsigned p910_w1_pin3[] = {GPIO106}; 579 static const unsigned p910_w1_pin3[] = {GPIO106};
580 static const unsigned p910_w1_pin4[] = {GPIO123}; 580 static const unsigned p910_w1_pin4[] = {GPIO123};
581 static const unsigned p910_kpmk_pin1[] = {GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, 581 static const unsigned p910_kpmk_pin1[] = {GPIO0, GPIO1, GPIO2, GPIO3, GPIO4,
582 GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, 582 GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13,
583 GPIO14, GPIO15}; 583 GPIO14, GPIO15};
584 static const unsigned p910_kpmk_pin2[] = {GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, 584 static const unsigned p910_kpmk_pin2[] = {GPIO0, GPIO1, GPIO2, GPIO3, GPIO4,
585 GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO12}; 585 GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO12};
586 static const unsigned p910_kpdk_pin1[] = {GPIO12, GPIO13, GPIO14, GPIO15, 586 static const unsigned p910_kpdk_pin1[] = {GPIO12, GPIO13, GPIO14, GPIO15,
587 GPIO16, GPIO17, GPIO18, GPIO19}; 587 GPIO16, GPIO17, GPIO18, GPIO19};
588 static const unsigned p910_tds_pin1[] = {GPIO55, GPIO56, GPIO57, GPIO58, 588 static const unsigned p910_tds_pin1[] = {GPIO55, GPIO56, GPIO57, GPIO58,
589 GPIO59}; 589 GPIO59};
590 static const unsigned p910_tds_pin2[] = {GPIO55, GPIO57, GPIO58, GPIO59}; 590 static const unsigned p910_tds_pin2[] = {GPIO55, GPIO57, GPIO58, GPIO59};
591 static const unsigned p910_tb_pin1[] = {GPIO14, GPIO15, GPIO16, GPIO17}; 591 static const unsigned p910_tb_pin1[] = {GPIO14, GPIO15, GPIO16, GPIO17};
592 static const unsigned p910_tb_pin2[] = {GPIO55, GPIO56, GPIO57, GPIO58}; 592 static const unsigned p910_tb_pin2[] = {GPIO55, GPIO56, GPIO57, GPIO58};
593 static const unsigned p910_tb_pin3[] = {MMC1_DAT7, MMC1_DAT6, MMC1_DAT5, 593 static const unsigned p910_tb_pin3[] = {MMC1_DAT7, MMC1_DAT6, MMC1_DAT5,
594 MMC1_DAT4}; 594 MMC1_DAT4};
595 static const unsigned p910_ext_dma0_pin1[] = {GPIO72}; 595 static const unsigned p910_ext_dma0_pin1[] = {GPIO72};
596 static const unsigned p910_ext_dma0_pin2[] = {ND_IO15}; 596 static const unsigned p910_ext_dma0_pin2[] = {ND_IO15};
597 static const unsigned p910_ext_dma0_pin3[] = {ND_NRE}; 597 static const unsigned p910_ext_dma0_pin3[] = {ND_NRE};
598 static const unsigned p910_ext_dma1_pin1[] = {GPIO73}; 598 static const unsigned p910_ext_dma1_pin1[] = {GPIO73};
599 static const unsigned p910_ext_dma1_pin2[] = {GPIO123}; 599 static const unsigned p910_ext_dma1_pin2[] = {GPIO123};
600 static const unsigned p910_ext_dma1_pin3[] = {GPIO126}; 600 static const unsigned p910_ext_dma1_pin3[] = {GPIO126};
601 static const unsigned p910_ext_dma2_pin1[] = {GPIO74}; 601 static const unsigned p910_ext_dma2_pin1[] = {GPIO74};
602 static const unsigned p910_ext0_int_pin1[] = {GPIO44}; 602 static const unsigned p910_ext0_int_pin1[] = {GPIO44};
603 static const unsigned p910_ext0_int_pin2[] = {ND_IO13}; 603 static const unsigned p910_ext0_int_pin2[] = {ND_IO13};
604 static const unsigned p910_ext1_int_pin1[] = {GPIO45}; 604 static const unsigned p910_ext1_int_pin1[] = {GPIO45};
605 static const unsigned p910_ext1_int_pin2[] = {ND_IO12}; 605 static const unsigned p910_ext1_int_pin2[] = {ND_IO12};
606 static const unsigned p910_ext2_int_pin1[] = {GPIO46}; 606 static const unsigned p910_ext2_int_pin1[] = {GPIO46};
607 static const unsigned p910_ext2_int_pin2[] = {GPIO125}; 607 static const unsigned p910_ext2_int_pin2[] = {GPIO125};
608 static const unsigned p910_dac_st23_pin1[] = {GPIO32}; 608 static const unsigned p910_dac_st23_pin1[] = {GPIO32};
609 static const unsigned p910_dac_st23_pin2[] = {GPIO43}; 609 static const unsigned p910_dac_st23_pin2[] = {GPIO43};
610 static const unsigned p910_dac_st23_pin3[] = {GPIO52}; 610 static const unsigned p910_dac_st23_pin3[] = {GPIO52};
611 static const unsigned p910_dac_st23_pin4[] = {GPIO124}; 611 static const unsigned p910_dac_st23_pin4[] = {GPIO124};
612 static const unsigned p910_vcxo_out_pin1[] = {GPIO50}; 612 static const unsigned p910_vcxo_out_pin1[] = {GPIO50};
613 static const unsigned p910_vcxo_out_pin2[] = {VCXO_OUT}; 613 static const unsigned p910_vcxo_out_pin2[] = {VCXO_OUT};
614 static const unsigned p910_vcxo_out_pin3[] = {GPIO20}; 614 static const unsigned p910_vcxo_out_pin3[] = {GPIO20};
615 static const unsigned p910_vcxo_req_pin1[] = {GPIO49}; 615 static const unsigned p910_vcxo_req_pin1[] = {GPIO49};
616 static const unsigned p910_vcxo_req_pin2[] = {GPIO125}; 616 static const unsigned p910_vcxo_req_pin2[] = {GPIO125};
617 static const unsigned p910_vcxo_out2_pin1[] = {GPIO86}; 617 static const unsigned p910_vcxo_out2_pin1[] = {GPIO86};
618 static const unsigned p910_vcxo_out2_pin2[] = {ND_IO9}; 618 static const unsigned p910_vcxo_out2_pin2[] = {ND_IO9};
619 static const unsigned p910_vcxo_req2_pin1[] = {GPIO84}; 619 static const unsigned p910_vcxo_req2_pin1[] = {GPIO84};
620 static const unsigned p910_ulpi_pin1[] = {GPIO67, GPIO68, GPIO69, GPIO70, 620 static const unsigned p910_ulpi_pin1[] = {GPIO67, GPIO68, GPIO69, GPIO70,
621 GPIO71, GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78}; 621 GPIO71, GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78};
622 static const unsigned p910_nand_pin1[] = {ND_IO15, ND_IO14, ND_IO13, ND_IO12, 622 static const unsigned p910_nand_pin1[] = {ND_IO15, ND_IO14, ND_IO13, ND_IO12,
623 ND_IO11, ND_IO10, ND_IO9, ND_IO8, ND_IO7, ND_IO6, ND_IO5, ND_IO4, 623 ND_IO11, ND_IO10, ND_IO9, ND_IO8, ND_IO7, ND_IO6, ND_IO5, ND_IO4,
624 ND_IO3, ND_IO2, ND_IO1, ND_IO0, ND_NCS0, ND_NWE, ND_NRE, ND_CLE, 624 ND_IO3, ND_IO2, ND_IO1, ND_IO0, ND_NCS0, ND_NWE, ND_NRE, ND_CLE,
625 ND_ALE, ND_RDY0}; 625 ND_ALE, ND_RDY0};
626 static const unsigned p910_gpio0_pin1[] = {GPIO0}; 626 static const unsigned p910_gpio0_pin1[] = {GPIO0};
627 static const unsigned p910_gpio0_pin2[] = {SM_ADV}; 627 static const unsigned p910_gpio0_pin2[] = {SM_ADV};
628 static const unsigned p910_gpio1_pin1[] = {GPIO1}; 628 static const unsigned p910_gpio1_pin1[] = {GPIO1};
629 static const unsigned p910_gpio1_pin2[] = {ND_RDY1}; 629 static const unsigned p910_gpio1_pin2[] = {ND_RDY1};
630 static const unsigned p910_gpio2_pin1[] = {GPIO2}; 630 static const unsigned p910_gpio2_pin1[] = {GPIO2};
631 static const unsigned p910_gpio2_pin2[] = {SM_ADVMUX}; 631 static const unsigned p910_gpio2_pin2[] = {SM_ADVMUX};
632 static const unsigned p910_gpio3_pin1[] = {GPIO3}; 632 static const unsigned p910_gpio3_pin1[] = {GPIO3};
633 static const unsigned p910_gpio3_pin2[] = {SM_RDY}; 633 static const unsigned p910_gpio3_pin2[] = {SM_RDY};
634 static const unsigned p910_gpio20_pin1[] = {GPIO20}; 634 static const unsigned p910_gpio20_pin1[] = {GPIO20};
635 static const unsigned p910_gpio20_pin2[] = {ND_IO15}; 635 static const unsigned p910_gpio20_pin2[] = {ND_IO15};
636 static const unsigned p910_gpio20_pin3[] = {MMC1_DAT6}; 636 static const unsigned p910_gpio20_pin3[] = {MMC1_DAT6};
637 static const unsigned p910_gpio21_pin1[] = {GPIO21}; 637 static const unsigned p910_gpio21_pin1[] = {GPIO21};
638 static const unsigned p910_gpio21_pin2[] = {ND_IO14}; 638 static const unsigned p910_gpio21_pin2[] = {ND_IO14};
639 static const unsigned p910_gpio21_pin3[] = {MMC1_DAT5}; 639 static const unsigned p910_gpio21_pin3[] = {MMC1_DAT5};
640 static const unsigned p910_gpio22_pin1[] = {GPIO22}; 640 static const unsigned p910_gpio22_pin1[] = {GPIO22};
641 static const unsigned p910_gpio22_pin2[] = {ND_IO13}; 641 static const unsigned p910_gpio22_pin2[] = {ND_IO13};
642 static const unsigned p910_gpio22_pin3[] = {MMC1_DAT4}; 642 static const unsigned p910_gpio22_pin3[] = {MMC1_DAT4};
643 static const unsigned p910_gpio23_pin1[] = {GPIO23}; 643 static const unsigned p910_gpio23_pin1[] = {GPIO23};
644 static const unsigned p910_gpio23_pin2[] = {ND_IO12}; 644 static const unsigned p910_gpio23_pin2[] = {ND_IO12};
645 static const unsigned p910_gpio23_pin3[] = {MMC1_CD}; 645 static const unsigned p910_gpio23_pin3[] = {MMC1_CD};
646 static const unsigned p910_gpio24_pin1[] = {GPIO24}; 646 static const unsigned p910_gpio24_pin1[] = {GPIO24};
647 static const unsigned p910_gpio24_pin2[] = {ND_IO11}; 647 static const unsigned p910_gpio24_pin2[] = {ND_IO11};
648 static const unsigned p910_gpio24_pin3[] = {MMC1_DAT7}; 648 static const unsigned p910_gpio24_pin3[] = {MMC1_DAT7};
649 static const unsigned p910_gpio25_pin1[] = {GPIO25}; 649 static const unsigned p910_gpio25_pin1[] = {GPIO25};
650 static const unsigned p910_gpio25_pin2[] = {ND_IO10}; 650 static const unsigned p910_gpio25_pin2[] = {ND_IO10};
651 static const unsigned p910_gpio26_pin1[] = {GPIO26}; 651 static const unsigned p910_gpio26_pin1[] = {GPIO26};
652 static const unsigned p910_gpio26_pin2[] = {ND_IO9}; 652 static const unsigned p910_gpio26_pin2[] = {ND_IO9};
653 static const unsigned p910_gpio27_pin1[] = {GPIO27}; 653 static const unsigned p910_gpio27_pin1[] = {GPIO27};
654 static const unsigned p910_gpio27_pin2[] = {ND_IO8}; 654 static const unsigned p910_gpio27_pin2[] = {ND_IO8};
655 static const unsigned p910_gpio85_pin1[] = {GPIO85}; 655 static const unsigned p910_gpio85_pin1[] = {GPIO85};
656 static const unsigned p910_gpio85_pin2[] = {ND_NCS0}; 656 static const unsigned p910_gpio85_pin2[] = {ND_NCS0};
657 static const unsigned p910_gpio86_pin1[] = {GPIO86}; 657 static const unsigned p910_gpio86_pin1[] = {GPIO86};
658 static const unsigned p910_gpio86_pin2[] = {ND_NCS1}; 658 static const unsigned p910_gpio86_pin2[] = {ND_NCS1};
659 static const unsigned p910_gpio87_pin1[] = {GPIO87}; 659 static const unsigned p910_gpio87_pin1[] = {GPIO87};
660 static const unsigned p910_gpio87_pin2[] = {SM_NCS0}; 660 static const unsigned p910_gpio87_pin2[] = {SM_NCS0};
661 static const unsigned p910_gpio88_pin1[] = {GPIO88}; 661 static const unsigned p910_gpio88_pin1[] = {GPIO88};
662 static const unsigned p910_gpio88_pin2[] = {SM_NCS1}; 662 static const unsigned p910_gpio88_pin2[] = {SM_NCS1};
663 static const unsigned p910_gpio89_pin1[] = {GPIO89}; 663 static const unsigned p910_gpio89_pin1[] = {GPIO89};
664 static const unsigned p910_gpio89_pin2[] = {ND_NWE}; 664 static const unsigned p910_gpio89_pin2[] = {ND_NWE};
665 static const unsigned p910_gpio90_pin1[] = {GPIO90}; 665 static const unsigned p910_gpio90_pin1[] = {GPIO90};
666 static const unsigned p910_gpio90_pin2[] = {ND_NRE}; 666 static const unsigned p910_gpio90_pin2[] = {ND_NRE};
667 static const unsigned p910_gpio91_pin1[] = {GPIO91}; 667 static const unsigned p910_gpio91_pin1[] = {GPIO91};
668 static const unsigned p910_gpio91_pin2[] = {ND_ALE}; 668 static const unsigned p910_gpio91_pin2[] = {ND_ALE};
669 static const unsigned p910_gpio92_pin1[] = {GPIO92}; 669 static const unsigned p910_gpio92_pin1[] = {GPIO92};
670 static const unsigned p910_gpio92_pin2[] = {ND_RDY0}; 670 static const unsigned p910_gpio92_pin2[] = {ND_RDY0};
671 671
672 static struct pxa3xx_pin_group pxa910_grps[] = { 672 static struct pxa3xx_pin_group pxa910_grps[] = {
673 GRP_910("usim2 3p1", USIM2, p910_usim2_pin1), 673 GRP_910("usim2 3p1", USIM2, p910_usim2_pin1),
674 GRP_910("usim2 3p2", USIM2, p910_usim2_pin2), 674 GRP_910("usim2 3p2", USIM2, p910_usim2_pin2),
675 GRP_910("mmc1 12p", MMC1, p910_mmc1_pin1), 675 GRP_910("mmc1 12p", MMC1, p910_mmc1_pin1),
676 GRP_910("mmc2 10p", MMC2, p910_mmc2_pin1), 676 GRP_910("mmc2 10p", MMC2, p910_mmc2_pin1),
677 GRP_910("mmc3 6p", MMC3, p910_mmc3_pin1), 677 GRP_910("mmc3 6p", MMC3, p910_mmc3_pin1),
678 GRP_910("mmc3 10p", MMC3, p910_mmc3_pin2), 678 GRP_910("mmc3 10p", MMC3, p910_mmc3_pin2),
679 GRP_910("uart0 4p", UART0, p910_uart0_pin1), 679 GRP_910("uart0 4p", UART0, p910_uart0_pin1),
680 GRP_910("uart1 2p1", UART1, p910_uart1_pin1), 680 GRP_910("uart1 2p1", UART1, p910_uart1_pin1),
681 GRP_910("uart1 2p2", UART1, p910_uart1_pin2), 681 GRP_910("uart1 2p2", UART1, p910_uart1_pin2),
682 GRP_910("uart1 2p3", UART1, p910_uart1_pin3), 682 GRP_910("uart1 2p3", UART1, p910_uart1_pin3),
683 GRP_910("uart1 4p4", UART1, p910_uart1_pin4), 683 GRP_910("uart1 4p4", UART1, p910_uart1_pin4),
684 GRP_910("uart1 4p5", UART1, p910_uart1_pin5), 684 GRP_910("uart1 4p5", UART1, p910_uart1_pin5),
685 GRP_910("uart2 2p1", UART2, p910_uart2_pin1), 685 GRP_910("uart2 2p1", UART2, p910_uart2_pin1),
686 GRP_910("uart2 2p2", UART2, p910_uart2_pin2), 686 GRP_910("uart2 2p2", UART2, p910_uart2_pin2),
687 GRP_910("uart2 4p3", UART2, p910_uart2_pin3), 687 GRP_910("uart2 4p3", UART2, p910_uart2_pin3),
688 GRP_910("uart2 4p4", UART2, p910_uart2_pin4), 688 GRP_910("uart2 4p4", UART2, p910_uart2_pin4),
689 GRP_910("twsi 2p1", TWSI, p910_twsi_pin1), 689 GRP_910("twsi 2p1", TWSI, p910_twsi_pin1),
690 GRP_910("twsi 2p2", TWSI, p910_twsi_pin2), 690 GRP_910("twsi 2p2", TWSI, p910_twsi_pin2),
691 GRP_910("twsi 2p3", TWSI, p910_twsi_pin3), 691 GRP_910("twsi 2p3", TWSI, p910_twsi_pin3),
692 GRP_910("ccic", CCIC, p910_ccic_pin1), 692 GRP_910("ccic", CCIC, p910_ccic_pin1),
693 GRP_910("lcd", LCD, p910_lcd_pin1), 693 GRP_910("lcd", LCD, p910_lcd_pin1),
694 GRP_910("spi 4p1", SPI, p910_spi_pin1), 694 GRP_910("spi 4p1", SPI, p910_spi_pin1),
695 GRP_910("spi 4p2", SPI, p910_spi_pin2), 695 GRP_910("spi 4p2", SPI, p910_spi_pin2),
696 GRP_910("spi 5p3", SPI, p910_spi_pin3), 696 GRP_910("spi 5p3", SPI, p910_spi_pin3),
697 GRP_910("spi 5p4", SPI, p910_spi_pin4), 697 GRP_910("spi 5p4", SPI, p910_spi_pin4),
698 GRP_910("dssp2 4p1", DSSP2, p910_dssp2_pin1), 698 GRP_910("dssp2 4p1", DSSP2, p910_dssp2_pin1),
699 GRP_910("dssp2 4p2", DSSP2, p910_dssp2_pin2), 699 GRP_910("dssp2 4p2", DSSP2, p910_dssp2_pin2),
700 GRP_910("dssp2 3p3", DSSP2, p910_dssp2_pin3), 700 GRP_910("dssp2 3p3", DSSP2, p910_dssp2_pin3),
701 GRP_910("dssp3 4p1", DSSP3, p910_dssp3_pin1), 701 GRP_910("dssp3 4p1", DSSP3, p910_dssp3_pin1),
702 GRP_910("dssp3 4p2", DSSP3, p910_dssp3_pin2), 702 GRP_910("dssp3 4p2", DSSP3, p910_dssp3_pin2),
703 GRP_910("dssp3 3p3", DSSP3, p910_dssp3_pin3), 703 GRP_910("dssp3 3p3", DSSP3, p910_dssp3_pin3),
704 GRP_910("ssp0 4p1", SSP0, p910_ssp0_pin1), 704 GRP_910("ssp0 4p1", SSP0, p910_ssp0_pin1),
705 GRP_910("ssp0 4p2", SSP0, p910_ssp0_pin2), 705 GRP_910("ssp0 4p2", SSP0, p910_ssp0_pin2),
706 GRP_910("ssp0 4p3", SSP0, p910_ssp0_pin3), 706 GRP_910("ssp0 4p3", SSP0, p910_ssp0_pin3),
707 GRP_910("ssp0 4p4", SSP0, p910_ssp0_pin4), 707 GRP_910("ssp0 4p4", SSP0, p910_ssp0_pin4),
708 GRP_910("ssp1 4p1", SSP1, p910_ssp1_pin1), 708 GRP_910("ssp1 4p1", SSP1, p910_ssp1_pin1),
709 GRP_910("ssp1 5p2", SSP1, p910_ssp1_pin2), 709 GRP_910("ssp1 5p2", SSP1, p910_ssp1_pin2),
710 GRP_910("ssp2 4p1", SSP2, p910_ssp2_pin1), 710 GRP_910("ssp2 4p1", SSP2, p910_ssp2_pin1),
711 GRP_910("ssp2 4p2", SSP2, p910_ssp2_pin2), 711 GRP_910("ssp2 4p2", SSP2, p910_ssp2_pin2),
712 GRP_910("ssp2 4p3", SSP2, p910_ssp2_pin3), 712 GRP_910("ssp2 4p3", SSP2, p910_ssp2_pin3),
713 GRP_910("ssp2 4p4", SSP2, p910_ssp2_pin4), 713 GRP_910("ssp2 4p4", SSP2, p910_ssp2_pin4),
714 GRP_910("gssp", GSSP, p910_gssp_pin1), 714 GRP_910("gssp", GSSP, p910_gssp_pin1),
715 GRP_910("pwm0", PWM0, p910_pwm0_pin1), 715 GRP_910("pwm0", PWM0, p910_pwm0_pin1),
716 GRP_910("pwm1-1", PWM1, p910_pwm1_pin1), 716 GRP_910("pwm1-1", PWM1, p910_pwm1_pin1),
717 GRP_910("pwm1-2", PWM1, p910_pwm1_pin2), 717 GRP_910("pwm1-2", PWM1, p910_pwm1_pin2),
718 GRP_910("pwm2", PWM2, p910_pwm2_pin1), 718 GRP_910("pwm2", PWM2, p910_pwm2_pin1),
719 GRP_910("pwm3-1", PWM3, p910_pwm3_pin1), 719 GRP_910("pwm3-1", PWM3, p910_pwm3_pin1),
720 GRP_910("pwm3-2", PWM3, p910_pwm3_pin2), 720 GRP_910("pwm3-2", PWM3, p910_pwm3_pin2),
721 GRP_910("pwm3-3", PWM3, p910_pwm3_pin3), 721 GRP_910("pwm3-3", PWM3, p910_pwm3_pin3),
722 GRP_910("pri jtag", PRI_JTAG, p910_pri_jtag_pin1), 722 GRP_910("pri jtag", PRI_JTAG, p910_pri_jtag_pin1),
723 GRP_910("sec1 jtag", SEC1_JTAG, p910_sec1_jtag_pin1), 723 GRP_910("sec1 jtag", SEC1_JTAG, p910_sec1_jtag_pin1),
724 GRP_910("sec2 jtag", SEC2_JTAG, p910_sec2_jtag_pin1), 724 GRP_910("sec2 jtag", SEC2_JTAG, p910_sec2_jtag_pin1),
725 GRP_910("hsl 6p1", HSL, p910_hsl_pin1), 725 GRP_910("hsl 6p1", HSL, p910_hsl_pin1),
726 GRP_910("hsl 6p2", HSL, p910_hsl_pin2), 726 GRP_910("hsl 6p2", HSL, p910_hsl_pin2),
727 GRP_910("hsl 6p3", HSL, p910_hsl_pin3), 727 GRP_910("hsl 6p3", HSL, p910_hsl_pin3),
728 GRP_910("w1-1", ONE_WIRE, p910_w1_pin1), 728 GRP_910("w1-1", ONE_WIRE, p910_w1_pin1),
729 GRP_910("w1-2", ONE_WIRE, p910_w1_pin2), 729 GRP_910("w1-2", ONE_WIRE, p910_w1_pin2),
730 GRP_910("w1-3", ONE_WIRE, p910_w1_pin3), 730 GRP_910("w1-3", ONE_WIRE, p910_w1_pin3),
731 GRP_910("w1-4", ONE_WIRE, p910_w1_pin4), 731 GRP_910("w1-4", ONE_WIRE, p910_w1_pin4),
732 GRP_910("kpmk 16p1", KP_MK, p910_kpmk_pin1), 732 GRP_910("kpmk 16p1", KP_MK, p910_kpmk_pin1),
733 GRP_910("kpmk 11p2", KP_MK, p910_kpmk_pin2), 733 GRP_910("kpmk 11p2", KP_MK, p910_kpmk_pin2),
734 GRP_910("kpdk 8p1", KP_DK, p910_kpdk_pin1), 734 GRP_910("kpdk 8p1", KP_DK, p910_kpdk_pin1),
735 GRP_910("tds 5p1", TDS, p910_tds_pin1), 735 GRP_910("tds 5p1", TDS, p910_tds_pin1),
736 GRP_910("tds 4p2", TDS, p910_tds_pin2), 736 GRP_910("tds 4p2", TDS, p910_tds_pin2),
737 GRP_910("tb 4p1", TB, p910_tb_pin1), 737 GRP_910("tb 4p1", TB, p910_tb_pin1),
738 GRP_910("tb 4p2", TB, p910_tb_pin2), 738 GRP_910("tb 4p2", TB, p910_tb_pin2),
739 GRP_910("tb 4p3", TB, p910_tb_pin3), 739 GRP_910("tb 4p3", TB, p910_tb_pin3),
740 GRP_910("ext dma0-1", EXT_DMA, p910_ext_dma0_pin1), 740 GRP_910("ext dma0-1", EXT_DMA, p910_ext_dma0_pin1),
741 GRP_910("ext dma0-2", EXT_DMA, p910_ext_dma0_pin2), 741 GRP_910("ext dma0-2", EXT_DMA, p910_ext_dma0_pin2),
742 GRP_910("ext dma0-3", EXT_DMA, p910_ext_dma0_pin3), 742 GRP_910("ext dma0-3", EXT_DMA, p910_ext_dma0_pin3),
743 GRP_910("ext dma1-1", EXT_DMA, p910_ext_dma1_pin1), 743 GRP_910("ext dma1-1", EXT_DMA, p910_ext_dma1_pin1),
744 GRP_910("ext dma1-2", EXT_DMA, p910_ext_dma1_pin2), 744 GRP_910("ext dma1-2", EXT_DMA, p910_ext_dma1_pin2),
745 GRP_910("ext dma1-3", EXT_DMA, p910_ext_dma1_pin3), 745 GRP_910("ext dma1-3", EXT_DMA, p910_ext_dma1_pin3),
746 GRP_910("ext dma2", EXT_DMA, p910_ext_dma2_pin1), 746 GRP_910("ext dma2", EXT_DMA, p910_ext_dma2_pin1),
747 GRP_910("ext0 int-1", EXT_INT, p910_ext0_int_pin1), 747 GRP_910("ext0 int-1", EXT_INT, p910_ext0_int_pin1),
748 GRP_910("ext0 int-2", EXT_INT, p910_ext0_int_pin2), 748 GRP_910("ext0 int-2", EXT_INT, p910_ext0_int_pin2),
749 GRP_910("ext1 int-1", EXT_INT, p910_ext1_int_pin1), 749 GRP_910("ext1 int-1", EXT_INT, p910_ext1_int_pin1),
750 GRP_910("ext1 int-2", EXT_INT, p910_ext1_int_pin2), 750 GRP_910("ext1 int-2", EXT_INT, p910_ext1_int_pin2),
751 GRP_910("ext2 int-1", EXT_INT, p910_ext2_int_pin1), 751 GRP_910("ext2 int-1", EXT_INT, p910_ext2_int_pin1),
752 GRP_910("ext2 int-2", EXT_INT, p910_ext2_int_pin2), 752 GRP_910("ext2 int-2", EXT_INT, p910_ext2_int_pin2),
753 GRP_910("dac st23-1", DAC_ST23, p910_dac_st23_pin1), 753 GRP_910("dac st23-1", DAC_ST23, p910_dac_st23_pin1),
754 GRP_910("dac st23-2", DAC_ST23, p910_dac_st23_pin2), 754 GRP_910("dac st23-2", DAC_ST23, p910_dac_st23_pin2),
755 GRP_910("dac st23-3", DAC_ST23, p910_dac_st23_pin3), 755 GRP_910("dac st23-3", DAC_ST23, p910_dac_st23_pin3),
756 GRP_910("dac st23-4", DAC_ST23, p910_dac_st23_pin4), 756 GRP_910("dac st23-4", DAC_ST23, p910_dac_st23_pin4),
757 GRP_910("vcxo out-1", VCXO_OUT, p910_vcxo_out_pin1), 757 GRP_910("vcxo out-1", VCXO_OUT, p910_vcxo_out_pin1),
758 GRP_910("vcxo out-2", VCXO_OUT, p910_vcxo_out_pin2), 758 GRP_910("vcxo out-2", VCXO_OUT, p910_vcxo_out_pin2),
759 GRP_910("vcxo out-3", VCXO_OUT, p910_vcxo_out_pin3), 759 GRP_910("vcxo out-3", VCXO_OUT, p910_vcxo_out_pin3),
760 GRP_910("vcxo req-1", VCXO_REQ, p910_vcxo_req_pin1), 760 GRP_910("vcxo req-1", VCXO_REQ, p910_vcxo_req_pin1),
761 GRP_910("vcxo req-2", VCXO_REQ, p910_vcxo_req_pin2), 761 GRP_910("vcxo req-2", VCXO_REQ, p910_vcxo_req_pin2),
762 GRP_910("vcxo out2-1", VCXO_OUT2, p910_vcxo_out2_pin1), 762 GRP_910("vcxo out2-1", VCXO_OUT2, p910_vcxo_out2_pin1),
763 GRP_910("vcxo out2-2", VCXO_OUT2, p910_vcxo_out2_pin2), 763 GRP_910("vcxo out2-2", VCXO_OUT2, p910_vcxo_out2_pin2),
764 GRP_910("vcxo req2", VCXO_REQ2, p910_vcxo_req2_pin1), 764 GRP_910("vcxo req2", VCXO_REQ2, p910_vcxo_req2_pin1),
765 GRP_910("ulpi", ULPI, p910_ulpi_pin1), 765 GRP_910("ulpi", ULPI, p910_ulpi_pin1),
766 GRP_910("nand", NAND, p910_nand_pin1), 766 GRP_910("nand", NAND, p910_nand_pin1),
767 GRP_910("gpio0-1", GPIO, p910_gpio0_pin1), 767 GRP_910("gpio0-1", GPIO, p910_gpio0_pin1),
768 GRP_910("gpio0-2", GPIO, p910_gpio0_pin2), 768 GRP_910("gpio0-2", GPIO, p910_gpio0_pin2),
769 GRP_910("gpio1-1", GPIO, p910_gpio1_pin1), 769 GRP_910("gpio1-1", GPIO, p910_gpio1_pin1),
770 GRP_910("gpio1-2", GPIO, p910_gpio1_pin2), 770 GRP_910("gpio1-2", GPIO, p910_gpio1_pin2),
771 GRP_910("gpio2-1", GPIO, p910_gpio2_pin1), 771 GRP_910("gpio2-1", GPIO, p910_gpio2_pin1),
772 GRP_910("gpio2-2", GPIO, p910_gpio2_pin2), 772 GRP_910("gpio2-2", GPIO, p910_gpio2_pin2),
773 GRP_910("gpio3-1", GPIO, p910_gpio3_pin1), 773 GRP_910("gpio3-1", GPIO, p910_gpio3_pin1),
774 GRP_910("gpio3-2", GPIO, p910_gpio3_pin2), 774 GRP_910("gpio3-2", GPIO, p910_gpio3_pin2),
775 GRP_910("gpio20-1", GPIO, p910_gpio20_pin1), 775 GRP_910("gpio20-1", GPIO, p910_gpio20_pin1),
776 GRP_910("gpio20-2", GPIO, p910_gpio20_pin2), 776 GRP_910("gpio20-2", GPIO, p910_gpio20_pin2),
777 GRP_910("gpio21-1", GPIO, p910_gpio21_pin1), 777 GRP_910("gpio21-1", GPIO, p910_gpio21_pin1),
778 GRP_910("gpio21-2", GPIO, p910_gpio21_pin2), 778 GRP_910("gpio21-2", GPIO, p910_gpio21_pin2),
779 GRP_910("gpio22-1", GPIO, p910_gpio22_pin1), 779 GRP_910("gpio22-1", GPIO, p910_gpio22_pin1),
780 GRP_910("gpio22-2", GPIO, p910_gpio22_pin2), 780 GRP_910("gpio22-2", GPIO, p910_gpio22_pin2),
781 GRP_910("gpio23-1", GPIO, p910_gpio23_pin1), 781 GRP_910("gpio23-1", GPIO, p910_gpio23_pin1),
782 GRP_910("gpio23-2", GPIO, p910_gpio23_pin2), 782 GRP_910("gpio23-2", GPIO, p910_gpio23_pin2),
783 GRP_910("gpio24-1", GPIO, p910_gpio24_pin1), 783 GRP_910("gpio24-1", GPIO, p910_gpio24_pin1),
784 GRP_910("gpio24-2", GPIO, p910_gpio24_pin2), 784 GRP_910("gpio24-2", GPIO, p910_gpio24_pin2),
785 GRP_910("gpio25-1", GPIO, p910_gpio25_pin1), 785 GRP_910("gpio25-1", GPIO, p910_gpio25_pin1),
786 GRP_910("gpio25-2", GPIO, p910_gpio25_pin2), 786 GRP_910("gpio25-2", GPIO, p910_gpio25_pin2),
787 GRP_910("gpio26-1", GPIO, p910_gpio26_pin1), 787 GRP_910("gpio26-1", GPIO, p910_gpio26_pin1),
788 GRP_910("gpio26-2", GPIO, p910_gpio26_pin2), 788 GRP_910("gpio26-2", GPIO, p910_gpio26_pin2),
789 GRP_910("gpio27-1", GPIO, p910_gpio27_pin1), 789 GRP_910("gpio27-1", GPIO, p910_gpio27_pin1),
790 GRP_910("gpio27-2", GPIO, p910_gpio27_pin2), 790 GRP_910("gpio27-2", GPIO, p910_gpio27_pin2),
791 GRP_910("gpio85-1", GPIO, p910_gpio85_pin1), 791 GRP_910("gpio85-1", GPIO, p910_gpio85_pin1),
792 GRP_910("gpio85-2", GPIO, p910_gpio85_pin2), 792 GRP_910("gpio85-2", GPIO, p910_gpio85_pin2),
793 GRP_910("gpio86-1", GPIO, p910_gpio86_pin1), 793 GRP_910("gpio86-1", GPIO, p910_gpio86_pin1),
794 GRP_910("gpio86-2", GPIO, p910_gpio86_pin2), 794 GRP_910("gpio86-2", GPIO, p910_gpio86_pin2),
795 GRP_910("gpio87-1", GPIO, p910_gpio87_pin1), 795 GRP_910("gpio87-1", GPIO, p910_gpio87_pin1),
796 GRP_910("gpio87-2", GPIO, p910_gpio87_pin2), 796 GRP_910("gpio87-2", GPIO, p910_gpio87_pin2),
797 GRP_910("gpio88-1", GPIO, p910_gpio88_pin1), 797 GRP_910("gpio88-1", GPIO, p910_gpio88_pin1),
798 GRP_910("gpio88-2", GPIO, p910_gpio88_pin2), 798 GRP_910("gpio88-2", GPIO, p910_gpio88_pin2),
799 GRP_910("gpio89-1", GPIO, p910_gpio89_pin1), 799 GRP_910("gpio89-1", GPIO, p910_gpio89_pin1),
800 GRP_910("gpio89-2", GPIO, p910_gpio89_pin2), 800 GRP_910("gpio89-2", GPIO, p910_gpio89_pin2),
801 GRP_910("gpio90-1", GPIO, p910_gpio90_pin1), 801 GRP_910("gpio90-1", GPIO, p910_gpio90_pin1),
802 GRP_910("gpio90-2", GPIO, p910_gpio90_pin2), 802 GRP_910("gpio90-2", GPIO, p910_gpio90_pin2),
803 GRP_910("gpio91-1", GPIO, p910_gpio91_pin1), 803 GRP_910("gpio91-1", GPIO, p910_gpio91_pin1),
804 GRP_910("gpio91-2", GPIO, p910_gpio91_pin2), 804 GRP_910("gpio91-2", GPIO, p910_gpio91_pin2),
805 GRP_910("gpio92-1", GPIO, p910_gpio92_pin1), 805 GRP_910("gpio92-1", GPIO, p910_gpio92_pin1),
806 GRP_910("gpio92-2", GPIO, p910_gpio92_pin2), 806 GRP_910("gpio92-2", GPIO, p910_gpio92_pin2),
807 }; 807 };
808 808
809 static const char * const p910_usim2_grps[] = {"usim2 3p1", "usim2 3p2"}; 809 static const char * const p910_usim2_grps[] = {"usim2 3p1", "usim2 3p2"};
810 static const char * const p910_mmc1_grps[] = {"mmc1 12p"}; 810 static const char * const p910_mmc1_grps[] = {"mmc1 12p"};
811 static const char * const p910_mmc2_grps[] = {"mmc2 10p"}; 811 static const char * const p910_mmc2_grps[] = {"mmc2 10p"};
812 static const char * const p910_mmc3_grps[] = {"mmc3 6p", "mmc3 10p"}; 812 static const char * const p910_mmc3_grps[] = {"mmc3 6p", "mmc3 10p"};
813 static const char * const p910_uart0_grps[] = {"uart0 4p"}; 813 static const char * const p910_uart0_grps[] = {"uart0 4p"};
814 static const char * const p910_uart1_grps[] = {"uart1 2p1", "uart1 2p2", 814 static const char * const p910_uart1_grps[] = {"uart1 2p1", "uart1 2p2",
815 "uart1 2p3", "uart1 4p4", "uart1 4p5"}; 815 "uart1 2p3", "uart1 4p4", "uart1 4p5"};
816 static const char * const p910_uart2_grps[] = {"uart2 2p1", "uart2 2p2", 816 static const char * const p910_uart2_grps[] = {"uart2 2p1", "uart2 2p2",
817 "uart2 4p3", "uart2 4p4"}; 817 "uart2 4p3", "uart2 4p4"};
818 static const char * const p910_twsi_grps[] = {"twsi 2p1", "twsi 2p2", 818 static const char * const p910_twsi_grps[] = {"twsi 2p1", "twsi 2p2",
819 "twsi 2p3"}; 819 "twsi 2p3"};
820 static const char * const p910_ccic_grps[] = {"ccic"}; 820 static const char * const p910_ccic_grps[] = {"ccic"};
821 static const char * const p910_lcd_grps[] = {"lcd"}; 821 static const char * const p910_lcd_grps[] = {"lcd"};
822 static const char * const p910_spi_grps[] = {"spi 4p1", "spi 4p2", "spi 5p3", 822 static const char * const p910_spi_grps[] = {"spi 4p1", "spi 4p2", "spi 5p3",
823 "spi 5p4"}; 823 "spi 5p4"};
824 static const char * const p910_dssp2_grps[] = {"dssp2 4p1", "dssp2 4p2", 824 static const char * const p910_dssp2_grps[] = {"dssp2 4p1", "dssp2 4p2",
825 "dssp2 3p3"}; 825 "dssp2 3p3"};
826 static const char * const p910_dssp3_grps[] = {"dssp3 4p1", "dssp3 4p2", 826 static const char * const p910_dssp3_grps[] = {"dssp3 4p1", "dssp3 4p2",
827 "dssp3 3p3"}; 827 "dssp3 3p3"};
828 static const char * const p910_ssp0_grps[] = {"ssp0 4p1", "ssp0 4p2", 828 static const char * const p910_ssp0_grps[] = {"ssp0 4p1", "ssp0 4p2",
829 "ssp0 4p3", "ssp0 4p4"}; 829 "ssp0 4p3", "ssp0 4p4"};
830 static const char * const p910_ssp1_grps[] = {"ssp1 4p1", "ssp1 5p2"}; 830 static const char * const p910_ssp1_grps[] = {"ssp1 4p1", "ssp1 5p2"};
831 static const char * const p910_ssp2_grps[] = {"ssp2 4p1", "ssp2 4p2", 831 static const char * const p910_ssp2_grps[] = {"ssp2 4p1", "ssp2 4p2",
832 "ssp2 4p3", "ssp2 4p4"}; 832 "ssp2 4p3", "ssp2 4p4"};
833 static const char * const p910_gssp_grps[] = {"gssp"}; 833 static const char * const p910_gssp_grps[] = {"gssp"};
834 static const char * const p910_pwm0_grps[] = {"pwm0"}; 834 static const char * const p910_pwm0_grps[] = {"pwm0"};
835 static const char * const p910_pwm1_grps[] = {"pwm1-1", "pwm1-2"}; 835 static const char * const p910_pwm1_grps[] = {"pwm1-1", "pwm1-2"};
836 static const char * const p910_pwm2_grps[] = {"pwm2"}; 836 static const char * const p910_pwm2_grps[] = {"pwm2"};
837 static const char * const p910_pwm3_grps[] = {"pwm3-1", "pwm3-2", "pwm3-3"}; 837 static const char * const p910_pwm3_grps[] = {"pwm3-1", "pwm3-2", "pwm3-3"};
838 static const char * const p910_pri_jtag_grps[] = {"pri jtag"}; 838 static const char * const p910_pri_jtag_grps[] = {"pri jtag"};
839 static const char * const p910_sec1_jtag_grps[] = {"sec1 jtag"}; 839 static const char * const p910_sec1_jtag_grps[] = {"sec1 jtag"};
840 static const char * const p910_sec2_jtag_grps[] = {"sec2 jtag"}; 840 static const char * const p910_sec2_jtag_grps[] = {"sec2 jtag"};
841 static const char * const p910_hsl_grps[] = {"hsl 6p1", "hsl 6p2", "hsl 6p3"}; 841 static const char * const p910_hsl_grps[] = {"hsl 6p1", "hsl 6p2", "hsl 6p3"};
842 static const char * const p910_w1_grps[] = {"w1-1", "w1-2", "w1-3", "w1-4"}; 842 static const char * const p910_w1_grps[] = {"w1-1", "w1-2", "w1-3", "w1-4"};
843 static const char * const p910_kpmk_grps[] = {"kpmk 16p1", "kpmk 11p2"}; 843 static const char * const p910_kpmk_grps[] = {"kpmk 16p1", "kpmk 11p2"};
844 static const char * const p910_kpdk_grps[] = {"kpdk 8p1"}; 844 static const char * const p910_kpdk_grps[] = {"kpdk 8p1"};
845 static const char * const p910_tds_grps[] = {"tds 5p1", "tds 4p2"}; 845 static const char * const p910_tds_grps[] = {"tds 5p1", "tds 4p2"};
846 static const char * const p910_tb_grps[] = {"tb 4p1", "tb 4p2", "tb 4p3"}; 846 static const char * const p910_tb_grps[] = {"tb 4p1", "tb 4p2", "tb 4p3"};
847 static const char * const p910_dma0_grps[] = {"ext dma0-1", "ext dma0-2", 847 static const char * const p910_dma0_grps[] = {"ext dma0-1", "ext dma0-2",
848 "ext dma0-3"}; 848 "ext dma0-3"};
849 static const char * const p910_dma1_grps[] = {"ext dma1-1", "ext dma1-2", 849 static const char * const p910_dma1_grps[] = {"ext dma1-1", "ext dma1-2",
850 "ext dma1-3"}; 850 "ext dma1-3"};
851 static const char * const p910_dma2_grps[] = {"ext dma2"}; 851 static const char * const p910_dma2_grps[] = {"ext dma2"};
852 static const char * const p910_int0_grps[] = {"ext0 int-1", "ext0 int-2"}; 852 static const char * const p910_int0_grps[] = {"ext0 int-1", "ext0 int-2"};
853 static const char * const p910_int1_grps[] = {"ext1 int-1", "ext1 int-2"}; 853 static const char * const p910_int1_grps[] = {"ext1 int-1", "ext1 int-2"};
854 static const char * const p910_int2_grps[] = {"ext2 int-1", "ext2 int-2"}; 854 static const char * const p910_int2_grps[] = {"ext2 int-1", "ext2 int-2"};
855 static const char * const p910_dac_st23_grps[] = {"dac st23-1", "dac st23-2", 855 static const char * const p910_dac_st23_grps[] = {"dac st23-1", "dac st23-2",
856 "dac st23-3", "dac st23-4"}; 856 "dac st23-3", "dac st23-4"};
857 static const char * const p910_vcxo_out_grps[] = {"vcxo out-1", "vcxo out-2", 857 static const char * const p910_vcxo_out_grps[] = {"vcxo out-1", "vcxo out-2",
858 "vcxo out-3"}; 858 "vcxo out-3"};
859 static const char * const p910_vcxo_req_grps[] = {"vcxo req-1", "vcxo req-2"}; 859 static const char * const p910_vcxo_req_grps[] = {"vcxo req-1", "vcxo req-2"};
860 static const char * const p910_vcxo_out2_grps[] = {"vcxo out2-1", 860 static const char * const p910_vcxo_out2_grps[] = {"vcxo out2-1",
861 "vcxo out2-2"}; 861 "vcxo out2-2"};
862 static const char * const p910_vcxo_req2_grps[] = {"vcxo req2"}; 862 static const char * const p910_vcxo_req2_grps[] = {"vcxo req2"};
863 static const char * const p910_ulpi_grps[] = {"ulpi"}; 863 static const char * const p910_ulpi_grps[] = {"ulpi"};
864 static const char * const p910_nand_grps[] = {"nand"}; 864 static const char * const p910_nand_grps[] = {"nand"};
865 static const char * const p910_gpio0_grps[] = {"gpio0-1", "gpio0-2"}; 865 static const char * const p910_gpio0_grps[] = {"gpio0-1", "gpio0-2"};
866 static const char * const p910_gpio1_grps[] = {"gpio1-1", "gpio1-2"}; 866 static const char * const p910_gpio1_grps[] = {"gpio1-1", "gpio1-2"};
867 static const char * const p910_gpio2_grps[] = {"gpio2-1", "gpio2-2"}; 867 static const char * const p910_gpio2_grps[] = {"gpio2-1", "gpio2-2"};
868 static const char * const p910_gpio3_grps[] = {"gpio3-1", "gpio3-2"}; 868 static const char * const p910_gpio3_grps[] = {"gpio3-1", "gpio3-2"};
869 static const char * const p910_gpio20_grps[] = {"gpio20-1", "gpio20-2"}; 869 static const char * const p910_gpio20_grps[] = {"gpio20-1", "gpio20-2"};
870 static const char * const p910_gpio21_grps[] = {"gpio21-1", "gpio21-2"}; 870 static const char * const p910_gpio21_grps[] = {"gpio21-1", "gpio21-2"};
871 static const char * const p910_gpio22_grps[] = {"gpio22-1", "gpio22-2"}; 871 static const char * const p910_gpio22_grps[] = {"gpio22-1", "gpio22-2"};
872 static const char * const p910_gpio23_grps[] = {"gpio23-1", "gpio23-2"}; 872 static const char * const p910_gpio23_grps[] = {"gpio23-1", "gpio23-2"};
873 static const char * const p910_gpio24_grps[] = {"gpio24-1", "gpio24-2"}; 873 static const char * const p910_gpio24_grps[] = {"gpio24-1", "gpio24-2"};
874 static const char * const p910_gpio25_grps[] = {"gpio25-1", "gpio25-2"}; 874 static const char * const p910_gpio25_grps[] = {"gpio25-1", "gpio25-2"};
875 static const char * const p910_gpio26_grps[] = {"gpio26-1", "gpio26-2"}; 875 static const char * const p910_gpio26_grps[] = {"gpio26-1", "gpio26-2"};
876 static const char * const p910_gpio27_grps[] = {"gpio27-1", "gpio27-2"}; 876 static const char * const p910_gpio27_grps[] = {"gpio27-1", "gpio27-2"};
877 static const char * const p910_gpio85_grps[] = {"gpio85-1", "gpio85-2"}; 877 static const char * const p910_gpio85_grps[] = {"gpio85-1", "gpio85-2"};
878 static const char * const p910_gpio86_grps[] = {"gpio86-1", "gpio86-2"}; 878 static const char * const p910_gpio86_grps[] = {"gpio86-1", "gpio86-2"};
879 static const char * const p910_gpio87_grps[] = {"gpio87-1", "gpio87-2"}; 879 static const char * const p910_gpio87_grps[] = {"gpio87-1", "gpio87-2"};
880 static const char * const p910_gpio88_grps[] = {"gpio88-1", "gpio88-2"}; 880 static const char * const p910_gpio88_grps[] = {"gpio88-1", "gpio88-2"};
881 static const char * const p910_gpio89_grps[] = {"gpio89-1", "gpio89-2"}; 881 static const char * const p910_gpio89_grps[] = {"gpio89-1", "gpio89-2"};
882 static const char * const p910_gpio90_grps[] = {"gpio90-1", "gpio90-2"}; 882 static const char * const p910_gpio90_grps[] = {"gpio90-1", "gpio90-2"};
883 static const char * const p910_gpio91_grps[] = {"gpio91-1", "gpio91-2"}; 883 static const char * const p910_gpio91_grps[] = {"gpio91-1", "gpio91-2"};
884 static const char * const p910_gpio92_grps[] = {"gpio92-1", "gpio92-2"}; 884 static const char * const p910_gpio92_grps[] = {"gpio92-1", "gpio92-2"};
885 885
886 static struct pxa3xx_pmx_func pxa910_funcs[] = { 886 static struct pxa3xx_pmx_func pxa910_funcs[] = {
887 {"usim2", ARRAY_AND_SIZE(p910_usim2_grps)}, 887 {"usim2", ARRAY_AND_SIZE(p910_usim2_grps)},
888 {"mmc1", ARRAY_AND_SIZE(p910_mmc1_grps)}, 888 {"mmc1", ARRAY_AND_SIZE(p910_mmc1_grps)},
889 {"mmc2", ARRAY_AND_SIZE(p910_mmc2_grps)}, 889 {"mmc2", ARRAY_AND_SIZE(p910_mmc2_grps)},
890 {"mmc3", ARRAY_AND_SIZE(p910_mmc3_grps)}, 890 {"mmc3", ARRAY_AND_SIZE(p910_mmc3_grps)},
891 {"uart0", ARRAY_AND_SIZE(p910_uart0_grps)}, 891 {"uart0", ARRAY_AND_SIZE(p910_uart0_grps)},
892 {"uart1", ARRAY_AND_SIZE(p910_uart1_grps)}, 892 {"uart1", ARRAY_AND_SIZE(p910_uart1_grps)},
893 {"uart2", ARRAY_AND_SIZE(p910_uart2_grps)}, 893 {"uart2", ARRAY_AND_SIZE(p910_uart2_grps)},
894 {"twsi", ARRAY_AND_SIZE(p910_twsi_grps)}, 894 {"twsi", ARRAY_AND_SIZE(p910_twsi_grps)},
895 {"ccic", ARRAY_AND_SIZE(p910_ccic_grps)}, 895 {"ccic", ARRAY_AND_SIZE(p910_ccic_grps)},
896 {"lcd", ARRAY_AND_SIZE(p910_lcd_grps)}, 896 {"lcd", ARRAY_AND_SIZE(p910_lcd_grps)},
897 {"spi", ARRAY_AND_SIZE(p910_spi_grps)}, 897 {"spi", ARRAY_AND_SIZE(p910_spi_grps)},
898 {"dssp2", ARRAY_AND_SIZE(p910_dssp2_grps)}, 898 {"dssp2", ARRAY_AND_SIZE(p910_dssp2_grps)},
899 {"dssp3", ARRAY_AND_SIZE(p910_dssp3_grps)}, 899 {"dssp3", ARRAY_AND_SIZE(p910_dssp3_grps)},
900 {"ssp0", ARRAY_AND_SIZE(p910_ssp0_grps)}, 900 {"ssp0", ARRAY_AND_SIZE(p910_ssp0_grps)},
901 {"ssp1", ARRAY_AND_SIZE(p910_ssp1_grps)}, 901 {"ssp1", ARRAY_AND_SIZE(p910_ssp1_grps)},
902 {"ssp2", ARRAY_AND_SIZE(p910_ssp2_grps)}, 902 {"ssp2", ARRAY_AND_SIZE(p910_ssp2_grps)},
903 {"gssp", ARRAY_AND_SIZE(p910_gssp_grps)}, 903 {"gssp", ARRAY_AND_SIZE(p910_gssp_grps)},
904 {"pwm0", ARRAY_AND_SIZE(p910_pwm0_grps)}, 904 {"pwm0", ARRAY_AND_SIZE(p910_pwm0_grps)},
905 {"pwm1", ARRAY_AND_SIZE(p910_pwm1_grps)}, 905 {"pwm1", ARRAY_AND_SIZE(p910_pwm1_grps)},
906 {"pwm2", ARRAY_AND_SIZE(p910_pwm2_grps)}, 906 {"pwm2", ARRAY_AND_SIZE(p910_pwm2_grps)},
907 {"pwm3", ARRAY_AND_SIZE(p910_pwm3_grps)}, 907 {"pwm3", ARRAY_AND_SIZE(p910_pwm3_grps)},
908 {"pri_jtag", ARRAY_AND_SIZE(p910_pri_jtag_grps)}, 908 {"pri_jtag", ARRAY_AND_SIZE(p910_pri_jtag_grps)},
909 {"sec1_jtag", ARRAY_AND_SIZE(p910_sec1_jtag_grps)}, 909 {"sec1_jtag", ARRAY_AND_SIZE(p910_sec1_jtag_grps)},
910 {"sec2_jtag", ARRAY_AND_SIZE(p910_sec2_jtag_grps)}, 910 {"sec2_jtag", ARRAY_AND_SIZE(p910_sec2_jtag_grps)},
911 {"hsl", ARRAY_AND_SIZE(p910_hsl_grps)}, 911 {"hsl", ARRAY_AND_SIZE(p910_hsl_grps)},
912 {"w1", ARRAY_AND_SIZE(p910_w1_grps)}, 912 {"w1", ARRAY_AND_SIZE(p910_w1_grps)},
913 {"kpmk", ARRAY_AND_SIZE(p910_kpmk_grps)}, 913 {"kpmk", ARRAY_AND_SIZE(p910_kpmk_grps)},
914 {"kpdk", ARRAY_AND_SIZE(p910_kpdk_grps)}, 914 {"kpdk", ARRAY_AND_SIZE(p910_kpdk_grps)},
915 {"tds", ARRAY_AND_SIZE(p910_tds_grps)}, 915 {"tds", ARRAY_AND_SIZE(p910_tds_grps)},
916 {"tb", ARRAY_AND_SIZE(p910_tb_grps)}, 916 {"tb", ARRAY_AND_SIZE(p910_tb_grps)},
917 {"dma0", ARRAY_AND_SIZE(p910_dma0_grps)}, 917 {"dma0", ARRAY_AND_SIZE(p910_dma0_grps)},
918 {"dma1", ARRAY_AND_SIZE(p910_dma1_grps)}, 918 {"dma1", ARRAY_AND_SIZE(p910_dma1_grps)},
919 {"dma2", ARRAY_AND_SIZE(p910_dma2_grps)}, 919 {"dma2", ARRAY_AND_SIZE(p910_dma2_grps)},
920 {"int0", ARRAY_AND_SIZE(p910_int0_grps)}, 920 {"int0", ARRAY_AND_SIZE(p910_int0_grps)},
921 {"int1", ARRAY_AND_SIZE(p910_int1_grps)}, 921 {"int1", ARRAY_AND_SIZE(p910_int1_grps)},
922 {"int2", ARRAY_AND_SIZE(p910_int2_grps)}, 922 {"int2", ARRAY_AND_SIZE(p910_int2_grps)},
923 {"dac_st23", ARRAY_AND_SIZE(p910_dac_st23_grps)}, 923 {"dac_st23", ARRAY_AND_SIZE(p910_dac_st23_grps)},
924 {"vcxo_out", ARRAY_AND_SIZE(p910_vcxo_out_grps)}, 924 {"vcxo_out", ARRAY_AND_SIZE(p910_vcxo_out_grps)},
925 {"vcxo_req", ARRAY_AND_SIZE(p910_vcxo_req_grps)}, 925 {"vcxo_req", ARRAY_AND_SIZE(p910_vcxo_req_grps)},
926 {"vcxo_out2", ARRAY_AND_SIZE(p910_vcxo_out2_grps)}, 926 {"vcxo_out2", ARRAY_AND_SIZE(p910_vcxo_out2_grps)},
927 {"vcxo_req2", ARRAY_AND_SIZE(p910_vcxo_req2_grps)}, 927 {"vcxo_req2", ARRAY_AND_SIZE(p910_vcxo_req2_grps)},
928 {"ulpi", ARRAY_AND_SIZE(p910_ulpi_grps)}, 928 {"ulpi", ARRAY_AND_SIZE(p910_ulpi_grps)},
929 {"nand", ARRAY_AND_SIZE(p910_nand_grps)}, 929 {"nand", ARRAY_AND_SIZE(p910_nand_grps)},
930 {"gpio0", ARRAY_AND_SIZE(p910_gpio0_grps)}, 930 {"gpio0", ARRAY_AND_SIZE(p910_gpio0_grps)},
931 {"gpio1", ARRAY_AND_SIZE(p910_gpio1_grps)}, 931 {"gpio1", ARRAY_AND_SIZE(p910_gpio1_grps)},
932 {"gpio2", ARRAY_AND_SIZE(p910_gpio2_grps)}, 932 {"gpio2", ARRAY_AND_SIZE(p910_gpio2_grps)},
933 {"gpio3", ARRAY_AND_SIZE(p910_gpio3_grps)}, 933 {"gpio3", ARRAY_AND_SIZE(p910_gpio3_grps)},
934 {"gpio20", ARRAY_AND_SIZE(p910_gpio20_grps)}, 934 {"gpio20", ARRAY_AND_SIZE(p910_gpio20_grps)},
935 {"gpio21", ARRAY_AND_SIZE(p910_gpio21_grps)}, 935 {"gpio21", ARRAY_AND_SIZE(p910_gpio21_grps)},
936 {"gpio22", ARRAY_AND_SIZE(p910_gpio22_grps)}, 936 {"gpio22", ARRAY_AND_SIZE(p910_gpio22_grps)},
937 {"gpio23", ARRAY_AND_SIZE(p910_gpio23_grps)}, 937 {"gpio23", ARRAY_AND_SIZE(p910_gpio23_grps)},
938 {"gpio24", ARRAY_AND_SIZE(p910_gpio24_grps)}, 938 {"gpio24", ARRAY_AND_SIZE(p910_gpio24_grps)},
939 {"gpio25", ARRAY_AND_SIZE(p910_gpio25_grps)}, 939 {"gpio25", ARRAY_AND_SIZE(p910_gpio25_grps)},
940 {"gpio26", ARRAY_AND_SIZE(p910_gpio26_grps)}, 940 {"gpio26", ARRAY_AND_SIZE(p910_gpio26_grps)},
941 {"gpio27", ARRAY_AND_SIZE(p910_gpio27_grps)}, 941 {"gpio27", ARRAY_AND_SIZE(p910_gpio27_grps)},
942 {"gpio85", ARRAY_AND_SIZE(p910_gpio85_grps)}, 942 {"gpio85", ARRAY_AND_SIZE(p910_gpio85_grps)},
943 {"gpio86", ARRAY_AND_SIZE(p910_gpio86_grps)}, 943 {"gpio86", ARRAY_AND_SIZE(p910_gpio86_grps)},
944 {"gpio87", ARRAY_AND_SIZE(p910_gpio87_grps)}, 944 {"gpio87", ARRAY_AND_SIZE(p910_gpio87_grps)},
945 {"gpio88", ARRAY_AND_SIZE(p910_gpio88_grps)}, 945 {"gpio88", ARRAY_AND_SIZE(p910_gpio88_grps)},
946 {"gpio89", ARRAY_AND_SIZE(p910_gpio89_grps)}, 946 {"gpio89", ARRAY_AND_SIZE(p910_gpio89_grps)},
947 {"gpio90", ARRAY_AND_SIZE(p910_gpio90_grps)}, 947 {"gpio90", ARRAY_AND_SIZE(p910_gpio90_grps)},
948 {"gpio91", ARRAY_AND_SIZE(p910_gpio91_grps)}, 948 {"gpio91", ARRAY_AND_SIZE(p910_gpio91_grps)},
949 {"gpio92", ARRAY_AND_SIZE(p910_gpio92_grps)}, 949 {"gpio92", ARRAY_AND_SIZE(p910_gpio92_grps)},
950 }; 950 };
951 951
952 static struct pinctrl_desc pxa910_pctrl_desc = { 952 static struct pinctrl_desc pxa910_pctrl_desc = {
953 .name = "pxa910-pinctrl", 953 .name = "pxa910-pinctrl",
954 .owner = THIS_MODULE, 954 .owner = THIS_MODULE,
955 }; 955 };
956 956
957 static struct pxa3xx_pinmux_info pxa910_info = { 957 static struct pxa3xx_pinmux_info pxa910_info = {
958 .mfp = pxa910_mfp, 958 .mfp = pxa910_mfp,
959 .num_mfp = ARRAY_SIZE(pxa910_mfp), 959 .num_mfp = ARRAY_SIZE(pxa910_mfp),
960 .grps = pxa910_grps, 960 .grps = pxa910_grps,
961 .num_grps = ARRAY_SIZE(pxa910_grps), 961 .num_grps = ARRAY_SIZE(pxa910_grps),
962 .funcs = pxa910_funcs, 962 .funcs = pxa910_funcs,
963 .num_funcs = ARRAY_SIZE(pxa910_funcs), 963 .num_funcs = ARRAY_SIZE(pxa910_funcs),
964 .num_gpio = 128, 964 .num_gpio = 128,
965 .desc = &pxa910_pctrl_desc, 965 .desc = &pxa910_pctrl_desc,
966 .pads = pxa910_pads, 966 .pads = pxa910_pads,
967 .num_pads = ARRAY_SIZE(pxa910_pads), 967 .num_pads = ARRAY_SIZE(pxa910_pads),
968 968
969 .cputype = PINCTRL_PXA910, 969 .cputype = PINCTRL_PXA910,
970 .ds_mask = PXA910_DS_MASK, 970 .ds_mask = PXA910_DS_MASK,
971 .ds_shift = PXA910_DS_SHIFT, 971 .ds_shift = PXA910_DS_SHIFT,
972 }; 972 };
973 973
974 static int __devinit pxa910_pinmux_probe(struct platform_device *pdev) 974 static int __devinit pxa910_pinmux_probe(struct platform_device *pdev)
975 { 975 {
976 return pxa3xx_pinctrl_register(pdev, &pxa910_info); 976 return pxa3xx_pinctrl_register(pdev, &pxa910_info);
977 } 977 }
978 978
979 static int __devexit pxa910_pinmux_remove(struct platform_device *pdev) 979 static int pxa910_pinmux_remove(struct platform_device *pdev)
980 { 980 {
981 return pxa3xx_pinctrl_unregister(pdev); 981 return pxa3xx_pinctrl_unregister(pdev);
982 } 982 }
983 983
984 static struct platform_driver pxa910_pinmux_driver = { 984 static struct platform_driver pxa910_pinmux_driver = {
985 .driver = { 985 .driver = {
986 .name = "pxa910-pinmux", 986 .name = "pxa910-pinmux",
987 .owner = THIS_MODULE, 987 .owner = THIS_MODULE,
988 }, 988 },
989 .probe = pxa910_pinmux_probe, 989 .probe = pxa910_pinmux_probe,
990 .remove = pxa910_pinmux_remove, 990 .remove = pxa910_pinmux_remove,
991 }; 991 };
992 992
993 static int __init pxa910_pinmux_init(void) 993 static int __init pxa910_pinmux_init(void)
994 { 994 {
995 return platform_driver_register(&pxa910_pinmux_driver); 995 return platform_driver_register(&pxa910_pinmux_driver);
996 } 996 }
997 core_initcall_sync(pxa910_pinmux_init); 997 core_initcall_sync(pxa910_pinmux_init);
998 998
999 static void __exit pxa910_pinmux_exit(void) 999 static void __exit pxa910_pinmux_exit(void)
1000 { 1000 {
1001 platform_driver_unregister(&pxa910_pinmux_driver); 1001 platform_driver_unregister(&pxa910_pinmux_driver);
1002 } 1002 }
1003 module_exit(pxa910_pinmux_exit); 1003 module_exit(pxa910_pinmux_exit);
1004 1004
1005 MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com>"); 1005 MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com>");
1006 MODULE_DESCRIPTION("PXA3xx pin control driver"); 1006 MODULE_DESCRIPTION("PXA3xx pin control driver");
1007 MODULE_LICENSE("GPL v2"); 1007 MODULE_LICENSE("GPL v2");
1008 1008
drivers/pinctrl/pinctrl-single.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Generic device tree based pinctrl driver for one register per pin 2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers 3 * type pinmux controllers
4 * 4 *
5 * Copyright (C) 2012 Texas Instruments, Inc. 5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/init.h> 12 #include <linux/init.h>
13 #include <linux/module.h> 13 #include <linux/module.h>
14 #include <linux/io.h> 14 #include <linux/io.h>
15 #include <linux/slab.h> 15 #include <linux/slab.h>
16 #include <linux/err.h> 16 #include <linux/err.h>
17 #include <linux/list.h> 17 #include <linux/list.h>
18 18
19 #include <linux/of.h> 19 #include <linux/of.h>
20 #include <linux/of_device.h> 20 #include <linux/of_device.h>
21 #include <linux/of_address.h> 21 #include <linux/of_address.h>
22 22
23 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinmux.h>
25 25
26 #include "core.h" 26 #include "core.h"
27 27
28 #define DRIVER_NAME "pinctrl-single" 28 #define DRIVER_NAME "pinctrl-single"
29 #define PCS_MUX_PINS_NAME "pinctrl-single,pins" 29 #define PCS_MUX_PINS_NAME "pinctrl-single,pins"
30 #define PCS_MUX_BITS_NAME "pinctrl-single,bits" 30 #define PCS_MUX_BITS_NAME "pinctrl-single,bits"
31 #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) 31 #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1)
32 #define PCS_OFF_DISABLED ~0U 32 #define PCS_OFF_DISABLED ~0U
33 33
34 /** 34 /**
35 * struct pcs_pingroup - pingroups for a function 35 * struct pcs_pingroup - pingroups for a function
36 * @np: pingroup device node pointer 36 * @np: pingroup device node pointer
37 * @name: pingroup name 37 * @name: pingroup name
38 * @gpins: array of the pins in the group 38 * @gpins: array of the pins in the group
39 * @ngpins: number of pins in the group 39 * @ngpins: number of pins in the group
40 * @node: list node 40 * @node: list node
41 */ 41 */
42 struct pcs_pingroup { 42 struct pcs_pingroup {
43 struct device_node *np; 43 struct device_node *np;
44 const char *name; 44 const char *name;
45 int *gpins; 45 int *gpins;
46 int ngpins; 46 int ngpins;
47 struct list_head node; 47 struct list_head node;
48 }; 48 };
49 49
50 /** 50 /**
51 * struct pcs_func_vals - mux function register offset and value pair 51 * struct pcs_func_vals - mux function register offset and value pair
52 * @reg: register virtual address 52 * @reg: register virtual address
53 * @val: register value 53 * @val: register value
54 */ 54 */
55 struct pcs_func_vals { 55 struct pcs_func_vals {
56 void __iomem *reg; 56 void __iomem *reg;
57 unsigned val; 57 unsigned val;
58 unsigned mask; 58 unsigned mask;
59 }; 59 };
60 60
61 /** 61 /**
62 * struct pcs_function - pinctrl function 62 * struct pcs_function - pinctrl function
63 * @name: pinctrl function name 63 * @name: pinctrl function name
64 * @vals: register and vals array 64 * @vals: register and vals array
65 * @nvals: number of entries in vals array 65 * @nvals: number of entries in vals array
66 * @pgnames: array of pingroup names the function uses 66 * @pgnames: array of pingroup names the function uses
67 * @npgnames: number of pingroup names the function uses 67 * @npgnames: number of pingroup names the function uses
68 * @node: list node 68 * @node: list node
69 */ 69 */
70 struct pcs_function { 70 struct pcs_function {
71 const char *name; 71 const char *name;
72 struct pcs_func_vals *vals; 72 struct pcs_func_vals *vals;
73 unsigned nvals; 73 unsigned nvals;
74 const char **pgnames; 74 const char **pgnames;
75 int npgnames; 75 int npgnames;
76 struct list_head node; 76 struct list_head node;
77 }; 77 };
78 78
79 /** 79 /**
80 * struct pcs_data - wrapper for data needed by pinctrl framework 80 * struct pcs_data - wrapper for data needed by pinctrl framework
81 * @pa: pindesc array 81 * @pa: pindesc array
82 * @cur: index to current element 82 * @cur: index to current element
83 * 83 *
84 * REVISIT: We should be able to drop this eventually by adding 84 * REVISIT: We should be able to drop this eventually by adding
85 * support for registering pins individually in the pinctrl 85 * support for registering pins individually in the pinctrl
86 * framework for those drivers that don't need a static array. 86 * framework for those drivers that don't need a static array.
87 */ 87 */
88 struct pcs_data { 88 struct pcs_data {
89 struct pinctrl_pin_desc *pa; 89 struct pinctrl_pin_desc *pa;
90 int cur; 90 int cur;
91 }; 91 };
92 92
93 /** 93 /**
94 * struct pcs_name - register name for a pin 94 * struct pcs_name - register name for a pin
95 * @name: name of the pinctrl register 95 * @name: name of the pinctrl register
96 * 96 *
97 * REVISIT: We may want to make names optional in the pinctrl 97 * REVISIT: We may want to make names optional in the pinctrl
98 * framework as some drivers may not care about pin names to 98 * framework as some drivers may not care about pin names to
99 * avoid kernel bloat. The pin names can be deciphered by user 99 * avoid kernel bloat. The pin names can be deciphered by user
100 * space tools using debugfs based on the register address and 100 * space tools using debugfs based on the register address and
101 * SoC packaging information. 101 * SoC packaging information.
102 */ 102 */
103 struct pcs_name { 103 struct pcs_name {
104 char name[PCS_REG_NAME_LEN]; 104 char name[PCS_REG_NAME_LEN];
105 }; 105 };
106 106
107 /** 107 /**
108 * struct pcs_device - pinctrl device instance 108 * struct pcs_device - pinctrl device instance
109 * @res: resources 109 * @res: resources
110 * @base: virtual address of the controller 110 * @base: virtual address of the controller
111 * @size: size of the ioremapped area 111 * @size: size of the ioremapped area
112 * @dev: device entry 112 * @dev: device entry
113 * @pctl: pin controller device 113 * @pctl: pin controller device
114 * @mutex: mutex protecting the lists 114 * @mutex: mutex protecting the lists
115 * @width: bits per mux register 115 * @width: bits per mux register
116 * @fmask: function register mask 116 * @fmask: function register mask
117 * @fshift: function register shift 117 * @fshift: function register shift
118 * @foff: value to turn mux off 118 * @foff: value to turn mux off
119 * @fmax: max number of functions in fmask 119 * @fmax: max number of functions in fmask
120 * @names: array of register names for pins 120 * @names: array of register names for pins
121 * @pins: physical pins on the SoC 121 * @pins: physical pins on the SoC
122 * @pgtree: pingroup index radix tree 122 * @pgtree: pingroup index radix tree
123 * @ftree: function index radix tree 123 * @ftree: function index radix tree
124 * @pingroups: list of pingroups 124 * @pingroups: list of pingroups
125 * @functions: list of functions 125 * @functions: list of functions
126 * @ngroups: number of pingroups 126 * @ngroups: number of pingroups
127 * @nfuncs: number of functions 127 * @nfuncs: number of functions
128 * @desc: pin controller descriptor 128 * @desc: pin controller descriptor
129 * @read: register read function to use 129 * @read: register read function to use
130 * @write: register write function to use 130 * @write: register write function to use
131 */ 131 */
132 struct pcs_device { 132 struct pcs_device {
133 struct resource *res; 133 struct resource *res;
134 void __iomem *base; 134 void __iomem *base;
135 unsigned size; 135 unsigned size;
136 struct device *dev; 136 struct device *dev;
137 struct pinctrl_dev *pctl; 137 struct pinctrl_dev *pctl;
138 struct mutex mutex; 138 struct mutex mutex;
139 unsigned width; 139 unsigned width;
140 unsigned fmask; 140 unsigned fmask;
141 unsigned fshift; 141 unsigned fshift;
142 unsigned foff; 142 unsigned foff;
143 unsigned fmax; 143 unsigned fmax;
144 bool bits_per_mux; 144 bool bits_per_mux;
145 struct pcs_name *names; 145 struct pcs_name *names;
146 struct pcs_data pins; 146 struct pcs_data pins;
147 struct radix_tree_root pgtree; 147 struct radix_tree_root pgtree;
148 struct radix_tree_root ftree; 148 struct radix_tree_root ftree;
149 struct list_head pingroups; 149 struct list_head pingroups;
150 struct list_head functions; 150 struct list_head functions;
151 unsigned ngroups; 151 unsigned ngroups;
152 unsigned nfuncs; 152 unsigned nfuncs;
153 struct pinctrl_desc desc; 153 struct pinctrl_desc desc;
154 unsigned (*read)(void __iomem *reg); 154 unsigned (*read)(void __iomem *reg);
155 void (*write)(unsigned val, void __iomem *reg); 155 void (*write)(unsigned val, void __iomem *reg);
156 }; 156 };
157 157
158 /* 158 /*
159 * REVISIT: Reads and writes could eventually use regmap or something 159 * REVISIT: Reads and writes could eventually use regmap or something
160 * generic. But at least on omaps, some mux registers are performance 160 * generic. But at least on omaps, some mux registers are performance
161 * critical as they may need to be remuxed every time before and after 161 * critical as they may need to be remuxed every time before and after
162 * idle. Adding tests for register access width for every read and 162 * idle. Adding tests for register access width for every read and
163 * write like regmap is doing is not desired, and caching the registers 163 * write like regmap is doing is not desired, and caching the registers
164 * does not help in this case. 164 * does not help in this case.
165 */ 165 */
166 166
167 static unsigned __maybe_unused pcs_readb(void __iomem *reg) 167 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
168 { 168 {
169 return readb(reg); 169 return readb(reg);
170 } 170 }
171 171
172 static unsigned __maybe_unused pcs_readw(void __iomem *reg) 172 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
173 { 173 {
174 return readw(reg); 174 return readw(reg);
175 } 175 }
176 176
177 static unsigned __maybe_unused pcs_readl(void __iomem *reg) 177 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
178 { 178 {
179 return readl(reg); 179 return readl(reg);
180 } 180 }
181 181
182 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg) 182 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
183 { 183 {
184 writeb(val, reg); 184 writeb(val, reg);
185 } 185 }
186 186
187 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg) 187 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
188 { 188 {
189 writew(val, reg); 189 writew(val, reg);
190 } 190 }
191 191
192 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) 192 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
193 { 193 {
194 writel(val, reg); 194 writel(val, reg);
195 } 195 }
196 196
197 static int pcs_get_groups_count(struct pinctrl_dev *pctldev) 197 static int pcs_get_groups_count(struct pinctrl_dev *pctldev)
198 { 198 {
199 struct pcs_device *pcs; 199 struct pcs_device *pcs;
200 200
201 pcs = pinctrl_dev_get_drvdata(pctldev); 201 pcs = pinctrl_dev_get_drvdata(pctldev);
202 202
203 return pcs->ngroups; 203 return pcs->ngroups;
204 } 204 }
205 205
206 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev, 206 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev,
207 unsigned gselector) 207 unsigned gselector)
208 { 208 {
209 struct pcs_device *pcs; 209 struct pcs_device *pcs;
210 struct pcs_pingroup *group; 210 struct pcs_pingroup *group;
211 211
212 pcs = pinctrl_dev_get_drvdata(pctldev); 212 pcs = pinctrl_dev_get_drvdata(pctldev);
213 group = radix_tree_lookup(&pcs->pgtree, gselector); 213 group = radix_tree_lookup(&pcs->pgtree, gselector);
214 if (!group) { 214 if (!group) {
215 dev_err(pcs->dev, "%s could not find pingroup%i\n", 215 dev_err(pcs->dev, "%s could not find pingroup%i\n",
216 __func__, gselector); 216 __func__, gselector);
217 return NULL; 217 return NULL;
218 } 218 }
219 219
220 return group->name; 220 return group->name;
221 } 221 }
222 222
223 static int pcs_get_group_pins(struct pinctrl_dev *pctldev, 223 static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
224 unsigned gselector, 224 unsigned gselector,
225 const unsigned **pins, 225 const unsigned **pins,
226 unsigned *npins) 226 unsigned *npins)
227 { 227 {
228 struct pcs_device *pcs; 228 struct pcs_device *pcs;
229 struct pcs_pingroup *group; 229 struct pcs_pingroup *group;
230 230
231 pcs = pinctrl_dev_get_drvdata(pctldev); 231 pcs = pinctrl_dev_get_drvdata(pctldev);
232 group = radix_tree_lookup(&pcs->pgtree, gselector); 232 group = radix_tree_lookup(&pcs->pgtree, gselector);
233 if (!group) { 233 if (!group) {
234 dev_err(pcs->dev, "%s could not find pingroup%i\n", 234 dev_err(pcs->dev, "%s could not find pingroup%i\n",
235 __func__, gselector); 235 __func__, gselector);
236 return -EINVAL; 236 return -EINVAL;
237 } 237 }
238 238
239 *pins = group->gpins; 239 *pins = group->gpins;
240 *npins = group->ngpins; 240 *npins = group->ngpins;
241 241
242 return 0; 242 return 0;
243 } 243 }
244 244
245 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, 245 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
246 struct seq_file *s, 246 struct seq_file *s,
247 unsigned offset) 247 unsigned offset)
248 { 248 {
249 struct pcs_device *pcs; 249 struct pcs_device *pcs;
250 unsigned val; 250 unsigned val;
251 251
252 pcs = pinctrl_dev_get_drvdata(pctldev); 252 pcs = pinctrl_dev_get_drvdata(pctldev);
253 253
254 val = pcs->read(pcs->base + offset); 254 val = pcs->read(pcs->base + offset);
255 val &= pcs->fmask; 255 val &= pcs->fmask;
256 256
257 seq_printf(s, "%08x %s " , val, DRIVER_NAME); 257 seq_printf(s, "%08x %s " , val, DRIVER_NAME);
258 } 258 }
259 259
260 static void pcs_dt_free_map(struct pinctrl_dev *pctldev, 260 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
261 struct pinctrl_map *map, unsigned num_maps) 261 struct pinctrl_map *map, unsigned num_maps)
262 { 262 {
263 struct pcs_device *pcs; 263 struct pcs_device *pcs;
264 264
265 pcs = pinctrl_dev_get_drvdata(pctldev); 265 pcs = pinctrl_dev_get_drvdata(pctldev);
266 devm_kfree(pcs->dev, map); 266 devm_kfree(pcs->dev, map);
267 } 267 }
268 268
269 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, 269 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
270 struct device_node *np_config, 270 struct device_node *np_config,
271 struct pinctrl_map **map, unsigned *num_maps); 271 struct pinctrl_map **map, unsigned *num_maps);
272 272
273 static struct pinctrl_ops pcs_pinctrl_ops = { 273 static struct pinctrl_ops pcs_pinctrl_ops = {
274 .get_groups_count = pcs_get_groups_count, 274 .get_groups_count = pcs_get_groups_count,
275 .get_group_name = pcs_get_group_name, 275 .get_group_name = pcs_get_group_name,
276 .get_group_pins = pcs_get_group_pins, 276 .get_group_pins = pcs_get_group_pins,
277 .pin_dbg_show = pcs_pin_dbg_show, 277 .pin_dbg_show = pcs_pin_dbg_show,
278 .dt_node_to_map = pcs_dt_node_to_map, 278 .dt_node_to_map = pcs_dt_node_to_map,
279 .dt_free_map = pcs_dt_free_map, 279 .dt_free_map = pcs_dt_free_map,
280 }; 280 };
281 281
282 static int pcs_get_functions_count(struct pinctrl_dev *pctldev) 282 static int pcs_get_functions_count(struct pinctrl_dev *pctldev)
283 { 283 {
284 struct pcs_device *pcs; 284 struct pcs_device *pcs;
285 285
286 pcs = pinctrl_dev_get_drvdata(pctldev); 286 pcs = pinctrl_dev_get_drvdata(pctldev);
287 287
288 return pcs->nfuncs; 288 return pcs->nfuncs;
289 } 289 }
290 290
291 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev, 291 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev,
292 unsigned fselector) 292 unsigned fselector)
293 { 293 {
294 struct pcs_device *pcs; 294 struct pcs_device *pcs;
295 struct pcs_function *func; 295 struct pcs_function *func;
296 296
297 pcs = pinctrl_dev_get_drvdata(pctldev); 297 pcs = pinctrl_dev_get_drvdata(pctldev);
298 func = radix_tree_lookup(&pcs->ftree, fselector); 298 func = radix_tree_lookup(&pcs->ftree, fselector);
299 if (!func) { 299 if (!func) {
300 dev_err(pcs->dev, "%s could not find function%i\n", 300 dev_err(pcs->dev, "%s could not find function%i\n",
301 __func__, fselector); 301 __func__, fselector);
302 return NULL; 302 return NULL;
303 } 303 }
304 304
305 return func->name; 305 return func->name;
306 } 306 }
307 307
308 static int pcs_get_function_groups(struct pinctrl_dev *pctldev, 308 static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
309 unsigned fselector, 309 unsigned fselector,
310 const char * const **groups, 310 const char * const **groups,
311 unsigned * const ngroups) 311 unsigned * const ngroups)
312 { 312 {
313 struct pcs_device *pcs; 313 struct pcs_device *pcs;
314 struct pcs_function *func; 314 struct pcs_function *func;
315 315
316 pcs = pinctrl_dev_get_drvdata(pctldev); 316 pcs = pinctrl_dev_get_drvdata(pctldev);
317 func = radix_tree_lookup(&pcs->ftree, fselector); 317 func = radix_tree_lookup(&pcs->ftree, fselector);
318 if (!func) { 318 if (!func) {
319 dev_err(pcs->dev, "%s could not find function%i\n", 319 dev_err(pcs->dev, "%s could not find function%i\n",
320 __func__, fselector); 320 __func__, fselector);
321 return -EINVAL; 321 return -EINVAL;
322 } 322 }
323 *groups = func->pgnames; 323 *groups = func->pgnames;
324 *ngroups = func->npgnames; 324 *ngroups = func->npgnames;
325 325
326 return 0; 326 return 0;
327 } 327 }
328 328
329 static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, 329 static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
330 unsigned group) 330 unsigned group)
331 { 331 {
332 struct pcs_device *pcs; 332 struct pcs_device *pcs;
333 struct pcs_function *func; 333 struct pcs_function *func;
334 int i; 334 int i;
335 335
336 pcs = pinctrl_dev_get_drvdata(pctldev); 336 pcs = pinctrl_dev_get_drvdata(pctldev);
337 func = radix_tree_lookup(&pcs->ftree, fselector); 337 func = radix_tree_lookup(&pcs->ftree, fselector);
338 if (!func) 338 if (!func)
339 return -EINVAL; 339 return -EINVAL;
340 340
341 dev_dbg(pcs->dev, "enabling %s function%i\n", 341 dev_dbg(pcs->dev, "enabling %s function%i\n",
342 func->name, fselector); 342 func->name, fselector);
343 343
344 for (i = 0; i < func->nvals; i++) { 344 for (i = 0; i < func->nvals; i++) {
345 struct pcs_func_vals *vals; 345 struct pcs_func_vals *vals;
346 unsigned val, mask; 346 unsigned val, mask;
347 347
348 vals = &func->vals[i]; 348 vals = &func->vals[i];
349 val = pcs->read(vals->reg); 349 val = pcs->read(vals->reg);
350 if (!vals->mask) 350 if (!vals->mask)
351 mask = pcs->fmask; 351 mask = pcs->fmask;
352 else 352 else
353 mask = pcs->fmask & vals->mask; 353 mask = pcs->fmask & vals->mask;
354 354
355 val &= ~mask; 355 val &= ~mask;
356 val |= (vals->val & mask); 356 val |= (vals->val & mask);
357 pcs->write(val, vals->reg); 357 pcs->write(val, vals->reg);
358 } 358 }
359 359
360 return 0; 360 return 0;
361 } 361 }
362 362
363 static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, 363 static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
364 unsigned group) 364 unsigned group)
365 { 365 {
366 struct pcs_device *pcs; 366 struct pcs_device *pcs;
367 struct pcs_function *func; 367 struct pcs_function *func;
368 int i; 368 int i;
369 369
370 pcs = pinctrl_dev_get_drvdata(pctldev); 370 pcs = pinctrl_dev_get_drvdata(pctldev);
371 func = radix_tree_lookup(&pcs->ftree, fselector); 371 func = radix_tree_lookup(&pcs->ftree, fselector);
372 if (!func) { 372 if (!func) {
373 dev_err(pcs->dev, "%s could not find function%i\n", 373 dev_err(pcs->dev, "%s could not find function%i\n",
374 __func__, fselector); 374 __func__, fselector);
375 return; 375 return;
376 } 376 }
377 377
378 /* 378 /*
379 * Ignore disable if function-off is not specified. Some hardware 379 * Ignore disable if function-off is not specified. Some hardware
380 * does not have clearly defined disable function. For pin specific 380 * does not have clearly defined disable function. For pin specific
381 * off modes, you can use alternate named states as described in 381 * off modes, you can use alternate named states as described in
382 * pinctrl-bindings.txt. 382 * pinctrl-bindings.txt.
383 */ 383 */
384 if (pcs->foff == PCS_OFF_DISABLED) { 384 if (pcs->foff == PCS_OFF_DISABLED) {
385 dev_dbg(pcs->dev, "ignoring disable for %s function%i\n", 385 dev_dbg(pcs->dev, "ignoring disable for %s function%i\n",
386 func->name, fselector); 386 func->name, fselector);
387 return; 387 return;
388 } 388 }
389 389
390 dev_dbg(pcs->dev, "disabling function%i %s\n", 390 dev_dbg(pcs->dev, "disabling function%i %s\n",
391 fselector, func->name); 391 fselector, func->name);
392 392
393 for (i = 0; i < func->nvals; i++) { 393 for (i = 0; i < func->nvals; i++) {
394 struct pcs_func_vals *vals; 394 struct pcs_func_vals *vals;
395 unsigned val; 395 unsigned val;
396 396
397 vals = &func->vals[i]; 397 vals = &func->vals[i];
398 val = pcs->read(vals->reg); 398 val = pcs->read(vals->reg);
399 val &= ~pcs->fmask; 399 val &= ~pcs->fmask;
400 val |= pcs->foff << pcs->fshift; 400 val |= pcs->foff << pcs->fshift;
401 pcs->write(val, vals->reg); 401 pcs->write(val, vals->reg);
402 } 402 }
403 } 403 }
404 404
405 static int pcs_request_gpio(struct pinctrl_dev *pctldev, 405 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
406 struct pinctrl_gpio_range *range, unsigned offset) 406 struct pinctrl_gpio_range *range, unsigned offset)
407 { 407 {
408 return -ENOTSUPP; 408 return -ENOTSUPP;
409 } 409 }
410 410
411 static struct pinmux_ops pcs_pinmux_ops = { 411 static struct pinmux_ops pcs_pinmux_ops = {
412 .get_functions_count = pcs_get_functions_count, 412 .get_functions_count = pcs_get_functions_count,
413 .get_function_name = pcs_get_function_name, 413 .get_function_name = pcs_get_function_name,
414 .get_function_groups = pcs_get_function_groups, 414 .get_function_groups = pcs_get_function_groups,
415 .enable = pcs_enable, 415 .enable = pcs_enable,
416 .disable = pcs_disable, 416 .disable = pcs_disable,
417 .gpio_request_enable = pcs_request_gpio, 417 .gpio_request_enable = pcs_request_gpio,
418 }; 418 };
419 419
420 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, 420 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
421 unsigned pin, unsigned long *config) 421 unsigned pin, unsigned long *config)
422 { 422 {
423 return -ENOTSUPP; 423 return -ENOTSUPP;
424 } 424 }
425 425
426 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, 426 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
427 unsigned pin, unsigned long config) 427 unsigned pin, unsigned long config)
428 { 428 {
429 return -ENOTSUPP; 429 return -ENOTSUPP;
430 } 430 }
431 431
432 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, 432 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
433 unsigned group, unsigned long *config) 433 unsigned group, unsigned long *config)
434 { 434 {
435 return -ENOTSUPP; 435 return -ENOTSUPP;
436 } 436 }
437 437
438 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, 438 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
439 unsigned group, unsigned long config) 439 unsigned group, unsigned long config)
440 { 440 {
441 return -ENOTSUPP; 441 return -ENOTSUPP;
442 } 442 }
443 443
444 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev, 444 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
445 struct seq_file *s, unsigned offset) 445 struct seq_file *s, unsigned offset)
446 { 446 {
447 } 447 }
448 448
449 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 449 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
450 struct seq_file *s, unsigned selector) 450 struct seq_file *s, unsigned selector)
451 { 451 {
452 } 452 }
453 453
454 static struct pinconf_ops pcs_pinconf_ops = { 454 static struct pinconf_ops pcs_pinconf_ops = {
455 .pin_config_get = pcs_pinconf_get, 455 .pin_config_get = pcs_pinconf_get,
456 .pin_config_set = pcs_pinconf_set, 456 .pin_config_set = pcs_pinconf_set,
457 .pin_config_group_get = pcs_pinconf_group_get, 457 .pin_config_group_get = pcs_pinconf_group_get,
458 .pin_config_group_set = pcs_pinconf_group_set, 458 .pin_config_group_set = pcs_pinconf_group_set,
459 .pin_config_dbg_show = pcs_pinconf_dbg_show, 459 .pin_config_dbg_show = pcs_pinconf_dbg_show,
460 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, 460 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
461 }; 461 };
462 462
463 /** 463 /**
464 * pcs_add_pin() - add a pin to the static per controller pin array 464 * pcs_add_pin() - add a pin to the static per controller pin array
465 * @pcs: pcs driver instance 465 * @pcs: pcs driver instance
466 * @offset: register offset from base 466 * @offset: register offset from base
467 */ 467 */
468 static int __devinit pcs_add_pin(struct pcs_device *pcs, unsigned offset) 468 static int __devinit pcs_add_pin(struct pcs_device *pcs, unsigned offset)
469 { 469 {
470 struct pinctrl_pin_desc *pin; 470 struct pinctrl_pin_desc *pin;
471 struct pcs_name *pn; 471 struct pcs_name *pn;
472 int i; 472 int i;
473 473
474 i = pcs->pins.cur; 474 i = pcs->pins.cur;
475 if (i >= pcs->desc.npins) { 475 if (i >= pcs->desc.npins) {
476 dev_err(pcs->dev, "too many pins, max %i\n", 476 dev_err(pcs->dev, "too many pins, max %i\n",
477 pcs->desc.npins); 477 pcs->desc.npins);
478 return -ENOMEM; 478 return -ENOMEM;
479 } 479 }
480 480
481 pin = &pcs->pins.pa[i]; 481 pin = &pcs->pins.pa[i];
482 pn = &pcs->names[i]; 482 pn = &pcs->names[i];
483 sprintf(pn->name, "%lx", 483 sprintf(pn->name, "%lx",
484 (unsigned long)pcs->res->start + offset); 484 (unsigned long)pcs->res->start + offset);
485 pin->name = pn->name; 485 pin->name = pn->name;
486 pin->number = i; 486 pin->number = i;
487 pcs->pins.cur++; 487 pcs->pins.cur++;
488 488
489 return i; 489 return i;
490 } 490 }
491 491
492 /** 492 /**
493 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver 493 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
494 * @pcs: pcs driver instance 494 * @pcs: pcs driver instance
495 * 495 *
496 * In case of errors, resources are freed in pcs_free_resources. 496 * In case of errors, resources are freed in pcs_free_resources.
497 * 497 *
498 * If your hardware needs holes in the address space, then just set 498 * If your hardware needs holes in the address space, then just set
499 * up multiple driver instances. 499 * up multiple driver instances.
500 */ 500 */
501 static int __devinit pcs_allocate_pin_table(struct pcs_device *pcs) 501 static int __devinit pcs_allocate_pin_table(struct pcs_device *pcs)
502 { 502 {
503 int mux_bytes, nr_pins, i; 503 int mux_bytes, nr_pins, i;
504 504
505 mux_bytes = pcs->width / BITS_PER_BYTE; 505 mux_bytes = pcs->width / BITS_PER_BYTE;
506 nr_pins = pcs->size / mux_bytes; 506 nr_pins = pcs->size / mux_bytes;
507 507
508 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); 508 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
509 pcs->pins.pa = devm_kzalloc(pcs->dev, 509 pcs->pins.pa = devm_kzalloc(pcs->dev,
510 sizeof(*pcs->pins.pa) * nr_pins, 510 sizeof(*pcs->pins.pa) * nr_pins,
511 GFP_KERNEL); 511 GFP_KERNEL);
512 if (!pcs->pins.pa) 512 if (!pcs->pins.pa)
513 return -ENOMEM; 513 return -ENOMEM;
514 514
515 pcs->names = devm_kzalloc(pcs->dev, 515 pcs->names = devm_kzalloc(pcs->dev,
516 sizeof(struct pcs_name) * nr_pins, 516 sizeof(struct pcs_name) * nr_pins,
517 GFP_KERNEL); 517 GFP_KERNEL);
518 if (!pcs->names) 518 if (!pcs->names)
519 return -ENOMEM; 519 return -ENOMEM;
520 520
521 pcs->desc.pins = pcs->pins.pa; 521 pcs->desc.pins = pcs->pins.pa;
522 pcs->desc.npins = nr_pins; 522 pcs->desc.npins = nr_pins;
523 523
524 for (i = 0; i < pcs->desc.npins; i++) { 524 for (i = 0; i < pcs->desc.npins; i++) {
525 unsigned offset; 525 unsigned offset;
526 int res; 526 int res;
527 527
528 offset = i * mux_bytes; 528 offset = i * mux_bytes;
529 res = pcs_add_pin(pcs, offset); 529 res = pcs_add_pin(pcs, offset);
530 if (res < 0) { 530 if (res < 0) {
531 dev_err(pcs->dev, "error adding pins: %i\n", res); 531 dev_err(pcs->dev, "error adding pins: %i\n", res);
532 return res; 532 return res;
533 } 533 }
534 } 534 }
535 535
536 return 0; 536 return 0;
537 } 537 }
538 538
539 /** 539 /**
540 * pcs_add_function() - adds a new function to the function list 540 * pcs_add_function() - adds a new function to the function list
541 * @pcs: pcs driver instance 541 * @pcs: pcs driver instance
542 * @np: device node of the mux entry 542 * @np: device node of the mux entry
543 * @name: name of the function 543 * @name: name of the function
544 * @vals: array of mux register value pairs used by the function 544 * @vals: array of mux register value pairs used by the function
545 * @nvals: number of mux register value pairs 545 * @nvals: number of mux register value pairs
546 * @pgnames: array of pingroup names for the function 546 * @pgnames: array of pingroup names for the function
547 * @npgnames: number of pingroup names 547 * @npgnames: number of pingroup names
548 */ 548 */
549 static struct pcs_function *pcs_add_function(struct pcs_device *pcs, 549 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
550 struct device_node *np, 550 struct device_node *np,
551 const char *name, 551 const char *name,
552 struct pcs_func_vals *vals, 552 struct pcs_func_vals *vals,
553 unsigned nvals, 553 unsigned nvals,
554 const char **pgnames, 554 const char **pgnames,
555 unsigned npgnames) 555 unsigned npgnames)
556 { 556 {
557 struct pcs_function *function; 557 struct pcs_function *function;
558 558
559 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); 559 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
560 if (!function) 560 if (!function)
561 return NULL; 561 return NULL;
562 562
563 function->name = name; 563 function->name = name;
564 function->vals = vals; 564 function->vals = vals;
565 function->nvals = nvals; 565 function->nvals = nvals;
566 function->pgnames = pgnames; 566 function->pgnames = pgnames;
567 function->npgnames = npgnames; 567 function->npgnames = npgnames;
568 568
569 mutex_lock(&pcs->mutex); 569 mutex_lock(&pcs->mutex);
570 list_add_tail(&function->node, &pcs->functions); 570 list_add_tail(&function->node, &pcs->functions);
571 radix_tree_insert(&pcs->ftree, pcs->nfuncs, function); 571 radix_tree_insert(&pcs->ftree, pcs->nfuncs, function);
572 pcs->nfuncs++; 572 pcs->nfuncs++;
573 mutex_unlock(&pcs->mutex); 573 mutex_unlock(&pcs->mutex);
574 574
575 return function; 575 return function;
576 } 576 }
577 577
578 static void pcs_remove_function(struct pcs_device *pcs, 578 static void pcs_remove_function(struct pcs_device *pcs,
579 struct pcs_function *function) 579 struct pcs_function *function)
580 { 580 {
581 int i; 581 int i;
582 582
583 mutex_lock(&pcs->mutex); 583 mutex_lock(&pcs->mutex);
584 for (i = 0; i < pcs->nfuncs; i++) { 584 for (i = 0; i < pcs->nfuncs; i++) {
585 struct pcs_function *found; 585 struct pcs_function *found;
586 586
587 found = radix_tree_lookup(&pcs->ftree, i); 587 found = radix_tree_lookup(&pcs->ftree, i);
588 if (found == function) 588 if (found == function)
589 radix_tree_delete(&pcs->ftree, i); 589 radix_tree_delete(&pcs->ftree, i);
590 } 590 }
591 list_del(&function->node); 591 list_del(&function->node);
592 mutex_unlock(&pcs->mutex); 592 mutex_unlock(&pcs->mutex);
593 } 593 }
594 594
595 /** 595 /**
596 * pcs_add_pingroup() - add a pingroup to the pingroup list 596 * pcs_add_pingroup() - add a pingroup to the pingroup list
597 * @pcs: pcs driver instance 597 * @pcs: pcs driver instance
598 * @np: device node of the mux entry 598 * @np: device node of the mux entry
599 * @name: name of the pingroup 599 * @name: name of the pingroup
600 * @gpins: array of the pins that belong to the group 600 * @gpins: array of the pins that belong to the group
601 * @ngpins: number of pins in the group 601 * @ngpins: number of pins in the group
602 */ 602 */
603 static int pcs_add_pingroup(struct pcs_device *pcs, 603 static int pcs_add_pingroup(struct pcs_device *pcs,
604 struct device_node *np, 604 struct device_node *np,
605 const char *name, 605 const char *name,
606 int *gpins, 606 int *gpins,
607 int ngpins) 607 int ngpins)
608 { 608 {
609 struct pcs_pingroup *pingroup; 609 struct pcs_pingroup *pingroup;
610 610
611 pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL); 611 pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL);
612 if (!pingroup) 612 if (!pingroup)
613 return -ENOMEM; 613 return -ENOMEM;
614 614
615 pingroup->name = name; 615 pingroup->name = name;
616 pingroup->np = np; 616 pingroup->np = np;
617 pingroup->gpins = gpins; 617 pingroup->gpins = gpins;
618 pingroup->ngpins = ngpins; 618 pingroup->ngpins = ngpins;
619 619
620 mutex_lock(&pcs->mutex); 620 mutex_lock(&pcs->mutex);
621 list_add_tail(&pingroup->node, &pcs->pingroups); 621 list_add_tail(&pingroup->node, &pcs->pingroups);
622 radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup); 622 radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup);
623 pcs->ngroups++; 623 pcs->ngroups++;
624 mutex_unlock(&pcs->mutex); 624 mutex_unlock(&pcs->mutex);
625 625
626 return 0; 626 return 0;
627 } 627 }
628 628
629 /** 629 /**
630 * pcs_get_pin_by_offset() - get a pin index based on the register offset 630 * pcs_get_pin_by_offset() - get a pin index based on the register offset
631 * @pcs: pcs driver instance 631 * @pcs: pcs driver instance
632 * @offset: register offset from the base 632 * @offset: register offset from the base
633 * 633 *
634 * Note that this is OK as long as the pins are in a static array. 634 * Note that this is OK as long as the pins are in a static array.
635 */ 635 */
636 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) 636 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
637 { 637 {
638 unsigned index; 638 unsigned index;
639 639
640 if (offset >= pcs->size) { 640 if (offset >= pcs->size) {
641 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", 641 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
642 offset, pcs->size); 642 offset, pcs->size);
643 return -EINVAL; 643 return -EINVAL;
644 } 644 }
645 645
646 index = offset / (pcs->width / BITS_PER_BYTE); 646 index = offset / (pcs->width / BITS_PER_BYTE);
647 647
648 return index; 648 return index;
649 } 649 }
650 650
651 /** 651 /**
652 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry 652 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
653 * @pcs: pinctrl driver instance 653 * @pcs: pinctrl driver instance
654 * @np: device node of the mux entry 654 * @np: device node of the mux entry
655 * @map: map entry 655 * @map: map entry
656 * @pgnames: pingroup names 656 * @pgnames: pingroup names
657 * 657 *
658 * Note that this binding currently supports only sets of one register + value. 658 * Note that this binding currently supports only sets of one register + value.
659 * 659 *
660 * Also note that this driver tries to avoid understanding pin and function 660 * Also note that this driver tries to avoid understanding pin and function
661 * names because of the extra bloat they would cause especially in the case of 661 * names because of the extra bloat they would cause especially in the case of
662 * a large number of pins. This driver just sets what is specified for the board 662 * a large number of pins. This driver just sets what is specified for the board
663 * in the .dts file. Further user space debugging tools can be developed to 663 * in the .dts file. Further user space debugging tools can be developed to
664 * decipher the pin and function names using debugfs. 664 * decipher the pin and function names using debugfs.
665 * 665 *
666 * If you are concerned about the boot time, set up the static pins in 666 * If you are concerned about the boot time, set up the static pins in
667 * the bootloader, and only set up selected pins as device tree entries. 667 * the bootloader, and only set up selected pins as device tree entries.
668 */ 668 */
669 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, 669 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
670 struct device_node *np, 670 struct device_node *np,
671 struct pinctrl_map **map, 671 struct pinctrl_map **map,
672 const char **pgnames) 672 const char **pgnames)
673 { 673 {
674 struct pcs_func_vals *vals; 674 struct pcs_func_vals *vals;
675 const __be32 *mux; 675 const __be32 *mux;
676 int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM; 676 int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM;
677 struct pcs_function *function; 677 struct pcs_function *function;
678 678
679 if (pcs->bits_per_mux) { 679 if (pcs->bits_per_mux) {
680 params = 3; 680 params = 3;
681 mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); 681 mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
682 } else { 682 } else {
683 params = 2; 683 params = 2;
684 mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); 684 mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
685 } 685 }
686 686
687 if (!mux) { 687 if (!mux) {
688 dev_err(pcs->dev, "no valid property for %s\n", np->name); 688 dev_err(pcs->dev, "no valid property for %s\n", np->name);
689 return -EINVAL; 689 return -EINVAL;
690 } 690 }
691 691
692 if (size < (sizeof(*mux) * params)) { 692 if (size < (sizeof(*mux) * params)) {
693 dev_err(pcs->dev, "bad data for %s\n", np->name); 693 dev_err(pcs->dev, "bad data for %s\n", np->name);
694 return -EINVAL; 694 return -EINVAL;
695 } 695 }
696 696
697 size /= sizeof(*mux); /* Number of elements in array */ 697 size /= sizeof(*mux); /* Number of elements in array */
698 rows = size / params; 698 rows = size / params;
699 699
700 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); 700 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
701 if (!vals) 701 if (!vals)
702 return -ENOMEM; 702 return -ENOMEM;
703 703
704 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL); 704 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
705 if (!pins) 705 if (!pins)
706 goto free_vals; 706 goto free_vals;
707 707
708 while (index < size) { 708 while (index < size) {
709 unsigned offset, val; 709 unsigned offset, val;
710 int pin; 710 int pin;
711 711
712 offset = be32_to_cpup(mux + index++); 712 offset = be32_to_cpup(mux + index++);
713 val = be32_to_cpup(mux + index++); 713 val = be32_to_cpup(mux + index++);
714 vals[found].reg = pcs->base + offset; 714 vals[found].reg = pcs->base + offset;
715 vals[found].val = val; 715 vals[found].val = val;
716 if (params == 3) { 716 if (params == 3) {
717 val = be32_to_cpup(mux + index++); 717 val = be32_to_cpup(mux + index++);
718 vals[found].mask = val; 718 vals[found].mask = val;
719 } 719 }
720 720
721 pin = pcs_get_pin_by_offset(pcs, offset); 721 pin = pcs_get_pin_by_offset(pcs, offset);
722 if (pin < 0) { 722 if (pin < 0) {
723 dev_err(pcs->dev, 723 dev_err(pcs->dev,
724 "could not add functions for %s %ux\n", 724 "could not add functions for %s %ux\n",
725 np->name, offset); 725 np->name, offset);
726 break; 726 break;
727 } 727 }
728 pins[found++] = pin; 728 pins[found++] = pin;
729 } 729 }
730 730
731 pgnames[0] = np->name; 731 pgnames[0] = np->name;
732 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); 732 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
733 if (!function) 733 if (!function)
734 goto free_pins; 734 goto free_pins;
735 735
736 res = pcs_add_pingroup(pcs, np, np->name, pins, found); 736 res = pcs_add_pingroup(pcs, np, np->name, pins, found);
737 if (res < 0) 737 if (res < 0)
738 goto free_function; 738 goto free_function;
739 739
740 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; 740 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
741 (*map)->data.mux.group = np->name; 741 (*map)->data.mux.group = np->name;
742 (*map)->data.mux.function = np->name; 742 (*map)->data.mux.function = np->name;
743 743
744 return 0; 744 return 0;
745 745
746 free_function: 746 free_function:
747 pcs_remove_function(pcs, function); 747 pcs_remove_function(pcs, function);
748 748
749 free_pins: 749 free_pins:
750 devm_kfree(pcs->dev, pins); 750 devm_kfree(pcs->dev, pins);
751 751
752 free_vals: 752 free_vals:
753 devm_kfree(pcs->dev, vals); 753 devm_kfree(pcs->dev, vals);
754 754
755 return res; 755 return res;
756 } 756 }
757 /** 757 /**
758 * pcs_dt_node_to_map() - allocates and parses pinctrl maps 758 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
759 * @pctldev: pinctrl instance 759 * @pctldev: pinctrl instance
760 * @np_config: device tree pinmux entry 760 * @np_config: device tree pinmux entry
761 * @map: array of map entries 761 * @map: array of map entries
762 * @num_maps: number of maps 762 * @num_maps: number of maps
763 */ 763 */
764 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, 764 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
765 struct device_node *np_config, 765 struct device_node *np_config,
766 struct pinctrl_map **map, unsigned *num_maps) 766 struct pinctrl_map **map, unsigned *num_maps)
767 { 767 {
768 struct pcs_device *pcs; 768 struct pcs_device *pcs;
769 const char **pgnames; 769 const char **pgnames;
770 int ret; 770 int ret;
771 771
772 pcs = pinctrl_dev_get_drvdata(pctldev); 772 pcs = pinctrl_dev_get_drvdata(pctldev);
773 773
774 *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL); 774 *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL);
775 if (!map) 775 if (!map)
776 return -ENOMEM; 776 return -ENOMEM;
777 777
778 *num_maps = 0; 778 *num_maps = 0;
779 779
780 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); 780 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
781 if (!pgnames) { 781 if (!pgnames) {
782 ret = -ENOMEM; 782 ret = -ENOMEM;
783 goto free_map; 783 goto free_map;
784 } 784 }
785 785
786 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames); 786 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames);
787 if (ret < 0) { 787 if (ret < 0) {
788 dev_err(pcs->dev, "no pins entries for %s\n", 788 dev_err(pcs->dev, "no pins entries for %s\n",
789 np_config->name); 789 np_config->name);
790 goto free_pgnames; 790 goto free_pgnames;
791 } 791 }
792 *num_maps = 1; 792 *num_maps = 1;
793 793
794 return 0; 794 return 0;
795 795
796 free_pgnames: 796 free_pgnames:
797 devm_kfree(pcs->dev, pgnames); 797 devm_kfree(pcs->dev, pgnames);
798 free_map: 798 free_map:
799 devm_kfree(pcs->dev, *map); 799 devm_kfree(pcs->dev, *map);
800 800
801 return ret; 801 return ret;
802 } 802 }
803 803
804 /** 804 /**
805 * pcs_free_funcs() - free memory used by functions 805 * pcs_free_funcs() - free memory used by functions
806 * @pcs: pcs driver instance 806 * @pcs: pcs driver instance
807 */ 807 */
808 static void pcs_free_funcs(struct pcs_device *pcs) 808 static void pcs_free_funcs(struct pcs_device *pcs)
809 { 809 {
810 struct list_head *pos, *tmp; 810 struct list_head *pos, *tmp;
811 int i; 811 int i;
812 812
813 mutex_lock(&pcs->mutex); 813 mutex_lock(&pcs->mutex);
814 for (i = 0; i < pcs->nfuncs; i++) { 814 for (i = 0; i < pcs->nfuncs; i++) {
815 struct pcs_function *func; 815 struct pcs_function *func;
816 816
817 func = radix_tree_lookup(&pcs->ftree, i); 817 func = radix_tree_lookup(&pcs->ftree, i);
818 if (!func) 818 if (!func)
819 continue; 819 continue;
820 radix_tree_delete(&pcs->ftree, i); 820 radix_tree_delete(&pcs->ftree, i);
821 } 821 }
822 list_for_each_safe(pos, tmp, &pcs->functions) { 822 list_for_each_safe(pos, tmp, &pcs->functions) {
823 struct pcs_function *function; 823 struct pcs_function *function;
824 824
825 function = list_entry(pos, struct pcs_function, node); 825 function = list_entry(pos, struct pcs_function, node);
826 list_del(&function->node); 826 list_del(&function->node);
827 } 827 }
828 mutex_unlock(&pcs->mutex); 828 mutex_unlock(&pcs->mutex);
829 } 829 }
830 830
831 /** 831 /**
832 * pcs_free_pingroups() - free memory used by pingroups 832 * pcs_free_pingroups() - free memory used by pingroups
833 * @pcs: pcs driver instance 833 * @pcs: pcs driver instance
834 */ 834 */
835 static void pcs_free_pingroups(struct pcs_device *pcs) 835 static void pcs_free_pingroups(struct pcs_device *pcs)
836 { 836 {
837 struct list_head *pos, *tmp; 837 struct list_head *pos, *tmp;
838 int i; 838 int i;
839 839
840 mutex_lock(&pcs->mutex); 840 mutex_lock(&pcs->mutex);
841 for (i = 0; i < pcs->ngroups; i++) { 841 for (i = 0; i < pcs->ngroups; i++) {
842 struct pcs_pingroup *pingroup; 842 struct pcs_pingroup *pingroup;
843 843
844 pingroup = radix_tree_lookup(&pcs->pgtree, i); 844 pingroup = radix_tree_lookup(&pcs->pgtree, i);
845 if (!pingroup) 845 if (!pingroup)
846 continue; 846 continue;
847 radix_tree_delete(&pcs->pgtree, i); 847 radix_tree_delete(&pcs->pgtree, i);
848 } 848 }
849 list_for_each_safe(pos, tmp, &pcs->pingroups) { 849 list_for_each_safe(pos, tmp, &pcs->pingroups) {
850 struct pcs_pingroup *pingroup; 850 struct pcs_pingroup *pingroup;
851 851
852 pingroup = list_entry(pos, struct pcs_pingroup, node); 852 pingroup = list_entry(pos, struct pcs_pingroup, node);
853 list_del(&pingroup->node); 853 list_del(&pingroup->node);
854 } 854 }
855 mutex_unlock(&pcs->mutex); 855 mutex_unlock(&pcs->mutex);
856 } 856 }
857 857
858 /** 858 /**
859 * pcs_free_resources() - free memory used by this driver 859 * pcs_free_resources() - free memory used by this driver
860 * @pcs: pcs driver instance 860 * @pcs: pcs driver instance
861 */ 861 */
862 static void pcs_free_resources(struct pcs_device *pcs) 862 static void pcs_free_resources(struct pcs_device *pcs)
863 { 863 {
864 if (pcs->pctl) 864 if (pcs->pctl)
865 pinctrl_unregister(pcs->pctl); 865 pinctrl_unregister(pcs->pctl);
866 866
867 pcs_free_funcs(pcs); 867 pcs_free_funcs(pcs);
868 pcs_free_pingroups(pcs); 868 pcs_free_pingroups(pcs);
869 } 869 }
870 870
871 #define PCS_GET_PROP_U32(name, reg, err) \ 871 #define PCS_GET_PROP_U32(name, reg, err) \
872 do { \ 872 do { \
873 ret = of_property_read_u32(np, name, reg); \ 873 ret = of_property_read_u32(np, name, reg); \
874 if (ret) { \ 874 if (ret) { \
875 dev_err(pcs->dev, err); \ 875 dev_err(pcs->dev, err); \
876 return ret; \ 876 return ret; \
877 } \ 877 } \
878 } while (0); 878 } while (0);
879 879
880 static struct of_device_id pcs_of_match[]; 880 static struct of_device_id pcs_of_match[];
881 881
882 static int __devinit pcs_probe(struct platform_device *pdev) 882 static int __devinit pcs_probe(struct platform_device *pdev)
883 { 883 {
884 struct device_node *np = pdev->dev.of_node; 884 struct device_node *np = pdev->dev.of_node;
885 const struct of_device_id *match; 885 const struct of_device_id *match;
886 struct resource *res; 886 struct resource *res;
887 struct pcs_device *pcs; 887 struct pcs_device *pcs;
888 int ret; 888 int ret;
889 889
890 match = of_match_device(pcs_of_match, &pdev->dev); 890 match = of_match_device(pcs_of_match, &pdev->dev);
891 if (!match) 891 if (!match)
892 return -EINVAL; 892 return -EINVAL;
893 893
894 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); 894 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
895 if (!pcs) { 895 if (!pcs) {
896 dev_err(&pdev->dev, "could not allocate\n"); 896 dev_err(&pdev->dev, "could not allocate\n");
897 return -ENOMEM; 897 return -ENOMEM;
898 } 898 }
899 pcs->dev = &pdev->dev; 899 pcs->dev = &pdev->dev;
900 mutex_init(&pcs->mutex); 900 mutex_init(&pcs->mutex);
901 INIT_LIST_HEAD(&pcs->pingroups); 901 INIT_LIST_HEAD(&pcs->pingroups);
902 INIT_LIST_HEAD(&pcs->functions); 902 INIT_LIST_HEAD(&pcs->functions);
903 903
904 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, 904 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
905 "register width not specified\n"); 905 "register width not specified\n");
906 906
907 PCS_GET_PROP_U32("pinctrl-single,function-mask", &pcs->fmask, 907 PCS_GET_PROP_U32("pinctrl-single,function-mask", &pcs->fmask,
908 "function register mask not specified\n"); 908 "function register mask not specified\n");
909 pcs->fshift = ffs(pcs->fmask) - 1; 909 pcs->fshift = ffs(pcs->fmask) - 1;
910 pcs->fmax = pcs->fmask >> pcs->fshift; 910 pcs->fmax = pcs->fmask >> pcs->fshift;
911 911
912 ret = of_property_read_u32(np, "pinctrl-single,function-off", 912 ret = of_property_read_u32(np, "pinctrl-single,function-off",
913 &pcs->foff); 913 &pcs->foff);
914 if (ret) 914 if (ret)
915 pcs->foff = PCS_OFF_DISABLED; 915 pcs->foff = PCS_OFF_DISABLED;
916 916
917 pcs->bits_per_mux = of_property_read_bool(np, 917 pcs->bits_per_mux = of_property_read_bool(np,
918 "pinctrl-single,bit-per-mux"); 918 "pinctrl-single,bit-per-mux");
919 919
920 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 920 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
921 if (!res) { 921 if (!res) {
922 dev_err(pcs->dev, "could not get resource\n"); 922 dev_err(pcs->dev, "could not get resource\n");
923 return -ENODEV; 923 return -ENODEV;
924 } 924 }
925 925
926 pcs->res = devm_request_mem_region(pcs->dev, res->start, 926 pcs->res = devm_request_mem_region(pcs->dev, res->start,
927 resource_size(res), DRIVER_NAME); 927 resource_size(res), DRIVER_NAME);
928 if (!pcs->res) { 928 if (!pcs->res) {
929 dev_err(pcs->dev, "could not get mem_region\n"); 929 dev_err(pcs->dev, "could not get mem_region\n");
930 return -EBUSY; 930 return -EBUSY;
931 } 931 }
932 932
933 pcs->size = resource_size(pcs->res); 933 pcs->size = resource_size(pcs->res);
934 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); 934 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
935 if (!pcs->base) { 935 if (!pcs->base) {
936 dev_err(pcs->dev, "could not ioremap\n"); 936 dev_err(pcs->dev, "could not ioremap\n");
937 return -ENODEV; 937 return -ENODEV;
938 } 938 }
939 939
940 INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL); 940 INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL);
941 INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL); 941 INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL);
942 platform_set_drvdata(pdev, pcs); 942 platform_set_drvdata(pdev, pcs);
943 943
944 switch (pcs->width) { 944 switch (pcs->width) {
945 case 8: 945 case 8:
946 pcs->read = pcs_readb; 946 pcs->read = pcs_readb;
947 pcs->write = pcs_writeb; 947 pcs->write = pcs_writeb;
948 break; 948 break;
949 case 16: 949 case 16:
950 pcs->read = pcs_readw; 950 pcs->read = pcs_readw;
951 pcs->write = pcs_writew; 951 pcs->write = pcs_writew;
952 break; 952 break;
953 case 32: 953 case 32:
954 pcs->read = pcs_readl; 954 pcs->read = pcs_readl;
955 pcs->write = pcs_writel; 955 pcs->write = pcs_writel;
956 break; 956 break;
957 default: 957 default:
958 break; 958 break;
959 } 959 }
960 960
961 pcs->desc.name = DRIVER_NAME; 961 pcs->desc.name = DRIVER_NAME;
962 pcs->desc.pctlops = &pcs_pinctrl_ops; 962 pcs->desc.pctlops = &pcs_pinctrl_ops;
963 pcs->desc.pmxops = &pcs_pinmux_ops; 963 pcs->desc.pmxops = &pcs_pinmux_ops;
964 pcs->desc.confops = &pcs_pinconf_ops; 964 pcs->desc.confops = &pcs_pinconf_ops;
965 pcs->desc.owner = THIS_MODULE; 965 pcs->desc.owner = THIS_MODULE;
966 966
967 ret = pcs_allocate_pin_table(pcs); 967 ret = pcs_allocate_pin_table(pcs);
968 if (ret < 0) 968 if (ret < 0)
969 goto free; 969 goto free;
970 970
971 pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs); 971 pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs);
972 if (!pcs->pctl) { 972 if (!pcs->pctl) {
973 dev_err(pcs->dev, "could not register single pinctrl driver\n"); 973 dev_err(pcs->dev, "could not register single pinctrl driver\n");
974 ret = -EINVAL; 974 ret = -EINVAL;
975 goto free; 975 goto free;
976 } 976 }
977 977
978 dev_info(pcs->dev, "%i pins at pa %p size %u\n", 978 dev_info(pcs->dev, "%i pins at pa %p size %u\n",
979 pcs->desc.npins, pcs->base, pcs->size); 979 pcs->desc.npins, pcs->base, pcs->size);
980 980
981 return 0; 981 return 0;
982 982
983 free: 983 free:
984 pcs_free_resources(pcs); 984 pcs_free_resources(pcs);
985 985
986 return ret; 986 return ret;
987 } 987 }
988 988
989 static int __devexit pcs_remove(struct platform_device *pdev) 989 static int pcs_remove(struct platform_device *pdev)
990 { 990 {
991 struct pcs_device *pcs = platform_get_drvdata(pdev); 991 struct pcs_device *pcs = platform_get_drvdata(pdev);
992 992
993 if (!pcs) 993 if (!pcs)
994 return 0; 994 return 0;
995 995
996 pcs_free_resources(pcs); 996 pcs_free_resources(pcs);
997 997
998 return 0; 998 return 0;
999 } 999 }
1000 1000
1001 static struct of_device_id pcs_of_match[] = { 1001 static struct of_device_id pcs_of_match[] = {
1002 { .compatible = DRIVER_NAME, }, 1002 { .compatible = DRIVER_NAME, },
1003 { }, 1003 { },
1004 }; 1004 };
1005 MODULE_DEVICE_TABLE(of, pcs_of_match); 1005 MODULE_DEVICE_TABLE(of, pcs_of_match);
1006 1006
1007 static struct platform_driver pcs_driver = { 1007 static struct platform_driver pcs_driver = {
1008 .probe = pcs_probe, 1008 .probe = pcs_probe,
1009 .remove = pcs_remove, 1009 .remove = pcs_remove,
1010 .driver = { 1010 .driver = {
1011 .owner = THIS_MODULE, 1011 .owner = THIS_MODULE,
1012 .name = DRIVER_NAME, 1012 .name = DRIVER_NAME,
1013 .of_match_table = pcs_of_match, 1013 .of_match_table = pcs_of_match,
1014 }, 1014 },
1015 }; 1015 };
1016 1016
1017 module_platform_driver(pcs_driver); 1017 module_platform_driver(pcs_driver);
1018 1018
1019 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); 1019 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1020 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver"); 1020 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1021 MODULE_LICENSE("GPL v2"); 1021 MODULE_LICENSE("GPL v2");
1022 1022
drivers/pinctrl/pinctrl-tegra.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Driver for the NVIDIA Tegra pinmux 2 * Driver for the NVIDIA Tegra pinmux
3 * 3 *
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Derived from code: 6 * Derived from code:
7 * Copyright (C) 2010 Google, Inc. 7 * Copyright (C) 2010 Google, Inc.
8 * Copyright (C) 2010 NVIDIA Corporation 8 * Copyright (C) 2010 NVIDIA Corporation
9 * Copyright (C) 2009-2011 ST-Ericsson AB 9 * Copyright (C) 2009-2011 ST-Ericsson AB
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify it 11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License, 12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation. 13 * version 2, as published by the Free Software Foundation.
14 * 14 *
15 * This program is distributed in the hope it will be useful, but WITHOUT 15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details. 18 * more details.
19 */ 19 */
20 20
21 #include <linux/err.h> 21 #include <linux/err.h>
22 #include <linux/init.h> 22 #include <linux/init.h>
23 #include <linux/io.h> 23 #include <linux/io.h>
24 #include <linux/module.h> 24 #include <linux/module.h>
25 #include <linux/of.h> 25 #include <linux/of.h>
26 #include <linux/platform_device.h> 26 #include <linux/platform_device.h>
27 #include <linux/pinctrl/machine.h> 27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h> 29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h> 30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/slab.h> 31 #include <linux/slab.h>
32 32
33 #include "core.h" 33 #include "core.h"
34 #include "pinctrl-tegra.h" 34 #include "pinctrl-tegra.h"
35 35
36 struct tegra_pmx { 36 struct tegra_pmx {
37 struct device *dev; 37 struct device *dev;
38 struct pinctrl_dev *pctl; 38 struct pinctrl_dev *pctl;
39 39
40 const struct tegra_pinctrl_soc_data *soc; 40 const struct tegra_pinctrl_soc_data *soc;
41 41
42 int nbanks; 42 int nbanks;
43 void __iomem **regs; 43 void __iomem **regs;
44 }; 44 };
45 45
46 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) 46 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
47 { 47 {
48 return readl(pmx->regs[bank] + reg); 48 return readl(pmx->regs[bank] + reg);
49 } 49 }
50 50
51 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) 51 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
52 { 52 {
53 writel(val, pmx->regs[bank] + reg); 53 writel(val, pmx->regs[bank] + reg);
54 } 54 }
55 55
56 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 56 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
57 { 57 {
58 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 58 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
59 59
60 return pmx->soc->ngroups; 60 return pmx->soc->ngroups;
61 } 61 }
62 62
63 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 63 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
64 unsigned group) 64 unsigned group)
65 { 65 {
66 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 66 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
67 67
68 return pmx->soc->groups[group].name; 68 return pmx->soc->groups[group].name;
69 } 69 }
70 70
71 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 71 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
72 unsigned group, 72 unsigned group,
73 const unsigned **pins, 73 const unsigned **pins,
74 unsigned *num_pins) 74 unsigned *num_pins)
75 { 75 {
76 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 76 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
77 77
78 *pins = pmx->soc->groups[group].pins; 78 *pins = pmx->soc->groups[group].pins;
79 *num_pins = pmx->soc->groups[group].npins; 79 *num_pins = pmx->soc->groups[group].npins;
80 80
81 return 0; 81 return 0;
82 } 82 }
83 83
84 #ifdef CONFIG_DEBUG_FS 84 #ifdef CONFIG_DEBUG_FS
85 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 85 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
86 struct seq_file *s, 86 struct seq_file *s,
87 unsigned offset) 87 unsigned offset)
88 { 88 {
89 seq_printf(s, " %s", dev_name(pctldev->dev)); 89 seq_printf(s, " %s", dev_name(pctldev->dev));
90 } 90 }
91 #endif 91 #endif
92 92
93 static int reserve_map(struct device *dev, struct pinctrl_map **map, 93 static int reserve_map(struct device *dev, struct pinctrl_map **map,
94 unsigned *reserved_maps, unsigned *num_maps, 94 unsigned *reserved_maps, unsigned *num_maps,
95 unsigned reserve) 95 unsigned reserve)
96 { 96 {
97 unsigned old_num = *reserved_maps; 97 unsigned old_num = *reserved_maps;
98 unsigned new_num = *num_maps + reserve; 98 unsigned new_num = *num_maps + reserve;
99 struct pinctrl_map *new_map; 99 struct pinctrl_map *new_map;
100 100
101 if (old_num >= new_num) 101 if (old_num >= new_num)
102 return 0; 102 return 0;
103 103
104 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); 104 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
105 if (!new_map) { 105 if (!new_map) {
106 dev_err(dev, "krealloc(map) failed\n"); 106 dev_err(dev, "krealloc(map) failed\n");
107 return -ENOMEM; 107 return -ENOMEM;
108 } 108 }
109 109
110 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); 110 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
111 111
112 *map = new_map; 112 *map = new_map;
113 *reserved_maps = new_num; 113 *reserved_maps = new_num;
114 114
115 return 0; 115 return 0;
116 } 116 }
117 117
118 static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 118 static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
119 unsigned *num_maps, const char *group, 119 unsigned *num_maps, const char *group,
120 const char *function) 120 const char *function)
121 { 121 {
122 if (WARN_ON(*num_maps == *reserved_maps)) 122 if (WARN_ON(*num_maps == *reserved_maps))
123 return -ENOSPC; 123 return -ENOSPC;
124 124
125 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 125 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
126 (*map)[*num_maps].data.mux.group = group; 126 (*map)[*num_maps].data.mux.group = group;
127 (*map)[*num_maps].data.mux.function = function; 127 (*map)[*num_maps].data.mux.function = function;
128 (*num_maps)++; 128 (*num_maps)++;
129 129
130 return 0; 130 return 0;
131 } 131 }
132 132
133 static int add_map_configs(struct device *dev, struct pinctrl_map **map, 133 static int add_map_configs(struct device *dev, struct pinctrl_map **map,
134 unsigned *reserved_maps, unsigned *num_maps, 134 unsigned *reserved_maps, unsigned *num_maps,
135 const char *group, unsigned long *configs, 135 const char *group, unsigned long *configs,
136 unsigned num_configs) 136 unsigned num_configs)
137 { 137 {
138 unsigned long *dup_configs; 138 unsigned long *dup_configs;
139 139
140 if (WARN_ON(*num_maps == *reserved_maps)) 140 if (WARN_ON(*num_maps == *reserved_maps))
141 return -ENOSPC; 141 return -ENOSPC;
142 142
143 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 143 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
144 GFP_KERNEL); 144 GFP_KERNEL);
145 if (!dup_configs) { 145 if (!dup_configs) {
146 dev_err(dev, "kmemdup(configs) failed\n"); 146 dev_err(dev, "kmemdup(configs) failed\n");
147 return -ENOMEM; 147 return -ENOMEM;
148 } 148 }
149 149
150 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 150 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
151 (*map)[*num_maps].data.configs.group_or_pin = group; 151 (*map)[*num_maps].data.configs.group_or_pin = group;
152 (*map)[*num_maps].data.configs.configs = dup_configs; 152 (*map)[*num_maps].data.configs.configs = dup_configs;
153 (*map)[*num_maps].data.configs.num_configs = num_configs; 153 (*map)[*num_maps].data.configs.num_configs = num_configs;
154 (*num_maps)++; 154 (*num_maps)++;
155 155
156 return 0; 156 return 0;
157 } 157 }
158 158
159 static int add_config(struct device *dev, unsigned long **configs, 159 static int add_config(struct device *dev, unsigned long **configs,
160 unsigned *num_configs, unsigned long config) 160 unsigned *num_configs, unsigned long config)
161 { 161 {
162 unsigned old_num = *num_configs; 162 unsigned old_num = *num_configs;
163 unsigned new_num = old_num + 1; 163 unsigned new_num = old_num + 1;
164 unsigned long *new_configs; 164 unsigned long *new_configs;
165 165
166 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, 166 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
167 GFP_KERNEL); 167 GFP_KERNEL);
168 if (!new_configs) { 168 if (!new_configs) {
169 dev_err(dev, "krealloc(configs) failed\n"); 169 dev_err(dev, "krealloc(configs) failed\n");
170 return -ENOMEM; 170 return -ENOMEM;
171 } 171 }
172 172
173 new_configs[old_num] = config; 173 new_configs[old_num] = config;
174 174
175 *configs = new_configs; 175 *configs = new_configs;
176 *num_configs = new_num; 176 *num_configs = new_num;
177 177
178 return 0; 178 return 0;
179 } 179 }
180 180
181 void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, 181 void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
182 struct pinctrl_map *map, unsigned num_maps) 182 struct pinctrl_map *map, unsigned num_maps)
183 { 183 {
184 int i; 184 int i;
185 185
186 for (i = 0; i < num_maps; i++) 186 for (i = 0; i < num_maps; i++)
187 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) 187 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
188 kfree(map[i].data.configs.configs); 188 kfree(map[i].data.configs.configs);
189 189
190 kfree(map); 190 kfree(map);
191 } 191 }
192 192
193 static const struct cfg_param { 193 static const struct cfg_param {
194 const char *property; 194 const char *property;
195 enum tegra_pinconf_param param; 195 enum tegra_pinconf_param param;
196 } cfg_params[] = { 196 } cfg_params[] = {
197 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL}, 197 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
198 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE}, 198 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
199 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT}, 199 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
200 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN}, 200 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
201 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, 201 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
202 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, 202 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
203 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, 203 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
204 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, 204 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
205 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, 205 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
206 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH}, 206 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
207 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH}, 207 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
208 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, 208 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
209 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, 209 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
210 }; 210 };
211 211
212 int tegra_pinctrl_dt_subnode_to_map(struct device *dev, 212 int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
213 struct device_node *np, 213 struct device_node *np,
214 struct pinctrl_map **map, 214 struct pinctrl_map **map,
215 unsigned *reserved_maps, 215 unsigned *reserved_maps,
216 unsigned *num_maps) 216 unsigned *num_maps)
217 { 217 {
218 int ret, i; 218 int ret, i;
219 const char *function; 219 const char *function;
220 u32 val; 220 u32 val;
221 unsigned long config; 221 unsigned long config;
222 unsigned long *configs = NULL; 222 unsigned long *configs = NULL;
223 unsigned num_configs = 0; 223 unsigned num_configs = 0;
224 unsigned reserve; 224 unsigned reserve;
225 struct property *prop; 225 struct property *prop;
226 const char *group; 226 const char *group;
227 227
228 ret = of_property_read_string(np, "nvidia,function", &function); 228 ret = of_property_read_string(np, "nvidia,function", &function);
229 if (ret < 0) { 229 if (ret < 0) {
230 /* EINVAL=missing, which is fine since it's optional */ 230 /* EINVAL=missing, which is fine since it's optional */
231 if (ret != -EINVAL) 231 if (ret != -EINVAL)
232 dev_err(dev, 232 dev_err(dev,
233 "could not parse property nvidia,function\n"); 233 "could not parse property nvidia,function\n");
234 function = NULL; 234 function = NULL;
235 } 235 }
236 236
237 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 237 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
238 ret = of_property_read_u32(np, cfg_params[i].property, &val); 238 ret = of_property_read_u32(np, cfg_params[i].property, &val);
239 if (!ret) { 239 if (!ret) {
240 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); 240 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
241 ret = add_config(dev, &configs, &num_configs, config); 241 ret = add_config(dev, &configs, &num_configs, config);
242 if (ret < 0) 242 if (ret < 0)
243 goto exit; 243 goto exit;
244 /* EINVAL=missing, which is fine since it's optional */ 244 /* EINVAL=missing, which is fine since it's optional */
245 } else if (ret != -EINVAL) { 245 } else if (ret != -EINVAL) {
246 dev_err(dev, "could not parse property %s\n", 246 dev_err(dev, "could not parse property %s\n",
247 cfg_params[i].property); 247 cfg_params[i].property);
248 } 248 }
249 } 249 }
250 250
251 reserve = 0; 251 reserve = 0;
252 if (function != NULL) 252 if (function != NULL)
253 reserve++; 253 reserve++;
254 if (num_configs) 254 if (num_configs)
255 reserve++; 255 reserve++;
256 ret = of_property_count_strings(np, "nvidia,pins"); 256 ret = of_property_count_strings(np, "nvidia,pins");
257 if (ret < 0) { 257 if (ret < 0) {
258 dev_err(dev, "could not parse property nvidia,pins\n"); 258 dev_err(dev, "could not parse property nvidia,pins\n");
259 goto exit; 259 goto exit;
260 } 260 }
261 reserve *= ret; 261 reserve *= ret;
262 262
263 ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); 263 ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
264 if (ret < 0) 264 if (ret < 0)
265 goto exit; 265 goto exit;
266 266
267 of_property_for_each_string(np, "nvidia,pins", prop, group) { 267 of_property_for_each_string(np, "nvidia,pins", prop, group) {
268 if (function) { 268 if (function) {
269 ret = add_map_mux(map, reserved_maps, num_maps, 269 ret = add_map_mux(map, reserved_maps, num_maps,
270 group, function); 270 group, function);
271 if (ret < 0) 271 if (ret < 0)
272 goto exit; 272 goto exit;
273 } 273 }
274 274
275 if (num_configs) { 275 if (num_configs) {
276 ret = add_map_configs(dev, map, reserved_maps, 276 ret = add_map_configs(dev, map, reserved_maps,
277 num_maps, group, configs, 277 num_maps, group, configs,
278 num_configs); 278 num_configs);
279 if (ret < 0) 279 if (ret < 0)
280 goto exit; 280 goto exit;
281 } 281 }
282 } 282 }
283 283
284 ret = 0; 284 ret = 0;
285 285
286 exit: 286 exit:
287 kfree(configs); 287 kfree(configs);
288 return ret; 288 return ret;
289 } 289 }
290 290
291 int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 291 int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
292 struct device_node *np_config, 292 struct device_node *np_config,
293 struct pinctrl_map **map, unsigned *num_maps) 293 struct pinctrl_map **map, unsigned *num_maps)
294 { 294 {
295 unsigned reserved_maps; 295 unsigned reserved_maps;
296 struct device_node *np; 296 struct device_node *np;
297 int ret; 297 int ret;
298 298
299 reserved_maps = 0; 299 reserved_maps = 0;
300 *map = NULL; 300 *map = NULL;
301 *num_maps = 0; 301 *num_maps = 0;
302 302
303 for_each_child_of_node(np_config, np) { 303 for_each_child_of_node(np_config, np) {
304 ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map, 304 ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
305 &reserved_maps, num_maps); 305 &reserved_maps, num_maps);
306 if (ret < 0) { 306 if (ret < 0) {
307 tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps); 307 tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
308 return ret; 308 return ret;
309 } 309 }
310 } 310 }
311 311
312 return 0; 312 return 0;
313 } 313 }
314 314
315 static struct pinctrl_ops tegra_pinctrl_ops = { 315 static struct pinctrl_ops tegra_pinctrl_ops = {
316 .get_groups_count = tegra_pinctrl_get_groups_count, 316 .get_groups_count = tegra_pinctrl_get_groups_count,
317 .get_group_name = tegra_pinctrl_get_group_name, 317 .get_group_name = tegra_pinctrl_get_group_name,
318 .get_group_pins = tegra_pinctrl_get_group_pins, 318 .get_group_pins = tegra_pinctrl_get_group_pins,
319 #ifdef CONFIG_DEBUG_FS 319 #ifdef CONFIG_DEBUG_FS
320 .pin_dbg_show = tegra_pinctrl_pin_dbg_show, 320 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
321 #endif 321 #endif
322 .dt_node_to_map = tegra_pinctrl_dt_node_to_map, 322 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
323 .dt_free_map = tegra_pinctrl_dt_free_map, 323 .dt_free_map = tegra_pinctrl_dt_free_map,
324 }; 324 };
325 325
326 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) 326 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
327 { 327 {
328 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 328 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
329 329
330 return pmx->soc->nfunctions; 330 return pmx->soc->nfunctions;
331 } 331 }
332 332
333 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 333 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
334 unsigned function) 334 unsigned function)
335 { 335 {
336 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 336 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
337 337
338 return pmx->soc->functions[function].name; 338 return pmx->soc->functions[function].name;
339 } 339 }
340 340
341 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, 341 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
342 unsigned function, 342 unsigned function,
343 const char * const **groups, 343 const char * const **groups,
344 unsigned * const num_groups) 344 unsigned * const num_groups)
345 { 345 {
346 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 346 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
347 347
348 *groups = pmx->soc->functions[function].groups; 348 *groups = pmx->soc->functions[function].groups;
349 *num_groups = pmx->soc->functions[function].ngroups; 349 *num_groups = pmx->soc->functions[function].ngroups;
350 350
351 return 0; 351 return 0;
352 } 352 }
353 353
354 static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, 354 static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
355 unsigned group) 355 unsigned group)
356 { 356 {
357 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 357 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
358 const struct tegra_pingroup *g; 358 const struct tegra_pingroup *g;
359 int i; 359 int i;
360 u32 val; 360 u32 val;
361 361
362 g = &pmx->soc->groups[group]; 362 g = &pmx->soc->groups[group];
363 363
364 if (WARN_ON(g->mux_reg < 0)) 364 if (WARN_ON(g->mux_reg < 0))
365 return -EINVAL; 365 return -EINVAL;
366 366
367 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { 367 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
368 if (g->funcs[i] == function) 368 if (g->funcs[i] == function)
369 break; 369 break;
370 } 370 }
371 if (WARN_ON(i == ARRAY_SIZE(g->funcs))) 371 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
372 return -EINVAL; 372 return -EINVAL;
373 373
374 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 374 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
375 val &= ~(0x3 << g->mux_bit); 375 val &= ~(0x3 << g->mux_bit);
376 val |= i << g->mux_bit; 376 val |= i << g->mux_bit;
377 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); 377 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
378 378
379 return 0; 379 return 0;
380 } 380 }
381 381
382 static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev, 382 static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
383 unsigned function, unsigned group) 383 unsigned function, unsigned group)
384 { 384 {
385 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 385 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
386 const struct tegra_pingroup *g; 386 const struct tegra_pingroup *g;
387 u32 val; 387 u32 val;
388 388
389 g = &pmx->soc->groups[group]; 389 g = &pmx->soc->groups[group];
390 390
391 if (WARN_ON(g->mux_reg < 0)) 391 if (WARN_ON(g->mux_reg < 0))
392 return; 392 return;
393 393
394 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 394 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
395 val &= ~(0x3 << g->mux_bit); 395 val &= ~(0x3 << g->mux_bit);
396 val |= g->func_safe << g->mux_bit; 396 val |= g->func_safe << g->mux_bit;
397 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); 397 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
398 } 398 }
399 399
400 static struct pinmux_ops tegra_pinmux_ops = { 400 static struct pinmux_ops tegra_pinmux_ops = {
401 .get_functions_count = tegra_pinctrl_get_funcs_count, 401 .get_functions_count = tegra_pinctrl_get_funcs_count,
402 .get_function_name = tegra_pinctrl_get_func_name, 402 .get_function_name = tegra_pinctrl_get_func_name,
403 .get_function_groups = tegra_pinctrl_get_func_groups, 403 .get_function_groups = tegra_pinctrl_get_func_groups,
404 .enable = tegra_pinctrl_enable, 404 .enable = tegra_pinctrl_enable,
405 .disable = tegra_pinctrl_disable, 405 .disable = tegra_pinctrl_disable,
406 }; 406 };
407 407
408 static int tegra_pinconf_reg(struct tegra_pmx *pmx, 408 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
409 const struct tegra_pingroup *g, 409 const struct tegra_pingroup *g,
410 enum tegra_pinconf_param param, 410 enum tegra_pinconf_param param,
411 bool report_err, 411 bool report_err,
412 s8 *bank, s16 *reg, s8 *bit, s8 *width) 412 s8 *bank, s16 *reg, s8 *bit, s8 *width)
413 { 413 {
414 switch (param) { 414 switch (param) {
415 case TEGRA_PINCONF_PARAM_PULL: 415 case TEGRA_PINCONF_PARAM_PULL:
416 *bank = g->pupd_bank; 416 *bank = g->pupd_bank;
417 *reg = g->pupd_reg; 417 *reg = g->pupd_reg;
418 *bit = g->pupd_bit; 418 *bit = g->pupd_bit;
419 *width = 2; 419 *width = 2;
420 break; 420 break;
421 case TEGRA_PINCONF_PARAM_TRISTATE: 421 case TEGRA_PINCONF_PARAM_TRISTATE:
422 *bank = g->tri_bank; 422 *bank = g->tri_bank;
423 *reg = g->tri_reg; 423 *reg = g->tri_reg;
424 *bit = g->tri_bit; 424 *bit = g->tri_bit;
425 *width = 1; 425 *width = 1;
426 break; 426 break;
427 case TEGRA_PINCONF_PARAM_ENABLE_INPUT: 427 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
428 *bank = g->einput_bank; 428 *bank = g->einput_bank;
429 *reg = g->einput_reg; 429 *reg = g->einput_reg;
430 *bit = g->einput_bit; 430 *bit = g->einput_bit;
431 *width = 1; 431 *width = 1;
432 break; 432 break;
433 case TEGRA_PINCONF_PARAM_OPEN_DRAIN: 433 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
434 *bank = g->odrain_bank; 434 *bank = g->odrain_bank;
435 *reg = g->odrain_reg; 435 *reg = g->odrain_reg;
436 *bit = g->odrain_bit; 436 *bit = g->odrain_bit;
437 *width = 1; 437 *width = 1;
438 break; 438 break;
439 case TEGRA_PINCONF_PARAM_LOCK: 439 case TEGRA_PINCONF_PARAM_LOCK:
440 *bank = g->lock_bank; 440 *bank = g->lock_bank;
441 *reg = g->lock_reg; 441 *reg = g->lock_reg;
442 *bit = g->lock_bit; 442 *bit = g->lock_bit;
443 *width = 1; 443 *width = 1;
444 break; 444 break;
445 case TEGRA_PINCONF_PARAM_IORESET: 445 case TEGRA_PINCONF_PARAM_IORESET:
446 *bank = g->ioreset_bank; 446 *bank = g->ioreset_bank;
447 *reg = g->ioreset_reg; 447 *reg = g->ioreset_reg;
448 *bit = g->ioreset_bit; 448 *bit = g->ioreset_bit;
449 *width = 1; 449 *width = 1;
450 break; 450 break;
451 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE: 451 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
452 *bank = g->drv_bank; 452 *bank = g->drv_bank;
453 *reg = g->drv_reg; 453 *reg = g->drv_reg;
454 *bit = g->hsm_bit; 454 *bit = g->hsm_bit;
455 *width = 1; 455 *width = 1;
456 break; 456 break;
457 case TEGRA_PINCONF_PARAM_SCHMITT: 457 case TEGRA_PINCONF_PARAM_SCHMITT:
458 *bank = g->drv_bank; 458 *bank = g->drv_bank;
459 *reg = g->drv_reg; 459 *reg = g->drv_reg;
460 *bit = g->schmitt_bit; 460 *bit = g->schmitt_bit;
461 *width = 1; 461 *width = 1;
462 break; 462 break;
463 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE: 463 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
464 *bank = g->drv_bank; 464 *bank = g->drv_bank;
465 *reg = g->drv_reg; 465 *reg = g->drv_reg;
466 *bit = g->lpmd_bit; 466 *bit = g->lpmd_bit;
467 *width = 2; 467 *width = 2;
468 break; 468 break;
469 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH: 469 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
470 *bank = g->drv_bank; 470 *bank = g->drv_bank;
471 *reg = g->drv_reg; 471 *reg = g->drv_reg;
472 *bit = g->drvdn_bit; 472 *bit = g->drvdn_bit;
473 *width = g->drvdn_width; 473 *width = g->drvdn_width;
474 break; 474 break;
475 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH: 475 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
476 *bank = g->drv_bank; 476 *bank = g->drv_bank;
477 *reg = g->drv_reg; 477 *reg = g->drv_reg;
478 *bit = g->drvup_bit; 478 *bit = g->drvup_bit;
479 *width = g->drvup_width; 479 *width = g->drvup_width;
480 break; 480 break;
481 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING: 481 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
482 *bank = g->drv_bank; 482 *bank = g->drv_bank;
483 *reg = g->drv_reg; 483 *reg = g->drv_reg;
484 *bit = g->slwf_bit; 484 *bit = g->slwf_bit;
485 *width = g->slwf_width; 485 *width = g->slwf_width;
486 break; 486 break;
487 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING: 487 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
488 *bank = g->drv_bank; 488 *bank = g->drv_bank;
489 *reg = g->drv_reg; 489 *reg = g->drv_reg;
490 *bit = g->slwr_bit; 490 *bit = g->slwr_bit;
491 *width = g->slwr_width; 491 *width = g->slwr_width;
492 break; 492 break;
493 default: 493 default:
494 dev_err(pmx->dev, "Invalid config param %04x\n", param); 494 dev_err(pmx->dev, "Invalid config param %04x\n", param);
495 return -ENOTSUPP; 495 return -ENOTSUPP;
496 } 496 }
497 497
498 if (*reg < 0) { 498 if (*reg < 0) {
499 if (report_err) 499 if (report_err)
500 dev_err(pmx->dev, 500 dev_err(pmx->dev,
501 "Config param %04x not supported on group %s\n", 501 "Config param %04x not supported on group %s\n",
502 param, g->name); 502 param, g->name);
503 return -ENOTSUPP; 503 return -ENOTSUPP;
504 } 504 }
505 505
506 return 0; 506 return 0;
507 } 507 }
508 508
509 static int tegra_pinconf_get(struct pinctrl_dev *pctldev, 509 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
510 unsigned pin, unsigned long *config) 510 unsigned pin, unsigned long *config)
511 { 511 {
512 dev_err(pctldev->dev, "pin_config_get op not supported\n"); 512 dev_err(pctldev->dev, "pin_config_get op not supported\n");
513 return -ENOTSUPP; 513 return -ENOTSUPP;
514 } 514 }
515 515
516 static int tegra_pinconf_set(struct pinctrl_dev *pctldev, 516 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
517 unsigned pin, unsigned long config) 517 unsigned pin, unsigned long config)
518 { 518 {
519 dev_err(pctldev->dev, "pin_config_set op not supported\n"); 519 dev_err(pctldev->dev, "pin_config_set op not supported\n");
520 return -ENOTSUPP; 520 return -ENOTSUPP;
521 } 521 }
522 522
523 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, 523 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
524 unsigned group, unsigned long *config) 524 unsigned group, unsigned long *config)
525 { 525 {
526 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 526 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
527 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config); 527 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
528 u16 arg; 528 u16 arg;
529 const struct tegra_pingroup *g; 529 const struct tegra_pingroup *g;
530 int ret; 530 int ret;
531 s8 bank, bit, width; 531 s8 bank, bit, width;
532 s16 reg; 532 s16 reg;
533 u32 val, mask; 533 u32 val, mask;
534 534
535 g = &pmx->soc->groups[group]; 535 g = &pmx->soc->groups[group];
536 536
537 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit, 537 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
538 &width); 538 &width);
539 if (ret < 0) 539 if (ret < 0)
540 return ret; 540 return ret;
541 541
542 val = pmx_readl(pmx, bank, reg); 542 val = pmx_readl(pmx, bank, reg);
543 mask = (1 << width) - 1; 543 mask = (1 << width) - 1;
544 arg = (val >> bit) & mask; 544 arg = (val >> bit) & mask;
545 545
546 *config = TEGRA_PINCONF_PACK(param, arg); 546 *config = TEGRA_PINCONF_PACK(param, arg);
547 547
548 return 0; 548 return 0;
549 } 549 }
550 550
551 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, 551 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
552 unsigned group, unsigned long config) 552 unsigned group, unsigned long config)
553 { 553 {
554 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 554 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
555 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); 555 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
556 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); 556 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
557 const struct tegra_pingroup *g; 557 const struct tegra_pingroup *g;
558 int ret; 558 int ret;
559 s8 bank, bit, width; 559 s8 bank, bit, width;
560 s16 reg; 560 s16 reg;
561 u32 val, mask; 561 u32 val, mask;
562 562
563 g = &pmx->soc->groups[group]; 563 g = &pmx->soc->groups[group];
564 564
565 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit, 565 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
566 &width); 566 &width);
567 if (ret < 0) 567 if (ret < 0)
568 return ret; 568 return ret;
569 569
570 val = pmx_readl(pmx, bank, reg); 570 val = pmx_readl(pmx, bank, reg);
571 571
572 /* LOCK can't be cleared */ 572 /* LOCK can't be cleared */
573 if (param == TEGRA_PINCONF_PARAM_LOCK) { 573 if (param == TEGRA_PINCONF_PARAM_LOCK) {
574 if ((val & BIT(bit)) && !arg) { 574 if ((val & BIT(bit)) && !arg) {
575 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); 575 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
576 return -EINVAL; 576 return -EINVAL;
577 } 577 }
578 } 578 }
579 579
580 /* Special-case Boolean values; allow any non-zero as true */ 580 /* Special-case Boolean values; allow any non-zero as true */
581 if (width == 1) 581 if (width == 1)
582 arg = !!arg; 582 arg = !!arg;
583 583
584 /* Range-check user-supplied value */ 584 /* Range-check user-supplied value */
585 mask = (1 << width) - 1; 585 mask = (1 << width) - 1;
586 if (arg & ~mask) { 586 if (arg & ~mask) {
587 dev_err(pctldev->dev, 587 dev_err(pctldev->dev,
588 "config %lx: %x too big for %d bit register\n", 588 "config %lx: %x too big for %d bit register\n",
589 config, arg, width); 589 config, arg, width);
590 return -EINVAL; 590 return -EINVAL;
591 } 591 }
592 592
593 /* Update register */ 593 /* Update register */
594 val &= ~(mask << bit); 594 val &= ~(mask << bit);
595 val |= arg << bit; 595 val |= arg << bit;
596 pmx_writel(pmx, val, bank, reg); 596 pmx_writel(pmx, val, bank, reg);
597 597
598 return 0; 598 return 0;
599 } 599 }
600 600
601 #ifdef CONFIG_DEBUG_FS 601 #ifdef CONFIG_DEBUG_FS
602 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, 602 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
603 struct seq_file *s, unsigned offset) 603 struct seq_file *s, unsigned offset)
604 { 604 {
605 } 605 }
606 606
607 static const char *strip_prefix(const char *s) 607 static const char *strip_prefix(const char *s)
608 { 608 {
609 const char *comma = strchr(s, ','); 609 const char *comma = strchr(s, ',');
610 if (!comma) 610 if (!comma)
611 return s; 611 return s;
612 612
613 return comma + 1; 613 return comma + 1;
614 } 614 }
615 615
616 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 616 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
617 struct seq_file *s, unsigned group) 617 struct seq_file *s, unsigned group)
618 { 618 {
619 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 619 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
620 const struct tegra_pingroup *g; 620 const struct tegra_pingroup *g;
621 int i, ret; 621 int i, ret;
622 s8 bank, bit, width; 622 s8 bank, bit, width;
623 s16 reg; 623 s16 reg;
624 u32 val; 624 u32 val;
625 625
626 g = &pmx->soc->groups[group]; 626 g = &pmx->soc->groups[group];
627 627
628 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 628 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
629 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false, 629 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
630 &bank, &reg, &bit, &width); 630 &bank, &reg, &bit, &width);
631 if (ret < 0) 631 if (ret < 0)
632 continue; 632 continue;
633 633
634 val = pmx_readl(pmx, bank, reg); 634 val = pmx_readl(pmx, bank, reg);
635 val >>= bit; 635 val >>= bit;
636 val &= (1 << width) - 1; 636 val &= (1 << width) - 1;
637 637
638 seq_printf(s, "\n\t%s=%u", 638 seq_printf(s, "\n\t%s=%u",
639 strip_prefix(cfg_params[i].property), val); 639 strip_prefix(cfg_params[i].property), val);
640 } 640 }
641 } 641 }
642 642
643 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, 643 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
644 struct seq_file *s, 644 struct seq_file *s,
645 unsigned long config) 645 unsigned long config)
646 { 646 {
647 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); 647 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
648 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); 648 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
649 const char *pname = "unknown"; 649 const char *pname = "unknown";
650 int i; 650 int i;
651 651
652 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 652 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
653 if (cfg_params[i].param == param) { 653 if (cfg_params[i].param == param) {
654 pname = cfg_params[i].property; 654 pname = cfg_params[i].property;
655 break; 655 break;
656 } 656 }
657 } 657 }
658 658
659 seq_printf(s, "%s=%d", strip_prefix(pname), arg); 659 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
660 } 660 }
661 #endif 661 #endif
662 662
663 struct pinconf_ops tegra_pinconf_ops = { 663 struct pinconf_ops tegra_pinconf_ops = {
664 .pin_config_get = tegra_pinconf_get, 664 .pin_config_get = tegra_pinconf_get,
665 .pin_config_set = tegra_pinconf_set, 665 .pin_config_set = tegra_pinconf_set,
666 .pin_config_group_get = tegra_pinconf_group_get, 666 .pin_config_group_get = tegra_pinconf_group_get,
667 .pin_config_group_set = tegra_pinconf_group_set, 667 .pin_config_group_set = tegra_pinconf_group_set,
668 #ifdef CONFIG_DEBUG_FS 668 #ifdef CONFIG_DEBUG_FS
669 .pin_config_dbg_show = tegra_pinconf_dbg_show, 669 .pin_config_dbg_show = tegra_pinconf_dbg_show,
670 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, 670 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
671 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show, 671 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
672 #endif 672 #endif
673 }; 673 };
674 674
675 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { 675 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
676 .name = "Tegra GPIOs", 676 .name = "Tegra GPIOs",
677 .id = 0, 677 .id = 0,
678 .base = 0, 678 .base = 0,
679 }; 679 };
680 680
681 static struct pinctrl_desc tegra_pinctrl_desc = { 681 static struct pinctrl_desc tegra_pinctrl_desc = {
682 .pctlops = &tegra_pinctrl_ops, 682 .pctlops = &tegra_pinctrl_ops,
683 .pmxops = &tegra_pinmux_ops, 683 .pmxops = &tegra_pinmux_ops,
684 .confops = &tegra_pinconf_ops, 684 .confops = &tegra_pinconf_ops,
685 .owner = THIS_MODULE, 685 .owner = THIS_MODULE,
686 }; 686 };
687 687
688 int __devinit tegra_pinctrl_probe(struct platform_device *pdev, 688 int __devinit tegra_pinctrl_probe(struct platform_device *pdev,
689 const struct tegra_pinctrl_soc_data *soc_data) 689 const struct tegra_pinctrl_soc_data *soc_data)
690 { 690 {
691 struct tegra_pmx *pmx; 691 struct tegra_pmx *pmx;
692 struct resource *res; 692 struct resource *res;
693 int i; 693 int i;
694 694
695 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 695 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
696 if (!pmx) { 696 if (!pmx) {
697 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n"); 697 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
698 return -ENOMEM; 698 return -ENOMEM;
699 } 699 }
700 pmx->dev = &pdev->dev; 700 pmx->dev = &pdev->dev;
701 pmx->soc = soc_data; 701 pmx->soc = soc_data;
702 702
703 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; 703 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
704 tegra_pinctrl_desc.name = dev_name(&pdev->dev); 704 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
705 tegra_pinctrl_desc.pins = pmx->soc->pins; 705 tegra_pinctrl_desc.pins = pmx->soc->pins;
706 tegra_pinctrl_desc.npins = pmx->soc->npins; 706 tegra_pinctrl_desc.npins = pmx->soc->npins;
707 707
708 for (i = 0; ; i++) { 708 for (i = 0; ; i++) {
709 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 709 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
710 if (!res) 710 if (!res)
711 break; 711 break;
712 } 712 }
713 pmx->nbanks = i; 713 pmx->nbanks = i;
714 714
715 pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs), 715 pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
716 GFP_KERNEL); 716 GFP_KERNEL);
717 if (!pmx->regs) { 717 if (!pmx->regs) {
718 dev_err(&pdev->dev, "Can't alloc regs pointer\n"); 718 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
719 return -ENODEV; 719 return -ENODEV;
720 } 720 }
721 721
722 for (i = 0; i < pmx->nbanks; i++) { 722 for (i = 0; i < pmx->nbanks; i++) {
723 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 723 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
724 if (!res) { 724 if (!res) {
725 dev_err(&pdev->dev, "Missing MEM resource\n"); 725 dev_err(&pdev->dev, "Missing MEM resource\n");
726 return -ENODEV; 726 return -ENODEV;
727 } 727 }
728 728
729 if (!devm_request_mem_region(&pdev->dev, res->start, 729 if (!devm_request_mem_region(&pdev->dev, res->start,
730 resource_size(res), 730 resource_size(res),
731 dev_name(&pdev->dev))) { 731 dev_name(&pdev->dev))) {
732 dev_err(&pdev->dev, 732 dev_err(&pdev->dev,
733 "Couldn't request MEM resource %d\n", i); 733 "Couldn't request MEM resource %d\n", i);
734 return -ENODEV; 734 return -ENODEV;
735 } 735 }
736 736
737 pmx->regs[i] = devm_ioremap(&pdev->dev, res->start, 737 pmx->regs[i] = devm_ioremap(&pdev->dev, res->start,
738 resource_size(res)); 738 resource_size(res));
739 if (!pmx->regs[i]) { 739 if (!pmx->regs[i]) {
740 dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i); 740 dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
741 return -ENODEV; 741 return -ENODEV;
742 } 742 }
743 } 743 }
744 744
745 pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx); 745 pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
746 if (!pmx->pctl) { 746 if (!pmx->pctl) {
747 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 747 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
748 return -ENODEV; 748 return -ENODEV;
749 } 749 }
750 750
751 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range); 751 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
752 752
753 platform_set_drvdata(pdev, pmx); 753 platform_set_drvdata(pdev, pmx);
754 754
755 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n"); 755 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
756 756
757 return 0; 757 return 0;
758 } 758 }
759 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe); 759 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
760 760
761 int __devexit tegra_pinctrl_remove(struct platform_device *pdev) 761 int tegra_pinctrl_remove(struct platform_device *pdev)
762 { 762 {
763 struct tegra_pmx *pmx = platform_get_drvdata(pdev); 763 struct tegra_pmx *pmx = platform_get_drvdata(pdev);
764 764
765 pinctrl_unregister(pmx->pctl); 765 pinctrl_unregister(pmx->pctl);
766 766
767 return 0; 767 return 0;
768 } 768 }
769 EXPORT_SYMBOL_GPL(tegra_pinctrl_remove); 769 EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
770 770
drivers/pinctrl/pinctrl-u300.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Driver for the U300 pin controller 2 * Driver for the U300 pin controller
3 * 3 *
4 * Based on the original U300 padmux functions 4 * Based on the original U300 padmux functions
5 * Copyright (C) 2009-2011 ST-Ericsson AB 5 * Copyright (C) 2009-2011 ST-Ericsson AB
6 * Author: Martin Persson <martin.persson@stericsson.com> 6 * Author: Martin Persson <martin.persson@stericsson.com>
7 * Author: Linus Walleij <linus.walleij@linaro.org> 7 * Author: Linus Walleij <linus.walleij@linaro.org>
8 * 8 *
9 * The DB3350 design and control registers are oriented around pads rather than 9 * The DB3350 design and control registers are oriented around pads rather than
10 * pins, so we enumerate the pads we can mux rather than actual pins. The pads 10 * pins, so we enumerate the pads we can mux rather than actual pins. The pads
11 * are connected to different pins in different packaging types, so it would 11 * are connected to different pins in different packaging types, so it would
12 * be confusing. 12 * be confusing.
13 */ 13 */
14 #include <linux/init.h> 14 #include <linux/init.h>
15 #include <linux/module.h> 15 #include <linux/module.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include <linux/io.h> 17 #include <linux/io.h>
18 #include <linux/slab.h> 18 #include <linux/slab.h>
19 #include <linux/err.h> 19 #include <linux/err.h>
20 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h> 21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinconf-generic.h> 23 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-coh901.h" 24 #include "pinctrl-coh901.h"
25 25
26 /* 26 /*
27 * Register definitions for the U300 Padmux control registers in the 27 * Register definitions for the U300 Padmux control registers in the
28 * system controller 28 * system controller
29 */ 29 */
30 30
31 /* PAD MUX Control register 1 (LOW) 16bit (R/W) */ 31 /* PAD MUX Control register 1 (LOW) 16bit (R/W) */
32 #define U300_SYSCON_PMC1LR 0x007C 32 #define U300_SYSCON_PMC1LR 0x007C
33 #define U300_SYSCON_PMC1LR_MASK 0xFFFF 33 #define U300_SYSCON_PMC1LR_MASK 0xFFFF
34 #define U300_SYSCON_PMC1LR_CDI_MASK 0xC000 34 #define U300_SYSCON_PMC1LR_CDI_MASK 0xC000
35 #define U300_SYSCON_PMC1LR_CDI_CDI 0x0000 35 #define U300_SYSCON_PMC1LR_CDI_CDI 0x0000
36 #define U300_SYSCON_PMC1LR_CDI_EMIF 0x4000 36 #define U300_SYSCON_PMC1LR_CDI_EMIF 0x4000
37 /* For BS335 */ 37 /* For BS335 */
38 #define U300_SYSCON_PMC1LR_CDI_CDI2 0x8000 38 #define U300_SYSCON_PMC1LR_CDI_CDI2 0x8000
39 #define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO 0xC000 39 #define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO 0xC000
40 /* For BS365 */ 40 /* For BS365 */
41 #define U300_SYSCON_PMC1LR_CDI_GPIO 0x8000 41 #define U300_SYSCON_PMC1LR_CDI_GPIO 0x8000
42 #define U300_SYSCON_PMC1LR_CDI_WCDMA 0xC000 42 #define U300_SYSCON_PMC1LR_CDI_WCDMA 0xC000
43 /* Common defs */ 43 /* Common defs */
44 #define U300_SYSCON_PMC1LR_PDI_MASK 0x3000 44 #define U300_SYSCON_PMC1LR_PDI_MASK 0x3000
45 #define U300_SYSCON_PMC1LR_PDI_PDI 0x0000 45 #define U300_SYSCON_PMC1LR_PDI_PDI 0x0000
46 #define U300_SYSCON_PMC1LR_PDI_EGG 0x1000 46 #define U300_SYSCON_PMC1LR_PDI_EGG 0x1000
47 #define U300_SYSCON_PMC1LR_PDI_WCDMA 0x3000 47 #define U300_SYSCON_PMC1LR_PDI_WCDMA 0x3000
48 #define U300_SYSCON_PMC1LR_MMCSD_MASK 0x0C00 48 #define U300_SYSCON_PMC1LR_MMCSD_MASK 0x0C00
49 #define U300_SYSCON_PMC1LR_MMCSD_MMCSD 0x0000 49 #define U300_SYSCON_PMC1LR_MMCSD_MMCSD 0x0000
50 #define U300_SYSCON_PMC1LR_MMCSD_MSPRO 0x0400 50 #define U300_SYSCON_PMC1LR_MMCSD_MSPRO 0x0400
51 #define U300_SYSCON_PMC1LR_MMCSD_DSP 0x0800 51 #define U300_SYSCON_PMC1LR_MMCSD_DSP 0x0800
52 #define U300_SYSCON_PMC1LR_MMCSD_WCDMA 0x0C00 52 #define U300_SYSCON_PMC1LR_MMCSD_WCDMA 0x0C00
53 #define U300_SYSCON_PMC1LR_ETM_MASK 0x0300 53 #define U300_SYSCON_PMC1LR_ETM_MASK 0x0300
54 #define U300_SYSCON_PMC1LR_ETM_ACC 0x0000 54 #define U300_SYSCON_PMC1LR_ETM_ACC 0x0000
55 #define U300_SYSCON_PMC1LR_ETM_APP 0x0100 55 #define U300_SYSCON_PMC1LR_ETM_APP 0x0100
56 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK 0x00C0 56 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK 0x00C0
57 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC 0x0000 57 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC 0x0000
58 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF 0x0040 58 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF 0x0040
59 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM 0x0080 59 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM 0x0080
60 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB 0x00C0 60 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB 0x00C0
61 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK 0x0030 61 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK 0x0030
62 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC 0x0000 62 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC 0x0000
63 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF 0x0010 63 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF 0x0010
64 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM 0x0020 64 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM 0x0020
65 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI 0x0030 65 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI 0x0030
66 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK 0x000C 66 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK 0x000C
67 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC 0x0000 67 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC 0x0000
68 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF 0x0004 68 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF 0x0004
69 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM 0x0008 69 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM 0x0008
70 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI 0x000C 70 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI 0x000C
71 #define U300_SYSCON_PMC1LR_EMIF_1_MASK 0x0003 71 #define U300_SYSCON_PMC1LR_EMIF_1_MASK 0x0003
72 #define U300_SYSCON_PMC1LR_EMIF_1_STATIC 0x0000 72 #define U300_SYSCON_PMC1LR_EMIF_1_STATIC 0x0000
73 #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 0x0001 73 #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 0x0001
74 #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 0x0002 74 #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 0x0002
75 #define U300_SYSCON_PMC1LR_EMIF_1 0x0003 75 #define U300_SYSCON_PMC1LR_EMIF_1 0x0003
76 /* PAD MUX Control register 2 (HIGH) 16bit (R/W) */ 76 /* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
77 #define U300_SYSCON_PMC1HR 0x007E 77 #define U300_SYSCON_PMC1HR 0x007E
78 #define U300_SYSCON_PMC1HR_MASK 0xFFFF 78 #define U300_SYSCON_PMC1HR_MASK 0xFFFF
79 #define U300_SYSCON_PMC1HR_MISC_2_MASK 0xC000 79 #define U300_SYSCON_PMC1HR_MISC_2_MASK 0xC000
80 #define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO 0x0000 80 #define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO 0x0000
81 #define U300_SYSCON_PMC1HR_MISC_2_MSPRO 0x4000 81 #define U300_SYSCON_PMC1HR_MISC_2_MSPRO 0x4000
82 #define U300_SYSCON_PMC1HR_MISC_2_DSP 0x8000 82 #define U300_SYSCON_PMC1HR_MISC_2_DSP 0x8000
83 #define U300_SYSCON_PMC1HR_MISC_2_AAIF 0xC000 83 #define U300_SYSCON_PMC1HR_MISC_2_AAIF 0xC000
84 #define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK 0x3000 84 #define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK 0x3000
85 #define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO 0x0000 85 #define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO 0x0000
86 #define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF 0x1000 86 #define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF 0x1000
87 #define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP 0x2000 87 #define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP 0x2000
88 #define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF 0x3000 88 #define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF 0x3000
89 #define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK 0x0C00 89 #define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK 0x0C00
90 #define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO 0x0000 90 #define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO 0x0000
91 #define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC 0x0400 91 #define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC 0x0400
92 #define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP 0x0800 92 #define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP 0x0800
93 #define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF 0x0C00 93 #define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF 0x0C00
94 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK 0x0300 94 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK 0x0300
95 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO 0x0000 95 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO 0x0000
96 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI 0x0100 96 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI 0x0100
97 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF 0x0300 97 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF 0x0300
98 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK 0x00C0 98 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK 0x00C0
99 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO 0x0000 99 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO 0x0000
100 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI 0x0040 100 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI 0x0040
101 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF 0x00C0 101 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF 0x00C0
102 #define U300_SYSCON_PMC1HR_APP_SPI_2_MASK 0x0030 102 #define U300_SYSCON_PMC1HR_APP_SPI_2_MASK 0x0030
103 #define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO 0x0000 103 #define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO 0x0000
104 #define U300_SYSCON_PMC1HR_APP_SPI_2_SPI 0x0010 104 #define U300_SYSCON_PMC1HR_APP_SPI_2_SPI 0x0010
105 #define U300_SYSCON_PMC1HR_APP_SPI_2_DSP 0x0020 105 #define U300_SYSCON_PMC1HR_APP_SPI_2_DSP 0x0020
106 #define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF 0x0030 106 #define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF 0x0030
107 #define U300_SYSCON_PMC1HR_APP_UART0_2_MASK 0x000C 107 #define U300_SYSCON_PMC1HR_APP_UART0_2_MASK 0x000C
108 #define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO 0x0000 108 #define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO 0x0000
109 #define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 0x0004 109 #define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 0x0004
110 #define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS 0x0008 110 #define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS 0x0008
111 #define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF 0x000C 111 #define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF 0x000C
112 #define U300_SYSCON_PMC1HR_APP_UART0_1_MASK 0x0003 112 #define U300_SYSCON_PMC1HR_APP_UART0_1_MASK 0x0003
113 #define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO 0x0000 113 #define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO 0x0000
114 #define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 0x0001 114 #define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 0x0001
115 #define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF 0x0003 115 #define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF 0x0003
116 /* Padmux 2 control */ 116 /* Padmux 2 control */
117 #define U300_SYSCON_PMC2R 0x100 117 #define U300_SYSCON_PMC2R 0x100
118 #define U300_SYSCON_PMC2R_APP_MISC_0_MASK 0x00C0 118 #define U300_SYSCON_PMC2R_APP_MISC_0_MASK 0x00C0
119 #define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO 0x0000 119 #define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO 0x0000
120 #define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM 0x0040 120 #define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM 0x0040
121 #define U300_SYSCON_PMC2R_APP_MISC_0_MMC 0x0080 121 #define U300_SYSCON_PMC2R_APP_MISC_0_MMC 0x0080
122 #define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 0x00C0 122 #define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 0x00C0
123 #define U300_SYSCON_PMC2R_APP_MISC_1_MASK 0x0300 123 #define U300_SYSCON_PMC2R_APP_MISC_1_MASK 0x0300
124 #define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO 0x0000 124 #define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO 0x0000
125 #define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM 0x0100 125 #define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM 0x0100
126 #define U300_SYSCON_PMC2R_APP_MISC_1_MMC 0x0200 126 #define U300_SYSCON_PMC2R_APP_MISC_1_MMC 0x0200
127 #define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 0x0300 127 #define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 0x0300
128 #define U300_SYSCON_PMC2R_APP_MISC_2_MASK 0x0C00 128 #define U300_SYSCON_PMC2R_APP_MISC_2_MASK 0x0C00
129 #define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO 0x0000 129 #define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO 0x0000
130 #define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM 0x0400 130 #define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM 0x0400
131 #define U300_SYSCON_PMC2R_APP_MISC_2_MMC 0x0800 131 #define U300_SYSCON_PMC2R_APP_MISC_2_MMC 0x0800
132 #define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 0x0C00 132 #define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 0x0C00
133 #define U300_SYSCON_PMC2R_APP_MISC_3_MASK 0x3000 133 #define U300_SYSCON_PMC2R_APP_MISC_3_MASK 0x3000
134 #define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO 0x0000 134 #define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO 0x0000
135 #define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM 0x1000 135 #define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM 0x1000
136 #define U300_SYSCON_PMC2R_APP_MISC_3_MMC 0x2000 136 #define U300_SYSCON_PMC2R_APP_MISC_3_MMC 0x2000
137 #define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 0x3000 137 #define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 0x3000
138 #define U300_SYSCON_PMC2R_APP_MISC_4_MASK 0xC000 138 #define U300_SYSCON_PMC2R_APP_MISC_4_MASK 0xC000
139 #define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO 0x0000 139 #define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO 0x0000
140 #define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM 0x4000 140 #define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM 0x4000
141 #define U300_SYSCON_PMC2R_APP_MISC_4_MMC 0x8000 141 #define U300_SYSCON_PMC2R_APP_MISC_4_MMC 0x8000
142 #define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO 0xC000 142 #define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO 0xC000
143 /* TODO: More SYSCON registers missing */ 143 /* TODO: More SYSCON registers missing */
144 #define U300_SYSCON_PMC3R 0x10C 144 #define U300_SYSCON_PMC3R 0x10C
145 #define U300_SYSCON_PMC3R_APP_MISC_11_MASK 0xC000 145 #define U300_SYSCON_PMC3R_APP_MISC_11_MASK 0xC000
146 #define U300_SYSCON_PMC3R_APP_MISC_11_SPI 0x4000 146 #define U300_SYSCON_PMC3R_APP_MISC_11_SPI 0x4000
147 #define U300_SYSCON_PMC3R_APP_MISC_10_MASK 0x3000 147 #define U300_SYSCON_PMC3R_APP_MISC_10_MASK 0x3000
148 #define U300_SYSCON_PMC3R_APP_MISC_10_SPI 0x1000 148 #define U300_SYSCON_PMC3R_APP_MISC_10_SPI 0x1000
149 /* TODO: Missing other configs */ 149 /* TODO: Missing other configs */
150 #define U300_SYSCON_PMC4R 0x168 150 #define U300_SYSCON_PMC4R 0x168
151 #define U300_SYSCON_PMC4R_APP_MISC_12_MASK 0x0003 151 #define U300_SYSCON_PMC4R_APP_MISC_12_MASK 0x0003
152 #define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO 0x0000 152 #define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO 0x0000
153 #define U300_SYSCON_PMC4R_APP_MISC_13_MASK 0x000C 153 #define U300_SYSCON_PMC4R_APP_MISC_13_MASK 0x000C
154 #define U300_SYSCON_PMC4R_APP_MISC_13_CDI 0x0000 154 #define U300_SYSCON_PMC4R_APP_MISC_13_CDI 0x0000
155 #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA 0x0004 155 #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA 0x0004
156 #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 0x0008 156 #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 0x0008
157 #define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO 0x000C 157 #define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO 0x000C
158 #define U300_SYSCON_PMC4R_APP_MISC_14_MASK 0x0030 158 #define U300_SYSCON_PMC4R_APP_MISC_14_MASK 0x0030
159 #define U300_SYSCON_PMC4R_APP_MISC_14_CDI 0x0000 159 #define U300_SYSCON_PMC4R_APP_MISC_14_CDI 0x0000
160 #define U300_SYSCON_PMC4R_APP_MISC_14_SMIA 0x0010 160 #define U300_SYSCON_PMC4R_APP_MISC_14_SMIA 0x0010
161 #define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 0x0020 161 #define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 0x0020
162 #define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO 0x0030 162 #define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO 0x0030
163 #define U300_SYSCON_PMC4R_APP_MISC_16_MASK 0x0300 163 #define U300_SYSCON_PMC4R_APP_MISC_16_MASK 0x0300
164 #define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 0x0000 164 #define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 0x0000
165 #define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS 0x0100 165 #define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS 0x0100
166 #define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N 0x0200 166 #define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N 0x0200
167 167
168 #define DRIVER_NAME "pinctrl-u300" 168 #define DRIVER_NAME "pinctrl-u300"
169 169
170 /* 170 /*
171 * The DB3350 has 467 pads, I have enumerated the pads clockwise around the 171 * The DB3350 has 467 pads, I have enumerated the pads clockwise around the
172 * edges of the silicon, finger by finger. LTCORNER upper left is pad 0. 172 * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
173 * Data taken from the PadRing chart, arranged like this: 173 * Data taken from the PadRing chart, arranged like this:
174 * 174 *
175 * 0 ..... 104 175 * 0 ..... 104
176 * 466 105 176 * 466 105
177 * . . 177 * . .
178 * . . 178 * . .
179 * 358 224 179 * 358 224
180 * 357 .... 225 180 * 357 .... 225
181 */ 181 */
182 #define U300_NUM_PADS 467 182 #define U300_NUM_PADS 467
183 183
184 /* Pad names for the pinmux subsystem */ 184 /* Pad names for the pinmux subsystem */
185 static const struct pinctrl_pin_desc u300_pads[] = { 185 static const struct pinctrl_pin_desc u300_pads[] = {
186 /* Pads along the top edge of the chip */ 186 /* Pads along the top edge of the chip */
187 PINCTRL_PIN(0, "P PAD VDD 28"), 187 PINCTRL_PIN(0, "P PAD VDD 28"),
188 PINCTRL_PIN(1, "P PAD GND 28"), 188 PINCTRL_PIN(1, "P PAD GND 28"),
189 PINCTRL_PIN(2, "PO SIM RST N"), 189 PINCTRL_PIN(2, "PO SIM RST N"),
190 PINCTRL_PIN(3, "VSSIO 25"), 190 PINCTRL_PIN(3, "VSSIO 25"),
191 PINCTRL_PIN(4, "VSSA ADDA ESDSUB"), 191 PINCTRL_PIN(4, "VSSA ADDA ESDSUB"),
192 PINCTRL_PIN(5, "PWR VSSCOMMON"), 192 PINCTRL_PIN(5, "PWR VSSCOMMON"),
193 PINCTRL_PIN(6, "PI ADC I1 POS"), 193 PINCTRL_PIN(6, "PI ADC I1 POS"),
194 PINCTRL_PIN(7, "PI ADC I1 NEG"), 194 PINCTRL_PIN(7, "PI ADC I1 NEG"),
195 PINCTRL_PIN(8, "PWR VSSAD0"), 195 PINCTRL_PIN(8, "PWR VSSAD0"),
196 PINCTRL_PIN(9, "PWR VCCAD0"), 196 PINCTRL_PIN(9, "PWR VCCAD0"),
197 PINCTRL_PIN(10, "PI ADC Q1 NEG"), 197 PINCTRL_PIN(10, "PI ADC Q1 NEG"),
198 PINCTRL_PIN(11, "PI ADC Q1 POS"), 198 PINCTRL_PIN(11, "PI ADC Q1 POS"),
199 PINCTRL_PIN(12, "PWR VDDAD"), 199 PINCTRL_PIN(12, "PWR VDDAD"),
200 PINCTRL_PIN(13, "PWR GNDAD"), 200 PINCTRL_PIN(13, "PWR GNDAD"),
201 PINCTRL_PIN(14, "PI ADC I2 POS"), 201 PINCTRL_PIN(14, "PI ADC I2 POS"),
202 PINCTRL_PIN(15, "PI ADC I2 NEG"), 202 PINCTRL_PIN(15, "PI ADC I2 NEG"),
203 PINCTRL_PIN(16, "PWR VSSAD1"), 203 PINCTRL_PIN(16, "PWR VSSAD1"),
204 PINCTRL_PIN(17, "PWR VCCAD1"), 204 PINCTRL_PIN(17, "PWR VCCAD1"),
205 PINCTRL_PIN(18, "PI ADC Q2 NEG"), 205 PINCTRL_PIN(18, "PI ADC Q2 NEG"),
206 PINCTRL_PIN(19, "PI ADC Q2 POS"), 206 PINCTRL_PIN(19, "PI ADC Q2 POS"),
207 PINCTRL_PIN(20, "VSSA ADDA ESDSUB"), 207 PINCTRL_PIN(20, "VSSA ADDA ESDSUB"),
208 PINCTRL_PIN(21, "PWR VCCGPAD"), 208 PINCTRL_PIN(21, "PWR VCCGPAD"),
209 PINCTRL_PIN(22, "PI TX POW"), 209 PINCTRL_PIN(22, "PI TX POW"),
210 PINCTRL_PIN(23, "PWR VSSGPAD"), 210 PINCTRL_PIN(23, "PWR VSSGPAD"),
211 PINCTRL_PIN(24, "PO DAC I POS"), 211 PINCTRL_PIN(24, "PO DAC I POS"),
212 PINCTRL_PIN(25, "PO DAC I NEG"), 212 PINCTRL_PIN(25, "PO DAC I NEG"),
213 PINCTRL_PIN(26, "PO DAC Q POS"), 213 PINCTRL_PIN(26, "PO DAC Q POS"),
214 PINCTRL_PIN(27, "PO DAC Q NEG"), 214 PINCTRL_PIN(27, "PO DAC Q NEG"),
215 PINCTRL_PIN(28, "PWR VSSDA"), 215 PINCTRL_PIN(28, "PWR VSSDA"),
216 PINCTRL_PIN(29, "PWR VCCDA"), 216 PINCTRL_PIN(29, "PWR VCCDA"),
217 PINCTRL_PIN(30, "VSSA ADDA ESDSUB"), 217 PINCTRL_PIN(30, "VSSA ADDA ESDSUB"),
218 PINCTRL_PIN(31, "P PAD VDDIO 11"), 218 PINCTRL_PIN(31, "P PAD VDDIO 11"),
219 PINCTRL_PIN(32, "PI PLL 26 FILTVDD"), 219 PINCTRL_PIN(32, "PI PLL 26 FILTVDD"),
220 PINCTRL_PIN(33, "PI PLL 26 VCONT"), 220 PINCTRL_PIN(33, "PI PLL 26 VCONT"),
221 PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"), 221 PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"),
222 PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"), 222 PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"),
223 PINCTRL_PIN(36, "VDDA PLL ESD"), 223 PINCTRL_PIN(36, "VDDA PLL ESD"),
224 PINCTRL_PIN(37, "VSSA PLL ESD"), 224 PINCTRL_PIN(37, "VSSA PLL ESD"),
225 PINCTRL_PIN(38, "VSS PLL"), 225 PINCTRL_PIN(38, "VSS PLL"),
226 PINCTRL_PIN(39, "VDDC PLL"), 226 PINCTRL_PIN(39, "VDDC PLL"),
227 PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"), 227 PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"),
228 PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"), 228 PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"),
229 PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"), 229 PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"),
230 PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"), 230 PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"),
231 PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"), 231 PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"),
232 PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"), 232 PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"),
233 PINCTRL_PIN(46, "P PAD VSSIO 11"), 233 PINCTRL_PIN(46, "P PAD VSSIO 11"),
234 PINCTRL_PIN(47, "P PAD VSSIO 12"), 234 PINCTRL_PIN(47, "P PAD VSSIO 12"),
235 PINCTRL_PIN(48, "PI POW RST N"), 235 PINCTRL_PIN(48, "PI POW RST N"),
236 PINCTRL_PIN(49, "VDDC IO"), 236 PINCTRL_PIN(49, "VDDC IO"),
237 PINCTRL_PIN(50, "P PAD VDDIO 16"), 237 PINCTRL_PIN(50, "P PAD VDDIO 16"),
238 PINCTRL_PIN(51, "PO RF WCDMA EN 4"), 238 PINCTRL_PIN(51, "PO RF WCDMA EN 4"),
239 PINCTRL_PIN(52, "PO RF WCDMA EN 3"), 239 PINCTRL_PIN(52, "PO RF WCDMA EN 3"),
240 PINCTRL_PIN(53, "PO RF WCDMA EN 2"), 240 PINCTRL_PIN(53, "PO RF WCDMA EN 2"),
241 PINCTRL_PIN(54, "PO RF WCDMA EN 1"), 241 PINCTRL_PIN(54, "PO RF WCDMA EN 1"),
242 PINCTRL_PIN(55, "PO RF WCDMA EN 0"), 242 PINCTRL_PIN(55, "PO RF WCDMA EN 0"),
243 PINCTRL_PIN(56, "PO GSM PA ENABLE"), 243 PINCTRL_PIN(56, "PO GSM PA ENABLE"),
244 PINCTRL_PIN(57, "PO RF DATA STRB"), 244 PINCTRL_PIN(57, "PO RF DATA STRB"),
245 PINCTRL_PIN(58, "PO RF DATA2"), 245 PINCTRL_PIN(58, "PO RF DATA2"),
246 PINCTRL_PIN(59, "PIO RF DATA1"), 246 PINCTRL_PIN(59, "PIO RF DATA1"),
247 PINCTRL_PIN(60, "PIO RF DATA0"), 247 PINCTRL_PIN(60, "PIO RF DATA0"),
248 PINCTRL_PIN(61, "P PAD VDD 11"), 248 PINCTRL_PIN(61, "P PAD VDD 11"),
249 PINCTRL_PIN(62, "P PAD GND 11"), 249 PINCTRL_PIN(62, "P PAD GND 11"),
250 PINCTRL_PIN(63, "P PAD VSSIO 16"), 250 PINCTRL_PIN(63, "P PAD VSSIO 16"),
251 PINCTRL_PIN(64, "P PAD VDDIO 18"), 251 PINCTRL_PIN(64, "P PAD VDDIO 18"),
252 PINCTRL_PIN(65, "PO RF CTRL STRB2"), 252 PINCTRL_PIN(65, "PO RF CTRL STRB2"),
253 PINCTRL_PIN(66, "PO RF CTRL STRB1"), 253 PINCTRL_PIN(66, "PO RF CTRL STRB1"),
254 PINCTRL_PIN(67, "PO RF CTRL STRB0"), 254 PINCTRL_PIN(67, "PO RF CTRL STRB0"),
255 PINCTRL_PIN(68, "PIO RF CTRL DATA"), 255 PINCTRL_PIN(68, "PIO RF CTRL DATA"),
256 PINCTRL_PIN(69, "PO RF CTRL CLK"), 256 PINCTRL_PIN(69, "PO RF CTRL CLK"),
257 PINCTRL_PIN(70, "PO TX ADC STRB"), 257 PINCTRL_PIN(70, "PO TX ADC STRB"),
258 PINCTRL_PIN(71, "PO ANT SW 2"), 258 PINCTRL_PIN(71, "PO ANT SW 2"),
259 PINCTRL_PIN(72, "PO ANT SW 3"), 259 PINCTRL_PIN(72, "PO ANT SW 3"),
260 PINCTRL_PIN(73, "PO ANT SW 0"), 260 PINCTRL_PIN(73, "PO ANT SW 0"),
261 PINCTRL_PIN(74, "PO ANT SW 1"), 261 PINCTRL_PIN(74, "PO ANT SW 1"),
262 PINCTRL_PIN(75, "PO M CLKRQ"), 262 PINCTRL_PIN(75, "PO M CLKRQ"),
263 PINCTRL_PIN(76, "PI M CLK"), 263 PINCTRL_PIN(76, "PI M CLK"),
264 PINCTRL_PIN(77, "PI RTC CLK"), 264 PINCTRL_PIN(77, "PI RTC CLK"),
265 PINCTRL_PIN(78, "P PAD VDD 8"), 265 PINCTRL_PIN(78, "P PAD VDD 8"),
266 PINCTRL_PIN(79, "P PAD GND 8"), 266 PINCTRL_PIN(79, "P PAD GND 8"),
267 PINCTRL_PIN(80, "P PAD VSSIO 13"), 267 PINCTRL_PIN(80, "P PAD VSSIO 13"),
268 PINCTRL_PIN(81, "P PAD VDDIO 13"), 268 PINCTRL_PIN(81, "P PAD VDDIO 13"),
269 PINCTRL_PIN(82, "PO SYS 1 CLK"), 269 PINCTRL_PIN(82, "PO SYS 1 CLK"),
270 PINCTRL_PIN(83, "PO SYS 2 CLK"), 270 PINCTRL_PIN(83, "PO SYS 2 CLK"),
271 PINCTRL_PIN(84, "PO SYS 0 CLK"), 271 PINCTRL_PIN(84, "PO SYS 0 CLK"),
272 PINCTRL_PIN(85, "PI SYS 0 CLKRQ"), 272 PINCTRL_PIN(85, "PI SYS 0 CLKRQ"),
273 PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"), 273 PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"),
274 PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"), 274 PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"),
275 PINCTRL_PIN(88, "PO RESOUT2 RST N"), 275 PINCTRL_PIN(88, "PO RESOUT2 RST N"),
276 PINCTRL_PIN(89, "PO RESOUT1 RST N"), 276 PINCTRL_PIN(89, "PO RESOUT1 RST N"),
277 PINCTRL_PIN(90, "PO RESOUT0 RST N"), 277 PINCTRL_PIN(90, "PO RESOUT0 RST N"),
278 PINCTRL_PIN(91, "PI SERVICE N"), 278 PINCTRL_PIN(91, "PI SERVICE N"),
279 PINCTRL_PIN(92, "P PAD VDD 29"), 279 PINCTRL_PIN(92, "P PAD VDD 29"),
280 PINCTRL_PIN(93, "P PAD GND 29"), 280 PINCTRL_PIN(93, "P PAD GND 29"),
281 PINCTRL_PIN(94, "P PAD VSSIO 8"), 281 PINCTRL_PIN(94, "P PAD VSSIO 8"),
282 PINCTRL_PIN(95, "P PAD VDDIO 8"), 282 PINCTRL_PIN(95, "P PAD VDDIO 8"),
283 PINCTRL_PIN(96, "PI EXT IRQ1 N"), 283 PINCTRL_PIN(96, "PI EXT IRQ1 N"),
284 PINCTRL_PIN(97, "PI EXT IRQ0 N"), 284 PINCTRL_PIN(97, "PI EXT IRQ0 N"),
285 PINCTRL_PIN(98, "PIO DC ON"), 285 PINCTRL_PIN(98, "PIO DC ON"),
286 PINCTRL_PIN(99, "PIO ACC APP I2C DATA"), 286 PINCTRL_PIN(99, "PIO ACC APP I2C DATA"),
287 PINCTRL_PIN(100, "PIO ACC APP I2C CLK"), 287 PINCTRL_PIN(100, "PIO ACC APP I2C CLK"),
288 PINCTRL_PIN(101, "P PAD VDD 12"), 288 PINCTRL_PIN(101, "P PAD VDD 12"),
289 PINCTRL_PIN(102, "P PAD GND 12"), 289 PINCTRL_PIN(102, "P PAD GND 12"),
290 PINCTRL_PIN(103, "P PAD VSSIO 14"), 290 PINCTRL_PIN(103, "P PAD VSSIO 14"),
291 PINCTRL_PIN(104, "P PAD VDDIO 14"), 291 PINCTRL_PIN(104, "P PAD VDDIO 14"),
292 /* Pads along the right edge of the chip */ 292 /* Pads along the right edge of the chip */
293 PINCTRL_PIN(105, "PIO APP I2C1 DATA"), 293 PINCTRL_PIN(105, "PIO APP I2C1 DATA"),
294 PINCTRL_PIN(106, "PIO APP I2C1 CLK"), 294 PINCTRL_PIN(106, "PIO APP I2C1 CLK"),
295 PINCTRL_PIN(107, "PO KEY OUT0"), 295 PINCTRL_PIN(107, "PO KEY OUT0"),
296 PINCTRL_PIN(108, "PO KEY OUT1"), 296 PINCTRL_PIN(108, "PO KEY OUT1"),
297 PINCTRL_PIN(109, "PO KEY OUT2"), 297 PINCTRL_PIN(109, "PO KEY OUT2"),
298 PINCTRL_PIN(110, "PO KEY OUT3"), 298 PINCTRL_PIN(110, "PO KEY OUT3"),
299 PINCTRL_PIN(111, "PO KEY OUT4"), 299 PINCTRL_PIN(111, "PO KEY OUT4"),
300 PINCTRL_PIN(112, "PI KEY IN0"), 300 PINCTRL_PIN(112, "PI KEY IN0"),
301 PINCTRL_PIN(113, "PI KEY IN1"), 301 PINCTRL_PIN(113, "PI KEY IN1"),
302 PINCTRL_PIN(114, "PI KEY IN2"), 302 PINCTRL_PIN(114, "PI KEY IN2"),
303 PINCTRL_PIN(115, "P PAD VDDIO 15"), 303 PINCTRL_PIN(115, "P PAD VDDIO 15"),
304 PINCTRL_PIN(116, "P PAD VSSIO 15"), 304 PINCTRL_PIN(116, "P PAD VSSIO 15"),
305 PINCTRL_PIN(117, "P PAD GND 13"), 305 PINCTRL_PIN(117, "P PAD GND 13"),
306 PINCTRL_PIN(118, "P PAD VDD 13"), 306 PINCTRL_PIN(118, "P PAD VDD 13"),
307 PINCTRL_PIN(119, "PI KEY IN3"), 307 PINCTRL_PIN(119, "PI KEY IN3"),
308 PINCTRL_PIN(120, "PI KEY IN4"), 308 PINCTRL_PIN(120, "PI KEY IN4"),
309 PINCTRL_PIN(121, "PI KEY IN5"), 309 PINCTRL_PIN(121, "PI KEY IN5"),
310 PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"), 310 PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"),
311 PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"), 311 PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"),
312 PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"), 312 PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"),
313 PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"), 313 PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"),
314 PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"), 314 PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"),
315 PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"), 315 PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"),
316 PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"), 316 PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"),
317 PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"), 317 PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"),
318 PINCTRL_PIN(130, "P PAD VDD 17"), 318 PINCTRL_PIN(130, "P PAD VDD 17"),
319 PINCTRL_PIN(131, "P PAD GND 17"), 319 PINCTRL_PIN(131, "P PAD GND 17"),
320 PINCTRL_PIN(132, "P PAD VSSIO 19"), 320 PINCTRL_PIN(132, "P PAD VSSIO 19"),
321 PINCTRL_PIN(133, "P PAD VDDIO 19"), 321 PINCTRL_PIN(133, "P PAD VDDIO 19"),
322 PINCTRL_PIN(134, "UART0 RTS"), 322 PINCTRL_PIN(134, "UART0 RTS"),
323 PINCTRL_PIN(135, "UART0 CTS"), 323 PINCTRL_PIN(135, "UART0 CTS"),
324 PINCTRL_PIN(136, "UART0 TX"), 324 PINCTRL_PIN(136, "UART0 TX"),
325 PINCTRL_PIN(137, "UART0 RX"), 325 PINCTRL_PIN(137, "UART0 RX"),
326 PINCTRL_PIN(138, "PIO ACC SPI DO"), 326 PINCTRL_PIN(138, "PIO ACC SPI DO"),
327 PINCTRL_PIN(139, "PIO ACC SPI DI"), 327 PINCTRL_PIN(139, "PIO ACC SPI DI"),
328 PINCTRL_PIN(140, "PIO ACC SPI CS0 N"), 328 PINCTRL_PIN(140, "PIO ACC SPI CS0 N"),
329 PINCTRL_PIN(141, "PIO ACC SPI CS1 N"), 329 PINCTRL_PIN(141, "PIO ACC SPI CS1 N"),
330 PINCTRL_PIN(142, "PIO ACC SPI CS2 N"), 330 PINCTRL_PIN(142, "PIO ACC SPI CS2 N"),
331 PINCTRL_PIN(143, "PIO ACC SPI CLK"), 331 PINCTRL_PIN(143, "PIO ACC SPI CLK"),
332 PINCTRL_PIN(144, "PO PDI EXT RST N"), 332 PINCTRL_PIN(144, "PO PDI EXT RST N"),
333 PINCTRL_PIN(145, "P PAD VDDIO 22"), 333 PINCTRL_PIN(145, "P PAD VDDIO 22"),
334 PINCTRL_PIN(146, "P PAD VSSIO 22"), 334 PINCTRL_PIN(146, "P PAD VSSIO 22"),
335 PINCTRL_PIN(147, "P PAD GND 18"), 335 PINCTRL_PIN(147, "P PAD GND 18"),
336 PINCTRL_PIN(148, "P PAD VDD 18"), 336 PINCTRL_PIN(148, "P PAD VDD 18"),
337 PINCTRL_PIN(149, "PIO PDI C0"), 337 PINCTRL_PIN(149, "PIO PDI C0"),
338 PINCTRL_PIN(150, "PIO PDI C1"), 338 PINCTRL_PIN(150, "PIO PDI C1"),
339 PINCTRL_PIN(151, "PIO PDI C2"), 339 PINCTRL_PIN(151, "PIO PDI C2"),
340 PINCTRL_PIN(152, "PIO PDI C3"), 340 PINCTRL_PIN(152, "PIO PDI C3"),
341 PINCTRL_PIN(153, "PIO PDI C4"), 341 PINCTRL_PIN(153, "PIO PDI C4"),
342 PINCTRL_PIN(154, "PIO PDI C5"), 342 PINCTRL_PIN(154, "PIO PDI C5"),
343 PINCTRL_PIN(155, "PIO PDI D0"), 343 PINCTRL_PIN(155, "PIO PDI D0"),
344 PINCTRL_PIN(156, "PIO PDI D1"), 344 PINCTRL_PIN(156, "PIO PDI D1"),
345 PINCTRL_PIN(157, "PIO PDI D2"), 345 PINCTRL_PIN(157, "PIO PDI D2"),
346 PINCTRL_PIN(158, "PIO PDI D3"), 346 PINCTRL_PIN(158, "PIO PDI D3"),
347 PINCTRL_PIN(159, "P PAD VDDIO 21"), 347 PINCTRL_PIN(159, "P PAD VDDIO 21"),
348 PINCTRL_PIN(160, "P PAD VSSIO 21"), 348 PINCTRL_PIN(160, "P PAD VSSIO 21"),
349 PINCTRL_PIN(161, "PIO PDI D4"), 349 PINCTRL_PIN(161, "PIO PDI D4"),
350 PINCTRL_PIN(162, "PIO PDI D5"), 350 PINCTRL_PIN(162, "PIO PDI D5"),
351 PINCTRL_PIN(163, "PIO PDI D6"), 351 PINCTRL_PIN(163, "PIO PDI D6"),
352 PINCTRL_PIN(164, "PIO PDI D7"), 352 PINCTRL_PIN(164, "PIO PDI D7"),
353 PINCTRL_PIN(165, "PIO MS INS"), 353 PINCTRL_PIN(165, "PIO MS INS"),
354 PINCTRL_PIN(166, "MMC DATA DIR LS"), 354 PINCTRL_PIN(166, "MMC DATA DIR LS"),
355 PINCTRL_PIN(167, "MMC DATA 3"), 355 PINCTRL_PIN(167, "MMC DATA 3"),
356 PINCTRL_PIN(168, "MMC DATA 2"), 356 PINCTRL_PIN(168, "MMC DATA 2"),
357 PINCTRL_PIN(169, "MMC DATA 1"), 357 PINCTRL_PIN(169, "MMC DATA 1"),
358 PINCTRL_PIN(170, "MMC DATA 0"), 358 PINCTRL_PIN(170, "MMC DATA 0"),
359 PINCTRL_PIN(171, "MMC CMD DIR LS"), 359 PINCTRL_PIN(171, "MMC CMD DIR LS"),
360 PINCTRL_PIN(172, "P PAD VDD 27"), 360 PINCTRL_PIN(172, "P PAD VDD 27"),
361 PINCTRL_PIN(173, "P PAD GND 27"), 361 PINCTRL_PIN(173, "P PAD GND 27"),
362 PINCTRL_PIN(174, "P PAD VSSIO 20"), 362 PINCTRL_PIN(174, "P PAD VSSIO 20"),
363 PINCTRL_PIN(175, "P PAD VDDIO 20"), 363 PINCTRL_PIN(175, "P PAD VDDIO 20"),
364 PINCTRL_PIN(176, "MMC CMD"), 364 PINCTRL_PIN(176, "MMC CMD"),
365 PINCTRL_PIN(177, "MMC CLK"), 365 PINCTRL_PIN(177, "MMC CLK"),
366 PINCTRL_PIN(178, "PIO APP GPIO 14"), 366 PINCTRL_PIN(178, "PIO APP GPIO 14"),
367 PINCTRL_PIN(179, "PIO APP GPIO 13"), 367 PINCTRL_PIN(179, "PIO APP GPIO 13"),
368 PINCTRL_PIN(180, "PIO APP GPIO 11"), 368 PINCTRL_PIN(180, "PIO APP GPIO 11"),
369 PINCTRL_PIN(181, "PIO APP GPIO 25"), 369 PINCTRL_PIN(181, "PIO APP GPIO 25"),
370 PINCTRL_PIN(182, "PIO APP GPIO 24"), 370 PINCTRL_PIN(182, "PIO APP GPIO 24"),
371 PINCTRL_PIN(183, "PIO APP GPIO 23"), 371 PINCTRL_PIN(183, "PIO APP GPIO 23"),
372 PINCTRL_PIN(184, "PIO APP GPIO 22"), 372 PINCTRL_PIN(184, "PIO APP GPIO 22"),
373 PINCTRL_PIN(185, "PIO APP GPIO 21"), 373 PINCTRL_PIN(185, "PIO APP GPIO 21"),
374 PINCTRL_PIN(186, "PIO APP GPIO 20"), 374 PINCTRL_PIN(186, "PIO APP GPIO 20"),
375 PINCTRL_PIN(187, "P PAD VDD 19"), 375 PINCTRL_PIN(187, "P PAD VDD 19"),
376 PINCTRL_PIN(188, "P PAD GND 19"), 376 PINCTRL_PIN(188, "P PAD GND 19"),
377 PINCTRL_PIN(189, "P PAD VSSIO 23"), 377 PINCTRL_PIN(189, "P PAD VSSIO 23"),
378 PINCTRL_PIN(190, "P PAD VDDIO 23"), 378 PINCTRL_PIN(190, "P PAD VDDIO 23"),
379 PINCTRL_PIN(191, "PIO APP GPIO 19"), 379 PINCTRL_PIN(191, "PIO APP GPIO 19"),
380 PINCTRL_PIN(192, "PIO APP GPIO 18"), 380 PINCTRL_PIN(192, "PIO APP GPIO 18"),
381 PINCTRL_PIN(193, "PIO APP GPIO 17"), 381 PINCTRL_PIN(193, "PIO APP GPIO 17"),
382 PINCTRL_PIN(194, "PIO APP GPIO 16"), 382 PINCTRL_PIN(194, "PIO APP GPIO 16"),
383 PINCTRL_PIN(195, "PI CI D1"), 383 PINCTRL_PIN(195, "PI CI D1"),
384 PINCTRL_PIN(196, "PI CI D0"), 384 PINCTRL_PIN(196, "PI CI D0"),
385 PINCTRL_PIN(197, "PI CI HSYNC"), 385 PINCTRL_PIN(197, "PI CI HSYNC"),
386 PINCTRL_PIN(198, "PI CI VSYNC"), 386 PINCTRL_PIN(198, "PI CI VSYNC"),
387 PINCTRL_PIN(199, "PI CI EXT CLK"), 387 PINCTRL_PIN(199, "PI CI EXT CLK"),
388 PINCTRL_PIN(200, "PO CI EXT RST N"), 388 PINCTRL_PIN(200, "PO CI EXT RST N"),
389 PINCTRL_PIN(201, "P PAD VSSIO 43"), 389 PINCTRL_PIN(201, "P PAD VSSIO 43"),
390 PINCTRL_PIN(202, "P PAD VDDIO 43"), 390 PINCTRL_PIN(202, "P PAD VDDIO 43"),
391 PINCTRL_PIN(203, "PI CI D6"), 391 PINCTRL_PIN(203, "PI CI D6"),
392 PINCTRL_PIN(204, "PI CI D7"), 392 PINCTRL_PIN(204, "PI CI D7"),
393 PINCTRL_PIN(205, "PI CI D2"), 393 PINCTRL_PIN(205, "PI CI D2"),
394 PINCTRL_PIN(206, "PI CI D3"), 394 PINCTRL_PIN(206, "PI CI D3"),
395 PINCTRL_PIN(207, "PI CI D4"), 395 PINCTRL_PIN(207, "PI CI D4"),
396 PINCTRL_PIN(208, "PI CI D5"), 396 PINCTRL_PIN(208, "PI CI D5"),
397 PINCTRL_PIN(209, "PI CI D8"), 397 PINCTRL_PIN(209, "PI CI D8"),
398 PINCTRL_PIN(210, "PI CI D9"), 398 PINCTRL_PIN(210, "PI CI D9"),
399 PINCTRL_PIN(211, "P PAD VDD 20"), 399 PINCTRL_PIN(211, "P PAD VDD 20"),
400 PINCTRL_PIN(212, "P PAD GND 20"), 400 PINCTRL_PIN(212, "P PAD GND 20"),
401 PINCTRL_PIN(213, "P PAD VSSIO 24"), 401 PINCTRL_PIN(213, "P PAD VSSIO 24"),
402 PINCTRL_PIN(214, "P PAD VDDIO 24"), 402 PINCTRL_PIN(214, "P PAD VDDIO 24"),
403 PINCTRL_PIN(215, "P PAD VDDIO 26"), 403 PINCTRL_PIN(215, "P PAD VDDIO 26"),
404 PINCTRL_PIN(216, "PO EMIF 1 A26"), 404 PINCTRL_PIN(216, "PO EMIF 1 A26"),
405 PINCTRL_PIN(217, "PO EMIF 1 A25"), 405 PINCTRL_PIN(217, "PO EMIF 1 A25"),
406 PINCTRL_PIN(218, "P PAD VSSIO 26"), 406 PINCTRL_PIN(218, "P PAD VSSIO 26"),
407 PINCTRL_PIN(219, "PO EMIF 1 A24"), 407 PINCTRL_PIN(219, "PO EMIF 1 A24"),
408 PINCTRL_PIN(220, "PO EMIF 1 A23"), 408 PINCTRL_PIN(220, "PO EMIF 1 A23"),
409 /* Pads along the bottom edge of the chip */ 409 /* Pads along the bottom edge of the chip */
410 PINCTRL_PIN(221, "PO EMIF 1 A22"), 410 PINCTRL_PIN(221, "PO EMIF 1 A22"),
411 PINCTRL_PIN(222, "PO EMIF 1 A21"), 411 PINCTRL_PIN(222, "PO EMIF 1 A21"),
412 PINCTRL_PIN(223, "P PAD VDD 21"), 412 PINCTRL_PIN(223, "P PAD VDD 21"),
413 PINCTRL_PIN(224, "P PAD GND 21"), 413 PINCTRL_PIN(224, "P PAD GND 21"),
414 PINCTRL_PIN(225, "P PAD VSSIO 27"), 414 PINCTRL_PIN(225, "P PAD VSSIO 27"),
415 PINCTRL_PIN(226, "P PAD VDDIO 27"), 415 PINCTRL_PIN(226, "P PAD VDDIO 27"),
416 PINCTRL_PIN(227, "PO EMIF 1 A20"), 416 PINCTRL_PIN(227, "PO EMIF 1 A20"),
417 PINCTRL_PIN(228, "PO EMIF 1 A19"), 417 PINCTRL_PIN(228, "PO EMIF 1 A19"),
418 PINCTRL_PIN(229, "PO EMIF 1 A18"), 418 PINCTRL_PIN(229, "PO EMIF 1 A18"),
419 PINCTRL_PIN(230, "PO EMIF 1 A17"), 419 PINCTRL_PIN(230, "PO EMIF 1 A17"),
420 PINCTRL_PIN(231, "P PAD VDDIO 28"), 420 PINCTRL_PIN(231, "P PAD VDDIO 28"),
421 PINCTRL_PIN(232, "P PAD VSSIO 28"), 421 PINCTRL_PIN(232, "P PAD VSSIO 28"),
422 PINCTRL_PIN(233, "PO EMIF 1 A16"), 422 PINCTRL_PIN(233, "PO EMIF 1 A16"),
423 PINCTRL_PIN(234, "PIO EMIF 1 D15"), 423 PINCTRL_PIN(234, "PIO EMIF 1 D15"),
424 PINCTRL_PIN(235, "PO EMIF 1 A15"), 424 PINCTRL_PIN(235, "PO EMIF 1 A15"),
425 PINCTRL_PIN(236, "PIO EMIF 1 D14"), 425 PINCTRL_PIN(236, "PIO EMIF 1 D14"),
426 PINCTRL_PIN(237, "P PAD VDD 22"), 426 PINCTRL_PIN(237, "P PAD VDD 22"),
427 PINCTRL_PIN(238, "P PAD GND 22"), 427 PINCTRL_PIN(238, "P PAD GND 22"),
428 PINCTRL_PIN(239, "P PAD VSSIO 29"), 428 PINCTRL_PIN(239, "P PAD VSSIO 29"),
429 PINCTRL_PIN(240, "P PAD VDDIO 29"), 429 PINCTRL_PIN(240, "P PAD VDDIO 29"),
430 PINCTRL_PIN(241, "PO EMIF 1 A14"), 430 PINCTRL_PIN(241, "PO EMIF 1 A14"),
431 PINCTRL_PIN(242, "PIO EMIF 1 D13"), 431 PINCTRL_PIN(242, "PIO EMIF 1 D13"),
432 PINCTRL_PIN(243, "PO EMIF 1 A13"), 432 PINCTRL_PIN(243, "PO EMIF 1 A13"),
433 PINCTRL_PIN(244, "PIO EMIF 1 D12"), 433 PINCTRL_PIN(244, "PIO EMIF 1 D12"),
434 PINCTRL_PIN(245, "P PAD VSSIO 30"), 434 PINCTRL_PIN(245, "P PAD VSSIO 30"),
435 PINCTRL_PIN(246, "P PAD VDDIO 30"), 435 PINCTRL_PIN(246, "P PAD VDDIO 30"),
436 PINCTRL_PIN(247, "PO EMIF 1 A12"), 436 PINCTRL_PIN(247, "PO EMIF 1 A12"),
437 PINCTRL_PIN(248, "PIO EMIF 1 D11"), 437 PINCTRL_PIN(248, "PIO EMIF 1 D11"),
438 PINCTRL_PIN(249, "PO EMIF 1 A11"), 438 PINCTRL_PIN(249, "PO EMIF 1 A11"),
439 PINCTRL_PIN(250, "PIO EMIF 1 D10"), 439 PINCTRL_PIN(250, "PIO EMIF 1 D10"),
440 PINCTRL_PIN(251, "P PAD VSSIO 31"), 440 PINCTRL_PIN(251, "P PAD VSSIO 31"),
441 PINCTRL_PIN(252, "P PAD VDDIO 31"), 441 PINCTRL_PIN(252, "P PAD VDDIO 31"),
442 PINCTRL_PIN(253, "PO EMIF 1 A10"), 442 PINCTRL_PIN(253, "PO EMIF 1 A10"),
443 PINCTRL_PIN(254, "PIO EMIF 1 D09"), 443 PINCTRL_PIN(254, "PIO EMIF 1 D09"),
444 PINCTRL_PIN(255, "PO EMIF 1 A09"), 444 PINCTRL_PIN(255, "PO EMIF 1 A09"),
445 PINCTRL_PIN(256, "P PAD VDDIO 32"), 445 PINCTRL_PIN(256, "P PAD VDDIO 32"),
446 PINCTRL_PIN(257, "P PAD VSSIO 32"), 446 PINCTRL_PIN(257, "P PAD VSSIO 32"),
447 PINCTRL_PIN(258, "P PAD GND 24"), 447 PINCTRL_PIN(258, "P PAD GND 24"),
448 PINCTRL_PIN(259, "P PAD VDD 24"), 448 PINCTRL_PIN(259, "P PAD VDD 24"),
449 PINCTRL_PIN(260, "PIO EMIF 1 D08"), 449 PINCTRL_PIN(260, "PIO EMIF 1 D08"),
450 PINCTRL_PIN(261, "PO EMIF 1 A08"), 450 PINCTRL_PIN(261, "PO EMIF 1 A08"),
451 PINCTRL_PIN(262, "PIO EMIF 1 D07"), 451 PINCTRL_PIN(262, "PIO EMIF 1 D07"),
452 PINCTRL_PIN(263, "PO EMIF 1 A07"), 452 PINCTRL_PIN(263, "PO EMIF 1 A07"),
453 PINCTRL_PIN(264, "P PAD VDDIO 33"), 453 PINCTRL_PIN(264, "P PAD VDDIO 33"),
454 PINCTRL_PIN(265, "P PAD VSSIO 33"), 454 PINCTRL_PIN(265, "P PAD VSSIO 33"),
455 PINCTRL_PIN(266, "PIO EMIF 1 D06"), 455 PINCTRL_PIN(266, "PIO EMIF 1 D06"),
456 PINCTRL_PIN(267, "PO EMIF 1 A06"), 456 PINCTRL_PIN(267, "PO EMIF 1 A06"),
457 PINCTRL_PIN(268, "PIO EMIF 1 D05"), 457 PINCTRL_PIN(268, "PIO EMIF 1 D05"),
458 PINCTRL_PIN(269, "PO EMIF 1 A05"), 458 PINCTRL_PIN(269, "PO EMIF 1 A05"),
459 PINCTRL_PIN(270, "P PAD VDDIO 34"), 459 PINCTRL_PIN(270, "P PAD VDDIO 34"),
460 PINCTRL_PIN(271, "P PAD VSSIO 34"), 460 PINCTRL_PIN(271, "P PAD VSSIO 34"),
461 PINCTRL_PIN(272, "PIO EMIF 1 D04"), 461 PINCTRL_PIN(272, "PIO EMIF 1 D04"),
462 PINCTRL_PIN(273, "PO EMIF 1 A04"), 462 PINCTRL_PIN(273, "PO EMIF 1 A04"),
463 PINCTRL_PIN(274, "PIO EMIF 1 D03"), 463 PINCTRL_PIN(274, "PIO EMIF 1 D03"),
464 PINCTRL_PIN(275, "PO EMIF 1 A03"), 464 PINCTRL_PIN(275, "PO EMIF 1 A03"),
465 PINCTRL_PIN(276, "P PAD VDDIO 35"), 465 PINCTRL_PIN(276, "P PAD VDDIO 35"),
466 PINCTRL_PIN(277, "P PAD VSSIO 35"), 466 PINCTRL_PIN(277, "P PAD VSSIO 35"),
467 PINCTRL_PIN(278, "P PAD GND 23"), 467 PINCTRL_PIN(278, "P PAD GND 23"),
468 PINCTRL_PIN(279, "P PAD VDD 23"), 468 PINCTRL_PIN(279, "P PAD VDD 23"),
469 PINCTRL_PIN(280, "PIO EMIF 1 D02"), 469 PINCTRL_PIN(280, "PIO EMIF 1 D02"),
470 PINCTRL_PIN(281, "PO EMIF 1 A02"), 470 PINCTRL_PIN(281, "PO EMIF 1 A02"),
471 PINCTRL_PIN(282, "PIO EMIF 1 D01"), 471 PINCTRL_PIN(282, "PIO EMIF 1 D01"),
472 PINCTRL_PIN(283, "PO EMIF 1 A01"), 472 PINCTRL_PIN(283, "PO EMIF 1 A01"),
473 PINCTRL_PIN(284, "P PAD VDDIO 36"), 473 PINCTRL_PIN(284, "P PAD VDDIO 36"),
474 PINCTRL_PIN(285, "P PAD VSSIO 36"), 474 PINCTRL_PIN(285, "P PAD VSSIO 36"),
475 PINCTRL_PIN(286, "PIO EMIF 1 D00"), 475 PINCTRL_PIN(286, "PIO EMIF 1 D00"),
476 PINCTRL_PIN(287, "PO EMIF 1 BE1 N"), 476 PINCTRL_PIN(287, "PO EMIF 1 BE1 N"),
477 PINCTRL_PIN(288, "PO EMIF 1 BE0 N"), 477 PINCTRL_PIN(288, "PO EMIF 1 BE0 N"),
478 PINCTRL_PIN(289, "PO EMIF 1 ADV N"), 478 PINCTRL_PIN(289, "PO EMIF 1 ADV N"),
479 PINCTRL_PIN(290, "P PAD VDDIO 37"), 479 PINCTRL_PIN(290, "P PAD VDDIO 37"),
480 PINCTRL_PIN(291, "P PAD VSSIO 37"), 480 PINCTRL_PIN(291, "P PAD VSSIO 37"),
481 PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"), 481 PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"),
482 PINCTRL_PIN(293, "PO EMIF 1 OE N"), 482 PINCTRL_PIN(293, "PO EMIF 1 OE N"),
483 PINCTRL_PIN(294, "PO EMIF 1 WE N"), 483 PINCTRL_PIN(294, "PO EMIF 1 WE N"),
484 PINCTRL_PIN(295, "P PAD VDDIO 38"), 484 PINCTRL_PIN(295, "P PAD VDDIO 38"),
485 PINCTRL_PIN(296, "P PAD VSSIO 38"), 485 PINCTRL_PIN(296, "P PAD VSSIO 38"),
486 PINCTRL_PIN(297, "PO EMIF 1 CLK"), 486 PINCTRL_PIN(297, "PO EMIF 1 CLK"),
487 PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"), 487 PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"),
488 PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"), 488 PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"),
489 PINCTRL_PIN(300, "P PAD VDDIO 42"), 489 PINCTRL_PIN(300, "P PAD VDDIO 42"),
490 PINCTRL_PIN(301, "P PAD VSSIO 42"), 490 PINCTRL_PIN(301, "P PAD VSSIO 42"),
491 PINCTRL_PIN(302, "P PAD GND 31"), 491 PINCTRL_PIN(302, "P PAD GND 31"),
492 PINCTRL_PIN(303, "P PAD VDD 31"), 492 PINCTRL_PIN(303, "P PAD VDD 31"),
493 PINCTRL_PIN(304, "PI EMIF 1 RET CLK"), 493 PINCTRL_PIN(304, "PI EMIF 1 RET CLK"),
494 PINCTRL_PIN(305, "PI EMIF 1 WAIT N"), 494 PINCTRL_PIN(305, "PI EMIF 1 WAIT N"),
495 PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"), 495 PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"),
496 PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"), 496 PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"),
497 PINCTRL_PIN(308, "PO EMIF 1 CS3 N"), 497 PINCTRL_PIN(308, "PO EMIF 1 CS3 N"),
498 PINCTRL_PIN(309, "P PAD VDD 25"), 498 PINCTRL_PIN(309, "P PAD VDD 25"),
499 PINCTRL_PIN(310, "P PAD GND 25"), 499 PINCTRL_PIN(310, "P PAD GND 25"),
500 PINCTRL_PIN(311, "P PAD VSSIO 39"), 500 PINCTRL_PIN(311, "P PAD VSSIO 39"),
501 PINCTRL_PIN(312, "P PAD VDDIO 39"), 501 PINCTRL_PIN(312, "P PAD VDDIO 39"),
502 PINCTRL_PIN(313, "PO EMIF 1 CS2 N"), 502 PINCTRL_PIN(313, "PO EMIF 1 CS2 N"),
503 PINCTRL_PIN(314, "PO EMIF 1 CS1 N"), 503 PINCTRL_PIN(314, "PO EMIF 1 CS1 N"),
504 PINCTRL_PIN(315, "PO EMIF 1 CS0 N"), 504 PINCTRL_PIN(315, "PO EMIF 1 CS0 N"),
505 PINCTRL_PIN(316, "PO ETM TRACE PKT0"), 505 PINCTRL_PIN(316, "PO ETM TRACE PKT0"),
506 PINCTRL_PIN(317, "PO ETM TRACE PKT1"), 506 PINCTRL_PIN(317, "PO ETM TRACE PKT1"),
507 PINCTRL_PIN(318, "PO ETM TRACE PKT2"), 507 PINCTRL_PIN(318, "PO ETM TRACE PKT2"),
508 PINCTRL_PIN(319, "P PAD VDD 30"), 508 PINCTRL_PIN(319, "P PAD VDD 30"),
509 PINCTRL_PIN(320, "P PAD GND 30"), 509 PINCTRL_PIN(320, "P PAD GND 30"),
510 PINCTRL_PIN(321, "P PAD VSSIO 44"), 510 PINCTRL_PIN(321, "P PAD VSSIO 44"),
511 PINCTRL_PIN(322, "P PAD VDDIO 44"), 511 PINCTRL_PIN(322, "P PAD VDDIO 44"),
512 PINCTRL_PIN(323, "PO ETM TRACE PKT3"), 512 PINCTRL_PIN(323, "PO ETM TRACE PKT3"),
513 PINCTRL_PIN(324, "PO ETM TRACE PKT4"), 513 PINCTRL_PIN(324, "PO ETM TRACE PKT4"),
514 PINCTRL_PIN(325, "PO ETM TRACE PKT5"), 514 PINCTRL_PIN(325, "PO ETM TRACE PKT5"),
515 PINCTRL_PIN(326, "PO ETM TRACE PKT6"), 515 PINCTRL_PIN(326, "PO ETM TRACE PKT6"),
516 PINCTRL_PIN(327, "PO ETM TRACE PKT7"), 516 PINCTRL_PIN(327, "PO ETM TRACE PKT7"),
517 PINCTRL_PIN(328, "PO ETM PIPE STAT0"), 517 PINCTRL_PIN(328, "PO ETM PIPE STAT0"),
518 PINCTRL_PIN(329, "P PAD VDD 26"), 518 PINCTRL_PIN(329, "P PAD VDD 26"),
519 PINCTRL_PIN(330, "P PAD GND 26"), 519 PINCTRL_PIN(330, "P PAD GND 26"),
520 PINCTRL_PIN(331, "P PAD VSSIO 40"), 520 PINCTRL_PIN(331, "P PAD VSSIO 40"),
521 PINCTRL_PIN(332, "P PAD VDDIO 40"), 521 PINCTRL_PIN(332, "P PAD VDDIO 40"),
522 PINCTRL_PIN(333, "PO ETM PIPE STAT1"), 522 PINCTRL_PIN(333, "PO ETM PIPE STAT1"),
523 PINCTRL_PIN(334, "PO ETM PIPE STAT2"), 523 PINCTRL_PIN(334, "PO ETM PIPE STAT2"),
524 PINCTRL_PIN(335, "PO ETM TRACE CLK"), 524 PINCTRL_PIN(335, "PO ETM TRACE CLK"),
525 PINCTRL_PIN(336, "PO ETM TRACE SYNC"), 525 PINCTRL_PIN(336, "PO ETM TRACE SYNC"),
526 PINCTRL_PIN(337, "PIO ACC GPIO 33"), 526 PINCTRL_PIN(337, "PIO ACC GPIO 33"),
527 PINCTRL_PIN(338, "PIO ACC GPIO 32"), 527 PINCTRL_PIN(338, "PIO ACC GPIO 32"),
528 PINCTRL_PIN(339, "PIO ACC GPIO 30"), 528 PINCTRL_PIN(339, "PIO ACC GPIO 30"),
529 PINCTRL_PIN(340, "PIO ACC GPIO 29"), 529 PINCTRL_PIN(340, "PIO ACC GPIO 29"),
530 PINCTRL_PIN(341, "P PAD VDDIO 17"), 530 PINCTRL_PIN(341, "P PAD VDDIO 17"),
531 PINCTRL_PIN(342, "P PAD VSSIO 17"), 531 PINCTRL_PIN(342, "P PAD VSSIO 17"),
532 PINCTRL_PIN(343, "P PAD GND 15"), 532 PINCTRL_PIN(343, "P PAD GND 15"),
533 PINCTRL_PIN(344, "P PAD VDD 15"), 533 PINCTRL_PIN(344, "P PAD VDD 15"),
534 PINCTRL_PIN(345, "PIO ACC GPIO 28"), 534 PINCTRL_PIN(345, "PIO ACC GPIO 28"),
535 PINCTRL_PIN(346, "PIO ACC GPIO 27"), 535 PINCTRL_PIN(346, "PIO ACC GPIO 27"),
536 PINCTRL_PIN(347, "PIO ACC GPIO 16"), 536 PINCTRL_PIN(347, "PIO ACC GPIO 16"),
537 PINCTRL_PIN(348, "PI TAP TMS"), 537 PINCTRL_PIN(348, "PI TAP TMS"),
538 PINCTRL_PIN(349, "PI TAP TDI"), 538 PINCTRL_PIN(349, "PI TAP TDI"),
539 PINCTRL_PIN(350, "PO TAP TDO"), 539 PINCTRL_PIN(350, "PO TAP TDO"),
540 PINCTRL_PIN(351, "PI TAP RST N"), 540 PINCTRL_PIN(351, "PI TAP RST N"),
541 /* Pads along the left edge of the chip */ 541 /* Pads along the left edge of the chip */
542 PINCTRL_PIN(352, "PI EMU MODE 0"), 542 PINCTRL_PIN(352, "PI EMU MODE 0"),
543 PINCTRL_PIN(353, "PO TAP RET CLK"), 543 PINCTRL_PIN(353, "PO TAP RET CLK"),
544 PINCTRL_PIN(354, "PI TAP CLK"), 544 PINCTRL_PIN(354, "PI TAP CLK"),
545 PINCTRL_PIN(355, "PO EMIF 0 SD CS N"), 545 PINCTRL_PIN(355, "PO EMIF 0 SD CS N"),
546 PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"), 546 PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
547 PINCTRL_PIN(357, "PO EMIF 0 SD WE N"), 547 PINCTRL_PIN(357, "PO EMIF 0 SD WE N"),
548 PINCTRL_PIN(358, "P PAD VDDIO 1"), 548 PINCTRL_PIN(358, "P PAD VDDIO 1"),
549 PINCTRL_PIN(359, "P PAD VSSIO 1"), 549 PINCTRL_PIN(359, "P PAD VSSIO 1"),
550 PINCTRL_PIN(360, "P PAD GND 1"), 550 PINCTRL_PIN(360, "P PAD GND 1"),
551 PINCTRL_PIN(361, "P PAD VDD 1"), 551 PINCTRL_PIN(361, "P PAD VDD 1"),
552 PINCTRL_PIN(362, "PO EMIF 0 SD CKE"), 552 PINCTRL_PIN(362, "PO EMIF 0 SD CKE"),
553 PINCTRL_PIN(363, "PO EMIF 0 SD DQML"), 553 PINCTRL_PIN(363, "PO EMIF 0 SD DQML"),
554 PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"), 554 PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"),
555 PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"), 555 PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
556 PINCTRL_PIN(366, "PIO EMIF 0 D15"), 556 PINCTRL_PIN(366, "PIO EMIF 0 D15"),
557 PINCTRL_PIN(367, "PO EMIF 0 A15"), 557 PINCTRL_PIN(367, "PO EMIF 0 A15"),
558 PINCTRL_PIN(368, "PIO EMIF 0 D14"), 558 PINCTRL_PIN(368, "PIO EMIF 0 D14"),
559 PINCTRL_PIN(369, "PO EMIF 0 A14"), 559 PINCTRL_PIN(369, "PO EMIF 0 A14"),
560 PINCTRL_PIN(370, "PIO EMIF 0 D13"), 560 PINCTRL_PIN(370, "PIO EMIF 0 D13"),
561 PINCTRL_PIN(371, "PO EMIF 0 A13"), 561 PINCTRL_PIN(371, "PO EMIF 0 A13"),
562 PINCTRL_PIN(372, "P PAD VDDIO 2"), 562 PINCTRL_PIN(372, "P PAD VDDIO 2"),
563 PINCTRL_PIN(373, "P PAD VSSIO 2"), 563 PINCTRL_PIN(373, "P PAD VSSIO 2"),
564 PINCTRL_PIN(374, "P PAD GND 2"), 564 PINCTRL_PIN(374, "P PAD GND 2"),
565 PINCTRL_PIN(375, "P PAD VDD 2"), 565 PINCTRL_PIN(375, "P PAD VDD 2"),
566 PINCTRL_PIN(376, "PIO EMIF 0 D12"), 566 PINCTRL_PIN(376, "PIO EMIF 0 D12"),
567 PINCTRL_PIN(377, "PO EMIF 0 A12"), 567 PINCTRL_PIN(377, "PO EMIF 0 A12"),
568 PINCTRL_PIN(378, "PIO EMIF 0 D11"), 568 PINCTRL_PIN(378, "PIO EMIF 0 D11"),
569 PINCTRL_PIN(379, "PO EMIF 0 A11"), 569 PINCTRL_PIN(379, "PO EMIF 0 A11"),
570 PINCTRL_PIN(380, "PIO EMIF 0 D10"), 570 PINCTRL_PIN(380, "PIO EMIF 0 D10"),
571 PINCTRL_PIN(381, "PO EMIF 0 A10"), 571 PINCTRL_PIN(381, "PO EMIF 0 A10"),
572 PINCTRL_PIN(382, "PIO EMIF 0 D09"), 572 PINCTRL_PIN(382, "PIO EMIF 0 D09"),
573 PINCTRL_PIN(383, "PO EMIF 0 A09"), 573 PINCTRL_PIN(383, "PO EMIF 0 A09"),
574 PINCTRL_PIN(384, "PIO EMIF 0 D08"), 574 PINCTRL_PIN(384, "PIO EMIF 0 D08"),
575 PINCTRL_PIN(385, "PO EMIF 0 A08"), 575 PINCTRL_PIN(385, "PO EMIF 0 A08"),
576 PINCTRL_PIN(386, "PIO EMIF 0 D07"), 576 PINCTRL_PIN(386, "PIO EMIF 0 D07"),
577 PINCTRL_PIN(387, "PO EMIF 0 A07"), 577 PINCTRL_PIN(387, "PO EMIF 0 A07"),
578 PINCTRL_PIN(388, "P PAD VDDIO 3"), 578 PINCTRL_PIN(388, "P PAD VDDIO 3"),
579 PINCTRL_PIN(389, "P PAD VSSIO 3"), 579 PINCTRL_PIN(389, "P PAD VSSIO 3"),
580 PINCTRL_PIN(390, "P PAD GND 3"), 580 PINCTRL_PIN(390, "P PAD GND 3"),
581 PINCTRL_PIN(391, "P PAD VDD 3"), 581 PINCTRL_PIN(391, "P PAD VDD 3"),
582 PINCTRL_PIN(392, "PO EFUSE RDOUT1"), 582 PINCTRL_PIN(392, "PO EFUSE RDOUT1"),
583 PINCTRL_PIN(393, "PIO EMIF 0 D06"), 583 PINCTRL_PIN(393, "PIO EMIF 0 D06"),
584 PINCTRL_PIN(394, "PO EMIF 0 A06"), 584 PINCTRL_PIN(394, "PO EMIF 0 A06"),
585 PINCTRL_PIN(395, "PIO EMIF 0 D05"), 585 PINCTRL_PIN(395, "PIO EMIF 0 D05"),
586 PINCTRL_PIN(396, "PO EMIF 0 A05"), 586 PINCTRL_PIN(396, "PO EMIF 0 A05"),
587 PINCTRL_PIN(397, "PIO EMIF 0 D04"), 587 PINCTRL_PIN(397, "PIO EMIF 0 D04"),
588 PINCTRL_PIN(398, "PO EMIF 0 A04"), 588 PINCTRL_PIN(398, "PO EMIF 0 A04"),
589 PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"), 589 PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"),
590 PINCTRL_PIN(400, "PWR VDDCO AF"), 590 PINCTRL_PIN(400, "PWR VDDCO AF"),
591 PINCTRL_PIN(401, "PWR EFUSE HV1"), 591 PINCTRL_PIN(401, "PWR EFUSE HV1"),
592 PINCTRL_PIN(402, "P PAD VSSIO 4"), 592 PINCTRL_PIN(402, "P PAD VSSIO 4"),
593 PINCTRL_PIN(403, "P PAD VDDIO 4"), 593 PINCTRL_PIN(403, "P PAD VDDIO 4"),
594 PINCTRL_PIN(404, "P PAD GND 4"), 594 PINCTRL_PIN(404, "P PAD GND 4"),
595 PINCTRL_PIN(405, "P PAD VDD 4"), 595 PINCTRL_PIN(405, "P PAD VDD 4"),
596 PINCTRL_PIN(406, "PIO EMIF 0 D03"), 596 PINCTRL_PIN(406, "PIO EMIF 0 D03"),
597 PINCTRL_PIN(407, "PO EMIF 0 A03"), 597 PINCTRL_PIN(407, "PO EMIF 0 A03"),
598 PINCTRL_PIN(408, "PWR EFUSE HV2"), 598 PINCTRL_PIN(408, "PWR EFUSE HV2"),
599 PINCTRL_PIN(409, "PWR EFUSE HV3"), 599 PINCTRL_PIN(409, "PWR EFUSE HV3"),
600 PINCTRL_PIN(410, "PIO EMIF 0 D02"), 600 PINCTRL_PIN(410, "PIO EMIF 0 D02"),
601 PINCTRL_PIN(411, "PO EMIF 0 A02"), 601 PINCTRL_PIN(411, "PO EMIF 0 A02"),
602 PINCTRL_PIN(412, "PIO EMIF 0 D01"), 602 PINCTRL_PIN(412, "PIO EMIF 0 D01"),
603 PINCTRL_PIN(413, "P PAD VDDIO 5"), 603 PINCTRL_PIN(413, "P PAD VDDIO 5"),
604 PINCTRL_PIN(414, "P PAD VSSIO 5"), 604 PINCTRL_PIN(414, "P PAD VSSIO 5"),
605 PINCTRL_PIN(415, "P PAD GND 5"), 605 PINCTRL_PIN(415, "P PAD GND 5"),
606 PINCTRL_PIN(416, "P PAD VDD 5"), 606 PINCTRL_PIN(416, "P PAD VDD 5"),
607 PINCTRL_PIN(417, "PO EMIF 0 A01"), 607 PINCTRL_PIN(417, "PO EMIF 0 A01"),
608 PINCTRL_PIN(418, "PIO EMIF 0 D00"), 608 PINCTRL_PIN(418, "PIO EMIF 0 D00"),
609 PINCTRL_PIN(419, "IF 0 SD CLK"), 609 PINCTRL_PIN(419, "IF 0 SD CLK"),
610 PINCTRL_PIN(420, "APP SPI CLK"), 610 PINCTRL_PIN(420, "APP SPI CLK"),
611 PINCTRL_PIN(421, "APP SPI DO"), 611 PINCTRL_PIN(421, "APP SPI DO"),
612 PINCTRL_PIN(422, "APP SPI DI"), 612 PINCTRL_PIN(422, "APP SPI DI"),
613 PINCTRL_PIN(423, "APP SPI CS0"), 613 PINCTRL_PIN(423, "APP SPI CS0"),
614 PINCTRL_PIN(424, "APP SPI CS1"), 614 PINCTRL_PIN(424, "APP SPI CS1"),
615 PINCTRL_PIN(425, "APP SPI CS2"), 615 PINCTRL_PIN(425, "APP SPI CS2"),
616 PINCTRL_PIN(426, "PIO APP GPIO 10"), 616 PINCTRL_PIN(426, "PIO APP GPIO 10"),
617 PINCTRL_PIN(427, "P PAD VDDIO 41"), 617 PINCTRL_PIN(427, "P PAD VDDIO 41"),
618 PINCTRL_PIN(428, "P PAD VSSIO 41"), 618 PINCTRL_PIN(428, "P PAD VSSIO 41"),
619 PINCTRL_PIN(429, "P PAD GND 6"), 619 PINCTRL_PIN(429, "P PAD GND 6"),
620 PINCTRL_PIN(430, "P PAD VDD 6"), 620 PINCTRL_PIN(430, "P PAD VDD 6"),
621 PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"), 621 PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"),
622 PINCTRL_PIN(432, "PIO ACC SDIO0 CK"), 622 PINCTRL_PIN(432, "PIO ACC SDIO0 CK"),
623 PINCTRL_PIN(433, "PIO ACC SDIO0 D3"), 623 PINCTRL_PIN(433, "PIO ACC SDIO0 D3"),
624 PINCTRL_PIN(434, "PIO ACC SDIO0 D2"), 624 PINCTRL_PIN(434, "PIO ACC SDIO0 D2"),
625 PINCTRL_PIN(435, "PIO ACC SDIO0 D1"), 625 PINCTRL_PIN(435, "PIO ACC SDIO0 D1"),
626 PINCTRL_PIN(436, "PIO ACC SDIO0 D0"), 626 PINCTRL_PIN(436, "PIO ACC SDIO0 D0"),
627 PINCTRL_PIN(437, "PIO USB PU"), 627 PINCTRL_PIN(437, "PIO USB PU"),
628 PINCTRL_PIN(438, "PIO USB SP"), 628 PINCTRL_PIN(438, "PIO USB SP"),
629 PINCTRL_PIN(439, "PIO USB DAT VP"), 629 PINCTRL_PIN(439, "PIO USB DAT VP"),
630 PINCTRL_PIN(440, "PIO USB SE0 VM"), 630 PINCTRL_PIN(440, "PIO USB SE0 VM"),
631 PINCTRL_PIN(441, "PIO USB OE"), 631 PINCTRL_PIN(441, "PIO USB OE"),
632 PINCTRL_PIN(442, "PIO USB SUSP"), 632 PINCTRL_PIN(442, "PIO USB SUSP"),
633 PINCTRL_PIN(443, "P PAD VSSIO 6"), 633 PINCTRL_PIN(443, "P PAD VSSIO 6"),
634 PINCTRL_PIN(444, "P PAD VDDIO 6"), 634 PINCTRL_PIN(444, "P PAD VDDIO 6"),
635 PINCTRL_PIN(445, "PIO USB PUEN"), 635 PINCTRL_PIN(445, "PIO USB PUEN"),
636 PINCTRL_PIN(446, "PIO ACC UART0 RX"), 636 PINCTRL_PIN(446, "PIO ACC UART0 RX"),
637 PINCTRL_PIN(447, "PIO ACC UART0 TX"), 637 PINCTRL_PIN(447, "PIO ACC UART0 TX"),
638 PINCTRL_PIN(448, "PIO ACC UART0 CTS"), 638 PINCTRL_PIN(448, "PIO ACC UART0 CTS"),
639 PINCTRL_PIN(449, "PIO ACC UART0 RTS"), 639 PINCTRL_PIN(449, "PIO ACC UART0 RTS"),
640 PINCTRL_PIN(450, "PIO ACC UART3 RX"), 640 PINCTRL_PIN(450, "PIO ACC UART3 RX"),
641 PINCTRL_PIN(451, "PIO ACC UART3 TX"), 641 PINCTRL_PIN(451, "PIO ACC UART3 TX"),
642 PINCTRL_PIN(452, "PIO ACC UART3 CTS"), 642 PINCTRL_PIN(452, "PIO ACC UART3 CTS"),
643 PINCTRL_PIN(453, "PIO ACC UART3 RTS"), 643 PINCTRL_PIN(453, "PIO ACC UART3 RTS"),
644 PINCTRL_PIN(454, "PIO ACC IRDA TX"), 644 PINCTRL_PIN(454, "PIO ACC IRDA TX"),
645 PINCTRL_PIN(455, "P PAD VDDIO 7"), 645 PINCTRL_PIN(455, "P PAD VDDIO 7"),
646 PINCTRL_PIN(456, "P PAD VSSIO 7"), 646 PINCTRL_PIN(456, "P PAD VSSIO 7"),
647 PINCTRL_PIN(457, "P PAD GND 7"), 647 PINCTRL_PIN(457, "P PAD GND 7"),
648 PINCTRL_PIN(458, "P PAD VDD 7"), 648 PINCTRL_PIN(458, "P PAD VDD 7"),
649 PINCTRL_PIN(459, "PIO ACC IRDA RX"), 649 PINCTRL_PIN(459, "PIO ACC IRDA RX"),
650 PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"), 650 PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"),
651 PINCTRL_PIN(461, "PIO ACC PCM I2S WS"), 651 PINCTRL_PIN(461, "PIO ACC PCM I2S WS"),
652 PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"), 652 PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"),
653 PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"), 653 PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"),
654 PINCTRL_PIN(464, "PO SIM CLK"), 654 PINCTRL_PIN(464, "PO SIM CLK"),
655 PINCTRL_PIN(465, "PIO ACC IRDA SD"), 655 PINCTRL_PIN(465, "PIO ACC IRDA SD"),
656 PINCTRL_PIN(466, "PIO SIM DATA"), 656 PINCTRL_PIN(466, "PIO SIM DATA"),
657 }; 657 };
658 658
659 /** 659 /**
660 * @dev: a pointer back to containing device 660 * @dev: a pointer back to containing device
661 * @virtbase: the offset to the controller in virtual memory 661 * @virtbase: the offset to the controller in virtual memory
662 */ 662 */
663 struct u300_pmx { 663 struct u300_pmx {
664 struct device *dev; 664 struct device *dev;
665 struct pinctrl_dev *pctl; 665 struct pinctrl_dev *pctl;
666 u32 phybase; 666 u32 phybase;
667 u32 physize; 667 u32 physize;
668 void __iomem *virtbase; 668 void __iomem *virtbase;
669 }; 669 };
670 670
671 /** 671 /**
672 * u300_pmx_registers - the array of registers read/written for each pinmux 672 * u300_pmx_registers - the array of registers read/written for each pinmux
673 * shunt setting 673 * shunt setting
674 */ 674 */
675 const u32 u300_pmx_registers[] = { 675 const u32 u300_pmx_registers[] = {
676 U300_SYSCON_PMC1LR, 676 U300_SYSCON_PMC1LR,
677 U300_SYSCON_PMC1HR, 677 U300_SYSCON_PMC1HR,
678 U300_SYSCON_PMC2R, 678 U300_SYSCON_PMC2R,
679 U300_SYSCON_PMC3R, 679 U300_SYSCON_PMC3R,
680 U300_SYSCON_PMC4R, 680 U300_SYSCON_PMC4R,
681 }; 681 };
682 682
683 /** 683 /**
684 * struct u300_pin_group - describes a U300 pin group 684 * struct u300_pin_group - describes a U300 pin group
685 * @name: the name of this specific pin group 685 * @name: the name of this specific pin group
686 * @pins: an array of discrete physical pins used in this group, taken 686 * @pins: an array of discrete physical pins used in this group, taken
687 * from the driver-local pin enumeration space 687 * from the driver-local pin enumeration space
688 * @num_pins: the number of pins in this group array, i.e. the number of 688 * @num_pins: the number of pins in this group array, i.e. the number of
689 * elements in .pins so we can iterate over that array 689 * elements in .pins so we can iterate over that array
690 */ 690 */
691 struct u300_pin_group { 691 struct u300_pin_group {
692 const char *name; 692 const char *name;
693 const unsigned int *pins; 693 const unsigned int *pins;
694 const unsigned num_pins; 694 const unsigned num_pins;
695 }; 695 };
696 696
697 /** 697 /**
698 * struct pmx_onmask - mask bits to enable/disable padmux 698 * struct pmx_onmask - mask bits to enable/disable padmux
699 * @mask: mask bits to disable 699 * @mask: mask bits to disable
700 * @val: mask bits to enable 700 * @val: mask bits to enable
701 * 701 *
702 * onmask lazy dog: 702 * onmask lazy dog:
703 * onmask = { 703 * onmask = {
704 * {"PMC1LR" mask, "PMC1LR" value}, 704 * {"PMC1LR" mask, "PMC1LR" value},
705 * {"PMC1HR" mask, "PMC1HR" value}, 705 * {"PMC1HR" mask, "PMC1HR" value},
706 * {"PMC2R" mask, "PMC2R" value}, 706 * {"PMC2R" mask, "PMC2R" value},
707 * {"PMC3R" mask, "PMC3R" value}, 707 * {"PMC3R" mask, "PMC3R" value},
708 * {"PMC4R" mask, "PMC4R" value} 708 * {"PMC4R" mask, "PMC4R" value}
709 * } 709 * }
710 */ 710 */
711 struct u300_pmx_mask { 711 struct u300_pmx_mask {
712 u16 mask; 712 u16 mask;
713 u16 bits; 713 u16 bits;
714 }; 714 };
715 715
716 /* The chip power pins are VDD, GND, VDDIO and VSSIO */ 716 /* The chip power pins are VDD, GND, VDDIO and VSSIO */
717 static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63, 717 static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63,
718 64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117, 718 64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117,
719 118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174, 719 118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174,
720 175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223, 720 175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223,
721 224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256, 721 224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256,
722 257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290, 722 257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290,
723 291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320, 723 291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320,
724 321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361, 724 321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361,
725 372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414, 725 372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414,
726 415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 }; 726 415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 };
727 static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366, 727 static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366,
728 367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384, 728 367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384,
729 385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412, 729 385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412,
730 417, 418 }; 730 417, 418 };
731 static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228, 731 static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228,
732 229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250, 732 229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250,
733 253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274, 733 253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274,
734 275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298, 734 275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298,
735 304, 305, 306, 307, 308, 313, 314, 315 }; 735 304, 305, 306, 307, 308, 313, 314, 315 };
736 static const unsigned uart0_pins[] = { 134, 135, 136, 137 }; 736 static const unsigned uart0_pins[] = { 134, 135, 136, 137 };
737 static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 }; 737 static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 };
738 static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 }; 738 static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 };
739 739
740 static const struct u300_pmx_mask emif0_mask[] = { 740 static const struct u300_pmx_mask emif0_mask[] = {
741 {0, 0}, 741 {0, 0},
742 {0, 0}, 742 {0, 0},
743 {0, 0}, 743 {0, 0},
744 {0, 0}, 744 {0, 0},
745 {0, 0}, 745 {0, 0},
746 }; 746 };
747 747
748 static const struct u300_pmx_mask emif1_mask[] = { 748 static const struct u300_pmx_mask emif1_mask[] = {
749 /* 749 /*
750 * This connects the SDRAM to CS2 and a NAND flash to 750 * This connects the SDRAM to CS2 and a NAND flash to
751 * CS0 on the EMIF. 751 * CS0 on the EMIF.
752 */ 752 */
753 { 753 {
754 U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK | 754 U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK |
755 U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK | 755 U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK |
756 U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK | 756 U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK |
757 U300_SYSCON_PMC1LR_EMIF_1_MASK, 757 U300_SYSCON_PMC1LR_EMIF_1_MASK,
758 U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM | 758 U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM |
759 U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC | 759 U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC |
760 U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF | 760 U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF |
761 U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 761 U300_SYSCON_PMC1LR_EMIF_1_SDRAM0
762 }, 762 },
763 {0, 0}, 763 {0, 0},
764 {0, 0}, 764 {0, 0},
765 {0, 0}, 765 {0, 0},
766 {0, 0}, 766 {0, 0},
767 }; 767 };
768 768
769 static const struct u300_pmx_mask uart0_mask[] = { 769 static const struct u300_pmx_mask uart0_mask[] = {
770 {0, 0}, 770 {0, 0},
771 { 771 {
772 U300_SYSCON_PMC1HR_APP_UART0_1_MASK | 772 U300_SYSCON_PMC1HR_APP_UART0_1_MASK |
773 U300_SYSCON_PMC1HR_APP_UART0_2_MASK, 773 U300_SYSCON_PMC1HR_APP_UART0_2_MASK,
774 U300_SYSCON_PMC1HR_APP_UART0_1_UART0 | 774 U300_SYSCON_PMC1HR_APP_UART0_1_UART0 |
775 U300_SYSCON_PMC1HR_APP_UART0_2_UART0 775 U300_SYSCON_PMC1HR_APP_UART0_2_UART0
776 }, 776 },
777 {0, 0}, 777 {0, 0},
778 {0, 0}, 778 {0, 0},
779 {0, 0}, 779 {0, 0},
780 }; 780 };
781 781
782 static const struct u300_pmx_mask mmc0_mask[] = { 782 static const struct u300_pmx_mask mmc0_mask[] = {
783 { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD}, 783 { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD},
784 {0, 0}, 784 {0, 0},
785 {0, 0}, 785 {0, 0},
786 {0, 0}, 786 {0, 0},
787 { U300_SYSCON_PMC4R_APP_MISC_12_MASK, 787 { U300_SYSCON_PMC4R_APP_MISC_12_MASK,
788 U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO } 788 U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO }
789 }; 789 };
790 790
791 static const struct u300_pmx_mask spi0_mask[] = { 791 static const struct u300_pmx_mask spi0_mask[] = {
792 {0, 0}, 792 {0, 0},
793 { 793 {
794 U300_SYSCON_PMC1HR_APP_SPI_2_MASK | 794 U300_SYSCON_PMC1HR_APP_SPI_2_MASK |
795 U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK | 795 U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK |
796 U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK, 796 U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK,
797 U300_SYSCON_PMC1HR_APP_SPI_2_SPI | 797 U300_SYSCON_PMC1HR_APP_SPI_2_SPI |
798 U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI | 798 U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI |
799 U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI 799 U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI
800 }, 800 },
801 {0, 0}, 801 {0, 0},
802 {0, 0}, 802 {0, 0},
803 {0, 0} 803 {0, 0}
804 }; 804 };
805 805
806 static const struct u300_pin_group u300_pin_groups[] = { 806 static const struct u300_pin_group u300_pin_groups[] = {
807 { 807 {
808 .name = "powergrp", 808 .name = "powergrp",
809 .pins = power_pins, 809 .pins = power_pins,
810 .num_pins = ARRAY_SIZE(power_pins), 810 .num_pins = ARRAY_SIZE(power_pins),
811 }, 811 },
812 { 812 {
813 .name = "emif0grp", 813 .name = "emif0grp",
814 .pins = emif0_pins, 814 .pins = emif0_pins,
815 .num_pins = ARRAY_SIZE(emif0_pins), 815 .num_pins = ARRAY_SIZE(emif0_pins),
816 }, 816 },
817 { 817 {
818 .name = "emif1grp", 818 .name = "emif1grp",
819 .pins = emif1_pins, 819 .pins = emif1_pins,
820 .num_pins = ARRAY_SIZE(emif1_pins), 820 .num_pins = ARRAY_SIZE(emif1_pins),
821 }, 821 },
822 { 822 {
823 .name = "uart0grp", 823 .name = "uart0grp",
824 .pins = uart0_pins, 824 .pins = uart0_pins,
825 .num_pins = ARRAY_SIZE(uart0_pins), 825 .num_pins = ARRAY_SIZE(uart0_pins),
826 }, 826 },
827 { 827 {
828 .name = "mmc0grp", 828 .name = "mmc0grp",
829 .pins = mmc0_pins, 829 .pins = mmc0_pins,
830 .num_pins = ARRAY_SIZE(mmc0_pins), 830 .num_pins = ARRAY_SIZE(mmc0_pins),
831 }, 831 },
832 { 832 {
833 .name = "spi0grp", 833 .name = "spi0grp",
834 .pins = spi0_pins, 834 .pins = spi0_pins,
835 .num_pins = ARRAY_SIZE(spi0_pins), 835 .num_pins = ARRAY_SIZE(spi0_pins),
836 }, 836 },
837 }; 837 };
838 838
839 static int u300_get_groups_count(struct pinctrl_dev *pctldev) 839 static int u300_get_groups_count(struct pinctrl_dev *pctldev)
840 { 840 {
841 return ARRAY_SIZE(u300_pin_groups); 841 return ARRAY_SIZE(u300_pin_groups);
842 } 842 }
843 843
844 static const char *u300_get_group_name(struct pinctrl_dev *pctldev, 844 static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
845 unsigned selector) 845 unsigned selector)
846 { 846 {
847 return u300_pin_groups[selector].name; 847 return u300_pin_groups[selector].name;
848 } 848 }
849 849
850 static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 850 static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
851 const unsigned **pins, 851 const unsigned **pins,
852 unsigned *num_pins) 852 unsigned *num_pins)
853 { 853 {
854 *pins = u300_pin_groups[selector].pins; 854 *pins = u300_pin_groups[selector].pins;
855 *num_pins = u300_pin_groups[selector].num_pins; 855 *num_pins = u300_pin_groups[selector].num_pins;
856 return 0; 856 return 0;
857 } 857 }
858 858
859 static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 859 static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
860 unsigned offset) 860 unsigned offset)
861 { 861 {
862 seq_printf(s, " " DRIVER_NAME); 862 seq_printf(s, " " DRIVER_NAME);
863 } 863 }
864 864
865 static struct pinctrl_ops u300_pctrl_ops = { 865 static struct pinctrl_ops u300_pctrl_ops = {
866 .get_groups_count = u300_get_groups_count, 866 .get_groups_count = u300_get_groups_count,
867 .get_group_name = u300_get_group_name, 867 .get_group_name = u300_get_group_name,
868 .get_group_pins = u300_get_group_pins, 868 .get_group_pins = u300_get_group_pins,
869 .pin_dbg_show = u300_pin_dbg_show, 869 .pin_dbg_show = u300_pin_dbg_show,
870 }; 870 };
871 871
872 /* 872 /*
873 * Here we define the available functions and their corresponding pin groups 873 * Here we define the available functions and their corresponding pin groups
874 */ 874 */
875 875
876 /** 876 /**
877 * struct u300_pmx_func - describes U300 pinmux functions 877 * struct u300_pmx_func - describes U300 pinmux functions
878 * @name: the name of this specific function 878 * @name: the name of this specific function
879 * @groups: corresponding pin groups 879 * @groups: corresponding pin groups
880 * @onmask: bits to set to enable this when doing pin muxing 880 * @onmask: bits to set to enable this when doing pin muxing
881 */ 881 */
882 struct u300_pmx_func { 882 struct u300_pmx_func {
883 const char *name; 883 const char *name;
884 const char * const *groups; 884 const char * const *groups;
885 const unsigned num_groups; 885 const unsigned num_groups;
886 const struct u300_pmx_mask *mask; 886 const struct u300_pmx_mask *mask;
887 }; 887 };
888 888
889 static const char * const powergrps[] = { "powergrp" }; 889 static const char * const powergrps[] = { "powergrp" };
890 static const char * const emif0grps[] = { "emif0grp" }; 890 static const char * const emif0grps[] = { "emif0grp" };
891 static const char * const emif1grps[] = { "emif1grp" }; 891 static const char * const emif1grps[] = { "emif1grp" };
892 static const char * const uart0grps[] = { "uart0grp" }; 892 static const char * const uart0grps[] = { "uart0grp" };
893 static const char * const mmc0grps[] = { "mmc0grp" }; 893 static const char * const mmc0grps[] = { "mmc0grp" };
894 static const char * const spi0grps[] = { "spi0grp" }; 894 static const char * const spi0grps[] = { "spi0grp" };
895 895
896 static const struct u300_pmx_func u300_pmx_functions[] = { 896 static const struct u300_pmx_func u300_pmx_functions[] = {
897 { 897 {
898 .name = "power", 898 .name = "power",
899 .groups = powergrps, 899 .groups = powergrps,
900 .num_groups = ARRAY_SIZE(powergrps), 900 .num_groups = ARRAY_SIZE(powergrps),
901 /* Mask is N/A */ 901 /* Mask is N/A */
902 }, 902 },
903 { 903 {
904 .name = "emif0", 904 .name = "emif0",
905 .groups = emif0grps, 905 .groups = emif0grps,
906 .num_groups = ARRAY_SIZE(emif0grps), 906 .num_groups = ARRAY_SIZE(emif0grps),
907 .mask = emif0_mask, 907 .mask = emif0_mask,
908 }, 908 },
909 { 909 {
910 .name = "emif1", 910 .name = "emif1",
911 .groups = emif1grps, 911 .groups = emif1grps,
912 .num_groups = ARRAY_SIZE(emif1grps), 912 .num_groups = ARRAY_SIZE(emif1grps),
913 .mask = emif1_mask, 913 .mask = emif1_mask,
914 }, 914 },
915 { 915 {
916 .name = "uart0", 916 .name = "uart0",
917 .groups = uart0grps, 917 .groups = uart0grps,
918 .num_groups = ARRAY_SIZE(uart0grps), 918 .num_groups = ARRAY_SIZE(uart0grps),
919 .mask = uart0_mask, 919 .mask = uart0_mask,
920 }, 920 },
921 { 921 {
922 .name = "mmc0", 922 .name = "mmc0",
923 .groups = mmc0grps, 923 .groups = mmc0grps,
924 .num_groups = ARRAY_SIZE(mmc0grps), 924 .num_groups = ARRAY_SIZE(mmc0grps),
925 .mask = mmc0_mask, 925 .mask = mmc0_mask,
926 }, 926 },
927 { 927 {
928 .name = "spi0", 928 .name = "spi0",
929 .groups = spi0grps, 929 .groups = spi0grps,
930 .num_groups = ARRAY_SIZE(spi0grps), 930 .num_groups = ARRAY_SIZE(spi0grps),
931 .mask = spi0_mask, 931 .mask = spi0_mask,
932 }, 932 },
933 }; 933 };
934 934
935 static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector, 935 static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
936 bool enable) 936 bool enable)
937 { 937 {
938 u16 regval, val, mask; 938 u16 regval, val, mask;
939 int i; 939 int i;
940 const struct u300_pmx_mask *upmx_mask; 940 const struct u300_pmx_mask *upmx_mask;
941 941
942 upmx_mask = u300_pmx_functions[selector].mask; 942 upmx_mask = u300_pmx_functions[selector].mask;
943 for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) { 943 for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) {
944 if (enable) 944 if (enable)
945 val = upmx_mask->bits; 945 val = upmx_mask->bits;
946 else 946 else
947 val = 0; 947 val = 0;
948 948
949 mask = upmx_mask->mask; 949 mask = upmx_mask->mask;
950 if (mask != 0) { 950 if (mask != 0) {
951 regval = readw(upmx->virtbase + u300_pmx_registers[i]); 951 regval = readw(upmx->virtbase + u300_pmx_registers[i]);
952 regval &= ~mask; 952 regval &= ~mask;
953 regval |= val; 953 regval |= val;
954 writew(regval, upmx->virtbase + u300_pmx_registers[i]); 954 writew(regval, upmx->virtbase + u300_pmx_registers[i]);
955 } 955 }
956 upmx_mask++; 956 upmx_mask++;
957 } 957 }
958 } 958 }
959 959
960 static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 960 static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
961 unsigned group) 961 unsigned group)
962 { 962 {
963 struct u300_pmx *upmx; 963 struct u300_pmx *upmx;
964 964
965 /* There is nothing to do with the power pins */ 965 /* There is nothing to do with the power pins */
966 if (selector == 0) 966 if (selector == 0)
967 return 0; 967 return 0;
968 968
969 upmx = pinctrl_dev_get_drvdata(pctldev); 969 upmx = pinctrl_dev_get_drvdata(pctldev);
970 u300_pmx_endisable(upmx, selector, true); 970 u300_pmx_endisable(upmx, selector, true);
971 971
972 return 0; 972 return 0;
973 } 973 }
974 974
975 static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, 975 static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
976 unsigned group) 976 unsigned group)
977 { 977 {
978 struct u300_pmx *upmx; 978 struct u300_pmx *upmx;
979 979
980 /* There is nothing to do with the power pins */ 980 /* There is nothing to do with the power pins */
981 if (selector == 0) 981 if (selector == 0)
982 return; 982 return;
983 983
984 upmx = pinctrl_dev_get_drvdata(pctldev); 984 upmx = pinctrl_dev_get_drvdata(pctldev);
985 u300_pmx_endisable(upmx, selector, false); 985 u300_pmx_endisable(upmx, selector, false);
986 } 986 }
987 987
988 static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 988 static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
989 { 989 {
990 return ARRAY_SIZE(u300_pmx_functions); 990 return ARRAY_SIZE(u300_pmx_functions);
991 } 991 }
992 992
993 static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev, 993 static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
994 unsigned selector) 994 unsigned selector)
995 { 995 {
996 return u300_pmx_functions[selector].name; 996 return u300_pmx_functions[selector].name;
997 } 997 }
998 998
999 static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 999 static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1000 const char * const **groups, 1000 const char * const **groups,
1001 unsigned * const num_groups) 1001 unsigned * const num_groups)
1002 { 1002 {
1003 *groups = u300_pmx_functions[selector].groups; 1003 *groups = u300_pmx_functions[selector].groups;
1004 *num_groups = u300_pmx_functions[selector].num_groups; 1004 *num_groups = u300_pmx_functions[selector].num_groups;
1005 return 0; 1005 return 0;
1006 } 1006 }
1007 1007
1008 static struct pinmux_ops u300_pmx_ops = { 1008 static struct pinmux_ops u300_pmx_ops = {
1009 .get_functions_count = u300_pmx_get_funcs_count, 1009 .get_functions_count = u300_pmx_get_funcs_count,
1010 .get_function_name = u300_pmx_get_func_name, 1010 .get_function_name = u300_pmx_get_func_name,
1011 .get_function_groups = u300_pmx_get_groups, 1011 .get_function_groups = u300_pmx_get_groups,
1012 .enable = u300_pmx_enable, 1012 .enable = u300_pmx_enable,
1013 .disable = u300_pmx_disable, 1013 .disable = u300_pmx_disable,
1014 }; 1014 };
1015 1015
1016 /* 1016 /*
1017 * GPIO ranges handled by the application-side COH901XXX GPIO controller 1017 * GPIO ranges handled by the application-side COH901XXX GPIO controller
1018 * Very many pins can be converted into GPIO pins, but we only list those 1018 * Very many pins can be converted into GPIO pins, but we only list those
1019 * that are useful in practice to cut down on tables. 1019 * that are useful in practice to cut down on tables.
1020 */ 1020 */
1021 #define U300_GPIO_RANGE(a, b, c) { .name = "COH901XXX", .id = a, .base= a, \ 1021 #define U300_GPIO_RANGE(a, b, c) { .name = "COH901XXX", .id = a, .base= a, \
1022 .pin_base = b, .npins = c } 1022 .pin_base = b, .npins = c }
1023 1023
1024 static struct pinctrl_gpio_range u300_gpio_ranges[] = { 1024 static struct pinctrl_gpio_range u300_gpio_ranges[] = {
1025 U300_GPIO_RANGE(10, 426, 1), 1025 U300_GPIO_RANGE(10, 426, 1),
1026 U300_GPIO_RANGE(11, 180, 1), 1026 U300_GPIO_RANGE(11, 180, 1),
1027 U300_GPIO_RANGE(12, 165, 1), /* MS/MMC card insertion */ 1027 U300_GPIO_RANGE(12, 165, 1), /* MS/MMC card insertion */
1028 U300_GPIO_RANGE(13, 179, 1), 1028 U300_GPIO_RANGE(13, 179, 1),
1029 U300_GPIO_RANGE(14, 178, 1), 1029 U300_GPIO_RANGE(14, 178, 1),
1030 U300_GPIO_RANGE(16, 194, 1), 1030 U300_GPIO_RANGE(16, 194, 1),
1031 U300_GPIO_RANGE(17, 193, 1), 1031 U300_GPIO_RANGE(17, 193, 1),
1032 U300_GPIO_RANGE(18, 192, 1), 1032 U300_GPIO_RANGE(18, 192, 1),
1033 U300_GPIO_RANGE(19, 191, 1), 1033 U300_GPIO_RANGE(19, 191, 1),
1034 U300_GPIO_RANGE(20, 186, 1), 1034 U300_GPIO_RANGE(20, 186, 1),
1035 U300_GPIO_RANGE(21, 185, 1), 1035 U300_GPIO_RANGE(21, 185, 1),
1036 U300_GPIO_RANGE(22, 184, 1), 1036 U300_GPIO_RANGE(22, 184, 1),
1037 U300_GPIO_RANGE(23, 183, 1), 1037 U300_GPIO_RANGE(23, 183, 1),
1038 U300_GPIO_RANGE(24, 182, 1), 1038 U300_GPIO_RANGE(24, 182, 1),
1039 U300_GPIO_RANGE(25, 181, 1), 1039 U300_GPIO_RANGE(25, 181, 1),
1040 }; 1040 };
1041 1041
1042 static struct pinctrl_gpio_range *u300_match_gpio_range(unsigned pin) 1042 static struct pinctrl_gpio_range *u300_match_gpio_range(unsigned pin)
1043 { 1043 {
1044 int i; 1044 int i;
1045 1045
1046 for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++) { 1046 for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++) {
1047 struct pinctrl_gpio_range *range; 1047 struct pinctrl_gpio_range *range;
1048 1048
1049 range = &u300_gpio_ranges[i]; 1049 range = &u300_gpio_ranges[i];
1050 if (pin >= range->pin_base && 1050 if (pin >= range->pin_base &&
1051 pin <= (range->pin_base + range->npins - 1)) 1051 pin <= (range->pin_base + range->npins - 1))
1052 return range; 1052 return range;
1053 } 1053 }
1054 return NULL; 1054 return NULL;
1055 } 1055 }
1056 1056
1057 int u300_pin_config_get(struct pinctrl_dev *pctldev, 1057 int u300_pin_config_get(struct pinctrl_dev *pctldev,
1058 unsigned pin, 1058 unsigned pin,
1059 unsigned long *config) 1059 unsigned long *config)
1060 { 1060 {
1061 struct pinctrl_gpio_range *range = u300_match_gpio_range(pin); 1061 struct pinctrl_gpio_range *range = u300_match_gpio_range(pin);
1062 1062
1063 /* We get config for those pins we CAN get it for and that's it */ 1063 /* We get config for those pins we CAN get it for and that's it */
1064 if (!range) 1064 if (!range)
1065 return -ENOTSUPP; 1065 return -ENOTSUPP;
1066 1066
1067 return u300_gpio_config_get(range->gc, 1067 return u300_gpio_config_get(range->gc,
1068 (pin - range->pin_base + range->base), 1068 (pin - range->pin_base + range->base),
1069 config); 1069 config);
1070 } 1070 }
1071 1071
1072 int u300_pin_config_set(struct pinctrl_dev *pctldev, 1072 int u300_pin_config_set(struct pinctrl_dev *pctldev,
1073 unsigned pin, 1073 unsigned pin,
1074 unsigned long config) 1074 unsigned long config)
1075 { 1075 {
1076 struct pinctrl_gpio_range *range = u300_match_gpio_range(pin); 1076 struct pinctrl_gpio_range *range = u300_match_gpio_range(pin);
1077 int ret; 1077 int ret;
1078 1078
1079 if (!range) 1079 if (!range)
1080 return -EINVAL; 1080 return -EINVAL;
1081 1081
1082 /* Note: none of these configurations take any argument */ 1082 /* Note: none of these configurations take any argument */
1083 ret = u300_gpio_config_set(range->gc, 1083 ret = u300_gpio_config_set(range->gc,
1084 (pin - range->pin_base + range->base), 1084 (pin - range->pin_base + range->base),
1085 pinconf_to_config_param(config)); 1085 pinconf_to_config_param(config));
1086 if (ret) 1086 if (ret)
1087 return ret; 1087 return ret;
1088 1088
1089 return 0; 1089 return 0;
1090 } 1090 }
1091 1091
1092 static struct pinconf_ops u300_pconf_ops = { 1092 static struct pinconf_ops u300_pconf_ops = {
1093 .is_generic = true, 1093 .is_generic = true,
1094 .pin_config_get = u300_pin_config_get, 1094 .pin_config_get = u300_pin_config_get,
1095 .pin_config_set = u300_pin_config_set, 1095 .pin_config_set = u300_pin_config_set,
1096 }; 1096 };
1097 1097
1098 static struct pinctrl_desc u300_pmx_desc = { 1098 static struct pinctrl_desc u300_pmx_desc = {
1099 .name = DRIVER_NAME, 1099 .name = DRIVER_NAME,
1100 .pins = u300_pads, 1100 .pins = u300_pads,
1101 .npins = ARRAY_SIZE(u300_pads), 1101 .npins = ARRAY_SIZE(u300_pads),
1102 .pctlops = &u300_pctrl_ops, 1102 .pctlops = &u300_pctrl_ops,
1103 .pmxops = &u300_pmx_ops, 1103 .pmxops = &u300_pmx_ops,
1104 .confops = &u300_pconf_ops, 1104 .confops = &u300_pconf_ops,
1105 .owner = THIS_MODULE, 1105 .owner = THIS_MODULE,
1106 }; 1106 };
1107 1107
1108 static int __devinit u300_pmx_probe(struct platform_device *pdev) 1108 static int __devinit u300_pmx_probe(struct platform_device *pdev)
1109 { 1109 {
1110 struct u300_pmx *upmx; 1110 struct u300_pmx *upmx;
1111 struct resource *res; 1111 struct resource *res;
1112 struct gpio_chip *gpio_chip = dev_get_platdata(&pdev->dev); 1112 struct gpio_chip *gpio_chip = dev_get_platdata(&pdev->dev);
1113 int ret; 1113 int ret;
1114 int i; 1114 int i;
1115 1115
1116 /* Create state holders etc for this driver */ 1116 /* Create state holders etc for this driver */
1117 upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL); 1117 upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
1118 if (!upmx) 1118 if (!upmx)
1119 return -ENOMEM; 1119 return -ENOMEM;
1120 1120
1121 upmx->dev = &pdev->dev; 1121 upmx->dev = &pdev->dev;
1122 1122
1123 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1123 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1124 if (!res) 1124 if (!res)
1125 return -ENOENT; 1125 return -ENOENT;
1126 upmx->phybase = res->start; 1126 upmx->phybase = res->start;
1127 upmx->physize = resource_size(res); 1127 upmx->physize = resource_size(res);
1128 1128
1129 if (request_mem_region(upmx->phybase, upmx->physize, 1129 if (request_mem_region(upmx->phybase, upmx->physize,
1130 DRIVER_NAME) == NULL) { 1130 DRIVER_NAME) == NULL) {
1131 ret = -ENOMEM; 1131 ret = -ENOMEM;
1132 goto out_no_memregion; 1132 goto out_no_memregion;
1133 } 1133 }
1134 1134
1135 upmx->virtbase = ioremap(upmx->phybase, upmx->physize); 1135 upmx->virtbase = ioremap(upmx->phybase, upmx->physize);
1136 if (!upmx->virtbase) { 1136 if (!upmx->virtbase) {
1137 ret = -ENOMEM; 1137 ret = -ENOMEM;
1138 goto out_no_remap; 1138 goto out_no_remap;
1139 } 1139 }
1140 1140
1141 upmx->pctl = pinctrl_register(&u300_pmx_desc, &pdev->dev, upmx); 1141 upmx->pctl = pinctrl_register(&u300_pmx_desc, &pdev->dev, upmx);
1142 if (!upmx->pctl) { 1142 if (!upmx->pctl) {
1143 dev_err(&pdev->dev, "could not register U300 pinmux driver\n"); 1143 dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
1144 ret = -EINVAL; 1144 ret = -EINVAL;
1145 goto out_no_pmx; 1145 goto out_no_pmx;
1146 } 1146 }
1147 1147
1148 /* We will handle a range of GPIO pins */ 1148 /* We will handle a range of GPIO pins */
1149 for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++) { 1149 for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++) {
1150 u300_gpio_ranges[i].gc = gpio_chip; 1150 u300_gpio_ranges[i].gc = gpio_chip;
1151 pinctrl_add_gpio_range(upmx->pctl, &u300_gpio_ranges[i]); 1151 pinctrl_add_gpio_range(upmx->pctl, &u300_gpio_ranges[i]);
1152 } 1152 }
1153 1153
1154 platform_set_drvdata(pdev, upmx); 1154 platform_set_drvdata(pdev, upmx);
1155 1155
1156 dev_info(&pdev->dev, "initialized U300 pin control driver\n"); 1156 dev_info(&pdev->dev, "initialized U300 pin control driver\n");
1157 1157
1158 return 0; 1158 return 0;
1159 1159
1160 out_no_pmx: 1160 out_no_pmx:
1161 iounmap(upmx->virtbase); 1161 iounmap(upmx->virtbase);
1162 out_no_remap: 1162 out_no_remap:
1163 platform_set_drvdata(pdev, NULL); 1163 platform_set_drvdata(pdev, NULL);
1164 out_no_memregion: 1164 out_no_memregion:
1165 release_mem_region(upmx->phybase, upmx->physize); 1165 release_mem_region(upmx->phybase, upmx->physize);
1166 return ret; 1166 return ret;
1167 } 1167 }
1168 1168
1169 static int __devexit u300_pmx_remove(struct platform_device *pdev) 1169 static int u300_pmx_remove(struct platform_device *pdev)
1170 { 1170 {
1171 struct u300_pmx *upmx = platform_get_drvdata(pdev); 1171 struct u300_pmx *upmx = platform_get_drvdata(pdev);
1172 1172
1173 pinctrl_unregister(upmx->pctl); 1173 pinctrl_unregister(upmx->pctl);
1174 iounmap(upmx->virtbase); 1174 iounmap(upmx->virtbase);
1175 release_mem_region(upmx->phybase, upmx->physize); 1175 release_mem_region(upmx->phybase, upmx->physize);
1176 platform_set_drvdata(pdev, NULL); 1176 platform_set_drvdata(pdev, NULL);
1177 1177
1178 return 0; 1178 return 0;
1179 } 1179 }
1180 1180
1181 static struct platform_driver u300_pmx_driver = { 1181 static struct platform_driver u300_pmx_driver = {
1182 .driver = { 1182 .driver = {
1183 .name = DRIVER_NAME, 1183 .name = DRIVER_NAME,
1184 .owner = THIS_MODULE, 1184 .owner = THIS_MODULE,
1185 }, 1185 },
1186 .probe = u300_pmx_probe, 1186 .probe = u300_pmx_probe,
1187 .remove = u300_pmx_remove, 1187 .remove = u300_pmx_remove,
1188 }; 1188 };
1189 1189
1190 static int __init u300_pmx_init(void) 1190 static int __init u300_pmx_init(void)
1191 { 1191 {
1192 return platform_driver_register(&u300_pmx_driver); 1192 return platform_driver_register(&u300_pmx_driver);
1193 } 1193 }
1194 arch_initcall(u300_pmx_init); 1194 arch_initcall(u300_pmx_init);
1195 1195
1196 static void __exit u300_pmx_exit(void) 1196 static void __exit u300_pmx_exit(void)
1197 { 1197 {
1198 platform_driver_unregister(&u300_pmx_driver); 1198 platform_driver_unregister(&u300_pmx_driver);
1199 } 1199 }
1200 module_exit(u300_pmx_exit); 1200 module_exit(u300_pmx_exit);
1201 1201
1202 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 1202 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1203 MODULE_DESCRIPTION("U300 pin control driver"); 1203 MODULE_DESCRIPTION("U300 pin control driver");
1204 MODULE_LICENSE("GPL v2"); 1204 MODULE_LICENSE("GPL v2");
1205 1205
drivers/pinctrl/spear/pinctrl-spear.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Driver for the ST Microelectronics SPEAr pinmux 2 * Driver for the ST Microelectronics SPEAr pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * Inspired from: 7 * Inspired from:
8 * - U300 Pinctl drivers 8 * - U300 Pinctl drivers
9 * - Tegra Pinctl drivers 9 * - Tegra Pinctl drivers
10 * 10 *
11 * This file is licensed under the terms of the GNU General Public 11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any 12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 */ 14 */
15 15
16 #include <linux/err.h> 16 #include <linux/err.h>
17 #include <linux/io.h> 17 #include <linux/io.h>
18 #include <linux/module.h> 18 #include <linux/module.h>
19 #include <linux/of.h> 19 #include <linux/of.h>
20 #include <linux/of_address.h> 20 #include <linux/of_address.h>
21 #include <linux/pinctrl/machine.h> 21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h> 23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/platform_device.h> 24 #include <linux/platform_device.h>
25 #include <linux/slab.h> 25 #include <linux/slab.h>
26 26
27 #include "pinctrl-spear.h" 27 #include "pinctrl-spear.h"
28 28
29 #define DRIVER_NAME "spear-pinmux" 29 #define DRIVER_NAME "spear-pinmux"
30 30
31 static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) 31 static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
32 { 32 {
33 return readl_relaxed(pmx->vbase + reg); 33 return readl_relaxed(pmx->vbase + reg);
34 } 34 }
35 35
36 static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) 36 static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
37 { 37 {
38 writel_relaxed(val, pmx->vbase + reg); 38 writel_relaxed(val, pmx->vbase + reg);
39 } 39 }
40 40
41 static int set_mode(struct spear_pmx *pmx, int mode) 41 static int set_mode(struct spear_pmx *pmx, int mode)
42 { 42 {
43 struct spear_pmx_mode *pmx_mode = NULL; 43 struct spear_pmx_mode *pmx_mode = NULL;
44 int i; 44 int i;
45 u32 val; 45 u32 val;
46 46
47 if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes) 47 if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes)
48 return -EINVAL; 48 return -EINVAL;
49 49
50 for (i = 0; i < pmx->machdata->npmx_modes; i++) { 50 for (i = 0; i < pmx->machdata->npmx_modes; i++) {
51 if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) { 51 if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) {
52 pmx_mode = pmx->machdata->pmx_modes[i]; 52 pmx_mode = pmx->machdata->pmx_modes[i];
53 break; 53 break;
54 } 54 }
55 } 55 }
56 56
57 if (!pmx_mode) 57 if (!pmx_mode)
58 return -EINVAL; 58 return -EINVAL;
59 59
60 val = pmx_readl(pmx, pmx_mode->reg); 60 val = pmx_readl(pmx, pmx_mode->reg);
61 val &= ~pmx_mode->mask; 61 val &= ~pmx_mode->mask;
62 val |= pmx_mode->val; 62 val |= pmx_mode->val;
63 pmx_writel(pmx, val, pmx_mode->reg); 63 pmx_writel(pmx, val, pmx_mode->reg);
64 64
65 pmx->machdata->mode = pmx_mode->mode; 65 pmx->machdata->mode = pmx_mode->mode;
66 dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n", 66 dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n",
67 pmx_mode->name ? pmx_mode->name : "no_name", 67 pmx_mode->name ? pmx_mode->name : "no_name",
68 pmx_mode->reg); 68 pmx_mode->reg);
69 69
70 return 0; 70 return 0;
71 } 71 }
72 72
73 void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg) 73 void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
74 { 74 {
75 struct spear_pingroup *pgroup; 75 struct spear_pingroup *pgroup;
76 struct spear_modemux *modemux; 76 struct spear_modemux *modemux;
77 int i, j, group; 77 int i, j, group;
78 78
79 for (group = 0; group < machdata->ngroups; group++) { 79 for (group = 0; group < machdata->ngroups; group++) {
80 pgroup = machdata->groups[group]; 80 pgroup = machdata->groups[group];
81 81
82 for (i = 0; i < pgroup->nmodemuxs; i++) { 82 for (i = 0; i < pgroup->nmodemuxs; i++) {
83 modemux = &pgroup->modemuxs[i]; 83 modemux = &pgroup->modemuxs[i];
84 84
85 for (j = 0; j < modemux->nmuxregs; j++) 85 for (j = 0; j < modemux->nmuxregs; j++)
86 if (modemux->muxregs[j].reg == 0xFFFF) 86 if (modemux->muxregs[j].reg == 0xFFFF)
87 modemux->muxregs[j].reg = reg; 87 modemux->muxregs[j].reg = reg;
88 } 88 }
89 } 89 }
90 } 90 }
91 91
92 static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev) 92 static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev)
93 { 93 {
94 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 94 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
95 95
96 return pmx->machdata->ngroups; 96 return pmx->machdata->ngroups;
97 } 97 }
98 98
99 static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 99 static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
100 unsigned group) 100 unsigned group)
101 { 101 {
102 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 102 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
103 103
104 return pmx->machdata->groups[group]->name; 104 return pmx->machdata->groups[group]->name;
105 } 105 }
106 106
107 static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 107 static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
108 unsigned group, const unsigned **pins, unsigned *num_pins) 108 unsigned group, const unsigned **pins, unsigned *num_pins)
109 { 109 {
110 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 110 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
111 111
112 *pins = pmx->machdata->groups[group]->pins; 112 *pins = pmx->machdata->groups[group]->pins;
113 *num_pins = pmx->machdata->groups[group]->npins; 113 *num_pins = pmx->machdata->groups[group]->npins;
114 114
115 return 0; 115 return 0;
116 } 116 }
117 117
118 static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 118 static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
119 struct seq_file *s, unsigned offset) 119 struct seq_file *s, unsigned offset)
120 { 120 {
121 seq_printf(s, " " DRIVER_NAME); 121 seq_printf(s, " " DRIVER_NAME);
122 } 122 }
123 123
124 int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 124 int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
125 struct device_node *np_config, 125 struct device_node *np_config,
126 struct pinctrl_map **map, unsigned *num_maps) 126 struct pinctrl_map **map, unsigned *num_maps)
127 { 127 {
128 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 128 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
129 struct device_node *np; 129 struct device_node *np;
130 struct property *prop; 130 struct property *prop;
131 const char *function, *group; 131 const char *function, *group;
132 int ret, index = 0, count = 0; 132 int ret, index = 0, count = 0;
133 133
134 /* calculate number of maps required */ 134 /* calculate number of maps required */
135 for_each_child_of_node(np_config, np) { 135 for_each_child_of_node(np_config, np) {
136 ret = of_property_read_string(np, "st,function", &function); 136 ret = of_property_read_string(np, "st,function", &function);
137 if (ret < 0) 137 if (ret < 0)
138 return ret; 138 return ret;
139 139
140 ret = of_property_count_strings(np, "st,pins"); 140 ret = of_property_count_strings(np, "st,pins");
141 if (ret < 0) 141 if (ret < 0)
142 return ret; 142 return ret;
143 143
144 count += ret; 144 count += ret;
145 } 145 }
146 146
147 if (!count) { 147 if (!count) {
148 dev_err(pmx->dev, "No child nodes passed via DT\n"); 148 dev_err(pmx->dev, "No child nodes passed via DT\n");
149 return -ENODEV; 149 return -ENODEV;
150 } 150 }
151 151
152 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); 152 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
153 if (!*map) 153 if (!*map)
154 return -ENOMEM; 154 return -ENOMEM;
155 155
156 for_each_child_of_node(np_config, np) { 156 for_each_child_of_node(np_config, np) {
157 of_property_read_string(np, "st,function", &function); 157 of_property_read_string(np, "st,function", &function);
158 of_property_for_each_string(np, "st,pins", prop, group) { 158 of_property_for_each_string(np, "st,pins", prop, group) {
159 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; 159 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
160 (*map)[index].data.mux.group = group; 160 (*map)[index].data.mux.group = group;
161 (*map)[index].data.mux.function = function; 161 (*map)[index].data.mux.function = function;
162 index++; 162 index++;
163 } 163 }
164 } 164 }
165 165
166 *num_maps = count; 166 *num_maps = count;
167 167
168 return 0; 168 return 0;
169 } 169 }
170 170
171 void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, 171 void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
172 struct pinctrl_map *map, unsigned num_maps) 172 struct pinctrl_map *map, unsigned num_maps)
173 { 173 {
174 kfree(map); 174 kfree(map);
175 } 175 }
176 176
177 static struct pinctrl_ops spear_pinctrl_ops = { 177 static struct pinctrl_ops spear_pinctrl_ops = {
178 .get_groups_count = spear_pinctrl_get_groups_cnt, 178 .get_groups_count = spear_pinctrl_get_groups_cnt,
179 .get_group_name = spear_pinctrl_get_group_name, 179 .get_group_name = spear_pinctrl_get_group_name,
180 .get_group_pins = spear_pinctrl_get_group_pins, 180 .get_group_pins = spear_pinctrl_get_group_pins,
181 .pin_dbg_show = spear_pinctrl_pin_dbg_show, 181 .pin_dbg_show = spear_pinctrl_pin_dbg_show,
182 .dt_node_to_map = spear_pinctrl_dt_node_to_map, 182 .dt_node_to_map = spear_pinctrl_dt_node_to_map,
183 .dt_free_map = spear_pinctrl_dt_free_map, 183 .dt_free_map = spear_pinctrl_dt_free_map,
184 }; 184 };
185 185
186 static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) 186 static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
187 { 187 {
188 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 188 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
189 189
190 return pmx->machdata->nfunctions; 190 return pmx->machdata->nfunctions;
191 } 191 }
192 192
193 static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 193 static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
194 unsigned function) 194 unsigned function)
195 { 195 {
196 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 196 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
197 197
198 return pmx->machdata->functions[function]->name; 198 return pmx->machdata->functions[function]->name;
199 } 199 }
200 200
201 static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, 201 static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
202 unsigned function, const char *const **groups, 202 unsigned function, const char *const **groups,
203 unsigned * const ngroups) 203 unsigned * const ngroups)
204 { 204 {
205 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 205 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
206 206
207 *groups = pmx->machdata->functions[function]->groups; 207 *groups = pmx->machdata->functions[function]->groups;
208 *ngroups = pmx->machdata->functions[function]->ngroups; 208 *ngroups = pmx->machdata->functions[function]->ngroups;
209 209
210 return 0; 210 return 0;
211 } 211 }
212 212
213 static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev, 213 static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
214 unsigned function, unsigned group, bool enable) 214 unsigned function, unsigned group, bool enable)
215 { 215 {
216 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 216 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
217 const struct spear_pingroup *pgroup; 217 const struct spear_pingroup *pgroup;
218 const struct spear_modemux *modemux; 218 const struct spear_modemux *modemux;
219 struct spear_muxreg *muxreg; 219 struct spear_muxreg *muxreg;
220 u32 val, temp; 220 u32 val, temp;
221 int i, j; 221 int i, j;
222 bool found = false; 222 bool found = false;
223 223
224 pgroup = pmx->machdata->groups[group]; 224 pgroup = pmx->machdata->groups[group];
225 225
226 for (i = 0; i < pgroup->nmodemuxs; i++) { 226 for (i = 0; i < pgroup->nmodemuxs; i++) {
227 modemux = &pgroup->modemuxs[i]; 227 modemux = &pgroup->modemuxs[i];
228 228
229 /* SoC have any modes */ 229 /* SoC have any modes */
230 if (pmx->machdata->modes_supported) { 230 if (pmx->machdata->modes_supported) {
231 if (!(pmx->machdata->mode & modemux->modes)) 231 if (!(pmx->machdata->mode & modemux->modes))
232 continue; 232 continue;
233 } 233 }
234 234
235 found = true; 235 found = true;
236 for (j = 0; j < modemux->nmuxregs; j++) { 236 for (j = 0; j < modemux->nmuxregs; j++) {
237 muxreg = &modemux->muxregs[j]; 237 muxreg = &modemux->muxregs[j];
238 238
239 val = pmx_readl(pmx, muxreg->reg); 239 val = pmx_readl(pmx, muxreg->reg);
240 val &= ~muxreg->mask; 240 val &= ~muxreg->mask;
241 241
242 if (enable) 242 if (enable)
243 temp = muxreg->val; 243 temp = muxreg->val;
244 else 244 else
245 temp = ~muxreg->val; 245 temp = ~muxreg->val;
246 246
247 val |= muxreg->mask & temp; 247 val |= muxreg->mask & temp;
248 pmx_writel(pmx, val, muxreg->reg); 248 pmx_writel(pmx, val, muxreg->reg);
249 } 249 }
250 } 250 }
251 251
252 if (!found) { 252 if (!found) {
253 dev_err(pmx->dev, "pinmux group: %s not supported\n", 253 dev_err(pmx->dev, "pinmux group: %s not supported\n",
254 pgroup->name); 254 pgroup->name);
255 return -ENODEV; 255 return -ENODEV;
256 } 256 }
257 257
258 return 0; 258 return 0;
259 } 259 }
260 260
261 static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, 261 static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
262 unsigned group) 262 unsigned group)
263 { 263 {
264 return spear_pinctrl_endisable(pctldev, function, group, true); 264 return spear_pinctrl_endisable(pctldev, function, group, true);
265 } 265 }
266 266
267 static void spear_pinctrl_disable(struct pinctrl_dev *pctldev, 267 static void spear_pinctrl_disable(struct pinctrl_dev *pctldev,
268 unsigned function, unsigned group) 268 unsigned function, unsigned group)
269 { 269 {
270 spear_pinctrl_endisable(pctldev, function, group, false); 270 spear_pinctrl_endisable(pctldev, function, group, false);
271 } 271 }
272 272
273 static struct pinmux_ops spear_pinmux_ops = { 273 static struct pinmux_ops spear_pinmux_ops = {
274 .get_functions_count = spear_pinctrl_get_funcs_count, 274 .get_functions_count = spear_pinctrl_get_funcs_count,
275 .get_function_name = spear_pinctrl_get_func_name, 275 .get_function_name = spear_pinctrl_get_func_name,
276 .get_function_groups = spear_pinctrl_get_func_groups, 276 .get_function_groups = spear_pinctrl_get_func_groups,
277 .enable = spear_pinctrl_enable, 277 .enable = spear_pinctrl_enable,
278 .disable = spear_pinctrl_disable, 278 .disable = spear_pinctrl_disable,
279 }; 279 };
280 280
281 static struct pinctrl_desc spear_pinctrl_desc = { 281 static struct pinctrl_desc spear_pinctrl_desc = {
282 .name = DRIVER_NAME, 282 .name = DRIVER_NAME,
283 .pctlops = &spear_pinctrl_ops, 283 .pctlops = &spear_pinctrl_ops,
284 .pmxops = &spear_pinmux_ops, 284 .pmxops = &spear_pinmux_ops,
285 .owner = THIS_MODULE, 285 .owner = THIS_MODULE,
286 }; 286 };
287 287
288 int __devinit spear_pinctrl_probe(struct platform_device *pdev, 288 int __devinit spear_pinctrl_probe(struct platform_device *pdev,
289 struct spear_pinctrl_machdata *machdata) 289 struct spear_pinctrl_machdata *machdata)
290 { 290 {
291 struct device_node *np = pdev->dev.of_node; 291 struct device_node *np = pdev->dev.of_node;
292 struct resource *res; 292 struct resource *res;
293 struct spear_pmx *pmx; 293 struct spear_pmx *pmx;
294 294
295 if (!machdata) 295 if (!machdata)
296 return -ENODEV; 296 return -ENODEV;
297 297
298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
299 if (!res) 299 if (!res)
300 return -EINVAL; 300 return -EINVAL;
301 301
302 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 302 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
303 if (!pmx) { 303 if (!pmx) {
304 dev_err(&pdev->dev, "Can't alloc spear_pmx\n"); 304 dev_err(&pdev->dev, "Can't alloc spear_pmx\n");
305 return -ENOMEM; 305 return -ENOMEM;
306 } 306 }
307 307
308 pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 308 pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
309 if (!pmx->vbase) { 309 if (!pmx->vbase) {
310 dev_err(&pdev->dev, "Couldn't ioremap at index 0\n"); 310 dev_err(&pdev->dev, "Couldn't ioremap at index 0\n");
311 return -ENODEV; 311 return -ENODEV;
312 } 312 }
313 313
314 pmx->dev = &pdev->dev; 314 pmx->dev = &pdev->dev;
315 pmx->machdata = machdata; 315 pmx->machdata = machdata;
316 316
317 /* configure mode, if supported by SoC */ 317 /* configure mode, if supported by SoC */
318 if (machdata->modes_supported) { 318 if (machdata->modes_supported) {
319 int mode = 0; 319 int mode = 0;
320 320
321 if (of_property_read_u32(np, "st,pinmux-mode", &mode)) { 321 if (of_property_read_u32(np, "st,pinmux-mode", &mode)) {
322 dev_err(&pdev->dev, "OF: pinmux mode not passed\n"); 322 dev_err(&pdev->dev, "OF: pinmux mode not passed\n");
323 return -EINVAL; 323 return -EINVAL;
324 } 324 }
325 325
326 if (set_mode(pmx, mode)) { 326 if (set_mode(pmx, mode)) {
327 dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n", 327 dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n",
328 mode); 328 mode);
329 return -EINVAL; 329 return -EINVAL;
330 } 330 }
331 } 331 }
332 332
333 platform_set_drvdata(pdev, pmx); 333 platform_set_drvdata(pdev, pmx);
334 334
335 spear_pinctrl_desc.pins = machdata->pins; 335 spear_pinctrl_desc.pins = machdata->pins;
336 spear_pinctrl_desc.npins = machdata->npins; 336 spear_pinctrl_desc.npins = machdata->npins;
337 337
338 pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx); 338 pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx);
339 if (!pmx->pctl) { 339 if (!pmx->pctl) {
340 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 340 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
341 return -ENODEV; 341 return -ENODEV;
342 } 342 }
343 343
344 return 0; 344 return 0;
345 } 345 }
346 346
347 int __devexit spear_pinctrl_remove(struct platform_device *pdev) 347 int spear_pinctrl_remove(struct platform_device *pdev)
348 { 348 {
349 struct spear_pmx *pmx = platform_get_drvdata(pdev); 349 struct spear_pmx *pmx = platform_get_drvdata(pdev);
350 350
351 pinctrl_unregister(pmx->pctl); 351 pinctrl_unregister(pmx->pctl);
352 352
353 return 0; 353 return 0;
354 } 354 }
355 355
drivers/pinctrl/spear/pinctrl-spear.h
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Driver header file for the ST Microelectronics SPEAr pinmux 2 * Driver header file for the ST Microelectronics SPEAr pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #ifndef __PINMUX_SPEAR_H__ 12 #ifndef __PINMUX_SPEAR_H__
13 #define __PINMUX_SPEAR_H__ 13 #define __PINMUX_SPEAR_H__
14 14
15 #include <linux/pinctrl/pinctrl.h> 15 #include <linux/pinctrl/pinctrl.h>
16 #include <linux/types.h> 16 #include <linux/types.h>
17 17
18 struct platform_device; 18 struct platform_device;
19 struct device; 19 struct device;
20 20
21 /** 21 /**
22 * struct spear_pmx_mode - SPEAr pmx mode 22 * struct spear_pmx_mode - SPEAr pmx mode
23 * @name: name of pmx mode 23 * @name: name of pmx mode
24 * @mode: mode id 24 * @mode: mode id
25 * @reg: register for configuring this mode 25 * @reg: register for configuring this mode
26 * @mask: mask of this mode in reg 26 * @mask: mask of this mode in reg
27 * @val: val to be configured at reg after doing (val & mask) 27 * @val: val to be configured at reg after doing (val & mask)
28 */ 28 */
29 struct spear_pmx_mode { 29 struct spear_pmx_mode {
30 const char *const name; 30 const char *const name;
31 u16 mode; 31 u16 mode;
32 u16 reg; 32 u16 reg;
33 u16 mask; 33 u16 mask;
34 u32 val; 34 u32 val;
35 }; 35 };
36 36
37 /** 37 /**
38 * struct spear_muxreg - SPEAr mux reg configuration 38 * struct spear_muxreg - SPEAr mux reg configuration
39 * @reg: register offset 39 * @reg: register offset
40 * @mask: mask bits 40 * @mask: mask bits
41 * @val: val to be written on mask bits 41 * @val: val to be written on mask bits
42 */ 42 */
43 struct spear_muxreg { 43 struct spear_muxreg {
44 u16 reg; 44 u16 reg;
45 u32 mask; 45 u32 mask;
46 u32 val; 46 u32 val;
47 }; 47 };
48 48
49 /** 49 /**
50 * struct spear_modemux - SPEAr mode mux configuration 50 * struct spear_modemux - SPEAr mode mux configuration
51 * @modes: mode ids supported by this group of muxregs 51 * @modes: mode ids supported by this group of muxregs
52 * @nmuxregs: number of muxreg configurations to be done for modes 52 * @nmuxregs: number of muxreg configurations to be done for modes
53 * @muxregs: array of muxreg configurations to be done for modes 53 * @muxregs: array of muxreg configurations to be done for modes
54 */ 54 */
55 struct spear_modemux { 55 struct spear_modemux {
56 u16 modes; 56 u16 modes;
57 u8 nmuxregs; 57 u8 nmuxregs;
58 struct spear_muxreg *muxregs; 58 struct spear_muxreg *muxregs;
59 }; 59 };
60 60
61 /** 61 /**
62 * struct spear_pingroup - SPEAr pin group configurations 62 * struct spear_pingroup - SPEAr pin group configurations
63 * @name: name of pin group 63 * @name: name of pin group
64 * @pins: array containing pin numbers 64 * @pins: array containing pin numbers
65 * @npins: size of pins array 65 * @npins: size of pins array
66 * @modemuxs: array of modemux configurations for this pin group 66 * @modemuxs: array of modemux configurations for this pin group
67 * @nmodemuxs: size of array modemuxs 67 * @nmodemuxs: size of array modemuxs
68 * 68 *
69 * A representation of a group of pins in the SPEAr pin controller. Each group 69 * A representation of a group of pins in the SPEAr pin controller. Each group
70 * allows some parameter or parameters to be configured. 70 * allows some parameter or parameters to be configured.
71 */ 71 */
72 struct spear_pingroup { 72 struct spear_pingroup {
73 const char *name; 73 const char *name;
74 const unsigned *pins; 74 const unsigned *pins;
75 unsigned npins; 75 unsigned npins;
76 struct spear_modemux *modemuxs; 76 struct spear_modemux *modemuxs;
77 unsigned nmodemuxs; 77 unsigned nmodemuxs;
78 }; 78 };
79 79
80 /** 80 /**
81 * struct spear_function - SPEAr pinctrl mux function 81 * struct spear_function - SPEAr pinctrl mux function
82 * @name: The name of the function, exported to pinctrl core. 82 * @name: The name of the function, exported to pinctrl core.
83 * @groups: An array of pin groups that may select this function. 83 * @groups: An array of pin groups that may select this function.
84 * @ngroups: The number of entries in @groups. 84 * @ngroups: The number of entries in @groups.
85 */ 85 */
86 struct spear_function { 86 struct spear_function {
87 const char *name; 87 const char *name;
88 const char *const *groups; 88 const char *const *groups;
89 unsigned ngroups; 89 unsigned ngroups;
90 }; 90 };
91 91
92 /** 92 /**
93 * struct spear_pinctrl_machdata - SPEAr pin controller machine driver 93 * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
94 * configuration 94 * configuration
95 * @pins: An array describing all pins the pin controller affects. 95 * @pins: An array describing all pins the pin controller affects.
96 * All pins which are also GPIOs must be listed first within the *array, 96 * All pins which are also GPIOs must be listed first within the *array,
97 * and be numbered identically to the GPIO controller's *numbering. 97 * and be numbered identically to the GPIO controller's *numbering.
98 * @npins: The numbmer of entries in @pins. 98 * @npins: The numbmer of entries in @pins.
99 * @functions: An array describing all mux functions the SoC supports. 99 * @functions: An array describing all mux functions the SoC supports.
100 * @nfunctions: The numbmer of entries in @functions. 100 * @nfunctions: The numbmer of entries in @functions.
101 * @groups: An array describing all pin groups the pin SoC supports. 101 * @groups: An array describing all pin groups the pin SoC supports.
102 * @ngroups: The numbmer of entries in @groups. 102 * @ngroups: The numbmer of entries in @groups.
103 * 103 *
104 * @modes_supported: Does SoC support modes 104 * @modes_supported: Does SoC support modes
105 * @mode: mode configured from probe 105 * @mode: mode configured from probe
106 * @pmx_modes: array of modes supported by SoC 106 * @pmx_modes: array of modes supported by SoC
107 * @npmx_modes: number of entries in pmx_modes. 107 * @npmx_modes: number of entries in pmx_modes.
108 */ 108 */
109 struct spear_pinctrl_machdata { 109 struct spear_pinctrl_machdata {
110 const struct pinctrl_pin_desc *pins; 110 const struct pinctrl_pin_desc *pins;
111 unsigned npins; 111 unsigned npins;
112 struct spear_function **functions; 112 struct spear_function **functions;
113 unsigned nfunctions; 113 unsigned nfunctions;
114 struct spear_pingroup **groups; 114 struct spear_pingroup **groups;
115 unsigned ngroups; 115 unsigned ngroups;
116 116
117 bool modes_supported; 117 bool modes_supported;
118 u16 mode; 118 u16 mode;
119 struct spear_pmx_mode **pmx_modes; 119 struct spear_pmx_mode **pmx_modes;
120 unsigned npmx_modes; 120 unsigned npmx_modes;
121 }; 121 };
122 122
123 /** 123 /**
124 * struct spear_pmx - SPEAr pinctrl mux 124 * struct spear_pmx - SPEAr pinctrl mux
125 * @dev: pointer to struct dev of platform_device registered 125 * @dev: pointer to struct dev of platform_device registered
126 * @pctl: pointer to struct pinctrl_dev 126 * @pctl: pointer to struct pinctrl_dev
127 * @machdata: pointer to SoC or machine specific structure 127 * @machdata: pointer to SoC or machine specific structure
128 * @vbase: virtual base address of pinmux controller 128 * @vbase: virtual base address of pinmux controller
129 */ 129 */
130 struct spear_pmx { 130 struct spear_pmx {
131 struct device *dev; 131 struct device *dev;
132 struct pinctrl_dev *pctl; 132 struct pinctrl_dev *pctl;
133 struct spear_pinctrl_machdata *machdata; 133 struct spear_pinctrl_machdata *machdata;
134 void __iomem *vbase; 134 void __iomem *vbase;
135 }; 135 };
136 136
137 /* exported routines */ 137 /* exported routines */
138 void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); 138 void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
139 int __devinit spear_pinctrl_probe(struct platform_device *pdev, 139 int __devinit spear_pinctrl_probe(struct platform_device *pdev,
140 struct spear_pinctrl_machdata *machdata); 140 struct spear_pinctrl_machdata *machdata);
141 int __devexit spear_pinctrl_remove(struct platform_device *pdev); 141 int spear_pinctrl_remove(struct platform_device *pdev);
142 142
143 #define SPEAR_PIN_0_TO_101 \ 143 #define SPEAR_PIN_0_TO_101 \
144 PINCTRL_PIN(0, "PLGPIO0"), \ 144 PINCTRL_PIN(0, "PLGPIO0"), \
145 PINCTRL_PIN(1, "PLGPIO1"), \ 145 PINCTRL_PIN(1, "PLGPIO1"), \
146 PINCTRL_PIN(2, "PLGPIO2"), \ 146 PINCTRL_PIN(2, "PLGPIO2"), \
147 PINCTRL_PIN(3, "PLGPIO3"), \ 147 PINCTRL_PIN(3, "PLGPIO3"), \
148 PINCTRL_PIN(4, "PLGPIO4"), \ 148 PINCTRL_PIN(4, "PLGPIO4"), \
149 PINCTRL_PIN(5, "PLGPIO5"), \ 149 PINCTRL_PIN(5, "PLGPIO5"), \
150 PINCTRL_PIN(6, "PLGPIO6"), \ 150 PINCTRL_PIN(6, "PLGPIO6"), \
151 PINCTRL_PIN(7, "PLGPIO7"), \ 151 PINCTRL_PIN(7, "PLGPIO7"), \
152 PINCTRL_PIN(8, "PLGPIO8"), \ 152 PINCTRL_PIN(8, "PLGPIO8"), \
153 PINCTRL_PIN(9, "PLGPIO9"), \ 153 PINCTRL_PIN(9, "PLGPIO9"), \
154 PINCTRL_PIN(10, "PLGPIO10"), \ 154 PINCTRL_PIN(10, "PLGPIO10"), \
155 PINCTRL_PIN(11, "PLGPIO11"), \ 155 PINCTRL_PIN(11, "PLGPIO11"), \
156 PINCTRL_PIN(12, "PLGPIO12"), \ 156 PINCTRL_PIN(12, "PLGPIO12"), \
157 PINCTRL_PIN(13, "PLGPIO13"), \ 157 PINCTRL_PIN(13, "PLGPIO13"), \
158 PINCTRL_PIN(14, "PLGPIO14"), \ 158 PINCTRL_PIN(14, "PLGPIO14"), \
159 PINCTRL_PIN(15, "PLGPIO15"), \ 159 PINCTRL_PIN(15, "PLGPIO15"), \
160 PINCTRL_PIN(16, "PLGPIO16"), \ 160 PINCTRL_PIN(16, "PLGPIO16"), \
161 PINCTRL_PIN(17, "PLGPIO17"), \ 161 PINCTRL_PIN(17, "PLGPIO17"), \
162 PINCTRL_PIN(18, "PLGPIO18"), \ 162 PINCTRL_PIN(18, "PLGPIO18"), \
163 PINCTRL_PIN(19, "PLGPIO19"), \ 163 PINCTRL_PIN(19, "PLGPIO19"), \
164 PINCTRL_PIN(20, "PLGPIO20"), \ 164 PINCTRL_PIN(20, "PLGPIO20"), \
165 PINCTRL_PIN(21, "PLGPIO21"), \ 165 PINCTRL_PIN(21, "PLGPIO21"), \
166 PINCTRL_PIN(22, "PLGPIO22"), \ 166 PINCTRL_PIN(22, "PLGPIO22"), \
167 PINCTRL_PIN(23, "PLGPIO23"), \ 167 PINCTRL_PIN(23, "PLGPIO23"), \
168 PINCTRL_PIN(24, "PLGPIO24"), \ 168 PINCTRL_PIN(24, "PLGPIO24"), \
169 PINCTRL_PIN(25, "PLGPIO25"), \ 169 PINCTRL_PIN(25, "PLGPIO25"), \
170 PINCTRL_PIN(26, "PLGPIO26"), \ 170 PINCTRL_PIN(26, "PLGPIO26"), \
171 PINCTRL_PIN(27, "PLGPIO27"), \ 171 PINCTRL_PIN(27, "PLGPIO27"), \
172 PINCTRL_PIN(28, "PLGPIO28"), \ 172 PINCTRL_PIN(28, "PLGPIO28"), \
173 PINCTRL_PIN(29, "PLGPIO29"), \ 173 PINCTRL_PIN(29, "PLGPIO29"), \
174 PINCTRL_PIN(30, "PLGPIO30"), \ 174 PINCTRL_PIN(30, "PLGPIO30"), \
175 PINCTRL_PIN(31, "PLGPIO31"), \ 175 PINCTRL_PIN(31, "PLGPIO31"), \
176 PINCTRL_PIN(32, "PLGPIO32"), \ 176 PINCTRL_PIN(32, "PLGPIO32"), \
177 PINCTRL_PIN(33, "PLGPIO33"), \ 177 PINCTRL_PIN(33, "PLGPIO33"), \
178 PINCTRL_PIN(34, "PLGPIO34"), \ 178 PINCTRL_PIN(34, "PLGPIO34"), \
179 PINCTRL_PIN(35, "PLGPIO35"), \ 179 PINCTRL_PIN(35, "PLGPIO35"), \
180 PINCTRL_PIN(36, "PLGPIO36"), \ 180 PINCTRL_PIN(36, "PLGPIO36"), \
181 PINCTRL_PIN(37, "PLGPIO37"), \ 181 PINCTRL_PIN(37, "PLGPIO37"), \
182 PINCTRL_PIN(38, "PLGPIO38"), \ 182 PINCTRL_PIN(38, "PLGPIO38"), \
183 PINCTRL_PIN(39, "PLGPIO39"), \ 183 PINCTRL_PIN(39, "PLGPIO39"), \
184 PINCTRL_PIN(40, "PLGPIO40"), \ 184 PINCTRL_PIN(40, "PLGPIO40"), \
185 PINCTRL_PIN(41, "PLGPIO41"), \ 185 PINCTRL_PIN(41, "PLGPIO41"), \
186 PINCTRL_PIN(42, "PLGPIO42"), \ 186 PINCTRL_PIN(42, "PLGPIO42"), \
187 PINCTRL_PIN(43, "PLGPIO43"), \ 187 PINCTRL_PIN(43, "PLGPIO43"), \
188 PINCTRL_PIN(44, "PLGPIO44"), \ 188 PINCTRL_PIN(44, "PLGPIO44"), \
189 PINCTRL_PIN(45, "PLGPIO45"), \ 189 PINCTRL_PIN(45, "PLGPIO45"), \
190 PINCTRL_PIN(46, "PLGPIO46"), \ 190 PINCTRL_PIN(46, "PLGPIO46"), \
191 PINCTRL_PIN(47, "PLGPIO47"), \ 191 PINCTRL_PIN(47, "PLGPIO47"), \
192 PINCTRL_PIN(48, "PLGPIO48"), \ 192 PINCTRL_PIN(48, "PLGPIO48"), \
193 PINCTRL_PIN(49, "PLGPIO49"), \ 193 PINCTRL_PIN(49, "PLGPIO49"), \
194 PINCTRL_PIN(50, "PLGPIO50"), \ 194 PINCTRL_PIN(50, "PLGPIO50"), \
195 PINCTRL_PIN(51, "PLGPIO51"), \ 195 PINCTRL_PIN(51, "PLGPIO51"), \
196 PINCTRL_PIN(52, "PLGPIO52"), \ 196 PINCTRL_PIN(52, "PLGPIO52"), \
197 PINCTRL_PIN(53, "PLGPIO53"), \ 197 PINCTRL_PIN(53, "PLGPIO53"), \
198 PINCTRL_PIN(54, "PLGPIO54"), \ 198 PINCTRL_PIN(54, "PLGPIO54"), \
199 PINCTRL_PIN(55, "PLGPIO55"), \ 199 PINCTRL_PIN(55, "PLGPIO55"), \
200 PINCTRL_PIN(56, "PLGPIO56"), \ 200 PINCTRL_PIN(56, "PLGPIO56"), \
201 PINCTRL_PIN(57, "PLGPIO57"), \ 201 PINCTRL_PIN(57, "PLGPIO57"), \
202 PINCTRL_PIN(58, "PLGPIO58"), \ 202 PINCTRL_PIN(58, "PLGPIO58"), \
203 PINCTRL_PIN(59, "PLGPIO59"), \ 203 PINCTRL_PIN(59, "PLGPIO59"), \
204 PINCTRL_PIN(60, "PLGPIO60"), \ 204 PINCTRL_PIN(60, "PLGPIO60"), \
205 PINCTRL_PIN(61, "PLGPIO61"), \ 205 PINCTRL_PIN(61, "PLGPIO61"), \
206 PINCTRL_PIN(62, "PLGPIO62"), \ 206 PINCTRL_PIN(62, "PLGPIO62"), \
207 PINCTRL_PIN(63, "PLGPIO63"), \ 207 PINCTRL_PIN(63, "PLGPIO63"), \
208 PINCTRL_PIN(64, "PLGPIO64"), \ 208 PINCTRL_PIN(64, "PLGPIO64"), \
209 PINCTRL_PIN(65, "PLGPIO65"), \ 209 PINCTRL_PIN(65, "PLGPIO65"), \
210 PINCTRL_PIN(66, "PLGPIO66"), \ 210 PINCTRL_PIN(66, "PLGPIO66"), \
211 PINCTRL_PIN(67, "PLGPIO67"), \ 211 PINCTRL_PIN(67, "PLGPIO67"), \
212 PINCTRL_PIN(68, "PLGPIO68"), \ 212 PINCTRL_PIN(68, "PLGPIO68"), \
213 PINCTRL_PIN(69, "PLGPIO69"), \ 213 PINCTRL_PIN(69, "PLGPIO69"), \
214 PINCTRL_PIN(70, "PLGPIO70"), \ 214 PINCTRL_PIN(70, "PLGPIO70"), \
215 PINCTRL_PIN(71, "PLGPIO71"), \ 215 PINCTRL_PIN(71, "PLGPIO71"), \
216 PINCTRL_PIN(72, "PLGPIO72"), \ 216 PINCTRL_PIN(72, "PLGPIO72"), \
217 PINCTRL_PIN(73, "PLGPIO73"), \ 217 PINCTRL_PIN(73, "PLGPIO73"), \
218 PINCTRL_PIN(74, "PLGPIO74"), \ 218 PINCTRL_PIN(74, "PLGPIO74"), \
219 PINCTRL_PIN(75, "PLGPIO75"), \ 219 PINCTRL_PIN(75, "PLGPIO75"), \
220 PINCTRL_PIN(76, "PLGPIO76"), \ 220 PINCTRL_PIN(76, "PLGPIO76"), \
221 PINCTRL_PIN(77, "PLGPIO77"), \ 221 PINCTRL_PIN(77, "PLGPIO77"), \
222 PINCTRL_PIN(78, "PLGPIO78"), \ 222 PINCTRL_PIN(78, "PLGPIO78"), \
223 PINCTRL_PIN(79, "PLGPIO79"), \ 223 PINCTRL_PIN(79, "PLGPIO79"), \
224 PINCTRL_PIN(80, "PLGPIO80"), \ 224 PINCTRL_PIN(80, "PLGPIO80"), \
225 PINCTRL_PIN(81, "PLGPIO81"), \ 225 PINCTRL_PIN(81, "PLGPIO81"), \
226 PINCTRL_PIN(82, "PLGPIO82"), \ 226 PINCTRL_PIN(82, "PLGPIO82"), \
227 PINCTRL_PIN(83, "PLGPIO83"), \ 227 PINCTRL_PIN(83, "PLGPIO83"), \
228 PINCTRL_PIN(84, "PLGPIO84"), \ 228 PINCTRL_PIN(84, "PLGPIO84"), \
229 PINCTRL_PIN(85, "PLGPIO85"), \ 229 PINCTRL_PIN(85, "PLGPIO85"), \
230 PINCTRL_PIN(86, "PLGPIO86"), \ 230 PINCTRL_PIN(86, "PLGPIO86"), \
231 PINCTRL_PIN(87, "PLGPIO87"), \ 231 PINCTRL_PIN(87, "PLGPIO87"), \
232 PINCTRL_PIN(88, "PLGPIO88"), \ 232 PINCTRL_PIN(88, "PLGPIO88"), \
233 PINCTRL_PIN(89, "PLGPIO89"), \ 233 PINCTRL_PIN(89, "PLGPIO89"), \
234 PINCTRL_PIN(90, "PLGPIO90"), \ 234 PINCTRL_PIN(90, "PLGPIO90"), \
235 PINCTRL_PIN(91, "PLGPIO91"), \ 235 PINCTRL_PIN(91, "PLGPIO91"), \
236 PINCTRL_PIN(92, "PLGPIO92"), \ 236 PINCTRL_PIN(92, "PLGPIO92"), \
237 PINCTRL_PIN(93, "PLGPIO93"), \ 237 PINCTRL_PIN(93, "PLGPIO93"), \
238 PINCTRL_PIN(94, "PLGPIO94"), \ 238 PINCTRL_PIN(94, "PLGPIO94"), \
239 PINCTRL_PIN(95, "PLGPIO95"), \ 239 PINCTRL_PIN(95, "PLGPIO95"), \
240 PINCTRL_PIN(96, "PLGPIO96"), \ 240 PINCTRL_PIN(96, "PLGPIO96"), \
241 PINCTRL_PIN(97, "PLGPIO97"), \ 241 PINCTRL_PIN(97, "PLGPIO97"), \
242 PINCTRL_PIN(98, "PLGPIO98"), \ 242 PINCTRL_PIN(98, "PLGPIO98"), \
243 PINCTRL_PIN(99, "PLGPIO99"), \ 243 PINCTRL_PIN(99, "PLGPIO99"), \
244 PINCTRL_PIN(100, "PLGPIO100"), \ 244 PINCTRL_PIN(100, "PLGPIO100"), \
245 PINCTRL_PIN(101, "PLGPIO101") 245 PINCTRL_PIN(101, "PLGPIO101")
246 246
247 #define SPEAR_PIN_102_TO_245 \ 247 #define SPEAR_PIN_102_TO_245 \
248 PINCTRL_PIN(102, "PLGPIO102"), \ 248 PINCTRL_PIN(102, "PLGPIO102"), \
249 PINCTRL_PIN(103, "PLGPIO103"), \ 249 PINCTRL_PIN(103, "PLGPIO103"), \
250 PINCTRL_PIN(104, "PLGPIO104"), \ 250 PINCTRL_PIN(104, "PLGPIO104"), \
251 PINCTRL_PIN(105, "PLGPIO105"), \ 251 PINCTRL_PIN(105, "PLGPIO105"), \
252 PINCTRL_PIN(106, "PLGPIO106"), \ 252 PINCTRL_PIN(106, "PLGPIO106"), \
253 PINCTRL_PIN(107, "PLGPIO107"), \ 253 PINCTRL_PIN(107, "PLGPIO107"), \
254 PINCTRL_PIN(108, "PLGPIO108"), \ 254 PINCTRL_PIN(108, "PLGPIO108"), \
255 PINCTRL_PIN(109, "PLGPIO109"), \ 255 PINCTRL_PIN(109, "PLGPIO109"), \
256 PINCTRL_PIN(110, "PLGPIO110"), \ 256 PINCTRL_PIN(110, "PLGPIO110"), \
257 PINCTRL_PIN(111, "PLGPIO111"), \ 257 PINCTRL_PIN(111, "PLGPIO111"), \
258 PINCTRL_PIN(112, "PLGPIO112"), \ 258 PINCTRL_PIN(112, "PLGPIO112"), \
259 PINCTRL_PIN(113, "PLGPIO113"), \ 259 PINCTRL_PIN(113, "PLGPIO113"), \
260 PINCTRL_PIN(114, "PLGPIO114"), \ 260 PINCTRL_PIN(114, "PLGPIO114"), \
261 PINCTRL_PIN(115, "PLGPIO115"), \ 261 PINCTRL_PIN(115, "PLGPIO115"), \
262 PINCTRL_PIN(116, "PLGPIO116"), \ 262 PINCTRL_PIN(116, "PLGPIO116"), \
263 PINCTRL_PIN(117, "PLGPIO117"), \ 263 PINCTRL_PIN(117, "PLGPIO117"), \
264 PINCTRL_PIN(118, "PLGPIO118"), \ 264 PINCTRL_PIN(118, "PLGPIO118"), \
265 PINCTRL_PIN(119, "PLGPIO119"), \ 265 PINCTRL_PIN(119, "PLGPIO119"), \
266 PINCTRL_PIN(120, "PLGPIO120"), \ 266 PINCTRL_PIN(120, "PLGPIO120"), \
267 PINCTRL_PIN(121, "PLGPIO121"), \ 267 PINCTRL_PIN(121, "PLGPIO121"), \
268 PINCTRL_PIN(122, "PLGPIO122"), \ 268 PINCTRL_PIN(122, "PLGPIO122"), \
269 PINCTRL_PIN(123, "PLGPIO123"), \ 269 PINCTRL_PIN(123, "PLGPIO123"), \
270 PINCTRL_PIN(124, "PLGPIO124"), \ 270 PINCTRL_PIN(124, "PLGPIO124"), \
271 PINCTRL_PIN(125, "PLGPIO125"), \ 271 PINCTRL_PIN(125, "PLGPIO125"), \
272 PINCTRL_PIN(126, "PLGPIO126"), \ 272 PINCTRL_PIN(126, "PLGPIO126"), \
273 PINCTRL_PIN(127, "PLGPIO127"), \ 273 PINCTRL_PIN(127, "PLGPIO127"), \
274 PINCTRL_PIN(128, "PLGPIO128"), \ 274 PINCTRL_PIN(128, "PLGPIO128"), \
275 PINCTRL_PIN(129, "PLGPIO129"), \ 275 PINCTRL_PIN(129, "PLGPIO129"), \
276 PINCTRL_PIN(130, "PLGPIO130"), \ 276 PINCTRL_PIN(130, "PLGPIO130"), \
277 PINCTRL_PIN(131, "PLGPIO131"), \ 277 PINCTRL_PIN(131, "PLGPIO131"), \
278 PINCTRL_PIN(132, "PLGPIO132"), \ 278 PINCTRL_PIN(132, "PLGPIO132"), \
279 PINCTRL_PIN(133, "PLGPIO133"), \ 279 PINCTRL_PIN(133, "PLGPIO133"), \
280 PINCTRL_PIN(134, "PLGPIO134"), \ 280 PINCTRL_PIN(134, "PLGPIO134"), \
281 PINCTRL_PIN(135, "PLGPIO135"), \ 281 PINCTRL_PIN(135, "PLGPIO135"), \
282 PINCTRL_PIN(136, "PLGPIO136"), \ 282 PINCTRL_PIN(136, "PLGPIO136"), \
283 PINCTRL_PIN(137, "PLGPIO137"), \ 283 PINCTRL_PIN(137, "PLGPIO137"), \
284 PINCTRL_PIN(138, "PLGPIO138"), \ 284 PINCTRL_PIN(138, "PLGPIO138"), \
285 PINCTRL_PIN(139, "PLGPIO139"), \ 285 PINCTRL_PIN(139, "PLGPIO139"), \
286 PINCTRL_PIN(140, "PLGPIO140"), \ 286 PINCTRL_PIN(140, "PLGPIO140"), \
287 PINCTRL_PIN(141, "PLGPIO141"), \ 287 PINCTRL_PIN(141, "PLGPIO141"), \
288 PINCTRL_PIN(142, "PLGPIO142"), \ 288 PINCTRL_PIN(142, "PLGPIO142"), \
289 PINCTRL_PIN(143, "PLGPIO143"), \ 289 PINCTRL_PIN(143, "PLGPIO143"), \
290 PINCTRL_PIN(144, "PLGPIO144"), \ 290 PINCTRL_PIN(144, "PLGPIO144"), \
291 PINCTRL_PIN(145, "PLGPIO145"), \ 291 PINCTRL_PIN(145, "PLGPIO145"), \
292 PINCTRL_PIN(146, "PLGPIO146"), \ 292 PINCTRL_PIN(146, "PLGPIO146"), \
293 PINCTRL_PIN(147, "PLGPIO147"), \ 293 PINCTRL_PIN(147, "PLGPIO147"), \
294 PINCTRL_PIN(148, "PLGPIO148"), \ 294 PINCTRL_PIN(148, "PLGPIO148"), \
295 PINCTRL_PIN(149, "PLGPIO149"), \ 295 PINCTRL_PIN(149, "PLGPIO149"), \
296 PINCTRL_PIN(150, "PLGPIO150"), \ 296 PINCTRL_PIN(150, "PLGPIO150"), \
297 PINCTRL_PIN(151, "PLGPIO151"), \ 297 PINCTRL_PIN(151, "PLGPIO151"), \
298 PINCTRL_PIN(152, "PLGPIO152"), \ 298 PINCTRL_PIN(152, "PLGPIO152"), \
299 PINCTRL_PIN(153, "PLGPIO153"), \ 299 PINCTRL_PIN(153, "PLGPIO153"), \
300 PINCTRL_PIN(154, "PLGPIO154"), \ 300 PINCTRL_PIN(154, "PLGPIO154"), \
301 PINCTRL_PIN(155, "PLGPIO155"), \ 301 PINCTRL_PIN(155, "PLGPIO155"), \
302 PINCTRL_PIN(156, "PLGPIO156"), \ 302 PINCTRL_PIN(156, "PLGPIO156"), \
303 PINCTRL_PIN(157, "PLGPIO157"), \ 303 PINCTRL_PIN(157, "PLGPIO157"), \
304 PINCTRL_PIN(158, "PLGPIO158"), \ 304 PINCTRL_PIN(158, "PLGPIO158"), \
305 PINCTRL_PIN(159, "PLGPIO159"), \ 305 PINCTRL_PIN(159, "PLGPIO159"), \
306 PINCTRL_PIN(160, "PLGPIO160"), \ 306 PINCTRL_PIN(160, "PLGPIO160"), \
307 PINCTRL_PIN(161, "PLGPIO161"), \ 307 PINCTRL_PIN(161, "PLGPIO161"), \
308 PINCTRL_PIN(162, "PLGPIO162"), \ 308 PINCTRL_PIN(162, "PLGPIO162"), \
309 PINCTRL_PIN(163, "PLGPIO163"), \ 309 PINCTRL_PIN(163, "PLGPIO163"), \
310 PINCTRL_PIN(164, "PLGPIO164"), \ 310 PINCTRL_PIN(164, "PLGPIO164"), \
311 PINCTRL_PIN(165, "PLGPIO165"), \ 311 PINCTRL_PIN(165, "PLGPIO165"), \
312 PINCTRL_PIN(166, "PLGPIO166"), \ 312 PINCTRL_PIN(166, "PLGPIO166"), \
313 PINCTRL_PIN(167, "PLGPIO167"), \ 313 PINCTRL_PIN(167, "PLGPIO167"), \
314 PINCTRL_PIN(168, "PLGPIO168"), \ 314 PINCTRL_PIN(168, "PLGPIO168"), \
315 PINCTRL_PIN(169, "PLGPIO169"), \ 315 PINCTRL_PIN(169, "PLGPIO169"), \
316 PINCTRL_PIN(170, "PLGPIO170"), \ 316 PINCTRL_PIN(170, "PLGPIO170"), \
317 PINCTRL_PIN(171, "PLGPIO171"), \ 317 PINCTRL_PIN(171, "PLGPIO171"), \
318 PINCTRL_PIN(172, "PLGPIO172"), \ 318 PINCTRL_PIN(172, "PLGPIO172"), \
319 PINCTRL_PIN(173, "PLGPIO173"), \ 319 PINCTRL_PIN(173, "PLGPIO173"), \
320 PINCTRL_PIN(174, "PLGPIO174"), \ 320 PINCTRL_PIN(174, "PLGPIO174"), \
321 PINCTRL_PIN(175, "PLGPIO175"), \ 321 PINCTRL_PIN(175, "PLGPIO175"), \
322 PINCTRL_PIN(176, "PLGPIO176"), \ 322 PINCTRL_PIN(176, "PLGPIO176"), \
323 PINCTRL_PIN(177, "PLGPIO177"), \ 323 PINCTRL_PIN(177, "PLGPIO177"), \
324 PINCTRL_PIN(178, "PLGPIO178"), \ 324 PINCTRL_PIN(178, "PLGPIO178"), \
325 PINCTRL_PIN(179, "PLGPIO179"), \ 325 PINCTRL_PIN(179, "PLGPIO179"), \
326 PINCTRL_PIN(180, "PLGPIO180"), \ 326 PINCTRL_PIN(180, "PLGPIO180"), \
327 PINCTRL_PIN(181, "PLGPIO181"), \ 327 PINCTRL_PIN(181, "PLGPIO181"), \
328 PINCTRL_PIN(182, "PLGPIO182"), \ 328 PINCTRL_PIN(182, "PLGPIO182"), \
329 PINCTRL_PIN(183, "PLGPIO183"), \ 329 PINCTRL_PIN(183, "PLGPIO183"), \
330 PINCTRL_PIN(184, "PLGPIO184"), \ 330 PINCTRL_PIN(184, "PLGPIO184"), \
331 PINCTRL_PIN(185, "PLGPIO185"), \ 331 PINCTRL_PIN(185, "PLGPIO185"), \
332 PINCTRL_PIN(186, "PLGPIO186"), \ 332 PINCTRL_PIN(186, "PLGPIO186"), \
333 PINCTRL_PIN(187, "PLGPIO187"), \ 333 PINCTRL_PIN(187, "PLGPIO187"), \
334 PINCTRL_PIN(188, "PLGPIO188"), \ 334 PINCTRL_PIN(188, "PLGPIO188"), \
335 PINCTRL_PIN(189, "PLGPIO189"), \ 335 PINCTRL_PIN(189, "PLGPIO189"), \
336 PINCTRL_PIN(190, "PLGPIO190"), \ 336 PINCTRL_PIN(190, "PLGPIO190"), \
337 PINCTRL_PIN(191, "PLGPIO191"), \ 337 PINCTRL_PIN(191, "PLGPIO191"), \
338 PINCTRL_PIN(192, "PLGPIO192"), \ 338 PINCTRL_PIN(192, "PLGPIO192"), \
339 PINCTRL_PIN(193, "PLGPIO193"), \ 339 PINCTRL_PIN(193, "PLGPIO193"), \
340 PINCTRL_PIN(194, "PLGPIO194"), \ 340 PINCTRL_PIN(194, "PLGPIO194"), \
341 PINCTRL_PIN(195, "PLGPIO195"), \ 341 PINCTRL_PIN(195, "PLGPIO195"), \
342 PINCTRL_PIN(196, "PLGPIO196"), \ 342 PINCTRL_PIN(196, "PLGPIO196"), \
343 PINCTRL_PIN(197, "PLGPIO197"), \ 343 PINCTRL_PIN(197, "PLGPIO197"), \
344 PINCTRL_PIN(198, "PLGPIO198"), \ 344 PINCTRL_PIN(198, "PLGPIO198"), \
345 PINCTRL_PIN(199, "PLGPIO199"), \ 345 PINCTRL_PIN(199, "PLGPIO199"), \
346 PINCTRL_PIN(200, "PLGPIO200"), \ 346 PINCTRL_PIN(200, "PLGPIO200"), \
347 PINCTRL_PIN(201, "PLGPIO201"), \ 347 PINCTRL_PIN(201, "PLGPIO201"), \
348 PINCTRL_PIN(202, "PLGPIO202"), \ 348 PINCTRL_PIN(202, "PLGPIO202"), \
349 PINCTRL_PIN(203, "PLGPIO203"), \ 349 PINCTRL_PIN(203, "PLGPIO203"), \
350 PINCTRL_PIN(204, "PLGPIO204"), \ 350 PINCTRL_PIN(204, "PLGPIO204"), \
351 PINCTRL_PIN(205, "PLGPIO205"), \ 351 PINCTRL_PIN(205, "PLGPIO205"), \
352 PINCTRL_PIN(206, "PLGPIO206"), \ 352 PINCTRL_PIN(206, "PLGPIO206"), \
353 PINCTRL_PIN(207, "PLGPIO207"), \ 353 PINCTRL_PIN(207, "PLGPIO207"), \
354 PINCTRL_PIN(208, "PLGPIO208"), \ 354 PINCTRL_PIN(208, "PLGPIO208"), \
355 PINCTRL_PIN(209, "PLGPIO209"), \ 355 PINCTRL_PIN(209, "PLGPIO209"), \
356 PINCTRL_PIN(210, "PLGPIO210"), \ 356 PINCTRL_PIN(210, "PLGPIO210"), \
357 PINCTRL_PIN(211, "PLGPIO211"), \ 357 PINCTRL_PIN(211, "PLGPIO211"), \
358 PINCTRL_PIN(212, "PLGPIO212"), \ 358 PINCTRL_PIN(212, "PLGPIO212"), \
359 PINCTRL_PIN(213, "PLGPIO213"), \ 359 PINCTRL_PIN(213, "PLGPIO213"), \
360 PINCTRL_PIN(214, "PLGPIO214"), \ 360 PINCTRL_PIN(214, "PLGPIO214"), \
361 PINCTRL_PIN(215, "PLGPIO215"), \ 361 PINCTRL_PIN(215, "PLGPIO215"), \
362 PINCTRL_PIN(216, "PLGPIO216"), \ 362 PINCTRL_PIN(216, "PLGPIO216"), \
363 PINCTRL_PIN(217, "PLGPIO217"), \ 363 PINCTRL_PIN(217, "PLGPIO217"), \
364 PINCTRL_PIN(218, "PLGPIO218"), \ 364 PINCTRL_PIN(218, "PLGPIO218"), \
365 PINCTRL_PIN(219, "PLGPIO219"), \ 365 PINCTRL_PIN(219, "PLGPIO219"), \
366 PINCTRL_PIN(220, "PLGPIO220"), \ 366 PINCTRL_PIN(220, "PLGPIO220"), \
367 PINCTRL_PIN(221, "PLGPIO221"), \ 367 PINCTRL_PIN(221, "PLGPIO221"), \
368 PINCTRL_PIN(222, "PLGPIO222"), \ 368 PINCTRL_PIN(222, "PLGPIO222"), \
369 PINCTRL_PIN(223, "PLGPIO223"), \ 369 PINCTRL_PIN(223, "PLGPIO223"), \
370 PINCTRL_PIN(224, "PLGPIO224"), \ 370 PINCTRL_PIN(224, "PLGPIO224"), \
371 PINCTRL_PIN(225, "PLGPIO225"), \ 371 PINCTRL_PIN(225, "PLGPIO225"), \
372 PINCTRL_PIN(226, "PLGPIO226"), \ 372 PINCTRL_PIN(226, "PLGPIO226"), \
373 PINCTRL_PIN(227, "PLGPIO227"), \ 373 PINCTRL_PIN(227, "PLGPIO227"), \
374 PINCTRL_PIN(228, "PLGPIO228"), \ 374 PINCTRL_PIN(228, "PLGPIO228"), \
375 PINCTRL_PIN(229, "PLGPIO229"), \ 375 PINCTRL_PIN(229, "PLGPIO229"), \
376 PINCTRL_PIN(230, "PLGPIO230"), \ 376 PINCTRL_PIN(230, "PLGPIO230"), \
377 PINCTRL_PIN(231, "PLGPIO231"), \ 377 PINCTRL_PIN(231, "PLGPIO231"), \
378 PINCTRL_PIN(232, "PLGPIO232"), \ 378 PINCTRL_PIN(232, "PLGPIO232"), \
379 PINCTRL_PIN(233, "PLGPIO233"), \ 379 PINCTRL_PIN(233, "PLGPIO233"), \
380 PINCTRL_PIN(234, "PLGPIO234"), \ 380 PINCTRL_PIN(234, "PLGPIO234"), \
381 PINCTRL_PIN(235, "PLGPIO235"), \ 381 PINCTRL_PIN(235, "PLGPIO235"), \
382 PINCTRL_PIN(236, "PLGPIO236"), \ 382 PINCTRL_PIN(236, "PLGPIO236"), \
383 PINCTRL_PIN(237, "PLGPIO237"), \ 383 PINCTRL_PIN(237, "PLGPIO237"), \
384 PINCTRL_PIN(238, "PLGPIO238"), \ 384 PINCTRL_PIN(238, "PLGPIO238"), \
385 PINCTRL_PIN(239, "PLGPIO239"), \ 385 PINCTRL_PIN(239, "PLGPIO239"), \
386 PINCTRL_PIN(240, "PLGPIO240"), \ 386 PINCTRL_PIN(240, "PLGPIO240"), \
387 PINCTRL_PIN(241, "PLGPIO241"), \ 387 PINCTRL_PIN(241, "PLGPIO241"), \
388 PINCTRL_PIN(242, "PLGPIO242"), \ 388 PINCTRL_PIN(242, "PLGPIO242"), \
389 PINCTRL_PIN(243, "PLGPIO243"), \ 389 PINCTRL_PIN(243, "PLGPIO243"), \
390 PINCTRL_PIN(244, "PLGPIO244"), \ 390 PINCTRL_PIN(244, "PLGPIO244"), \
391 PINCTRL_PIN(245, "PLGPIO245") 391 PINCTRL_PIN(245, "PLGPIO245")
392 392
393 #endif /* __PINMUX_SPEAR_H__ */ 393 #endif /* __PINMUX_SPEAR_H__ */
394 394
drivers/pinctrl/spear/pinctrl-spear1310.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Driver for the ST Microelectronics SPEAr1310 pinmux 2 * Driver for the ST Microelectronics SPEAr1310 pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/err.h> 12 #include <linux/err.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/module.h> 14 #include <linux/module.h>
15 #include <linux/of_device.h> 15 #include <linux/of_device.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include "pinctrl-spear.h" 17 #include "pinctrl-spear.h"
18 18
19 #define DRIVER_NAME "spear1310-pinmux" 19 #define DRIVER_NAME "spear1310-pinmux"
20 20
21 /* pins */ 21 /* pins */
22 static const struct pinctrl_pin_desc spear1310_pins[] = { 22 static const struct pinctrl_pin_desc spear1310_pins[] = {
23 SPEAR_PIN_0_TO_101, 23 SPEAR_PIN_0_TO_101,
24 SPEAR_PIN_102_TO_245, 24 SPEAR_PIN_102_TO_245,
25 }; 25 };
26 26
27 /* registers */ 27 /* registers */
28 #define PERIP_CFG 0x3B0 28 #define PERIP_CFG 0x3B0
29 #define MCIF_SEL_SHIFT 5 29 #define MCIF_SEL_SHIFT 5
30 #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT) 30 #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
31 #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT) 31 #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
32 #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT) 32 #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
33 #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT) 33 #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
34 34
35 #define PCIE_SATA_CFG 0x3A4 35 #define PCIE_SATA_CFG 0x3A4
36 #define PCIE_SATA2_SEL_PCIE (0 << 31) 36 #define PCIE_SATA2_SEL_PCIE (0 << 31)
37 #define PCIE_SATA1_SEL_PCIE (0 << 30) 37 #define PCIE_SATA1_SEL_PCIE (0 << 30)
38 #define PCIE_SATA0_SEL_PCIE (0 << 29) 38 #define PCIE_SATA0_SEL_PCIE (0 << 29)
39 #define PCIE_SATA2_SEL_SATA (1 << 31) 39 #define PCIE_SATA2_SEL_SATA (1 << 31)
40 #define PCIE_SATA1_SEL_SATA (1 << 30) 40 #define PCIE_SATA1_SEL_SATA (1 << 30)
41 #define PCIE_SATA0_SEL_SATA (1 << 29) 41 #define PCIE_SATA0_SEL_SATA (1 << 29)
42 #define SATA2_CFG_TX_CLK_EN (1 << 27) 42 #define SATA2_CFG_TX_CLK_EN (1 << 27)
43 #define SATA2_CFG_RX_CLK_EN (1 << 26) 43 #define SATA2_CFG_RX_CLK_EN (1 << 26)
44 #define SATA2_CFG_POWERUP_RESET (1 << 25) 44 #define SATA2_CFG_POWERUP_RESET (1 << 25)
45 #define SATA2_CFG_PM_CLK_EN (1 << 24) 45 #define SATA2_CFG_PM_CLK_EN (1 << 24)
46 #define SATA1_CFG_TX_CLK_EN (1 << 23) 46 #define SATA1_CFG_TX_CLK_EN (1 << 23)
47 #define SATA1_CFG_RX_CLK_EN (1 << 22) 47 #define SATA1_CFG_RX_CLK_EN (1 << 22)
48 #define SATA1_CFG_POWERUP_RESET (1 << 21) 48 #define SATA1_CFG_POWERUP_RESET (1 << 21)
49 #define SATA1_CFG_PM_CLK_EN (1 << 20) 49 #define SATA1_CFG_PM_CLK_EN (1 << 20)
50 #define SATA0_CFG_TX_CLK_EN (1 << 19) 50 #define SATA0_CFG_TX_CLK_EN (1 << 19)
51 #define SATA0_CFG_RX_CLK_EN (1 << 18) 51 #define SATA0_CFG_RX_CLK_EN (1 << 18)
52 #define SATA0_CFG_POWERUP_RESET (1 << 17) 52 #define SATA0_CFG_POWERUP_RESET (1 << 17)
53 #define SATA0_CFG_PM_CLK_EN (1 << 16) 53 #define SATA0_CFG_PM_CLK_EN (1 << 16)
54 #define PCIE2_CFG_DEVICE_PRESENT (1 << 11) 54 #define PCIE2_CFG_DEVICE_PRESENT (1 << 11)
55 #define PCIE2_CFG_POWERUP_RESET (1 << 10) 55 #define PCIE2_CFG_POWERUP_RESET (1 << 10)
56 #define PCIE2_CFG_CORE_CLK_EN (1 << 9) 56 #define PCIE2_CFG_CORE_CLK_EN (1 << 9)
57 #define PCIE2_CFG_AUX_CLK_EN (1 << 8) 57 #define PCIE2_CFG_AUX_CLK_EN (1 << 8)
58 #define PCIE1_CFG_DEVICE_PRESENT (1 << 7) 58 #define PCIE1_CFG_DEVICE_PRESENT (1 << 7)
59 #define PCIE1_CFG_POWERUP_RESET (1 << 6) 59 #define PCIE1_CFG_POWERUP_RESET (1 << 6)
60 #define PCIE1_CFG_CORE_CLK_EN (1 << 5) 60 #define PCIE1_CFG_CORE_CLK_EN (1 << 5)
61 #define PCIE1_CFG_AUX_CLK_EN (1 << 4) 61 #define PCIE1_CFG_AUX_CLK_EN (1 << 4)
62 #define PCIE0_CFG_DEVICE_PRESENT (1 << 3) 62 #define PCIE0_CFG_DEVICE_PRESENT (1 << 3)
63 #define PCIE0_CFG_POWERUP_RESET (1 << 2) 63 #define PCIE0_CFG_POWERUP_RESET (1 << 2)
64 #define PCIE0_CFG_CORE_CLK_EN (1 << 1) 64 #define PCIE0_CFG_CORE_CLK_EN (1 << 1)
65 #define PCIE0_CFG_AUX_CLK_EN (1 << 0) 65 #define PCIE0_CFG_AUX_CLK_EN (1 << 0)
66 66
67 #define PAD_FUNCTION_EN_0 0x650 67 #define PAD_FUNCTION_EN_0 0x650
68 #define PMX_UART0_MASK (1 << 1) 68 #define PMX_UART0_MASK (1 << 1)
69 #define PMX_I2C0_MASK (1 << 2) 69 #define PMX_I2C0_MASK (1 << 2)
70 #define PMX_I2S0_MASK (1 << 3) 70 #define PMX_I2S0_MASK (1 << 3)
71 #define PMX_SSP0_MASK (1 << 4) 71 #define PMX_SSP0_MASK (1 << 4)
72 #define PMX_CLCD1_MASK (1 << 5) 72 #define PMX_CLCD1_MASK (1 << 5)
73 #define PMX_EGPIO00_MASK (1 << 6) 73 #define PMX_EGPIO00_MASK (1 << 6)
74 #define PMX_EGPIO01_MASK (1 << 7) 74 #define PMX_EGPIO01_MASK (1 << 7)
75 #define PMX_EGPIO02_MASK (1 << 8) 75 #define PMX_EGPIO02_MASK (1 << 8)
76 #define PMX_EGPIO03_MASK (1 << 9) 76 #define PMX_EGPIO03_MASK (1 << 9)
77 #define PMX_EGPIO04_MASK (1 << 10) 77 #define PMX_EGPIO04_MASK (1 << 10)
78 #define PMX_EGPIO05_MASK (1 << 11) 78 #define PMX_EGPIO05_MASK (1 << 11)
79 #define PMX_EGPIO06_MASK (1 << 12) 79 #define PMX_EGPIO06_MASK (1 << 12)
80 #define PMX_EGPIO07_MASK (1 << 13) 80 #define PMX_EGPIO07_MASK (1 << 13)
81 #define PMX_EGPIO08_MASK (1 << 14) 81 #define PMX_EGPIO08_MASK (1 << 14)
82 #define PMX_EGPIO09_MASK (1 << 15) 82 #define PMX_EGPIO09_MASK (1 << 15)
83 #define PMX_SMI_MASK (1 << 16) 83 #define PMX_SMI_MASK (1 << 16)
84 #define PMX_NAND8_MASK (1 << 17) 84 #define PMX_NAND8_MASK (1 << 17)
85 #define PMX_GMIICLK_MASK (1 << 18) 85 #define PMX_GMIICLK_MASK (1 << 18)
86 #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19) 86 #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
87 #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20) 87 #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
88 #define PMX_GMIID47_MASK (1 << 21) 88 #define PMX_GMIID47_MASK (1 << 21)
89 #define PMX_MDC_MDIO_MASK (1 << 22) 89 #define PMX_MDC_MDIO_MASK (1 << 22)
90 #define PMX_MCI_DATA8_15_MASK (1 << 23) 90 #define PMX_MCI_DATA8_15_MASK (1 << 23)
91 #define PMX_NFAD23_MASK (1 << 24) 91 #define PMX_NFAD23_MASK (1 << 24)
92 #define PMX_NFAD24_MASK (1 << 25) 92 #define PMX_NFAD24_MASK (1 << 25)
93 #define PMX_NFAD25_MASK (1 << 26) 93 #define PMX_NFAD25_MASK (1 << 26)
94 #define PMX_NFCE3_MASK (1 << 27) 94 #define PMX_NFCE3_MASK (1 << 27)
95 #define PMX_NFWPRT3_MASK (1 << 28) 95 #define PMX_NFWPRT3_MASK (1 << 28)
96 #define PMX_NFRSTPWDWN0_MASK (1 << 29) 96 #define PMX_NFRSTPWDWN0_MASK (1 << 29)
97 #define PMX_NFRSTPWDWN1_MASK (1 << 30) 97 #define PMX_NFRSTPWDWN1_MASK (1 << 30)
98 #define PMX_NFRSTPWDWN2_MASK (1 << 31) 98 #define PMX_NFRSTPWDWN2_MASK (1 << 31)
99 99
100 #define PAD_FUNCTION_EN_1 0x654 100 #define PAD_FUNCTION_EN_1 0x654
101 #define PMX_NFRSTPWDWN3_MASK (1 << 0) 101 #define PMX_NFRSTPWDWN3_MASK (1 << 0)
102 #define PMX_SMINCS2_MASK (1 << 1) 102 #define PMX_SMINCS2_MASK (1 << 1)
103 #define PMX_SMINCS3_MASK (1 << 2) 103 #define PMX_SMINCS3_MASK (1 << 2)
104 #define PMX_CLCD2_MASK (1 << 3) 104 #define PMX_CLCD2_MASK (1 << 3)
105 #define PMX_KBD_ROWCOL68_MASK (1 << 4) 105 #define PMX_KBD_ROWCOL68_MASK (1 << 4)
106 #define PMX_EGPIO10_MASK (1 << 5) 106 #define PMX_EGPIO10_MASK (1 << 5)
107 #define PMX_EGPIO11_MASK (1 << 6) 107 #define PMX_EGPIO11_MASK (1 << 6)
108 #define PMX_EGPIO12_MASK (1 << 7) 108 #define PMX_EGPIO12_MASK (1 << 7)
109 #define PMX_EGPIO13_MASK (1 << 8) 109 #define PMX_EGPIO13_MASK (1 << 8)
110 #define PMX_EGPIO14_MASK (1 << 9) 110 #define PMX_EGPIO14_MASK (1 << 9)
111 #define PMX_EGPIO15_MASK (1 << 10) 111 #define PMX_EGPIO15_MASK (1 << 10)
112 #define PMX_UART0_MODEM_MASK (1 << 11) 112 #define PMX_UART0_MODEM_MASK (1 << 11)
113 #define PMX_GPT0_TMR0_MASK (1 << 12) 113 #define PMX_GPT0_TMR0_MASK (1 << 12)
114 #define PMX_GPT0_TMR1_MASK (1 << 13) 114 #define PMX_GPT0_TMR1_MASK (1 << 13)
115 #define PMX_GPT1_TMR0_MASK (1 << 14) 115 #define PMX_GPT1_TMR0_MASK (1 << 14)
116 #define PMX_GPT1_TMR1_MASK (1 << 15) 116 #define PMX_GPT1_TMR1_MASK (1 << 15)
117 #define PMX_I2S1_MASK (1 << 16) 117 #define PMX_I2S1_MASK (1 << 16)
118 #define PMX_KBD_ROWCOL25_MASK (1 << 17) 118 #define PMX_KBD_ROWCOL25_MASK (1 << 17)
119 #define PMX_NFIO8_15_MASK (1 << 18) 119 #define PMX_NFIO8_15_MASK (1 << 18)
120 #define PMX_KBD_COL1_MASK (1 << 19) 120 #define PMX_KBD_COL1_MASK (1 << 19)
121 #define PMX_NFCE1_MASK (1 << 20) 121 #define PMX_NFCE1_MASK (1 << 20)
122 #define PMX_KBD_COL0_MASK (1 << 21) 122 #define PMX_KBD_COL0_MASK (1 << 21)
123 #define PMX_NFCE2_MASK (1 << 22) 123 #define PMX_NFCE2_MASK (1 << 22)
124 #define PMX_KBD_ROW1_MASK (1 << 23) 124 #define PMX_KBD_ROW1_MASK (1 << 23)
125 #define PMX_NFWPRT1_MASK (1 << 24) 125 #define PMX_NFWPRT1_MASK (1 << 24)
126 #define PMX_KBD_ROW0_MASK (1 << 25) 126 #define PMX_KBD_ROW0_MASK (1 << 25)
127 #define PMX_NFWPRT2_MASK (1 << 26) 127 #define PMX_NFWPRT2_MASK (1 << 26)
128 #define PMX_MCIDATA0_MASK (1 << 27) 128 #define PMX_MCIDATA0_MASK (1 << 27)
129 #define PMX_MCIDATA1_MASK (1 << 28) 129 #define PMX_MCIDATA1_MASK (1 << 28)
130 #define PMX_MCIDATA2_MASK (1 << 29) 130 #define PMX_MCIDATA2_MASK (1 << 29)
131 #define PMX_MCIDATA3_MASK (1 << 30) 131 #define PMX_MCIDATA3_MASK (1 << 30)
132 #define PMX_MCIDATA4_MASK (1 << 31) 132 #define PMX_MCIDATA4_MASK (1 << 31)
133 133
134 #define PAD_FUNCTION_EN_2 0x658 134 #define PAD_FUNCTION_EN_2 0x658
135 #define PMX_MCIDATA5_MASK (1 << 0) 135 #define PMX_MCIDATA5_MASK (1 << 0)
136 #define PMX_MCIDATA6_MASK (1 << 1) 136 #define PMX_MCIDATA6_MASK (1 << 1)
137 #define PMX_MCIDATA7_MASK (1 << 2) 137 #define PMX_MCIDATA7_MASK (1 << 2)
138 #define PMX_MCIDATA1SD_MASK (1 << 3) 138 #define PMX_MCIDATA1SD_MASK (1 << 3)
139 #define PMX_MCIDATA2SD_MASK (1 << 4) 139 #define PMX_MCIDATA2SD_MASK (1 << 4)
140 #define PMX_MCIDATA3SD_MASK (1 << 5) 140 #define PMX_MCIDATA3SD_MASK (1 << 5)
141 #define PMX_MCIADDR0ALE_MASK (1 << 6) 141 #define PMX_MCIADDR0ALE_MASK (1 << 6)
142 #define PMX_MCIADDR1CLECLK_MASK (1 << 7) 142 #define PMX_MCIADDR1CLECLK_MASK (1 << 7)
143 #define PMX_MCIADDR2_MASK (1 << 8) 143 #define PMX_MCIADDR2_MASK (1 << 8)
144 #define PMX_MCICECF_MASK (1 << 9) 144 #define PMX_MCICECF_MASK (1 << 9)
145 #define PMX_MCICEXD_MASK (1 << 10) 145 #define PMX_MCICEXD_MASK (1 << 10)
146 #define PMX_MCICESDMMC_MASK (1 << 11) 146 #define PMX_MCICESDMMC_MASK (1 << 11)
147 #define PMX_MCICDCF1_MASK (1 << 12) 147 #define PMX_MCICDCF1_MASK (1 << 12)
148 #define PMX_MCICDCF2_MASK (1 << 13) 148 #define PMX_MCICDCF2_MASK (1 << 13)
149 #define PMX_MCICDXD_MASK (1 << 14) 149 #define PMX_MCICDXD_MASK (1 << 14)
150 #define PMX_MCICDSDMMC_MASK (1 << 15) 150 #define PMX_MCICDSDMMC_MASK (1 << 15)
151 #define PMX_MCIDATADIR_MASK (1 << 16) 151 #define PMX_MCIDATADIR_MASK (1 << 16)
152 #define PMX_MCIDMARQWP_MASK (1 << 17) 152 #define PMX_MCIDMARQWP_MASK (1 << 17)
153 #define PMX_MCIIORDRE_MASK (1 << 18) 153 #define PMX_MCIIORDRE_MASK (1 << 18)
154 #define PMX_MCIIOWRWE_MASK (1 << 19) 154 #define PMX_MCIIOWRWE_MASK (1 << 19)
155 #define PMX_MCIRESETCF_MASK (1 << 20) 155 #define PMX_MCIRESETCF_MASK (1 << 20)
156 #define PMX_MCICS0CE_MASK (1 << 21) 156 #define PMX_MCICS0CE_MASK (1 << 21)
157 #define PMX_MCICFINTR_MASK (1 << 22) 157 #define PMX_MCICFINTR_MASK (1 << 22)
158 #define PMX_MCIIORDY_MASK (1 << 23) 158 #define PMX_MCIIORDY_MASK (1 << 23)
159 #define PMX_MCICS1_MASK (1 << 24) 159 #define PMX_MCICS1_MASK (1 << 24)
160 #define PMX_MCIDMAACK_MASK (1 << 25) 160 #define PMX_MCIDMAACK_MASK (1 << 25)
161 #define PMX_MCISDCMD_MASK (1 << 26) 161 #define PMX_MCISDCMD_MASK (1 << 26)
162 #define PMX_MCILEDS_MASK (1 << 27) 162 #define PMX_MCILEDS_MASK (1 << 27)
163 #define PMX_TOUCH_XY_MASK (1 << 28) 163 #define PMX_TOUCH_XY_MASK (1 << 28)
164 #define PMX_SSP0_CS0_MASK (1 << 29) 164 #define PMX_SSP0_CS0_MASK (1 << 29)
165 #define PMX_SSP0_CS1_2_MASK (1 << 30) 165 #define PMX_SSP0_CS1_2_MASK (1 << 30)
166 166
167 #define PAD_DIRECTION_SEL_0 0x65C 167 #define PAD_DIRECTION_SEL_0 0x65C
168 #define PAD_DIRECTION_SEL_1 0x660 168 #define PAD_DIRECTION_SEL_1 0x660
169 #define PAD_DIRECTION_SEL_2 0x664 169 #define PAD_DIRECTION_SEL_2 0x664
170 170
171 /* combined macros */ 171 /* combined macros */
172 #define PMX_GMII_MASK (PMX_GMIICLK_MASK | \ 172 #define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
173 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \ 173 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
174 PMX_RXCLK_RDV_TXEN_D03_MASK | \ 174 PMX_RXCLK_RDV_TXEN_D03_MASK | \
175 PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK) 175 PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
176 176
177 #define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \ 177 #define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
178 PMX_EGPIO02_MASK | \ 178 PMX_EGPIO02_MASK | \
179 PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \ 179 PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
180 PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \ 180 PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \
181 PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \ 181 PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \
182 PMX_EGPIO09_MASK) 182 PMX_EGPIO09_MASK)
183 #define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \ 183 #define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
184 PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \ 184 PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \
185 PMX_EGPIO14_MASK | PMX_EGPIO15_MASK) 185 PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
186 186
187 #define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \ 187 #define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
188 PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \ 188 PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
189 PMX_KBD_COL1_MASK) 189 PMX_KBD_COL1_MASK)
190 190
191 #define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \ 191 #define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \
192 PMX_NFAD24_MASK | PMX_NFAD25_MASK | \ 192 PMX_NFAD24_MASK | PMX_NFAD25_MASK | \
193 PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \ 193 PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
194 PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \ 194 PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
195 PMX_NFCE3_MASK) 195 PMX_NFCE3_MASK)
196 #define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK 196 #define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK
197 197
198 #define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK) 198 #define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
199 #define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \ 199 #define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \
200 PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \ 200 PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \
201 PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \ 201 PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
202 PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK) 202 PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
203 203
204 #define PMX_MCIFALL_1_MASK 0xF8000000 204 #define PMX_MCIFALL_1_MASK 0xF8000000
205 #define PMX_MCIFALL_2_MASK 0x0FFFFFFF 205 #define PMX_MCIFALL_2_MASK 0x0FFFFFFF
206 206
207 #define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \ 207 #define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \
208 PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \ 208 PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
209 PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \ 209 PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
210 PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \ 210 PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
211 PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \ 211 PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \
212 PMX_NFCE2_MASK) 212 PMX_NFCE2_MASK)
213 #define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \ 213 #define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
214 PMX_SSP0_CS1_2_MASK) 214 PMX_SSP0_CS1_2_MASK)
215 215
216 #define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK) 216 #define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
217 #define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \ 217 #define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \
218 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \ 218 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
219 PMX_GMIID47_MASK) 219 PMX_GMIID47_MASK)
220 #define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\ 220 #define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
221 PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \ 221 PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \
222 PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK) 222 PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
223 #define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \ 223 #define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
224 PMX_SSP0_CS1_2_MASK) 224 PMX_SSP0_CS1_2_MASK)
225 225
226 #define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \ 226 #define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \
227 PCIE##x##_CFG_AUX_CLK_EN | \ 227 PCIE##x##_CFG_AUX_CLK_EN | \
228 PCIE##x##_CFG_CORE_CLK_EN | \ 228 PCIE##x##_CFG_CORE_CLK_EN | \
229 PCIE##x##_CFG_POWERUP_RESET | \ 229 PCIE##x##_CFG_POWERUP_RESET | \
230 PCIE##x##_CFG_DEVICE_PRESENT) 230 PCIE##x##_CFG_DEVICE_PRESENT)
231 #define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \ 231 #define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \
232 SATA##x##_CFG_PM_CLK_EN | \ 232 SATA##x##_CFG_PM_CLK_EN | \
233 SATA##x##_CFG_POWERUP_RESET | \ 233 SATA##x##_CFG_POWERUP_RESET | \
234 SATA##x##_CFG_RX_CLK_EN | \ 234 SATA##x##_CFG_RX_CLK_EN | \
235 SATA##x##_CFG_TX_CLK_EN) 235 SATA##x##_CFG_TX_CLK_EN)
236 236
237 /* Pad multiplexing for i2c0 device */ 237 /* Pad multiplexing for i2c0 device */
238 static const unsigned i2c0_pins[] = { 102, 103 }; 238 static const unsigned i2c0_pins[] = { 102, 103 };
239 static struct spear_muxreg i2c0_muxreg[] = { 239 static struct spear_muxreg i2c0_muxreg[] = {
240 { 240 {
241 .reg = PAD_FUNCTION_EN_0, 241 .reg = PAD_FUNCTION_EN_0,
242 .mask = PMX_I2C0_MASK, 242 .mask = PMX_I2C0_MASK,
243 .val = PMX_I2C0_MASK, 243 .val = PMX_I2C0_MASK,
244 }, { 244 }, {
245 .reg = PAD_DIRECTION_SEL_0, 245 .reg = PAD_DIRECTION_SEL_0,
246 .mask = PMX_I2C0_MASK, 246 .mask = PMX_I2C0_MASK,
247 .val = PMX_I2C0_MASK, 247 .val = PMX_I2C0_MASK,
248 }, 248 },
249 }; 249 };
250 250
251 static struct spear_modemux i2c0_modemux[] = { 251 static struct spear_modemux i2c0_modemux[] = {
252 { 252 {
253 .muxregs = i2c0_muxreg, 253 .muxregs = i2c0_muxreg,
254 .nmuxregs = ARRAY_SIZE(i2c0_muxreg), 254 .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
255 }, 255 },
256 }; 256 };
257 257
258 static struct spear_pingroup i2c0_pingroup = { 258 static struct spear_pingroup i2c0_pingroup = {
259 .name = "i2c0_grp", 259 .name = "i2c0_grp",
260 .pins = i2c0_pins, 260 .pins = i2c0_pins,
261 .npins = ARRAY_SIZE(i2c0_pins), 261 .npins = ARRAY_SIZE(i2c0_pins),
262 .modemuxs = i2c0_modemux, 262 .modemuxs = i2c0_modemux,
263 .nmodemuxs = ARRAY_SIZE(i2c0_modemux), 263 .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
264 }; 264 };
265 265
266 static const char *const i2c0_grps[] = { "i2c0_grp" }; 266 static const char *const i2c0_grps[] = { "i2c0_grp" };
267 static struct spear_function i2c0_function = { 267 static struct spear_function i2c0_function = {
268 .name = "i2c0", 268 .name = "i2c0",
269 .groups = i2c0_grps, 269 .groups = i2c0_grps,
270 .ngroups = ARRAY_SIZE(i2c0_grps), 270 .ngroups = ARRAY_SIZE(i2c0_grps),
271 }; 271 };
272 272
273 /* Pad multiplexing for ssp0 device */ 273 /* Pad multiplexing for ssp0 device */
274 static const unsigned ssp0_pins[] = { 109, 110, 111, 112 }; 274 static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
275 static struct spear_muxreg ssp0_muxreg[] = { 275 static struct spear_muxreg ssp0_muxreg[] = {
276 { 276 {
277 .reg = PAD_FUNCTION_EN_0, 277 .reg = PAD_FUNCTION_EN_0,
278 .mask = PMX_SSP0_MASK, 278 .mask = PMX_SSP0_MASK,
279 .val = PMX_SSP0_MASK, 279 .val = PMX_SSP0_MASK,
280 }, { 280 }, {
281 .reg = PAD_DIRECTION_SEL_0, 281 .reg = PAD_DIRECTION_SEL_0,
282 .mask = PMX_SSP0_MASK, 282 .mask = PMX_SSP0_MASK,
283 .val = PMX_SSP0_MASK, 283 .val = PMX_SSP0_MASK,
284 }, 284 },
285 }; 285 };
286 286
287 static struct spear_modemux ssp0_modemux[] = { 287 static struct spear_modemux ssp0_modemux[] = {
288 { 288 {
289 .muxregs = ssp0_muxreg, 289 .muxregs = ssp0_muxreg,
290 .nmuxregs = ARRAY_SIZE(ssp0_muxreg), 290 .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
291 }, 291 },
292 }; 292 };
293 293
294 static struct spear_pingroup ssp0_pingroup = { 294 static struct spear_pingroup ssp0_pingroup = {
295 .name = "ssp0_grp", 295 .name = "ssp0_grp",
296 .pins = ssp0_pins, 296 .pins = ssp0_pins,
297 .npins = ARRAY_SIZE(ssp0_pins), 297 .npins = ARRAY_SIZE(ssp0_pins),
298 .modemuxs = ssp0_modemux, 298 .modemuxs = ssp0_modemux,
299 .nmodemuxs = ARRAY_SIZE(ssp0_modemux), 299 .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
300 }; 300 };
301 301
302 /* Pad multiplexing for ssp0_cs0 device */ 302 /* Pad multiplexing for ssp0_cs0 device */
303 static const unsigned ssp0_cs0_pins[] = { 96 }; 303 static const unsigned ssp0_cs0_pins[] = { 96 };
304 static struct spear_muxreg ssp0_cs0_muxreg[] = { 304 static struct spear_muxreg ssp0_cs0_muxreg[] = {
305 { 305 {
306 .reg = PAD_FUNCTION_EN_2, 306 .reg = PAD_FUNCTION_EN_2,
307 .mask = PMX_SSP0_CS0_MASK, 307 .mask = PMX_SSP0_CS0_MASK,
308 .val = PMX_SSP0_CS0_MASK, 308 .val = PMX_SSP0_CS0_MASK,
309 }, { 309 }, {
310 .reg = PAD_DIRECTION_SEL_2, 310 .reg = PAD_DIRECTION_SEL_2,
311 .mask = PMX_SSP0_CS0_MASK, 311 .mask = PMX_SSP0_CS0_MASK,
312 .val = PMX_SSP0_CS0_MASK, 312 .val = PMX_SSP0_CS0_MASK,
313 }, 313 },
314 }; 314 };
315 315
316 static struct spear_modemux ssp0_cs0_modemux[] = { 316 static struct spear_modemux ssp0_cs0_modemux[] = {
317 { 317 {
318 .muxregs = ssp0_cs0_muxreg, 318 .muxregs = ssp0_cs0_muxreg,
319 .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg), 319 .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
320 }, 320 },
321 }; 321 };
322 322
323 static struct spear_pingroup ssp0_cs0_pingroup = { 323 static struct spear_pingroup ssp0_cs0_pingroup = {
324 .name = "ssp0_cs0_grp", 324 .name = "ssp0_cs0_grp",
325 .pins = ssp0_cs0_pins, 325 .pins = ssp0_cs0_pins,
326 .npins = ARRAY_SIZE(ssp0_cs0_pins), 326 .npins = ARRAY_SIZE(ssp0_cs0_pins),
327 .modemuxs = ssp0_cs0_modemux, 327 .modemuxs = ssp0_cs0_modemux,
328 .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux), 328 .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
329 }; 329 };
330 330
331 /* ssp0_cs1_2 device */ 331 /* ssp0_cs1_2 device */
332 static const unsigned ssp0_cs1_2_pins[] = { 94, 95 }; 332 static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
333 static struct spear_muxreg ssp0_cs1_2_muxreg[] = { 333 static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
334 { 334 {
335 .reg = PAD_FUNCTION_EN_2, 335 .reg = PAD_FUNCTION_EN_2,
336 .mask = PMX_SSP0_CS1_2_MASK, 336 .mask = PMX_SSP0_CS1_2_MASK,
337 .val = PMX_SSP0_CS1_2_MASK, 337 .val = PMX_SSP0_CS1_2_MASK,
338 }, { 338 }, {
339 .reg = PAD_DIRECTION_SEL_2, 339 .reg = PAD_DIRECTION_SEL_2,
340 .mask = PMX_SSP0_CS1_2_MASK, 340 .mask = PMX_SSP0_CS1_2_MASK,
341 .val = PMX_SSP0_CS1_2_MASK, 341 .val = PMX_SSP0_CS1_2_MASK,
342 }, 342 },
343 }; 343 };
344 344
345 static struct spear_modemux ssp0_cs1_2_modemux[] = { 345 static struct spear_modemux ssp0_cs1_2_modemux[] = {
346 { 346 {
347 .muxregs = ssp0_cs1_2_muxreg, 347 .muxregs = ssp0_cs1_2_muxreg,
348 .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg), 348 .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
349 }, 349 },
350 }; 350 };
351 351
352 static struct spear_pingroup ssp0_cs1_2_pingroup = { 352 static struct spear_pingroup ssp0_cs1_2_pingroup = {
353 .name = "ssp0_cs1_2_grp", 353 .name = "ssp0_cs1_2_grp",
354 .pins = ssp0_cs1_2_pins, 354 .pins = ssp0_cs1_2_pins,
355 .npins = ARRAY_SIZE(ssp0_cs1_2_pins), 355 .npins = ARRAY_SIZE(ssp0_cs1_2_pins),
356 .modemuxs = ssp0_cs1_2_modemux, 356 .modemuxs = ssp0_cs1_2_modemux,
357 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux), 357 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
358 }; 358 };
359 359
360 static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp", 360 static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
361 "ssp0_cs1_2_grp" }; 361 "ssp0_cs1_2_grp" };
362 static struct spear_function ssp0_function = { 362 static struct spear_function ssp0_function = {
363 .name = "ssp0", 363 .name = "ssp0",
364 .groups = ssp0_grps, 364 .groups = ssp0_grps,
365 .ngroups = ARRAY_SIZE(ssp0_grps), 365 .ngroups = ARRAY_SIZE(ssp0_grps),
366 }; 366 };
367 367
368 /* Pad multiplexing for i2s0 device */ 368 /* Pad multiplexing for i2s0 device */
369 static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 }; 369 static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
370 static struct spear_muxreg i2s0_muxreg[] = { 370 static struct spear_muxreg i2s0_muxreg[] = {
371 { 371 {
372 .reg = PAD_FUNCTION_EN_0, 372 .reg = PAD_FUNCTION_EN_0,
373 .mask = PMX_I2S0_MASK, 373 .mask = PMX_I2S0_MASK,
374 .val = PMX_I2S0_MASK, 374 .val = PMX_I2S0_MASK,
375 }, { 375 }, {
376 .reg = PAD_DIRECTION_SEL_0, 376 .reg = PAD_DIRECTION_SEL_0,
377 .mask = PMX_I2S0_MASK, 377 .mask = PMX_I2S0_MASK,
378 .val = PMX_I2S0_MASK, 378 .val = PMX_I2S0_MASK,
379 }, 379 },
380 }; 380 };
381 381
382 static struct spear_modemux i2s0_modemux[] = { 382 static struct spear_modemux i2s0_modemux[] = {
383 { 383 {
384 .muxregs = i2s0_muxreg, 384 .muxregs = i2s0_muxreg,
385 .nmuxregs = ARRAY_SIZE(i2s0_muxreg), 385 .nmuxregs = ARRAY_SIZE(i2s0_muxreg),
386 }, 386 },
387 }; 387 };
388 388
389 static struct spear_pingroup i2s0_pingroup = { 389 static struct spear_pingroup i2s0_pingroup = {
390 .name = "i2s0_grp", 390 .name = "i2s0_grp",
391 .pins = i2s0_pins, 391 .pins = i2s0_pins,
392 .npins = ARRAY_SIZE(i2s0_pins), 392 .npins = ARRAY_SIZE(i2s0_pins),
393 .modemuxs = i2s0_modemux, 393 .modemuxs = i2s0_modemux,
394 .nmodemuxs = ARRAY_SIZE(i2s0_modemux), 394 .nmodemuxs = ARRAY_SIZE(i2s0_modemux),
395 }; 395 };
396 396
397 static const char *const i2s0_grps[] = { "i2s0_grp" }; 397 static const char *const i2s0_grps[] = { "i2s0_grp" };
398 static struct spear_function i2s0_function = { 398 static struct spear_function i2s0_function = {
399 .name = "i2s0", 399 .name = "i2s0",
400 .groups = i2s0_grps, 400 .groups = i2s0_grps,
401 .ngroups = ARRAY_SIZE(i2s0_grps), 401 .ngroups = ARRAY_SIZE(i2s0_grps),
402 }; 402 };
403 403
404 /* Pad multiplexing for i2s1 device */ 404 /* Pad multiplexing for i2s1 device */
405 static const unsigned i2s1_pins[] = { 0, 1, 2, 3 }; 405 static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
406 static struct spear_muxreg i2s1_muxreg[] = { 406 static struct spear_muxreg i2s1_muxreg[] = {
407 { 407 {
408 .reg = PAD_FUNCTION_EN_1, 408 .reg = PAD_FUNCTION_EN_1,
409 .mask = PMX_I2S1_MASK, 409 .mask = PMX_I2S1_MASK,
410 .val = PMX_I2S1_MASK, 410 .val = PMX_I2S1_MASK,
411 }, { 411 }, {
412 .reg = PAD_DIRECTION_SEL_1, 412 .reg = PAD_DIRECTION_SEL_1,
413 .mask = PMX_I2S1_MASK, 413 .mask = PMX_I2S1_MASK,
414 .val = PMX_I2S1_MASK, 414 .val = PMX_I2S1_MASK,
415 }, 415 },
416 }; 416 };
417 417
418 static struct spear_modemux i2s1_modemux[] = { 418 static struct spear_modemux i2s1_modemux[] = {
419 { 419 {
420 .muxregs = i2s1_muxreg, 420 .muxregs = i2s1_muxreg,
421 .nmuxregs = ARRAY_SIZE(i2s1_muxreg), 421 .nmuxregs = ARRAY_SIZE(i2s1_muxreg),
422 }, 422 },
423 }; 423 };
424 424
425 static struct spear_pingroup i2s1_pingroup = { 425 static struct spear_pingroup i2s1_pingroup = {
426 .name = "i2s1_grp", 426 .name = "i2s1_grp",
427 .pins = i2s1_pins, 427 .pins = i2s1_pins,
428 .npins = ARRAY_SIZE(i2s1_pins), 428 .npins = ARRAY_SIZE(i2s1_pins),
429 .modemuxs = i2s1_modemux, 429 .modemuxs = i2s1_modemux,
430 .nmodemuxs = ARRAY_SIZE(i2s1_modemux), 430 .nmodemuxs = ARRAY_SIZE(i2s1_modemux),
431 }; 431 };
432 432
433 static const char *const i2s1_grps[] = { "i2s1_grp" }; 433 static const char *const i2s1_grps[] = { "i2s1_grp" };
434 static struct spear_function i2s1_function = { 434 static struct spear_function i2s1_function = {
435 .name = "i2s1", 435 .name = "i2s1",
436 .groups = i2s1_grps, 436 .groups = i2s1_grps,
437 .ngroups = ARRAY_SIZE(i2s1_grps), 437 .ngroups = ARRAY_SIZE(i2s1_grps),
438 }; 438 };
439 439
440 /* Pad multiplexing for clcd device */ 440 /* Pad multiplexing for clcd device */
441 static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120, 441 static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
442 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 442 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
443 135, 136, 137, 138, 139, 140, 141, 142 }; 443 135, 136, 137, 138, 139, 140, 141, 142 };
444 static struct spear_muxreg clcd_muxreg[] = { 444 static struct spear_muxreg clcd_muxreg[] = {
445 { 445 {
446 .reg = PAD_FUNCTION_EN_0, 446 .reg = PAD_FUNCTION_EN_0,
447 .mask = PMX_CLCD1_MASK, 447 .mask = PMX_CLCD1_MASK,
448 .val = PMX_CLCD1_MASK, 448 .val = PMX_CLCD1_MASK,
449 }, { 449 }, {
450 .reg = PAD_DIRECTION_SEL_0, 450 .reg = PAD_DIRECTION_SEL_0,
451 .mask = PMX_CLCD1_MASK, 451 .mask = PMX_CLCD1_MASK,
452 .val = PMX_CLCD1_MASK, 452 .val = PMX_CLCD1_MASK,
453 }, 453 },
454 }; 454 };
455 455
456 static struct spear_modemux clcd_modemux[] = { 456 static struct spear_modemux clcd_modemux[] = {
457 { 457 {
458 .muxregs = clcd_muxreg, 458 .muxregs = clcd_muxreg,
459 .nmuxregs = ARRAY_SIZE(clcd_muxreg), 459 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
460 }, 460 },
461 }; 461 };
462 462
463 static struct spear_pingroup clcd_pingroup = { 463 static struct spear_pingroup clcd_pingroup = {
464 .name = "clcd_grp", 464 .name = "clcd_grp",
465 .pins = clcd_pins, 465 .pins = clcd_pins,
466 .npins = ARRAY_SIZE(clcd_pins), 466 .npins = ARRAY_SIZE(clcd_pins),
467 .modemuxs = clcd_modemux, 467 .modemuxs = clcd_modemux,
468 .nmodemuxs = ARRAY_SIZE(clcd_modemux), 468 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
469 }; 469 };
470 470
471 static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37, 471 static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
472 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 }; 472 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
473 static struct spear_muxreg clcd_high_res_muxreg[] = { 473 static struct spear_muxreg clcd_high_res_muxreg[] = {
474 { 474 {
475 .reg = PAD_FUNCTION_EN_1, 475 .reg = PAD_FUNCTION_EN_1,
476 .mask = PMX_CLCD2_MASK, 476 .mask = PMX_CLCD2_MASK,
477 .val = PMX_CLCD2_MASK, 477 .val = PMX_CLCD2_MASK,
478 }, { 478 }, {
479 .reg = PAD_DIRECTION_SEL_1, 479 .reg = PAD_DIRECTION_SEL_1,
480 .mask = PMX_CLCD2_MASK, 480 .mask = PMX_CLCD2_MASK,
481 .val = PMX_CLCD2_MASK, 481 .val = PMX_CLCD2_MASK,
482 }, 482 },
483 }; 483 };
484 484
485 static struct spear_modemux clcd_high_res_modemux[] = { 485 static struct spear_modemux clcd_high_res_modemux[] = {
486 { 486 {
487 .muxregs = clcd_high_res_muxreg, 487 .muxregs = clcd_high_res_muxreg,
488 .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg), 488 .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
489 }, 489 },
490 }; 490 };
491 491
492 static struct spear_pingroup clcd_high_res_pingroup = { 492 static struct spear_pingroup clcd_high_res_pingroup = {
493 .name = "clcd_high_res_grp", 493 .name = "clcd_high_res_grp",
494 .pins = clcd_high_res_pins, 494 .pins = clcd_high_res_pins,
495 .npins = ARRAY_SIZE(clcd_high_res_pins), 495 .npins = ARRAY_SIZE(clcd_high_res_pins),
496 .modemuxs = clcd_high_res_modemux, 496 .modemuxs = clcd_high_res_modemux,
497 .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux), 497 .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
498 }; 498 };
499 499
500 static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res_grp" }; 500 static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res_grp" };
501 static struct spear_function clcd_function = { 501 static struct spear_function clcd_function = {
502 .name = "clcd", 502 .name = "clcd",
503 .groups = clcd_grps, 503 .groups = clcd_grps,
504 .ngroups = ARRAY_SIZE(clcd_grps), 504 .ngroups = ARRAY_SIZE(clcd_grps),
505 }; 505 };
506 506
507 static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145, 507 static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
508 146, 147, 148, 149, 150, 151, 152 }; 508 146, 147, 148, 149, 150, 151, 152 };
509 static struct spear_muxreg arm_gpio_muxreg[] = { 509 static struct spear_muxreg arm_gpio_muxreg[] = {
510 { 510 {
511 .reg = PAD_FUNCTION_EN_0, 511 .reg = PAD_FUNCTION_EN_0,
512 .mask = PMX_EGPIO_0_GRP_MASK, 512 .mask = PMX_EGPIO_0_GRP_MASK,
513 .val = PMX_EGPIO_0_GRP_MASK, 513 .val = PMX_EGPIO_0_GRP_MASK,
514 }, { 514 }, {
515 .reg = PAD_FUNCTION_EN_1, 515 .reg = PAD_FUNCTION_EN_1,
516 .mask = PMX_EGPIO_1_GRP_MASK, 516 .mask = PMX_EGPIO_1_GRP_MASK,
517 .val = PMX_EGPIO_1_GRP_MASK, 517 .val = PMX_EGPIO_1_GRP_MASK,
518 }, { 518 }, {
519 .reg = PAD_DIRECTION_SEL_0, 519 .reg = PAD_DIRECTION_SEL_0,
520 .mask = PMX_EGPIO_0_GRP_MASK, 520 .mask = PMX_EGPIO_0_GRP_MASK,
521 .val = PMX_EGPIO_0_GRP_MASK, 521 .val = PMX_EGPIO_0_GRP_MASK,
522 }, { 522 }, {
523 .reg = PAD_DIRECTION_SEL_1, 523 .reg = PAD_DIRECTION_SEL_1,
524 .mask = PMX_EGPIO_1_GRP_MASK, 524 .mask = PMX_EGPIO_1_GRP_MASK,
525 .val = PMX_EGPIO_1_GRP_MASK, 525 .val = PMX_EGPIO_1_GRP_MASK,
526 }, 526 },
527 }; 527 };
528 528
529 static struct spear_modemux arm_gpio_modemux[] = { 529 static struct spear_modemux arm_gpio_modemux[] = {
530 { 530 {
531 .muxregs = arm_gpio_muxreg, 531 .muxregs = arm_gpio_muxreg,
532 .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg), 532 .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
533 }, 533 },
534 }; 534 };
535 535
536 static struct spear_pingroup arm_gpio_pingroup = { 536 static struct spear_pingroup arm_gpio_pingroup = {
537 .name = "arm_gpio_grp", 537 .name = "arm_gpio_grp",
538 .pins = arm_gpio_pins, 538 .pins = arm_gpio_pins,
539 .npins = ARRAY_SIZE(arm_gpio_pins), 539 .npins = ARRAY_SIZE(arm_gpio_pins),
540 .modemuxs = arm_gpio_modemux, 540 .modemuxs = arm_gpio_modemux,
541 .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux), 541 .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
542 }; 542 };
543 543
544 static const char *const arm_gpio_grps[] = { "arm_gpio_grp" }; 544 static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
545 static struct spear_function arm_gpio_function = { 545 static struct spear_function arm_gpio_function = {
546 .name = "arm_gpio", 546 .name = "arm_gpio",
547 .groups = arm_gpio_grps, 547 .groups = arm_gpio_grps,
548 .ngroups = ARRAY_SIZE(arm_gpio_grps), 548 .ngroups = ARRAY_SIZE(arm_gpio_grps),
549 }; 549 };
550 550
551 /* Pad multiplexing for smi 2 chips device */ 551 /* Pad multiplexing for smi 2 chips device */
552 static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 }; 552 static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
553 static struct spear_muxreg smi_2_chips_muxreg[] = { 553 static struct spear_muxreg smi_2_chips_muxreg[] = {
554 { 554 {
555 .reg = PAD_FUNCTION_EN_0, 555 .reg = PAD_FUNCTION_EN_0,
556 .mask = PMX_SMI_MASK, 556 .mask = PMX_SMI_MASK,
557 .val = PMX_SMI_MASK, 557 .val = PMX_SMI_MASK,
558 }, { 558 }, {
559 .reg = PAD_DIRECTION_SEL_0, 559 .reg = PAD_DIRECTION_SEL_0,
560 .mask = PMX_SMI_MASK, 560 .mask = PMX_SMI_MASK,
561 .val = PMX_SMI_MASK, 561 .val = PMX_SMI_MASK,
562 }, 562 },
563 }; 563 };
564 564
565 static struct spear_modemux smi_2_chips_modemux[] = { 565 static struct spear_modemux smi_2_chips_modemux[] = {
566 { 566 {
567 .muxregs = smi_2_chips_muxreg, 567 .muxregs = smi_2_chips_muxreg,
568 .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg), 568 .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
569 }, 569 },
570 }; 570 };
571 571
572 static struct spear_pingroup smi_2_chips_pingroup = { 572 static struct spear_pingroup smi_2_chips_pingroup = {
573 .name = "smi_2_chips_grp", 573 .name = "smi_2_chips_grp",
574 .pins = smi_2_chips_pins, 574 .pins = smi_2_chips_pins,
575 .npins = ARRAY_SIZE(smi_2_chips_pins), 575 .npins = ARRAY_SIZE(smi_2_chips_pins),
576 .modemuxs = smi_2_chips_modemux, 576 .modemuxs = smi_2_chips_modemux,
577 .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux), 577 .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
578 }; 578 };
579 579
580 static const unsigned smi_4_chips_pins[] = { 54, 55 }; 580 static const unsigned smi_4_chips_pins[] = { 54, 55 };
581 static struct spear_muxreg smi_4_chips_muxreg[] = { 581 static struct spear_muxreg smi_4_chips_muxreg[] = {
582 { 582 {
583 .reg = PAD_FUNCTION_EN_0, 583 .reg = PAD_FUNCTION_EN_0,
584 .mask = PMX_SMI_MASK, 584 .mask = PMX_SMI_MASK,
585 .val = PMX_SMI_MASK, 585 .val = PMX_SMI_MASK,
586 }, { 586 }, {
587 .reg = PAD_FUNCTION_EN_1, 587 .reg = PAD_FUNCTION_EN_1,
588 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, 588 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
589 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, 589 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
590 }, { 590 }, {
591 .reg = PAD_DIRECTION_SEL_0, 591 .reg = PAD_DIRECTION_SEL_0,
592 .mask = PMX_SMI_MASK, 592 .mask = PMX_SMI_MASK,
593 .val = PMX_SMI_MASK, 593 .val = PMX_SMI_MASK,
594 }, { 594 }, {
595 .reg = PAD_DIRECTION_SEL_1, 595 .reg = PAD_DIRECTION_SEL_1,
596 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, 596 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
597 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, 597 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
598 }, 598 },
599 }; 599 };
600 600
601 static struct spear_modemux smi_4_chips_modemux[] = { 601 static struct spear_modemux smi_4_chips_modemux[] = {
602 { 602 {
603 .muxregs = smi_4_chips_muxreg, 603 .muxregs = smi_4_chips_muxreg,
604 .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg), 604 .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
605 }, 605 },
606 }; 606 };
607 607
608 static struct spear_pingroup smi_4_chips_pingroup = { 608 static struct spear_pingroup smi_4_chips_pingroup = {
609 .name = "smi_4_chips_grp", 609 .name = "smi_4_chips_grp",
610 .pins = smi_4_chips_pins, 610 .pins = smi_4_chips_pins,
611 .npins = ARRAY_SIZE(smi_4_chips_pins), 611 .npins = ARRAY_SIZE(smi_4_chips_pins),
612 .modemuxs = smi_4_chips_modemux, 612 .modemuxs = smi_4_chips_modemux,
613 .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux), 613 .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
614 }; 614 };
615 615
616 static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" }; 616 static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
617 static struct spear_function smi_function = { 617 static struct spear_function smi_function = {
618 .name = "smi", 618 .name = "smi",
619 .groups = smi_grps, 619 .groups = smi_grps,
620 .ngroups = ARRAY_SIZE(smi_grps), 620 .ngroups = ARRAY_SIZE(smi_grps),
621 }; 621 };
622 622
623 /* Pad multiplexing for gmii device */ 623 /* Pad multiplexing for gmii device */
624 static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180, 624 static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
625 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 625 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
626 195, 196, 197, 198, 199, 200 }; 626 195, 196, 197, 198, 199, 200 };
627 static struct spear_muxreg gmii_muxreg[] = { 627 static struct spear_muxreg gmii_muxreg[] = {
628 { 628 {
629 .reg = PAD_FUNCTION_EN_0, 629 .reg = PAD_FUNCTION_EN_0,
630 .mask = PMX_GMII_MASK, 630 .mask = PMX_GMII_MASK,
631 .val = PMX_GMII_MASK, 631 .val = PMX_GMII_MASK,
632 }, { 632 }, {
633 .reg = PAD_DIRECTION_SEL_0, 633 .reg = PAD_DIRECTION_SEL_0,
634 .mask = PMX_GMII_MASK, 634 .mask = PMX_GMII_MASK,
635 .val = PMX_GMII_MASK, 635 .val = PMX_GMII_MASK,
636 }, 636 },
637 }; 637 };
638 638
639 static struct spear_modemux gmii_modemux[] = { 639 static struct spear_modemux gmii_modemux[] = {
640 { 640 {
641 .muxregs = gmii_muxreg, 641 .muxregs = gmii_muxreg,
642 .nmuxregs = ARRAY_SIZE(gmii_muxreg), 642 .nmuxregs = ARRAY_SIZE(gmii_muxreg),
643 }, 643 },
644 }; 644 };
645 645
646 static struct spear_pingroup gmii_pingroup = { 646 static struct spear_pingroup gmii_pingroup = {
647 .name = "gmii_grp", 647 .name = "gmii_grp",
648 .pins = gmii_pins, 648 .pins = gmii_pins,
649 .npins = ARRAY_SIZE(gmii_pins), 649 .npins = ARRAY_SIZE(gmii_pins),
650 .modemuxs = gmii_modemux, 650 .modemuxs = gmii_modemux,
651 .nmodemuxs = ARRAY_SIZE(gmii_modemux), 651 .nmodemuxs = ARRAY_SIZE(gmii_modemux),
652 }; 652 };
653 653
654 static const char *const gmii_grps[] = { "gmii_grp" }; 654 static const char *const gmii_grps[] = { "gmii_grp" };
655 static struct spear_function gmii_function = { 655 static struct spear_function gmii_function = {
656 .name = "gmii", 656 .name = "gmii",
657 .groups = gmii_grps, 657 .groups = gmii_grps,
658 .ngroups = ARRAY_SIZE(gmii_grps), 658 .ngroups = ARRAY_SIZE(gmii_grps),
659 }; 659 };
660 660
661 /* Pad multiplexing for rgmii device */ 661 /* Pad multiplexing for rgmii device */
662 static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 662 static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
663 28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175, 663 28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
664 180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 }; 664 180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
665 static struct spear_muxreg rgmii_muxreg[] = { 665 static struct spear_muxreg rgmii_muxreg[] = {
666 { 666 {
667 .reg = PAD_FUNCTION_EN_0, 667 .reg = PAD_FUNCTION_EN_0,
668 .mask = PMX_RGMII_REG0_MASK, 668 .mask = PMX_RGMII_REG0_MASK,
669 .val = 0, 669 .val = 0,
670 }, { 670 }, {
671 .reg = PAD_FUNCTION_EN_1, 671 .reg = PAD_FUNCTION_EN_1,
672 .mask = PMX_RGMII_REG1_MASK, 672 .mask = PMX_RGMII_REG1_MASK,
673 .val = 0, 673 .val = 0,
674 }, { 674 }, {
675 .reg = PAD_FUNCTION_EN_2, 675 .reg = PAD_FUNCTION_EN_2,
676 .mask = PMX_RGMII_REG2_MASK, 676 .mask = PMX_RGMII_REG2_MASK,
677 .val = 0, 677 .val = 0,
678 }, { 678 }, {
679 .reg = PAD_DIRECTION_SEL_0, 679 .reg = PAD_DIRECTION_SEL_0,
680 .mask = PMX_RGMII_REG0_MASK, 680 .mask = PMX_RGMII_REG0_MASK,
681 .val = PMX_RGMII_REG0_MASK, 681 .val = PMX_RGMII_REG0_MASK,
682 }, { 682 }, {
683 .reg = PAD_DIRECTION_SEL_1, 683 .reg = PAD_DIRECTION_SEL_1,
684 .mask = PMX_RGMII_REG1_MASK, 684 .mask = PMX_RGMII_REG1_MASK,
685 .val = PMX_RGMII_REG1_MASK, 685 .val = PMX_RGMII_REG1_MASK,
686 }, { 686 }, {
687 .reg = PAD_DIRECTION_SEL_2, 687 .reg = PAD_DIRECTION_SEL_2,
688 .mask = PMX_RGMII_REG2_MASK, 688 .mask = PMX_RGMII_REG2_MASK,
689 .val = PMX_RGMII_REG2_MASK, 689 .val = PMX_RGMII_REG2_MASK,
690 }, 690 },
691 }; 691 };
692 692
693 static struct spear_modemux rgmii_modemux[] = { 693 static struct spear_modemux rgmii_modemux[] = {
694 { 694 {
695 .muxregs = rgmii_muxreg, 695 .muxregs = rgmii_muxreg,
696 .nmuxregs = ARRAY_SIZE(rgmii_muxreg), 696 .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
697 }, 697 },
698 }; 698 };
699 699
700 static struct spear_pingroup rgmii_pingroup = { 700 static struct spear_pingroup rgmii_pingroup = {
701 .name = "rgmii_grp", 701 .name = "rgmii_grp",
702 .pins = rgmii_pins, 702 .pins = rgmii_pins,
703 .npins = ARRAY_SIZE(rgmii_pins), 703 .npins = ARRAY_SIZE(rgmii_pins),
704 .modemuxs = rgmii_modemux, 704 .modemuxs = rgmii_modemux,
705 .nmodemuxs = ARRAY_SIZE(rgmii_modemux), 705 .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
706 }; 706 };
707 707
708 static const char *const rgmii_grps[] = { "rgmii_grp" }; 708 static const char *const rgmii_grps[] = { "rgmii_grp" };
709 static struct spear_function rgmii_function = { 709 static struct spear_function rgmii_function = {
710 .name = "rgmii", 710 .name = "rgmii",
711 .groups = rgmii_grps, 711 .groups = rgmii_grps,
712 .ngroups = ARRAY_SIZE(rgmii_grps), 712 .ngroups = ARRAY_SIZE(rgmii_grps),
713 }; 713 };
714 714
715 /* Pad multiplexing for smii_0_1_2 device */ 715 /* Pad multiplexing for smii_0_1_2 device */
716 static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32, 716 static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
717 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 717 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
718 51, 52, 53, 54, 55 }; 718 51, 52, 53, 54, 55 };
719 static struct spear_muxreg smii_0_1_2_muxreg[] = { 719 static struct spear_muxreg smii_0_1_2_muxreg[] = {
720 { 720 {
721 .reg = PAD_FUNCTION_EN_1, 721 .reg = PAD_FUNCTION_EN_1,
722 .mask = PMX_SMII_0_1_2_MASK, 722 .mask = PMX_SMII_0_1_2_MASK,
723 .val = 0, 723 .val = 0,
724 }, { 724 }, {
725 .reg = PAD_DIRECTION_SEL_1, 725 .reg = PAD_DIRECTION_SEL_1,
726 .mask = PMX_SMII_0_1_2_MASK, 726 .mask = PMX_SMII_0_1_2_MASK,
727 .val = PMX_SMII_0_1_2_MASK, 727 .val = PMX_SMII_0_1_2_MASK,
728 }, 728 },
729 }; 729 };
730 730
731 static struct spear_modemux smii_0_1_2_modemux[] = { 731 static struct spear_modemux smii_0_1_2_modemux[] = {
732 { 732 {
733 .muxregs = smii_0_1_2_muxreg, 733 .muxregs = smii_0_1_2_muxreg,
734 .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg), 734 .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
735 }, 735 },
736 }; 736 };
737 737
738 static struct spear_pingroup smii_0_1_2_pingroup = { 738 static struct spear_pingroup smii_0_1_2_pingroup = {
739 .name = "smii_0_1_2_grp", 739 .name = "smii_0_1_2_grp",
740 .pins = smii_0_1_2_pins, 740 .pins = smii_0_1_2_pins,
741 .npins = ARRAY_SIZE(smii_0_1_2_pins), 741 .npins = ARRAY_SIZE(smii_0_1_2_pins),
742 .modemuxs = smii_0_1_2_modemux, 742 .modemuxs = smii_0_1_2_modemux,
743 .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux), 743 .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
744 }; 744 };
745 745
746 static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" }; 746 static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
747 static struct spear_function smii_0_1_2_function = { 747 static struct spear_function smii_0_1_2_function = {
748 .name = "smii_0_1_2", 748 .name = "smii_0_1_2",
749 .groups = smii_0_1_2_grps, 749 .groups = smii_0_1_2_grps,
750 .ngroups = ARRAY_SIZE(smii_0_1_2_grps), 750 .ngroups = ARRAY_SIZE(smii_0_1_2_grps),
751 }; 751 };
752 752
753 /* Pad multiplexing for ras_mii_txclk device */ 753 /* Pad multiplexing for ras_mii_txclk device */
754 static const unsigned ras_mii_txclk_pins[] = { 98, 99 }; 754 static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
755 static struct spear_muxreg ras_mii_txclk_muxreg[] = { 755 static struct spear_muxreg ras_mii_txclk_muxreg[] = {
756 { 756 {
757 .reg = PAD_FUNCTION_EN_1, 757 .reg = PAD_FUNCTION_EN_1,
758 .mask = PMX_NFCE2_MASK, 758 .mask = PMX_NFCE2_MASK,
759 .val = 0, 759 .val = 0,
760 }, { 760 }, {
761 .reg = PAD_DIRECTION_SEL_1, 761 .reg = PAD_DIRECTION_SEL_1,
762 .mask = PMX_NFCE2_MASK, 762 .mask = PMX_NFCE2_MASK,
763 .val = PMX_NFCE2_MASK, 763 .val = PMX_NFCE2_MASK,
764 }, 764 },
765 }; 765 };
766 766
767 static struct spear_modemux ras_mii_txclk_modemux[] = { 767 static struct spear_modemux ras_mii_txclk_modemux[] = {
768 { 768 {
769 .muxregs = ras_mii_txclk_muxreg, 769 .muxregs = ras_mii_txclk_muxreg,
770 .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg), 770 .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
771 }, 771 },
772 }; 772 };
773 773
774 static struct spear_pingroup ras_mii_txclk_pingroup = { 774 static struct spear_pingroup ras_mii_txclk_pingroup = {
775 .name = "ras_mii_txclk_grp", 775 .name = "ras_mii_txclk_grp",
776 .pins = ras_mii_txclk_pins, 776 .pins = ras_mii_txclk_pins,
777 .npins = ARRAY_SIZE(ras_mii_txclk_pins), 777 .npins = ARRAY_SIZE(ras_mii_txclk_pins),
778 .modemuxs = ras_mii_txclk_modemux, 778 .modemuxs = ras_mii_txclk_modemux,
779 .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux), 779 .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
780 }; 780 };
781 781
782 static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" }; 782 static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
783 static struct spear_function ras_mii_txclk_function = { 783 static struct spear_function ras_mii_txclk_function = {
784 .name = "ras_mii_txclk", 784 .name = "ras_mii_txclk",
785 .groups = ras_mii_txclk_grps, 785 .groups = ras_mii_txclk_grps,
786 .ngroups = ARRAY_SIZE(ras_mii_txclk_grps), 786 .ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
787 }; 787 };
788 788
789 /* Pad multiplexing for nand 8bit device (cs0 only) */ 789 /* Pad multiplexing for nand 8bit device (cs0 only) */
790 static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64, 790 static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
791 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 791 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
792 83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 792 83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
793 170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 793 170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
794 212 }; 794 212 };
795 static struct spear_muxreg nand_8bit_muxreg[] = { 795 static struct spear_muxreg nand_8bit_muxreg[] = {
796 { 796 {
797 .reg = PAD_FUNCTION_EN_0, 797 .reg = PAD_FUNCTION_EN_0,
798 .mask = PMX_NAND8BIT_0_MASK, 798 .mask = PMX_NAND8BIT_0_MASK,
799 .val = PMX_NAND8BIT_0_MASK, 799 .val = PMX_NAND8BIT_0_MASK,
800 }, { 800 }, {
801 .reg = PAD_FUNCTION_EN_1, 801 .reg = PAD_FUNCTION_EN_1,
802 .mask = PMX_NAND8BIT_1_MASK, 802 .mask = PMX_NAND8BIT_1_MASK,
803 .val = PMX_NAND8BIT_1_MASK, 803 .val = PMX_NAND8BIT_1_MASK,
804 }, { 804 }, {
805 .reg = PAD_DIRECTION_SEL_0, 805 .reg = PAD_DIRECTION_SEL_0,
806 .mask = PMX_NAND8BIT_0_MASK, 806 .mask = PMX_NAND8BIT_0_MASK,
807 .val = PMX_NAND8BIT_0_MASK, 807 .val = PMX_NAND8BIT_0_MASK,
808 }, { 808 }, {
809 .reg = PAD_DIRECTION_SEL_1, 809 .reg = PAD_DIRECTION_SEL_1,
810 .mask = PMX_NAND8BIT_1_MASK, 810 .mask = PMX_NAND8BIT_1_MASK,
811 .val = PMX_NAND8BIT_1_MASK, 811 .val = PMX_NAND8BIT_1_MASK,
812 }, 812 },
813 }; 813 };
814 814
815 static struct spear_modemux nand_8bit_modemux[] = { 815 static struct spear_modemux nand_8bit_modemux[] = {
816 { 816 {
817 .muxregs = nand_8bit_muxreg, 817 .muxregs = nand_8bit_muxreg,
818 .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg), 818 .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
819 }, 819 },
820 }; 820 };
821 821
822 static struct spear_pingroup nand_8bit_pingroup = { 822 static struct spear_pingroup nand_8bit_pingroup = {
823 .name = "nand_8bit_grp", 823 .name = "nand_8bit_grp",
824 .pins = nand_8bit_pins, 824 .pins = nand_8bit_pins,
825 .npins = ARRAY_SIZE(nand_8bit_pins), 825 .npins = ARRAY_SIZE(nand_8bit_pins),
826 .modemuxs = nand_8bit_modemux, 826 .modemuxs = nand_8bit_modemux,
827 .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux), 827 .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
828 }; 828 };
829 829
830 /* Pad multiplexing for nand 16bit device */ 830 /* Pad multiplexing for nand 16bit device */
831 static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209, 831 static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
832 210 }; 832 210 };
833 static struct spear_muxreg nand_16bit_muxreg[] = { 833 static struct spear_muxreg nand_16bit_muxreg[] = {
834 { 834 {
835 .reg = PAD_FUNCTION_EN_1, 835 .reg = PAD_FUNCTION_EN_1,
836 .mask = PMX_NAND16BIT_1_MASK, 836 .mask = PMX_NAND16BIT_1_MASK,
837 .val = PMX_NAND16BIT_1_MASK, 837 .val = PMX_NAND16BIT_1_MASK,
838 }, { 838 }, {
839 .reg = PAD_DIRECTION_SEL_1, 839 .reg = PAD_DIRECTION_SEL_1,
840 .mask = PMX_NAND16BIT_1_MASK, 840 .mask = PMX_NAND16BIT_1_MASK,
841 .val = PMX_NAND16BIT_1_MASK, 841 .val = PMX_NAND16BIT_1_MASK,
842 }, 842 },
843 }; 843 };
844 844
845 static struct spear_modemux nand_16bit_modemux[] = { 845 static struct spear_modemux nand_16bit_modemux[] = {
846 { 846 {
847 .muxregs = nand_16bit_muxreg, 847 .muxregs = nand_16bit_muxreg,
848 .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg), 848 .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
849 }, 849 },
850 }; 850 };
851 851
852 static struct spear_pingroup nand_16bit_pingroup = { 852 static struct spear_pingroup nand_16bit_pingroup = {
853 .name = "nand_16bit_grp", 853 .name = "nand_16bit_grp",
854 .pins = nand_16bit_pins, 854 .pins = nand_16bit_pins,
855 .npins = ARRAY_SIZE(nand_16bit_pins), 855 .npins = ARRAY_SIZE(nand_16bit_pins),
856 .modemuxs = nand_16bit_modemux, 856 .modemuxs = nand_16bit_modemux,
857 .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux), 857 .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
858 }; 858 };
859 859
860 /* Pad multiplexing for nand 4 chips */ 860 /* Pad multiplexing for nand 4 chips */
861 static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 }; 861 static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
862 static struct spear_muxreg nand_4_chips_muxreg[] = { 862 static struct spear_muxreg nand_4_chips_muxreg[] = {
863 { 863 {
864 .reg = PAD_FUNCTION_EN_1, 864 .reg = PAD_FUNCTION_EN_1,
865 .mask = PMX_NAND_4CHIPS_MASK, 865 .mask = PMX_NAND_4CHIPS_MASK,
866 .val = PMX_NAND_4CHIPS_MASK, 866 .val = PMX_NAND_4CHIPS_MASK,
867 }, { 867 }, {
868 .reg = PAD_DIRECTION_SEL_1, 868 .reg = PAD_DIRECTION_SEL_1,
869 .mask = PMX_NAND_4CHIPS_MASK, 869 .mask = PMX_NAND_4CHIPS_MASK,
870 .val = PMX_NAND_4CHIPS_MASK, 870 .val = PMX_NAND_4CHIPS_MASK,
871 }, 871 },
872 }; 872 };
873 873
874 static struct spear_modemux nand_4_chips_modemux[] = { 874 static struct spear_modemux nand_4_chips_modemux[] = {
875 { 875 {
876 .muxregs = nand_4_chips_muxreg, 876 .muxregs = nand_4_chips_muxreg,
877 .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg), 877 .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
878 }, 878 },
879 }; 879 };
880 880
881 static struct spear_pingroup nand_4_chips_pingroup = { 881 static struct spear_pingroup nand_4_chips_pingroup = {
882 .name = "nand_4_chips_grp", 882 .name = "nand_4_chips_grp",
883 .pins = nand_4_chips_pins, 883 .pins = nand_4_chips_pins,
884 .npins = ARRAY_SIZE(nand_4_chips_pins), 884 .npins = ARRAY_SIZE(nand_4_chips_pins),
885 .modemuxs = nand_4_chips_modemux, 885 .modemuxs = nand_4_chips_modemux,
886 .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux), 886 .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
887 }; 887 };
888 888
889 static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp", 889 static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
890 "nand_4_chips_grp" }; 890 "nand_4_chips_grp" };
891 static struct spear_function nand_function = { 891 static struct spear_function nand_function = {
892 .name = "nand", 892 .name = "nand",
893 .groups = nand_grps, 893 .groups = nand_grps,
894 .ngroups = ARRAY_SIZE(nand_grps), 894 .ngroups = ARRAY_SIZE(nand_grps),
895 }; 895 };
896 896
897 /* Pad multiplexing for keyboard_6x6 device */ 897 /* Pad multiplexing for keyboard_6x6 device */
898 static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207, 898 static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
899 208, 209, 210, 211, 212 }; 899 208, 209, 210, 211, 212 };
900 static struct spear_muxreg keyboard_6x6_muxreg[] = { 900 static struct spear_muxreg keyboard_6x6_muxreg[] = {
901 { 901 {
902 .reg = PAD_FUNCTION_EN_1, 902 .reg = PAD_FUNCTION_EN_1,
903 .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK | 903 .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
904 PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK | 904 PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
905 PMX_NFWPRT2_MASK, 905 PMX_NFWPRT2_MASK,
906 .val = PMX_KEYBOARD_6X6_MASK, 906 .val = PMX_KEYBOARD_6X6_MASK,
907 }, 907 },
908 }; 908 };
909 909
910 static struct spear_modemux keyboard_6x6_modemux[] = { 910 static struct spear_modemux keyboard_6x6_modemux[] = {
911 { 911 {
912 .muxregs = keyboard_6x6_muxreg, 912 .muxregs = keyboard_6x6_muxreg,
913 .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg), 913 .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
914 }, 914 },
915 }; 915 };
916 916
917 static struct spear_pingroup keyboard_6x6_pingroup = { 917 static struct spear_pingroup keyboard_6x6_pingroup = {
918 .name = "keyboard_6x6_grp", 918 .name = "keyboard_6x6_grp",
919 .pins = keyboard_6x6_pins, 919 .pins = keyboard_6x6_pins,
920 .npins = ARRAY_SIZE(keyboard_6x6_pins), 920 .npins = ARRAY_SIZE(keyboard_6x6_pins),
921 .modemuxs = keyboard_6x6_modemux, 921 .modemuxs = keyboard_6x6_modemux,
922 .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux), 922 .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
923 }; 923 };
924 924
925 /* Pad multiplexing for keyboard_rowcol6_8 device */ 925 /* Pad multiplexing for keyboard_rowcol6_8 device */
926 static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 }; 926 static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
927 static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = { 927 static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
928 { 928 {
929 .reg = PAD_FUNCTION_EN_1, 929 .reg = PAD_FUNCTION_EN_1,
930 .mask = PMX_KBD_ROWCOL68_MASK, 930 .mask = PMX_KBD_ROWCOL68_MASK,
931 .val = PMX_KBD_ROWCOL68_MASK, 931 .val = PMX_KBD_ROWCOL68_MASK,
932 }, { 932 }, {
933 .reg = PAD_DIRECTION_SEL_1, 933 .reg = PAD_DIRECTION_SEL_1,
934 .mask = PMX_KBD_ROWCOL68_MASK, 934 .mask = PMX_KBD_ROWCOL68_MASK,
935 .val = PMX_KBD_ROWCOL68_MASK, 935 .val = PMX_KBD_ROWCOL68_MASK,
936 }, 936 },
937 }; 937 };
938 938
939 static struct spear_modemux keyboard_rowcol6_8_modemux[] = { 939 static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
940 { 940 {
941 .muxregs = keyboard_rowcol6_8_muxreg, 941 .muxregs = keyboard_rowcol6_8_muxreg,
942 .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg), 942 .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
943 }, 943 },
944 }; 944 };
945 945
946 static struct spear_pingroup keyboard_rowcol6_8_pingroup = { 946 static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
947 .name = "keyboard_rowcol6_8_grp", 947 .name = "keyboard_rowcol6_8_grp",
948 .pins = keyboard_rowcol6_8_pins, 948 .pins = keyboard_rowcol6_8_pins,
949 .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins), 949 .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
950 .modemuxs = keyboard_rowcol6_8_modemux, 950 .modemuxs = keyboard_rowcol6_8_modemux,
951 .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux), 951 .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
952 }; 952 };
953 953
954 static const char *const keyboard_grps[] = { "keyboard_6x6_grp", 954 static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
955 "keyboard_rowcol6_8_grp" }; 955 "keyboard_rowcol6_8_grp" };
956 static struct spear_function keyboard_function = { 956 static struct spear_function keyboard_function = {
957 .name = "keyboard", 957 .name = "keyboard",
958 .groups = keyboard_grps, 958 .groups = keyboard_grps,
959 .ngroups = ARRAY_SIZE(keyboard_grps), 959 .ngroups = ARRAY_SIZE(keyboard_grps),
960 }; 960 };
961 961
962 /* Pad multiplexing for uart0 device */ 962 /* Pad multiplexing for uart0 device */
963 static const unsigned uart0_pins[] = { 100, 101 }; 963 static const unsigned uart0_pins[] = { 100, 101 };
964 static struct spear_muxreg uart0_muxreg[] = { 964 static struct spear_muxreg uart0_muxreg[] = {
965 { 965 {
966 .reg = PAD_FUNCTION_EN_0, 966 .reg = PAD_FUNCTION_EN_0,
967 .mask = PMX_UART0_MASK, 967 .mask = PMX_UART0_MASK,
968 .val = PMX_UART0_MASK, 968 .val = PMX_UART0_MASK,
969 }, { 969 }, {
970 .reg = PAD_DIRECTION_SEL_0, 970 .reg = PAD_DIRECTION_SEL_0,
971 .mask = PMX_UART0_MASK, 971 .mask = PMX_UART0_MASK,
972 .val = PMX_UART0_MASK, 972 .val = PMX_UART0_MASK,
973 }, 973 },
974 }; 974 };
975 975
976 static struct spear_modemux uart0_modemux[] = { 976 static struct spear_modemux uart0_modemux[] = {
977 { 977 {
978 .muxregs = uart0_muxreg, 978 .muxregs = uart0_muxreg,
979 .nmuxregs = ARRAY_SIZE(uart0_muxreg), 979 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
980 }, 980 },
981 }; 981 };
982 982
983 static struct spear_pingroup uart0_pingroup = { 983 static struct spear_pingroup uart0_pingroup = {
984 .name = "uart0_grp", 984 .name = "uart0_grp",
985 .pins = uart0_pins, 985 .pins = uart0_pins,
986 .npins = ARRAY_SIZE(uart0_pins), 986 .npins = ARRAY_SIZE(uart0_pins),
987 .modemuxs = uart0_modemux, 987 .modemuxs = uart0_modemux,
988 .nmodemuxs = ARRAY_SIZE(uart0_modemux), 988 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
989 }; 989 };
990 990
991 /* Pad multiplexing for uart0_modem device */ 991 /* Pad multiplexing for uart0_modem device */
992 static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 }; 992 static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
993 static struct spear_muxreg uart0_modem_muxreg[] = { 993 static struct spear_muxreg uart0_modem_muxreg[] = {
994 { 994 {
995 .reg = PAD_FUNCTION_EN_1, 995 .reg = PAD_FUNCTION_EN_1,
996 .mask = PMX_UART0_MODEM_MASK, 996 .mask = PMX_UART0_MODEM_MASK,
997 .val = PMX_UART0_MODEM_MASK, 997 .val = PMX_UART0_MODEM_MASK,
998 }, { 998 }, {
999 .reg = PAD_DIRECTION_SEL_1, 999 .reg = PAD_DIRECTION_SEL_1,
1000 .mask = PMX_UART0_MODEM_MASK, 1000 .mask = PMX_UART0_MODEM_MASK,
1001 .val = PMX_UART0_MODEM_MASK, 1001 .val = PMX_UART0_MODEM_MASK,
1002 }, 1002 },
1003 }; 1003 };
1004 1004
1005 static struct spear_modemux uart0_modem_modemux[] = { 1005 static struct spear_modemux uart0_modem_modemux[] = {
1006 { 1006 {
1007 .muxregs = uart0_modem_muxreg, 1007 .muxregs = uart0_modem_muxreg,
1008 .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg), 1008 .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
1009 }, 1009 },
1010 }; 1010 };
1011 1011
1012 static struct spear_pingroup uart0_modem_pingroup = { 1012 static struct spear_pingroup uart0_modem_pingroup = {
1013 .name = "uart0_modem_grp", 1013 .name = "uart0_modem_grp",
1014 .pins = uart0_modem_pins, 1014 .pins = uart0_modem_pins,
1015 .npins = ARRAY_SIZE(uart0_modem_pins), 1015 .npins = ARRAY_SIZE(uart0_modem_pins),
1016 .modemuxs = uart0_modem_modemux, 1016 .modemuxs = uart0_modem_modemux,
1017 .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux), 1017 .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
1018 }; 1018 };
1019 1019
1020 static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" }; 1020 static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
1021 static struct spear_function uart0_function = { 1021 static struct spear_function uart0_function = {
1022 .name = "uart0", 1022 .name = "uart0",
1023 .groups = uart0_grps, 1023 .groups = uart0_grps,
1024 .ngroups = ARRAY_SIZE(uart0_grps), 1024 .ngroups = ARRAY_SIZE(uart0_grps),
1025 }; 1025 };
1026 1026
1027 /* Pad multiplexing for gpt0_tmr0 device */ 1027 /* Pad multiplexing for gpt0_tmr0 device */
1028 static const unsigned gpt0_tmr0_pins[] = { 10, 11 }; 1028 static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
1029 static struct spear_muxreg gpt0_tmr0_muxreg[] = { 1029 static struct spear_muxreg gpt0_tmr0_muxreg[] = {
1030 { 1030 {
1031 .reg = PAD_FUNCTION_EN_1, 1031 .reg = PAD_FUNCTION_EN_1,
1032 .mask = PMX_GPT0_TMR0_MASK, 1032 .mask = PMX_GPT0_TMR0_MASK,
1033 .val = PMX_GPT0_TMR0_MASK, 1033 .val = PMX_GPT0_TMR0_MASK,
1034 }, { 1034 }, {
1035 .reg = PAD_DIRECTION_SEL_1, 1035 .reg = PAD_DIRECTION_SEL_1,
1036 .mask = PMX_GPT0_TMR0_MASK, 1036 .mask = PMX_GPT0_TMR0_MASK,
1037 .val = PMX_GPT0_TMR0_MASK, 1037 .val = PMX_GPT0_TMR0_MASK,
1038 }, 1038 },
1039 }; 1039 };
1040 1040
1041 static struct spear_modemux gpt0_tmr0_modemux[] = { 1041 static struct spear_modemux gpt0_tmr0_modemux[] = {
1042 { 1042 {
1043 .muxregs = gpt0_tmr0_muxreg, 1043 .muxregs = gpt0_tmr0_muxreg,
1044 .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg), 1044 .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
1045 }, 1045 },
1046 }; 1046 };
1047 1047
1048 static struct spear_pingroup gpt0_tmr0_pingroup = { 1048 static struct spear_pingroup gpt0_tmr0_pingroup = {
1049 .name = "gpt0_tmr0_grp", 1049 .name = "gpt0_tmr0_grp",
1050 .pins = gpt0_tmr0_pins, 1050 .pins = gpt0_tmr0_pins,
1051 .npins = ARRAY_SIZE(gpt0_tmr0_pins), 1051 .npins = ARRAY_SIZE(gpt0_tmr0_pins),
1052 .modemuxs = gpt0_tmr0_modemux, 1052 .modemuxs = gpt0_tmr0_modemux,
1053 .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux), 1053 .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
1054 }; 1054 };
1055 1055
1056 /* Pad multiplexing for gpt0_tmr1 device */ 1056 /* Pad multiplexing for gpt0_tmr1 device */
1057 static const unsigned gpt0_tmr1_pins[] = { 8, 9 }; 1057 static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
1058 static struct spear_muxreg gpt0_tmr1_muxreg[] = { 1058 static struct spear_muxreg gpt0_tmr1_muxreg[] = {
1059 { 1059 {
1060 .reg = PAD_FUNCTION_EN_1, 1060 .reg = PAD_FUNCTION_EN_1,
1061 .mask = PMX_GPT0_TMR1_MASK, 1061 .mask = PMX_GPT0_TMR1_MASK,
1062 .val = PMX_GPT0_TMR1_MASK, 1062 .val = PMX_GPT0_TMR1_MASK,
1063 }, { 1063 }, {
1064 .reg = PAD_DIRECTION_SEL_1, 1064 .reg = PAD_DIRECTION_SEL_1,
1065 .mask = PMX_GPT0_TMR1_MASK, 1065 .mask = PMX_GPT0_TMR1_MASK,
1066 .val = PMX_GPT0_TMR1_MASK, 1066 .val = PMX_GPT0_TMR1_MASK,
1067 }, 1067 },
1068 }; 1068 };
1069 1069
1070 static struct spear_modemux gpt0_tmr1_modemux[] = { 1070 static struct spear_modemux gpt0_tmr1_modemux[] = {
1071 { 1071 {
1072 .muxregs = gpt0_tmr1_muxreg, 1072 .muxregs = gpt0_tmr1_muxreg,
1073 .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg), 1073 .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
1074 }, 1074 },
1075 }; 1075 };
1076 1076
1077 static struct spear_pingroup gpt0_tmr1_pingroup = { 1077 static struct spear_pingroup gpt0_tmr1_pingroup = {
1078 .name = "gpt0_tmr1_grp", 1078 .name = "gpt0_tmr1_grp",
1079 .pins = gpt0_tmr1_pins, 1079 .pins = gpt0_tmr1_pins,
1080 .npins = ARRAY_SIZE(gpt0_tmr1_pins), 1080 .npins = ARRAY_SIZE(gpt0_tmr1_pins),
1081 .modemuxs = gpt0_tmr1_modemux, 1081 .modemuxs = gpt0_tmr1_modemux,
1082 .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux), 1082 .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
1083 }; 1083 };
1084 1084
1085 static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" }; 1085 static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
1086 static struct spear_function gpt0_function = { 1086 static struct spear_function gpt0_function = {
1087 .name = "gpt0", 1087 .name = "gpt0",
1088 .groups = gpt0_grps, 1088 .groups = gpt0_grps,
1089 .ngroups = ARRAY_SIZE(gpt0_grps), 1089 .ngroups = ARRAY_SIZE(gpt0_grps),
1090 }; 1090 };
1091 1091
1092 /* Pad multiplexing for gpt1_tmr0 device */ 1092 /* Pad multiplexing for gpt1_tmr0 device */
1093 static const unsigned gpt1_tmr0_pins[] = { 6, 7 }; 1093 static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
1094 static struct spear_muxreg gpt1_tmr0_muxreg[] = { 1094 static struct spear_muxreg gpt1_tmr0_muxreg[] = {
1095 { 1095 {
1096 .reg = PAD_FUNCTION_EN_1, 1096 .reg = PAD_FUNCTION_EN_1,
1097 .mask = PMX_GPT1_TMR0_MASK, 1097 .mask = PMX_GPT1_TMR0_MASK,
1098 .val = PMX_GPT1_TMR0_MASK, 1098 .val = PMX_GPT1_TMR0_MASK,
1099 }, { 1099 }, {
1100 .reg = PAD_DIRECTION_SEL_1, 1100 .reg = PAD_DIRECTION_SEL_1,
1101 .mask = PMX_GPT1_TMR0_MASK, 1101 .mask = PMX_GPT1_TMR0_MASK,
1102 .val = PMX_GPT1_TMR0_MASK, 1102 .val = PMX_GPT1_TMR0_MASK,
1103 }, 1103 },
1104 }; 1104 };
1105 1105
1106 static struct spear_modemux gpt1_tmr0_modemux[] = { 1106 static struct spear_modemux gpt1_tmr0_modemux[] = {
1107 { 1107 {
1108 .muxregs = gpt1_tmr0_muxreg, 1108 .muxregs = gpt1_tmr0_muxreg,
1109 .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg), 1109 .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
1110 }, 1110 },
1111 }; 1111 };
1112 1112
1113 static struct spear_pingroup gpt1_tmr0_pingroup = { 1113 static struct spear_pingroup gpt1_tmr0_pingroup = {
1114 .name = "gpt1_tmr0_grp", 1114 .name = "gpt1_tmr0_grp",
1115 .pins = gpt1_tmr0_pins, 1115 .pins = gpt1_tmr0_pins,
1116 .npins = ARRAY_SIZE(gpt1_tmr0_pins), 1116 .npins = ARRAY_SIZE(gpt1_tmr0_pins),
1117 .modemuxs = gpt1_tmr0_modemux, 1117 .modemuxs = gpt1_tmr0_modemux,
1118 .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux), 1118 .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
1119 }; 1119 };
1120 1120
1121 /* Pad multiplexing for gpt1_tmr1 device */ 1121 /* Pad multiplexing for gpt1_tmr1 device */
1122 static const unsigned gpt1_tmr1_pins[] = { 4, 5 }; 1122 static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
1123 static struct spear_muxreg gpt1_tmr1_muxreg[] = { 1123 static struct spear_muxreg gpt1_tmr1_muxreg[] = {
1124 { 1124 {
1125 .reg = PAD_FUNCTION_EN_1, 1125 .reg = PAD_FUNCTION_EN_1,
1126 .mask = PMX_GPT1_TMR1_MASK, 1126 .mask = PMX_GPT1_TMR1_MASK,
1127 .val = PMX_GPT1_TMR1_MASK, 1127 .val = PMX_GPT1_TMR1_MASK,
1128 }, { 1128 }, {
1129 .reg = PAD_DIRECTION_SEL_1, 1129 .reg = PAD_DIRECTION_SEL_1,
1130 .mask = PMX_GPT1_TMR1_MASK, 1130 .mask = PMX_GPT1_TMR1_MASK,
1131 .val = PMX_GPT1_TMR1_MASK, 1131 .val = PMX_GPT1_TMR1_MASK,
1132 }, 1132 },
1133 }; 1133 };
1134 1134
1135 static struct spear_modemux gpt1_tmr1_modemux[] = { 1135 static struct spear_modemux gpt1_tmr1_modemux[] = {
1136 { 1136 {
1137 .muxregs = gpt1_tmr1_muxreg, 1137 .muxregs = gpt1_tmr1_muxreg,
1138 .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg), 1138 .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
1139 }, 1139 },
1140 }; 1140 };
1141 1141
1142 static struct spear_pingroup gpt1_tmr1_pingroup = { 1142 static struct spear_pingroup gpt1_tmr1_pingroup = {
1143 .name = "gpt1_tmr1_grp", 1143 .name = "gpt1_tmr1_grp",
1144 .pins = gpt1_tmr1_pins, 1144 .pins = gpt1_tmr1_pins,
1145 .npins = ARRAY_SIZE(gpt1_tmr1_pins), 1145 .npins = ARRAY_SIZE(gpt1_tmr1_pins),
1146 .modemuxs = gpt1_tmr1_modemux, 1146 .modemuxs = gpt1_tmr1_modemux,
1147 .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux), 1147 .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
1148 }; 1148 };
1149 1149
1150 static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" }; 1150 static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
1151 static struct spear_function gpt1_function = { 1151 static struct spear_function gpt1_function = {
1152 .name = "gpt1", 1152 .name = "gpt1",
1153 .groups = gpt1_grps, 1153 .groups = gpt1_grps,
1154 .ngroups = ARRAY_SIZE(gpt1_grps), 1154 .ngroups = ARRAY_SIZE(gpt1_grps),
1155 }; 1155 };
1156 1156
1157 /* Pad multiplexing for mcif device */ 1157 /* Pad multiplexing for mcif device */
1158 static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214, 1158 static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
1159 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 1159 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
1160 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 1160 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
1161 243, 244, 245 }; 1161 243, 244, 245 };
1162 #define MCIF_MUXREG \ 1162 #define MCIF_MUXREG \
1163 { \ 1163 { \
1164 .reg = PAD_FUNCTION_EN_0, \ 1164 .reg = PAD_FUNCTION_EN_0, \
1165 .mask = PMX_MCI_DATA8_15_MASK, \ 1165 .mask = PMX_MCI_DATA8_15_MASK, \
1166 .val = PMX_MCI_DATA8_15_MASK, \ 1166 .val = PMX_MCI_DATA8_15_MASK, \
1167 }, { \ 1167 }, { \
1168 .reg = PAD_FUNCTION_EN_1, \ 1168 .reg = PAD_FUNCTION_EN_1, \
1169 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ 1169 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1170 PMX_NFWPRT2_MASK, \ 1170 PMX_NFWPRT2_MASK, \
1171 .val = PMX_MCIFALL_1_MASK, \ 1171 .val = PMX_MCIFALL_1_MASK, \
1172 }, { \ 1172 }, { \
1173 .reg = PAD_FUNCTION_EN_2, \ 1173 .reg = PAD_FUNCTION_EN_2, \
1174 .mask = PMX_MCIFALL_2_MASK, \ 1174 .mask = PMX_MCIFALL_2_MASK, \
1175 .val = PMX_MCIFALL_2_MASK, \ 1175 .val = PMX_MCIFALL_2_MASK, \
1176 }, { \ 1176 }, { \
1177 .reg = PAD_DIRECTION_SEL_0, \ 1177 .reg = PAD_DIRECTION_SEL_0, \
1178 .mask = PMX_MCI_DATA8_15_MASK, \ 1178 .mask = PMX_MCI_DATA8_15_MASK, \
1179 .val = PMX_MCI_DATA8_15_MASK, \ 1179 .val = PMX_MCI_DATA8_15_MASK, \
1180 }, { \ 1180 }, { \
1181 .reg = PAD_DIRECTION_SEL_1, \ 1181 .reg = PAD_DIRECTION_SEL_1, \
1182 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ 1182 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1183 PMX_NFWPRT2_MASK, \ 1183 PMX_NFWPRT2_MASK, \
1184 .val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ 1184 .val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1185 PMX_NFWPRT2_MASK, \ 1185 PMX_NFWPRT2_MASK, \
1186 }, { \ 1186 }, { \
1187 .reg = PAD_DIRECTION_SEL_2, \ 1187 .reg = PAD_DIRECTION_SEL_2, \
1188 .mask = PMX_MCIFALL_2_MASK, \ 1188 .mask = PMX_MCIFALL_2_MASK, \
1189 .val = PMX_MCIFALL_2_MASK, \ 1189 .val = PMX_MCIFALL_2_MASK, \
1190 } 1190 }
1191 1191
1192 /* sdhci device */ 1192 /* sdhci device */
1193 static struct spear_muxreg sdhci_muxreg[] = { 1193 static struct spear_muxreg sdhci_muxreg[] = {
1194 MCIF_MUXREG, 1194 MCIF_MUXREG,
1195 { 1195 {
1196 .reg = PERIP_CFG, 1196 .reg = PERIP_CFG,
1197 .mask = MCIF_SEL_MASK, 1197 .mask = MCIF_SEL_MASK,
1198 .val = MCIF_SEL_SD, 1198 .val = MCIF_SEL_SD,
1199 }, 1199 },
1200 }; 1200 };
1201 1201
1202 static struct spear_modemux sdhci_modemux[] = { 1202 static struct spear_modemux sdhci_modemux[] = {
1203 { 1203 {
1204 .muxregs = sdhci_muxreg, 1204 .muxregs = sdhci_muxreg,
1205 .nmuxregs = ARRAY_SIZE(sdhci_muxreg), 1205 .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
1206 }, 1206 },
1207 }; 1207 };
1208 1208
1209 static struct spear_pingroup sdhci_pingroup = { 1209 static struct spear_pingroup sdhci_pingroup = {
1210 .name = "sdhci_grp", 1210 .name = "sdhci_grp",
1211 .pins = mcif_pins, 1211 .pins = mcif_pins,
1212 .npins = ARRAY_SIZE(mcif_pins), 1212 .npins = ARRAY_SIZE(mcif_pins),
1213 .modemuxs = sdhci_modemux, 1213 .modemuxs = sdhci_modemux,
1214 .nmodemuxs = ARRAY_SIZE(sdhci_modemux), 1214 .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
1215 }; 1215 };
1216 1216
1217 static const char *const sdhci_grps[] = { "sdhci_grp" }; 1217 static const char *const sdhci_grps[] = { "sdhci_grp" };
1218 static struct spear_function sdhci_function = { 1218 static struct spear_function sdhci_function = {
1219 .name = "sdhci", 1219 .name = "sdhci",
1220 .groups = sdhci_grps, 1220 .groups = sdhci_grps,
1221 .ngroups = ARRAY_SIZE(sdhci_grps), 1221 .ngroups = ARRAY_SIZE(sdhci_grps),
1222 }; 1222 };
1223 1223
1224 /* cf device */ 1224 /* cf device */
1225 static struct spear_muxreg cf_muxreg[] = { 1225 static struct spear_muxreg cf_muxreg[] = {
1226 MCIF_MUXREG, 1226 MCIF_MUXREG,
1227 { 1227 {
1228 .reg = PERIP_CFG, 1228 .reg = PERIP_CFG,
1229 .mask = MCIF_SEL_MASK, 1229 .mask = MCIF_SEL_MASK,
1230 .val = MCIF_SEL_CF, 1230 .val = MCIF_SEL_CF,
1231 }, 1231 },
1232 }; 1232 };
1233 1233
1234 static struct spear_modemux cf_modemux[] = { 1234 static struct spear_modemux cf_modemux[] = {
1235 { 1235 {
1236 .muxregs = cf_muxreg, 1236 .muxregs = cf_muxreg,
1237 .nmuxregs = ARRAY_SIZE(cf_muxreg), 1237 .nmuxregs = ARRAY_SIZE(cf_muxreg),
1238 }, 1238 },
1239 }; 1239 };
1240 1240
1241 static struct spear_pingroup cf_pingroup = { 1241 static struct spear_pingroup cf_pingroup = {
1242 .name = "cf_grp", 1242 .name = "cf_grp",
1243 .pins = mcif_pins, 1243 .pins = mcif_pins,
1244 .npins = ARRAY_SIZE(mcif_pins), 1244 .npins = ARRAY_SIZE(mcif_pins),
1245 .modemuxs = cf_modemux, 1245 .modemuxs = cf_modemux,
1246 .nmodemuxs = ARRAY_SIZE(cf_modemux), 1246 .nmodemuxs = ARRAY_SIZE(cf_modemux),
1247 }; 1247 };
1248 1248
1249 static const char *const cf_grps[] = { "cf_grp" }; 1249 static const char *const cf_grps[] = { "cf_grp" };
1250 static struct spear_function cf_function = { 1250 static struct spear_function cf_function = {
1251 .name = "cf", 1251 .name = "cf",
1252 .groups = cf_grps, 1252 .groups = cf_grps,
1253 .ngroups = ARRAY_SIZE(cf_grps), 1253 .ngroups = ARRAY_SIZE(cf_grps),
1254 }; 1254 };
1255 1255
1256 /* xd device */ 1256 /* xd device */
1257 static struct spear_muxreg xd_muxreg[] = { 1257 static struct spear_muxreg xd_muxreg[] = {
1258 MCIF_MUXREG, 1258 MCIF_MUXREG,
1259 { 1259 {
1260 .reg = PERIP_CFG, 1260 .reg = PERIP_CFG,
1261 .mask = MCIF_SEL_MASK, 1261 .mask = MCIF_SEL_MASK,
1262 .val = MCIF_SEL_XD, 1262 .val = MCIF_SEL_XD,
1263 }, 1263 },
1264 }; 1264 };
1265 1265
1266 static struct spear_modemux xd_modemux[] = { 1266 static struct spear_modemux xd_modemux[] = {
1267 { 1267 {
1268 .muxregs = xd_muxreg, 1268 .muxregs = xd_muxreg,
1269 .nmuxregs = ARRAY_SIZE(xd_muxreg), 1269 .nmuxregs = ARRAY_SIZE(xd_muxreg),
1270 }, 1270 },
1271 }; 1271 };
1272 1272
1273 static struct spear_pingroup xd_pingroup = { 1273 static struct spear_pingroup xd_pingroup = {
1274 .name = "xd_grp", 1274 .name = "xd_grp",
1275 .pins = mcif_pins, 1275 .pins = mcif_pins,
1276 .npins = ARRAY_SIZE(mcif_pins), 1276 .npins = ARRAY_SIZE(mcif_pins),
1277 .modemuxs = xd_modemux, 1277 .modemuxs = xd_modemux,
1278 .nmodemuxs = ARRAY_SIZE(xd_modemux), 1278 .nmodemuxs = ARRAY_SIZE(xd_modemux),
1279 }; 1279 };
1280 1280
1281 static const char *const xd_grps[] = { "xd_grp" }; 1281 static const char *const xd_grps[] = { "xd_grp" };
1282 static struct spear_function xd_function = { 1282 static struct spear_function xd_function = {
1283 .name = "xd", 1283 .name = "xd",
1284 .groups = xd_grps, 1284 .groups = xd_grps,
1285 .ngroups = ARRAY_SIZE(xd_grps), 1285 .ngroups = ARRAY_SIZE(xd_grps),
1286 }; 1286 };
1287 1287
1288 /* Pad multiplexing for touch_xy device */ 1288 /* Pad multiplexing for touch_xy device */
1289 static const unsigned touch_xy_pins[] = { 97 }; 1289 static const unsigned touch_xy_pins[] = { 97 };
1290 static struct spear_muxreg touch_xy_muxreg[] = { 1290 static struct spear_muxreg touch_xy_muxreg[] = {
1291 { 1291 {
1292 .reg = PAD_FUNCTION_EN_2, 1292 .reg = PAD_FUNCTION_EN_2,
1293 .mask = PMX_TOUCH_XY_MASK, 1293 .mask = PMX_TOUCH_XY_MASK,
1294 .val = PMX_TOUCH_XY_MASK, 1294 .val = PMX_TOUCH_XY_MASK,
1295 }, { 1295 }, {
1296 .reg = PAD_DIRECTION_SEL_2, 1296 .reg = PAD_DIRECTION_SEL_2,
1297 .mask = PMX_TOUCH_XY_MASK, 1297 .mask = PMX_TOUCH_XY_MASK,
1298 .val = PMX_TOUCH_XY_MASK, 1298 .val = PMX_TOUCH_XY_MASK,
1299 }, 1299 },
1300 }; 1300 };
1301 1301
1302 static struct spear_modemux touch_xy_modemux[] = { 1302 static struct spear_modemux touch_xy_modemux[] = {
1303 { 1303 {
1304 .muxregs = touch_xy_muxreg, 1304 .muxregs = touch_xy_muxreg,
1305 .nmuxregs = ARRAY_SIZE(touch_xy_muxreg), 1305 .nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
1306 }, 1306 },
1307 }; 1307 };
1308 1308
1309 static struct spear_pingroup touch_xy_pingroup = { 1309 static struct spear_pingroup touch_xy_pingroup = {
1310 .name = "touch_xy_grp", 1310 .name = "touch_xy_grp",
1311 .pins = touch_xy_pins, 1311 .pins = touch_xy_pins,
1312 .npins = ARRAY_SIZE(touch_xy_pins), 1312 .npins = ARRAY_SIZE(touch_xy_pins),
1313 .modemuxs = touch_xy_modemux, 1313 .modemuxs = touch_xy_modemux,
1314 .nmodemuxs = ARRAY_SIZE(touch_xy_modemux), 1314 .nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
1315 }; 1315 };
1316 1316
1317 static const char *const touch_xy_grps[] = { "touch_xy_grp" }; 1317 static const char *const touch_xy_grps[] = { "touch_xy_grp" };
1318 static struct spear_function touch_xy_function = { 1318 static struct spear_function touch_xy_function = {
1319 .name = "touchscreen", 1319 .name = "touchscreen",
1320 .groups = touch_xy_grps, 1320 .groups = touch_xy_grps,
1321 .ngroups = ARRAY_SIZE(touch_xy_grps), 1321 .ngroups = ARRAY_SIZE(touch_xy_grps),
1322 }; 1322 };
1323 1323
1324 /* Pad multiplexing for uart1 device */ 1324 /* Pad multiplexing for uart1 device */
1325 /* Muxed with I2C */ 1325 /* Muxed with I2C */
1326 static const unsigned uart1_dis_i2c_pins[] = { 102, 103 }; 1326 static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
1327 static struct spear_muxreg uart1_dis_i2c_muxreg[] = { 1327 static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
1328 { 1328 {
1329 .reg = PAD_FUNCTION_EN_0, 1329 .reg = PAD_FUNCTION_EN_0,
1330 .mask = PMX_I2C0_MASK, 1330 .mask = PMX_I2C0_MASK,
1331 .val = 0, 1331 .val = 0,
1332 }, { 1332 }, {
1333 .reg = PAD_DIRECTION_SEL_0, 1333 .reg = PAD_DIRECTION_SEL_0,
1334 .mask = PMX_I2C0_MASK, 1334 .mask = PMX_I2C0_MASK,
1335 .val = PMX_I2C0_MASK, 1335 .val = PMX_I2C0_MASK,
1336 }, 1336 },
1337 }; 1337 };
1338 1338
1339 static struct spear_modemux uart1_dis_i2c_modemux[] = { 1339 static struct spear_modemux uart1_dis_i2c_modemux[] = {
1340 { 1340 {
1341 .muxregs = uart1_dis_i2c_muxreg, 1341 .muxregs = uart1_dis_i2c_muxreg,
1342 .nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg), 1342 .nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
1343 }, 1343 },
1344 }; 1344 };
1345 1345
1346 static struct spear_pingroup uart_1_dis_i2c_pingroup = { 1346 static struct spear_pingroup uart_1_dis_i2c_pingroup = {
1347 .name = "uart1_disable_i2c_grp", 1347 .name = "uart1_disable_i2c_grp",
1348 .pins = uart1_dis_i2c_pins, 1348 .pins = uart1_dis_i2c_pins,
1349 .npins = ARRAY_SIZE(uart1_dis_i2c_pins), 1349 .npins = ARRAY_SIZE(uart1_dis_i2c_pins),
1350 .modemuxs = uart1_dis_i2c_modemux, 1350 .modemuxs = uart1_dis_i2c_modemux,
1351 .nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux), 1351 .nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
1352 }; 1352 };
1353 1353
1354 /* Muxed with SD/MMC */ 1354 /* Muxed with SD/MMC */
1355 static const unsigned uart1_dis_sd_pins[] = { 214, 215 }; 1355 static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
1356 static struct spear_muxreg uart1_dis_sd_muxreg[] = { 1356 static struct spear_muxreg uart1_dis_sd_muxreg[] = {
1357 { 1357 {
1358 .reg = PAD_FUNCTION_EN_1, 1358 .reg = PAD_FUNCTION_EN_1,
1359 .mask = PMX_MCIDATA1_MASK | 1359 .mask = PMX_MCIDATA1_MASK |
1360 PMX_MCIDATA2_MASK, 1360 PMX_MCIDATA2_MASK,
1361 .val = 0, 1361 .val = 0,
1362 }, { 1362 }, {
1363 .reg = PAD_DIRECTION_SEL_1, 1363 .reg = PAD_DIRECTION_SEL_1,
1364 .mask = PMX_MCIDATA1_MASK | 1364 .mask = PMX_MCIDATA1_MASK |
1365 PMX_MCIDATA2_MASK, 1365 PMX_MCIDATA2_MASK,
1366 .val = PMX_MCIDATA1_MASK | 1366 .val = PMX_MCIDATA1_MASK |
1367 PMX_MCIDATA2_MASK, 1367 PMX_MCIDATA2_MASK,
1368 }, 1368 },
1369 }; 1369 };
1370 1370
1371 static struct spear_modemux uart1_dis_sd_modemux[] = { 1371 static struct spear_modemux uart1_dis_sd_modemux[] = {
1372 { 1372 {
1373 .muxregs = uart1_dis_sd_muxreg, 1373 .muxregs = uart1_dis_sd_muxreg,
1374 .nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg), 1374 .nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
1375 }, 1375 },
1376 }; 1376 };
1377 1377
1378 static struct spear_pingroup uart_1_dis_sd_pingroup = { 1378 static struct spear_pingroup uart_1_dis_sd_pingroup = {
1379 .name = "uart1_disable_sd_grp", 1379 .name = "uart1_disable_sd_grp",
1380 .pins = uart1_dis_sd_pins, 1380 .pins = uart1_dis_sd_pins,
1381 .npins = ARRAY_SIZE(uart1_dis_sd_pins), 1381 .npins = ARRAY_SIZE(uart1_dis_sd_pins),
1382 .modemuxs = uart1_dis_sd_modemux, 1382 .modemuxs = uart1_dis_sd_modemux,
1383 .nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux), 1383 .nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
1384 }; 1384 };
1385 1385
1386 static const char *const uart1_grps[] = { "uart1_disable_i2c_grp", 1386 static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
1387 "uart1_disable_sd_grp" }; 1387 "uart1_disable_sd_grp" };
1388 static struct spear_function uart1_function = { 1388 static struct spear_function uart1_function = {
1389 .name = "uart1", 1389 .name = "uart1",
1390 .groups = uart1_grps, 1390 .groups = uart1_grps,
1391 .ngroups = ARRAY_SIZE(uart1_grps), 1391 .ngroups = ARRAY_SIZE(uart1_grps),
1392 }; 1392 };
1393 1393
1394 /* Pad multiplexing for uart2_3 device */ 1394 /* Pad multiplexing for uart2_3 device */
1395 static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 }; 1395 static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
1396 static struct spear_muxreg uart2_3_muxreg[] = { 1396 static struct spear_muxreg uart2_3_muxreg[] = {
1397 { 1397 {
1398 .reg = PAD_FUNCTION_EN_0, 1398 .reg = PAD_FUNCTION_EN_0,
1399 .mask = PMX_I2S0_MASK, 1399 .mask = PMX_I2S0_MASK,
1400 .val = 0, 1400 .val = 0,
1401 }, { 1401 }, {
1402 .reg = PAD_DIRECTION_SEL_0, 1402 .reg = PAD_DIRECTION_SEL_0,
1403 .mask = PMX_I2S0_MASK, 1403 .mask = PMX_I2S0_MASK,
1404 .val = PMX_I2S0_MASK, 1404 .val = PMX_I2S0_MASK,
1405 }, 1405 },
1406 }; 1406 };
1407 1407
1408 static struct spear_modemux uart2_3_modemux[] = { 1408 static struct spear_modemux uart2_3_modemux[] = {
1409 { 1409 {
1410 .muxregs = uart2_3_muxreg, 1410 .muxregs = uart2_3_muxreg,
1411 .nmuxregs = ARRAY_SIZE(uart2_3_muxreg), 1411 .nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
1412 }, 1412 },
1413 }; 1413 };
1414 1414
1415 static struct spear_pingroup uart_2_3_pingroup = { 1415 static struct spear_pingroup uart_2_3_pingroup = {
1416 .name = "uart2_3_grp", 1416 .name = "uart2_3_grp",
1417 .pins = uart2_3_pins, 1417 .pins = uart2_3_pins,
1418 .npins = ARRAY_SIZE(uart2_3_pins), 1418 .npins = ARRAY_SIZE(uart2_3_pins),
1419 .modemuxs = uart2_3_modemux, 1419 .modemuxs = uart2_3_modemux,
1420 .nmodemuxs = ARRAY_SIZE(uart2_3_modemux), 1420 .nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
1421 }; 1421 };
1422 1422
1423 static const char *const uart2_3_grps[] = { "uart2_3_grp" }; 1423 static const char *const uart2_3_grps[] = { "uart2_3_grp" };
1424 static struct spear_function uart2_3_function = { 1424 static struct spear_function uart2_3_function = {
1425 .name = "uart2_3", 1425 .name = "uart2_3",
1426 .groups = uart2_3_grps, 1426 .groups = uart2_3_grps,
1427 .ngroups = ARRAY_SIZE(uart2_3_grps), 1427 .ngroups = ARRAY_SIZE(uart2_3_grps),
1428 }; 1428 };
1429 1429
1430 /* Pad multiplexing for uart4 device */ 1430 /* Pad multiplexing for uart4 device */
1431 static const unsigned uart4_pins[] = { 108, 113 }; 1431 static const unsigned uart4_pins[] = { 108, 113 };
1432 static struct spear_muxreg uart4_muxreg[] = { 1432 static struct spear_muxreg uart4_muxreg[] = {
1433 { 1433 {
1434 .reg = PAD_FUNCTION_EN_0, 1434 .reg = PAD_FUNCTION_EN_0,
1435 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK, 1435 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1436 .val = 0, 1436 .val = 0,
1437 }, { 1437 }, {
1438 .reg = PAD_DIRECTION_SEL_0, 1438 .reg = PAD_DIRECTION_SEL_0,
1439 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK, 1439 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1440 .val = PMX_I2S0_MASK | PMX_CLCD1_MASK, 1440 .val = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1441 }, 1441 },
1442 }; 1442 };
1443 1443
1444 static struct spear_modemux uart4_modemux[] = { 1444 static struct spear_modemux uart4_modemux[] = {
1445 { 1445 {
1446 .muxregs = uart4_muxreg, 1446 .muxregs = uart4_muxreg,
1447 .nmuxregs = ARRAY_SIZE(uart4_muxreg), 1447 .nmuxregs = ARRAY_SIZE(uart4_muxreg),
1448 }, 1448 },
1449 }; 1449 };
1450 1450
1451 static struct spear_pingroup uart_4_pingroup = { 1451 static struct spear_pingroup uart_4_pingroup = {
1452 .name = "uart4_grp", 1452 .name = "uart4_grp",
1453 .pins = uart4_pins, 1453 .pins = uart4_pins,
1454 .npins = ARRAY_SIZE(uart4_pins), 1454 .npins = ARRAY_SIZE(uart4_pins),
1455 .modemuxs = uart4_modemux, 1455 .modemuxs = uart4_modemux,
1456 .nmodemuxs = ARRAY_SIZE(uart4_modemux), 1456 .nmodemuxs = ARRAY_SIZE(uart4_modemux),
1457 }; 1457 };
1458 1458
1459 static const char *const uart4_grps[] = { "uart4_grp" }; 1459 static const char *const uart4_grps[] = { "uart4_grp" };
1460 static struct spear_function uart4_function = { 1460 static struct spear_function uart4_function = {
1461 .name = "uart4", 1461 .name = "uart4",
1462 .groups = uart4_grps, 1462 .groups = uart4_grps,
1463 .ngroups = ARRAY_SIZE(uart4_grps), 1463 .ngroups = ARRAY_SIZE(uart4_grps),
1464 }; 1464 };
1465 1465
1466 /* Pad multiplexing for uart5 device */ 1466 /* Pad multiplexing for uart5 device */
1467 static const unsigned uart5_pins[] = { 114, 115 }; 1467 static const unsigned uart5_pins[] = { 114, 115 };
1468 static struct spear_muxreg uart5_muxreg[] = { 1468 static struct spear_muxreg uart5_muxreg[] = {
1469 { 1469 {
1470 .reg = PAD_FUNCTION_EN_0, 1470 .reg = PAD_FUNCTION_EN_0,
1471 .mask = PMX_CLCD1_MASK, 1471 .mask = PMX_CLCD1_MASK,
1472 .val = 0, 1472 .val = 0,
1473 }, { 1473 }, {
1474 .reg = PAD_DIRECTION_SEL_0, 1474 .reg = PAD_DIRECTION_SEL_0,
1475 .mask = PMX_CLCD1_MASK, 1475 .mask = PMX_CLCD1_MASK,
1476 .val = PMX_CLCD1_MASK, 1476 .val = PMX_CLCD1_MASK,
1477 }, 1477 },
1478 }; 1478 };
1479 1479
1480 static struct spear_modemux uart5_modemux[] = { 1480 static struct spear_modemux uart5_modemux[] = {
1481 { 1481 {
1482 .muxregs = uart5_muxreg, 1482 .muxregs = uart5_muxreg,
1483 .nmuxregs = ARRAY_SIZE(uart5_muxreg), 1483 .nmuxregs = ARRAY_SIZE(uart5_muxreg),
1484 }, 1484 },
1485 }; 1485 };
1486 1486
1487 static struct spear_pingroup uart_5_pingroup = { 1487 static struct spear_pingroup uart_5_pingroup = {
1488 .name = "uart5_grp", 1488 .name = "uart5_grp",
1489 .pins = uart5_pins, 1489 .pins = uart5_pins,
1490 .npins = ARRAY_SIZE(uart5_pins), 1490 .npins = ARRAY_SIZE(uart5_pins),
1491 .modemuxs = uart5_modemux, 1491 .modemuxs = uart5_modemux,
1492 .nmodemuxs = ARRAY_SIZE(uart5_modemux), 1492 .nmodemuxs = ARRAY_SIZE(uart5_modemux),
1493 }; 1493 };
1494 1494
1495 static const char *const uart5_grps[] = { "uart5_grp" }; 1495 static const char *const uart5_grps[] = { "uart5_grp" };
1496 static struct spear_function uart5_function = { 1496 static struct spear_function uart5_function = {
1497 .name = "uart5", 1497 .name = "uart5",
1498 .groups = uart5_grps, 1498 .groups = uart5_grps,
1499 .ngroups = ARRAY_SIZE(uart5_grps), 1499 .ngroups = ARRAY_SIZE(uart5_grps),
1500 }; 1500 };
1501 1501
1502 /* Pad multiplexing for rs485_0_1_tdm_0_1 device */ 1502 /* Pad multiplexing for rs485_0_1_tdm_0_1 device */
1503 static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121, 1503 static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
1504 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 1504 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
1505 136, 137 }; 1505 136, 137 };
1506 static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = { 1506 static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
1507 { 1507 {
1508 .reg = PAD_FUNCTION_EN_0, 1508 .reg = PAD_FUNCTION_EN_0,
1509 .mask = PMX_CLCD1_MASK, 1509 .mask = PMX_CLCD1_MASK,
1510 .val = 0, 1510 .val = 0,
1511 }, { 1511 }, {
1512 .reg = PAD_DIRECTION_SEL_0, 1512 .reg = PAD_DIRECTION_SEL_0,
1513 .mask = PMX_CLCD1_MASK, 1513 .mask = PMX_CLCD1_MASK,
1514 .val = PMX_CLCD1_MASK, 1514 .val = PMX_CLCD1_MASK,
1515 }, 1515 },
1516 }; 1516 };
1517 1517
1518 static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = { 1518 static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
1519 { 1519 {
1520 .muxregs = rs485_0_1_tdm_0_1_muxreg, 1520 .muxregs = rs485_0_1_tdm_0_1_muxreg,
1521 .nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg), 1521 .nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
1522 }, 1522 },
1523 }; 1523 };
1524 1524
1525 static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = { 1525 static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
1526 .name = "rs485_0_1_tdm_0_1_grp", 1526 .name = "rs485_0_1_tdm_0_1_grp",
1527 .pins = rs485_0_1_tdm_0_1_pins, 1527 .pins = rs485_0_1_tdm_0_1_pins,
1528 .npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins), 1528 .npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
1529 .modemuxs = rs485_0_1_tdm_0_1_modemux, 1529 .modemuxs = rs485_0_1_tdm_0_1_modemux,
1530 .nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux), 1530 .nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
1531 }; 1531 };
1532 1532
1533 static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" }; 1533 static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
1534 static struct spear_function rs485_0_1_tdm_0_1_function = { 1534 static struct spear_function rs485_0_1_tdm_0_1_function = {
1535 .name = "rs485_0_1_tdm_0_1", 1535 .name = "rs485_0_1_tdm_0_1",
1536 .groups = rs485_0_1_tdm_0_1_grps, 1536 .groups = rs485_0_1_tdm_0_1_grps,
1537 .ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps), 1537 .ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
1538 }; 1538 };
1539 1539
1540 /* Pad multiplexing for i2c_1_2 device */ 1540 /* Pad multiplexing for i2c_1_2 device */
1541 static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 }; 1541 static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
1542 static struct spear_muxreg i2c_1_2_muxreg[] = { 1542 static struct spear_muxreg i2c_1_2_muxreg[] = {
1543 { 1543 {
1544 .reg = PAD_FUNCTION_EN_0, 1544 .reg = PAD_FUNCTION_EN_0,
1545 .mask = PMX_CLCD1_MASK, 1545 .mask = PMX_CLCD1_MASK,
1546 .val = 0, 1546 .val = 0,
1547 }, { 1547 }, {
1548 .reg = PAD_DIRECTION_SEL_0, 1548 .reg = PAD_DIRECTION_SEL_0,
1549 .mask = PMX_CLCD1_MASK, 1549 .mask = PMX_CLCD1_MASK,
1550 .val = PMX_CLCD1_MASK, 1550 .val = PMX_CLCD1_MASK,
1551 }, 1551 },
1552 }; 1552 };
1553 1553
1554 static struct spear_modemux i2c_1_2_modemux[] = { 1554 static struct spear_modemux i2c_1_2_modemux[] = {
1555 { 1555 {
1556 .muxregs = i2c_1_2_muxreg, 1556 .muxregs = i2c_1_2_muxreg,
1557 .nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg), 1557 .nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
1558 }, 1558 },
1559 }; 1559 };
1560 1560
1561 static struct spear_pingroup i2c_1_2_pingroup = { 1561 static struct spear_pingroup i2c_1_2_pingroup = {
1562 .name = "i2c_1_2_grp", 1562 .name = "i2c_1_2_grp",
1563 .pins = i2c_1_2_pins, 1563 .pins = i2c_1_2_pins,
1564 .npins = ARRAY_SIZE(i2c_1_2_pins), 1564 .npins = ARRAY_SIZE(i2c_1_2_pins),
1565 .modemuxs = i2c_1_2_modemux, 1565 .modemuxs = i2c_1_2_modemux,
1566 .nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux), 1566 .nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
1567 }; 1567 };
1568 1568
1569 static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" }; 1569 static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
1570 static struct spear_function i2c_1_2_function = { 1570 static struct spear_function i2c_1_2_function = {
1571 .name = "i2c_1_2", 1571 .name = "i2c_1_2",
1572 .groups = i2c_1_2_grps, 1572 .groups = i2c_1_2_grps,
1573 .ngroups = ARRAY_SIZE(i2c_1_2_grps), 1573 .ngroups = ARRAY_SIZE(i2c_1_2_grps),
1574 }; 1574 };
1575 1575
1576 /* Pad multiplexing for i2c3_dis_smi_clcd device */ 1576 /* Pad multiplexing for i2c3_dis_smi_clcd device */
1577 /* Muxed with SMI & CLCD */ 1577 /* Muxed with SMI & CLCD */
1578 static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 }; 1578 static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
1579 static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = { 1579 static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
1580 { 1580 {
1581 .reg = PAD_FUNCTION_EN_0, 1581 .reg = PAD_FUNCTION_EN_0,
1582 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK, 1582 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1583 .val = 0, 1583 .val = 0,
1584 }, { 1584 }, {
1585 .reg = PAD_DIRECTION_SEL_0, 1585 .reg = PAD_DIRECTION_SEL_0,
1586 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK, 1586 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1587 .val = PMX_CLCD1_MASK | PMX_SMI_MASK, 1587 .val = PMX_CLCD1_MASK | PMX_SMI_MASK,
1588 }, 1588 },
1589 }; 1589 };
1590 1590
1591 static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = { 1591 static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
1592 { 1592 {
1593 .muxregs = i2c3_dis_smi_clcd_muxreg, 1593 .muxregs = i2c3_dis_smi_clcd_muxreg,
1594 .nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg), 1594 .nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
1595 }, 1595 },
1596 }; 1596 };
1597 1597
1598 static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = { 1598 static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
1599 .name = "i2c3_dis_smi_clcd_grp", 1599 .name = "i2c3_dis_smi_clcd_grp",
1600 .pins = i2c3_dis_smi_clcd_pins, 1600 .pins = i2c3_dis_smi_clcd_pins,
1601 .npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins), 1601 .npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
1602 .modemuxs = i2c3_dis_smi_clcd_modemux, 1602 .modemuxs = i2c3_dis_smi_clcd_modemux,
1603 .nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux), 1603 .nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
1604 }; 1604 };
1605 1605
1606 /* Pad multiplexing for i2c3_dis_sd_i2s0 device */ 1606 /* Pad multiplexing for i2c3_dis_sd_i2s0 device */
1607 /* Muxed with SD/MMC & I2S1 */ 1607 /* Muxed with SD/MMC & I2S1 */
1608 static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 }; 1608 static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
1609 static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = { 1609 static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
1610 { 1610 {
1611 .reg = PAD_FUNCTION_EN_1, 1611 .reg = PAD_FUNCTION_EN_1,
1612 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, 1612 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1613 .val = 0, 1613 .val = 0,
1614 }, { 1614 }, {
1615 .reg = PAD_DIRECTION_SEL_1, 1615 .reg = PAD_DIRECTION_SEL_1,
1616 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, 1616 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1617 .val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, 1617 .val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1618 }, 1618 },
1619 }; 1619 };
1620 1620
1621 static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = { 1621 static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
1622 { 1622 {
1623 .muxregs = i2c3_dis_sd_i2s0_muxreg, 1623 .muxregs = i2c3_dis_sd_i2s0_muxreg,
1624 .nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg), 1624 .nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
1625 }, 1625 },
1626 }; 1626 };
1627 1627
1628 static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = { 1628 static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
1629 .name = "i2c3_dis_sd_i2s0_grp", 1629 .name = "i2c3_dis_sd_i2s0_grp",
1630 .pins = i2c3_dis_sd_i2s0_pins, 1630 .pins = i2c3_dis_sd_i2s0_pins,
1631 .npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins), 1631 .npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
1632 .modemuxs = i2c3_dis_sd_i2s0_modemux, 1632 .modemuxs = i2c3_dis_sd_i2s0_modemux,
1633 .nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux), 1633 .nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
1634 }; 1634 };
1635 1635
1636 static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp", 1636 static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
1637 "i2c3_dis_sd_i2s0_grp" }; 1637 "i2c3_dis_sd_i2s0_grp" };
1638 static struct spear_function i2c3_unction = { 1638 static struct spear_function i2c3_unction = {
1639 .name = "i2c3_i2s1", 1639 .name = "i2c3_i2s1",
1640 .groups = i2c3_grps, 1640 .groups = i2c3_grps,
1641 .ngroups = ARRAY_SIZE(i2c3_grps), 1641 .ngroups = ARRAY_SIZE(i2c3_grps),
1642 }; 1642 };
1643 1643
1644 /* Pad multiplexing for i2c_4_5_dis_smi device */ 1644 /* Pad multiplexing for i2c_4_5_dis_smi device */
1645 /* Muxed with SMI */ 1645 /* Muxed with SMI */
1646 static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 }; 1646 static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
1647 static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = { 1647 static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
1648 { 1648 {
1649 .reg = PAD_FUNCTION_EN_0, 1649 .reg = PAD_FUNCTION_EN_0,
1650 .mask = PMX_SMI_MASK, 1650 .mask = PMX_SMI_MASK,
1651 .val = 0, 1651 .val = 0,
1652 }, { 1652 }, {
1653 .reg = PAD_DIRECTION_SEL_0, 1653 .reg = PAD_DIRECTION_SEL_0,
1654 .mask = PMX_SMI_MASK, 1654 .mask = PMX_SMI_MASK,
1655 .val = PMX_SMI_MASK, 1655 .val = PMX_SMI_MASK,
1656 }, 1656 },
1657 }; 1657 };
1658 1658
1659 static struct spear_modemux i2c_4_5_dis_smi_modemux[] = { 1659 static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
1660 { 1660 {
1661 .muxregs = i2c_4_5_dis_smi_muxreg, 1661 .muxregs = i2c_4_5_dis_smi_muxreg,
1662 .nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg), 1662 .nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
1663 }, 1663 },
1664 }; 1664 };
1665 1665
1666 static struct spear_pingroup i2c_4_5_dis_smi_pingroup = { 1666 static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
1667 .name = "i2c_4_5_dis_smi_grp", 1667 .name = "i2c_4_5_dis_smi_grp",
1668 .pins = i2c_4_5_dis_smi_pins, 1668 .pins = i2c_4_5_dis_smi_pins,
1669 .npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins), 1669 .npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
1670 .modemuxs = i2c_4_5_dis_smi_modemux, 1670 .modemuxs = i2c_4_5_dis_smi_modemux,
1671 .nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux), 1671 .nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
1672 }; 1672 };
1673 1673
1674 /* Pad multiplexing for i2c4_dis_sd device */ 1674 /* Pad multiplexing for i2c4_dis_sd device */
1675 /* Muxed with SD/MMC */ 1675 /* Muxed with SD/MMC */
1676 static const unsigned i2c4_dis_sd_pins[] = { 217, 218 }; 1676 static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
1677 static struct spear_muxreg i2c4_dis_sd_muxreg[] = { 1677 static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
1678 { 1678 {
1679 .reg = PAD_FUNCTION_EN_1, 1679 .reg = PAD_FUNCTION_EN_1,
1680 .mask = PMX_MCIDATA4_MASK, 1680 .mask = PMX_MCIDATA4_MASK,
1681 .val = 0, 1681 .val = 0,
1682 }, { 1682 }, {
1683 .reg = PAD_FUNCTION_EN_2, 1683 .reg = PAD_FUNCTION_EN_2,
1684 .mask = PMX_MCIDATA5_MASK, 1684 .mask = PMX_MCIDATA5_MASK,
1685 .val = 0, 1685 .val = 0,
1686 }, { 1686 }, {
1687 .reg = PAD_DIRECTION_SEL_1, 1687 .reg = PAD_DIRECTION_SEL_1,
1688 .mask = PMX_MCIDATA4_MASK, 1688 .mask = PMX_MCIDATA4_MASK,
1689 .val = PMX_MCIDATA4_MASK, 1689 .val = PMX_MCIDATA4_MASK,
1690 }, { 1690 }, {
1691 .reg = PAD_DIRECTION_SEL_2, 1691 .reg = PAD_DIRECTION_SEL_2,
1692 .mask = PMX_MCIDATA5_MASK, 1692 .mask = PMX_MCIDATA5_MASK,
1693 .val = PMX_MCIDATA5_MASK, 1693 .val = PMX_MCIDATA5_MASK,
1694 }, 1694 },
1695 }; 1695 };
1696 1696
1697 static struct spear_modemux i2c4_dis_sd_modemux[] = { 1697 static struct spear_modemux i2c4_dis_sd_modemux[] = {
1698 { 1698 {
1699 .muxregs = i2c4_dis_sd_muxreg, 1699 .muxregs = i2c4_dis_sd_muxreg,
1700 .nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg), 1700 .nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
1701 }, 1701 },
1702 }; 1702 };
1703 1703
1704 static struct spear_pingroup i2c4_dis_sd_pingroup = { 1704 static struct spear_pingroup i2c4_dis_sd_pingroup = {
1705 .name = "i2c4_dis_sd_grp", 1705 .name = "i2c4_dis_sd_grp",
1706 .pins = i2c4_dis_sd_pins, 1706 .pins = i2c4_dis_sd_pins,
1707 .npins = ARRAY_SIZE(i2c4_dis_sd_pins), 1707 .npins = ARRAY_SIZE(i2c4_dis_sd_pins),
1708 .modemuxs = i2c4_dis_sd_modemux, 1708 .modemuxs = i2c4_dis_sd_modemux,
1709 .nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux), 1709 .nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
1710 }; 1710 };
1711 1711
1712 /* Pad multiplexing for i2c5_dis_sd device */ 1712 /* Pad multiplexing for i2c5_dis_sd device */
1713 /* Muxed with SD/MMC */ 1713 /* Muxed with SD/MMC */
1714 static const unsigned i2c5_dis_sd_pins[] = { 219, 220 }; 1714 static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
1715 static struct spear_muxreg i2c5_dis_sd_muxreg[] = { 1715 static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
1716 { 1716 {
1717 .reg = PAD_FUNCTION_EN_2, 1717 .reg = PAD_FUNCTION_EN_2,
1718 .mask = PMX_MCIDATA6_MASK | 1718 .mask = PMX_MCIDATA6_MASK |
1719 PMX_MCIDATA7_MASK, 1719 PMX_MCIDATA7_MASK,
1720 .val = 0, 1720 .val = 0,
1721 }, { 1721 }, {
1722 .reg = PAD_DIRECTION_SEL_2, 1722 .reg = PAD_DIRECTION_SEL_2,
1723 .mask = PMX_MCIDATA6_MASK | 1723 .mask = PMX_MCIDATA6_MASK |
1724 PMX_MCIDATA7_MASK, 1724 PMX_MCIDATA7_MASK,
1725 .val = PMX_MCIDATA6_MASK | 1725 .val = PMX_MCIDATA6_MASK |
1726 PMX_MCIDATA7_MASK, 1726 PMX_MCIDATA7_MASK,
1727 }, 1727 },
1728 }; 1728 };
1729 1729
1730 static struct spear_modemux i2c5_dis_sd_modemux[] = { 1730 static struct spear_modemux i2c5_dis_sd_modemux[] = {
1731 { 1731 {
1732 .muxregs = i2c5_dis_sd_muxreg, 1732 .muxregs = i2c5_dis_sd_muxreg,
1733 .nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg), 1733 .nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
1734 }, 1734 },
1735 }; 1735 };
1736 1736
1737 static struct spear_pingroup i2c5_dis_sd_pingroup = { 1737 static struct spear_pingroup i2c5_dis_sd_pingroup = {
1738 .name = "i2c5_dis_sd_grp", 1738 .name = "i2c5_dis_sd_grp",
1739 .pins = i2c5_dis_sd_pins, 1739 .pins = i2c5_dis_sd_pins,
1740 .npins = ARRAY_SIZE(i2c5_dis_sd_pins), 1740 .npins = ARRAY_SIZE(i2c5_dis_sd_pins),
1741 .modemuxs = i2c5_dis_sd_modemux, 1741 .modemuxs = i2c5_dis_sd_modemux,
1742 .nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux), 1742 .nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
1743 }; 1743 };
1744 1744
1745 static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp", 1745 static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
1746 "i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" }; 1746 "i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
1747 static struct spear_function i2c_4_5_function = { 1747 static struct spear_function i2c_4_5_function = {
1748 .name = "i2c_4_5", 1748 .name = "i2c_4_5",
1749 .groups = i2c_4_5_grps, 1749 .groups = i2c_4_5_grps,
1750 .ngroups = ARRAY_SIZE(i2c_4_5_grps), 1750 .ngroups = ARRAY_SIZE(i2c_4_5_grps),
1751 }; 1751 };
1752 1752
1753 /* Pad multiplexing for i2c_6_7_dis_kbd device */ 1753 /* Pad multiplexing for i2c_6_7_dis_kbd device */
1754 /* Muxed with KBD */ 1754 /* Muxed with KBD */
1755 static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 }; 1755 static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
1756 static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = { 1756 static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
1757 { 1757 {
1758 .reg = PAD_FUNCTION_EN_1, 1758 .reg = PAD_FUNCTION_EN_1,
1759 .mask = PMX_KBD_ROWCOL25_MASK, 1759 .mask = PMX_KBD_ROWCOL25_MASK,
1760 .val = 0, 1760 .val = 0,
1761 }, { 1761 }, {
1762 .reg = PAD_DIRECTION_SEL_1, 1762 .reg = PAD_DIRECTION_SEL_1,
1763 .mask = PMX_KBD_ROWCOL25_MASK, 1763 .mask = PMX_KBD_ROWCOL25_MASK,
1764 .val = PMX_KBD_ROWCOL25_MASK, 1764 .val = PMX_KBD_ROWCOL25_MASK,
1765 }, 1765 },
1766 }; 1766 };
1767 1767
1768 static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = { 1768 static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
1769 { 1769 {
1770 .muxregs = i2c_6_7_dis_kbd_muxreg, 1770 .muxregs = i2c_6_7_dis_kbd_muxreg,
1771 .nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg), 1771 .nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
1772 }, 1772 },
1773 }; 1773 };
1774 1774
1775 static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = { 1775 static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
1776 .name = "i2c_6_7_dis_kbd_grp", 1776 .name = "i2c_6_7_dis_kbd_grp",
1777 .pins = i2c_6_7_dis_kbd_pins, 1777 .pins = i2c_6_7_dis_kbd_pins,
1778 .npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins), 1778 .npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
1779 .modemuxs = i2c_6_7_dis_kbd_modemux, 1779 .modemuxs = i2c_6_7_dis_kbd_modemux,
1780 .nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux), 1780 .nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
1781 }; 1781 };
1782 1782
1783 /* Pad multiplexing for i2c6_dis_sd device */ 1783 /* Pad multiplexing for i2c6_dis_sd device */
1784 /* Muxed with SD/MMC */ 1784 /* Muxed with SD/MMC */
1785 static const unsigned i2c6_dis_sd_pins[] = { 236, 237 }; 1785 static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
1786 static struct spear_muxreg i2c6_dis_sd_muxreg[] = { 1786 static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
1787 { 1787 {
1788 .reg = PAD_FUNCTION_EN_2, 1788 .reg = PAD_FUNCTION_EN_2,
1789 .mask = PMX_MCIIORDRE_MASK | 1789 .mask = PMX_MCIIORDRE_MASK |
1790 PMX_MCIIOWRWE_MASK, 1790 PMX_MCIIOWRWE_MASK,
1791 .val = 0, 1791 .val = 0,
1792 }, { 1792 }, {
1793 .reg = PAD_DIRECTION_SEL_2, 1793 .reg = PAD_DIRECTION_SEL_2,
1794 .mask = PMX_MCIIORDRE_MASK | 1794 .mask = PMX_MCIIORDRE_MASK |
1795 PMX_MCIIOWRWE_MASK, 1795 PMX_MCIIOWRWE_MASK,
1796 .val = PMX_MCIIORDRE_MASK | 1796 .val = PMX_MCIIORDRE_MASK |
1797 PMX_MCIIOWRWE_MASK, 1797 PMX_MCIIOWRWE_MASK,
1798 }, 1798 },
1799 }; 1799 };
1800 1800
1801 static struct spear_modemux i2c6_dis_sd_modemux[] = { 1801 static struct spear_modemux i2c6_dis_sd_modemux[] = {
1802 { 1802 {
1803 .muxregs = i2c6_dis_sd_muxreg, 1803 .muxregs = i2c6_dis_sd_muxreg,
1804 .nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg), 1804 .nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
1805 }, 1805 },
1806 }; 1806 };
1807 1807
1808 static struct spear_pingroup i2c6_dis_sd_pingroup = { 1808 static struct spear_pingroup i2c6_dis_sd_pingroup = {
1809 .name = "i2c6_dis_sd_grp", 1809 .name = "i2c6_dis_sd_grp",
1810 .pins = i2c6_dis_sd_pins, 1810 .pins = i2c6_dis_sd_pins,
1811 .npins = ARRAY_SIZE(i2c6_dis_sd_pins), 1811 .npins = ARRAY_SIZE(i2c6_dis_sd_pins),
1812 .modemuxs = i2c6_dis_sd_modemux, 1812 .modemuxs = i2c6_dis_sd_modemux,
1813 .nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux), 1813 .nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
1814 }; 1814 };
1815 1815
1816 /* Pad multiplexing for i2c7_dis_sd device */ 1816 /* Pad multiplexing for i2c7_dis_sd device */
1817 static const unsigned i2c7_dis_sd_pins[] = { 238, 239 }; 1817 static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
1818 static struct spear_muxreg i2c7_dis_sd_muxreg[] = { 1818 static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
1819 { 1819 {
1820 .reg = PAD_FUNCTION_EN_2, 1820 .reg = PAD_FUNCTION_EN_2,
1821 .mask = PMX_MCIRESETCF_MASK | 1821 .mask = PMX_MCIRESETCF_MASK |
1822 PMX_MCICS0CE_MASK, 1822 PMX_MCICS0CE_MASK,
1823 .val = 0, 1823 .val = 0,
1824 }, { 1824 }, {
1825 .reg = PAD_DIRECTION_SEL_2, 1825 .reg = PAD_DIRECTION_SEL_2,
1826 .mask = PMX_MCIRESETCF_MASK | 1826 .mask = PMX_MCIRESETCF_MASK |
1827 PMX_MCICS0CE_MASK, 1827 PMX_MCICS0CE_MASK,
1828 .val = PMX_MCIRESETCF_MASK | 1828 .val = PMX_MCIRESETCF_MASK |
1829 PMX_MCICS0CE_MASK, 1829 PMX_MCICS0CE_MASK,
1830 }, 1830 },
1831 }; 1831 };
1832 1832
1833 static struct spear_modemux i2c7_dis_sd_modemux[] = { 1833 static struct spear_modemux i2c7_dis_sd_modemux[] = {
1834 { 1834 {
1835 .muxregs = i2c7_dis_sd_muxreg, 1835 .muxregs = i2c7_dis_sd_muxreg,
1836 .nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg), 1836 .nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
1837 }, 1837 },
1838 }; 1838 };
1839 1839
1840 static struct spear_pingroup i2c7_dis_sd_pingroup = { 1840 static struct spear_pingroup i2c7_dis_sd_pingroup = {
1841 .name = "i2c7_dis_sd_grp", 1841 .name = "i2c7_dis_sd_grp",
1842 .pins = i2c7_dis_sd_pins, 1842 .pins = i2c7_dis_sd_pins,
1843 .npins = ARRAY_SIZE(i2c7_dis_sd_pins), 1843 .npins = ARRAY_SIZE(i2c7_dis_sd_pins),
1844 .modemuxs = i2c7_dis_sd_modemux, 1844 .modemuxs = i2c7_dis_sd_modemux,
1845 .nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux), 1845 .nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
1846 }; 1846 };
1847 1847
1848 static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp", 1848 static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
1849 "i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" }; 1849 "i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
1850 static struct spear_function i2c_6_7_function = { 1850 static struct spear_function i2c_6_7_function = {
1851 .name = "i2c_6_7", 1851 .name = "i2c_6_7",
1852 .groups = i2c_6_7_grps, 1852 .groups = i2c_6_7_grps,
1853 .ngroups = ARRAY_SIZE(i2c_6_7_grps), 1853 .ngroups = ARRAY_SIZE(i2c_6_7_grps),
1854 }; 1854 };
1855 1855
1856 /* Pad multiplexing for can0_dis_nor device */ 1856 /* Pad multiplexing for can0_dis_nor device */
1857 /* Muxed with NOR */ 1857 /* Muxed with NOR */
1858 static const unsigned can0_dis_nor_pins[] = { 56, 57 }; 1858 static const unsigned can0_dis_nor_pins[] = { 56, 57 };
1859 static struct spear_muxreg can0_dis_nor_muxreg[] = { 1859 static struct spear_muxreg can0_dis_nor_muxreg[] = {
1860 { 1860 {
1861 .reg = PAD_FUNCTION_EN_0, 1861 .reg = PAD_FUNCTION_EN_0,
1862 .mask = PMX_NFRSTPWDWN2_MASK, 1862 .mask = PMX_NFRSTPWDWN2_MASK,
1863 .val = 0, 1863 .val = 0,
1864 }, { 1864 }, {
1865 .reg = PAD_FUNCTION_EN_1, 1865 .reg = PAD_FUNCTION_EN_1,
1866 .mask = PMX_NFRSTPWDWN3_MASK, 1866 .mask = PMX_NFRSTPWDWN3_MASK,
1867 .val = 0, 1867 .val = 0,
1868 }, { 1868 }, {
1869 .reg = PAD_DIRECTION_SEL_0, 1869 .reg = PAD_DIRECTION_SEL_0,
1870 .mask = PMX_NFRSTPWDWN2_MASK, 1870 .mask = PMX_NFRSTPWDWN2_MASK,
1871 .val = PMX_NFRSTPWDWN2_MASK, 1871 .val = PMX_NFRSTPWDWN2_MASK,
1872 }, { 1872 }, {
1873 .reg = PAD_DIRECTION_SEL_1, 1873 .reg = PAD_DIRECTION_SEL_1,
1874 .mask = PMX_NFRSTPWDWN3_MASK, 1874 .mask = PMX_NFRSTPWDWN3_MASK,
1875 .val = PMX_NFRSTPWDWN3_MASK, 1875 .val = PMX_NFRSTPWDWN3_MASK,
1876 }, 1876 },
1877 }; 1877 };
1878 1878
1879 static struct spear_modemux can0_dis_nor_modemux[] = { 1879 static struct spear_modemux can0_dis_nor_modemux[] = {
1880 { 1880 {
1881 .muxregs = can0_dis_nor_muxreg, 1881 .muxregs = can0_dis_nor_muxreg,
1882 .nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg), 1882 .nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
1883 }, 1883 },
1884 }; 1884 };
1885 1885
1886 static struct spear_pingroup can0_dis_nor_pingroup = { 1886 static struct spear_pingroup can0_dis_nor_pingroup = {
1887 .name = "can0_dis_nor_grp", 1887 .name = "can0_dis_nor_grp",
1888 .pins = can0_dis_nor_pins, 1888 .pins = can0_dis_nor_pins,
1889 .npins = ARRAY_SIZE(can0_dis_nor_pins), 1889 .npins = ARRAY_SIZE(can0_dis_nor_pins),
1890 .modemuxs = can0_dis_nor_modemux, 1890 .modemuxs = can0_dis_nor_modemux,
1891 .nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux), 1891 .nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
1892 }; 1892 };
1893 1893
1894 /* Pad multiplexing for can0_dis_sd device */ 1894 /* Pad multiplexing for can0_dis_sd device */
1895 /* Muxed with SD/MMC */ 1895 /* Muxed with SD/MMC */
1896 static const unsigned can0_dis_sd_pins[] = { 240, 241 }; 1896 static const unsigned can0_dis_sd_pins[] = { 240, 241 };
1897 static struct spear_muxreg can0_dis_sd_muxreg[] = { 1897 static struct spear_muxreg can0_dis_sd_muxreg[] = {
1898 { 1898 {
1899 .reg = PAD_FUNCTION_EN_2, 1899 .reg = PAD_FUNCTION_EN_2,
1900 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, 1900 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1901 .val = 0, 1901 .val = 0,
1902 }, { 1902 }, {
1903 .reg = PAD_DIRECTION_SEL_2, 1903 .reg = PAD_DIRECTION_SEL_2,
1904 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, 1904 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1905 .val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, 1905 .val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1906 }, 1906 },
1907 }; 1907 };
1908 1908
1909 static struct spear_modemux can0_dis_sd_modemux[] = { 1909 static struct spear_modemux can0_dis_sd_modemux[] = {
1910 { 1910 {
1911 .muxregs = can0_dis_sd_muxreg, 1911 .muxregs = can0_dis_sd_muxreg,
1912 .nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg), 1912 .nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
1913 }, 1913 },
1914 }; 1914 };
1915 1915
1916 static struct spear_pingroup can0_dis_sd_pingroup = { 1916 static struct spear_pingroup can0_dis_sd_pingroup = {
1917 .name = "can0_dis_sd_grp", 1917 .name = "can0_dis_sd_grp",
1918 .pins = can0_dis_sd_pins, 1918 .pins = can0_dis_sd_pins,
1919 .npins = ARRAY_SIZE(can0_dis_sd_pins), 1919 .npins = ARRAY_SIZE(can0_dis_sd_pins),
1920 .modemuxs = can0_dis_sd_modemux, 1920 .modemuxs = can0_dis_sd_modemux,
1921 .nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux), 1921 .nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
1922 }; 1922 };
1923 1923
1924 static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp" 1924 static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
1925 }; 1925 };
1926 static struct spear_function can0_function = { 1926 static struct spear_function can0_function = {
1927 .name = "can0", 1927 .name = "can0",
1928 .groups = can0_grps, 1928 .groups = can0_grps,
1929 .ngroups = ARRAY_SIZE(can0_grps), 1929 .ngroups = ARRAY_SIZE(can0_grps),
1930 }; 1930 };
1931 1931
1932 /* Pad multiplexing for can1_dis_sd device */ 1932 /* Pad multiplexing for can1_dis_sd device */
1933 /* Muxed with SD/MMC */ 1933 /* Muxed with SD/MMC */
1934 static const unsigned can1_dis_sd_pins[] = { 242, 243 }; 1934 static const unsigned can1_dis_sd_pins[] = { 242, 243 };
1935 static struct spear_muxreg can1_dis_sd_muxreg[] = { 1935 static struct spear_muxreg can1_dis_sd_muxreg[] = {
1936 { 1936 {
1937 .reg = PAD_FUNCTION_EN_2, 1937 .reg = PAD_FUNCTION_EN_2,
1938 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, 1938 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1939 .val = 0, 1939 .val = 0,
1940 }, { 1940 }, {
1941 .reg = PAD_DIRECTION_SEL_2, 1941 .reg = PAD_DIRECTION_SEL_2,
1942 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, 1942 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1943 .val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, 1943 .val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1944 }, 1944 },
1945 }; 1945 };
1946 1946
1947 static struct spear_modemux can1_dis_sd_modemux[] = { 1947 static struct spear_modemux can1_dis_sd_modemux[] = {
1948 { 1948 {
1949 .muxregs = can1_dis_sd_muxreg, 1949 .muxregs = can1_dis_sd_muxreg,
1950 .nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg), 1950 .nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
1951 }, 1951 },
1952 }; 1952 };
1953 1953
1954 static struct spear_pingroup can1_dis_sd_pingroup = { 1954 static struct spear_pingroup can1_dis_sd_pingroup = {
1955 .name = "can1_dis_sd_grp", 1955 .name = "can1_dis_sd_grp",
1956 .pins = can1_dis_sd_pins, 1956 .pins = can1_dis_sd_pins,
1957 .npins = ARRAY_SIZE(can1_dis_sd_pins), 1957 .npins = ARRAY_SIZE(can1_dis_sd_pins),
1958 .modemuxs = can1_dis_sd_modemux, 1958 .modemuxs = can1_dis_sd_modemux,
1959 .nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux), 1959 .nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
1960 }; 1960 };
1961 1961
1962 /* Pad multiplexing for can1_dis_kbd device */ 1962 /* Pad multiplexing for can1_dis_kbd device */
1963 /* Muxed with KBD */ 1963 /* Muxed with KBD */
1964 static const unsigned can1_dis_kbd_pins[] = { 201, 202 }; 1964 static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
1965 static struct spear_muxreg can1_dis_kbd_muxreg[] = { 1965 static struct spear_muxreg can1_dis_kbd_muxreg[] = {
1966 { 1966 {
1967 .reg = PAD_FUNCTION_EN_1, 1967 .reg = PAD_FUNCTION_EN_1,
1968 .mask = PMX_KBD_ROWCOL25_MASK, 1968 .mask = PMX_KBD_ROWCOL25_MASK,
1969 .val = 0, 1969 .val = 0,
1970 }, { 1970 }, {
1971 .reg = PAD_DIRECTION_SEL_1, 1971 .reg = PAD_DIRECTION_SEL_1,
1972 .mask = PMX_KBD_ROWCOL25_MASK, 1972 .mask = PMX_KBD_ROWCOL25_MASK,
1973 .val = PMX_KBD_ROWCOL25_MASK, 1973 .val = PMX_KBD_ROWCOL25_MASK,
1974 }, 1974 },
1975 }; 1975 };
1976 1976
1977 static struct spear_modemux can1_dis_kbd_modemux[] = { 1977 static struct spear_modemux can1_dis_kbd_modemux[] = {
1978 { 1978 {
1979 .muxregs = can1_dis_kbd_muxreg, 1979 .muxregs = can1_dis_kbd_muxreg,
1980 .nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg), 1980 .nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
1981 }, 1981 },
1982 }; 1982 };
1983 1983
1984 static struct spear_pingroup can1_dis_kbd_pingroup = { 1984 static struct spear_pingroup can1_dis_kbd_pingroup = {
1985 .name = "can1_dis_kbd_grp", 1985 .name = "can1_dis_kbd_grp",
1986 .pins = can1_dis_kbd_pins, 1986 .pins = can1_dis_kbd_pins,
1987 .npins = ARRAY_SIZE(can1_dis_kbd_pins), 1987 .npins = ARRAY_SIZE(can1_dis_kbd_pins),
1988 .modemuxs = can1_dis_kbd_modemux, 1988 .modemuxs = can1_dis_kbd_modemux,
1989 .nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux), 1989 .nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
1990 }; 1990 };
1991 1991
1992 static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp" 1992 static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
1993 }; 1993 };
1994 static struct spear_function can1_function = { 1994 static struct spear_function can1_function = {
1995 .name = "can1", 1995 .name = "can1",
1996 .groups = can1_grps, 1996 .groups = can1_grps,
1997 .ngroups = ARRAY_SIZE(can1_grps), 1997 .ngroups = ARRAY_SIZE(can1_grps),
1998 }; 1998 };
1999 1999
2000 /* Pad multiplexing for (ras-ip) pci device */ 2000 /* Pad multiplexing for (ras-ip) pci device */
2001 static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18, 2001 static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
2002 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 2002 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
2003 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 2003 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
2004 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 }; 2004 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
2005 2005
2006 static struct spear_muxreg pci_muxreg[] = { 2006 static struct spear_muxreg pci_muxreg[] = {
2007 { 2007 {
2008 .reg = PAD_FUNCTION_EN_0, 2008 .reg = PAD_FUNCTION_EN_0,
2009 .mask = PMX_MCI_DATA8_15_MASK, 2009 .mask = PMX_MCI_DATA8_15_MASK,
2010 .val = 0, 2010 .val = 0,
2011 }, { 2011 }, {
2012 .reg = PAD_FUNCTION_EN_1, 2012 .reg = PAD_FUNCTION_EN_1,
2013 .mask = PMX_PCI_REG1_MASK, 2013 .mask = PMX_PCI_REG1_MASK,
2014 .val = 0, 2014 .val = 0,
2015 }, { 2015 }, {
2016 .reg = PAD_FUNCTION_EN_2, 2016 .reg = PAD_FUNCTION_EN_2,
2017 .mask = PMX_PCI_REG2_MASK, 2017 .mask = PMX_PCI_REG2_MASK,
2018 .val = 0, 2018 .val = 0,
2019 }, { 2019 }, {
2020 .reg = PAD_DIRECTION_SEL_0, 2020 .reg = PAD_DIRECTION_SEL_0,
2021 .mask = PMX_MCI_DATA8_15_MASK, 2021 .mask = PMX_MCI_DATA8_15_MASK,
2022 .val = PMX_MCI_DATA8_15_MASK, 2022 .val = PMX_MCI_DATA8_15_MASK,
2023 }, { 2023 }, {
2024 .reg = PAD_DIRECTION_SEL_1, 2024 .reg = PAD_DIRECTION_SEL_1,
2025 .mask = PMX_PCI_REG1_MASK, 2025 .mask = PMX_PCI_REG1_MASK,
2026 .val = PMX_PCI_REG1_MASK, 2026 .val = PMX_PCI_REG1_MASK,
2027 }, { 2027 }, {
2028 .reg = PAD_DIRECTION_SEL_2, 2028 .reg = PAD_DIRECTION_SEL_2,
2029 .mask = PMX_PCI_REG2_MASK, 2029 .mask = PMX_PCI_REG2_MASK,
2030 .val = PMX_PCI_REG2_MASK, 2030 .val = PMX_PCI_REG2_MASK,
2031 }, 2031 },
2032 }; 2032 };
2033 2033
2034 static struct spear_modemux pci_modemux[] = { 2034 static struct spear_modemux pci_modemux[] = {
2035 { 2035 {
2036 .muxregs = pci_muxreg, 2036 .muxregs = pci_muxreg,
2037 .nmuxregs = ARRAY_SIZE(pci_muxreg), 2037 .nmuxregs = ARRAY_SIZE(pci_muxreg),
2038 }, 2038 },
2039 }; 2039 };
2040 2040
2041 static struct spear_pingroup pci_pingroup = { 2041 static struct spear_pingroup pci_pingroup = {
2042 .name = "pci_grp", 2042 .name = "pci_grp",
2043 .pins = pci_pins, 2043 .pins = pci_pins,
2044 .npins = ARRAY_SIZE(pci_pins), 2044 .npins = ARRAY_SIZE(pci_pins),
2045 .modemuxs = pci_modemux, 2045 .modemuxs = pci_modemux,
2046 .nmodemuxs = ARRAY_SIZE(pci_modemux), 2046 .nmodemuxs = ARRAY_SIZE(pci_modemux),
2047 }; 2047 };
2048 2048
2049 static const char *const pci_grps[] = { "pci_grp" }; 2049 static const char *const pci_grps[] = { "pci_grp" };
2050 static struct spear_function pci_function = { 2050 static struct spear_function pci_function = {
2051 .name = "pci", 2051 .name = "pci",
2052 .groups = pci_grps, 2052 .groups = pci_grps,
2053 .ngroups = ARRAY_SIZE(pci_grps), 2053 .ngroups = ARRAY_SIZE(pci_grps),
2054 }; 2054 };
2055 2055
2056 /* pad multiplexing for (fix-part) pcie0 device */ 2056 /* pad multiplexing for (fix-part) pcie0 device */
2057 static struct spear_muxreg pcie0_muxreg[] = { 2057 static struct spear_muxreg pcie0_muxreg[] = {
2058 { 2058 {
2059 .reg = PCIE_SATA_CFG, 2059 .reg = PCIE_SATA_CFG,
2060 .mask = PCIE_CFG_VAL(0), 2060 .mask = PCIE_CFG_VAL(0),
2061 .val = PCIE_CFG_VAL(0), 2061 .val = PCIE_CFG_VAL(0),
2062 }, 2062 },
2063 }; 2063 };
2064 2064
2065 static struct spear_modemux pcie0_modemux[] = { 2065 static struct spear_modemux pcie0_modemux[] = {
2066 { 2066 {
2067 .muxregs = pcie0_muxreg, 2067 .muxregs = pcie0_muxreg,
2068 .nmuxregs = ARRAY_SIZE(pcie0_muxreg), 2068 .nmuxregs = ARRAY_SIZE(pcie0_muxreg),
2069 }, 2069 },
2070 }; 2070 };
2071 2071
2072 static struct spear_pingroup pcie0_pingroup = { 2072 static struct spear_pingroup pcie0_pingroup = {
2073 .name = "pcie0_grp", 2073 .name = "pcie0_grp",
2074 .modemuxs = pcie0_modemux, 2074 .modemuxs = pcie0_modemux,
2075 .nmodemuxs = ARRAY_SIZE(pcie0_modemux), 2075 .nmodemuxs = ARRAY_SIZE(pcie0_modemux),
2076 }; 2076 };
2077 2077
2078 /* pad multiplexing for (fix-part) pcie1 device */ 2078 /* pad multiplexing for (fix-part) pcie1 device */
2079 static struct spear_muxreg pcie1_muxreg[] = { 2079 static struct spear_muxreg pcie1_muxreg[] = {
2080 { 2080 {
2081 .reg = PCIE_SATA_CFG, 2081 .reg = PCIE_SATA_CFG,
2082 .mask = PCIE_CFG_VAL(1), 2082 .mask = PCIE_CFG_VAL(1),
2083 .val = PCIE_CFG_VAL(1), 2083 .val = PCIE_CFG_VAL(1),
2084 }, 2084 },
2085 }; 2085 };
2086 2086
2087 static struct spear_modemux pcie1_modemux[] = { 2087 static struct spear_modemux pcie1_modemux[] = {
2088 { 2088 {
2089 .muxregs = pcie1_muxreg, 2089 .muxregs = pcie1_muxreg,
2090 .nmuxregs = ARRAY_SIZE(pcie1_muxreg), 2090 .nmuxregs = ARRAY_SIZE(pcie1_muxreg),
2091 }, 2091 },
2092 }; 2092 };
2093 2093
2094 static struct spear_pingroup pcie1_pingroup = { 2094 static struct spear_pingroup pcie1_pingroup = {
2095 .name = "pcie1_grp", 2095 .name = "pcie1_grp",
2096 .modemuxs = pcie1_modemux, 2096 .modemuxs = pcie1_modemux,
2097 .nmodemuxs = ARRAY_SIZE(pcie1_modemux), 2097 .nmodemuxs = ARRAY_SIZE(pcie1_modemux),
2098 }; 2098 };
2099 2099
2100 /* pad multiplexing for (fix-part) pcie2 device */ 2100 /* pad multiplexing for (fix-part) pcie2 device */
2101 static struct spear_muxreg pcie2_muxreg[] = { 2101 static struct spear_muxreg pcie2_muxreg[] = {
2102 { 2102 {
2103 .reg = PCIE_SATA_CFG, 2103 .reg = PCIE_SATA_CFG,
2104 .mask = PCIE_CFG_VAL(2), 2104 .mask = PCIE_CFG_VAL(2),
2105 .val = PCIE_CFG_VAL(2), 2105 .val = PCIE_CFG_VAL(2),
2106 }, 2106 },
2107 }; 2107 };
2108 2108
2109 static struct spear_modemux pcie2_modemux[] = { 2109 static struct spear_modemux pcie2_modemux[] = {
2110 { 2110 {
2111 .muxregs = pcie2_muxreg, 2111 .muxregs = pcie2_muxreg,
2112 .nmuxregs = ARRAY_SIZE(pcie2_muxreg), 2112 .nmuxregs = ARRAY_SIZE(pcie2_muxreg),
2113 }, 2113 },
2114 }; 2114 };
2115 2115
2116 static struct spear_pingroup pcie2_pingroup = { 2116 static struct spear_pingroup pcie2_pingroup = {
2117 .name = "pcie2_grp", 2117 .name = "pcie2_grp",
2118 .modemuxs = pcie2_modemux, 2118 .modemuxs = pcie2_modemux,
2119 .nmodemuxs = ARRAY_SIZE(pcie2_modemux), 2119 .nmodemuxs = ARRAY_SIZE(pcie2_modemux),
2120 }; 2120 };
2121 2121
2122 static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" 2122 static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp"
2123 }; 2123 };
2124 static struct spear_function pcie_function = { 2124 static struct spear_function pcie_function = {
2125 .name = "pci_express", 2125 .name = "pci_express",
2126 .groups = pcie_grps, 2126 .groups = pcie_grps,
2127 .ngroups = ARRAY_SIZE(pcie_grps), 2127 .ngroups = ARRAY_SIZE(pcie_grps),
2128 }; 2128 };
2129 2129
2130 /* pad multiplexing for sata0 device */ 2130 /* pad multiplexing for sata0 device */
2131 static struct spear_muxreg sata0_muxreg[] = { 2131 static struct spear_muxreg sata0_muxreg[] = {
2132 { 2132 {
2133 .reg = PCIE_SATA_CFG, 2133 .reg = PCIE_SATA_CFG,
2134 .mask = SATA_CFG_VAL(0), 2134 .mask = SATA_CFG_VAL(0),
2135 .val = SATA_CFG_VAL(0), 2135 .val = SATA_CFG_VAL(0),
2136 }, 2136 },
2137 }; 2137 };
2138 2138
2139 static struct spear_modemux sata0_modemux[] = { 2139 static struct spear_modemux sata0_modemux[] = {
2140 { 2140 {
2141 .muxregs = sata0_muxreg, 2141 .muxregs = sata0_muxreg,
2142 .nmuxregs = ARRAY_SIZE(sata0_muxreg), 2142 .nmuxregs = ARRAY_SIZE(sata0_muxreg),
2143 }, 2143 },
2144 }; 2144 };
2145 2145
2146 static struct spear_pingroup sata0_pingroup = { 2146 static struct spear_pingroup sata0_pingroup = {
2147 .name = "sata0_grp", 2147 .name = "sata0_grp",
2148 .modemuxs = sata0_modemux, 2148 .modemuxs = sata0_modemux,
2149 .nmodemuxs = ARRAY_SIZE(sata0_modemux), 2149 .nmodemuxs = ARRAY_SIZE(sata0_modemux),
2150 }; 2150 };
2151 2151
2152 /* pad multiplexing for sata1 device */ 2152 /* pad multiplexing for sata1 device */
2153 static struct spear_muxreg sata1_muxreg[] = { 2153 static struct spear_muxreg sata1_muxreg[] = {
2154 { 2154 {
2155 .reg = PCIE_SATA_CFG, 2155 .reg = PCIE_SATA_CFG,
2156 .mask = SATA_CFG_VAL(1), 2156 .mask = SATA_CFG_VAL(1),
2157 .val = SATA_CFG_VAL(1), 2157 .val = SATA_CFG_VAL(1),
2158 }, 2158 },
2159 }; 2159 };
2160 2160
2161 static struct spear_modemux sata1_modemux[] = { 2161 static struct spear_modemux sata1_modemux[] = {
2162 { 2162 {
2163 .muxregs = sata1_muxreg, 2163 .muxregs = sata1_muxreg,
2164 .nmuxregs = ARRAY_SIZE(sata1_muxreg), 2164 .nmuxregs = ARRAY_SIZE(sata1_muxreg),
2165 }, 2165 },
2166 }; 2166 };
2167 2167
2168 static struct spear_pingroup sata1_pingroup = { 2168 static struct spear_pingroup sata1_pingroup = {
2169 .name = "sata1_grp", 2169 .name = "sata1_grp",
2170 .modemuxs = sata1_modemux, 2170 .modemuxs = sata1_modemux,
2171 .nmodemuxs = ARRAY_SIZE(sata1_modemux), 2171 .nmodemuxs = ARRAY_SIZE(sata1_modemux),
2172 }; 2172 };
2173 2173
2174 /* pad multiplexing for sata2 device */ 2174 /* pad multiplexing for sata2 device */
2175 static struct spear_muxreg sata2_muxreg[] = { 2175 static struct spear_muxreg sata2_muxreg[] = {
2176 { 2176 {
2177 .reg = PCIE_SATA_CFG, 2177 .reg = PCIE_SATA_CFG,
2178 .mask = SATA_CFG_VAL(2), 2178 .mask = SATA_CFG_VAL(2),
2179 .val = SATA_CFG_VAL(2), 2179 .val = SATA_CFG_VAL(2),
2180 }, 2180 },
2181 }; 2181 };
2182 2182
2183 static struct spear_modemux sata2_modemux[] = { 2183 static struct spear_modemux sata2_modemux[] = {
2184 { 2184 {
2185 .muxregs = sata2_muxreg, 2185 .muxregs = sata2_muxreg,
2186 .nmuxregs = ARRAY_SIZE(sata2_muxreg), 2186 .nmuxregs = ARRAY_SIZE(sata2_muxreg),
2187 }, 2187 },
2188 }; 2188 };
2189 2189
2190 static struct spear_pingroup sata2_pingroup = { 2190 static struct spear_pingroup sata2_pingroup = {
2191 .name = "sata2_grp", 2191 .name = "sata2_grp",
2192 .modemuxs = sata2_modemux, 2192 .modemuxs = sata2_modemux,
2193 .nmodemuxs = ARRAY_SIZE(sata2_modemux), 2193 .nmodemuxs = ARRAY_SIZE(sata2_modemux),
2194 }; 2194 };
2195 2195
2196 static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp" 2196 static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
2197 }; 2197 };
2198 static struct spear_function sata_function = { 2198 static struct spear_function sata_function = {
2199 .name = "sata", 2199 .name = "sata",
2200 .groups = sata_grps, 2200 .groups = sata_grps,
2201 .ngroups = ARRAY_SIZE(sata_grps), 2201 .ngroups = ARRAY_SIZE(sata_grps),
2202 }; 2202 };
2203 2203
2204 /* Pad multiplexing for ssp1_dis_kbd device */ 2204 /* Pad multiplexing for ssp1_dis_kbd device */
2205 static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 }; 2205 static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
2206 static struct spear_muxreg ssp1_dis_kbd_muxreg[] = { 2206 static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
2207 { 2207 {
2208 .reg = PAD_FUNCTION_EN_1, 2208 .reg = PAD_FUNCTION_EN_1,
2209 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | 2209 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2210 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | 2210 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2211 PMX_NFCE2_MASK, 2211 PMX_NFCE2_MASK,
2212 .val = 0, 2212 .val = 0,
2213 }, { 2213 }, {
2214 .reg = PAD_DIRECTION_SEL_1, 2214 .reg = PAD_DIRECTION_SEL_1,
2215 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | 2215 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2216 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | 2216 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2217 PMX_NFCE2_MASK, 2217 PMX_NFCE2_MASK,
2218 .val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | 2218 .val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2219 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | 2219 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2220 PMX_NFCE2_MASK, 2220 PMX_NFCE2_MASK,
2221 }, 2221 },
2222 }; 2222 };
2223 2223
2224 static struct spear_modemux ssp1_dis_kbd_modemux[] = { 2224 static struct spear_modemux ssp1_dis_kbd_modemux[] = {
2225 { 2225 {
2226 .muxregs = ssp1_dis_kbd_muxreg, 2226 .muxregs = ssp1_dis_kbd_muxreg,
2227 .nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg), 2227 .nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
2228 }, 2228 },
2229 }; 2229 };
2230 2230
2231 static struct spear_pingroup ssp1_dis_kbd_pingroup = { 2231 static struct spear_pingroup ssp1_dis_kbd_pingroup = {
2232 .name = "ssp1_dis_kbd_grp", 2232 .name = "ssp1_dis_kbd_grp",
2233 .pins = ssp1_dis_kbd_pins, 2233 .pins = ssp1_dis_kbd_pins,
2234 .npins = ARRAY_SIZE(ssp1_dis_kbd_pins), 2234 .npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
2235 .modemuxs = ssp1_dis_kbd_modemux, 2235 .modemuxs = ssp1_dis_kbd_modemux,
2236 .nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux), 2236 .nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
2237 }; 2237 };
2238 2238
2239 /* Pad multiplexing for ssp1_dis_sd device */ 2239 /* Pad multiplexing for ssp1_dis_sd device */
2240 static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 }; 2240 static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
2241 static struct spear_muxreg ssp1_dis_sd_muxreg[] = { 2241 static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
2242 { 2242 {
2243 .reg = PAD_FUNCTION_EN_2, 2243 .reg = PAD_FUNCTION_EN_2,
2244 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | 2244 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2245 PMX_MCICECF_MASK | PMX_MCICEXD_MASK, 2245 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2246 .val = 0, 2246 .val = 0,
2247 }, { 2247 }, {
2248 .reg = PAD_DIRECTION_SEL_2, 2248 .reg = PAD_DIRECTION_SEL_2,
2249 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | 2249 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2250 PMX_MCICECF_MASK | PMX_MCICEXD_MASK, 2250 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2251 .val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | 2251 .val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2252 PMX_MCICECF_MASK | PMX_MCICEXD_MASK, 2252 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2253 }, 2253 },
2254 }; 2254 };
2255 2255
2256 static struct spear_modemux ssp1_dis_sd_modemux[] = { 2256 static struct spear_modemux ssp1_dis_sd_modemux[] = {
2257 { 2257 {
2258 .muxregs = ssp1_dis_sd_muxreg, 2258 .muxregs = ssp1_dis_sd_muxreg,
2259 .nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg), 2259 .nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
2260 }, 2260 },
2261 }; 2261 };
2262 2262
2263 static struct spear_pingroup ssp1_dis_sd_pingroup = { 2263 static struct spear_pingroup ssp1_dis_sd_pingroup = {
2264 .name = "ssp1_dis_sd_grp", 2264 .name = "ssp1_dis_sd_grp",
2265 .pins = ssp1_dis_sd_pins, 2265 .pins = ssp1_dis_sd_pins,
2266 .npins = ARRAY_SIZE(ssp1_dis_sd_pins), 2266 .npins = ARRAY_SIZE(ssp1_dis_sd_pins),
2267 .modemuxs = ssp1_dis_sd_modemux, 2267 .modemuxs = ssp1_dis_sd_modemux,
2268 .nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux), 2268 .nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
2269 }; 2269 };
2270 2270
2271 static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp", 2271 static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
2272 "ssp1_dis_sd_grp" }; 2272 "ssp1_dis_sd_grp" };
2273 static struct spear_function ssp1_function = { 2273 static struct spear_function ssp1_function = {
2274 .name = "ssp1", 2274 .name = "ssp1",
2275 .groups = ssp1_grps, 2275 .groups = ssp1_grps,
2276 .ngroups = ARRAY_SIZE(ssp1_grps), 2276 .ngroups = ARRAY_SIZE(ssp1_grps),
2277 }; 2277 };
2278 2278
2279 /* Pad multiplexing for gpt64 device */ 2279 /* Pad multiplexing for gpt64 device */
2280 static const unsigned gpt64_pins[] = { 230, 231, 232, 245 }; 2280 static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
2281 static struct spear_muxreg gpt64_muxreg[] = { 2281 static struct spear_muxreg gpt64_muxreg[] = {
2282 { 2282 {
2283 .reg = PAD_FUNCTION_EN_2, 2283 .reg = PAD_FUNCTION_EN_2,
2284 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK 2284 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2285 | PMX_MCILEDS_MASK, 2285 | PMX_MCILEDS_MASK,
2286 .val = 0, 2286 .val = 0,
2287 }, { 2287 }, {
2288 .reg = PAD_DIRECTION_SEL_2, 2288 .reg = PAD_DIRECTION_SEL_2,
2289 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK 2289 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2290 | PMX_MCILEDS_MASK, 2290 | PMX_MCILEDS_MASK,
2291 .val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK 2291 .val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2292 | PMX_MCILEDS_MASK, 2292 | PMX_MCILEDS_MASK,
2293 }, 2293 },
2294 }; 2294 };
2295 2295
2296 static struct spear_modemux gpt64_modemux[] = { 2296 static struct spear_modemux gpt64_modemux[] = {
2297 { 2297 {
2298 .muxregs = gpt64_muxreg, 2298 .muxregs = gpt64_muxreg,
2299 .nmuxregs = ARRAY_SIZE(gpt64_muxreg), 2299 .nmuxregs = ARRAY_SIZE(gpt64_muxreg),
2300 }, 2300 },
2301 }; 2301 };
2302 2302
2303 static struct spear_pingroup gpt64_pingroup = { 2303 static struct spear_pingroup gpt64_pingroup = {
2304 .name = "gpt64_grp", 2304 .name = "gpt64_grp",
2305 .pins = gpt64_pins, 2305 .pins = gpt64_pins,
2306 .npins = ARRAY_SIZE(gpt64_pins), 2306 .npins = ARRAY_SIZE(gpt64_pins),
2307 .modemuxs = gpt64_modemux, 2307 .modemuxs = gpt64_modemux,
2308 .nmodemuxs = ARRAY_SIZE(gpt64_modemux), 2308 .nmodemuxs = ARRAY_SIZE(gpt64_modemux),
2309 }; 2309 };
2310 2310
2311 static const char *const gpt64_grps[] = { "gpt64_grp" }; 2311 static const char *const gpt64_grps[] = { "gpt64_grp" };
2312 static struct spear_function gpt64_function = { 2312 static struct spear_function gpt64_function = {
2313 .name = "gpt64", 2313 .name = "gpt64",
2314 .groups = gpt64_grps, 2314 .groups = gpt64_grps,
2315 .ngroups = ARRAY_SIZE(gpt64_grps), 2315 .ngroups = ARRAY_SIZE(gpt64_grps),
2316 }; 2316 };
2317 2317
2318 /* pingroups */ 2318 /* pingroups */
2319 static struct spear_pingroup *spear1310_pingroups[] = { 2319 static struct spear_pingroup *spear1310_pingroups[] = {
2320 &i2c0_pingroup, 2320 &i2c0_pingroup,
2321 &ssp0_pingroup, 2321 &ssp0_pingroup,
2322 &i2s0_pingroup, 2322 &i2s0_pingroup,
2323 &i2s1_pingroup, 2323 &i2s1_pingroup,
2324 &clcd_pingroup, 2324 &clcd_pingroup,
2325 &clcd_high_res_pingroup, 2325 &clcd_high_res_pingroup,
2326 &arm_gpio_pingroup, 2326 &arm_gpio_pingroup,
2327 &smi_2_chips_pingroup, 2327 &smi_2_chips_pingroup,
2328 &smi_4_chips_pingroup, 2328 &smi_4_chips_pingroup,
2329 &gmii_pingroup, 2329 &gmii_pingroup,
2330 &rgmii_pingroup, 2330 &rgmii_pingroup,
2331 &smii_0_1_2_pingroup, 2331 &smii_0_1_2_pingroup,
2332 &ras_mii_txclk_pingroup, 2332 &ras_mii_txclk_pingroup,
2333 &nand_8bit_pingroup, 2333 &nand_8bit_pingroup,
2334 &nand_16bit_pingroup, 2334 &nand_16bit_pingroup,
2335 &nand_4_chips_pingroup, 2335 &nand_4_chips_pingroup,
2336 &keyboard_6x6_pingroup, 2336 &keyboard_6x6_pingroup,
2337 &keyboard_rowcol6_8_pingroup, 2337 &keyboard_rowcol6_8_pingroup,
2338 &uart0_pingroup, 2338 &uart0_pingroup,
2339 &uart0_modem_pingroup, 2339 &uart0_modem_pingroup,
2340 &gpt0_tmr0_pingroup, 2340 &gpt0_tmr0_pingroup,
2341 &gpt0_tmr1_pingroup, 2341 &gpt0_tmr1_pingroup,
2342 &gpt1_tmr0_pingroup, 2342 &gpt1_tmr0_pingroup,
2343 &gpt1_tmr1_pingroup, 2343 &gpt1_tmr1_pingroup,
2344 &sdhci_pingroup, 2344 &sdhci_pingroup,
2345 &cf_pingroup, 2345 &cf_pingroup,
2346 &xd_pingroup, 2346 &xd_pingroup,
2347 &touch_xy_pingroup, 2347 &touch_xy_pingroup,
2348 &ssp0_cs0_pingroup, 2348 &ssp0_cs0_pingroup,
2349 &ssp0_cs1_2_pingroup, 2349 &ssp0_cs1_2_pingroup,
2350 &uart_1_dis_i2c_pingroup, 2350 &uart_1_dis_i2c_pingroup,
2351 &uart_1_dis_sd_pingroup, 2351 &uart_1_dis_sd_pingroup,
2352 &uart_2_3_pingroup, 2352 &uart_2_3_pingroup,
2353 &uart_4_pingroup, 2353 &uart_4_pingroup,
2354 &uart_5_pingroup, 2354 &uart_5_pingroup,
2355 &rs485_0_1_tdm_0_1_pingroup, 2355 &rs485_0_1_tdm_0_1_pingroup,
2356 &i2c_1_2_pingroup, 2356 &i2c_1_2_pingroup,
2357 &i2c3_dis_smi_clcd_pingroup, 2357 &i2c3_dis_smi_clcd_pingroup,
2358 &i2c3_dis_sd_i2s0_pingroup, 2358 &i2c3_dis_sd_i2s0_pingroup,
2359 &i2c_4_5_dis_smi_pingroup, 2359 &i2c_4_5_dis_smi_pingroup,
2360 &i2c4_dis_sd_pingroup, 2360 &i2c4_dis_sd_pingroup,
2361 &i2c5_dis_sd_pingroup, 2361 &i2c5_dis_sd_pingroup,
2362 &i2c_6_7_dis_kbd_pingroup, 2362 &i2c_6_7_dis_kbd_pingroup,
2363 &i2c6_dis_sd_pingroup, 2363 &i2c6_dis_sd_pingroup,
2364 &i2c7_dis_sd_pingroup, 2364 &i2c7_dis_sd_pingroup,
2365 &can0_dis_nor_pingroup, 2365 &can0_dis_nor_pingroup,
2366 &can0_dis_sd_pingroup, 2366 &can0_dis_sd_pingroup,
2367 &can1_dis_sd_pingroup, 2367 &can1_dis_sd_pingroup,
2368 &can1_dis_kbd_pingroup, 2368 &can1_dis_kbd_pingroup,
2369 &pci_pingroup, 2369 &pci_pingroup,
2370 &pcie0_pingroup, 2370 &pcie0_pingroup,
2371 &pcie1_pingroup, 2371 &pcie1_pingroup,
2372 &pcie2_pingroup, 2372 &pcie2_pingroup,
2373 &sata0_pingroup, 2373 &sata0_pingroup,
2374 &sata1_pingroup, 2374 &sata1_pingroup,
2375 &sata2_pingroup, 2375 &sata2_pingroup,
2376 &ssp1_dis_kbd_pingroup, 2376 &ssp1_dis_kbd_pingroup,
2377 &ssp1_dis_sd_pingroup, 2377 &ssp1_dis_sd_pingroup,
2378 &gpt64_pingroup, 2378 &gpt64_pingroup,
2379 }; 2379 };
2380 2380
2381 /* functions */ 2381 /* functions */
2382 static struct spear_function *spear1310_functions[] = { 2382 static struct spear_function *spear1310_functions[] = {
2383 &i2c0_function, 2383 &i2c0_function,
2384 &ssp0_function, 2384 &ssp0_function,
2385 &i2s0_function, 2385 &i2s0_function,
2386 &i2s1_function, 2386 &i2s1_function,
2387 &clcd_function, 2387 &clcd_function,
2388 &arm_gpio_function, 2388 &arm_gpio_function,
2389 &smi_function, 2389 &smi_function,
2390 &gmii_function, 2390 &gmii_function,
2391 &rgmii_function, 2391 &rgmii_function,
2392 &smii_0_1_2_function, 2392 &smii_0_1_2_function,
2393 &ras_mii_txclk_function, 2393 &ras_mii_txclk_function,
2394 &nand_function, 2394 &nand_function,
2395 &keyboard_function, 2395 &keyboard_function,
2396 &uart0_function, 2396 &uart0_function,
2397 &gpt0_function, 2397 &gpt0_function,
2398 &gpt1_function, 2398 &gpt1_function,
2399 &sdhci_function, 2399 &sdhci_function,
2400 &cf_function, 2400 &cf_function,
2401 &xd_function, 2401 &xd_function,
2402 &touch_xy_function, 2402 &touch_xy_function,
2403 &uart1_function, 2403 &uart1_function,
2404 &uart2_3_function, 2404 &uart2_3_function,
2405 &uart4_function, 2405 &uart4_function,
2406 &uart5_function, 2406 &uart5_function,
2407 &rs485_0_1_tdm_0_1_function, 2407 &rs485_0_1_tdm_0_1_function,
2408 &i2c_1_2_function, 2408 &i2c_1_2_function,
2409 &i2c3_unction, 2409 &i2c3_unction,
2410 &i2c_4_5_function, 2410 &i2c_4_5_function,
2411 &i2c_6_7_function, 2411 &i2c_6_7_function,
2412 &can0_function, 2412 &can0_function,
2413 &can1_function, 2413 &can1_function,
2414 &pci_function, 2414 &pci_function,
2415 &pcie_function, 2415 &pcie_function,
2416 &sata_function, 2416 &sata_function,
2417 &ssp1_function, 2417 &ssp1_function,
2418 &gpt64_function, 2418 &gpt64_function,
2419 }; 2419 };
2420 2420
2421 static struct spear_pinctrl_machdata spear1310_machdata = { 2421 static struct spear_pinctrl_machdata spear1310_machdata = {
2422 .pins = spear1310_pins, 2422 .pins = spear1310_pins,
2423 .npins = ARRAY_SIZE(spear1310_pins), 2423 .npins = ARRAY_SIZE(spear1310_pins),
2424 .groups = spear1310_pingroups, 2424 .groups = spear1310_pingroups,
2425 .ngroups = ARRAY_SIZE(spear1310_pingroups), 2425 .ngroups = ARRAY_SIZE(spear1310_pingroups),
2426 .functions = spear1310_functions, 2426 .functions = spear1310_functions,
2427 .nfunctions = ARRAY_SIZE(spear1310_functions), 2427 .nfunctions = ARRAY_SIZE(spear1310_functions),
2428 .modes_supported = false, 2428 .modes_supported = false,
2429 }; 2429 };
2430 2430
2431 static struct of_device_id spear1310_pinctrl_of_match[] = { 2431 static struct of_device_id spear1310_pinctrl_of_match[] = {
2432 { 2432 {
2433 .compatible = "st,spear1310-pinmux", 2433 .compatible = "st,spear1310-pinmux",
2434 }, 2434 },
2435 {}, 2435 {},
2436 }; 2436 };
2437 2437
2438 static int __devinit spear1310_pinctrl_probe(struct platform_device *pdev) 2438 static int __devinit spear1310_pinctrl_probe(struct platform_device *pdev)
2439 { 2439 {
2440 return spear_pinctrl_probe(pdev, &spear1310_machdata); 2440 return spear_pinctrl_probe(pdev, &spear1310_machdata);
2441 } 2441 }
2442 2442
2443 static int __devexit spear1310_pinctrl_remove(struct platform_device *pdev) 2443 static int spear1310_pinctrl_remove(struct platform_device *pdev)
2444 { 2444 {
2445 return spear_pinctrl_remove(pdev); 2445 return spear_pinctrl_remove(pdev);
2446 } 2446 }
2447 2447
2448 static struct platform_driver spear1310_pinctrl_driver = { 2448 static struct platform_driver spear1310_pinctrl_driver = {
2449 .driver = { 2449 .driver = {
2450 .name = DRIVER_NAME, 2450 .name = DRIVER_NAME,
2451 .owner = THIS_MODULE, 2451 .owner = THIS_MODULE,
2452 .of_match_table = spear1310_pinctrl_of_match, 2452 .of_match_table = spear1310_pinctrl_of_match,
2453 }, 2453 },
2454 .probe = spear1310_pinctrl_probe, 2454 .probe = spear1310_pinctrl_probe,
2455 .remove = spear1310_pinctrl_remove, 2455 .remove = spear1310_pinctrl_remove,
2456 }; 2456 };
2457 2457
2458 static int __init spear1310_pinctrl_init(void) 2458 static int __init spear1310_pinctrl_init(void)
2459 { 2459 {
2460 return platform_driver_register(&spear1310_pinctrl_driver); 2460 return platform_driver_register(&spear1310_pinctrl_driver);
2461 } 2461 }
2462 arch_initcall(spear1310_pinctrl_init); 2462 arch_initcall(spear1310_pinctrl_init);
2463 2463
2464 static void __exit spear1310_pinctrl_exit(void) 2464 static void __exit spear1310_pinctrl_exit(void)
2465 { 2465 {
2466 platform_driver_unregister(&spear1310_pinctrl_driver); 2466 platform_driver_unregister(&spear1310_pinctrl_driver);
2467 } 2467 }
2468 module_exit(spear1310_pinctrl_exit); 2468 module_exit(spear1310_pinctrl_exit);
2469 2469
2470 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); 2470 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
2471 MODULE_DESCRIPTION("ST Microelectronics SPEAr1310 pinctrl driver"); 2471 MODULE_DESCRIPTION("ST Microelectronics SPEAr1310 pinctrl driver");
2472 MODULE_LICENSE("GPL v2"); 2472 MODULE_LICENSE("GPL v2");
2473 MODULE_DEVICE_TABLE(of, spear1310_pinctrl_of_match); 2473 MODULE_DEVICE_TABLE(of, spear1310_pinctrl_of_match);
2474 2474
drivers/pinctrl/spear/pinctrl-spear1340.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Driver for the ST Microelectronics SPEAr1340 pinmux 2 * Driver for the ST Microelectronics SPEAr1340 pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/err.h> 12 #include <linux/err.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/module.h> 14 #include <linux/module.h>
15 #include <linux/of_device.h> 15 #include <linux/of_device.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include "pinctrl-spear.h" 17 #include "pinctrl-spear.h"
18 18
19 #define DRIVER_NAME "spear1340-pinmux" 19 #define DRIVER_NAME "spear1340-pinmux"
20 20
21 /* pins */ 21 /* pins */
22 static const struct pinctrl_pin_desc spear1340_pins[] = { 22 static const struct pinctrl_pin_desc spear1340_pins[] = {
23 SPEAR_PIN_0_TO_101, 23 SPEAR_PIN_0_TO_101,
24 SPEAR_PIN_102_TO_245, 24 SPEAR_PIN_102_TO_245,
25 PINCTRL_PIN(246, "PLGPIO246"), 25 PINCTRL_PIN(246, "PLGPIO246"),
26 PINCTRL_PIN(247, "PLGPIO247"), 26 PINCTRL_PIN(247, "PLGPIO247"),
27 PINCTRL_PIN(248, "PLGPIO248"), 27 PINCTRL_PIN(248, "PLGPIO248"),
28 PINCTRL_PIN(249, "PLGPIO249"), 28 PINCTRL_PIN(249, "PLGPIO249"),
29 PINCTRL_PIN(250, "PLGPIO250"), 29 PINCTRL_PIN(250, "PLGPIO250"),
30 PINCTRL_PIN(251, "PLGPIO251"), 30 PINCTRL_PIN(251, "PLGPIO251"),
31 }; 31 };
32 32
33 /* In SPEAr1340 there are two levels of pad muxing */ 33 /* In SPEAr1340 there are two levels of pad muxing */
34 /* - pads as gpio OR peripherals */ 34 /* - pads as gpio OR peripherals */
35 #define PAD_FUNCTION_EN_1 0x668 35 #define PAD_FUNCTION_EN_1 0x668
36 #define PAD_FUNCTION_EN_2 0x66C 36 #define PAD_FUNCTION_EN_2 0x66C
37 #define PAD_FUNCTION_EN_3 0x670 37 #define PAD_FUNCTION_EN_3 0x670
38 #define PAD_FUNCTION_EN_4 0x674 38 #define PAD_FUNCTION_EN_4 0x674
39 #define PAD_FUNCTION_EN_5 0x690 39 #define PAD_FUNCTION_EN_5 0x690
40 #define PAD_FUNCTION_EN_6 0x694 40 #define PAD_FUNCTION_EN_6 0x694
41 #define PAD_FUNCTION_EN_7 0x698 41 #define PAD_FUNCTION_EN_7 0x698
42 #define PAD_FUNCTION_EN_8 0x69C 42 #define PAD_FUNCTION_EN_8 0x69C
43 43
44 /* - If peripherals, then primary OR alternate peripheral */ 44 /* - If peripherals, then primary OR alternate peripheral */
45 #define PAD_SHARED_IP_EN_1 0x6A0 45 #define PAD_SHARED_IP_EN_1 0x6A0
46 #define PAD_SHARED_IP_EN_2 0x6A4 46 #define PAD_SHARED_IP_EN_2 0x6A4
47 47
48 /* 48 /*
49 * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8 49 * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8
50 * registers with 32 bits each for handling gpio pads, register 8 has only 26 50 * registers with 32 bits each for handling gpio pads, register 8 has only 26
51 * relevant bits. 51 * relevant bits.
52 */ 52 */
53 /* macro's for making pads as gpio's */ 53 /* macro's for making pads as gpio's */
54 #define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE 54 #define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE
55 #define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF 55 #define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF
56 #define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF 56 #define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF
57 57
58 /* macro's for making pads as peripherals */ 58 /* macro's for making pads as peripherals */
59 #define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE 59 #define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE
60 #define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000 60 #define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000
61 #define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000 61 #define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000
62 #define I2C1_REG0_MASK 0x01080000 62 #define I2C1_REG0_MASK 0x01080000
63 #define SPDIF_IN_REG0_MASK 0x00100000 63 #define SPDIF_IN_REG0_MASK 0x00100000
64 #define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000 64 #define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000
65 #define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000 65 #define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000
66 #define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000 66 #define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000
67 #define VIP_AND_CAM3_REG0_MASK 0xFC200000 67 #define VIP_AND_CAM3_REG0_MASK 0xFC200000
68 #define VIP_AND_CAM3_REG1_MASK 0x0000000F 68 #define VIP_AND_CAM3_REG1_MASK 0x0000000F
69 #define VIP_REG1_MASK 0x00001EF0 69 #define VIP_REG1_MASK 0x00001EF0
70 #define VIP_AND_CAM2_REG1_MASK 0x007FE100 70 #define VIP_AND_CAM2_REG1_MASK 0x007FE100
71 #define VIP_AND_CAM1_REG1_MASK 0xFF800000 71 #define VIP_AND_CAM1_REG1_MASK 0xFF800000
72 #define VIP_AND_CAM1_REG2_MASK 0x00000003 72 #define VIP_AND_CAM1_REG2_MASK 0x00000003
73 #define VIP_AND_CAM0_REG2_MASK 0x00001FFC 73 #define VIP_AND_CAM0_REG2_MASK 0x00001FFC
74 #define SMI_REG2_MASK 0x0021E000 74 #define SMI_REG2_MASK 0x0021E000
75 #define SSP0_REG2_MASK 0x001E0000 75 #define SSP0_REG2_MASK 0x001E0000
76 #define TS_AND_SSP0_CS2_REG2_MASK 0x00400000 76 #define TS_AND_SSP0_CS2_REG2_MASK 0x00400000
77 #define UART0_REG2_MASK 0x01800000 77 #define UART0_REG2_MASK 0x01800000
78 #define UART1_REG2_MASK 0x06000000 78 #define UART1_REG2_MASK 0x06000000
79 #define I2S_IN_REG2_MASK 0xF8000000 79 #define I2S_IN_REG2_MASK 0xF8000000
80 #define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE 80 #define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE
81 #define I2S_OUT_REG3_MASK 0x000001EF 81 #define I2S_OUT_REG3_MASK 0x000001EF
82 #define I2S_IN_REG3_MASK 0x00000010 82 #define I2S_IN_REG3_MASK 0x00000010
83 #define GMAC_REG3_MASK 0xFFFFFE00 83 #define GMAC_REG3_MASK 0xFFFFFE00
84 #define GMAC_REG4_MASK 0x0000001F 84 #define GMAC_REG4_MASK 0x0000001F
85 #define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20 85 #define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20
86 #define SSP0_CS3_REG4_MASK 0x00000020 86 #define SSP0_CS3_REG4_MASK 0x00000020
87 #define I2C0_REG4_MASK 0x000000C0 87 #define I2C0_REG4_MASK 0x000000C0
88 #define CEC0_REG4_MASK 0x00000100 88 #define CEC0_REG4_MASK 0x00000100
89 #define CEC1_REG4_MASK 0x00000200 89 #define CEC1_REG4_MASK 0x00000200
90 #define SPDIF_OUT_REG4_MASK 0x00000400 90 #define SPDIF_OUT_REG4_MASK 0x00000400
91 #define CLCD_REG4_MASK 0x7FFFF800 91 #define CLCD_REG4_MASK 0x7FFFF800
92 #define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000 92 #define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000
93 #define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF 93 #define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF
94 #define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001 94 #define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001
95 #define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE 95 #define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE
96 #define MCIF_REG6_MASK 0xF8C00000 96 #define MCIF_REG6_MASK 0xF8C00000
97 #define MCIF_REG7_MASK 0x000043FF 97 #define MCIF_REG7_MASK 0x000043FF
98 #define FSMC_8BIT_REG7_MASK 0x07FFBC00 98 #define FSMC_8BIT_REG7_MASK 0x07FFBC00
99 99
100 /* other registers */ 100 /* other registers */
101 #define PERIP_CFG 0x42C 101 #define PERIP_CFG 0x42C
102 /* PERIP_CFG register masks */ 102 /* PERIP_CFG register masks */
103 #define SSP_CS_CTL_HW 0 103 #define SSP_CS_CTL_HW 0
104 #define SSP_CS_CTL_SW 1 104 #define SSP_CS_CTL_SW 1
105 #define SSP_CS_CTL_MASK 1 105 #define SSP_CS_CTL_MASK 1
106 #define SSP_CS_CTL_SHIFT 21 106 #define SSP_CS_CTL_SHIFT 21
107 #define SSP_CS_VAL_MASK 1 107 #define SSP_CS_VAL_MASK 1
108 #define SSP_CS_VAL_SHIFT 20 108 #define SSP_CS_VAL_SHIFT 20
109 #define SSP_CS_SEL_CS0 0 109 #define SSP_CS_SEL_CS0 0
110 #define SSP_CS_SEL_CS1 1 110 #define SSP_CS_SEL_CS1 1
111 #define SSP_CS_SEL_CS2 2 111 #define SSP_CS_SEL_CS2 2
112 #define SSP_CS_SEL_MASK 3 112 #define SSP_CS_SEL_MASK 3
113 #define SSP_CS_SEL_SHIFT 18 113 #define SSP_CS_SEL_SHIFT 18
114 114
115 #define I2S_CHNL_2_0 (0) 115 #define I2S_CHNL_2_0 (0)
116 #define I2S_CHNL_3_1 (1) 116 #define I2S_CHNL_3_1 (1)
117 #define I2S_CHNL_5_1 (2) 117 #define I2S_CHNL_5_1 (2)
118 #define I2S_CHNL_7_1 (3) 118 #define I2S_CHNL_7_1 (3)
119 #define I2S_CHNL_PLAY_SHIFT (4) 119 #define I2S_CHNL_PLAY_SHIFT (4)
120 #define I2S_CHNL_PLAY_MASK (3 << 4) 120 #define I2S_CHNL_PLAY_MASK (3 << 4)
121 #define I2S_CHNL_REC_SHIFT (6) 121 #define I2S_CHNL_REC_SHIFT (6)
122 #define I2S_CHNL_REC_MASK (3 << 6) 122 #define I2S_CHNL_REC_MASK (3 << 6)
123 123
124 #define SPDIF_OUT_ENB_MASK (1 << 2) 124 #define SPDIF_OUT_ENB_MASK (1 << 2)
125 #define SPDIF_OUT_ENB_SHIFT 2 125 #define SPDIF_OUT_ENB_SHIFT 2
126 126
127 #define MCIF_SEL_SD 1 127 #define MCIF_SEL_SD 1
128 #define MCIF_SEL_CF 2 128 #define MCIF_SEL_CF 2
129 #define MCIF_SEL_XD 3 129 #define MCIF_SEL_XD 3
130 #define MCIF_SEL_MASK 3 130 #define MCIF_SEL_MASK 3
131 #define MCIF_SEL_SHIFT 0 131 #define MCIF_SEL_SHIFT 0
132 132
133 #define GMAC_CLK_CFG 0x248 133 #define GMAC_CLK_CFG 0x248
134 #define GMAC_PHY_IF_GMII_VAL (0 << 3) 134 #define GMAC_PHY_IF_GMII_VAL (0 << 3)
135 #define GMAC_PHY_IF_RGMII_VAL (1 << 3) 135 #define GMAC_PHY_IF_RGMII_VAL (1 << 3)
136 #define GMAC_PHY_IF_SGMII_VAL (2 << 3) 136 #define GMAC_PHY_IF_SGMII_VAL (2 << 3)
137 #define GMAC_PHY_IF_RMII_VAL (4 << 3) 137 #define GMAC_PHY_IF_RMII_VAL (4 << 3)
138 #define GMAC_PHY_IF_SEL_MASK (7 << 3) 138 #define GMAC_PHY_IF_SEL_MASK (7 << 3)
139 #define GMAC_PHY_INPUT_ENB_VAL 0 139 #define GMAC_PHY_INPUT_ENB_VAL 0
140 #define GMAC_PHY_SYNT_ENB_VAL 1 140 #define GMAC_PHY_SYNT_ENB_VAL 1
141 #define GMAC_PHY_CLK_MASK 1 141 #define GMAC_PHY_CLK_MASK 1
142 #define GMAC_PHY_CLK_SHIFT 2 142 #define GMAC_PHY_CLK_SHIFT 2
143 #define GMAC_PHY_125M_PAD_VAL 0 143 #define GMAC_PHY_125M_PAD_VAL 0
144 #define GMAC_PHY_PLL2_VAL 1 144 #define GMAC_PHY_PLL2_VAL 1
145 #define GMAC_PHY_OSC3_VAL 2 145 #define GMAC_PHY_OSC3_VAL 2
146 #define GMAC_PHY_INPUT_CLK_MASK 3 146 #define GMAC_PHY_INPUT_CLK_MASK 3
147 #define GMAC_PHY_INPUT_CLK_SHIFT 0 147 #define GMAC_PHY_INPUT_CLK_SHIFT 0
148 148
149 #define PCIE_SATA_CFG 0x424 149 #define PCIE_SATA_CFG 0x424
150 /* PCIE CFG MASks */ 150 /* PCIE CFG MASks */
151 #define PCIE_CFG_DEVICE_PRESENT (1 << 11) 151 #define PCIE_CFG_DEVICE_PRESENT (1 << 11)
152 #define PCIE_CFG_POWERUP_RESET (1 << 10) 152 #define PCIE_CFG_POWERUP_RESET (1 << 10)
153 #define PCIE_CFG_CORE_CLK_EN (1 << 9) 153 #define PCIE_CFG_CORE_CLK_EN (1 << 9)
154 #define PCIE_CFG_AUX_CLK_EN (1 << 8) 154 #define PCIE_CFG_AUX_CLK_EN (1 << 8)
155 #define SATA_CFG_TX_CLK_EN (1 << 4) 155 #define SATA_CFG_TX_CLK_EN (1 << 4)
156 #define SATA_CFG_RX_CLK_EN (1 << 3) 156 #define SATA_CFG_RX_CLK_EN (1 << 3)
157 #define SATA_CFG_POWERUP_RESET (1 << 2) 157 #define SATA_CFG_POWERUP_RESET (1 << 2)
158 #define SATA_CFG_PM_CLK_EN (1 << 1) 158 #define SATA_CFG_PM_CLK_EN (1 << 1)
159 #define PCIE_SATA_SEL_PCIE (0) 159 #define PCIE_SATA_SEL_PCIE (0)
160 #define PCIE_SATA_SEL_SATA (1) 160 #define PCIE_SATA_SEL_SATA (1)
161 #define SATA_PCIE_CFG_MASK 0xF1F 161 #define SATA_PCIE_CFG_MASK 0xF1F
162 #define PCIE_CFG_VAL (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \ 162 #define PCIE_CFG_VAL (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \
163 PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\ 163 PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\
164 PCIE_CFG_DEVICE_PRESENT) 164 PCIE_CFG_DEVICE_PRESENT)
165 #define SATA_CFG_VAL (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \ 165 #define SATA_CFG_VAL (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \
166 SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \ 166 SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \
167 SATA_CFG_TX_CLK_EN) 167 SATA_CFG_TX_CLK_EN)
168 168
169 /* Macro's for second level of pmx - pads as primary OR alternate peripheral */ 169 /* Macro's for second level of pmx - pads as primary OR alternate peripheral */
170 /* Write 0 to enable FSMC_16_BIT */ 170 /* Write 0 to enable FSMC_16_BIT */
171 #define KBD_ROW_COL_MASK (1 << 0) 171 #define KBD_ROW_COL_MASK (1 << 0)
172 172
173 /* Write 0 to enable UART0_ENH */ 173 /* Write 0 to enable UART0_ENH */
174 #define GPT_MASK (1 << 1) /* Only clk & cpt */ 174 #define GPT_MASK (1 << 1) /* Only clk & cpt */
175 175
176 /* Write 0 to enable PWM1 */ 176 /* Write 0 to enable PWM1 */
177 #define KBD_COL5_MASK (1 << 2) 177 #define KBD_COL5_MASK (1 << 2)
178 178
179 /* Write 0 to enable PWM2 */ 179 /* Write 0 to enable PWM2 */
180 #define GPT0_TMR0_CPT_MASK (1 << 3) /* Only clk & cpt */ 180 #define GPT0_TMR0_CPT_MASK (1 << 3) /* Only clk & cpt */
181 181
182 /* Write 0 to enable PWM3 */ 182 /* Write 0 to enable PWM3 */
183 #define GPT0_TMR1_CLK_MASK (1 << 4) /* Only clk & cpt */ 183 #define GPT0_TMR1_CLK_MASK (1 << 4) /* Only clk & cpt */
184 184
185 /* Write 0 to enable PWM0 */ 185 /* Write 0 to enable PWM0 */
186 #define SSP0_CS1_MASK (1 << 5) 186 #define SSP0_CS1_MASK (1 << 5)
187 187
188 /* Write 0 to enable VIP */ 188 /* Write 0 to enable VIP */
189 #define CAM3_MASK (1 << 6) 189 #define CAM3_MASK (1 << 6)
190 190
191 /* Write 0 to enable VIP */ 191 /* Write 0 to enable VIP */
192 #define CAM2_MASK (1 << 7) 192 #define CAM2_MASK (1 << 7)
193 193
194 /* Write 0 to enable VIP */ 194 /* Write 0 to enable VIP */
195 #define CAM1_MASK (1 << 8) 195 #define CAM1_MASK (1 << 8)
196 196
197 /* Write 0 to enable VIP */ 197 /* Write 0 to enable VIP */
198 #define CAM0_MASK (1 << 9) 198 #define CAM0_MASK (1 << 9)
199 199
200 /* Write 0 to enable TS */ 200 /* Write 0 to enable TS */
201 #define SSP0_CS2_MASK (1 << 10) 201 #define SSP0_CS2_MASK (1 << 10)
202 202
203 /* Write 0 to enable FSMC PNOR */ 203 /* Write 0 to enable FSMC PNOR */
204 #define MCIF_MASK (1 << 11) 204 #define MCIF_MASK (1 << 11)
205 205
206 /* Write 0 to enable CLCD */ 206 /* Write 0 to enable CLCD */
207 #define ARM_TRACE_MASK (1 << 12) 207 #define ARM_TRACE_MASK (1 << 12)
208 208
209 /* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */ 209 /* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */
210 #define MIPHY_DBG_MASK (1 << 13) 210 #define MIPHY_DBG_MASK (1 << 13)
211 211
212 /* 212 /*
213 * Pad multiplexing for making all pads as gpio's. This is done to override the 213 * Pad multiplexing for making all pads as gpio's. This is done to override the
214 * values passed from bootloader and start from scratch. 214 * values passed from bootloader and start from scratch.
215 */ 215 */
216 static const unsigned pads_as_gpio_pins[] = { 12, 88, 89, 251 }; 216 static const unsigned pads_as_gpio_pins[] = { 12, 88, 89, 251 };
217 static struct spear_muxreg pads_as_gpio_muxreg[] = { 217 static struct spear_muxreg pads_as_gpio_muxreg[] = {
218 { 218 {
219 .reg = PAD_FUNCTION_EN_1, 219 .reg = PAD_FUNCTION_EN_1,
220 .mask = PADS_AS_GPIO_REG0_MASK, 220 .mask = PADS_AS_GPIO_REG0_MASK,
221 .val = 0x0, 221 .val = 0x0,
222 }, { 222 }, {
223 .reg = PAD_FUNCTION_EN_2, 223 .reg = PAD_FUNCTION_EN_2,
224 .mask = PADS_AS_GPIO_REGS_MASK, 224 .mask = PADS_AS_GPIO_REGS_MASK,
225 .val = 0x0, 225 .val = 0x0,
226 }, { 226 }, {
227 .reg = PAD_FUNCTION_EN_3, 227 .reg = PAD_FUNCTION_EN_3,
228 .mask = PADS_AS_GPIO_REGS_MASK, 228 .mask = PADS_AS_GPIO_REGS_MASK,
229 .val = 0x0, 229 .val = 0x0,
230 }, { 230 }, {
231 .reg = PAD_FUNCTION_EN_4, 231 .reg = PAD_FUNCTION_EN_4,
232 .mask = PADS_AS_GPIO_REGS_MASK, 232 .mask = PADS_AS_GPIO_REGS_MASK,
233 .val = 0x0, 233 .val = 0x0,
234 }, { 234 }, {
235 .reg = PAD_FUNCTION_EN_5, 235 .reg = PAD_FUNCTION_EN_5,
236 .mask = PADS_AS_GPIO_REGS_MASK, 236 .mask = PADS_AS_GPIO_REGS_MASK,
237 .val = 0x0, 237 .val = 0x0,
238 }, { 238 }, {
239 .reg = PAD_FUNCTION_EN_6, 239 .reg = PAD_FUNCTION_EN_6,
240 .mask = PADS_AS_GPIO_REGS_MASK, 240 .mask = PADS_AS_GPIO_REGS_MASK,
241 .val = 0x0, 241 .val = 0x0,
242 }, { 242 }, {
243 .reg = PAD_FUNCTION_EN_7, 243 .reg = PAD_FUNCTION_EN_7,
244 .mask = PADS_AS_GPIO_REGS_MASK, 244 .mask = PADS_AS_GPIO_REGS_MASK,
245 .val = 0x0, 245 .val = 0x0,
246 }, { 246 }, {
247 .reg = PAD_FUNCTION_EN_8, 247 .reg = PAD_FUNCTION_EN_8,
248 .mask = PADS_AS_GPIO_REG7_MASK, 248 .mask = PADS_AS_GPIO_REG7_MASK,
249 .val = 0x0, 249 .val = 0x0,
250 }, 250 },
251 }; 251 };
252 252
253 static struct spear_modemux pads_as_gpio_modemux[] = { 253 static struct spear_modemux pads_as_gpio_modemux[] = {
254 { 254 {
255 .muxregs = pads_as_gpio_muxreg, 255 .muxregs = pads_as_gpio_muxreg,
256 .nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg), 256 .nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg),
257 }, 257 },
258 }; 258 };
259 259
260 static struct spear_pingroup pads_as_gpio_pingroup = { 260 static struct spear_pingroup pads_as_gpio_pingroup = {
261 .name = "pads_as_gpio_grp", 261 .name = "pads_as_gpio_grp",
262 .pins = pads_as_gpio_pins, 262 .pins = pads_as_gpio_pins,
263 .npins = ARRAY_SIZE(pads_as_gpio_pins), 263 .npins = ARRAY_SIZE(pads_as_gpio_pins),
264 .modemuxs = pads_as_gpio_modemux, 264 .modemuxs = pads_as_gpio_modemux,
265 .nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux), 265 .nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux),
266 }; 266 };
267 267
268 static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" }; 268 static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" };
269 static struct spear_function pads_as_gpio_function = { 269 static struct spear_function pads_as_gpio_function = {
270 .name = "pads_as_gpio", 270 .name = "pads_as_gpio",
271 .groups = pads_as_gpio_grps, 271 .groups = pads_as_gpio_grps,
272 .ngroups = ARRAY_SIZE(pads_as_gpio_grps), 272 .ngroups = ARRAY_SIZE(pads_as_gpio_grps),
273 }; 273 };
274 274
275 /* Pad multiplexing for fsmc_8bit device */ 275 /* Pad multiplexing for fsmc_8bit device */
276 static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240, 276 static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240,
277 241, 242, 243, 244, 245, 246, 247, 248, 249 }; 277 241, 242, 243, 244, 245, 246, 247, 248, 249 };
278 static struct spear_muxreg fsmc_8bit_muxreg[] = { 278 static struct spear_muxreg fsmc_8bit_muxreg[] = {
279 { 279 {
280 .reg = PAD_FUNCTION_EN_8, 280 .reg = PAD_FUNCTION_EN_8,
281 .mask = FSMC_8BIT_REG7_MASK, 281 .mask = FSMC_8BIT_REG7_MASK,
282 .val = FSMC_8BIT_REG7_MASK, 282 .val = FSMC_8BIT_REG7_MASK,
283 } 283 }
284 }; 284 };
285 285
286 static struct spear_modemux fsmc_8bit_modemux[] = { 286 static struct spear_modemux fsmc_8bit_modemux[] = {
287 { 287 {
288 .muxregs = fsmc_8bit_muxreg, 288 .muxregs = fsmc_8bit_muxreg,
289 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), 289 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
290 }, 290 },
291 }; 291 };
292 292
293 static struct spear_pingroup fsmc_8bit_pingroup = { 293 static struct spear_pingroup fsmc_8bit_pingroup = {
294 .name = "fsmc_8bit_grp", 294 .name = "fsmc_8bit_grp",
295 .pins = fsmc_8bit_pins, 295 .pins = fsmc_8bit_pins,
296 .npins = ARRAY_SIZE(fsmc_8bit_pins), 296 .npins = ARRAY_SIZE(fsmc_8bit_pins),
297 .modemuxs = fsmc_8bit_modemux, 297 .modemuxs = fsmc_8bit_modemux,
298 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux), 298 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
299 }; 299 };
300 300
301 /* Pad multiplexing for fsmc_16bit device */ 301 /* Pad multiplexing for fsmc_16bit device */
302 static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 }; 302 static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
303 static struct spear_muxreg fsmc_16bit_muxreg[] = { 303 static struct spear_muxreg fsmc_16bit_muxreg[] = {
304 { 304 {
305 .reg = PAD_SHARED_IP_EN_1, 305 .reg = PAD_SHARED_IP_EN_1,
306 .mask = KBD_ROW_COL_MASK, 306 .mask = KBD_ROW_COL_MASK,
307 .val = 0, 307 .val = 0,
308 }, { 308 }, {
309 .reg = PAD_FUNCTION_EN_1, 309 .reg = PAD_FUNCTION_EN_1,
310 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, 310 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
311 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, 311 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
312 }, 312 },
313 }; 313 };
314 314
315 static struct spear_modemux fsmc_16bit_modemux[] = { 315 static struct spear_modemux fsmc_16bit_modemux[] = {
316 { 316 {
317 .muxregs = fsmc_16bit_muxreg, 317 .muxregs = fsmc_16bit_muxreg,
318 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg), 318 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
319 }, 319 },
320 }; 320 };
321 321
322 static struct spear_pingroup fsmc_16bit_pingroup = { 322 static struct spear_pingroup fsmc_16bit_pingroup = {
323 .name = "fsmc_16bit_grp", 323 .name = "fsmc_16bit_grp",
324 .pins = fsmc_16bit_pins, 324 .pins = fsmc_16bit_pins,
325 .npins = ARRAY_SIZE(fsmc_16bit_pins), 325 .npins = ARRAY_SIZE(fsmc_16bit_pins),
326 .modemuxs = fsmc_16bit_modemux, 326 .modemuxs = fsmc_16bit_modemux,
327 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux), 327 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
328 }; 328 };
329 329
330 /* pad multiplexing for fsmc_pnor device */ 330 /* pad multiplexing for fsmc_pnor device */
331 static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198, 331 static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198,
332 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 332 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212,
333 215, 216, 217 }; 333 215, 216, 217 };
334 static struct spear_muxreg fsmc_pnor_muxreg[] = { 334 static struct spear_muxreg fsmc_pnor_muxreg[] = {
335 { 335 {
336 .reg = PAD_SHARED_IP_EN_1, 336 .reg = PAD_SHARED_IP_EN_1,
337 .mask = MCIF_MASK, 337 .mask = MCIF_MASK,
338 .val = 0, 338 .val = 0,
339 }, { 339 }, {
340 .reg = PAD_FUNCTION_EN_7, 340 .reg = PAD_FUNCTION_EN_7,
341 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK, 341 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK,
342 .val = FSMC_PNOR_AND_MCIF_REG6_MASK, 342 .val = FSMC_PNOR_AND_MCIF_REG6_MASK,
343 }, 343 },
344 }; 344 };
345 345
346 static struct spear_modemux fsmc_pnor_modemux[] = { 346 static struct spear_modemux fsmc_pnor_modemux[] = {
347 { 347 {
348 .muxregs = fsmc_pnor_muxreg, 348 .muxregs = fsmc_pnor_muxreg,
349 .nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg), 349 .nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg),
350 }, 350 },
351 }; 351 };
352 352
353 static struct spear_pingroup fsmc_pnor_pingroup = { 353 static struct spear_pingroup fsmc_pnor_pingroup = {
354 .name = "fsmc_pnor_grp", 354 .name = "fsmc_pnor_grp",
355 .pins = fsmc_pnor_pins, 355 .pins = fsmc_pnor_pins,
356 .npins = ARRAY_SIZE(fsmc_pnor_pins), 356 .npins = ARRAY_SIZE(fsmc_pnor_pins),
357 .modemuxs = fsmc_pnor_modemux, 357 .modemuxs = fsmc_pnor_modemux,
358 .nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux), 358 .nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux),
359 }; 359 };
360 360
361 static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp", 361 static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp",
362 "fsmc_pnor_grp" }; 362 "fsmc_pnor_grp" };
363 static struct spear_function fsmc_function = { 363 static struct spear_function fsmc_function = {
364 .name = "fsmc", 364 .name = "fsmc",
365 .groups = fsmc_grps, 365 .groups = fsmc_grps,
366 .ngroups = ARRAY_SIZE(fsmc_grps), 366 .ngroups = ARRAY_SIZE(fsmc_grps),
367 }; 367 };
368 368
369 /* pad multiplexing for keyboard rows-cols device */ 369 /* pad multiplexing for keyboard rows-cols device */
370 static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 370 static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
371 10 }; 371 10 };
372 static struct spear_muxreg keyboard_row_col_muxreg[] = { 372 static struct spear_muxreg keyboard_row_col_muxreg[] = {
373 { 373 {
374 .reg = PAD_SHARED_IP_EN_1, 374 .reg = PAD_SHARED_IP_EN_1,
375 .mask = KBD_ROW_COL_MASK, 375 .mask = KBD_ROW_COL_MASK,
376 .val = KBD_ROW_COL_MASK, 376 .val = KBD_ROW_COL_MASK,
377 }, { 377 }, {
378 .reg = PAD_FUNCTION_EN_1, 378 .reg = PAD_FUNCTION_EN_1,
379 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, 379 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
380 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, 380 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
381 }, 381 },
382 }; 382 };
383 383
384 static struct spear_modemux keyboard_row_col_modemux[] = { 384 static struct spear_modemux keyboard_row_col_modemux[] = {
385 { 385 {
386 .muxregs = keyboard_row_col_muxreg, 386 .muxregs = keyboard_row_col_muxreg,
387 .nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg), 387 .nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg),
388 }, 388 },
389 }; 389 };
390 390
391 static struct spear_pingroup keyboard_row_col_pingroup = { 391 static struct spear_pingroup keyboard_row_col_pingroup = {
392 .name = "keyboard_row_col_grp", 392 .name = "keyboard_row_col_grp",
393 .pins = keyboard_row_col_pins, 393 .pins = keyboard_row_col_pins,
394 .npins = ARRAY_SIZE(keyboard_row_col_pins), 394 .npins = ARRAY_SIZE(keyboard_row_col_pins),
395 .modemuxs = keyboard_row_col_modemux, 395 .modemuxs = keyboard_row_col_modemux,
396 .nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux), 396 .nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux),
397 }; 397 };
398 398
399 /* pad multiplexing for keyboard col5 device */ 399 /* pad multiplexing for keyboard col5 device */
400 static const unsigned keyboard_col5_pins[] = { 17 }; 400 static const unsigned keyboard_col5_pins[] = { 17 };
401 static struct spear_muxreg keyboard_col5_muxreg[] = { 401 static struct spear_muxreg keyboard_col5_muxreg[] = {
402 { 402 {
403 .reg = PAD_SHARED_IP_EN_1, 403 .reg = PAD_SHARED_IP_EN_1,
404 .mask = KBD_COL5_MASK, 404 .mask = KBD_COL5_MASK,
405 .val = KBD_COL5_MASK, 405 .val = KBD_COL5_MASK,
406 }, { 406 }, {
407 .reg = PAD_FUNCTION_EN_1, 407 .reg = PAD_FUNCTION_EN_1,
408 .mask = PWM1_AND_KBD_COL5_REG0_MASK, 408 .mask = PWM1_AND_KBD_COL5_REG0_MASK,
409 .val = PWM1_AND_KBD_COL5_REG0_MASK, 409 .val = PWM1_AND_KBD_COL5_REG0_MASK,
410 }, 410 },
411 }; 411 };
412 412
413 static struct spear_modemux keyboard_col5_modemux[] = { 413 static struct spear_modemux keyboard_col5_modemux[] = {
414 { 414 {
415 .muxregs = keyboard_col5_muxreg, 415 .muxregs = keyboard_col5_muxreg,
416 .nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg), 416 .nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg),
417 }, 417 },
418 }; 418 };
419 419
420 static struct spear_pingroup keyboard_col5_pingroup = { 420 static struct spear_pingroup keyboard_col5_pingroup = {
421 .name = "keyboard_col5_grp", 421 .name = "keyboard_col5_grp",
422 .pins = keyboard_col5_pins, 422 .pins = keyboard_col5_pins,
423 .npins = ARRAY_SIZE(keyboard_col5_pins), 423 .npins = ARRAY_SIZE(keyboard_col5_pins),
424 .modemuxs = keyboard_col5_modemux, 424 .modemuxs = keyboard_col5_modemux,
425 .nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux), 425 .nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux),
426 }; 426 };
427 427
428 static const char *const keyboard_grps[] = { "keyboard_row_col_grp", 428 static const char *const keyboard_grps[] = { "keyboard_row_col_grp",
429 "keyboard_col5_grp" }; 429 "keyboard_col5_grp" };
430 static struct spear_function keyboard_function = { 430 static struct spear_function keyboard_function = {
431 .name = "keyboard", 431 .name = "keyboard",
432 .groups = keyboard_grps, 432 .groups = keyboard_grps,
433 .ngroups = ARRAY_SIZE(keyboard_grps), 433 .ngroups = ARRAY_SIZE(keyboard_grps),
434 }; 434 };
435 435
436 /* pad multiplexing for spdif_in device */ 436 /* pad multiplexing for spdif_in device */
437 static const unsigned spdif_in_pins[] = { 19 }; 437 static const unsigned spdif_in_pins[] = { 19 };
438 static struct spear_muxreg spdif_in_muxreg[] = { 438 static struct spear_muxreg spdif_in_muxreg[] = {
439 { 439 {
440 .reg = PAD_FUNCTION_EN_1, 440 .reg = PAD_FUNCTION_EN_1,
441 .mask = SPDIF_IN_REG0_MASK, 441 .mask = SPDIF_IN_REG0_MASK,
442 .val = SPDIF_IN_REG0_MASK, 442 .val = SPDIF_IN_REG0_MASK,
443 }, 443 },
444 }; 444 };
445 445
446 static struct spear_modemux spdif_in_modemux[] = { 446 static struct spear_modemux spdif_in_modemux[] = {
447 { 447 {
448 .muxregs = spdif_in_muxreg, 448 .muxregs = spdif_in_muxreg,
449 .nmuxregs = ARRAY_SIZE(spdif_in_muxreg), 449 .nmuxregs = ARRAY_SIZE(spdif_in_muxreg),
450 }, 450 },
451 }; 451 };
452 452
453 static struct spear_pingroup spdif_in_pingroup = { 453 static struct spear_pingroup spdif_in_pingroup = {
454 .name = "spdif_in_grp", 454 .name = "spdif_in_grp",
455 .pins = spdif_in_pins, 455 .pins = spdif_in_pins,
456 .npins = ARRAY_SIZE(spdif_in_pins), 456 .npins = ARRAY_SIZE(spdif_in_pins),
457 .modemuxs = spdif_in_modemux, 457 .modemuxs = spdif_in_modemux,
458 .nmodemuxs = ARRAY_SIZE(spdif_in_modemux), 458 .nmodemuxs = ARRAY_SIZE(spdif_in_modemux),
459 }; 459 };
460 460
461 static const char *const spdif_in_grps[] = { "spdif_in_grp" }; 461 static const char *const spdif_in_grps[] = { "spdif_in_grp" };
462 static struct spear_function spdif_in_function = { 462 static struct spear_function spdif_in_function = {
463 .name = "spdif_in", 463 .name = "spdif_in",
464 .groups = spdif_in_grps, 464 .groups = spdif_in_grps,
465 .ngroups = ARRAY_SIZE(spdif_in_grps), 465 .ngroups = ARRAY_SIZE(spdif_in_grps),
466 }; 466 };
467 467
468 /* pad multiplexing for spdif_out device */ 468 /* pad multiplexing for spdif_out device */
469 static const unsigned spdif_out_pins[] = { 137 }; 469 static const unsigned spdif_out_pins[] = { 137 };
470 static struct spear_muxreg spdif_out_muxreg[] = { 470 static struct spear_muxreg spdif_out_muxreg[] = {
471 { 471 {
472 .reg = PAD_FUNCTION_EN_5, 472 .reg = PAD_FUNCTION_EN_5,
473 .mask = SPDIF_OUT_REG4_MASK, 473 .mask = SPDIF_OUT_REG4_MASK,
474 .val = SPDIF_OUT_REG4_MASK, 474 .val = SPDIF_OUT_REG4_MASK,
475 }, { 475 }, {
476 .reg = PERIP_CFG, 476 .reg = PERIP_CFG,
477 .mask = SPDIF_OUT_ENB_MASK, 477 .mask = SPDIF_OUT_ENB_MASK,
478 .val = SPDIF_OUT_ENB_MASK, 478 .val = SPDIF_OUT_ENB_MASK,
479 } 479 }
480 }; 480 };
481 481
482 static struct spear_modemux spdif_out_modemux[] = { 482 static struct spear_modemux spdif_out_modemux[] = {
483 { 483 {
484 .muxregs = spdif_out_muxreg, 484 .muxregs = spdif_out_muxreg,
485 .nmuxregs = ARRAY_SIZE(spdif_out_muxreg), 485 .nmuxregs = ARRAY_SIZE(spdif_out_muxreg),
486 }, 486 },
487 }; 487 };
488 488
489 static struct spear_pingroup spdif_out_pingroup = { 489 static struct spear_pingroup spdif_out_pingroup = {
490 .name = "spdif_out_grp", 490 .name = "spdif_out_grp",
491 .pins = spdif_out_pins, 491 .pins = spdif_out_pins,
492 .npins = ARRAY_SIZE(spdif_out_pins), 492 .npins = ARRAY_SIZE(spdif_out_pins),
493 .modemuxs = spdif_out_modemux, 493 .modemuxs = spdif_out_modemux,
494 .nmodemuxs = ARRAY_SIZE(spdif_out_modemux), 494 .nmodemuxs = ARRAY_SIZE(spdif_out_modemux),
495 }; 495 };
496 496
497 static const char *const spdif_out_grps[] = { "spdif_out_grp" }; 497 static const char *const spdif_out_grps[] = { "spdif_out_grp" };
498 static struct spear_function spdif_out_function = { 498 static struct spear_function spdif_out_function = {
499 .name = "spdif_out", 499 .name = "spdif_out",
500 .groups = spdif_out_grps, 500 .groups = spdif_out_grps,
501 .ngroups = ARRAY_SIZE(spdif_out_grps), 501 .ngroups = ARRAY_SIZE(spdif_out_grps),
502 }; 502 };
503 503
504 /* pad multiplexing for gpt_0_1 device */ 504 /* pad multiplexing for gpt_0_1 device */
505 static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 }; 505 static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 };
506 static struct spear_muxreg gpt_0_1_muxreg[] = { 506 static struct spear_muxreg gpt_0_1_muxreg[] = {
507 { 507 {
508 .reg = PAD_SHARED_IP_EN_1, 508 .reg = PAD_SHARED_IP_EN_1,
509 .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK, 509 .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
510 .val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK, 510 .val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
511 }, { 511 }, {
512 .reg = PAD_FUNCTION_EN_1, 512 .reg = PAD_FUNCTION_EN_1,
513 .mask = UART0_ENH_AND_GPT_REG0_MASK | 513 .mask = UART0_ENH_AND_GPT_REG0_MASK |
514 PWM2_AND_GPT0_TMR0_CPT_REG0_MASK | 514 PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
515 PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, 515 PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
516 .val = UART0_ENH_AND_GPT_REG0_MASK | 516 .val = UART0_ENH_AND_GPT_REG0_MASK |
517 PWM2_AND_GPT0_TMR0_CPT_REG0_MASK | 517 PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
518 PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, 518 PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
519 }, 519 },
520 }; 520 };
521 521
522 static struct spear_modemux gpt_0_1_modemux[] = { 522 static struct spear_modemux gpt_0_1_modemux[] = {
523 { 523 {
524 .muxregs = gpt_0_1_muxreg, 524 .muxregs = gpt_0_1_muxreg,
525 .nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg), 525 .nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg),
526 }, 526 },
527 }; 527 };
528 528
529 static struct spear_pingroup gpt_0_1_pingroup = { 529 static struct spear_pingroup gpt_0_1_pingroup = {
530 .name = "gpt_0_1_grp", 530 .name = "gpt_0_1_grp",
531 .pins = gpt_0_1_pins, 531 .pins = gpt_0_1_pins,
532 .npins = ARRAY_SIZE(gpt_0_1_pins), 532 .npins = ARRAY_SIZE(gpt_0_1_pins),
533 .modemuxs = gpt_0_1_modemux, 533 .modemuxs = gpt_0_1_modemux,
534 .nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux), 534 .nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux),
535 }; 535 };
536 536
537 static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" }; 537 static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" };
538 static struct spear_function gpt_0_1_function = { 538 static struct spear_function gpt_0_1_function = {
539 .name = "gpt_0_1", 539 .name = "gpt_0_1",
540 .groups = gpt_0_1_grps, 540 .groups = gpt_0_1_grps,
541 .ngroups = ARRAY_SIZE(gpt_0_1_grps), 541 .ngroups = ARRAY_SIZE(gpt_0_1_grps),
542 }; 542 };
543 543
544 /* pad multiplexing for pwm0 device */ 544 /* pad multiplexing for pwm0 device */
545 static const unsigned pwm0_pins[] = { 24 }; 545 static const unsigned pwm0_pins[] = { 24 };
546 static struct spear_muxreg pwm0_muxreg[] = { 546 static struct spear_muxreg pwm0_muxreg[] = {
547 { 547 {
548 .reg = PAD_SHARED_IP_EN_1, 548 .reg = PAD_SHARED_IP_EN_1,
549 .mask = SSP0_CS1_MASK, 549 .mask = SSP0_CS1_MASK,
550 .val = 0, 550 .val = 0,
551 }, { 551 }, {
552 .reg = PAD_FUNCTION_EN_1, 552 .reg = PAD_FUNCTION_EN_1,
553 .mask = PWM0_AND_SSP0_CS1_REG0_MASK, 553 .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
554 .val = PWM0_AND_SSP0_CS1_REG0_MASK, 554 .val = PWM0_AND_SSP0_CS1_REG0_MASK,
555 }, 555 },
556 }; 556 };
557 557
558 static struct spear_modemux pwm0_modemux[] = { 558 static struct spear_modemux pwm0_modemux[] = {
559 { 559 {
560 .muxregs = pwm0_muxreg, 560 .muxregs = pwm0_muxreg,
561 .nmuxregs = ARRAY_SIZE(pwm0_muxreg), 561 .nmuxregs = ARRAY_SIZE(pwm0_muxreg),
562 }, 562 },
563 }; 563 };
564 564
565 static struct spear_pingroup pwm0_pingroup = { 565 static struct spear_pingroup pwm0_pingroup = {
566 .name = "pwm0_grp", 566 .name = "pwm0_grp",
567 .pins = pwm0_pins, 567 .pins = pwm0_pins,
568 .npins = ARRAY_SIZE(pwm0_pins), 568 .npins = ARRAY_SIZE(pwm0_pins),
569 .modemuxs = pwm0_modemux, 569 .modemuxs = pwm0_modemux,
570 .nmodemuxs = ARRAY_SIZE(pwm0_modemux), 570 .nmodemuxs = ARRAY_SIZE(pwm0_modemux),
571 }; 571 };
572 572
573 /* pad multiplexing for pwm1 device */ 573 /* pad multiplexing for pwm1 device */
574 static const unsigned pwm1_pins[] = { 17 }; 574 static const unsigned pwm1_pins[] = { 17 };
575 static struct spear_muxreg pwm1_muxreg[] = { 575 static struct spear_muxreg pwm1_muxreg[] = {
576 { 576 {
577 .reg = PAD_SHARED_IP_EN_1, 577 .reg = PAD_SHARED_IP_EN_1,
578 .mask = KBD_COL5_MASK, 578 .mask = KBD_COL5_MASK,
579 .val = 0, 579 .val = 0,
580 }, { 580 }, {
581 .reg = PAD_FUNCTION_EN_1, 581 .reg = PAD_FUNCTION_EN_1,
582 .mask = PWM1_AND_KBD_COL5_REG0_MASK, 582 .mask = PWM1_AND_KBD_COL5_REG0_MASK,
583 .val = PWM1_AND_KBD_COL5_REG0_MASK, 583 .val = PWM1_AND_KBD_COL5_REG0_MASK,
584 }, 584 },
585 }; 585 };
586 586
587 static struct spear_modemux pwm1_modemux[] = { 587 static struct spear_modemux pwm1_modemux[] = {
588 { 588 {
589 .muxregs = pwm1_muxreg, 589 .muxregs = pwm1_muxreg,
590 .nmuxregs = ARRAY_SIZE(pwm1_muxreg), 590 .nmuxregs = ARRAY_SIZE(pwm1_muxreg),
591 }, 591 },
592 }; 592 };
593 593
594 static struct spear_pingroup pwm1_pingroup = { 594 static struct spear_pingroup pwm1_pingroup = {
595 .name = "pwm1_grp", 595 .name = "pwm1_grp",
596 .pins = pwm1_pins, 596 .pins = pwm1_pins,
597 .npins = ARRAY_SIZE(pwm1_pins), 597 .npins = ARRAY_SIZE(pwm1_pins),
598 .modemuxs = pwm1_modemux, 598 .modemuxs = pwm1_modemux,
599 .nmodemuxs = ARRAY_SIZE(pwm1_modemux), 599 .nmodemuxs = ARRAY_SIZE(pwm1_modemux),
600 }; 600 };
601 601
602 /* pad multiplexing for pwm2 device */ 602 /* pad multiplexing for pwm2 device */
603 static const unsigned pwm2_pins[] = { 21 }; 603 static const unsigned pwm2_pins[] = { 21 };
604 static struct spear_muxreg pwm2_muxreg[] = { 604 static struct spear_muxreg pwm2_muxreg[] = {
605 { 605 {
606 .reg = PAD_SHARED_IP_EN_1, 606 .reg = PAD_SHARED_IP_EN_1,
607 .mask = GPT0_TMR0_CPT_MASK, 607 .mask = GPT0_TMR0_CPT_MASK,
608 .val = 0, 608 .val = 0,
609 }, { 609 }, {
610 .reg = PAD_FUNCTION_EN_1, 610 .reg = PAD_FUNCTION_EN_1,
611 .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK, 611 .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
612 .val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK, 612 .val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
613 }, 613 },
614 }; 614 };
615 615
616 static struct spear_modemux pwm2_modemux[] = { 616 static struct spear_modemux pwm2_modemux[] = {
617 { 617 {
618 .muxregs = pwm2_muxreg, 618 .muxregs = pwm2_muxreg,
619 .nmuxregs = ARRAY_SIZE(pwm2_muxreg), 619 .nmuxregs = ARRAY_SIZE(pwm2_muxreg),
620 }, 620 },
621 }; 621 };
622 622
623 static struct spear_pingroup pwm2_pingroup = { 623 static struct spear_pingroup pwm2_pingroup = {
624 .name = "pwm2_grp", 624 .name = "pwm2_grp",
625 .pins = pwm2_pins, 625 .pins = pwm2_pins,
626 .npins = ARRAY_SIZE(pwm2_pins), 626 .npins = ARRAY_SIZE(pwm2_pins),
627 .modemuxs = pwm2_modemux, 627 .modemuxs = pwm2_modemux,
628 .nmodemuxs = ARRAY_SIZE(pwm2_modemux), 628 .nmodemuxs = ARRAY_SIZE(pwm2_modemux),
629 }; 629 };
630 630
631 /* pad multiplexing for pwm3 device */ 631 /* pad multiplexing for pwm3 device */
632 static const unsigned pwm3_pins[] = { 22 }; 632 static const unsigned pwm3_pins[] = { 22 };
633 static struct spear_muxreg pwm3_muxreg[] = { 633 static struct spear_muxreg pwm3_muxreg[] = {
634 { 634 {
635 .reg = PAD_SHARED_IP_EN_1, 635 .reg = PAD_SHARED_IP_EN_1,
636 .mask = GPT0_TMR1_CLK_MASK, 636 .mask = GPT0_TMR1_CLK_MASK,
637 .val = 0, 637 .val = 0,
638 }, { 638 }, {
639 .reg = PAD_FUNCTION_EN_1, 639 .reg = PAD_FUNCTION_EN_1,
640 .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, 640 .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
641 .val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, 641 .val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
642 }, 642 },
643 }; 643 };
644 644
645 static struct spear_modemux pwm3_modemux[] = { 645 static struct spear_modemux pwm3_modemux[] = {
646 { 646 {
647 .muxregs = pwm3_muxreg, 647 .muxregs = pwm3_muxreg,
648 .nmuxregs = ARRAY_SIZE(pwm3_muxreg), 648 .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
649 }, 649 },
650 }; 650 };
651 651
652 static struct spear_pingroup pwm3_pingroup = { 652 static struct spear_pingroup pwm3_pingroup = {
653 .name = "pwm3_grp", 653 .name = "pwm3_grp",
654 .pins = pwm3_pins, 654 .pins = pwm3_pins,
655 .npins = ARRAY_SIZE(pwm3_pins), 655 .npins = ARRAY_SIZE(pwm3_pins),
656 .modemuxs = pwm3_modemux, 656 .modemuxs = pwm3_modemux,
657 .nmodemuxs = ARRAY_SIZE(pwm3_modemux), 657 .nmodemuxs = ARRAY_SIZE(pwm3_modemux),
658 }; 658 };
659 659
660 static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp", 660 static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp",
661 "pwm3_grp" }; 661 "pwm3_grp" };
662 static struct spear_function pwm_function = { 662 static struct spear_function pwm_function = {
663 .name = "pwm", 663 .name = "pwm",
664 .groups = pwm_grps, 664 .groups = pwm_grps,
665 .ngroups = ARRAY_SIZE(pwm_grps), 665 .ngroups = ARRAY_SIZE(pwm_grps),
666 }; 666 };
667 667
668 /* pad multiplexing for vip_mux device */ 668 /* pad multiplexing for vip_mux device */
669 static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 }; 669 static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 };
670 static struct spear_muxreg vip_mux_muxreg[] = { 670 static struct spear_muxreg vip_mux_muxreg[] = {
671 { 671 {
672 .reg = PAD_FUNCTION_EN_2, 672 .reg = PAD_FUNCTION_EN_2,
673 .mask = VIP_REG1_MASK, 673 .mask = VIP_REG1_MASK,
674 .val = VIP_REG1_MASK, 674 .val = VIP_REG1_MASK,
675 }, 675 },
676 }; 676 };
677 677
678 static struct spear_modemux vip_mux_modemux[] = { 678 static struct spear_modemux vip_mux_modemux[] = {
679 { 679 {
680 .muxregs = vip_mux_muxreg, 680 .muxregs = vip_mux_muxreg,
681 .nmuxregs = ARRAY_SIZE(vip_mux_muxreg), 681 .nmuxregs = ARRAY_SIZE(vip_mux_muxreg),
682 }, 682 },
683 }; 683 };
684 684
685 static struct spear_pingroup vip_mux_pingroup = { 685 static struct spear_pingroup vip_mux_pingroup = {
686 .name = "vip_mux_grp", 686 .name = "vip_mux_grp",
687 .pins = vip_mux_pins, 687 .pins = vip_mux_pins,
688 .npins = ARRAY_SIZE(vip_mux_pins), 688 .npins = ARRAY_SIZE(vip_mux_pins),
689 .modemuxs = vip_mux_modemux, 689 .modemuxs = vip_mux_modemux,
690 .nmodemuxs = ARRAY_SIZE(vip_mux_modemux), 690 .nmodemuxs = ARRAY_SIZE(vip_mux_modemux),
691 }; 691 };
692 692
693 /* pad multiplexing for vip_mux_cam0 (disables cam0) device */ 693 /* pad multiplexing for vip_mux_cam0 (disables cam0) device */
694 static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 694 static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72,
695 73, 74, 75 }; 695 73, 74, 75 };
696 static struct spear_muxreg vip_mux_cam0_muxreg[] = { 696 static struct spear_muxreg vip_mux_cam0_muxreg[] = {
697 { 697 {
698 .reg = PAD_SHARED_IP_EN_1, 698 .reg = PAD_SHARED_IP_EN_1,
699 .mask = CAM0_MASK, 699 .mask = CAM0_MASK,
700 .val = 0, 700 .val = 0,
701 }, { 701 }, {
702 .reg = PAD_FUNCTION_EN_3, 702 .reg = PAD_FUNCTION_EN_3,
703 .mask = VIP_AND_CAM0_REG2_MASK, 703 .mask = VIP_AND_CAM0_REG2_MASK,
704 .val = VIP_AND_CAM0_REG2_MASK, 704 .val = VIP_AND_CAM0_REG2_MASK,
705 }, 705 },
706 }; 706 };
707 707
708 static struct spear_modemux vip_mux_cam0_modemux[] = { 708 static struct spear_modemux vip_mux_cam0_modemux[] = {
709 { 709 {
710 .muxregs = vip_mux_cam0_muxreg, 710 .muxregs = vip_mux_cam0_muxreg,
711 .nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg), 711 .nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg),
712 }, 712 },
713 }; 713 };
714 714
715 static struct spear_pingroup vip_mux_cam0_pingroup = { 715 static struct spear_pingroup vip_mux_cam0_pingroup = {
716 .name = "vip_mux_cam0_grp", 716 .name = "vip_mux_cam0_grp",
717 .pins = vip_mux_cam0_pins, 717 .pins = vip_mux_cam0_pins,
718 .npins = ARRAY_SIZE(vip_mux_cam0_pins), 718 .npins = ARRAY_SIZE(vip_mux_cam0_pins),
719 .modemuxs = vip_mux_cam0_modemux, 719 .modemuxs = vip_mux_cam0_modemux,
720 .nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux), 720 .nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux),
721 }; 721 };
722 722
723 /* pad multiplexing for vip_mux_cam1 (disables cam1) device */ 723 /* pad multiplexing for vip_mux_cam1 (disables cam1) device */
724 static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 724 static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61,
725 62, 63, 64 }; 725 62, 63, 64 };
726 static struct spear_muxreg vip_mux_cam1_muxreg[] = { 726 static struct spear_muxreg vip_mux_cam1_muxreg[] = {
727 { 727 {
728 .reg = PAD_SHARED_IP_EN_1, 728 .reg = PAD_SHARED_IP_EN_1,
729 .mask = CAM1_MASK, 729 .mask = CAM1_MASK,
730 .val = 0, 730 .val = 0,
731 }, { 731 }, {
732 .reg = PAD_FUNCTION_EN_2, 732 .reg = PAD_FUNCTION_EN_2,
733 .mask = VIP_AND_CAM1_REG1_MASK, 733 .mask = VIP_AND_CAM1_REG1_MASK,
734 .val = VIP_AND_CAM1_REG1_MASK, 734 .val = VIP_AND_CAM1_REG1_MASK,
735 }, { 735 }, {
736 .reg = PAD_FUNCTION_EN_3, 736 .reg = PAD_FUNCTION_EN_3,
737 .mask = VIP_AND_CAM1_REG2_MASK, 737 .mask = VIP_AND_CAM1_REG2_MASK,
738 .val = VIP_AND_CAM1_REG2_MASK, 738 .val = VIP_AND_CAM1_REG2_MASK,
739 }, 739 },
740 }; 740 };
741 741
742 static struct spear_modemux vip_mux_cam1_modemux[] = { 742 static struct spear_modemux vip_mux_cam1_modemux[] = {
743 { 743 {
744 .muxregs = vip_mux_cam1_muxreg, 744 .muxregs = vip_mux_cam1_muxreg,
745 .nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg), 745 .nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg),
746 }, 746 },
747 }; 747 };
748 748
749 static struct spear_pingroup vip_mux_cam1_pingroup = { 749 static struct spear_pingroup vip_mux_cam1_pingroup = {
750 .name = "vip_mux_cam1_grp", 750 .name = "vip_mux_cam1_grp",
751 .pins = vip_mux_cam1_pins, 751 .pins = vip_mux_cam1_pins,
752 .npins = ARRAY_SIZE(vip_mux_cam1_pins), 752 .npins = ARRAY_SIZE(vip_mux_cam1_pins),
753 .modemuxs = vip_mux_cam1_modemux, 753 .modemuxs = vip_mux_cam1_modemux,
754 .nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux), 754 .nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux),
755 }; 755 };
756 756
757 /* pad multiplexing for vip_mux_cam2 (disables cam2) device */ 757 /* pad multiplexing for vip_mux_cam2 (disables cam2) device */
758 static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 758 static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50,
759 51, 52, 53 }; 759 51, 52, 53 };
760 static struct spear_muxreg vip_mux_cam2_muxreg[] = { 760 static struct spear_muxreg vip_mux_cam2_muxreg[] = {
761 { 761 {
762 .reg = PAD_SHARED_IP_EN_1, 762 .reg = PAD_SHARED_IP_EN_1,
763 .mask = CAM2_MASK, 763 .mask = CAM2_MASK,
764 .val = 0, 764 .val = 0,
765 }, { 765 }, {
766 .reg = PAD_FUNCTION_EN_2, 766 .reg = PAD_FUNCTION_EN_2,
767 .mask = VIP_AND_CAM2_REG1_MASK, 767 .mask = VIP_AND_CAM2_REG1_MASK,
768 .val = VIP_AND_CAM2_REG1_MASK, 768 .val = VIP_AND_CAM2_REG1_MASK,
769 }, 769 },
770 }; 770 };
771 771
772 static struct spear_modemux vip_mux_cam2_modemux[] = { 772 static struct spear_modemux vip_mux_cam2_modemux[] = {
773 { 773 {
774 .muxregs = vip_mux_cam2_muxreg, 774 .muxregs = vip_mux_cam2_muxreg,
775 .nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg), 775 .nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg),
776 }, 776 },
777 }; 777 };
778 778
779 static struct spear_pingroup vip_mux_cam2_pingroup = { 779 static struct spear_pingroup vip_mux_cam2_pingroup = {
780 .name = "vip_mux_cam2_grp", 780 .name = "vip_mux_cam2_grp",
781 .pins = vip_mux_cam2_pins, 781 .pins = vip_mux_cam2_pins,
782 .npins = ARRAY_SIZE(vip_mux_cam2_pins), 782 .npins = ARRAY_SIZE(vip_mux_cam2_pins),
783 .modemuxs = vip_mux_cam2_modemux, 783 .modemuxs = vip_mux_cam2_modemux,
784 .nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux), 784 .nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux),
785 }; 785 };
786 786
787 /* pad multiplexing for vip_mux_cam3 (disables cam3) device */ 787 /* pad multiplexing for vip_mux_cam3 (disables cam3) device */
788 static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 788 static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31,
789 32, 33, 34 }; 789 32, 33, 34 };
790 static struct spear_muxreg vip_mux_cam3_muxreg[] = { 790 static struct spear_muxreg vip_mux_cam3_muxreg[] = {
791 { 791 {
792 .reg = PAD_SHARED_IP_EN_1, 792 .reg = PAD_SHARED_IP_EN_1,
793 .mask = CAM3_MASK, 793 .mask = CAM3_MASK,
794 .val = 0, 794 .val = 0,
795 }, { 795 }, {
796 .reg = PAD_FUNCTION_EN_1, 796 .reg = PAD_FUNCTION_EN_1,
797 .mask = VIP_AND_CAM3_REG0_MASK, 797 .mask = VIP_AND_CAM3_REG0_MASK,
798 .val = VIP_AND_CAM3_REG0_MASK, 798 .val = VIP_AND_CAM3_REG0_MASK,
799 }, { 799 }, {
800 .reg = PAD_FUNCTION_EN_2, 800 .reg = PAD_FUNCTION_EN_2,
801 .mask = VIP_AND_CAM3_REG1_MASK, 801 .mask = VIP_AND_CAM3_REG1_MASK,
802 .val = VIP_AND_CAM3_REG1_MASK, 802 .val = VIP_AND_CAM3_REG1_MASK,
803 }, 803 },
804 }; 804 };
805 805
806 static struct spear_modemux vip_mux_cam3_modemux[] = { 806 static struct spear_modemux vip_mux_cam3_modemux[] = {
807 { 807 {
808 .muxregs = vip_mux_cam3_muxreg, 808 .muxregs = vip_mux_cam3_muxreg,
809 .nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg), 809 .nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg),
810 }, 810 },
811 }; 811 };
812 812
813 static struct spear_pingroup vip_mux_cam3_pingroup = { 813 static struct spear_pingroup vip_mux_cam3_pingroup = {
814 .name = "vip_mux_cam3_grp", 814 .name = "vip_mux_cam3_grp",
815 .pins = vip_mux_cam3_pins, 815 .pins = vip_mux_cam3_pins,
816 .npins = ARRAY_SIZE(vip_mux_cam3_pins), 816 .npins = ARRAY_SIZE(vip_mux_cam3_pins),
817 .modemuxs = vip_mux_cam3_modemux, 817 .modemuxs = vip_mux_cam3_modemux,
818 .nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux), 818 .nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux),
819 }; 819 };
820 820
821 static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" , 821 static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" ,
822 "vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" }; 822 "vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" };
823 static struct spear_function vip_function = { 823 static struct spear_function vip_function = {
824 .name = "vip", 824 .name = "vip",
825 .groups = vip_grps, 825 .groups = vip_grps,
826 .ngroups = ARRAY_SIZE(vip_grps), 826 .ngroups = ARRAY_SIZE(vip_grps),
827 }; 827 };
828 828
829 /* pad multiplexing for cam0 device */ 829 /* pad multiplexing for cam0 device */
830 static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 830 static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75
831 }; 831 };
832 static struct spear_muxreg cam0_muxreg[] = { 832 static struct spear_muxreg cam0_muxreg[] = {
833 { 833 {
834 .reg = PAD_SHARED_IP_EN_1, 834 .reg = PAD_SHARED_IP_EN_1,
835 .mask = CAM0_MASK, 835 .mask = CAM0_MASK,
836 .val = CAM0_MASK, 836 .val = CAM0_MASK,
837 }, { 837 }, {
838 .reg = PAD_FUNCTION_EN_3, 838 .reg = PAD_FUNCTION_EN_3,
839 .mask = VIP_AND_CAM0_REG2_MASK, 839 .mask = VIP_AND_CAM0_REG2_MASK,
840 .val = VIP_AND_CAM0_REG2_MASK, 840 .val = VIP_AND_CAM0_REG2_MASK,
841 }, 841 },
842 }; 842 };
843 843
844 static struct spear_modemux cam0_modemux[] = { 844 static struct spear_modemux cam0_modemux[] = {
845 { 845 {
846 .muxregs = cam0_muxreg, 846 .muxregs = cam0_muxreg,
847 .nmuxregs = ARRAY_SIZE(cam0_muxreg), 847 .nmuxregs = ARRAY_SIZE(cam0_muxreg),
848 }, 848 },
849 }; 849 };
850 850
851 static struct spear_pingroup cam0_pingroup = { 851 static struct spear_pingroup cam0_pingroup = {
852 .name = "cam0_grp", 852 .name = "cam0_grp",
853 .pins = cam0_pins, 853 .pins = cam0_pins,
854 .npins = ARRAY_SIZE(cam0_pins), 854 .npins = ARRAY_SIZE(cam0_pins),
855 .modemuxs = cam0_modemux, 855 .modemuxs = cam0_modemux,
856 .nmodemuxs = ARRAY_SIZE(cam0_modemux), 856 .nmodemuxs = ARRAY_SIZE(cam0_modemux),
857 }; 857 };
858 858
859 static const char *const cam0_grps[] = { "cam0_grp" }; 859 static const char *const cam0_grps[] = { "cam0_grp" };
860 static struct spear_function cam0_function = { 860 static struct spear_function cam0_function = {
861 .name = "cam0", 861 .name = "cam0",
862 .groups = cam0_grps, 862 .groups = cam0_grps,
863 .ngroups = ARRAY_SIZE(cam0_grps), 863 .ngroups = ARRAY_SIZE(cam0_grps),
864 }; 864 };
865 865
866 /* pad multiplexing for cam1 device */ 866 /* pad multiplexing for cam1 device */
867 static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 867 static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
868 }; 868 };
869 static struct spear_muxreg cam1_muxreg[] = { 869 static struct spear_muxreg cam1_muxreg[] = {
870 { 870 {
871 .reg = PAD_SHARED_IP_EN_1, 871 .reg = PAD_SHARED_IP_EN_1,
872 .mask = CAM1_MASK, 872 .mask = CAM1_MASK,
873 .val = CAM1_MASK, 873 .val = CAM1_MASK,
874 }, { 874 }, {
875 .reg = PAD_FUNCTION_EN_2, 875 .reg = PAD_FUNCTION_EN_2,
876 .mask = VIP_AND_CAM1_REG1_MASK, 876 .mask = VIP_AND_CAM1_REG1_MASK,
877 .val = VIP_AND_CAM1_REG1_MASK, 877 .val = VIP_AND_CAM1_REG1_MASK,
878 }, { 878 }, {
879 .reg = PAD_FUNCTION_EN_3, 879 .reg = PAD_FUNCTION_EN_3,
880 .mask = VIP_AND_CAM1_REG2_MASK, 880 .mask = VIP_AND_CAM1_REG2_MASK,
881 .val = VIP_AND_CAM1_REG2_MASK, 881 .val = VIP_AND_CAM1_REG2_MASK,
882 }, 882 },
883 }; 883 };
884 884
885 static struct spear_modemux cam1_modemux[] = { 885 static struct spear_modemux cam1_modemux[] = {
886 { 886 {
887 .muxregs = cam1_muxreg, 887 .muxregs = cam1_muxreg,
888 .nmuxregs = ARRAY_SIZE(cam1_muxreg), 888 .nmuxregs = ARRAY_SIZE(cam1_muxreg),
889 }, 889 },
890 }; 890 };
891 891
892 static struct spear_pingroup cam1_pingroup = { 892 static struct spear_pingroup cam1_pingroup = {
893 .name = "cam1_grp", 893 .name = "cam1_grp",
894 .pins = cam1_pins, 894 .pins = cam1_pins,
895 .npins = ARRAY_SIZE(cam1_pins), 895 .npins = ARRAY_SIZE(cam1_pins),
896 .modemuxs = cam1_modemux, 896 .modemuxs = cam1_modemux,
897 .nmodemuxs = ARRAY_SIZE(cam1_modemux), 897 .nmodemuxs = ARRAY_SIZE(cam1_modemux),
898 }; 898 };
899 899
900 static const char *const cam1_grps[] = { "cam1_grp" }; 900 static const char *const cam1_grps[] = { "cam1_grp" };
901 static struct spear_function cam1_function = { 901 static struct spear_function cam1_function = {
902 .name = "cam1", 902 .name = "cam1",
903 .groups = cam1_grps, 903 .groups = cam1_grps,
904 .ngroups = ARRAY_SIZE(cam1_grps), 904 .ngroups = ARRAY_SIZE(cam1_grps),
905 }; 905 };
906 906
907 /* pad multiplexing for cam2 device */ 907 /* pad multiplexing for cam2 device */
908 static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 908 static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53
909 }; 909 };
910 static struct spear_muxreg cam2_muxreg[] = { 910 static struct spear_muxreg cam2_muxreg[] = {
911 { 911 {
912 .reg = PAD_SHARED_IP_EN_1, 912 .reg = PAD_SHARED_IP_EN_1,
913 .mask = CAM2_MASK, 913 .mask = CAM2_MASK,
914 .val = CAM2_MASK, 914 .val = CAM2_MASK,
915 }, { 915 }, {
916 .reg = PAD_FUNCTION_EN_2, 916 .reg = PAD_FUNCTION_EN_2,
917 .mask = VIP_AND_CAM2_REG1_MASK, 917 .mask = VIP_AND_CAM2_REG1_MASK,
918 .val = VIP_AND_CAM2_REG1_MASK, 918 .val = VIP_AND_CAM2_REG1_MASK,
919 }, 919 },
920 }; 920 };
921 921
922 static struct spear_modemux cam2_modemux[] = { 922 static struct spear_modemux cam2_modemux[] = {
923 { 923 {
924 .muxregs = cam2_muxreg, 924 .muxregs = cam2_muxreg,
925 .nmuxregs = ARRAY_SIZE(cam2_muxreg), 925 .nmuxregs = ARRAY_SIZE(cam2_muxreg),
926 }, 926 },
927 }; 927 };
928 928
929 static struct spear_pingroup cam2_pingroup = { 929 static struct spear_pingroup cam2_pingroup = {
930 .name = "cam2_grp", 930 .name = "cam2_grp",
931 .pins = cam2_pins, 931 .pins = cam2_pins,
932 .npins = ARRAY_SIZE(cam2_pins), 932 .npins = ARRAY_SIZE(cam2_pins),
933 .modemuxs = cam2_modemux, 933 .modemuxs = cam2_modemux,
934 .nmodemuxs = ARRAY_SIZE(cam2_modemux), 934 .nmodemuxs = ARRAY_SIZE(cam2_modemux),
935 }; 935 };
936 936
937 static const char *const cam2_grps[] = { "cam2_grp" }; 937 static const char *const cam2_grps[] = { "cam2_grp" };
938 static struct spear_function cam2_function = { 938 static struct spear_function cam2_function = {
939 .name = "cam2", 939 .name = "cam2",
940 .groups = cam2_grps, 940 .groups = cam2_grps,
941 .ngroups = ARRAY_SIZE(cam2_grps), 941 .ngroups = ARRAY_SIZE(cam2_grps),
942 }; 942 };
943 943
944 /* pad multiplexing for cam3 device */ 944 /* pad multiplexing for cam3 device */
945 static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 945 static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
946 }; 946 };
947 static struct spear_muxreg cam3_muxreg[] = { 947 static struct spear_muxreg cam3_muxreg[] = {
948 { 948 {
949 .reg = PAD_SHARED_IP_EN_1, 949 .reg = PAD_SHARED_IP_EN_1,
950 .mask = CAM3_MASK, 950 .mask = CAM3_MASK,
951 .val = CAM3_MASK, 951 .val = CAM3_MASK,
952 }, { 952 }, {
953 .reg = PAD_FUNCTION_EN_1, 953 .reg = PAD_FUNCTION_EN_1,
954 .mask = VIP_AND_CAM3_REG0_MASK, 954 .mask = VIP_AND_CAM3_REG0_MASK,
955 .val = VIP_AND_CAM3_REG0_MASK, 955 .val = VIP_AND_CAM3_REG0_MASK,
956 }, { 956 }, {
957 .reg = PAD_FUNCTION_EN_2, 957 .reg = PAD_FUNCTION_EN_2,
958 .mask = VIP_AND_CAM3_REG1_MASK, 958 .mask = VIP_AND_CAM3_REG1_MASK,
959 .val = VIP_AND_CAM3_REG1_MASK, 959 .val = VIP_AND_CAM3_REG1_MASK,
960 }, 960 },
961 }; 961 };
962 962
963 static struct spear_modemux cam3_modemux[] = { 963 static struct spear_modemux cam3_modemux[] = {
964 { 964 {
965 .muxregs = cam3_muxreg, 965 .muxregs = cam3_muxreg,
966 .nmuxregs = ARRAY_SIZE(cam3_muxreg), 966 .nmuxregs = ARRAY_SIZE(cam3_muxreg),
967 }, 967 },
968 }; 968 };
969 969
970 static struct spear_pingroup cam3_pingroup = { 970 static struct spear_pingroup cam3_pingroup = {
971 .name = "cam3_grp", 971 .name = "cam3_grp",
972 .pins = cam3_pins, 972 .pins = cam3_pins,
973 .npins = ARRAY_SIZE(cam3_pins), 973 .npins = ARRAY_SIZE(cam3_pins),
974 .modemuxs = cam3_modemux, 974 .modemuxs = cam3_modemux,
975 .nmodemuxs = ARRAY_SIZE(cam3_modemux), 975 .nmodemuxs = ARRAY_SIZE(cam3_modemux),
976 }; 976 };
977 977
978 static const char *const cam3_grps[] = { "cam3_grp" }; 978 static const char *const cam3_grps[] = { "cam3_grp" };
979 static struct spear_function cam3_function = { 979 static struct spear_function cam3_function = {
980 .name = "cam3", 980 .name = "cam3",
981 .groups = cam3_grps, 981 .groups = cam3_grps,
982 .ngroups = ARRAY_SIZE(cam3_grps), 982 .ngroups = ARRAY_SIZE(cam3_grps),
983 }; 983 };
984 984
985 /* pad multiplexing for smi device */ 985 /* pad multiplexing for smi device */
986 static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 }; 986 static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 };
987 static struct spear_muxreg smi_muxreg[] = { 987 static struct spear_muxreg smi_muxreg[] = {
988 { 988 {
989 .reg = PAD_FUNCTION_EN_3, 989 .reg = PAD_FUNCTION_EN_3,
990 .mask = SMI_REG2_MASK, 990 .mask = SMI_REG2_MASK,
991 .val = SMI_REG2_MASK, 991 .val = SMI_REG2_MASK,
992 }, 992 },
993 }; 993 };
994 994
995 static struct spear_modemux smi_modemux[] = { 995 static struct spear_modemux smi_modemux[] = {
996 { 996 {
997 .muxregs = smi_muxreg, 997 .muxregs = smi_muxreg,
998 .nmuxregs = ARRAY_SIZE(smi_muxreg), 998 .nmuxregs = ARRAY_SIZE(smi_muxreg),
999 }, 999 },
1000 }; 1000 };
1001 1001
1002 static struct spear_pingroup smi_pingroup = { 1002 static struct spear_pingroup smi_pingroup = {
1003 .name = "smi_grp", 1003 .name = "smi_grp",
1004 .pins = smi_pins, 1004 .pins = smi_pins,
1005 .npins = ARRAY_SIZE(smi_pins), 1005 .npins = ARRAY_SIZE(smi_pins),
1006 .modemuxs = smi_modemux, 1006 .modemuxs = smi_modemux,
1007 .nmodemuxs = ARRAY_SIZE(smi_modemux), 1007 .nmodemuxs = ARRAY_SIZE(smi_modemux),
1008 }; 1008 };
1009 1009
1010 static const char *const smi_grps[] = { "smi_grp" }; 1010 static const char *const smi_grps[] = { "smi_grp" };
1011 static struct spear_function smi_function = { 1011 static struct spear_function smi_function = {
1012 .name = "smi", 1012 .name = "smi",
1013 .groups = smi_grps, 1013 .groups = smi_grps,
1014 .ngroups = ARRAY_SIZE(smi_grps), 1014 .ngroups = ARRAY_SIZE(smi_grps),
1015 }; 1015 };
1016 1016
1017 /* pad multiplexing for ssp0 device */ 1017 /* pad multiplexing for ssp0 device */
1018 static const unsigned ssp0_pins[] = { 80, 81, 82, 83 }; 1018 static const unsigned ssp0_pins[] = { 80, 81, 82, 83 };
1019 static struct spear_muxreg ssp0_muxreg[] = { 1019 static struct spear_muxreg ssp0_muxreg[] = {
1020 { 1020 {
1021 .reg = PAD_FUNCTION_EN_3, 1021 .reg = PAD_FUNCTION_EN_3,
1022 .mask = SSP0_REG2_MASK, 1022 .mask = SSP0_REG2_MASK,
1023 .val = SSP0_REG2_MASK, 1023 .val = SSP0_REG2_MASK,
1024 }, 1024 },
1025 }; 1025 };
1026 1026
1027 static struct spear_modemux ssp0_modemux[] = { 1027 static struct spear_modemux ssp0_modemux[] = {
1028 { 1028 {
1029 .muxregs = ssp0_muxreg, 1029 .muxregs = ssp0_muxreg,
1030 .nmuxregs = ARRAY_SIZE(ssp0_muxreg), 1030 .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
1031 }, 1031 },
1032 }; 1032 };
1033 1033
1034 static struct spear_pingroup ssp0_pingroup = { 1034 static struct spear_pingroup ssp0_pingroup = {
1035 .name = "ssp0_grp", 1035 .name = "ssp0_grp",
1036 .pins = ssp0_pins, 1036 .pins = ssp0_pins,
1037 .npins = ARRAY_SIZE(ssp0_pins), 1037 .npins = ARRAY_SIZE(ssp0_pins),
1038 .modemuxs = ssp0_modemux, 1038 .modemuxs = ssp0_modemux,
1039 .nmodemuxs = ARRAY_SIZE(ssp0_modemux), 1039 .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
1040 }; 1040 };
1041 1041
1042 /* pad multiplexing for ssp0_cs1 device */ 1042 /* pad multiplexing for ssp0_cs1 device */
1043 static const unsigned ssp0_cs1_pins[] = { 24 }; 1043 static const unsigned ssp0_cs1_pins[] = { 24 };
1044 static struct spear_muxreg ssp0_cs1_muxreg[] = { 1044 static struct spear_muxreg ssp0_cs1_muxreg[] = {
1045 { 1045 {
1046 .reg = PAD_SHARED_IP_EN_1, 1046 .reg = PAD_SHARED_IP_EN_1,
1047 .mask = SSP0_CS1_MASK, 1047 .mask = SSP0_CS1_MASK,
1048 .val = SSP0_CS1_MASK, 1048 .val = SSP0_CS1_MASK,
1049 }, { 1049 }, {
1050 .reg = PAD_FUNCTION_EN_1, 1050 .reg = PAD_FUNCTION_EN_1,
1051 .mask = PWM0_AND_SSP0_CS1_REG0_MASK, 1051 .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
1052 .val = PWM0_AND_SSP0_CS1_REG0_MASK, 1052 .val = PWM0_AND_SSP0_CS1_REG0_MASK,
1053 }, 1053 },
1054 }; 1054 };
1055 1055
1056 static struct spear_modemux ssp0_cs1_modemux[] = { 1056 static struct spear_modemux ssp0_cs1_modemux[] = {
1057 { 1057 {
1058 .muxregs = ssp0_cs1_muxreg, 1058 .muxregs = ssp0_cs1_muxreg,
1059 .nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg), 1059 .nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg),
1060 }, 1060 },
1061 }; 1061 };
1062 1062
1063 static struct spear_pingroup ssp0_cs1_pingroup = { 1063 static struct spear_pingroup ssp0_cs1_pingroup = {
1064 .name = "ssp0_cs1_grp", 1064 .name = "ssp0_cs1_grp",
1065 .pins = ssp0_cs1_pins, 1065 .pins = ssp0_cs1_pins,
1066 .npins = ARRAY_SIZE(ssp0_cs1_pins), 1066 .npins = ARRAY_SIZE(ssp0_cs1_pins),
1067 .modemuxs = ssp0_cs1_modemux, 1067 .modemuxs = ssp0_cs1_modemux,
1068 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux), 1068 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux),
1069 }; 1069 };
1070 1070
1071 /* pad multiplexing for ssp0_cs2 device */ 1071 /* pad multiplexing for ssp0_cs2 device */
1072 static const unsigned ssp0_cs2_pins[] = { 85 }; 1072 static const unsigned ssp0_cs2_pins[] = { 85 };
1073 static struct spear_muxreg ssp0_cs2_muxreg[] = { 1073 static struct spear_muxreg ssp0_cs2_muxreg[] = {
1074 { 1074 {
1075 .reg = PAD_SHARED_IP_EN_1, 1075 .reg = PAD_SHARED_IP_EN_1,
1076 .mask = SSP0_CS2_MASK, 1076 .mask = SSP0_CS2_MASK,
1077 .val = SSP0_CS2_MASK, 1077 .val = SSP0_CS2_MASK,
1078 }, { 1078 }, {
1079 .reg = PAD_FUNCTION_EN_3, 1079 .reg = PAD_FUNCTION_EN_3,
1080 .mask = TS_AND_SSP0_CS2_REG2_MASK, 1080 .mask = TS_AND_SSP0_CS2_REG2_MASK,
1081 .val = TS_AND_SSP0_CS2_REG2_MASK, 1081 .val = TS_AND_SSP0_CS2_REG2_MASK,
1082 }, 1082 },
1083 }; 1083 };
1084 1084
1085 static struct spear_modemux ssp0_cs2_modemux[] = { 1085 static struct spear_modemux ssp0_cs2_modemux[] = {
1086 { 1086 {
1087 .muxregs = ssp0_cs2_muxreg, 1087 .muxregs = ssp0_cs2_muxreg,
1088 .nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg), 1088 .nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg),
1089 }, 1089 },
1090 }; 1090 };
1091 1091
1092 static struct spear_pingroup ssp0_cs2_pingroup = { 1092 static struct spear_pingroup ssp0_cs2_pingroup = {
1093 .name = "ssp0_cs2_grp", 1093 .name = "ssp0_cs2_grp",
1094 .pins = ssp0_cs2_pins, 1094 .pins = ssp0_cs2_pins,
1095 .npins = ARRAY_SIZE(ssp0_cs2_pins), 1095 .npins = ARRAY_SIZE(ssp0_cs2_pins),
1096 .modemuxs = ssp0_cs2_modemux, 1096 .modemuxs = ssp0_cs2_modemux,
1097 .nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux), 1097 .nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux),
1098 }; 1098 };
1099 1099
1100 /* pad multiplexing for ssp0_cs3 device */ 1100 /* pad multiplexing for ssp0_cs3 device */
1101 static const unsigned ssp0_cs3_pins[] = { 132 }; 1101 static const unsigned ssp0_cs3_pins[] = { 132 };
1102 static struct spear_muxreg ssp0_cs3_muxreg[] = { 1102 static struct spear_muxreg ssp0_cs3_muxreg[] = {
1103 { 1103 {
1104 .reg = PAD_FUNCTION_EN_5, 1104 .reg = PAD_FUNCTION_EN_5,
1105 .mask = SSP0_CS3_REG4_MASK, 1105 .mask = SSP0_CS3_REG4_MASK,
1106 .val = SSP0_CS3_REG4_MASK, 1106 .val = SSP0_CS3_REG4_MASK,
1107 }, 1107 },
1108 }; 1108 };
1109 1109
1110 static struct spear_modemux ssp0_cs3_modemux[] = { 1110 static struct spear_modemux ssp0_cs3_modemux[] = {
1111 { 1111 {
1112 .muxregs = ssp0_cs3_muxreg, 1112 .muxregs = ssp0_cs3_muxreg,
1113 .nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg), 1113 .nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg),
1114 }, 1114 },
1115 }; 1115 };
1116 1116
1117 static struct spear_pingroup ssp0_cs3_pingroup = { 1117 static struct spear_pingroup ssp0_cs3_pingroup = {
1118 .name = "ssp0_cs3_grp", 1118 .name = "ssp0_cs3_grp",
1119 .pins = ssp0_cs3_pins, 1119 .pins = ssp0_cs3_pins,
1120 .npins = ARRAY_SIZE(ssp0_cs3_pins), 1120 .npins = ARRAY_SIZE(ssp0_cs3_pins),
1121 .modemuxs = ssp0_cs3_modemux, 1121 .modemuxs = ssp0_cs3_modemux,
1122 .nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux), 1122 .nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux),
1123 }; 1123 };
1124 1124
1125 static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp", 1125 static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp",
1126 "ssp0_cs2_grp", "ssp0_cs3_grp" }; 1126 "ssp0_cs2_grp", "ssp0_cs3_grp" };
1127 static struct spear_function ssp0_function = { 1127 static struct spear_function ssp0_function = {
1128 .name = "ssp0", 1128 .name = "ssp0",
1129 .groups = ssp0_grps, 1129 .groups = ssp0_grps,
1130 .ngroups = ARRAY_SIZE(ssp0_grps), 1130 .ngroups = ARRAY_SIZE(ssp0_grps),
1131 }; 1131 };
1132 1132
1133 /* pad multiplexing for uart0 device */ 1133 /* pad multiplexing for uart0 device */
1134 static const unsigned uart0_pins[] = { 86, 87 }; 1134 static const unsigned uart0_pins[] = { 86, 87 };
1135 static struct spear_muxreg uart0_muxreg[] = { 1135 static struct spear_muxreg uart0_muxreg[] = {
1136 { 1136 {
1137 .reg = PAD_FUNCTION_EN_3, 1137 .reg = PAD_FUNCTION_EN_3,
1138 .mask = UART0_REG2_MASK, 1138 .mask = UART0_REG2_MASK,
1139 .val = UART0_REG2_MASK, 1139 .val = UART0_REG2_MASK,
1140 }, 1140 },
1141 }; 1141 };
1142 1142
1143 static struct spear_modemux uart0_modemux[] = { 1143 static struct spear_modemux uart0_modemux[] = {
1144 { 1144 {
1145 .muxregs = uart0_muxreg, 1145 .muxregs = uart0_muxreg,
1146 .nmuxregs = ARRAY_SIZE(uart0_muxreg), 1146 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
1147 }, 1147 },
1148 }; 1148 };
1149 1149
1150 static struct spear_pingroup uart0_pingroup = { 1150 static struct spear_pingroup uart0_pingroup = {
1151 .name = "uart0_grp", 1151 .name = "uart0_grp",
1152 .pins = uart0_pins, 1152 .pins = uart0_pins,
1153 .npins = ARRAY_SIZE(uart0_pins), 1153 .npins = ARRAY_SIZE(uart0_pins),
1154 .modemuxs = uart0_modemux, 1154 .modemuxs = uart0_modemux,
1155 .nmodemuxs = ARRAY_SIZE(uart0_modemux), 1155 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
1156 }; 1156 };
1157 1157
1158 /* pad multiplexing for uart0_enh device */ 1158 /* pad multiplexing for uart0_enh device */
1159 static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 }; 1159 static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 };
1160 static struct spear_muxreg uart0_enh_muxreg[] = { 1160 static struct spear_muxreg uart0_enh_muxreg[] = {
1161 { 1161 {
1162 .reg = PAD_SHARED_IP_EN_1, 1162 .reg = PAD_SHARED_IP_EN_1,
1163 .mask = GPT_MASK, 1163 .mask = GPT_MASK,
1164 .val = 0, 1164 .val = 0,
1165 }, { 1165 }, {
1166 .reg = PAD_FUNCTION_EN_1, 1166 .reg = PAD_FUNCTION_EN_1,
1167 .mask = UART0_ENH_AND_GPT_REG0_MASK, 1167 .mask = UART0_ENH_AND_GPT_REG0_MASK,
1168 .val = UART0_ENH_AND_GPT_REG0_MASK, 1168 .val = UART0_ENH_AND_GPT_REG0_MASK,
1169 }, 1169 },
1170 }; 1170 };
1171 1171
1172 static struct spear_modemux uart0_enh_modemux[] = { 1172 static struct spear_modemux uart0_enh_modemux[] = {
1173 { 1173 {
1174 .muxregs = uart0_enh_muxreg, 1174 .muxregs = uart0_enh_muxreg,
1175 .nmuxregs = ARRAY_SIZE(uart0_enh_muxreg), 1175 .nmuxregs = ARRAY_SIZE(uart0_enh_muxreg),
1176 }, 1176 },
1177 }; 1177 };
1178 1178
1179 static struct spear_pingroup uart0_enh_pingroup = { 1179 static struct spear_pingroup uart0_enh_pingroup = {
1180 .name = "uart0_enh_grp", 1180 .name = "uart0_enh_grp",
1181 .pins = uart0_enh_pins, 1181 .pins = uart0_enh_pins,
1182 .npins = ARRAY_SIZE(uart0_enh_pins), 1182 .npins = ARRAY_SIZE(uart0_enh_pins),
1183 .modemuxs = uart0_enh_modemux, 1183 .modemuxs = uart0_enh_modemux,
1184 .nmodemuxs = ARRAY_SIZE(uart0_enh_modemux), 1184 .nmodemuxs = ARRAY_SIZE(uart0_enh_modemux),
1185 }; 1185 };
1186 1186
1187 static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" }; 1187 static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" };
1188 static struct spear_function uart0_function = { 1188 static struct spear_function uart0_function = {
1189 .name = "uart0", 1189 .name = "uart0",
1190 .groups = uart0_grps, 1190 .groups = uart0_grps,
1191 .ngroups = ARRAY_SIZE(uart0_grps), 1191 .ngroups = ARRAY_SIZE(uart0_grps),
1192 }; 1192 };
1193 1193
1194 /* pad multiplexing for uart1 device */ 1194 /* pad multiplexing for uart1 device */
1195 static const unsigned uart1_pins[] = { 88, 89 }; 1195 static const unsigned uart1_pins[] = { 88, 89 };
1196 static struct spear_muxreg uart1_muxreg[] = { 1196 static struct spear_muxreg uart1_muxreg[] = {
1197 { 1197 {
1198 .reg = PAD_FUNCTION_EN_3, 1198 .reg = PAD_FUNCTION_EN_3,
1199 .mask = UART1_REG2_MASK, 1199 .mask = UART1_REG2_MASK,
1200 .val = UART1_REG2_MASK, 1200 .val = UART1_REG2_MASK,
1201 }, 1201 },
1202 }; 1202 };
1203 1203
1204 static struct spear_modemux uart1_modemux[] = { 1204 static struct spear_modemux uart1_modemux[] = {
1205 { 1205 {
1206 .muxregs = uart1_muxreg, 1206 .muxregs = uart1_muxreg,
1207 .nmuxregs = ARRAY_SIZE(uart1_muxreg), 1207 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
1208 }, 1208 },
1209 }; 1209 };
1210 1210
1211 static struct spear_pingroup uart1_pingroup = { 1211 static struct spear_pingroup uart1_pingroup = {
1212 .name = "uart1_grp", 1212 .name = "uart1_grp",
1213 .pins = uart1_pins, 1213 .pins = uart1_pins,
1214 .npins = ARRAY_SIZE(uart1_pins), 1214 .npins = ARRAY_SIZE(uart1_pins),
1215 .modemuxs = uart1_modemux, 1215 .modemuxs = uart1_modemux,
1216 .nmodemuxs = ARRAY_SIZE(uart1_modemux), 1216 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
1217 }; 1217 };
1218 1218
1219 static const char *const uart1_grps[] = { "uart1_grp" }; 1219 static const char *const uart1_grps[] = { "uart1_grp" };
1220 static struct spear_function uart1_function = { 1220 static struct spear_function uart1_function = {
1221 .name = "uart1", 1221 .name = "uart1",
1222 .groups = uart1_grps, 1222 .groups = uart1_grps,
1223 .ngroups = ARRAY_SIZE(uart1_grps), 1223 .ngroups = ARRAY_SIZE(uart1_grps),
1224 }; 1224 };
1225 1225
1226 /* pad multiplexing for i2s_in device */ 1226 /* pad multiplexing for i2s_in device */
1227 static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 }; 1227 static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 };
1228 static struct spear_muxreg i2s_in_muxreg[] = { 1228 static struct spear_muxreg i2s_in_muxreg[] = {
1229 { 1229 {
1230 .reg = PAD_FUNCTION_EN_3, 1230 .reg = PAD_FUNCTION_EN_3,
1231 .mask = I2S_IN_REG2_MASK, 1231 .mask = I2S_IN_REG2_MASK,
1232 .val = I2S_IN_REG2_MASK, 1232 .val = I2S_IN_REG2_MASK,
1233 }, { 1233 }, {
1234 .reg = PAD_FUNCTION_EN_4, 1234 .reg = PAD_FUNCTION_EN_4,
1235 .mask = I2S_IN_REG3_MASK, 1235 .mask = I2S_IN_REG3_MASK,
1236 .val = I2S_IN_REG3_MASK, 1236 .val = I2S_IN_REG3_MASK,
1237 }, 1237 },
1238 }; 1238 };
1239 1239
1240 static struct spear_modemux i2s_in_modemux[] = { 1240 static struct spear_modemux i2s_in_modemux[] = {
1241 { 1241 {
1242 .muxregs = i2s_in_muxreg, 1242 .muxregs = i2s_in_muxreg,
1243 .nmuxregs = ARRAY_SIZE(i2s_in_muxreg), 1243 .nmuxregs = ARRAY_SIZE(i2s_in_muxreg),
1244 }, 1244 },
1245 }; 1245 };
1246 1246
1247 static struct spear_pingroup i2s_in_pingroup = { 1247 static struct spear_pingroup i2s_in_pingroup = {
1248 .name = "i2s_in_grp", 1248 .name = "i2s_in_grp",
1249 .pins = i2s_in_pins, 1249 .pins = i2s_in_pins,
1250 .npins = ARRAY_SIZE(i2s_in_pins), 1250 .npins = ARRAY_SIZE(i2s_in_pins),
1251 .modemuxs = i2s_in_modemux, 1251 .modemuxs = i2s_in_modemux,
1252 .nmodemuxs = ARRAY_SIZE(i2s_in_modemux), 1252 .nmodemuxs = ARRAY_SIZE(i2s_in_modemux),
1253 }; 1253 };
1254 1254
1255 /* pad multiplexing for i2s_out device */ 1255 /* pad multiplexing for i2s_out device */
1256 static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 }; 1256 static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 };
1257 static struct spear_muxreg i2s_out_muxreg[] = { 1257 static struct spear_muxreg i2s_out_muxreg[] = {
1258 { 1258 {
1259 .reg = PAD_FUNCTION_EN_4, 1259 .reg = PAD_FUNCTION_EN_4,
1260 .mask = I2S_OUT_REG3_MASK, 1260 .mask = I2S_OUT_REG3_MASK,
1261 .val = I2S_OUT_REG3_MASK, 1261 .val = I2S_OUT_REG3_MASK,
1262 }, 1262 },
1263 }; 1263 };
1264 1264
1265 static struct spear_modemux i2s_out_modemux[] = { 1265 static struct spear_modemux i2s_out_modemux[] = {
1266 { 1266 {
1267 .muxregs = i2s_out_muxreg, 1267 .muxregs = i2s_out_muxreg,
1268 .nmuxregs = ARRAY_SIZE(i2s_out_muxreg), 1268 .nmuxregs = ARRAY_SIZE(i2s_out_muxreg),
1269 }, 1269 },
1270 }; 1270 };
1271 1271
1272 static struct spear_pingroup i2s_out_pingroup = { 1272 static struct spear_pingroup i2s_out_pingroup = {
1273 .name = "i2s_out_grp", 1273 .name = "i2s_out_grp",
1274 .pins = i2s_out_pins, 1274 .pins = i2s_out_pins,
1275 .npins = ARRAY_SIZE(i2s_out_pins), 1275 .npins = ARRAY_SIZE(i2s_out_pins),
1276 .modemuxs = i2s_out_modemux, 1276 .modemuxs = i2s_out_modemux,
1277 .nmodemuxs = ARRAY_SIZE(i2s_out_modemux), 1277 .nmodemuxs = ARRAY_SIZE(i2s_out_modemux),
1278 }; 1278 };
1279 1279
1280 static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" }; 1280 static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" };
1281 static struct spear_function i2s_function = { 1281 static struct spear_function i2s_function = {
1282 .name = "i2s", 1282 .name = "i2s",
1283 .groups = i2s_grps, 1283 .groups = i2s_grps,
1284 .ngroups = ARRAY_SIZE(i2s_grps), 1284 .ngroups = ARRAY_SIZE(i2s_grps),
1285 }; 1285 };
1286 1286
1287 /* pad multiplexing for gmac device */ 1287 /* pad multiplexing for gmac device */
1288 static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111, 1288 static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111,
1289 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 1289 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125,
1290 126, 127, 128, 129, 130, 131 }; 1290 126, 127, 128, 129, 130, 131 };
1291 #define GMAC_MUXREG \ 1291 #define GMAC_MUXREG \
1292 { \ 1292 { \
1293 .reg = PAD_FUNCTION_EN_4, \ 1293 .reg = PAD_FUNCTION_EN_4, \
1294 .mask = GMAC_REG3_MASK, \ 1294 .mask = GMAC_REG3_MASK, \
1295 .val = GMAC_REG3_MASK, \ 1295 .val = GMAC_REG3_MASK, \
1296 }, { \ 1296 }, { \
1297 .reg = PAD_FUNCTION_EN_5, \ 1297 .reg = PAD_FUNCTION_EN_5, \
1298 .mask = GMAC_REG4_MASK, \ 1298 .mask = GMAC_REG4_MASK, \
1299 .val = GMAC_REG4_MASK, \ 1299 .val = GMAC_REG4_MASK, \
1300 } 1300 }
1301 1301
1302 /* pad multiplexing for gmii device */ 1302 /* pad multiplexing for gmii device */
1303 static struct spear_muxreg gmii_muxreg[] = { 1303 static struct spear_muxreg gmii_muxreg[] = {
1304 GMAC_MUXREG, 1304 GMAC_MUXREG,
1305 { 1305 {
1306 .reg = GMAC_CLK_CFG, 1306 .reg = GMAC_CLK_CFG,
1307 .mask = GMAC_PHY_IF_SEL_MASK, 1307 .mask = GMAC_PHY_IF_SEL_MASK,
1308 .val = GMAC_PHY_IF_GMII_VAL, 1308 .val = GMAC_PHY_IF_GMII_VAL,
1309 }, 1309 },
1310 }; 1310 };
1311 1311
1312 static struct spear_modemux gmii_modemux[] = { 1312 static struct spear_modemux gmii_modemux[] = {
1313 { 1313 {
1314 .muxregs = gmii_muxreg, 1314 .muxregs = gmii_muxreg,
1315 .nmuxregs = ARRAY_SIZE(gmii_muxreg), 1315 .nmuxregs = ARRAY_SIZE(gmii_muxreg),
1316 }, 1316 },
1317 }; 1317 };
1318 1318
1319 static struct spear_pingroup gmii_pingroup = { 1319 static struct spear_pingroup gmii_pingroup = {
1320 .name = "gmii_grp", 1320 .name = "gmii_grp",
1321 .pins = gmac_pins, 1321 .pins = gmac_pins,
1322 .npins = ARRAY_SIZE(gmac_pins), 1322 .npins = ARRAY_SIZE(gmac_pins),
1323 .modemuxs = gmii_modemux, 1323 .modemuxs = gmii_modemux,
1324 .nmodemuxs = ARRAY_SIZE(gmii_modemux), 1324 .nmodemuxs = ARRAY_SIZE(gmii_modemux),
1325 }; 1325 };
1326 1326
1327 /* pad multiplexing for rgmii device */ 1327 /* pad multiplexing for rgmii device */
1328 static struct spear_muxreg rgmii_muxreg[] = { 1328 static struct spear_muxreg rgmii_muxreg[] = {
1329 GMAC_MUXREG, 1329 GMAC_MUXREG,
1330 { 1330 {
1331 .reg = GMAC_CLK_CFG, 1331 .reg = GMAC_CLK_CFG,
1332 .mask = GMAC_PHY_IF_SEL_MASK, 1332 .mask = GMAC_PHY_IF_SEL_MASK,
1333 .val = GMAC_PHY_IF_RGMII_VAL, 1333 .val = GMAC_PHY_IF_RGMII_VAL,
1334 }, 1334 },
1335 }; 1335 };
1336 1336
1337 static struct spear_modemux rgmii_modemux[] = { 1337 static struct spear_modemux rgmii_modemux[] = {
1338 { 1338 {
1339 .muxregs = rgmii_muxreg, 1339 .muxregs = rgmii_muxreg,
1340 .nmuxregs = ARRAY_SIZE(rgmii_muxreg), 1340 .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
1341 }, 1341 },
1342 }; 1342 };
1343 1343
1344 static struct spear_pingroup rgmii_pingroup = { 1344 static struct spear_pingroup rgmii_pingroup = {
1345 .name = "rgmii_grp", 1345 .name = "rgmii_grp",
1346 .pins = gmac_pins, 1346 .pins = gmac_pins,
1347 .npins = ARRAY_SIZE(gmac_pins), 1347 .npins = ARRAY_SIZE(gmac_pins),
1348 .modemuxs = rgmii_modemux, 1348 .modemuxs = rgmii_modemux,
1349 .nmodemuxs = ARRAY_SIZE(rgmii_modemux), 1349 .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
1350 }; 1350 };
1351 1351
1352 /* pad multiplexing for rmii device */ 1352 /* pad multiplexing for rmii device */
1353 static struct spear_muxreg rmii_muxreg[] = { 1353 static struct spear_muxreg rmii_muxreg[] = {
1354 GMAC_MUXREG, 1354 GMAC_MUXREG,
1355 { 1355 {
1356 .reg = GMAC_CLK_CFG, 1356 .reg = GMAC_CLK_CFG,
1357 .mask = GMAC_PHY_IF_SEL_MASK, 1357 .mask = GMAC_PHY_IF_SEL_MASK,
1358 .val = GMAC_PHY_IF_RMII_VAL, 1358 .val = GMAC_PHY_IF_RMII_VAL,
1359 }, 1359 },
1360 }; 1360 };
1361 1361
1362 static struct spear_modemux rmii_modemux[] = { 1362 static struct spear_modemux rmii_modemux[] = {
1363 { 1363 {
1364 .muxregs = rmii_muxreg, 1364 .muxregs = rmii_muxreg,
1365 .nmuxregs = ARRAY_SIZE(rmii_muxreg), 1365 .nmuxregs = ARRAY_SIZE(rmii_muxreg),
1366 }, 1366 },
1367 }; 1367 };
1368 1368
1369 static struct spear_pingroup rmii_pingroup = { 1369 static struct spear_pingroup rmii_pingroup = {
1370 .name = "rmii_grp", 1370 .name = "rmii_grp",
1371 .pins = gmac_pins, 1371 .pins = gmac_pins,
1372 .npins = ARRAY_SIZE(gmac_pins), 1372 .npins = ARRAY_SIZE(gmac_pins),
1373 .modemuxs = rmii_modemux, 1373 .modemuxs = rmii_modemux,
1374 .nmodemuxs = ARRAY_SIZE(rmii_modemux), 1374 .nmodemuxs = ARRAY_SIZE(rmii_modemux),
1375 }; 1375 };
1376 1376
1377 /* pad multiplexing for sgmii device */ 1377 /* pad multiplexing for sgmii device */
1378 static struct spear_muxreg sgmii_muxreg[] = { 1378 static struct spear_muxreg sgmii_muxreg[] = {
1379 GMAC_MUXREG, 1379 GMAC_MUXREG,
1380 { 1380 {
1381 .reg = GMAC_CLK_CFG, 1381 .reg = GMAC_CLK_CFG,
1382 .mask = GMAC_PHY_IF_SEL_MASK, 1382 .mask = GMAC_PHY_IF_SEL_MASK,
1383 .val = GMAC_PHY_IF_SGMII_VAL, 1383 .val = GMAC_PHY_IF_SGMII_VAL,
1384 }, 1384 },
1385 }; 1385 };
1386 1386
1387 static struct spear_modemux sgmii_modemux[] = { 1387 static struct spear_modemux sgmii_modemux[] = {
1388 { 1388 {
1389 .muxregs = sgmii_muxreg, 1389 .muxregs = sgmii_muxreg,
1390 .nmuxregs = ARRAY_SIZE(sgmii_muxreg), 1390 .nmuxregs = ARRAY_SIZE(sgmii_muxreg),
1391 }, 1391 },
1392 }; 1392 };
1393 1393
1394 static struct spear_pingroup sgmii_pingroup = { 1394 static struct spear_pingroup sgmii_pingroup = {
1395 .name = "sgmii_grp", 1395 .name = "sgmii_grp",
1396 .pins = gmac_pins, 1396 .pins = gmac_pins,
1397 .npins = ARRAY_SIZE(gmac_pins), 1397 .npins = ARRAY_SIZE(gmac_pins),
1398 .modemuxs = sgmii_modemux, 1398 .modemuxs = sgmii_modemux,
1399 .nmodemuxs = ARRAY_SIZE(sgmii_modemux), 1399 .nmodemuxs = ARRAY_SIZE(sgmii_modemux),
1400 }; 1400 };
1401 1401
1402 static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp", 1402 static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp",
1403 "sgmii_grp" }; 1403 "sgmii_grp" };
1404 static struct spear_function gmac_function = { 1404 static struct spear_function gmac_function = {
1405 .name = "gmac", 1405 .name = "gmac",
1406 .groups = gmac_grps, 1406 .groups = gmac_grps,
1407 .ngroups = ARRAY_SIZE(gmac_grps), 1407 .ngroups = ARRAY_SIZE(gmac_grps),
1408 }; 1408 };
1409 1409
1410 /* pad multiplexing for i2c0 device */ 1410 /* pad multiplexing for i2c0 device */
1411 static const unsigned i2c0_pins[] = { 133, 134 }; 1411 static const unsigned i2c0_pins[] = { 133, 134 };
1412 static struct spear_muxreg i2c0_muxreg[] = { 1412 static struct spear_muxreg i2c0_muxreg[] = {
1413 { 1413 {
1414 .reg = PAD_FUNCTION_EN_5, 1414 .reg = PAD_FUNCTION_EN_5,
1415 .mask = I2C0_REG4_MASK, 1415 .mask = I2C0_REG4_MASK,
1416 .val = I2C0_REG4_MASK, 1416 .val = I2C0_REG4_MASK,
1417 }, 1417 },
1418 }; 1418 };
1419 1419
1420 static struct spear_modemux i2c0_modemux[] = { 1420 static struct spear_modemux i2c0_modemux[] = {
1421 { 1421 {
1422 .muxregs = i2c0_muxreg, 1422 .muxregs = i2c0_muxreg,
1423 .nmuxregs = ARRAY_SIZE(i2c0_muxreg), 1423 .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
1424 }, 1424 },
1425 }; 1425 };
1426 1426
1427 static struct spear_pingroup i2c0_pingroup = { 1427 static struct spear_pingroup i2c0_pingroup = {
1428 .name = "i2c0_grp", 1428 .name = "i2c0_grp",
1429 .pins = i2c0_pins, 1429 .pins = i2c0_pins,
1430 .npins = ARRAY_SIZE(i2c0_pins), 1430 .npins = ARRAY_SIZE(i2c0_pins),
1431 .modemuxs = i2c0_modemux, 1431 .modemuxs = i2c0_modemux,
1432 .nmodemuxs = ARRAY_SIZE(i2c0_modemux), 1432 .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
1433 }; 1433 };
1434 1434
1435 static const char *const i2c0_grps[] = { "i2c0_grp" }; 1435 static const char *const i2c0_grps[] = { "i2c0_grp" };
1436 static struct spear_function i2c0_function = { 1436 static struct spear_function i2c0_function = {
1437 .name = "i2c0", 1437 .name = "i2c0",
1438 .groups = i2c0_grps, 1438 .groups = i2c0_grps,
1439 .ngroups = ARRAY_SIZE(i2c0_grps), 1439 .ngroups = ARRAY_SIZE(i2c0_grps),
1440 }; 1440 };
1441 1441
1442 /* pad multiplexing for i2c1 device */ 1442 /* pad multiplexing for i2c1 device */
1443 static const unsigned i2c1_pins[] = { 18, 23 }; 1443 static const unsigned i2c1_pins[] = { 18, 23 };
1444 static struct spear_muxreg i2c1_muxreg[] = { 1444 static struct spear_muxreg i2c1_muxreg[] = {
1445 { 1445 {
1446 .reg = PAD_FUNCTION_EN_1, 1446 .reg = PAD_FUNCTION_EN_1,
1447 .mask = I2C1_REG0_MASK, 1447 .mask = I2C1_REG0_MASK,
1448 .val = I2C1_REG0_MASK, 1448 .val = I2C1_REG0_MASK,
1449 }, 1449 },
1450 }; 1450 };
1451 1451
1452 static struct spear_modemux i2c1_modemux[] = { 1452 static struct spear_modemux i2c1_modemux[] = {
1453 { 1453 {
1454 .muxregs = i2c1_muxreg, 1454 .muxregs = i2c1_muxreg,
1455 .nmuxregs = ARRAY_SIZE(i2c1_muxreg), 1455 .nmuxregs = ARRAY_SIZE(i2c1_muxreg),
1456 }, 1456 },
1457 }; 1457 };
1458 1458
1459 static struct spear_pingroup i2c1_pingroup = { 1459 static struct spear_pingroup i2c1_pingroup = {
1460 .name = "i2c1_grp", 1460 .name = "i2c1_grp",
1461 .pins = i2c1_pins, 1461 .pins = i2c1_pins,
1462 .npins = ARRAY_SIZE(i2c1_pins), 1462 .npins = ARRAY_SIZE(i2c1_pins),
1463 .modemuxs = i2c1_modemux, 1463 .modemuxs = i2c1_modemux,
1464 .nmodemuxs = ARRAY_SIZE(i2c1_modemux), 1464 .nmodemuxs = ARRAY_SIZE(i2c1_modemux),
1465 }; 1465 };
1466 1466
1467 static const char *const i2c1_grps[] = { "i2c1_grp" }; 1467 static const char *const i2c1_grps[] = { "i2c1_grp" };
1468 static struct spear_function i2c1_function = { 1468 static struct spear_function i2c1_function = {
1469 .name = "i2c1", 1469 .name = "i2c1",
1470 .groups = i2c1_grps, 1470 .groups = i2c1_grps,
1471 .ngroups = ARRAY_SIZE(i2c1_grps), 1471 .ngroups = ARRAY_SIZE(i2c1_grps),
1472 }; 1472 };
1473 1473
1474 /* pad multiplexing for cec0 device */ 1474 /* pad multiplexing for cec0 device */
1475 static const unsigned cec0_pins[] = { 135 }; 1475 static const unsigned cec0_pins[] = { 135 };
1476 static struct spear_muxreg cec0_muxreg[] = { 1476 static struct spear_muxreg cec0_muxreg[] = {
1477 { 1477 {
1478 .reg = PAD_FUNCTION_EN_5, 1478 .reg = PAD_FUNCTION_EN_5,
1479 .mask = CEC0_REG4_MASK, 1479 .mask = CEC0_REG4_MASK,
1480 .val = CEC0_REG4_MASK, 1480 .val = CEC0_REG4_MASK,
1481 }, 1481 },
1482 }; 1482 };
1483 1483
1484 static struct spear_modemux cec0_modemux[] = { 1484 static struct spear_modemux cec0_modemux[] = {
1485 { 1485 {
1486 .muxregs = cec0_muxreg, 1486 .muxregs = cec0_muxreg,
1487 .nmuxregs = ARRAY_SIZE(cec0_muxreg), 1487 .nmuxregs = ARRAY_SIZE(cec0_muxreg),
1488 }, 1488 },
1489 }; 1489 };
1490 1490
1491 static struct spear_pingroup cec0_pingroup = { 1491 static struct spear_pingroup cec0_pingroup = {
1492 .name = "cec0_grp", 1492 .name = "cec0_grp",
1493 .pins = cec0_pins, 1493 .pins = cec0_pins,
1494 .npins = ARRAY_SIZE(cec0_pins), 1494 .npins = ARRAY_SIZE(cec0_pins),
1495 .modemuxs = cec0_modemux, 1495 .modemuxs = cec0_modemux,
1496 .nmodemuxs = ARRAY_SIZE(cec0_modemux), 1496 .nmodemuxs = ARRAY_SIZE(cec0_modemux),
1497 }; 1497 };
1498 1498
1499 static const char *const cec0_grps[] = { "cec0_grp" }; 1499 static const char *const cec0_grps[] = { "cec0_grp" };
1500 static struct spear_function cec0_function = { 1500 static struct spear_function cec0_function = {
1501 .name = "cec0", 1501 .name = "cec0",
1502 .groups = cec0_grps, 1502 .groups = cec0_grps,
1503 .ngroups = ARRAY_SIZE(cec0_grps), 1503 .ngroups = ARRAY_SIZE(cec0_grps),
1504 }; 1504 };
1505 1505
1506 /* pad multiplexing for cec1 device */ 1506 /* pad multiplexing for cec1 device */
1507 static const unsigned cec1_pins[] = { 136 }; 1507 static const unsigned cec1_pins[] = { 136 };
1508 static struct spear_muxreg cec1_muxreg[] = { 1508 static struct spear_muxreg cec1_muxreg[] = {
1509 { 1509 {
1510 .reg = PAD_FUNCTION_EN_5, 1510 .reg = PAD_FUNCTION_EN_5,
1511 .mask = CEC1_REG4_MASK, 1511 .mask = CEC1_REG4_MASK,
1512 .val = CEC1_REG4_MASK, 1512 .val = CEC1_REG4_MASK,
1513 }, 1513 },
1514 }; 1514 };
1515 1515
1516 static struct spear_modemux cec1_modemux[] = { 1516 static struct spear_modemux cec1_modemux[] = {
1517 { 1517 {
1518 .muxregs = cec1_muxreg, 1518 .muxregs = cec1_muxreg,
1519 .nmuxregs = ARRAY_SIZE(cec1_muxreg), 1519 .nmuxregs = ARRAY_SIZE(cec1_muxreg),
1520 }, 1520 },
1521 }; 1521 };
1522 1522
1523 static struct spear_pingroup cec1_pingroup = { 1523 static struct spear_pingroup cec1_pingroup = {
1524 .name = "cec1_grp", 1524 .name = "cec1_grp",
1525 .pins = cec1_pins, 1525 .pins = cec1_pins,
1526 .npins = ARRAY_SIZE(cec1_pins), 1526 .npins = ARRAY_SIZE(cec1_pins),
1527 .modemuxs = cec1_modemux, 1527 .modemuxs = cec1_modemux,
1528 .nmodemuxs = ARRAY_SIZE(cec1_modemux), 1528 .nmodemuxs = ARRAY_SIZE(cec1_modemux),
1529 }; 1529 };
1530 1530
1531 static const char *const cec1_grps[] = { "cec1_grp" }; 1531 static const char *const cec1_grps[] = { "cec1_grp" };
1532 static struct spear_function cec1_function = { 1532 static struct spear_function cec1_function = {
1533 .name = "cec1", 1533 .name = "cec1",
1534 .groups = cec1_grps, 1534 .groups = cec1_grps,
1535 .ngroups = ARRAY_SIZE(cec1_grps), 1535 .ngroups = ARRAY_SIZE(cec1_grps),
1536 }; 1536 };
1537 1537
1538 /* pad multiplexing for mcif devices */ 1538 /* pad multiplexing for mcif devices */
1539 static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200, 1539 static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200,
1540 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 1540 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
1541 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 1541 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
1542 229, 230, 231, 232, 237 }; 1542 229, 230, 231, 232, 237 };
1543 #define MCIF_MUXREG \ 1543 #define MCIF_MUXREG \
1544 { \ 1544 { \
1545 .reg = PAD_SHARED_IP_EN_1, \ 1545 .reg = PAD_SHARED_IP_EN_1, \
1546 .mask = MCIF_MASK, \ 1546 .mask = MCIF_MASK, \
1547 .val = MCIF_MASK, \ 1547 .val = MCIF_MASK, \
1548 }, { \ 1548 }, { \
1549 .reg = PAD_FUNCTION_EN_7, \ 1549 .reg = PAD_FUNCTION_EN_7, \
1550 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \ 1550 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
1551 .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \ 1551 .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
1552 }, { \ 1552 }, { \
1553 .reg = PAD_FUNCTION_EN_8, \ 1553 .reg = PAD_FUNCTION_EN_8, \
1554 .mask = MCIF_REG7_MASK, \ 1554 .mask = MCIF_REG7_MASK, \
1555 .val = MCIF_REG7_MASK, \ 1555 .val = MCIF_REG7_MASK, \
1556 } 1556 }
1557 1557
1558 /* Pad multiplexing for sdhci device */ 1558 /* Pad multiplexing for sdhci device */
1559 static struct spear_muxreg sdhci_muxreg[] = { 1559 static struct spear_muxreg sdhci_muxreg[] = {
1560 MCIF_MUXREG, 1560 MCIF_MUXREG,
1561 { 1561 {
1562 .reg = PERIP_CFG, 1562 .reg = PERIP_CFG,
1563 .mask = MCIF_SEL_MASK, 1563 .mask = MCIF_SEL_MASK,
1564 .val = MCIF_SEL_SD, 1564 .val = MCIF_SEL_SD,
1565 }, 1565 },
1566 }; 1566 };
1567 1567
1568 static struct spear_modemux sdhci_modemux[] = { 1568 static struct spear_modemux sdhci_modemux[] = {
1569 { 1569 {
1570 .muxregs = sdhci_muxreg, 1570 .muxregs = sdhci_muxreg,
1571 .nmuxregs = ARRAY_SIZE(sdhci_muxreg), 1571 .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
1572 }, 1572 },
1573 }; 1573 };
1574 1574
1575 static struct spear_pingroup sdhci_pingroup = { 1575 static struct spear_pingroup sdhci_pingroup = {
1576 .name = "sdhci_grp", 1576 .name = "sdhci_grp",
1577 .pins = mcif_pins, 1577 .pins = mcif_pins,
1578 .npins = ARRAY_SIZE(mcif_pins), 1578 .npins = ARRAY_SIZE(mcif_pins),
1579 .modemuxs = sdhci_modemux, 1579 .modemuxs = sdhci_modemux,
1580 .nmodemuxs = ARRAY_SIZE(sdhci_modemux), 1580 .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
1581 }; 1581 };
1582 1582
1583 static const char *const sdhci_grps[] = { "sdhci_grp" }; 1583 static const char *const sdhci_grps[] = { "sdhci_grp" };
1584 static struct spear_function sdhci_function = { 1584 static struct spear_function sdhci_function = {
1585 .name = "sdhci", 1585 .name = "sdhci",
1586 .groups = sdhci_grps, 1586 .groups = sdhci_grps,
1587 .ngroups = ARRAY_SIZE(sdhci_grps), 1587 .ngroups = ARRAY_SIZE(sdhci_grps),
1588 }; 1588 };
1589 1589
1590 /* Pad multiplexing for cf device */ 1590 /* Pad multiplexing for cf device */
1591 static struct spear_muxreg cf_muxreg[] = { 1591 static struct spear_muxreg cf_muxreg[] = {
1592 MCIF_MUXREG, 1592 MCIF_MUXREG,
1593 { 1593 {
1594 .reg = PERIP_CFG, 1594 .reg = PERIP_CFG,
1595 .mask = MCIF_SEL_MASK, 1595 .mask = MCIF_SEL_MASK,
1596 .val = MCIF_SEL_CF, 1596 .val = MCIF_SEL_CF,
1597 }, 1597 },
1598 }; 1598 };
1599 1599
1600 static struct spear_modemux cf_modemux[] = { 1600 static struct spear_modemux cf_modemux[] = {
1601 { 1601 {
1602 .muxregs = cf_muxreg, 1602 .muxregs = cf_muxreg,
1603 .nmuxregs = ARRAY_SIZE(cf_muxreg), 1603 .nmuxregs = ARRAY_SIZE(cf_muxreg),
1604 }, 1604 },
1605 }; 1605 };
1606 1606
1607 static struct spear_pingroup cf_pingroup = { 1607 static struct spear_pingroup cf_pingroup = {
1608 .name = "cf_grp", 1608 .name = "cf_grp",
1609 .pins = mcif_pins, 1609 .pins = mcif_pins,
1610 .npins = ARRAY_SIZE(mcif_pins), 1610 .npins = ARRAY_SIZE(mcif_pins),
1611 .modemuxs = cf_modemux, 1611 .modemuxs = cf_modemux,
1612 .nmodemuxs = ARRAY_SIZE(cf_modemux), 1612 .nmodemuxs = ARRAY_SIZE(cf_modemux),
1613 }; 1613 };
1614 1614
1615 static const char *const cf_grps[] = { "cf_grp" }; 1615 static const char *const cf_grps[] = { "cf_grp" };
1616 static struct spear_function cf_function = { 1616 static struct spear_function cf_function = {
1617 .name = "cf", 1617 .name = "cf",
1618 .groups = cf_grps, 1618 .groups = cf_grps,
1619 .ngroups = ARRAY_SIZE(cf_grps), 1619 .ngroups = ARRAY_SIZE(cf_grps),
1620 }; 1620 };
1621 1621
1622 /* Pad multiplexing for xd device */ 1622 /* Pad multiplexing for xd device */
1623 static struct spear_muxreg xd_muxreg[] = { 1623 static struct spear_muxreg xd_muxreg[] = {
1624 MCIF_MUXREG, 1624 MCIF_MUXREG,
1625 { 1625 {
1626 .reg = PERIP_CFG, 1626 .reg = PERIP_CFG,
1627 .mask = MCIF_SEL_MASK, 1627 .mask = MCIF_SEL_MASK,
1628 .val = MCIF_SEL_XD, 1628 .val = MCIF_SEL_XD,
1629 }, 1629 },
1630 }; 1630 };
1631 1631
1632 static struct spear_modemux xd_modemux[] = { 1632 static struct spear_modemux xd_modemux[] = {
1633 { 1633 {
1634 .muxregs = xd_muxreg, 1634 .muxregs = xd_muxreg,
1635 .nmuxregs = ARRAY_SIZE(xd_muxreg), 1635 .nmuxregs = ARRAY_SIZE(xd_muxreg),
1636 }, 1636 },
1637 }; 1637 };
1638 1638
1639 static struct spear_pingroup xd_pingroup = { 1639 static struct spear_pingroup xd_pingroup = {
1640 .name = "xd_grp", 1640 .name = "xd_grp",
1641 .pins = mcif_pins, 1641 .pins = mcif_pins,
1642 .npins = ARRAY_SIZE(mcif_pins), 1642 .npins = ARRAY_SIZE(mcif_pins),
1643 .modemuxs = xd_modemux, 1643 .modemuxs = xd_modemux,
1644 .nmodemuxs = ARRAY_SIZE(xd_modemux), 1644 .nmodemuxs = ARRAY_SIZE(xd_modemux),
1645 }; 1645 };
1646 1646
1647 static const char *const xd_grps[] = { "xd_grp" }; 1647 static const char *const xd_grps[] = { "xd_grp" };
1648 static struct spear_function xd_function = { 1648 static struct spear_function xd_function = {
1649 .name = "xd", 1649 .name = "xd",
1650 .groups = xd_grps, 1650 .groups = xd_grps,
1651 .ngroups = ARRAY_SIZE(xd_grps), 1651 .ngroups = ARRAY_SIZE(xd_grps),
1652 }; 1652 };
1653 1653
1654 /* pad multiplexing for clcd device */ 1654 /* pad multiplexing for clcd device */
1655 static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145, 1655 static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145,
1656 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 1656 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159,
1657 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 1657 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,
1658 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 1658 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187,
1659 188, 189, 190, 191 }; 1659 188, 189, 190, 191 };
1660 static struct spear_muxreg clcd_muxreg[] = { 1660 static struct spear_muxreg clcd_muxreg[] = {
1661 { 1661 {
1662 .reg = PAD_SHARED_IP_EN_1, 1662 .reg = PAD_SHARED_IP_EN_1,
1663 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK, 1663 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
1664 .val = 0, 1664 .val = 0,
1665 }, { 1665 }, {
1666 .reg = PAD_FUNCTION_EN_5, 1666 .reg = PAD_FUNCTION_EN_5,
1667 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, 1667 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1668 .val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, 1668 .val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1669 }, { 1669 }, {
1670 .reg = PAD_FUNCTION_EN_6, 1670 .reg = PAD_FUNCTION_EN_6,
1671 .mask = CLCD_AND_ARM_TRACE_REG5_MASK, 1671 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1672 .val = CLCD_AND_ARM_TRACE_REG5_MASK, 1672 .val = CLCD_AND_ARM_TRACE_REG5_MASK,
1673 }, { 1673 }, {
1674 .reg = PAD_FUNCTION_EN_7, 1674 .reg = PAD_FUNCTION_EN_7,
1675 .mask = CLCD_AND_ARM_TRACE_REG6_MASK, 1675 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1676 .val = CLCD_AND_ARM_TRACE_REG6_MASK, 1676 .val = CLCD_AND_ARM_TRACE_REG6_MASK,
1677 }, 1677 },
1678 }; 1678 };
1679 1679
1680 static struct spear_modemux clcd_modemux[] = { 1680 static struct spear_modemux clcd_modemux[] = {
1681 { 1681 {
1682 .muxregs = clcd_muxreg, 1682 .muxregs = clcd_muxreg,
1683 .nmuxregs = ARRAY_SIZE(clcd_muxreg), 1683 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
1684 }, 1684 },
1685 }; 1685 };
1686 1686
1687 static struct spear_pingroup clcd_pingroup = { 1687 static struct spear_pingroup clcd_pingroup = {
1688 .name = "clcd_grp", 1688 .name = "clcd_grp",
1689 .pins = clcd_pins, 1689 .pins = clcd_pins,
1690 .npins = ARRAY_SIZE(clcd_pins), 1690 .npins = ARRAY_SIZE(clcd_pins),
1691 .modemuxs = clcd_modemux, 1691 .modemuxs = clcd_modemux,
1692 .nmodemuxs = ARRAY_SIZE(clcd_modemux), 1692 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
1693 }; 1693 };
1694 1694
1695 /* Disable cld runtime to save panel damage */ 1695 /* Disable cld runtime to save panel damage */
1696 static struct spear_muxreg clcd_sleep_muxreg[] = { 1696 static struct spear_muxreg clcd_sleep_muxreg[] = {
1697 { 1697 {
1698 .reg = PAD_SHARED_IP_EN_1, 1698 .reg = PAD_SHARED_IP_EN_1,
1699 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK, 1699 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
1700 .val = 0, 1700 .val = 0,
1701 }, { 1701 }, {
1702 .reg = PAD_FUNCTION_EN_5, 1702 .reg = PAD_FUNCTION_EN_5,
1703 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, 1703 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1704 .val = 0x0, 1704 .val = 0x0,
1705 }, { 1705 }, {
1706 .reg = PAD_FUNCTION_EN_6, 1706 .reg = PAD_FUNCTION_EN_6,
1707 .mask = CLCD_AND_ARM_TRACE_REG5_MASK, 1707 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1708 .val = 0x0, 1708 .val = 0x0,
1709 }, { 1709 }, {
1710 .reg = PAD_FUNCTION_EN_7, 1710 .reg = PAD_FUNCTION_EN_7,
1711 .mask = CLCD_AND_ARM_TRACE_REG6_MASK, 1711 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1712 .val = 0x0, 1712 .val = 0x0,
1713 }, 1713 },
1714 }; 1714 };
1715 1715
1716 static struct spear_modemux clcd_sleep_modemux[] = { 1716 static struct spear_modemux clcd_sleep_modemux[] = {
1717 { 1717 {
1718 .muxregs = clcd_sleep_muxreg, 1718 .muxregs = clcd_sleep_muxreg,
1719 .nmuxregs = ARRAY_SIZE(clcd_sleep_muxreg), 1719 .nmuxregs = ARRAY_SIZE(clcd_sleep_muxreg),
1720 }, 1720 },
1721 }; 1721 };
1722 1722
1723 static struct spear_pingroup clcd_sleep_pingroup = { 1723 static struct spear_pingroup clcd_sleep_pingroup = {
1724 .name = "clcd_sleep_grp", 1724 .name = "clcd_sleep_grp",
1725 .pins = clcd_pins, 1725 .pins = clcd_pins,
1726 .npins = ARRAY_SIZE(clcd_pins), 1726 .npins = ARRAY_SIZE(clcd_pins),
1727 .modemuxs = clcd_sleep_modemux, 1727 .modemuxs = clcd_sleep_modemux,
1728 .nmodemuxs = ARRAY_SIZE(clcd_sleep_modemux), 1728 .nmodemuxs = ARRAY_SIZE(clcd_sleep_modemux),
1729 }; 1729 };
1730 1730
1731 static const char *const clcd_grps[] = { "clcd_grp", "clcd_sleep_grp" }; 1731 static const char *const clcd_grps[] = { "clcd_grp", "clcd_sleep_grp" };
1732 static struct spear_function clcd_function = { 1732 static struct spear_function clcd_function = {
1733 .name = "clcd", 1733 .name = "clcd",
1734 .groups = clcd_grps, 1734 .groups = clcd_grps,
1735 .ngroups = ARRAY_SIZE(clcd_grps), 1735 .ngroups = ARRAY_SIZE(clcd_grps),
1736 }; 1736 };
1737 1737
1738 /* pad multiplexing for arm_trace device */ 1738 /* pad multiplexing for arm_trace device */
1739 static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164, 1739 static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164,
1740 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 1740 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178,
1741 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 1741 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192,
1742 193, 194, 195, 196, 197, 198, 199, 200 }; 1742 193, 194, 195, 196, 197, 198, 199, 200 };
1743 static struct spear_muxreg arm_trace_muxreg[] = { 1743 static struct spear_muxreg arm_trace_muxreg[] = {
1744 { 1744 {
1745 .reg = PAD_SHARED_IP_EN_1, 1745 .reg = PAD_SHARED_IP_EN_1,
1746 .mask = ARM_TRACE_MASK, 1746 .mask = ARM_TRACE_MASK,
1747 .val = ARM_TRACE_MASK, 1747 .val = ARM_TRACE_MASK,
1748 }, { 1748 }, {
1749 .reg = PAD_FUNCTION_EN_5, 1749 .reg = PAD_FUNCTION_EN_5,
1750 .mask = CLCD_AND_ARM_TRACE_REG4_MASK, 1750 .mask = CLCD_AND_ARM_TRACE_REG4_MASK,
1751 .val = CLCD_AND_ARM_TRACE_REG4_MASK, 1751 .val = CLCD_AND_ARM_TRACE_REG4_MASK,
1752 }, { 1752 }, {
1753 .reg = PAD_FUNCTION_EN_6, 1753 .reg = PAD_FUNCTION_EN_6,
1754 .mask = CLCD_AND_ARM_TRACE_REG5_MASK, 1754 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1755 .val = CLCD_AND_ARM_TRACE_REG5_MASK, 1755 .val = CLCD_AND_ARM_TRACE_REG5_MASK,
1756 }, { 1756 }, {
1757 .reg = PAD_FUNCTION_EN_7, 1757 .reg = PAD_FUNCTION_EN_7,
1758 .mask = CLCD_AND_ARM_TRACE_REG6_MASK, 1758 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1759 .val = CLCD_AND_ARM_TRACE_REG6_MASK, 1759 .val = CLCD_AND_ARM_TRACE_REG6_MASK,
1760 }, 1760 },
1761 }; 1761 };
1762 1762
1763 static struct spear_modemux arm_trace_modemux[] = { 1763 static struct spear_modemux arm_trace_modemux[] = {
1764 { 1764 {
1765 .muxregs = arm_trace_muxreg, 1765 .muxregs = arm_trace_muxreg,
1766 .nmuxregs = ARRAY_SIZE(arm_trace_muxreg), 1766 .nmuxregs = ARRAY_SIZE(arm_trace_muxreg),
1767 }, 1767 },
1768 }; 1768 };
1769 1769
1770 static struct spear_pingroup arm_trace_pingroup = { 1770 static struct spear_pingroup arm_trace_pingroup = {
1771 .name = "arm_trace_grp", 1771 .name = "arm_trace_grp",
1772 .pins = arm_trace_pins, 1772 .pins = arm_trace_pins,
1773 .npins = ARRAY_SIZE(arm_trace_pins), 1773 .npins = ARRAY_SIZE(arm_trace_pins),
1774 .modemuxs = arm_trace_modemux, 1774 .modemuxs = arm_trace_modemux,
1775 .nmodemuxs = ARRAY_SIZE(arm_trace_modemux), 1775 .nmodemuxs = ARRAY_SIZE(arm_trace_modemux),
1776 }; 1776 };
1777 1777
1778 static const char *const arm_trace_grps[] = { "arm_trace_grp" }; 1778 static const char *const arm_trace_grps[] = { "arm_trace_grp" };
1779 static struct spear_function arm_trace_function = { 1779 static struct spear_function arm_trace_function = {
1780 .name = "arm_trace", 1780 .name = "arm_trace",
1781 .groups = arm_trace_grps, 1781 .groups = arm_trace_grps,
1782 .ngroups = ARRAY_SIZE(arm_trace_grps), 1782 .ngroups = ARRAY_SIZE(arm_trace_grps),
1783 }; 1783 };
1784 1784
1785 /* pad multiplexing for miphy_dbg device */ 1785 /* pad multiplexing for miphy_dbg device */
1786 static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 1786 static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103,
1787 132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 1787 132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
1788 148, 149, 150, 151, 152, 153, 154, 155, 156, 157 }; 1788 148, 149, 150, 151, 152, 153, 154, 155, 156, 157 };
1789 static struct spear_muxreg miphy_dbg_muxreg[] = { 1789 static struct spear_muxreg miphy_dbg_muxreg[] = {
1790 { 1790 {
1791 .reg = PAD_SHARED_IP_EN_1, 1791 .reg = PAD_SHARED_IP_EN_1,
1792 .mask = MIPHY_DBG_MASK, 1792 .mask = MIPHY_DBG_MASK,
1793 .val = MIPHY_DBG_MASK, 1793 .val = MIPHY_DBG_MASK,
1794 }, { 1794 }, {
1795 .reg = PAD_FUNCTION_EN_5, 1795 .reg = PAD_FUNCTION_EN_5,
1796 .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK, 1796 .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
1797 .val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK, 1797 .val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
1798 }, 1798 },
1799 }; 1799 };
1800 1800
1801 static struct spear_modemux miphy_dbg_modemux[] = { 1801 static struct spear_modemux miphy_dbg_modemux[] = {
1802 { 1802 {
1803 .muxregs = miphy_dbg_muxreg, 1803 .muxregs = miphy_dbg_muxreg,
1804 .nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg), 1804 .nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg),
1805 }, 1805 },
1806 }; 1806 };
1807 1807
1808 static struct spear_pingroup miphy_dbg_pingroup = { 1808 static struct spear_pingroup miphy_dbg_pingroup = {
1809 .name = "miphy_dbg_grp", 1809 .name = "miphy_dbg_grp",
1810 .pins = miphy_dbg_pins, 1810 .pins = miphy_dbg_pins,
1811 .npins = ARRAY_SIZE(miphy_dbg_pins), 1811 .npins = ARRAY_SIZE(miphy_dbg_pins),
1812 .modemuxs = miphy_dbg_modemux, 1812 .modemuxs = miphy_dbg_modemux,
1813 .nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux), 1813 .nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux),
1814 }; 1814 };
1815 1815
1816 static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" }; 1816 static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" };
1817 static struct spear_function miphy_dbg_function = { 1817 static struct spear_function miphy_dbg_function = {
1818 .name = "miphy_dbg", 1818 .name = "miphy_dbg",
1819 .groups = miphy_dbg_grps, 1819 .groups = miphy_dbg_grps,
1820 .ngroups = ARRAY_SIZE(miphy_dbg_grps), 1820 .ngroups = ARRAY_SIZE(miphy_dbg_grps),
1821 }; 1821 };
1822 1822
1823 /* pad multiplexing for pcie device */ 1823 /* pad multiplexing for pcie device */
1824 static const unsigned pcie_pins[] = { 250 }; 1824 static const unsigned pcie_pins[] = { 250 };
1825 static struct spear_muxreg pcie_muxreg[] = { 1825 static struct spear_muxreg pcie_muxreg[] = {
1826 { 1826 {
1827 .reg = PCIE_SATA_CFG, 1827 .reg = PCIE_SATA_CFG,
1828 .mask = SATA_PCIE_CFG_MASK, 1828 .mask = SATA_PCIE_CFG_MASK,
1829 .val = PCIE_CFG_VAL, 1829 .val = PCIE_CFG_VAL,
1830 }, 1830 },
1831 }; 1831 };
1832 1832
1833 static struct spear_modemux pcie_modemux[] = { 1833 static struct spear_modemux pcie_modemux[] = {
1834 { 1834 {
1835 .muxregs = pcie_muxreg, 1835 .muxregs = pcie_muxreg,
1836 .nmuxregs = ARRAY_SIZE(pcie_muxreg), 1836 .nmuxregs = ARRAY_SIZE(pcie_muxreg),
1837 }, 1837 },
1838 }; 1838 };
1839 1839
1840 static struct spear_pingroup pcie_pingroup = { 1840 static struct spear_pingroup pcie_pingroup = {
1841 .name = "pcie_grp", 1841 .name = "pcie_grp",
1842 .pins = pcie_pins, 1842 .pins = pcie_pins,
1843 .npins = ARRAY_SIZE(pcie_pins), 1843 .npins = ARRAY_SIZE(pcie_pins),
1844 .modemuxs = pcie_modemux, 1844 .modemuxs = pcie_modemux,
1845 .nmodemuxs = ARRAY_SIZE(pcie_modemux), 1845 .nmodemuxs = ARRAY_SIZE(pcie_modemux),
1846 }; 1846 };
1847 1847
1848 static const char *const pcie_grps[] = { "pcie_grp" }; 1848 static const char *const pcie_grps[] = { "pcie_grp" };
1849 static struct spear_function pcie_function = { 1849 static struct spear_function pcie_function = {
1850 .name = "pcie", 1850 .name = "pcie",
1851 .groups = pcie_grps, 1851 .groups = pcie_grps,
1852 .ngroups = ARRAY_SIZE(pcie_grps), 1852 .ngroups = ARRAY_SIZE(pcie_grps),
1853 }; 1853 };
1854 1854
1855 /* pad multiplexing for sata device */ 1855 /* pad multiplexing for sata device */
1856 static const unsigned sata_pins[] = { 250 }; 1856 static const unsigned sata_pins[] = { 250 };
1857 static struct spear_muxreg sata_muxreg[] = { 1857 static struct spear_muxreg sata_muxreg[] = {
1858 { 1858 {
1859 .reg = PCIE_SATA_CFG, 1859 .reg = PCIE_SATA_CFG,
1860 .mask = SATA_PCIE_CFG_MASK, 1860 .mask = SATA_PCIE_CFG_MASK,
1861 .val = SATA_CFG_VAL, 1861 .val = SATA_CFG_VAL,
1862 }, 1862 },
1863 }; 1863 };
1864 1864
1865 static struct spear_modemux sata_modemux[] = { 1865 static struct spear_modemux sata_modemux[] = {
1866 { 1866 {
1867 .muxregs = sata_muxreg, 1867 .muxregs = sata_muxreg,
1868 .nmuxregs = ARRAY_SIZE(sata_muxreg), 1868 .nmuxregs = ARRAY_SIZE(sata_muxreg),
1869 }, 1869 },
1870 }; 1870 };
1871 1871
1872 static struct spear_pingroup sata_pingroup = { 1872 static struct spear_pingroup sata_pingroup = {
1873 .name = "sata_grp", 1873 .name = "sata_grp",
1874 .pins = sata_pins, 1874 .pins = sata_pins,
1875 .npins = ARRAY_SIZE(sata_pins), 1875 .npins = ARRAY_SIZE(sata_pins),
1876 .modemuxs = sata_modemux, 1876 .modemuxs = sata_modemux,
1877 .nmodemuxs = ARRAY_SIZE(sata_modemux), 1877 .nmodemuxs = ARRAY_SIZE(sata_modemux),
1878 }; 1878 };
1879 1879
1880 static const char *const sata_grps[] = { "sata_grp" }; 1880 static const char *const sata_grps[] = { "sata_grp" };
1881 static struct spear_function sata_function = { 1881 static struct spear_function sata_function = {
1882 .name = "sata", 1882 .name = "sata",
1883 .groups = sata_grps, 1883 .groups = sata_grps,
1884 .ngroups = ARRAY_SIZE(sata_grps), 1884 .ngroups = ARRAY_SIZE(sata_grps),
1885 }; 1885 };
1886 1886
1887 /* pingroups */ 1887 /* pingroups */
1888 static struct spear_pingroup *spear1340_pingroups[] = { 1888 static struct spear_pingroup *spear1340_pingroups[] = {
1889 &pads_as_gpio_pingroup, 1889 &pads_as_gpio_pingroup,
1890 &fsmc_8bit_pingroup, 1890 &fsmc_8bit_pingroup,
1891 &fsmc_16bit_pingroup, 1891 &fsmc_16bit_pingroup,
1892 &fsmc_pnor_pingroup, 1892 &fsmc_pnor_pingroup,
1893 &keyboard_row_col_pingroup, 1893 &keyboard_row_col_pingroup,
1894 &keyboard_col5_pingroup, 1894 &keyboard_col5_pingroup,
1895 &spdif_in_pingroup, 1895 &spdif_in_pingroup,
1896 &spdif_out_pingroup, 1896 &spdif_out_pingroup,
1897 &gpt_0_1_pingroup, 1897 &gpt_0_1_pingroup,
1898 &pwm0_pingroup, 1898 &pwm0_pingroup,
1899 &pwm1_pingroup, 1899 &pwm1_pingroup,
1900 &pwm2_pingroup, 1900 &pwm2_pingroup,
1901 &pwm3_pingroup, 1901 &pwm3_pingroup,
1902 &vip_mux_pingroup, 1902 &vip_mux_pingroup,
1903 &vip_mux_cam0_pingroup, 1903 &vip_mux_cam0_pingroup,
1904 &vip_mux_cam1_pingroup, 1904 &vip_mux_cam1_pingroup,
1905 &vip_mux_cam2_pingroup, 1905 &vip_mux_cam2_pingroup,
1906 &vip_mux_cam3_pingroup, 1906 &vip_mux_cam3_pingroup,
1907 &cam0_pingroup, 1907 &cam0_pingroup,
1908 &cam1_pingroup, 1908 &cam1_pingroup,
1909 &cam2_pingroup, 1909 &cam2_pingroup,
1910 &cam3_pingroup, 1910 &cam3_pingroup,
1911 &smi_pingroup, 1911 &smi_pingroup,
1912 &ssp0_pingroup, 1912 &ssp0_pingroup,
1913 &ssp0_cs1_pingroup, 1913 &ssp0_cs1_pingroup,
1914 &ssp0_cs2_pingroup, 1914 &ssp0_cs2_pingroup,
1915 &ssp0_cs3_pingroup, 1915 &ssp0_cs3_pingroup,
1916 &uart0_pingroup, 1916 &uart0_pingroup,
1917 &uart0_enh_pingroup, 1917 &uart0_enh_pingroup,
1918 &uart1_pingroup, 1918 &uart1_pingroup,
1919 &i2s_in_pingroup, 1919 &i2s_in_pingroup,
1920 &i2s_out_pingroup, 1920 &i2s_out_pingroup,
1921 &gmii_pingroup, 1921 &gmii_pingroup,
1922 &rgmii_pingroup, 1922 &rgmii_pingroup,
1923 &rmii_pingroup, 1923 &rmii_pingroup,
1924 &sgmii_pingroup, 1924 &sgmii_pingroup,
1925 &i2c0_pingroup, 1925 &i2c0_pingroup,
1926 &i2c1_pingroup, 1926 &i2c1_pingroup,
1927 &cec0_pingroup, 1927 &cec0_pingroup,
1928 &cec1_pingroup, 1928 &cec1_pingroup,
1929 &sdhci_pingroup, 1929 &sdhci_pingroup,
1930 &cf_pingroup, 1930 &cf_pingroup,
1931 &xd_pingroup, 1931 &xd_pingroup,
1932 &clcd_sleep_pingroup, 1932 &clcd_sleep_pingroup,
1933 &clcd_pingroup, 1933 &clcd_pingroup,
1934 &arm_trace_pingroup, 1934 &arm_trace_pingroup,
1935 &miphy_dbg_pingroup, 1935 &miphy_dbg_pingroup,
1936 &pcie_pingroup, 1936 &pcie_pingroup,
1937 &sata_pingroup, 1937 &sata_pingroup,
1938 }; 1938 };
1939 1939
1940 /* functions */ 1940 /* functions */
1941 static struct spear_function *spear1340_functions[] = { 1941 static struct spear_function *spear1340_functions[] = {
1942 &pads_as_gpio_function, 1942 &pads_as_gpio_function,
1943 &fsmc_function, 1943 &fsmc_function,
1944 &keyboard_function, 1944 &keyboard_function,
1945 &spdif_in_function, 1945 &spdif_in_function,
1946 &spdif_out_function, 1946 &spdif_out_function,
1947 &gpt_0_1_function, 1947 &gpt_0_1_function,
1948 &pwm_function, 1948 &pwm_function,
1949 &vip_function, 1949 &vip_function,
1950 &cam0_function, 1950 &cam0_function,
1951 &cam1_function, 1951 &cam1_function,
1952 &cam2_function, 1952 &cam2_function,
1953 &cam3_function, 1953 &cam3_function,
1954 &smi_function, 1954 &smi_function,
1955 &ssp0_function, 1955 &ssp0_function,
1956 &uart0_function, 1956 &uart0_function,
1957 &uart1_function, 1957 &uart1_function,
1958 &i2s_function, 1958 &i2s_function,
1959 &gmac_function, 1959 &gmac_function,
1960 &i2c0_function, 1960 &i2c0_function,
1961 &i2c1_function, 1961 &i2c1_function,
1962 &cec0_function, 1962 &cec0_function,
1963 &cec1_function, 1963 &cec1_function,
1964 &sdhci_function, 1964 &sdhci_function,
1965 &cf_function, 1965 &cf_function,
1966 &xd_function, 1966 &xd_function,
1967 &clcd_function, 1967 &clcd_function,
1968 &arm_trace_function, 1968 &arm_trace_function,
1969 &miphy_dbg_function, 1969 &miphy_dbg_function,
1970 &pcie_function, 1970 &pcie_function,
1971 &sata_function, 1971 &sata_function,
1972 }; 1972 };
1973 1973
1974 static struct spear_pinctrl_machdata spear1340_machdata = { 1974 static struct spear_pinctrl_machdata spear1340_machdata = {
1975 .pins = spear1340_pins, 1975 .pins = spear1340_pins,
1976 .npins = ARRAY_SIZE(spear1340_pins), 1976 .npins = ARRAY_SIZE(spear1340_pins),
1977 .groups = spear1340_pingroups, 1977 .groups = spear1340_pingroups,
1978 .ngroups = ARRAY_SIZE(spear1340_pingroups), 1978 .ngroups = ARRAY_SIZE(spear1340_pingroups),
1979 .functions = spear1340_functions, 1979 .functions = spear1340_functions,
1980 .nfunctions = ARRAY_SIZE(spear1340_functions), 1980 .nfunctions = ARRAY_SIZE(spear1340_functions),
1981 .modes_supported = false, 1981 .modes_supported = false,
1982 }; 1982 };
1983 1983
1984 static struct of_device_id spear1340_pinctrl_of_match[] = { 1984 static struct of_device_id spear1340_pinctrl_of_match[] = {
1985 { 1985 {
1986 .compatible = "st,spear1340-pinmux", 1986 .compatible = "st,spear1340-pinmux",
1987 }, 1987 },
1988 {}, 1988 {},
1989 }; 1989 };
1990 1990
1991 static int __devinit spear1340_pinctrl_probe(struct platform_device *pdev) 1991 static int __devinit spear1340_pinctrl_probe(struct platform_device *pdev)
1992 { 1992 {
1993 return spear_pinctrl_probe(pdev, &spear1340_machdata); 1993 return spear_pinctrl_probe(pdev, &spear1340_machdata);
1994 } 1994 }
1995 1995
1996 static int __devexit spear1340_pinctrl_remove(struct platform_device *pdev) 1996 static int spear1340_pinctrl_remove(struct platform_device *pdev)
1997 { 1997 {
1998 return spear_pinctrl_remove(pdev); 1998 return spear_pinctrl_remove(pdev);
1999 } 1999 }
2000 2000
2001 static struct platform_driver spear1340_pinctrl_driver = { 2001 static struct platform_driver spear1340_pinctrl_driver = {
2002 .driver = { 2002 .driver = {
2003 .name = DRIVER_NAME, 2003 .name = DRIVER_NAME,
2004 .owner = THIS_MODULE, 2004 .owner = THIS_MODULE,
2005 .of_match_table = spear1340_pinctrl_of_match, 2005 .of_match_table = spear1340_pinctrl_of_match,
2006 }, 2006 },
2007 .probe = spear1340_pinctrl_probe, 2007 .probe = spear1340_pinctrl_probe,
2008 .remove = spear1340_pinctrl_remove, 2008 .remove = spear1340_pinctrl_remove,
2009 }; 2009 };
2010 2010
2011 static int __init spear1340_pinctrl_init(void) 2011 static int __init spear1340_pinctrl_init(void)
2012 { 2012 {
2013 return platform_driver_register(&spear1340_pinctrl_driver); 2013 return platform_driver_register(&spear1340_pinctrl_driver);
2014 } 2014 }
2015 arch_initcall(spear1340_pinctrl_init); 2015 arch_initcall(spear1340_pinctrl_init);
2016 2016
2017 static void __exit spear1340_pinctrl_exit(void) 2017 static void __exit spear1340_pinctrl_exit(void)
2018 { 2018 {
2019 platform_driver_unregister(&spear1340_pinctrl_driver); 2019 platform_driver_unregister(&spear1340_pinctrl_driver);
2020 } 2020 }
2021 module_exit(spear1340_pinctrl_exit); 2021 module_exit(spear1340_pinctrl_exit);
2022 2022
2023 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); 2023 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
2024 MODULE_DESCRIPTION("ST Microelectronics SPEAr1340 pinctrl driver"); 2024 MODULE_DESCRIPTION("ST Microelectronics SPEAr1340 pinctrl driver");
2025 MODULE_LICENSE("GPL v2"); 2025 MODULE_LICENSE("GPL v2");
2026 MODULE_DEVICE_TABLE(of, spear1340_pinctrl_of_match); 2026 MODULE_DEVICE_TABLE(of, spear1340_pinctrl_of_match);
2027 2027
drivers/pinctrl/spear/pinctrl-spear300.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Driver for the ST Microelectronics SPEAr300 pinmux 2 * Driver for the ST Microelectronics SPEAr300 pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/err.h> 12 #include <linux/err.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/module.h> 14 #include <linux/module.h>
15 #include <linux/of_device.h> 15 #include <linux/of_device.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include "pinctrl-spear3xx.h" 17 #include "pinctrl-spear3xx.h"
18 18
19 #define DRIVER_NAME "spear300-pinmux" 19 #define DRIVER_NAME "spear300-pinmux"
20 20
21 /* addresses */ 21 /* addresses */
22 #define PMX_CONFIG_REG 0x00 22 #define PMX_CONFIG_REG 0x00
23 #define MODE_CONFIG_REG 0x04 23 #define MODE_CONFIG_REG 0x04
24 24
25 /* modes */ 25 /* modes */
26 #define NAND_MODE (1 << 0) 26 #define NAND_MODE (1 << 0)
27 #define NOR_MODE (1 << 1) 27 #define NOR_MODE (1 << 1)
28 #define PHOTO_FRAME_MODE (1 << 2) 28 #define PHOTO_FRAME_MODE (1 << 2)
29 #define LEND_IP_PHONE_MODE (1 << 3) 29 #define LEND_IP_PHONE_MODE (1 << 3)
30 #define HEND_IP_PHONE_MODE (1 << 4) 30 #define HEND_IP_PHONE_MODE (1 << 4)
31 #define LEND_WIFI_PHONE_MODE (1 << 5) 31 #define LEND_WIFI_PHONE_MODE (1 << 5)
32 #define HEND_WIFI_PHONE_MODE (1 << 6) 32 #define HEND_WIFI_PHONE_MODE (1 << 6)
33 #define ATA_PABX_WI2S_MODE (1 << 7) 33 #define ATA_PABX_WI2S_MODE (1 << 7)
34 #define ATA_PABX_I2S_MODE (1 << 8) 34 #define ATA_PABX_I2S_MODE (1 << 8)
35 #define CAML_LCDW_MODE (1 << 9) 35 #define CAML_LCDW_MODE (1 << 9)
36 #define CAMU_LCD_MODE (1 << 10) 36 #define CAMU_LCD_MODE (1 << 10)
37 #define CAMU_WLCD_MODE (1 << 11) 37 #define CAMU_WLCD_MODE (1 << 11)
38 #define CAML_LCD_MODE (1 << 12) 38 #define CAML_LCD_MODE (1 << 12)
39 39
40 static struct spear_pmx_mode pmx_mode_nand = { 40 static struct spear_pmx_mode pmx_mode_nand = {
41 .name = "nand", 41 .name = "nand",
42 .mode = NAND_MODE, 42 .mode = NAND_MODE,
43 .reg = MODE_CONFIG_REG, 43 .reg = MODE_CONFIG_REG,
44 .mask = 0x0000000F, 44 .mask = 0x0000000F,
45 .val = 0x00, 45 .val = 0x00,
46 }; 46 };
47 47
48 static struct spear_pmx_mode pmx_mode_nor = { 48 static struct spear_pmx_mode pmx_mode_nor = {
49 .name = "nor", 49 .name = "nor",
50 .mode = NOR_MODE, 50 .mode = NOR_MODE,
51 .reg = MODE_CONFIG_REG, 51 .reg = MODE_CONFIG_REG,
52 .mask = 0x0000000F, 52 .mask = 0x0000000F,
53 .val = 0x01, 53 .val = 0x01,
54 }; 54 };
55 55
56 static struct spear_pmx_mode pmx_mode_photo_frame = { 56 static struct spear_pmx_mode pmx_mode_photo_frame = {
57 .name = "photo frame mode", 57 .name = "photo frame mode",
58 .mode = PHOTO_FRAME_MODE, 58 .mode = PHOTO_FRAME_MODE,
59 .reg = MODE_CONFIG_REG, 59 .reg = MODE_CONFIG_REG,
60 .mask = 0x0000000F, 60 .mask = 0x0000000F,
61 .val = 0x02, 61 .val = 0x02,
62 }; 62 };
63 63
64 static struct spear_pmx_mode pmx_mode_lend_ip_phone = { 64 static struct spear_pmx_mode pmx_mode_lend_ip_phone = {
65 .name = "lend ip phone mode", 65 .name = "lend ip phone mode",
66 .mode = LEND_IP_PHONE_MODE, 66 .mode = LEND_IP_PHONE_MODE,
67 .reg = MODE_CONFIG_REG, 67 .reg = MODE_CONFIG_REG,
68 .mask = 0x0000000F, 68 .mask = 0x0000000F,
69 .val = 0x03, 69 .val = 0x03,
70 }; 70 };
71 71
72 static struct spear_pmx_mode pmx_mode_hend_ip_phone = { 72 static struct spear_pmx_mode pmx_mode_hend_ip_phone = {
73 .name = "hend ip phone mode", 73 .name = "hend ip phone mode",
74 .mode = HEND_IP_PHONE_MODE, 74 .mode = HEND_IP_PHONE_MODE,
75 .reg = MODE_CONFIG_REG, 75 .reg = MODE_CONFIG_REG,
76 .mask = 0x0000000F, 76 .mask = 0x0000000F,
77 .val = 0x04, 77 .val = 0x04,
78 }; 78 };
79 79
80 static struct spear_pmx_mode pmx_mode_lend_wifi_phone = { 80 static struct spear_pmx_mode pmx_mode_lend_wifi_phone = {
81 .name = "lend wifi phone mode", 81 .name = "lend wifi phone mode",
82 .mode = LEND_WIFI_PHONE_MODE, 82 .mode = LEND_WIFI_PHONE_MODE,
83 .reg = MODE_CONFIG_REG, 83 .reg = MODE_CONFIG_REG,
84 .mask = 0x0000000F, 84 .mask = 0x0000000F,
85 .val = 0x05, 85 .val = 0x05,
86 }; 86 };
87 87
88 static struct spear_pmx_mode pmx_mode_hend_wifi_phone = { 88 static struct spear_pmx_mode pmx_mode_hend_wifi_phone = {
89 .name = "hend wifi phone mode", 89 .name = "hend wifi phone mode",
90 .mode = HEND_WIFI_PHONE_MODE, 90 .mode = HEND_WIFI_PHONE_MODE,
91 .reg = MODE_CONFIG_REG, 91 .reg = MODE_CONFIG_REG,
92 .mask = 0x0000000F, 92 .mask = 0x0000000F,
93 .val = 0x06, 93 .val = 0x06,
94 }; 94 };
95 95
96 static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = { 96 static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = {
97 .name = "ata pabx wi2s mode", 97 .name = "ata pabx wi2s mode",
98 .mode = ATA_PABX_WI2S_MODE, 98 .mode = ATA_PABX_WI2S_MODE,
99 .reg = MODE_CONFIG_REG, 99 .reg = MODE_CONFIG_REG,
100 .mask = 0x0000000F, 100 .mask = 0x0000000F,
101 .val = 0x07, 101 .val = 0x07,
102 }; 102 };
103 103
104 static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = { 104 static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = {
105 .name = "ata pabx i2s mode", 105 .name = "ata pabx i2s mode",
106 .mode = ATA_PABX_I2S_MODE, 106 .mode = ATA_PABX_I2S_MODE,
107 .reg = MODE_CONFIG_REG, 107 .reg = MODE_CONFIG_REG,
108 .mask = 0x0000000F, 108 .mask = 0x0000000F,
109 .val = 0x08, 109 .val = 0x08,
110 }; 110 };
111 111
112 static struct spear_pmx_mode pmx_mode_caml_lcdw = { 112 static struct spear_pmx_mode pmx_mode_caml_lcdw = {
113 .name = "caml lcdw mode", 113 .name = "caml lcdw mode",
114 .mode = CAML_LCDW_MODE, 114 .mode = CAML_LCDW_MODE,
115 .reg = MODE_CONFIG_REG, 115 .reg = MODE_CONFIG_REG,
116 .mask = 0x0000000F, 116 .mask = 0x0000000F,
117 .val = 0x0C, 117 .val = 0x0C,
118 }; 118 };
119 119
120 static struct spear_pmx_mode pmx_mode_camu_lcd = { 120 static struct spear_pmx_mode pmx_mode_camu_lcd = {
121 .name = "camu lcd mode", 121 .name = "camu lcd mode",
122 .mode = CAMU_LCD_MODE, 122 .mode = CAMU_LCD_MODE,
123 .reg = MODE_CONFIG_REG, 123 .reg = MODE_CONFIG_REG,
124 .mask = 0x0000000F, 124 .mask = 0x0000000F,
125 .val = 0x0D, 125 .val = 0x0D,
126 }; 126 };
127 127
128 static struct spear_pmx_mode pmx_mode_camu_wlcd = { 128 static struct spear_pmx_mode pmx_mode_camu_wlcd = {
129 .name = "camu wlcd mode", 129 .name = "camu wlcd mode",
130 .mode = CAMU_WLCD_MODE, 130 .mode = CAMU_WLCD_MODE,
131 .reg = MODE_CONFIG_REG, 131 .reg = MODE_CONFIG_REG,
132 .mask = 0x0000000F, 132 .mask = 0x0000000F,
133 .val = 0xE, 133 .val = 0xE,
134 }; 134 };
135 135
136 static struct spear_pmx_mode pmx_mode_caml_lcd = { 136 static struct spear_pmx_mode pmx_mode_caml_lcd = {
137 .name = "caml lcd mode", 137 .name = "caml lcd mode",
138 .mode = CAML_LCD_MODE, 138 .mode = CAML_LCD_MODE,
139 .reg = MODE_CONFIG_REG, 139 .reg = MODE_CONFIG_REG,
140 .mask = 0x0000000F, 140 .mask = 0x0000000F,
141 .val = 0x0F, 141 .val = 0x0F,
142 }; 142 };
143 143
144 static struct spear_pmx_mode *spear300_pmx_modes[] = { 144 static struct spear_pmx_mode *spear300_pmx_modes[] = {
145 &pmx_mode_nand, 145 &pmx_mode_nand,
146 &pmx_mode_nor, 146 &pmx_mode_nor,
147 &pmx_mode_photo_frame, 147 &pmx_mode_photo_frame,
148 &pmx_mode_lend_ip_phone, 148 &pmx_mode_lend_ip_phone,
149 &pmx_mode_hend_ip_phone, 149 &pmx_mode_hend_ip_phone,
150 &pmx_mode_lend_wifi_phone, 150 &pmx_mode_lend_wifi_phone,
151 &pmx_mode_hend_wifi_phone, 151 &pmx_mode_hend_wifi_phone,
152 &pmx_mode_ata_pabx_wi2s, 152 &pmx_mode_ata_pabx_wi2s,
153 &pmx_mode_ata_pabx_i2s, 153 &pmx_mode_ata_pabx_i2s,
154 &pmx_mode_caml_lcdw, 154 &pmx_mode_caml_lcdw,
155 &pmx_mode_camu_lcd, 155 &pmx_mode_camu_lcd,
156 &pmx_mode_camu_wlcd, 156 &pmx_mode_camu_wlcd,
157 &pmx_mode_caml_lcd, 157 &pmx_mode_caml_lcd,
158 }; 158 };
159 159
160 /* fsmc_2chips_pins */ 160 /* fsmc_2chips_pins */
161 static const unsigned fsmc_2chips_pins[] = { 1, 97 }; 161 static const unsigned fsmc_2chips_pins[] = { 1, 97 };
162 static struct spear_muxreg fsmc_2chips_muxreg[] = { 162 static struct spear_muxreg fsmc_2chips_muxreg[] = {
163 { 163 {
164 .reg = PMX_CONFIG_REG, 164 .reg = PMX_CONFIG_REG,
165 .mask = PMX_FIRDA_MASK, 165 .mask = PMX_FIRDA_MASK,
166 .val = 0, 166 .val = 0,
167 }, 167 },
168 }; 168 };
169 169
170 static struct spear_modemux fsmc_2chips_modemux[] = { 170 static struct spear_modemux fsmc_2chips_modemux[] = {
171 { 171 {
172 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | 172 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
173 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, 173 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
174 .muxregs = fsmc_2chips_muxreg, 174 .muxregs = fsmc_2chips_muxreg,
175 .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg), 175 .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg),
176 }, 176 },
177 }; 177 };
178 178
179 static struct spear_pingroup fsmc_2chips_pingroup = { 179 static struct spear_pingroup fsmc_2chips_pingroup = {
180 .name = "fsmc_2chips_grp", 180 .name = "fsmc_2chips_grp",
181 .pins = fsmc_2chips_pins, 181 .pins = fsmc_2chips_pins,
182 .npins = ARRAY_SIZE(fsmc_2chips_pins), 182 .npins = ARRAY_SIZE(fsmc_2chips_pins),
183 .modemuxs = fsmc_2chips_modemux, 183 .modemuxs = fsmc_2chips_modemux,
184 .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux), 184 .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux),
185 }; 185 };
186 186
187 /* fsmc_4chips_pins */ 187 /* fsmc_4chips_pins */
188 static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 }; 188 static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 };
189 static struct spear_muxreg fsmc_4chips_muxreg[] = { 189 static struct spear_muxreg fsmc_4chips_muxreg[] = {
190 { 190 {
191 .reg = PMX_CONFIG_REG, 191 .reg = PMX_CONFIG_REG,
192 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, 192 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
193 .val = 0, 193 .val = 0,
194 }, 194 },
195 }; 195 };
196 196
197 static struct spear_modemux fsmc_4chips_modemux[] = { 197 static struct spear_modemux fsmc_4chips_modemux[] = {
198 { 198 {
199 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | 199 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
200 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, 200 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
201 .muxregs = fsmc_4chips_muxreg, 201 .muxregs = fsmc_4chips_muxreg,
202 .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg), 202 .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg),
203 }, 203 },
204 }; 204 };
205 205
206 static struct spear_pingroup fsmc_4chips_pingroup = { 206 static struct spear_pingroup fsmc_4chips_pingroup = {
207 .name = "fsmc_4chips_grp", 207 .name = "fsmc_4chips_grp",
208 .pins = fsmc_4chips_pins, 208 .pins = fsmc_4chips_pins,
209 .npins = ARRAY_SIZE(fsmc_4chips_pins), 209 .npins = ARRAY_SIZE(fsmc_4chips_pins),
210 .modemuxs = fsmc_4chips_modemux, 210 .modemuxs = fsmc_4chips_modemux,
211 .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux), 211 .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux),
212 }; 212 };
213 213
214 static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp" 214 static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp"
215 }; 215 };
216 static struct spear_function fsmc_function = { 216 static struct spear_function fsmc_function = {
217 .name = "fsmc", 217 .name = "fsmc",
218 .groups = fsmc_grps, 218 .groups = fsmc_grps,
219 .ngroups = ARRAY_SIZE(fsmc_grps), 219 .ngroups = ARRAY_SIZE(fsmc_grps),
220 }; 220 };
221 221
222 /* clcd_lcdmode_pins */ 222 /* clcd_lcdmode_pins */
223 static const unsigned clcd_lcdmode_pins[] = { 49, 50 }; 223 static const unsigned clcd_lcdmode_pins[] = { 49, 50 };
224 static struct spear_muxreg clcd_lcdmode_muxreg[] = { 224 static struct spear_muxreg clcd_lcdmode_muxreg[] = {
225 { 225 {
226 .reg = PMX_CONFIG_REG, 226 .reg = PMX_CONFIG_REG,
227 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 227 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
228 .val = 0, 228 .val = 0,
229 }, 229 },
230 }; 230 };
231 231
232 static struct spear_modemux clcd_lcdmode_modemux[] = { 232 static struct spear_modemux clcd_lcdmode_modemux[] = {
233 { 233 {
234 .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE | 234 .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
235 CAMU_LCD_MODE | CAML_LCD_MODE, 235 CAMU_LCD_MODE | CAML_LCD_MODE,
236 .muxregs = clcd_lcdmode_muxreg, 236 .muxregs = clcd_lcdmode_muxreg,
237 .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg), 237 .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg),
238 }, 238 },
239 }; 239 };
240 240
241 static struct spear_pingroup clcd_lcdmode_pingroup = { 241 static struct spear_pingroup clcd_lcdmode_pingroup = {
242 .name = "clcd_lcdmode_grp", 242 .name = "clcd_lcdmode_grp",
243 .pins = clcd_lcdmode_pins, 243 .pins = clcd_lcdmode_pins,
244 .npins = ARRAY_SIZE(clcd_lcdmode_pins), 244 .npins = ARRAY_SIZE(clcd_lcdmode_pins),
245 .modemuxs = clcd_lcdmode_modemux, 245 .modemuxs = clcd_lcdmode_modemux,
246 .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux), 246 .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux),
247 }; 247 };
248 248
249 /* clcd_pfmode_pins */ 249 /* clcd_pfmode_pins */
250 static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 }; 250 static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 };
251 static struct spear_muxreg clcd_pfmode_muxreg[] = { 251 static struct spear_muxreg clcd_pfmode_muxreg[] = {
252 { 252 {
253 .reg = PMX_CONFIG_REG, 253 .reg = PMX_CONFIG_REG,
254 .mask = PMX_TIMER_2_3_MASK, 254 .mask = PMX_TIMER_2_3_MASK,
255 .val = 0, 255 .val = 0,
256 }, 256 },
257 }; 257 };
258 258
259 static struct spear_modemux clcd_pfmode_modemux[] = { 259 static struct spear_modemux clcd_pfmode_modemux[] = {
260 { 260 {
261 .modes = PHOTO_FRAME_MODE, 261 .modes = PHOTO_FRAME_MODE,
262 .muxregs = clcd_pfmode_muxreg, 262 .muxregs = clcd_pfmode_muxreg,
263 .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg), 263 .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg),
264 }, 264 },
265 }; 265 };
266 266
267 static struct spear_pingroup clcd_pfmode_pingroup = { 267 static struct spear_pingroup clcd_pfmode_pingroup = {
268 .name = "clcd_pfmode_grp", 268 .name = "clcd_pfmode_grp",
269 .pins = clcd_pfmode_pins, 269 .pins = clcd_pfmode_pins,
270 .npins = ARRAY_SIZE(clcd_pfmode_pins), 270 .npins = ARRAY_SIZE(clcd_pfmode_pins),
271 .modemuxs = clcd_pfmode_modemux, 271 .modemuxs = clcd_pfmode_modemux,
272 .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux), 272 .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux),
273 }; 273 };
274 274
275 static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp" 275 static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp"
276 }; 276 };
277 static struct spear_function clcd_function = { 277 static struct spear_function clcd_function = {
278 .name = "clcd", 278 .name = "clcd",
279 .groups = clcd_grps, 279 .groups = clcd_grps,
280 .ngroups = ARRAY_SIZE(clcd_grps), 280 .ngroups = ARRAY_SIZE(clcd_grps),
281 }; 281 };
282 282
283 /* tdm_pins */ 283 /* tdm_pins */
284 static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 }; 284 static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 };
285 static struct spear_muxreg tdm_muxreg[] = { 285 static struct spear_muxreg tdm_muxreg[] = {
286 { 286 {
287 .reg = PMX_CONFIG_REG, 287 .reg = PMX_CONFIG_REG,
288 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, 288 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
289 .val = 0, 289 .val = 0,
290 }, 290 },
291 }; 291 };
292 292
293 static struct spear_modemux tdm_modemux[] = { 293 static struct spear_modemux tdm_modemux[] = {
294 { 294 {
295 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | 295 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
296 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE 296 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
297 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE 297 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
298 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE 298 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
299 | CAMU_WLCD_MODE | CAML_LCD_MODE, 299 | CAMU_WLCD_MODE | CAML_LCD_MODE,
300 .muxregs = tdm_muxreg, 300 .muxregs = tdm_muxreg,
301 .nmuxregs = ARRAY_SIZE(tdm_muxreg), 301 .nmuxregs = ARRAY_SIZE(tdm_muxreg),
302 }, 302 },
303 }; 303 };
304 304
305 static struct spear_pingroup tdm_pingroup = { 305 static struct spear_pingroup tdm_pingroup = {
306 .name = "tdm_grp", 306 .name = "tdm_grp",
307 .pins = tdm_pins, 307 .pins = tdm_pins,
308 .npins = ARRAY_SIZE(tdm_pins), 308 .npins = ARRAY_SIZE(tdm_pins),
309 .modemuxs = tdm_modemux, 309 .modemuxs = tdm_modemux,
310 .nmodemuxs = ARRAY_SIZE(tdm_modemux), 310 .nmodemuxs = ARRAY_SIZE(tdm_modemux),
311 }; 311 };
312 312
313 static const char *const tdm_grps[] = { "tdm_grp" }; 313 static const char *const tdm_grps[] = { "tdm_grp" };
314 static struct spear_function tdm_function = { 314 static struct spear_function tdm_function = {
315 .name = "tdm", 315 .name = "tdm",
316 .groups = tdm_grps, 316 .groups = tdm_grps,
317 .ngroups = ARRAY_SIZE(tdm_grps), 317 .ngroups = ARRAY_SIZE(tdm_grps),
318 }; 318 };
319 319
320 /* i2c_clk_pins */ 320 /* i2c_clk_pins */
321 static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 }; 321 static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 };
322 static struct spear_muxreg i2c_clk_muxreg[] = { 322 static struct spear_muxreg i2c_clk_muxreg[] = {
323 { 323 {
324 .reg = PMX_CONFIG_REG, 324 .reg = PMX_CONFIG_REG,
325 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 325 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
326 .val = 0, 326 .val = 0,
327 }, 327 },
328 }; 328 };
329 329
330 static struct spear_modemux i2c_clk_modemux[] = { 330 static struct spear_modemux i2c_clk_modemux[] = {
331 { 331 {
332 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | 332 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
333 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | 333 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
334 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE 334 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE
335 | CAML_LCD_MODE, 335 | CAML_LCD_MODE,
336 .muxregs = i2c_clk_muxreg, 336 .muxregs = i2c_clk_muxreg,
337 .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg), 337 .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg),
338 }, 338 },
339 }; 339 };
340 340
341 static struct spear_pingroup i2c_clk_pingroup = { 341 static struct spear_pingroup i2c_clk_pingroup = {
342 .name = "i2c_clk_grp_grp", 342 .name = "i2c_clk_grp_grp",
343 .pins = i2c_clk_pins, 343 .pins = i2c_clk_pins,
344 .npins = ARRAY_SIZE(i2c_clk_pins), 344 .npins = ARRAY_SIZE(i2c_clk_pins),
345 .modemuxs = i2c_clk_modemux, 345 .modemuxs = i2c_clk_modemux,
346 .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux), 346 .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux),
347 }; 347 };
348 348
349 static const char *const i2c_grps[] = { "i2c_clk_grp" }; 349 static const char *const i2c_grps[] = { "i2c_clk_grp" };
350 static struct spear_function i2c_function = { 350 static struct spear_function i2c_function = {
351 .name = "i2c1", 351 .name = "i2c1",
352 .groups = i2c_grps, 352 .groups = i2c_grps,
353 .ngroups = ARRAY_SIZE(i2c_grps), 353 .ngroups = ARRAY_SIZE(i2c_grps),
354 }; 354 };
355 355
356 /* caml_pins */ 356 /* caml_pins */
357 static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 }; 357 static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
358 static struct spear_muxreg caml_muxreg[] = { 358 static struct spear_muxreg caml_muxreg[] = {
359 { 359 {
360 .reg = PMX_CONFIG_REG, 360 .reg = PMX_CONFIG_REG,
361 .mask = PMX_MII_MASK, 361 .mask = PMX_MII_MASK,
362 .val = 0, 362 .val = 0,
363 }, 363 },
364 }; 364 };
365 365
366 static struct spear_modemux caml_modemux[] = { 366 static struct spear_modemux caml_modemux[] = {
367 { 367 {
368 .modes = CAML_LCDW_MODE | CAML_LCD_MODE, 368 .modes = CAML_LCDW_MODE | CAML_LCD_MODE,
369 .muxregs = caml_muxreg, 369 .muxregs = caml_muxreg,
370 .nmuxregs = ARRAY_SIZE(caml_muxreg), 370 .nmuxregs = ARRAY_SIZE(caml_muxreg),
371 }, 371 },
372 }; 372 };
373 373
374 static struct spear_pingroup caml_pingroup = { 374 static struct spear_pingroup caml_pingroup = {
375 .name = "caml_grp", 375 .name = "caml_grp",
376 .pins = caml_pins, 376 .pins = caml_pins,
377 .npins = ARRAY_SIZE(caml_pins), 377 .npins = ARRAY_SIZE(caml_pins),
378 .modemuxs = caml_modemux, 378 .modemuxs = caml_modemux,
379 .nmodemuxs = ARRAY_SIZE(caml_modemux), 379 .nmodemuxs = ARRAY_SIZE(caml_modemux),
380 }; 380 };
381 381
382 /* camu_pins */ 382 /* camu_pins */
383 static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 }; 383 static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 };
384 static struct spear_muxreg camu_muxreg[] = { 384 static struct spear_muxreg camu_muxreg[] = {
385 { 385 {
386 .reg = PMX_CONFIG_REG, 386 .reg = PMX_CONFIG_REG,
387 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK, 387 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
388 .val = 0, 388 .val = 0,
389 }, 389 },
390 }; 390 };
391 391
392 static struct spear_modemux camu_modemux[] = { 392 static struct spear_modemux camu_modemux[] = {
393 { 393 {
394 .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE, 394 .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE,
395 .muxregs = camu_muxreg, 395 .muxregs = camu_muxreg,
396 .nmuxregs = ARRAY_SIZE(camu_muxreg), 396 .nmuxregs = ARRAY_SIZE(camu_muxreg),
397 }, 397 },
398 }; 398 };
399 399
400 static struct spear_pingroup camu_pingroup = { 400 static struct spear_pingroup camu_pingroup = {
401 .name = "camu_grp", 401 .name = "camu_grp",
402 .pins = camu_pins, 402 .pins = camu_pins,
403 .npins = ARRAY_SIZE(camu_pins), 403 .npins = ARRAY_SIZE(camu_pins),
404 .modemuxs = camu_modemux, 404 .modemuxs = camu_modemux,
405 .nmodemuxs = ARRAY_SIZE(camu_modemux), 405 .nmodemuxs = ARRAY_SIZE(camu_modemux),
406 }; 406 };
407 407
408 static const char *const cam_grps[] = { "caml_grp", "camu_grp" }; 408 static const char *const cam_grps[] = { "caml_grp", "camu_grp" };
409 static struct spear_function cam_function = { 409 static struct spear_function cam_function = {
410 .name = "cam", 410 .name = "cam",
411 .groups = cam_grps, 411 .groups = cam_grps,
412 .ngroups = ARRAY_SIZE(cam_grps), 412 .ngroups = ARRAY_SIZE(cam_grps),
413 }; 413 };
414 414
415 /* dac_pins */ 415 /* dac_pins */
416 static const unsigned dac_pins[] = { 43, 44 }; 416 static const unsigned dac_pins[] = { 43, 44 };
417 static struct spear_muxreg dac_muxreg[] = { 417 static struct spear_muxreg dac_muxreg[] = {
418 { 418 {
419 .reg = PMX_CONFIG_REG, 419 .reg = PMX_CONFIG_REG,
420 .mask = PMX_TIMER_0_1_MASK, 420 .mask = PMX_TIMER_0_1_MASK,
421 .val = 0, 421 .val = 0,
422 }, 422 },
423 }; 423 };
424 424
425 static struct spear_modemux dac_modemux[] = { 425 static struct spear_modemux dac_modemux[] = {
426 { 426 {
427 .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE 427 .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
428 | CAMU_WLCD_MODE | CAML_LCD_MODE, 428 | CAMU_WLCD_MODE | CAML_LCD_MODE,
429 .muxregs = dac_muxreg, 429 .muxregs = dac_muxreg,
430 .nmuxregs = ARRAY_SIZE(dac_muxreg), 430 .nmuxregs = ARRAY_SIZE(dac_muxreg),
431 }, 431 },
432 }; 432 };
433 433
434 static struct spear_pingroup dac_pingroup = { 434 static struct spear_pingroup dac_pingroup = {
435 .name = "dac_grp", 435 .name = "dac_grp",
436 .pins = dac_pins, 436 .pins = dac_pins,
437 .npins = ARRAY_SIZE(dac_pins), 437 .npins = ARRAY_SIZE(dac_pins),
438 .modemuxs = dac_modemux, 438 .modemuxs = dac_modemux,
439 .nmodemuxs = ARRAY_SIZE(dac_modemux), 439 .nmodemuxs = ARRAY_SIZE(dac_modemux),
440 }; 440 };
441 441
442 static const char *const dac_grps[] = { "dac_grp" }; 442 static const char *const dac_grps[] = { "dac_grp" };
443 static struct spear_function dac_function = { 443 static struct spear_function dac_function = {
444 .name = "dac", 444 .name = "dac",
445 .groups = dac_grps, 445 .groups = dac_grps,
446 .ngroups = ARRAY_SIZE(dac_grps), 446 .ngroups = ARRAY_SIZE(dac_grps),
447 }; 447 };
448 448
449 /* i2s_pins */ 449 /* i2s_pins */
450 static const unsigned i2s_pins[] = { 39, 40, 41, 42 }; 450 static const unsigned i2s_pins[] = { 39, 40, 41, 42 };
451 static struct spear_muxreg i2s_muxreg[] = { 451 static struct spear_muxreg i2s_muxreg[] = {
452 { 452 {
453 .reg = PMX_CONFIG_REG, 453 .reg = PMX_CONFIG_REG,
454 .mask = PMX_UART0_MODEM_MASK, 454 .mask = PMX_UART0_MODEM_MASK,
455 .val = 0, 455 .val = 0,
456 }, 456 },
457 }; 457 };
458 458
459 static struct spear_modemux i2s_modemux[] = { 459 static struct spear_modemux i2s_modemux[] = {
460 { 460 {
461 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE 461 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
462 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | 462 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
463 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE 463 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
464 | CAMU_WLCD_MODE | CAML_LCD_MODE, 464 | CAMU_WLCD_MODE | CAML_LCD_MODE,
465 .muxregs = i2s_muxreg, 465 .muxregs = i2s_muxreg,
466 .nmuxregs = ARRAY_SIZE(i2s_muxreg), 466 .nmuxregs = ARRAY_SIZE(i2s_muxreg),
467 }, 467 },
468 }; 468 };
469 469
470 static struct spear_pingroup i2s_pingroup = { 470 static struct spear_pingroup i2s_pingroup = {
471 .name = "i2s_grp", 471 .name = "i2s_grp",
472 .pins = i2s_pins, 472 .pins = i2s_pins,
473 .npins = ARRAY_SIZE(i2s_pins), 473 .npins = ARRAY_SIZE(i2s_pins),
474 .modemuxs = i2s_modemux, 474 .modemuxs = i2s_modemux,
475 .nmodemuxs = ARRAY_SIZE(i2s_modemux), 475 .nmodemuxs = ARRAY_SIZE(i2s_modemux),
476 }; 476 };
477 477
478 static const char *const i2s_grps[] = { "i2s_grp" }; 478 static const char *const i2s_grps[] = { "i2s_grp" };
479 static struct spear_function i2s_function = { 479 static struct spear_function i2s_function = {
480 .name = "i2s", 480 .name = "i2s",
481 .groups = i2s_grps, 481 .groups = i2s_grps,
482 .ngroups = ARRAY_SIZE(i2s_grps), 482 .ngroups = ARRAY_SIZE(i2s_grps),
483 }; 483 };
484 484
485 /* sdhci_4bit_pins */ 485 /* sdhci_4bit_pins */
486 static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 }; 486 static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 };
487 static struct spear_muxreg sdhci_4bit_muxreg[] = { 487 static struct spear_muxreg sdhci_4bit_muxreg[] = {
488 { 488 {
489 .reg = PMX_CONFIG_REG, 489 .reg = PMX_CONFIG_REG,
490 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | 490 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
491 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | 491 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
492 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, 492 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
493 .val = 0, 493 .val = 0,
494 }, 494 },
495 }; 495 };
496 496
497 static struct spear_modemux sdhci_4bit_modemux[] = { 497 static struct spear_modemux sdhci_4bit_modemux[] = {
498 { 498 {
499 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | 499 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
500 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | 500 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
501 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | 501 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
502 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE, 502 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE,
503 .muxregs = sdhci_4bit_muxreg, 503 .muxregs = sdhci_4bit_muxreg,
504 .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg), 504 .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg),
505 }, 505 },
506 }; 506 };
507 507
508 static struct spear_pingroup sdhci_4bit_pingroup = { 508 static struct spear_pingroup sdhci_4bit_pingroup = {
509 .name = "sdhci_4bit_grp", 509 .name = "sdhci_4bit_grp",
510 .pins = sdhci_4bit_pins, 510 .pins = sdhci_4bit_pins,
511 .npins = ARRAY_SIZE(sdhci_4bit_pins), 511 .npins = ARRAY_SIZE(sdhci_4bit_pins),
512 .modemuxs = sdhci_4bit_modemux, 512 .modemuxs = sdhci_4bit_modemux,
513 .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux), 513 .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux),
514 }; 514 };
515 515
516 /* sdhci_8bit_pins */ 516 /* sdhci_8bit_pins */
517 static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32, 517 static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
518 33 }; 518 33 };
519 static struct spear_muxreg sdhci_8bit_muxreg[] = { 519 static struct spear_muxreg sdhci_8bit_muxreg[] = {
520 { 520 {
521 .reg = PMX_CONFIG_REG, 521 .reg = PMX_CONFIG_REG,
522 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | 522 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
523 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | 523 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
524 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK, 524 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
525 .val = 0, 525 .val = 0,
526 }, 526 },
527 }; 527 };
528 528
529 static struct spear_modemux sdhci_8bit_modemux[] = { 529 static struct spear_modemux sdhci_8bit_modemux[] = {
530 { 530 {
531 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | 531 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
532 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | 532 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
533 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | 533 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
534 CAMU_WLCD_MODE | CAML_LCD_MODE, 534 CAMU_WLCD_MODE | CAML_LCD_MODE,
535 .muxregs = sdhci_8bit_muxreg, 535 .muxregs = sdhci_8bit_muxreg,
536 .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg), 536 .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg),
537 }, 537 },
538 }; 538 };
539 539
540 static struct spear_pingroup sdhci_8bit_pingroup = { 540 static struct spear_pingroup sdhci_8bit_pingroup = {
541 .name = "sdhci_8bit_grp", 541 .name = "sdhci_8bit_grp",
542 .pins = sdhci_8bit_pins, 542 .pins = sdhci_8bit_pins,
543 .npins = ARRAY_SIZE(sdhci_8bit_pins), 543 .npins = ARRAY_SIZE(sdhci_8bit_pins),
544 .modemuxs = sdhci_8bit_modemux, 544 .modemuxs = sdhci_8bit_modemux,
545 .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux), 545 .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux),
546 }; 546 };
547 547
548 static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" }; 548 static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" };
549 static struct spear_function sdhci_function = { 549 static struct spear_function sdhci_function = {
550 .name = "sdhci", 550 .name = "sdhci",
551 .groups = sdhci_grps, 551 .groups = sdhci_grps,
552 .ngroups = ARRAY_SIZE(sdhci_grps), 552 .ngroups = ARRAY_SIZE(sdhci_grps),
553 }; 553 };
554 554
555 /* gpio1_0_to_3_pins */ 555 /* gpio1_0_to_3_pins */
556 static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 }; 556 static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 };
557 static struct spear_muxreg gpio1_0_to_3_muxreg[] = { 557 static struct spear_muxreg gpio1_0_to_3_muxreg[] = {
558 { 558 {
559 .reg = PMX_CONFIG_REG, 559 .reg = PMX_CONFIG_REG,
560 .mask = PMX_UART0_MODEM_MASK, 560 .mask = PMX_UART0_MODEM_MASK,
561 .val = 0, 561 .val = 0,
562 }, 562 },
563 }; 563 };
564 564
565 static struct spear_modemux gpio1_0_to_3_modemux[] = { 565 static struct spear_modemux gpio1_0_to_3_modemux[] = {
566 { 566 {
567 .modes = PHOTO_FRAME_MODE, 567 .modes = PHOTO_FRAME_MODE,
568 .muxregs = gpio1_0_to_3_muxreg, 568 .muxregs = gpio1_0_to_3_muxreg,
569 .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg), 569 .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg),
570 }, 570 },
571 }; 571 };
572 572
573 static struct spear_pingroup gpio1_0_to_3_pingroup = { 573 static struct spear_pingroup gpio1_0_to_3_pingroup = {
574 .name = "gpio1_0_to_3_grp", 574 .name = "gpio1_0_to_3_grp",
575 .pins = gpio1_0_to_3_pins, 575 .pins = gpio1_0_to_3_pins,
576 .npins = ARRAY_SIZE(gpio1_0_to_3_pins), 576 .npins = ARRAY_SIZE(gpio1_0_to_3_pins),
577 .modemuxs = gpio1_0_to_3_modemux, 577 .modemuxs = gpio1_0_to_3_modemux,
578 .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux), 578 .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux),
579 }; 579 };
580 580
581 /* gpio1_4_to_7_pins */ 581 /* gpio1_4_to_7_pins */
582 static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 }; 582 static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 };
583 583
584 static struct spear_muxreg gpio1_4_to_7_muxreg[] = { 584 static struct spear_muxreg gpio1_4_to_7_muxreg[] = {
585 { 585 {
586 .reg = PMX_CONFIG_REG, 586 .reg = PMX_CONFIG_REG,
587 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 587 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
588 .val = 0, 588 .val = 0,
589 }, 589 },
590 }; 590 };
591 591
592 static struct spear_modemux gpio1_4_to_7_modemux[] = { 592 static struct spear_modemux gpio1_4_to_7_modemux[] = {
593 { 593 {
594 .modes = PHOTO_FRAME_MODE, 594 .modes = PHOTO_FRAME_MODE,
595 .muxregs = gpio1_4_to_7_muxreg, 595 .muxregs = gpio1_4_to_7_muxreg,
596 .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg), 596 .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg),
597 }, 597 },
598 }; 598 };
599 599
600 static struct spear_pingroup gpio1_4_to_7_pingroup = { 600 static struct spear_pingroup gpio1_4_to_7_pingroup = {
601 .name = "gpio1_4_to_7_grp", 601 .name = "gpio1_4_to_7_grp",
602 .pins = gpio1_4_to_7_pins, 602 .pins = gpio1_4_to_7_pins,
603 .npins = ARRAY_SIZE(gpio1_4_to_7_pins), 603 .npins = ARRAY_SIZE(gpio1_4_to_7_pins),
604 .modemuxs = gpio1_4_to_7_modemux, 604 .modemuxs = gpio1_4_to_7_modemux,
605 .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux), 605 .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux),
606 }; 606 };
607 607
608 static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp" 608 static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
609 }; 609 };
610 static struct spear_function gpio1_function = { 610 static struct spear_function gpio1_function = {
611 .name = "gpio1", 611 .name = "gpio1",
612 .groups = gpio1_grps, 612 .groups = gpio1_grps,
613 .ngroups = ARRAY_SIZE(gpio1_grps), 613 .ngroups = ARRAY_SIZE(gpio1_grps),
614 }; 614 };
615 615
616 /* pingroups */ 616 /* pingroups */
617 static struct spear_pingroup *spear300_pingroups[] = { 617 static struct spear_pingroup *spear300_pingroups[] = {
618 SPEAR3XX_COMMON_PINGROUPS, 618 SPEAR3XX_COMMON_PINGROUPS,
619 &fsmc_2chips_pingroup, 619 &fsmc_2chips_pingroup,
620 &fsmc_4chips_pingroup, 620 &fsmc_4chips_pingroup,
621 &clcd_lcdmode_pingroup, 621 &clcd_lcdmode_pingroup,
622 &clcd_pfmode_pingroup, 622 &clcd_pfmode_pingroup,
623 &tdm_pingroup, 623 &tdm_pingroup,
624 &i2c_clk_pingroup, 624 &i2c_clk_pingroup,
625 &caml_pingroup, 625 &caml_pingroup,
626 &camu_pingroup, 626 &camu_pingroup,
627 &dac_pingroup, 627 &dac_pingroup,
628 &i2s_pingroup, 628 &i2s_pingroup,
629 &sdhci_4bit_pingroup, 629 &sdhci_4bit_pingroup,
630 &sdhci_8bit_pingroup, 630 &sdhci_8bit_pingroup,
631 &gpio1_0_to_3_pingroup, 631 &gpio1_0_to_3_pingroup,
632 &gpio1_4_to_7_pingroup, 632 &gpio1_4_to_7_pingroup,
633 }; 633 };
634 634
635 /* functions */ 635 /* functions */
636 static struct spear_function *spear300_functions[] = { 636 static struct spear_function *spear300_functions[] = {
637 SPEAR3XX_COMMON_FUNCTIONS, 637 SPEAR3XX_COMMON_FUNCTIONS,
638 &fsmc_function, 638 &fsmc_function,
639 &clcd_function, 639 &clcd_function,
640 &tdm_function, 640 &tdm_function,
641 &i2c_function, 641 &i2c_function,
642 &cam_function, 642 &cam_function,
643 &dac_function, 643 &dac_function,
644 &i2s_function, 644 &i2s_function,
645 &sdhci_function, 645 &sdhci_function,
646 &gpio1_function, 646 &gpio1_function,
647 }; 647 };
648 648
649 static struct of_device_id spear300_pinctrl_of_match[] = { 649 static struct of_device_id spear300_pinctrl_of_match[] = {
650 { 650 {
651 .compatible = "st,spear300-pinmux", 651 .compatible = "st,spear300-pinmux",
652 }, 652 },
653 {}, 653 {},
654 }; 654 };
655 655
656 static int __devinit spear300_pinctrl_probe(struct platform_device *pdev) 656 static int __devinit spear300_pinctrl_probe(struct platform_device *pdev)
657 { 657 {
658 int ret; 658 int ret;
659 659
660 spear3xx_machdata.groups = spear300_pingroups; 660 spear3xx_machdata.groups = spear300_pingroups;
661 spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups); 661 spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
662 spear3xx_machdata.functions = spear300_functions; 662 spear3xx_machdata.functions = spear300_functions;
663 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions); 663 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
664 664
665 spear3xx_machdata.modes_supported = true; 665 spear3xx_machdata.modes_supported = true;
666 spear3xx_machdata.pmx_modes = spear300_pmx_modes; 666 spear3xx_machdata.pmx_modes = spear300_pmx_modes;
667 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes); 667 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes);
668 668
669 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); 669 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
670 670
671 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); 671 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
672 if (ret) 672 if (ret)
673 return ret; 673 return ret;
674 674
675 return 0; 675 return 0;
676 } 676 }
677 677
678 static int __devexit spear300_pinctrl_remove(struct platform_device *pdev) 678 static int spear300_pinctrl_remove(struct platform_device *pdev)
679 { 679 {
680 return spear_pinctrl_remove(pdev); 680 return spear_pinctrl_remove(pdev);
681 } 681 }
682 682
683 static struct platform_driver spear300_pinctrl_driver = { 683 static struct platform_driver spear300_pinctrl_driver = {
684 .driver = { 684 .driver = {
685 .name = DRIVER_NAME, 685 .name = DRIVER_NAME,
686 .owner = THIS_MODULE, 686 .owner = THIS_MODULE,
687 .of_match_table = spear300_pinctrl_of_match, 687 .of_match_table = spear300_pinctrl_of_match,
688 }, 688 },
689 .probe = spear300_pinctrl_probe, 689 .probe = spear300_pinctrl_probe,
690 .remove = spear300_pinctrl_remove, 690 .remove = spear300_pinctrl_remove,
691 }; 691 };
692 692
693 static int __init spear300_pinctrl_init(void) 693 static int __init spear300_pinctrl_init(void)
694 { 694 {
695 return platform_driver_register(&spear300_pinctrl_driver); 695 return platform_driver_register(&spear300_pinctrl_driver);
696 } 696 }
697 arch_initcall(spear300_pinctrl_init); 697 arch_initcall(spear300_pinctrl_init);
698 698
699 static void __exit spear300_pinctrl_exit(void) 699 static void __exit spear300_pinctrl_exit(void)
700 { 700 {
701 platform_driver_unregister(&spear300_pinctrl_driver); 701 platform_driver_unregister(&spear300_pinctrl_driver);
702 } 702 }
703 module_exit(spear300_pinctrl_exit); 703 module_exit(spear300_pinctrl_exit);
704 704
705 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); 705 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
706 MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver"); 706 MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver");
707 MODULE_LICENSE("GPL v2"); 707 MODULE_LICENSE("GPL v2");
708 MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match); 708 MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match);
709 709
drivers/pinctrl/spear/pinctrl-spear310.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Driver for the ST Microelectronics SPEAr310 pinmux 2 * Driver for the ST Microelectronics SPEAr310 pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/err.h> 12 #include <linux/err.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/module.h> 14 #include <linux/module.h>
15 #include <linux/of_device.h> 15 #include <linux/of_device.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include "pinctrl-spear3xx.h" 17 #include "pinctrl-spear3xx.h"
18 18
19 #define DRIVER_NAME "spear310-pinmux" 19 #define DRIVER_NAME "spear310-pinmux"
20 20
21 /* addresses */ 21 /* addresses */
22 #define PMX_CONFIG_REG 0x08 22 #define PMX_CONFIG_REG 0x08
23 23
24 /* emi_cs_0_to_5_pins */ 24 /* emi_cs_0_to_5_pins */
25 static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 }; 25 static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
26 static struct spear_muxreg emi_cs_0_to_5_muxreg[] = { 26 static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
27 { 27 {
28 .reg = PMX_CONFIG_REG, 28 .reg = PMX_CONFIG_REG,
29 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 29 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
30 .val = 0, 30 .val = 0,
31 }, 31 },
32 }; 32 };
33 33
34 static struct spear_modemux emi_cs_0_to_5_modemux[] = { 34 static struct spear_modemux emi_cs_0_to_5_modemux[] = {
35 { 35 {
36 .muxregs = emi_cs_0_to_5_muxreg, 36 .muxregs = emi_cs_0_to_5_muxreg,
37 .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg), 37 .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
38 }, 38 },
39 }; 39 };
40 40
41 static struct spear_pingroup emi_cs_0_to_5_pingroup = { 41 static struct spear_pingroup emi_cs_0_to_5_pingroup = {
42 .name = "emi_cs_0_to_5_grp", 42 .name = "emi_cs_0_to_5_grp",
43 .pins = emi_cs_0_to_5_pins, 43 .pins = emi_cs_0_to_5_pins,
44 .npins = ARRAY_SIZE(emi_cs_0_to_5_pins), 44 .npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
45 .modemuxs = emi_cs_0_to_5_modemux, 45 .modemuxs = emi_cs_0_to_5_modemux,
46 .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux), 46 .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
47 }; 47 };
48 48
49 static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" }; 49 static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
50 static struct spear_function emi_cs_0_to_5_function = { 50 static struct spear_function emi_cs_0_to_5_function = {
51 .name = "emi", 51 .name = "emi",
52 .groups = emi_cs_0_to_5_grps, 52 .groups = emi_cs_0_to_5_grps,
53 .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps), 53 .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
54 }; 54 };
55 55
56 /* uart1_pins */ 56 /* uart1_pins */
57 static const unsigned uart1_pins[] = { 0, 1 }; 57 static const unsigned uart1_pins[] = { 0, 1 };
58 static struct spear_muxreg uart1_muxreg[] = { 58 static struct spear_muxreg uart1_muxreg[] = {
59 { 59 {
60 .reg = PMX_CONFIG_REG, 60 .reg = PMX_CONFIG_REG,
61 .mask = PMX_FIRDA_MASK, 61 .mask = PMX_FIRDA_MASK,
62 .val = 0, 62 .val = 0,
63 }, 63 },
64 }; 64 };
65 65
66 static struct spear_modemux uart1_modemux[] = { 66 static struct spear_modemux uart1_modemux[] = {
67 { 67 {
68 .muxregs = uart1_muxreg, 68 .muxregs = uart1_muxreg,
69 .nmuxregs = ARRAY_SIZE(uart1_muxreg), 69 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
70 }, 70 },
71 }; 71 };
72 72
73 static struct spear_pingroup uart1_pingroup = { 73 static struct spear_pingroup uart1_pingroup = {
74 .name = "uart1_grp", 74 .name = "uart1_grp",
75 .pins = uart1_pins, 75 .pins = uart1_pins,
76 .npins = ARRAY_SIZE(uart1_pins), 76 .npins = ARRAY_SIZE(uart1_pins),
77 .modemuxs = uart1_modemux, 77 .modemuxs = uart1_modemux,
78 .nmodemuxs = ARRAY_SIZE(uart1_modemux), 78 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
79 }; 79 };
80 80
81 static const char *const uart1_grps[] = { "uart1_grp" }; 81 static const char *const uart1_grps[] = { "uart1_grp" };
82 static struct spear_function uart1_function = { 82 static struct spear_function uart1_function = {
83 .name = "uart1", 83 .name = "uart1",
84 .groups = uart1_grps, 84 .groups = uart1_grps,
85 .ngroups = ARRAY_SIZE(uart1_grps), 85 .ngroups = ARRAY_SIZE(uart1_grps),
86 }; 86 };
87 87
88 /* uart2_pins */ 88 /* uart2_pins */
89 static const unsigned uart2_pins[] = { 43, 44 }; 89 static const unsigned uart2_pins[] = { 43, 44 };
90 static struct spear_muxreg uart2_muxreg[] = { 90 static struct spear_muxreg uart2_muxreg[] = {
91 { 91 {
92 .reg = PMX_CONFIG_REG, 92 .reg = PMX_CONFIG_REG,
93 .mask = PMX_TIMER_0_1_MASK, 93 .mask = PMX_TIMER_0_1_MASK,
94 .val = 0, 94 .val = 0,
95 }, 95 },
96 }; 96 };
97 97
98 static struct spear_modemux uart2_modemux[] = { 98 static struct spear_modemux uart2_modemux[] = {
99 { 99 {
100 .muxregs = uart2_muxreg, 100 .muxregs = uart2_muxreg,
101 .nmuxregs = ARRAY_SIZE(uart2_muxreg), 101 .nmuxregs = ARRAY_SIZE(uart2_muxreg),
102 }, 102 },
103 }; 103 };
104 104
105 static struct spear_pingroup uart2_pingroup = { 105 static struct spear_pingroup uart2_pingroup = {
106 .name = "uart2_grp", 106 .name = "uart2_grp",
107 .pins = uart2_pins, 107 .pins = uart2_pins,
108 .npins = ARRAY_SIZE(uart2_pins), 108 .npins = ARRAY_SIZE(uart2_pins),
109 .modemuxs = uart2_modemux, 109 .modemuxs = uart2_modemux,
110 .nmodemuxs = ARRAY_SIZE(uart2_modemux), 110 .nmodemuxs = ARRAY_SIZE(uart2_modemux),
111 }; 111 };
112 112
113 static const char *const uart2_grps[] = { "uart2_grp" }; 113 static const char *const uart2_grps[] = { "uart2_grp" };
114 static struct spear_function uart2_function = { 114 static struct spear_function uart2_function = {
115 .name = "uart2", 115 .name = "uart2",
116 .groups = uart2_grps, 116 .groups = uart2_grps,
117 .ngroups = ARRAY_SIZE(uart2_grps), 117 .ngroups = ARRAY_SIZE(uart2_grps),
118 }; 118 };
119 119
120 /* uart3_pins */ 120 /* uart3_pins */
121 static const unsigned uart3_pins[] = { 37, 38 }; 121 static const unsigned uart3_pins[] = { 37, 38 };
122 static struct spear_muxreg uart3_muxreg[] = { 122 static struct spear_muxreg uart3_muxreg[] = {
123 { 123 {
124 .reg = PMX_CONFIG_REG, 124 .reg = PMX_CONFIG_REG,
125 .mask = PMX_UART0_MODEM_MASK, 125 .mask = PMX_UART0_MODEM_MASK,
126 .val = 0, 126 .val = 0,
127 }, 127 },
128 }; 128 };
129 129
130 static struct spear_modemux uart3_modemux[] = { 130 static struct spear_modemux uart3_modemux[] = {
131 { 131 {
132 .muxregs = uart3_muxreg, 132 .muxregs = uart3_muxreg,
133 .nmuxregs = ARRAY_SIZE(uart3_muxreg), 133 .nmuxregs = ARRAY_SIZE(uart3_muxreg),
134 }, 134 },
135 }; 135 };
136 136
137 static struct spear_pingroup uart3_pingroup = { 137 static struct spear_pingroup uart3_pingroup = {
138 .name = "uart3_grp", 138 .name = "uart3_grp",
139 .pins = uart3_pins, 139 .pins = uart3_pins,
140 .npins = ARRAY_SIZE(uart3_pins), 140 .npins = ARRAY_SIZE(uart3_pins),
141 .modemuxs = uart3_modemux, 141 .modemuxs = uart3_modemux,
142 .nmodemuxs = ARRAY_SIZE(uart3_modemux), 142 .nmodemuxs = ARRAY_SIZE(uart3_modemux),
143 }; 143 };
144 144
145 static const char *const uart3_grps[] = { "uart3_grp" }; 145 static const char *const uart3_grps[] = { "uart3_grp" };
146 static struct spear_function uart3_function = { 146 static struct spear_function uart3_function = {
147 .name = "uart3", 147 .name = "uart3",
148 .groups = uart3_grps, 148 .groups = uart3_grps,
149 .ngroups = ARRAY_SIZE(uart3_grps), 149 .ngroups = ARRAY_SIZE(uart3_grps),
150 }; 150 };
151 151
152 /* uart4_pins */ 152 /* uart4_pins */
153 static const unsigned uart4_pins[] = { 39, 40 }; 153 static const unsigned uart4_pins[] = { 39, 40 };
154 static struct spear_muxreg uart4_muxreg[] = { 154 static struct spear_muxreg uart4_muxreg[] = {
155 { 155 {
156 .reg = PMX_CONFIG_REG, 156 .reg = PMX_CONFIG_REG,
157 .mask = PMX_UART0_MODEM_MASK, 157 .mask = PMX_UART0_MODEM_MASK,
158 .val = 0, 158 .val = 0,
159 }, 159 },
160 }; 160 };
161 161
162 static struct spear_modemux uart4_modemux[] = { 162 static struct spear_modemux uart4_modemux[] = {
163 { 163 {
164 .muxregs = uart4_muxreg, 164 .muxregs = uart4_muxreg,
165 .nmuxregs = ARRAY_SIZE(uart4_muxreg), 165 .nmuxregs = ARRAY_SIZE(uart4_muxreg),
166 }, 166 },
167 }; 167 };
168 168
169 static struct spear_pingroup uart4_pingroup = { 169 static struct spear_pingroup uart4_pingroup = {
170 .name = "uart4_grp", 170 .name = "uart4_grp",
171 .pins = uart4_pins, 171 .pins = uart4_pins,
172 .npins = ARRAY_SIZE(uart4_pins), 172 .npins = ARRAY_SIZE(uart4_pins),
173 .modemuxs = uart4_modemux, 173 .modemuxs = uart4_modemux,
174 .nmodemuxs = ARRAY_SIZE(uart4_modemux), 174 .nmodemuxs = ARRAY_SIZE(uart4_modemux),
175 }; 175 };
176 176
177 static const char *const uart4_grps[] = { "uart4_grp" }; 177 static const char *const uart4_grps[] = { "uart4_grp" };
178 static struct spear_function uart4_function = { 178 static struct spear_function uart4_function = {
179 .name = "uart4", 179 .name = "uart4",
180 .groups = uart4_grps, 180 .groups = uart4_grps,
181 .ngroups = ARRAY_SIZE(uart4_grps), 181 .ngroups = ARRAY_SIZE(uart4_grps),
182 }; 182 };
183 183
184 /* uart5_pins */ 184 /* uart5_pins */
185 static const unsigned uart5_pins[] = { 41, 42 }; 185 static const unsigned uart5_pins[] = { 41, 42 };
186 static struct spear_muxreg uart5_muxreg[] = { 186 static struct spear_muxreg uart5_muxreg[] = {
187 { 187 {
188 .reg = PMX_CONFIG_REG, 188 .reg = PMX_CONFIG_REG,
189 .mask = PMX_UART0_MODEM_MASK, 189 .mask = PMX_UART0_MODEM_MASK,
190 .val = 0, 190 .val = 0,
191 }, 191 },
192 }; 192 };
193 193
194 static struct spear_modemux uart5_modemux[] = { 194 static struct spear_modemux uart5_modemux[] = {
195 { 195 {
196 .muxregs = uart5_muxreg, 196 .muxregs = uart5_muxreg,
197 .nmuxregs = ARRAY_SIZE(uart5_muxreg), 197 .nmuxregs = ARRAY_SIZE(uart5_muxreg),
198 }, 198 },
199 }; 199 };
200 200
201 static struct spear_pingroup uart5_pingroup = { 201 static struct spear_pingroup uart5_pingroup = {
202 .name = "uart5_grp", 202 .name = "uart5_grp",
203 .pins = uart5_pins, 203 .pins = uart5_pins,
204 .npins = ARRAY_SIZE(uart5_pins), 204 .npins = ARRAY_SIZE(uart5_pins),
205 .modemuxs = uart5_modemux, 205 .modemuxs = uart5_modemux,
206 .nmodemuxs = ARRAY_SIZE(uart5_modemux), 206 .nmodemuxs = ARRAY_SIZE(uart5_modemux),
207 }; 207 };
208 208
209 static const char *const uart5_grps[] = { "uart5_grp" }; 209 static const char *const uart5_grps[] = { "uart5_grp" };
210 static struct spear_function uart5_function = { 210 static struct spear_function uart5_function = {
211 .name = "uart5", 211 .name = "uart5",
212 .groups = uart5_grps, 212 .groups = uart5_grps,
213 .ngroups = ARRAY_SIZE(uart5_grps), 213 .ngroups = ARRAY_SIZE(uart5_grps),
214 }; 214 };
215 215
216 /* fsmc_pins */ 216 /* fsmc_pins */
217 static const unsigned fsmc_pins[] = { 34, 35, 36 }; 217 static const unsigned fsmc_pins[] = { 34, 35, 36 };
218 static struct spear_muxreg fsmc_muxreg[] = { 218 static struct spear_muxreg fsmc_muxreg[] = {
219 { 219 {
220 .reg = PMX_CONFIG_REG, 220 .reg = PMX_CONFIG_REG,
221 .mask = PMX_SSP_CS_MASK, 221 .mask = PMX_SSP_CS_MASK,
222 .val = 0, 222 .val = 0,
223 }, 223 },
224 }; 224 };
225 225
226 static struct spear_modemux fsmc_modemux[] = { 226 static struct spear_modemux fsmc_modemux[] = {
227 { 227 {
228 .muxregs = fsmc_muxreg, 228 .muxregs = fsmc_muxreg,
229 .nmuxregs = ARRAY_SIZE(fsmc_muxreg), 229 .nmuxregs = ARRAY_SIZE(fsmc_muxreg),
230 }, 230 },
231 }; 231 };
232 232
233 static struct spear_pingroup fsmc_pingroup = { 233 static struct spear_pingroup fsmc_pingroup = {
234 .name = "fsmc_grp", 234 .name = "fsmc_grp",
235 .pins = fsmc_pins, 235 .pins = fsmc_pins,
236 .npins = ARRAY_SIZE(fsmc_pins), 236 .npins = ARRAY_SIZE(fsmc_pins),
237 .modemuxs = fsmc_modemux, 237 .modemuxs = fsmc_modemux,
238 .nmodemuxs = ARRAY_SIZE(fsmc_modemux), 238 .nmodemuxs = ARRAY_SIZE(fsmc_modemux),
239 }; 239 };
240 240
241 static const char *const fsmc_grps[] = { "fsmc_grp" }; 241 static const char *const fsmc_grps[] = { "fsmc_grp" };
242 static struct spear_function fsmc_function = { 242 static struct spear_function fsmc_function = {
243 .name = "fsmc", 243 .name = "fsmc",
244 .groups = fsmc_grps, 244 .groups = fsmc_grps,
245 .ngroups = ARRAY_SIZE(fsmc_grps), 245 .ngroups = ARRAY_SIZE(fsmc_grps),
246 }; 246 };
247 247
248 /* rs485_0_pins */ 248 /* rs485_0_pins */
249 static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 }; 249 static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
250 static struct spear_muxreg rs485_0_muxreg[] = { 250 static struct spear_muxreg rs485_0_muxreg[] = {
251 { 251 {
252 .reg = PMX_CONFIG_REG, 252 .reg = PMX_CONFIG_REG,
253 .mask = PMX_MII_MASK, 253 .mask = PMX_MII_MASK,
254 .val = 0, 254 .val = 0,
255 }, 255 },
256 }; 256 };
257 257
258 static struct spear_modemux rs485_0_modemux[] = { 258 static struct spear_modemux rs485_0_modemux[] = {
259 { 259 {
260 .muxregs = rs485_0_muxreg, 260 .muxregs = rs485_0_muxreg,
261 .nmuxregs = ARRAY_SIZE(rs485_0_muxreg), 261 .nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
262 }, 262 },
263 }; 263 };
264 264
265 static struct spear_pingroup rs485_0_pingroup = { 265 static struct spear_pingroup rs485_0_pingroup = {
266 .name = "rs485_0_grp", 266 .name = "rs485_0_grp",
267 .pins = rs485_0_pins, 267 .pins = rs485_0_pins,
268 .npins = ARRAY_SIZE(rs485_0_pins), 268 .npins = ARRAY_SIZE(rs485_0_pins),
269 .modemuxs = rs485_0_modemux, 269 .modemuxs = rs485_0_modemux,
270 .nmodemuxs = ARRAY_SIZE(rs485_0_modemux), 270 .nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
271 }; 271 };
272 272
273 static const char *const rs485_0_grps[] = { "rs485_0" }; 273 static const char *const rs485_0_grps[] = { "rs485_0" };
274 static struct spear_function rs485_0_function = { 274 static struct spear_function rs485_0_function = {
275 .name = "rs485_0", 275 .name = "rs485_0",
276 .groups = rs485_0_grps, 276 .groups = rs485_0_grps,
277 .ngroups = ARRAY_SIZE(rs485_0_grps), 277 .ngroups = ARRAY_SIZE(rs485_0_grps),
278 }; 278 };
279 279
280 /* rs485_1_pins */ 280 /* rs485_1_pins */
281 static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 }; 281 static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
282 static struct spear_muxreg rs485_1_muxreg[] = { 282 static struct spear_muxreg rs485_1_muxreg[] = {
283 { 283 {
284 .reg = PMX_CONFIG_REG, 284 .reg = PMX_CONFIG_REG,
285 .mask = PMX_MII_MASK, 285 .mask = PMX_MII_MASK,
286 .val = 0, 286 .val = 0,
287 }, 287 },
288 }; 288 };
289 289
290 static struct spear_modemux rs485_1_modemux[] = { 290 static struct spear_modemux rs485_1_modemux[] = {
291 { 291 {
292 .muxregs = rs485_1_muxreg, 292 .muxregs = rs485_1_muxreg,
293 .nmuxregs = ARRAY_SIZE(rs485_1_muxreg), 293 .nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
294 }, 294 },
295 }; 295 };
296 296
297 static struct spear_pingroup rs485_1_pingroup = { 297 static struct spear_pingroup rs485_1_pingroup = {
298 .name = "rs485_1_grp", 298 .name = "rs485_1_grp",
299 .pins = rs485_1_pins, 299 .pins = rs485_1_pins,
300 .npins = ARRAY_SIZE(rs485_1_pins), 300 .npins = ARRAY_SIZE(rs485_1_pins),
301 .modemuxs = rs485_1_modemux, 301 .modemuxs = rs485_1_modemux,
302 .nmodemuxs = ARRAY_SIZE(rs485_1_modemux), 302 .nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
303 }; 303 };
304 304
305 static const char *const rs485_1_grps[] = { "rs485_1" }; 305 static const char *const rs485_1_grps[] = { "rs485_1" };
306 static struct spear_function rs485_1_function = { 306 static struct spear_function rs485_1_function = {
307 .name = "rs485_1", 307 .name = "rs485_1",
308 .groups = rs485_1_grps, 308 .groups = rs485_1_grps,
309 .ngroups = ARRAY_SIZE(rs485_1_grps), 309 .ngroups = ARRAY_SIZE(rs485_1_grps),
310 }; 310 };
311 311
312 /* tdm_pins */ 312 /* tdm_pins */
313 static const unsigned tdm_pins[] = { 10, 11, 12, 13 }; 313 static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
314 static struct spear_muxreg tdm_muxreg[] = { 314 static struct spear_muxreg tdm_muxreg[] = {
315 { 315 {
316 .reg = PMX_CONFIG_REG, 316 .reg = PMX_CONFIG_REG,
317 .mask = PMX_MII_MASK, 317 .mask = PMX_MII_MASK,
318 .val = 0, 318 .val = 0,
319 }, 319 },
320 }; 320 };
321 321
322 static struct spear_modemux tdm_modemux[] = { 322 static struct spear_modemux tdm_modemux[] = {
323 { 323 {
324 .muxregs = tdm_muxreg, 324 .muxregs = tdm_muxreg,
325 .nmuxregs = ARRAY_SIZE(tdm_muxreg), 325 .nmuxregs = ARRAY_SIZE(tdm_muxreg),
326 }, 326 },
327 }; 327 };
328 328
329 static struct spear_pingroup tdm_pingroup = { 329 static struct spear_pingroup tdm_pingroup = {
330 .name = "tdm_grp", 330 .name = "tdm_grp",
331 .pins = tdm_pins, 331 .pins = tdm_pins,
332 .npins = ARRAY_SIZE(tdm_pins), 332 .npins = ARRAY_SIZE(tdm_pins),
333 .modemuxs = tdm_modemux, 333 .modemuxs = tdm_modemux,
334 .nmodemuxs = ARRAY_SIZE(tdm_modemux), 334 .nmodemuxs = ARRAY_SIZE(tdm_modemux),
335 }; 335 };
336 336
337 static const char *const tdm_grps[] = { "tdm_grp" }; 337 static const char *const tdm_grps[] = { "tdm_grp" };
338 static struct spear_function tdm_function = { 338 static struct spear_function tdm_function = {
339 .name = "tdm", 339 .name = "tdm",
340 .groups = tdm_grps, 340 .groups = tdm_grps,
341 .ngroups = ARRAY_SIZE(tdm_grps), 341 .ngroups = ARRAY_SIZE(tdm_grps),
342 }; 342 };
343 343
344 /* pingroups */ 344 /* pingroups */
345 static struct spear_pingroup *spear310_pingroups[] = { 345 static struct spear_pingroup *spear310_pingroups[] = {
346 SPEAR3XX_COMMON_PINGROUPS, 346 SPEAR3XX_COMMON_PINGROUPS,
347 &emi_cs_0_to_5_pingroup, 347 &emi_cs_0_to_5_pingroup,
348 &uart1_pingroup, 348 &uart1_pingroup,
349 &uart2_pingroup, 349 &uart2_pingroup,
350 &uart3_pingroup, 350 &uart3_pingroup,
351 &uart4_pingroup, 351 &uart4_pingroup,
352 &uart5_pingroup, 352 &uart5_pingroup,
353 &fsmc_pingroup, 353 &fsmc_pingroup,
354 &rs485_0_pingroup, 354 &rs485_0_pingroup,
355 &rs485_1_pingroup, 355 &rs485_1_pingroup,
356 &tdm_pingroup, 356 &tdm_pingroup,
357 }; 357 };
358 358
359 /* functions */ 359 /* functions */
360 static struct spear_function *spear310_functions[] = { 360 static struct spear_function *spear310_functions[] = {
361 SPEAR3XX_COMMON_FUNCTIONS, 361 SPEAR3XX_COMMON_FUNCTIONS,
362 &emi_cs_0_to_5_function, 362 &emi_cs_0_to_5_function,
363 &uart1_function, 363 &uart1_function,
364 &uart2_function, 364 &uart2_function,
365 &uart3_function, 365 &uart3_function,
366 &uart4_function, 366 &uart4_function,
367 &uart5_function, 367 &uart5_function,
368 &fsmc_function, 368 &fsmc_function,
369 &rs485_0_function, 369 &rs485_0_function,
370 &rs485_1_function, 370 &rs485_1_function,
371 &tdm_function, 371 &tdm_function,
372 }; 372 };
373 373
374 static struct of_device_id spear310_pinctrl_of_match[] = { 374 static struct of_device_id spear310_pinctrl_of_match[] = {
375 { 375 {
376 .compatible = "st,spear310-pinmux", 376 .compatible = "st,spear310-pinmux",
377 }, 377 },
378 {}, 378 {},
379 }; 379 };
380 380
381 static int __devinit spear310_pinctrl_probe(struct platform_device *pdev) 381 static int __devinit spear310_pinctrl_probe(struct platform_device *pdev)
382 { 382 {
383 int ret; 383 int ret;
384 384
385 spear3xx_machdata.groups = spear310_pingroups; 385 spear3xx_machdata.groups = spear310_pingroups;
386 spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups); 386 spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
387 spear3xx_machdata.functions = spear310_functions; 387 spear3xx_machdata.functions = spear310_functions;
388 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions); 388 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
389 389
390 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); 390 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
391 391
392 spear3xx_machdata.modes_supported = false; 392 spear3xx_machdata.modes_supported = false;
393 393
394 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); 394 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
395 if (ret) 395 if (ret)
396 return ret; 396 return ret;
397 397
398 return 0; 398 return 0;
399 } 399 }
400 400
401 static int __devexit spear310_pinctrl_remove(struct platform_device *pdev) 401 static int spear310_pinctrl_remove(struct platform_device *pdev)
402 { 402 {
403 return spear_pinctrl_remove(pdev); 403 return spear_pinctrl_remove(pdev);
404 } 404 }
405 405
406 static struct platform_driver spear310_pinctrl_driver = { 406 static struct platform_driver spear310_pinctrl_driver = {
407 .driver = { 407 .driver = {
408 .name = DRIVER_NAME, 408 .name = DRIVER_NAME,
409 .owner = THIS_MODULE, 409 .owner = THIS_MODULE,
410 .of_match_table = spear310_pinctrl_of_match, 410 .of_match_table = spear310_pinctrl_of_match,
411 }, 411 },
412 .probe = spear310_pinctrl_probe, 412 .probe = spear310_pinctrl_probe,
413 .remove = spear310_pinctrl_remove, 413 .remove = spear310_pinctrl_remove,
414 }; 414 };
415 415
416 static int __init spear310_pinctrl_init(void) 416 static int __init spear310_pinctrl_init(void)
417 { 417 {
418 return platform_driver_register(&spear310_pinctrl_driver); 418 return platform_driver_register(&spear310_pinctrl_driver);
419 } 419 }
420 arch_initcall(spear310_pinctrl_init); 420 arch_initcall(spear310_pinctrl_init);
421 421
422 static void __exit spear310_pinctrl_exit(void) 422 static void __exit spear310_pinctrl_exit(void)
423 { 423 {
424 platform_driver_unregister(&spear310_pinctrl_driver); 424 platform_driver_unregister(&spear310_pinctrl_driver);
425 } 425 }
426 module_exit(spear310_pinctrl_exit); 426 module_exit(spear310_pinctrl_exit);
427 427
428 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); 428 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
429 MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver"); 429 MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver");
430 MODULE_LICENSE("GPL v2"); 430 MODULE_LICENSE("GPL v2");
431 MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match); 431 MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match);
432 432
drivers/pinctrl/spear/pinctrl-spear320.c
Diff comments   View file @ f90f54b
1 /* 1 /*
2 * Driver for the ST Microelectronics SPEAr320 pinmux 2 * Driver for the ST Microelectronics SPEAr320 pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/err.h> 12 #include <linux/err.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/module.h> 14 #include <linux/module.h>
15 #include <linux/of_device.h> 15 #include <linux/of_device.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include "pinctrl-spear3xx.h" 17 #include "pinctrl-spear3xx.h"
18 18
19 #define DRIVER_NAME "spear320-pinmux" 19 #define DRIVER_NAME "spear320-pinmux"
20 20
21 /* addresses */ 21 /* addresses */
22 #define PMX_CONFIG_REG 0x0C 22 #define PMX_CONFIG_REG 0x0C
23 #define MODE_CONFIG_REG 0x10 23 #define MODE_CONFIG_REG 0x10
24 #define MODE_EXT_CONFIG_REG 0x18 24 #define MODE_EXT_CONFIG_REG 0x18
25 25
26 /* modes */ 26 /* modes */
27 #define AUTO_NET_SMII_MODE (1 << 0) 27 #define AUTO_NET_SMII_MODE (1 << 0)
28 #define AUTO_NET_MII_MODE (1 << 1) 28 #define AUTO_NET_MII_MODE (1 << 1)
29 #define AUTO_EXP_MODE (1 << 2) 29 #define AUTO_EXP_MODE (1 << 2)
30 #define SMALL_PRINTERS_MODE (1 << 3) 30 #define SMALL_PRINTERS_MODE (1 << 3)
31 #define EXTENDED_MODE (1 << 4) 31 #define EXTENDED_MODE (1 << 4)
32 32
33 static struct spear_pmx_mode pmx_mode_auto_net_smii = { 33 static struct spear_pmx_mode pmx_mode_auto_net_smii = {
34 .name = "Automation Networking SMII mode", 34 .name = "Automation Networking SMII mode",
35 .mode = AUTO_NET_SMII_MODE, 35 .mode = AUTO_NET_SMII_MODE,
36 .reg = MODE_CONFIG_REG, 36 .reg = MODE_CONFIG_REG,
37 .mask = 0x00000007, 37 .mask = 0x00000007,
38 .val = 0x0, 38 .val = 0x0,
39 }; 39 };
40 40
41 static struct spear_pmx_mode pmx_mode_auto_net_mii = { 41 static struct spear_pmx_mode pmx_mode_auto_net_mii = {
42 .name = "Automation Networking MII mode", 42 .name = "Automation Networking MII mode",
43 .mode = AUTO_NET_MII_MODE, 43 .mode = AUTO_NET_MII_MODE,
44 .reg = MODE_CONFIG_REG, 44 .reg = MODE_CONFIG_REG,
45 .mask = 0x00000007, 45 .mask = 0x00000007,
46 .val = 0x1, 46 .val = 0x1,
47 }; 47 };
48 48
49 static struct spear_pmx_mode pmx_mode_auto_exp = { 49 static struct spear_pmx_mode pmx_mode_auto_exp = {
50 .name = "Automation Expanded mode", 50 .name = "Automation Expanded mode",
51 .mode = AUTO_EXP_MODE, 51 .mode = AUTO_EXP_MODE,
52 .reg = MODE_CONFIG_REG, 52 .reg = MODE_CONFIG_REG,
53 .mask = 0x00000007, 53 .mask = 0x00000007,
54 .val = 0x2, 54 .val = 0x2,
55 }; 55 };
56 56
57 static struct spear_pmx_mode pmx_mode_small_printers = { 57 static struct spear_pmx_mode pmx_mode_small_printers = {
58 .name = "Small Printers mode", 58 .name = "Small Printers mode",
59 .mode = SMALL_PRINTERS_MODE, 59 .mode = SMALL_PRINTERS_MODE,
60 .reg = MODE_CONFIG_REG, 60 .reg = MODE_CONFIG_REG,
61 .mask = 0x00000007, 61 .mask = 0x00000007,
62 .val = 0x3, 62 .val = 0x3,
63 }; 63 };
64 64
65 static struct spear_pmx_mode pmx_mode_extended = { 65 static struct spear_pmx_mode pmx_mode_extended = {
66 .name = "extended mode", 66 .name = "extended mode",
67 .mode = EXTENDED_MODE, 67 .mode = EXTENDED_MODE,
68 .reg = MODE_EXT_CONFIG_REG, 68 .reg = MODE_EXT_CONFIG_REG,
69 .mask = 0x00000001, 69 .mask = 0x00000001,
70 .val = 0x1, 70 .val = 0x1,
71 }; 71 };
72 72
73 static struct spear_pmx_mode *spear320_pmx_modes[] = { 73 static struct spear_pmx_mode *spear320_pmx_modes[] = {
74 &pmx_mode_auto_net_smii, 74 &pmx_mode_auto_net_smii,
75 &pmx_mode_auto_net_mii, 75 &pmx_mode_auto_net_mii,
76 &pmx_mode_auto_exp, 76 &pmx_mode_auto_exp,
77 &pmx_mode_small_printers, 77 &pmx_mode_small_printers,
78 &pmx_mode_extended, 78 &pmx_mode_extended,
79 }; 79 };
80 80
81 /* Extended mode registers and their offsets */ 81 /* Extended mode registers and their offsets */
82 #define EXT_CTRL_REG 0x0018 82 #define EXT_CTRL_REG 0x0018
83 #define MII_MDIO_MASK (1 << 4) 83 #define MII_MDIO_MASK (1 << 4)
84 #define MII_MDIO_10_11_VAL 0 84 #define MII_MDIO_10_11_VAL 0
85 #define MII_MDIO_81_VAL (1 << 4) 85 #define MII_MDIO_81_VAL (1 << 4)
86 #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5) 86 #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5)
87 #define MAC_MODE_MII 0 87 #define MAC_MODE_MII 0
88 #define MAC_MODE_RMII 1 88 #define MAC_MODE_RMII 1
89 #define MAC_MODE_SMII 2 89 #define MAC_MODE_SMII 2
90 #define MAC_MODE_SS_SMII 3 90 #define MAC_MODE_SS_SMII 3
91 #define MAC_MODE_MASK 0x3 91 #define MAC_MODE_MASK 0x3
92 #define MAC1_MODE_SHIFT 16 92 #define MAC1_MODE_SHIFT 16
93 #define MAC2_MODE_SHIFT 18 93 #define MAC2_MODE_SHIFT 18
94 94
95 #define IP_SEL_PAD_0_9_REG 0x00A4 95 #define IP_SEL_PAD_0_9_REG 0x00A4
96 #define PMX_PL_0_1_MASK (0x3F << 0) 96 #define PMX_PL_0_1_MASK (0x3F << 0)
97 #define PMX_UART2_PL_0_1_VAL 0x0 97 #define PMX_UART2_PL_0_1_VAL 0x0
98 #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3)) 98 #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3))
99 99
100 #define PMX_PL_2_3_MASK (0x3F << 6) 100 #define PMX_PL_2_3_MASK (0x3F << 6)
101 #define PMX_I2C2_PL_2_3_VAL 0x0 101 #define PMX_I2C2_PL_2_3_VAL 0x0
102 #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9)) 102 #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9))
103 #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9)) 103 #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9))
104 104
105 #define PMX_PL_4_5_MASK (0x3F << 12) 105 #define PMX_PL_4_5_MASK (0x3F << 12)
106 #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15)) 106 #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15))
107 #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15)) 107 #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15))
108 #define PMX_PL_5_MASK (0x7 << 15) 108 #define PMX_PL_5_MASK (0x7 << 15)
109 #define PMX_TOUCH_Y_PL_5_VAL 0x0 109 #define PMX_TOUCH_Y_PL_5_VAL 0x0
110 110
111 #define PMX_PL_6_7_MASK (0x3F << 18) 111 #define PMX_PL_6_7_MASK (0x3F << 18)
112 #define PMX_PL_6_MASK (0x7 << 18) 112 #define PMX_PL_6_MASK (0x7 << 18)
113 #define PMX_PL_7_MASK (0x7 << 21) 113 #define PMX_PL_7_MASK (0x7 << 21)
114 #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21)) 114 #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21))
115 #define PMX_PWM_3_PL_6_VAL (0x2 << 18) 115 #define PMX_PWM_3_PL_6_VAL (0x2 << 18)
116 #define PMX_PWM_2_PL_7_VAL (0x2 << 21) 116 #define PMX_PWM_2_PL_7_VAL (0x2 << 21)
117 #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21)) 117 #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21))
118 118
119 #define PMX_PL_8_9_MASK (0x3F << 24) 119 #define PMX_PL_8_9_MASK (0x3F << 24)
120 #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27)) 120 #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27))
121 #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27)) 121 #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
122 #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27)) 122 #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27))
123 123
124 #define IP_SEL_PAD_10_19_REG 0x00A8 124 #define IP_SEL_PAD_10_19_REG 0x00A8
125 #define PMX_PL_10_11_MASK (0x3F << 0) 125 #define PMX_PL_10_11_MASK (0x3F << 0)
126 #define PMX_SMII_PL_10_11_VAL 0 126 #define PMX_SMII_PL_10_11_VAL 0
127 #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3)) 127 #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3))
128 128
129 #define PMX_PL_12_MASK (0x7 << 6) 129 #define PMX_PL_12_MASK (0x7 << 6)
130 #define PMX_PWM3_PL_12_VAL 0 130 #define PMX_PWM3_PL_12_VAL 0
131 #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6) 131 #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6)
132 132
133 #define PMX_PL_13_14_MASK (0x3F << 9) 133 #define PMX_PL_13_14_MASK (0x3F << 9)
134 #define PMX_PL_13_MASK (0x7 << 9) 134 #define PMX_PL_13_MASK (0x7 << 9)
135 #define PMX_PL_14_MASK (0x7 << 12) 135 #define PMX_PL_14_MASK (0x7 << 12)
136 #define PMX_SSP2_PL_13_14_15_16_VAL 0 136 #define PMX_SSP2_PL_13_14_15_16_VAL 0
137 #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12)) 137 #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12))
138 #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12)) 138 #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12))
139 #define PMX_PWM2_PL_13_VAL (0x2 << 9) 139 #define PMX_PWM2_PL_13_VAL (0x2 << 9)
140 #define PMX_PWM1_PL_14_VAL (0x2 << 12) 140 #define PMX_PWM1_PL_14_VAL (0x2 << 12)
141 141
142 #define PMX_PL_15_MASK (0x7 << 15) 142 #define PMX_PL_15_MASK (0x7 << 15)
143 #define PMX_PWM0_PL_15_VAL (0x2 << 15) 143 #define PMX_PWM0_PL_15_VAL (0x2 << 15)
144 #define PMX_PL_15_16_MASK (0x3F << 15) 144 #define PMX_PL_15_16_MASK (0x3F << 15)
145 #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18)) 145 #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18))
146 #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18)) 146 #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18))
147 147
148 #define PMX_PL_17_18_MASK (0x3F << 21) 148 #define PMX_PL_17_18_MASK (0x3F << 21)
149 #define PMX_SSP1_PL_17_18_19_20_VAL 0 149 #define PMX_SSP1_PL_17_18_19_20_VAL 0
150 #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24)) 150 #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24))
151 151
152 #define PMX_PL_19_MASK (0x7 << 27) 152 #define PMX_PL_19_MASK (0x7 << 27)
153 #define PMX_I2C2_PL_19_VAL (0x1 << 27) 153 #define PMX_I2C2_PL_19_VAL (0x1 << 27)
154 #define PMX_RMII_PL_19_VAL (0x4 << 27) 154 #define PMX_RMII_PL_19_VAL (0x4 << 27)
155 155
156 #define IP_SEL_PAD_20_29_REG 0x00AC 156 #define IP_SEL_PAD_20_29_REG 0x00AC
157 #define PMX_PL_20_MASK (0x7 << 0) 157 #define PMX_PL_20_MASK (0x7 << 0)
158 #define PMX_I2C2_PL_20_VAL (0x1 << 0) 158 #define PMX_I2C2_PL_20_VAL (0x1 << 0)
159 #define PMX_RMII_PL_20_VAL (0x4 << 0) 159 #define PMX_RMII_PL_20_VAL (0x4 << 0)
160 160
161 #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3) 161 #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3)
162 #define PMX_SMII_PL_21_TO_27_VAL 0 162 #define PMX_SMII_PL_21_TO_27_VAL 0
163 #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21)) 163 #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
164 164
165 #define PMX_PL_28_29_MASK (0x3F << 24) 165 #define PMX_PL_28_29_MASK (0x3F << 24)
166 #define PMX_PL_28_MASK (0x7 << 24) 166 #define PMX_PL_28_MASK (0x7 << 24)
167 #define PMX_PL_29_MASK (0x7 << 27) 167 #define PMX_PL_29_MASK (0x7 << 27)
168 #define PMX_UART1_PL_28_29_VAL 0 168 #define PMX_UART1_PL_28_29_VAL 0
169 #define PMX_PWM_3_PL_28_VAL (0x4 << 24) 169 #define PMX_PWM_3_PL_28_VAL (0x4 << 24)
170 #define PMX_PWM_2_PL_29_VAL (0x4 << 27) 170 #define PMX_PWM_2_PL_29_VAL (0x4 << 27)
171 171
172 #define IP_SEL_PAD_30_39_REG 0x00B0 172 #define IP_SEL_PAD_30_39_REG 0x00B0
173 #define PMX_PL_30_31_MASK (0x3F << 0) 173 #define PMX_PL_30_31_MASK (0x3F << 0)
174 #define PMX_CAN1_PL_30_31_VAL (0) 174 #define PMX_CAN1_PL_30_31_VAL (0)
175 #define PMX_PL_30_MASK (0x7 << 0) 175 #define PMX_PL_30_MASK (0x7 << 0)
176 #define PMX_PL_31_MASK (0x7 << 3) 176 #define PMX_PL_31_MASK (0x7 << 3)
177 #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0) 177 #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0)
178 #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3) 178 #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3)
179 #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3) 179 #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3)
180 180
181 #define PMX_PL_32_33_MASK (0x3F << 6) 181 #define PMX_PL_32_33_MASK (0x3F << 6)
182 #define PMX_CAN0_PL_32_33_VAL 0 182 #define PMX_CAN0_PL_32_33_VAL 0
183 #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9)) 183 #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9))
184 #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9)) 184 #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9))
185 185
186 #define PMX_PL_34_MASK (0x7 << 12) 186 #define PMX_PL_34_MASK (0x7 << 12)
187 #define PMX_PWM2_PL_34_VAL 0 187 #define PMX_PWM2_PL_34_VAL 0
188 #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12) 188 #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
189 #define PMX_SSP2_PL_34_VAL (0x4 << 12) 189 #define PMX_SSP2_PL_34_VAL (0x4 << 12)
190 190
191 #define PMX_PL_35_MASK (0x7 << 15) 191 #define PMX_PL_35_MASK (0x7 << 15)
192 #define PMX_I2S_REF_CLK_PL_35_VAL 0 192 #define PMX_I2S_REF_CLK_PL_35_VAL 0
193 #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15) 193 #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
194 #define PMX_SSP2_PL_35_VAL (0x4 << 15) 194 #define PMX_SSP2_PL_35_VAL (0x4 << 15)
195 195
196 #define PMX_PL_36_MASK (0x7 << 18) 196 #define PMX_PL_36_MASK (0x7 << 18)
197 #define PMX_TOUCH_X_PL_36_VAL 0 197 #define PMX_TOUCH_X_PL_36_VAL 0
198 #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18) 198 #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
199 #define PMX_SSP1_PL_36_VAL (0x4 << 18) 199 #define PMX_SSP1_PL_36_VAL (0x4 << 18)
200 200
201 #define PMX_PL_37_38_MASK (0x3F << 21) 201 #define PMX_PL_37_38_MASK (0x3F << 21)
202 #define PMX_PWM0_1_PL_37_38_VAL 0 202 #define PMX_PWM0_1_PL_37_38_VAL 0
203 #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24)) 203 #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
204 #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24)) 204 #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24))
205 205
206 #define PMX_PL_39_MASK (0x7 << 27) 206 #define PMX_PL_39_MASK (0x7 << 27)
207 #define PMX_I2S_PL_39_VAL 0 207 #define PMX_I2S_PL_39_VAL 0
208 #define PMX_UART4_PL_39_VAL (0x2 << 27) 208 #define PMX_UART4_PL_39_VAL (0x2 << 27)
209 #define PMX_SSP1_PL_39_VAL (0x4 << 27) 209 #define PMX_SSP1_PL_39_VAL (0x4 << 27)
210 210
211 #define IP_SEL_PAD_40_49_REG 0x00B4 211 #define IP_SEL_PAD_40_49_REG 0x00B4
212 #define PMX_PL_40_MASK (0x7 << 0) 212 #define PMX_PL_40_MASK (0x7 << 0)
213 #define PMX_I2S_PL_40_VAL 0 213 #define PMX_I2S_PL_40_VAL 0
214 #define PMX_UART4_PL_40_VAL (0x2 << 0) 214 #define PMX_UART4_PL_40_VAL (0x2 << 0)
215 #define PMX_PWM3_PL_40_VAL (0x4 << 0) 215 #define PMX_PWM3_PL_40_VAL (0x4 << 0)
216 216
217 #define PMX_PL_41_42_MASK (0x3F << 3) 217 #define PMX_PL_41_42_MASK (0x3F << 3)
218 #define PMX_PL_41_MASK (0x7 << 3) 218 #define PMX_PL_41_MASK (0x7 << 3)
219 #define PMX_PL_42_MASK (0x7 << 6) 219 #define PMX_PL_42_MASK (0x7 << 6)
220 #define PMX_I2S_PL_41_42_VAL 0 220 #define PMX_I2S_PL_41_42_VAL 0
221 #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6)) 221 #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
222 #define PMX_PWM2_PL_41_VAL (0x4 << 3) 222 #define PMX_PWM2_PL_41_VAL (0x4 << 3)
223 #define PMX_PWM1_PL_42_VAL (0x4 << 6) 223 #define PMX_PWM1_PL_42_VAL (0x4 << 6)
224 224
225 #define PMX_PL_43_MASK (0x7 << 9) 225 #define PMX_PL_43_MASK (0x7 << 9)
226 #define PMX_SDHCI_PL_43_VAL 0 226 #define PMX_SDHCI_PL_43_VAL 0
227 #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9) 227 #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
228 #define PMX_PWM0_PL_43_VAL (0x4 << 9) 228 #define PMX_PWM0_PL_43_VAL (0x4 << 9)
229 229
230 #define PMX_PL_44_45_MASK (0x3F << 12) 230 #define PMX_PL_44_45_MASK (0x3F << 12)
231 #define PMX_SDHCI_PL_44_45_VAL 0 231 #define PMX_SDHCI_PL_44_45_VAL 0
232 #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15)) 232 #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
233 #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15)) 233 #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15))
234 234
235 #define PMX_PL_46_47_MASK (0x3F << 18) 235 #define PMX_PL_46_47_MASK (0x3F << 18)
236 #define PMX_SDHCI_PL_46_47_VAL 0 236 #define PMX_SDHCI_PL_46_47_VAL 0
237 #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21)) 237 #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
238 #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21)) 238 #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21))
239 239
240 #define PMX_PL_48_49_MASK (0x3F << 24) 240 #define PMX_PL_48_49_MASK (0x3F << 24)
241 #define PMX_SDHCI_PL_48_49_VAL 0 241 #define PMX_SDHCI_PL_48_49_VAL 0
242 #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27)) 242 #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
243 #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27)) 243 #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27))
244 244
245 #define IP_SEL_PAD_50_59_REG 0x00B8 245 #define IP_SEL_PAD_50_59_REG 0x00B8
246 #define PMX_PL_50_51_MASK (0x3F << 0) 246 #define PMX_PL_50_51_MASK (0x3F << 0)
247 #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3)) 247 #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
248 #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3)) 248 #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3))
249 #define PMX_PL_50_MASK (0x7 << 0) 249 #define PMX_PL_50_MASK (0x7 << 0)
250 #define PMX_PL_51_MASK (0x7 << 3) 250 #define PMX_PL_51_MASK (0x7 << 3)
251 #define PMX_SDHCI_PL_50_VAL 0 251 #define PMX_SDHCI_PL_50_VAL 0
252 #define PMX_SDHCI_CD_PL_51_VAL 0 252 #define PMX_SDHCI_CD_PL_51_VAL 0
253 253
254 #define PMX_PL_52_53_MASK (0x3F << 6) 254 #define PMX_PL_52_53_MASK (0x3F << 6)
255 #define PMX_FSMC_PL_52_53_VAL 0 255 #define PMX_FSMC_PL_52_53_VAL 0
256 #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9)) 256 #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
257 #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9)) 257 #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9))
258 258
259 #define PMX_PL_54_55_56_MASK (0x1FF << 12) 259 #define PMX_PL_54_55_56_MASK (0x1FF << 12)
260 #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18)) 260 #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
261 261
262 #define PMX_PL_57_MASK (0x7 << 21) 262 #define PMX_PL_57_MASK (0x7 << 21)
263 #define PMX_FSMC_PL_57_VAL 0 263 #define PMX_FSMC_PL_57_VAL 0
264 #define PMX_PWM3_PL_57_VAL (0x4 << 21) 264 #define PMX_PWM3_PL_57_VAL (0x4 << 21)
265 265
266 #define PMX_PL_58_59_MASK (0x3F << 24) 266 #define PMX_PL_58_59_MASK (0x3F << 24)
267 #define PMX_PL_58_MASK (0x7 << 24) 267 #define PMX_PL_58_MASK (0x7 << 24)
268 #define PMX_PL_59_MASK (0x7 << 27) 268 #define PMX_PL_59_MASK (0x7 << 27)
269 #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27)) 269 #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
270 #define PMX_PWM2_PL_58_VAL (0x4 << 24) 270 #define PMX_PWM2_PL_58_VAL (0x4 << 24)
271 #define PMX_PWM1_PL_59_VAL (0x4 << 27) 271 #define PMX_PWM1_PL_59_VAL (0x4 << 27)
272 272
273 #define IP_SEL_PAD_60_69_REG 0x00BC 273 #define IP_SEL_PAD_60_69_REG 0x00BC
274 #define PMX_PL_60_MASK (0x7 << 0) 274 #define PMX_PL_60_MASK (0x7 << 0)
275 #define PMX_FSMC_PL_60_VAL 0 275 #define PMX_FSMC_PL_60_VAL 0
276 #define PMX_PWM0_PL_60_VAL (0x4 << 0) 276 #define PMX_PWM0_PL_60_VAL (0x4 << 0)
277 277
278 #define PMX_PL_61_TO_64_MASK (0xFFF << 3) 278 #define PMX_PL_61_TO_64_MASK (0xFFF << 3)
279 #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12)) 279 #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
280 #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12)) 280 #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
281 281
282 #define PMX_PL_65_TO_68_MASK (0xFFF << 15) 282 #define PMX_PL_65_TO_68_MASK (0xFFF << 15)
283 #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24)) 283 #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
284 #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24)) 284 #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
285 285
286 #define PMX_PL_69_MASK (0x7 << 27) 286 #define PMX_PL_69_MASK (0x7 << 27)
287 #define PMX_CLCD_PL_69_VAL (0) 287 #define PMX_CLCD_PL_69_VAL (0)
288 #define PMX_EMI_PL_69_VAL (0x2 << 27) 288 #define PMX_EMI_PL_69_VAL (0x2 << 27)
289 #define PMX_SPP_PL_69_VAL (0x3 << 27) 289 #define PMX_SPP_PL_69_VAL (0x3 << 27)
290 #define PMX_UART5_PL_69_VAL (0x4 << 27) 290 #define PMX_UART5_PL_69_VAL (0x4 << 27)
291 291
292 #define IP_SEL_PAD_70_79_REG 0x00C0 292 #define IP_SEL_PAD_70_79_REG 0x00C0
293 #define PMX_PL_70_MASK (0x7 << 0) 293 #define PMX_PL_70_MASK (0x7 << 0)
294 #define PMX_CLCD_PL_70_VAL (0) 294 #define PMX_CLCD_PL_70_VAL (0)
295 #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0) 295 #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
296 #define PMX_SPP_PL_70_VAL (0x3 << 0) 296 #define PMX_SPP_PL_70_VAL (0x3 << 0)
297 #define PMX_UART5_PL_70_VAL (0x4 << 0) 297 #define PMX_UART5_PL_70_VAL (0x4 << 0)
298 298
299 #define PMX_PL_71_72_MASK (0x3F << 3) 299 #define PMX_PL_71_72_MASK (0x3F << 3)
300 #define PMX_CLCD_PL_71_72_VAL (0) 300 #define PMX_CLCD_PL_71_72_VAL (0)
301 #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6)) 301 #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
302 #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6)) 302 #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6))
303 #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6)) 303 #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6))
304 304
305 #define PMX_PL_73_MASK (0x7 << 9) 305 #define PMX_PL_73_MASK (0x7 << 9)
306 #define PMX_CLCD_PL_73_VAL (0) 306 #define PMX_CLCD_PL_73_VAL (0)
307 #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9) 307 #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
308 #define PMX_SPP_PL_73_VAL (0x3 << 9) 308 #define PMX_SPP_PL_73_VAL (0x3 << 9)
309 #define PMX_UART3_PL_73_VAL (0x4 << 9) 309 #define PMX_UART3_PL_73_VAL (0x4 << 9)
310 310
311 #define PMX_PL_74_MASK (0x7 << 12) 311 #define PMX_PL_74_MASK (0x7 << 12)
312 #define PMX_CLCD_PL_74_VAL (0) 312 #define PMX_CLCD_PL_74_VAL (0)
313 #define PMX_EMI_PL_74_VAL (0x2 << 12) 313 #define PMX_EMI_PL_74_VAL (0x2 << 12)
314 #define PMX_SPP_PL_74_VAL (0x3 << 12) 314 #define PMX_SPP_PL_74_VAL (0x3 << 12)
315 #define PMX_UART3_PL_74_VAL (0x4 << 12) 315 #define PMX_UART3_PL_74_VAL (0x4 << 12)
316 316
317 #define PMX_PL_75_76_MASK (0x3F << 15) 317 #define PMX_PL_75_76_MASK (0x3F << 15)
318 #define PMX_CLCD_PL_75_76_VAL (0) 318 #define PMX_CLCD_PL_75_76_VAL (0)
319 #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18)) 319 #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
320 #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18)) 320 #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18))
321 #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18)) 321 #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18))
322 322
323 #define PMX_PL_77_78_79_MASK (0x1FF << 21) 323 #define PMX_PL_77_78_79_MASK (0x1FF << 21)
324 #define PMX_CLCD_PL_77_78_79_VAL (0) 324 #define PMX_CLCD_PL_77_78_79_VAL (0)
325 #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27)) 325 #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
326 #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27)) 326 #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
327 #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27)) 327 #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
328 328
329 #define IP_SEL_PAD_80_89_REG 0x00C4 329 #define IP_SEL_PAD_80_89_REG 0x00C4
330 #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0) 330 #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0)
331 #define PMX_CLCD_PL_80_TO_85_VAL 0 331 #define PMX_CLCD_PL_80_TO_85_VAL 0
332 #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15)) 332 #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
333 #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15)) 333 #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
334 #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15)) 334 #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
335 #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15)) 335 #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
336 336
337 #define PMX_PL_86_87_MASK (0x3F << 18) 337 #define PMX_PL_86_87_MASK (0x3F << 18)
338 #define PMX_PL_86_MASK (0x7 << 18) 338 #define PMX_PL_86_MASK (0x7 << 18)
339 #define PMX_PL_87_MASK (0x7 << 21) 339 #define PMX_PL_87_MASK (0x7 << 21)
340 #define PMX_CLCD_PL_86_87_VAL 0 340 #define PMX_CLCD_PL_86_87_VAL 0
341 #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21)) 341 #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21))
342 #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21)) 342 #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
343 #define PMX_PWM3_PL_86_VAL (0x4 << 18) 343 #define PMX_PWM3_PL_86_VAL (0x4 << 18)
344 #define PMX_PWM2_PL_87_VAL (0x4 << 21) 344 #define PMX_PWM2_PL_87_VAL (0x4 << 21)
345 345
346 #define PMX_PL_88_89_MASK (0x3F << 24) 346 #define PMX_PL_88_89_MASK (0x3F << 24)
347 #define PMX_CLCD_PL_88_89_VAL 0 347 #define PMX_CLCD_PL_88_89_VAL 0
348 #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27)) 348 #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27))
349 #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27)) 349 #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
350 #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27)) 350 #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27))
351 #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27)) 351 #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27))
352 352
353 #define IP_SEL_PAD_90_99_REG 0x00C8 353 #define IP_SEL_PAD_90_99_REG 0x00C8
354 #define PMX_PL_90_91_MASK (0x3F << 0) 354 #define PMX_PL_90_91_MASK (0x3F << 0)
355 #define PMX_CLCD_PL_90_91_VAL 0 355 #define PMX_CLCD_PL_90_91_VAL 0
356 #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3)) 356 #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3))
357 #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3)) 357 #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
358 #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3)) 358 #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3))
359 #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3)) 359 #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3))
360 360
361 #define PMX_PL_92_93_MASK (0x3F << 6) 361 #define PMX_PL_92_93_MASK (0x3F << 6)
362 #define PMX_CLCD_PL_92_93_VAL 0 362 #define PMX_CLCD_PL_92_93_VAL 0
363 #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9)) 363 #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9))
364 #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9)) 364 #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
365 #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9)) 365 #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9))
366 #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9)) 366 #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9))
367 367
368 #define PMX_PL_94_95_MASK (0x3F << 12) 368 #define PMX_PL_94_95_MASK (0x3F << 12)
369 #define PMX_CLCD_PL_94_95_VAL 0 369 #define PMX_CLCD_PL_94_95_VAL 0
370 #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15)) 370 #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15))
371 #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15)) 371 #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
372 #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15)) 372 #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15))
373 #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15)) 373 #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15))
374 374
375 #define PMX_PL_96_97_MASK (0x3F << 18) 375 #define PMX_PL_96_97_MASK (0x3F << 18)
376 #define PMX_CLCD_PL_96_97_VAL 0 376 #define PMX_CLCD_PL_96_97_VAL 0
377 #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21)) 377 #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21))
378 #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21)) 378 #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
379 #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21)) 379 #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21))
380 #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21)) 380 #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21))
381 381
382 #define PMX_PL_98_MASK (0x7 << 24) 382 #define PMX_PL_98_MASK (0x7 << 24)
383 #define PMX_CLCD_PL_98_VAL 0 383 #define PMX_CLCD_PL_98_VAL 0
384 #define PMX_I2C1_PL_98_VAL (0x2 << 24) 384 #define PMX_I2C1_PL_98_VAL (0x2 << 24)
385 #define PMX_UART3_PL_98_VAL (0x4 << 24) 385 #define PMX_UART3_PL_98_VAL (0x4 << 24)
386 386
387 #define PMX_PL_99_MASK (0x7 << 27) 387 #define PMX_PL_99_MASK (0x7 << 27)
388 #define PMX_SDHCI_PL_99_VAL 0 388 #define PMX_SDHCI_PL_99_VAL 0
389 #define PMX_I2C1_PL_99_VAL (0x2 << 27) 389 #define PMX_I2C1_PL_99_VAL (0x2 << 27)
390 #define PMX_UART3_PL_99_VAL (0x4 << 27) 390 #define PMX_UART3_PL_99_VAL (0x4 << 27)
391 391
392 #define IP_SEL_MIX_PAD_REG 0x00CC 392 #define IP_SEL_MIX_PAD_REG 0x00CC
393 #define PMX_PL_100_101_MASK (0x3F << 0) 393 #define PMX_PL_100_101_MASK (0x3F << 0)
394 #define PMX_SDHCI_PL_100_101_VAL 0 394 #define PMX_SDHCI_PL_100_101_VAL 0
395 #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3)) 395 #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3))
396 396
397 #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8) 397 #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8)
398 #define PMX_SSP1_PORT_94_TO_97_VAL 0 398 #define PMX_SSP1_PORT_94_TO_97_VAL 0
399 #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8) 399 #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8)
400 #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8) 400 #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
401 #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8) 401 #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8)
402 #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8) 402 #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8)
403 403
404 #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11) 404 #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11)
405 #define PMX_SSP2_PORT_90_TO_93_VAL 0 405 #define PMX_SSP2_PORT_90_TO_93_VAL 0
406 #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11) 406 #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11)
407 #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11) 407 #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
408 #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11) 408 #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11)
409 #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11) 409 #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11)
410 410
411 #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14) 411 #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14)
412 #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0 412 #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0
413 #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14) 413 #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14)
414 #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14) 414 #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
415 #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14) 415 #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14)
416 416
417 #define PMX_UART3_PORT_SEL_MASK (0x7 << 16) 417 #define PMX_UART3_PORT_SEL_MASK (0x7 << 16)
418 #define PMX_UART3_PORT_94_VAL 0 418 #define PMX_UART3_PORT_94_VAL 0
419 #define PMX_UART3_PORT_73_VAL (0x1 << 16) 419 #define PMX_UART3_PORT_73_VAL (0x1 << 16)
420 #define PMX_UART3_PORT_52_VAL (0x2 << 16) 420 #define PMX_UART3_PORT_52_VAL (0x2 << 16)
421 #define PMX_UART3_PORT_41_VAL (0x3 << 16) 421 #define PMX_UART3_PORT_41_VAL (0x3 << 16)
422 #define PMX_UART3_PORT_15_VAL (0x4 << 16) 422 #define PMX_UART3_PORT_15_VAL (0x4 << 16)
423 #define PMX_UART3_PORT_8_VAL (0x5 << 16) 423 #define PMX_UART3_PORT_8_VAL (0x5 << 16)
424 #define PMX_UART3_PORT_99_VAL (0x6 << 16) 424 #define PMX_UART3_PORT_99_VAL (0x6 << 16)
425 425
426 #define PMX_UART4_PORT_SEL_MASK (0x7 << 19) 426 #define PMX_UART4_PORT_SEL_MASK (0x7 << 19)
427 #define PMX_UART4_PORT_92_VAL 0 427 #define PMX_UART4_PORT_92_VAL 0
428 #define PMX_UART4_PORT_71_VAL (0x1 << 19) 428 #define PMX_UART4_PORT_71_VAL (0x1 << 19)
429 #define PMX_UART4_PORT_39_VAL (0x2 << 19) 429 #define PMX_UART4_PORT_39_VAL (0x2 << 19)
430 #define PMX_UART4_PORT_13_VAL (0x3 << 19) 430 #define PMX_UART4_PORT_13_VAL (0x3 << 19)
431 #define PMX_UART4_PORT_6_VAL (0x4 << 19) 431 #define PMX_UART4_PORT_6_VAL (0x4 << 19)
432 #define PMX_UART4_PORT_101_VAL (0x5 << 19) 432 #define PMX_UART4_PORT_101_VAL (0x5 << 19)
433 433
434 #define PMX_UART5_PORT_SEL_MASK (0x3 << 22) 434 #define PMX_UART5_PORT_SEL_MASK (0x3 << 22)
435 #define PMX_UART5_PORT_90_VAL 0 435 #define PMX_UART5_PORT_90_VAL 0
436 #define PMX_UART5_PORT_69_VAL (0x1 << 22) 436 #define PMX_UART5_PORT_69_VAL (0x1 << 22)
437 #define PMX_UART5_PORT_37_VAL (0x2 << 22) 437 #define PMX_UART5_PORT_37_VAL (0x2 << 22)
438 #define PMX_UART5_PORT_4_VAL (0x3 << 22) 438 #define PMX_UART5_PORT_4_VAL (0x3 << 22)
439 439
440 #define PMX_UART6_PORT_SEL_MASK (0x1 << 24) 440 #define PMX_UART6_PORT_SEL_MASK (0x1 << 24)
441 #define PMX_UART6_PORT_88_VAL 0 441 #define PMX_UART6_PORT_88_VAL 0
442 #define PMX_UART6_PORT_2_VAL (0x1 << 24) 442 #define PMX_UART6_PORT_2_VAL (0x1 << 24)
443 443
444 #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25) 444 #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25)
445 #define PMX_I2C1_PORT_8_9_VAL 0 445 #define PMX_I2C1_PORT_8_9_VAL 0
446 #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25) 446 #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25)
447 447
448 #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26) 448 #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26)
449 #define PMX_I2C2_PORT_96_97_VAL 0 449 #define PMX_I2C2_PORT_96_97_VAL 0
450 #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26) 450 #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26)
451 #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26) 451 #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
452 #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26) 452 #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26)
453 #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26) 453 #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26)
454 454
455 #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29) 455 #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29)
456 #define PMX_SDHCI_CD_PORT_12_VAL 0 456 #define PMX_SDHCI_CD_PORT_12_VAL 0
457 #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29) 457 #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
458 458
459 /* Pad multiplexing for CLCD device */ 459 /* Pad multiplexing for CLCD device */
460 static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 460 static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
461 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 461 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
462 97 }; 462 97 };
463 static struct spear_muxreg clcd_muxreg[] = { 463 static struct spear_muxreg clcd_muxreg[] = {
464 { 464 {
465 .reg = IP_SEL_PAD_60_69_REG, 465 .reg = IP_SEL_PAD_60_69_REG,
466 .mask = PMX_PL_69_MASK, 466 .mask = PMX_PL_69_MASK,
467 .val = PMX_CLCD_PL_69_VAL, 467 .val = PMX_CLCD_PL_69_VAL,
468 }, { 468 }, {
469 .reg = IP_SEL_PAD_70_79_REG, 469 .reg = IP_SEL_PAD_70_79_REG,
470 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | 470 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
471 PMX_PL_74_MASK | PMX_PL_75_76_MASK | 471 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
472 PMX_PL_77_78_79_MASK, 472 PMX_PL_77_78_79_MASK,
473 .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL | 473 .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
474 PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL | 474 PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
475 PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL, 475 PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
476 }, { 476 }, {
477 .reg = IP_SEL_PAD_80_89_REG, 477 .reg = IP_SEL_PAD_80_89_REG,
478 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | 478 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
479 PMX_PL_88_89_MASK, 479 PMX_PL_88_89_MASK,
480 .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL | 480 .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
481 PMX_CLCD_PL_88_89_VAL, 481 PMX_CLCD_PL_88_89_VAL,
482 }, { 482 }, {
483 .reg = IP_SEL_PAD_90_99_REG, 483 .reg = IP_SEL_PAD_90_99_REG,
484 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | 484 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
485 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK, 485 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
486 .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL | 486 .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
487 PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL | 487 PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
488 PMX_CLCD_PL_98_VAL, 488 PMX_CLCD_PL_98_VAL,
489 }, 489 },
490 }; 490 };
491 491
492 static struct spear_modemux clcd_modemux[] = { 492 static struct spear_modemux clcd_modemux[] = {
493 { 493 {
494 .modes = EXTENDED_MODE, 494 .modes = EXTENDED_MODE,
495 .muxregs = clcd_muxreg, 495 .muxregs = clcd_muxreg,
496 .nmuxregs = ARRAY_SIZE(clcd_muxreg), 496 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
497 }, 497 },
498 }; 498 };
499 499
500 static struct spear_pingroup clcd_pingroup = { 500 static struct spear_pingroup clcd_pingroup = {
501 .name = "clcd_grp", 501 .name = "clcd_grp",
502 .pins = clcd_pins, 502 .pins = clcd_pins,
503 .npins = ARRAY_SIZE(clcd_pins), 503 .npins = ARRAY_SIZE(clcd_pins),
504 .modemuxs = clcd_modemux, 504 .modemuxs = clcd_modemux,
505 .nmodemuxs = ARRAY_SIZE(clcd_modemux), 505 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
506 }; 506 };
507 507
508 static const char *const clcd_grps[] = { "clcd_grp" }; 508 static const char *const clcd_grps[] = { "clcd_grp" };
509 static struct spear_function clcd_function = { 509 static struct spear_function clcd_function = {
510 .name = "clcd", 510 .name = "clcd",
511 .groups = clcd_grps, 511 .groups = clcd_grps,
512 .ngroups = ARRAY_SIZE(clcd_grps), 512 .ngroups = ARRAY_SIZE(clcd_grps),
513 }; 513 };
514 514
515 /* Pad multiplexing for EMI (Parallel NOR flash) device */ 515 /* Pad multiplexing for EMI (Parallel NOR flash) device */
516 static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 516 static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
517 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 517 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
518 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 518 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
519 93, 94, 95, 96, 97 }; 519 93, 94, 95, 96, 97 };
520 static struct spear_muxreg emi_muxreg[] = { 520 static struct spear_muxreg emi_muxreg[] = {
521 { 521 {
522 .reg = PMX_CONFIG_REG, 522 .reg = PMX_CONFIG_REG,
523 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 523 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
524 .val = 0, 524 .val = 0,
525 }, 525 },
526 }; 526 };
527 527
528 static struct spear_muxreg emi_ext_muxreg[] = { 528 static struct spear_muxreg emi_ext_muxreg[] = {
529 { 529 {
530 .reg = IP_SEL_PAD_40_49_REG, 530 .reg = IP_SEL_PAD_40_49_REG,
531 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, 531 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
532 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, 532 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
533 }, { 533 }, {
534 .reg = IP_SEL_PAD_50_59_REG, 534 .reg = IP_SEL_PAD_50_59_REG,
535 .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK | 535 .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
536 PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK, 536 PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
537 .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL | 537 .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
538 PMX_FSMC_EMI_PL_54_55_56_VAL | 538 PMX_FSMC_EMI_PL_54_55_56_VAL |
539 PMX_FSMC_EMI_PL_58_59_VAL, 539 PMX_FSMC_EMI_PL_58_59_VAL,
540 }, { 540 }, {
541 .reg = IP_SEL_PAD_60_69_REG, 541 .reg = IP_SEL_PAD_60_69_REG,
542 .mask = PMX_PL_69_MASK, 542 .mask = PMX_PL_69_MASK,
543 .val = PMX_EMI_PL_69_VAL, 543 .val = PMX_EMI_PL_69_VAL,
544 }, { 544 }, {
545 .reg = IP_SEL_PAD_70_79_REG, 545 .reg = IP_SEL_PAD_70_79_REG,
546 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | 546 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
547 PMX_PL_74_MASK | PMX_PL_75_76_MASK | 547 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
548 PMX_PL_77_78_79_MASK, 548 PMX_PL_77_78_79_MASK,
549 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | 549 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
550 PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL | 550 PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
551 PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL, 551 PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
552 }, { 552 }, {
553 .reg = IP_SEL_PAD_80_89_REG, 553 .reg = IP_SEL_PAD_80_89_REG,
554 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | 554 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
555 PMX_PL_88_89_MASK, 555 PMX_PL_88_89_MASK,
556 .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL | 556 .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
557 PMX_EMI_PL_88_89_VAL, 557 PMX_EMI_PL_88_89_VAL,
558 }, { 558 }, {
559 .reg = IP_SEL_PAD_90_99_REG, 559 .reg = IP_SEL_PAD_90_99_REG,
560 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | 560 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
561 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, 561 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
562 .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL | 562 .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
563 PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL, 563 PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
564 }, { 564 }, {
565 .reg = EXT_CTRL_REG, 565 .reg = EXT_CTRL_REG,
566 .mask = EMI_FSMC_DYNAMIC_MUX_MASK, 566 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
567 .val = EMI_FSMC_DYNAMIC_MUX_MASK, 567 .val = EMI_FSMC_DYNAMIC_MUX_MASK,
568 }, 568 },
569 }; 569 };
570 570
571 static struct spear_modemux emi_modemux[] = { 571 static struct spear_modemux emi_modemux[] = {
572 { 572 {
573 .modes = AUTO_EXP_MODE | EXTENDED_MODE, 573 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
574 .muxregs = emi_muxreg, 574 .muxregs = emi_muxreg,
575 .nmuxregs = ARRAY_SIZE(emi_muxreg), 575 .nmuxregs = ARRAY_SIZE(emi_muxreg),
576 }, { 576 }, {
577 .modes = EXTENDED_MODE, 577 .modes = EXTENDED_MODE,
578 .muxregs = emi_ext_muxreg, 578 .muxregs = emi_ext_muxreg,
579 .nmuxregs = ARRAY_SIZE(emi_ext_muxreg), 579 .nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
580 }, 580 },
581 }; 581 };
582 582
583 static struct spear_pingroup emi_pingroup = { 583 static struct spear_pingroup emi_pingroup = {
584 .name = "emi_grp", 584 .name = "emi_grp",
585 .pins = emi_pins, 585 .pins = emi_pins,
586 .npins = ARRAY_SIZE(emi_pins), 586 .npins = ARRAY_SIZE(emi_pins),
587 .modemuxs = emi_modemux, 587 .modemuxs = emi_modemux,
588 .nmodemuxs = ARRAY_SIZE(emi_modemux), 588 .nmodemuxs = ARRAY_SIZE(emi_modemux),
589 }; 589 };
590 590
591 static const char *const emi_grps[] = { "emi_grp" }; 591 static const char *const emi_grps[] = { "emi_grp" };
592 static struct spear_function emi_function = { 592 static struct spear_function emi_function = {
593 .name = "emi", 593 .name = "emi",
594 .groups = emi_grps, 594 .groups = emi_grps,
595 .ngroups = ARRAY_SIZE(emi_grps), 595 .ngroups = ARRAY_SIZE(emi_grps),
596 }; 596 };
597 597
598 /* Pad multiplexing for FSMC (NAND flash) device */ 598 /* Pad multiplexing for FSMC (NAND flash) device */
599 static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60, 599 static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
600 61, 62, 63, 64, 65, 66, 67, 68 }; 600 61, 62, 63, 64, 65, 66, 67, 68 };
601 static struct spear_muxreg fsmc_8bit_muxreg[] = { 601 static struct spear_muxreg fsmc_8bit_muxreg[] = {
602 { 602 {
603 .reg = IP_SEL_PAD_50_59_REG, 603 .reg = IP_SEL_PAD_50_59_REG,
604 .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK | 604 .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
605 PMX_PL_57_MASK | PMX_PL_58_59_MASK, 605 PMX_PL_57_MASK | PMX_PL_58_59_MASK,
606 .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL | 606 .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
607 PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL, 607 PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
608 }, { 608 }, {
609 .reg = IP_SEL_PAD_60_69_REG, 609 .reg = IP_SEL_PAD_60_69_REG,
610 .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK | 610 .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
611 PMX_PL_65_TO_68_MASK, 611 PMX_PL_65_TO_68_MASK,
612 .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL | 612 .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
613 PMX_FSMC_PL_65_TO_68_VAL, 613 PMX_FSMC_PL_65_TO_68_VAL,
614 }, { 614 }, {
615 .reg = EXT_CTRL_REG, 615 .reg = EXT_CTRL_REG,
616 .mask = EMI_FSMC_DYNAMIC_MUX_MASK, 616 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
617 .val = EMI_FSMC_DYNAMIC_MUX_MASK, 617 .val = EMI_FSMC_DYNAMIC_MUX_MASK,
618 }, 618 },
619 }; 619 };
620 620
621 static struct spear_modemux fsmc_8bit_modemux[] = { 621 static struct spear_modemux fsmc_8bit_modemux[] = {
622 { 622 {
623 .modes = EXTENDED_MODE, 623 .modes = EXTENDED_MODE,
624 .muxregs = fsmc_8bit_muxreg, 624 .muxregs = fsmc_8bit_muxreg,
625 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), 625 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
626 }, 626 },
627 }; 627 };
628 628
629 static struct spear_pingroup fsmc_8bit_pingroup = { 629 static struct spear_pingroup fsmc_8bit_pingroup = {
630 .name = "fsmc_8bit_grp", 630 .name = "fsmc_8bit_grp",
631 .pins = fsmc_8bit_pins, 631 .pins = fsmc_8bit_pins,
632 .npins = ARRAY_SIZE(fsmc_8bit_pins), 632 .npins = ARRAY_SIZE(fsmc_8bit_pins),
633 .modemuxs = fsmc_8bit_modemux, 633 .modemuxs = fsmc_8bit_modemux,
634 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux), 634 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
635 }; 635 };
636 636
637 static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56, 637 static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
638 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 }; 638 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
639 static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = { 639 static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
640 { 640 {
641 .reg = PMX_CONFIG_REG, 641 .reg = PMX_CONFIG_REG,
642 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 642 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
643 .val = 0, 643 .val = 0,
644 }, 644 },
645 }; 645 };
646 646
647 static struct spear_muxreg fsmc_16bit_muxreg[] = { 647 static struct spear_muxreg fsmc_16bit_muxreg[] = {
648 { 648 {
649 .reg = IP_SEL_PAD_40_49_REG, 649 .reg = IP_SEL_PAD_40_49_REG,
650 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, 650 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
651 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, 651 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
652 }, { 652 }, {
653 .reg = IP_SEL_PAD_70_79_REG, 653 .reg = IP_SEL_PAD_70_79_REG,
654 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK, 654 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
655 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | 655 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
656 PMX_FSMC_EMI_PL_73_VAL, 656 PMX_FSMC_EMI_PL_73_VAL,
657 } 657 }
658 }; 658 };
659 659
660 static struct spear_modemux fsmc_16bit_modemux[] = { 660 static struct spear_modemux fsmc_16bit_modemux[] = {
661 { 661 {
662 .modes = EXTENDED_MODE, 662 .modes = EXTENDED_MODE,
663 .muxregs = fsmc_8bit_muxreg, 663 .muxregs = fsmc_8bit_muxreg,
664 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), 664 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
665 }, { 665 }, {
666 .modes = AUTO_EXP_MODE | EXTENDED_MODE, 666 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
667 .muxregs = fsmc_16bit_autoexp_muxreg, 667 .muxregs = fsmc_16bit_autoexp_muxreg,
668 .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg), 668 .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
669 }, { 669 }, {
670 .modes = EXTENDED_MODE, 670 .modes = EXTENDED_MODE,
671 .muxregs = fsmc_16bit_muxreg, 671 .muxregs = fsmc_16bit_muxreg,
672 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg), 672 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
673 }, 673 },
674 }; 674 };
675 675
676 static struct spear_pingroup fsmc_16bit_pingroup = { 676 static struct spear_pingroup fsmc_16bit_pingroup = {
677 .name = "fsmc_16bit_grp", 677 .name = "fsmc_16bit_grp",
678 .pins = fsmc_16bit_pins, 678 .pins = fsmc_16bit_pins,
679 .npins = ARRAY_SIZE(fsmc_16bit_pins), 679 .npins = ARRAY_SIZE(fsmc_16bit_pins),
680 .modemuxs = fsmc_16bit_modemux, 680 .modemuxs = fsmc_16bit_modemux,
681 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux), 681 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
682 }; 682 };
683 683
684 static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" }; 684 static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
685 static struct spear_function fsmc_function = { 685 static struct spear_function fsmc_function = {
686 .name = "fsmc", 686 .name = "fsmc",
687 .groups = fsmc_grps, 687 .groups = fsmc_grps,
688 .ngroups = ARRAY_SIZE(fsmc_grps), 688 .ngroups = ARRAY_SIZE(fsmc_grps),
689 }; 689 };
690 690
691 /* Pad multiplexing for SPP device */ 691 /* Pad multiplexing for SPP device */
692 static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 692 static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
693 80, 81, 82, 83, 84, 85 }; 693 80, 81, 82, 83, 84, 85 };
694 static struct spear_muxreg spp_muxreg[] = { 694 static struct spear_muxreg spp_muxreg[] = {
695 { 695 {
696 .reg = IP_SEL_PAD_60_69_REG, 696 .reg = IP_SEL_PAD_60_69_REG,
697 .mask = PMX_PL_69_MASK, 697 .mask = PMX_PL_69_MASK,
698 .val = PMX_SPP_PL_69_VAL, 698 .val = PMX_SPP_PL_69_VAL,
699 }, { 699 }, {
700 .reg = IP_SEL_PAD_70_79_REG, 700 .reg = IP_SEL_PAD_70_79_REG,
701 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | 701 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
702 PMX_PL_74_MASK | PMX_PL_75_76_MASK | 702 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
703 PMX_PL_77_78_79_MASK, 703 PMX_PL_77_78_79_MASK,
704 .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL | 704 .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
705 PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL | 705 PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
706 PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL, 706 PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
707 }, { 707 }, {
708 .reg = IP_SEL_PAD_80_89_REG, 708 .reg = IP_SEL_PAD_80_89_REG,
709 .mask = PMX_PL_80_TO_85_MASK, 709 .mask = PMX_PL_80_TO_85_MASK,
710 .val = PMX_SPP_PL_80_TO_85_VAL, 710 .val = PMX_SPP_PL_80_TO_85_VAL,
711 }, 711 },
712 }; 712 };
713 713
714 static struct spear_modemux spp_modemux[] = { 714 static struct spear_modemux spp_modemux[] = {
715 { 715 {
716 .modes = EXTENDED_MODE, 716 .modes = EXTENDED_MODE,
717 .muxregs = spp_muxreg, 717 .muxregs = spp_muxreg,
718 .nmuxregs = ARRAY_SIZE(spp_muxreg), 718 .nmuxregs = ARRAY_SIZE(spp_muxreg),
719 }, 719 },
720 }; 720 };
721 721
722 static struct spear_pingroup spp_pingroup = { 722 static struct spear_pingroup spp_pingroup = {
723 .name = "spp_grp", 723 .name = "spp_grp",
724 .pins = spp_pins, 724 .pins = spp_pins,
725 .npins = ARRAY_SIZE(spp_pins), 725 .npins = ARRAY_SIZE(spp_pins),
726 .modemuxs = spp_modemux, 726 .modemuxs = spp_modemux,
727 .nmodemuxs = ARRAY_SIZE(spp_modemux), 727 .nmodemuxs = ARRAY_SIZE(spp_modemux),
728 }; 728 };
729 729
730 static const char *const spp_grps[] = { "spp_grp" }; 730 static const char *const spp_grps[] = { "spp_grp" };
731 static struct spear_function spp_function = { 731 static struct spear_function spp_function = {
732 .name = "spp", 732 .name = "spp",
733 .groups = spp_grps, 733 .groups = spp_grps,
734 .ngroups = ARRAY_SIZE(spp_grps), 734 .ngroups = ARRAY_SIZE(spp_grps),
735 }; 735 };
736 736
737 /* Pad multiplexing for SDHCI device */ 737 /* Pad multiplexing for SDHCI device */
738 static const unsigned sdhci_led_pins[] = { 34 }; 738 static const unsigned sdhci_led_pins[] = { 34 };
739 static struct spear_muxreg sdhci_led_muxreg[] = { 739 static struct spear_muxreg sdhci_led_muxreg[] = {
740 { 740 {
741 .reg = PMX_CONFIG_REG, 741 .reg = PMX_CONFIG_REG,
742 .mask = PMX_SSP_CS_MASK, 742 .mask = PMX_SSP_CS_MASK,
743 .val = 0, 743 .val = 0,
744 }, 744 },
745 }; 745 };
746 746
747 static struct spear_muxreg sdhci_led_ext_muxreg[] = { 747 static struct spear_muxreg sdhci_led_ext_muxreg[] = {
748 { 748 {
749 .reg = IP_SEL_PAD_30_39_REG, 749 .reg = IP_SEL_PAD_30_39_REG,
750 .mask = PMX_PL_34_MASK, 750 .mask = PMX_PL_34_MASK,
751 .val = PMX_PWM2_PL_34_VAL, 751 .val = PMX_PWM2_PL_34_VAL,
752 }, 752 },
753 }; 753 };
754 754
755 static struct spear_modemux sdhci_led_modemux[] = { 755 static struct spear_modemux sdhci_led_modemux[] = {
756 { 756 {
757 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, 757 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
758 .muxregs = sdhci_led_muxreg, 758 .muxregs = sdhci_led_muxreg,
759 .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg), 759 .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
760 }, { 760 }, {
761 .modes = EXTENDED_MODE, 761 .modes = EXTENDED_MODE,
762 .muxregs = sdhci_led_ext_muxreg, 762 .muxregs = sdhci_led_ext_muxreg,
763 .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg), 763 .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
764 }, 764 },
765 }; 765 };
766 766
767 static struct spear_pingroup sdhci_led_pingroup = { 767 static struct spear_pingroup sdhci_led_pingroup = {
768 .name = "sdhci_led_grp", 768 .name = "sdhci_led_grp",
769 .pins = sdhci_led_pins, 769 .pins = sdhci_led_pins,
770 .npins = ARRAY_SIZE(sdhci_led_pins), 770 .npins = ARRAY_SIZE(sdhci_led_pins),
771 .modemuxs = sdhci_led_modemux, 771 .modemuxs = sdhci_led_modemux,
772 .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux), 772 .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
773 }; 773 };
774 774
775 static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49, 775 static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
776 50}; 776 50};
777 static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51 777 static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
778 }; 778 };
779 static struct spear_muxreg sdhci_muxreg[] = { 779 static struct spear_muxreg sdhci_muxreg[] = {
780 { 780 {
781 .reg = PMX_CONFIG_REG, 781 .reg = PMX_CONFIG_REG,
782 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 782 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
783 .val = 0, 783 .val = 0,
784 }, 784 },
785 }; 785 };
786 786
787 static struct spear_muxreg sdhci_ext_muxreg[] = { 787 static struct spear_muxreg sdhci_ext_muxreg[] = {
788 { 788 {
789 .reg = IP_SEL_PAD_40_49_REG, 789 .reg = IP_SEL_PAD_40_49_REG,
790 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK | 790 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
791 PMX_PL_48_49_MASK, 791 PMX_PL_48_49_MASK,
792 .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL | 792 .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
793 PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL, 793 PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
794 }, { 794 }, {
795 .reg = IP_SEL_PAD_50_59_REG, 795 .reg = IP_SEL_PAD_50_59_REG,
796 .mask = PMX_PL_50_MASK, 796 .mask = PMX_PL_50_MASK,
797 .val = PMX_SDHCI_PL_50_VAL, 797 .val = PMX_SDHCI_PL_50_VAL,
798 }, { 798 }, {
799 .reg = IP_SEL_PAD_90_99_REG, 799 .reg = IP_SEL_PAD_90_99_REG,
800 .mask = PMX_PL_99_MASK, 800 .mask = PMX_PL_99_MASK,
801 .val = PMX_SDHCI_PL_99_VAL, 801 .val = PMX_SDHCI_PL_99_VAL,
802 }, { 802 }, {
803 .reg = IP_SEL_MIX_PAD_REG, 803 .reg = IP_SEL_MIX_PAD_REG,
804 .mask = PMX_PL_100_101_MASK, 804 .mask = PMX_PL_100_101_MASK,
805 .val = PMX_SDHCI_PL_100_101_VAL, 805 .val = PMX_SDHCI_PL_100_101_VAL,
806 }, 806 },
807 }; 807 };
808 808
809 static struct spear_muxreg sdhci_cd_12_muxreg[] = { 809 static struct spear_muxreg sdhci_cd_12_muxreg[] = {
810 { 810 {
811 .reg = PMX_CONFIG_REG, 811 .reg = PMX_CONFIG_REG,
812 .mask = PMX_MII_MASK, 812 .mask = PMX_MII_MASK,
813 .val = 0, 813 .val = 0,
814 }, { 814 }, {
815 .reg = IP_SEL_PAD_10_19_REG, 815 .reg = IP_SEL_PAD_10_19_REG,
816 .mask = PMX_PL_12_MASK, 816 .mask = PMX_PL_12_MASK,
817 .val = PMX_SDHCI_CD_PL_12_VAL, 817 .val = PMX_SDHCI_CD_PL_12_VAL,
818 }, { 818 }, {
819 .reg = IP_SEL_MIX_PAD_REG, 819 .reg = IP_SEL_MIX_PAD_REG,
820 .mask = PMX_SDHCI_CD_PORT_SEL_MASK, 820 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
821 .val = PMX_SDHCI_CD_PORT_12_VAL, 821 .val = PMX_SDHCI_CD_PORT_12_VAL,
822 }, 822 },
823 }; 823 };
824 824
825 static struct spear_muxreg sdhci_cd_51_muxreg[] = { 825 static struct spear_muxreg sdhci_cd_51_muxreg[] = {
826 { 826 {
827 .reg = IP_SEL_PAD_50_59_REG, 827 .reg = IP_SEL_PAD_50_59_REG,
828 .mask = PMX_PL_51_MASK, 828 .mask = PMX_PL_51_MASK,
829 .val = PMX_SDHCI_CD_PL_51_VAL, 829 .val = PMX_SDHCI_CD_PL_51_VAL,
830 }, { 830 }, {
831 .reg = IP_SEL_MIX_PAD_REG, 831 .reg = IP_SEL_MIX_PAD_REG,
832 .mask = PMX_SDHCI_CD_PORT_SEL_MASK, 832 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
833 .val = PMX_SDHCI_CD_PORT_51_VAL, 833 .val = PMX_SDHCI_CD_PORT_51_VAL,
834 }, 834 },
835 }; 835 };
836 836
837 #define pmx_sdhci_common_modemux \ 837 #define pmx_sdhci_common_modemux \
838 { \ 838 { \
839 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \ 839 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \
840 SMALL_PRINTERS_MODE | EXTENDED_MODE, \ 840 SMALL_PRINTERS_MODE | EXTENDED_MODE, \
841 .muxregs = sdhci_muxreg, \ 841 .muxregs = sdhci_muxreg, \
842 .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \ 842 .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \
843 }, { \ 843 }, { \
844 .modes = EXTENDED_MODE, \ 844 .modes = EXTENDED_MODE, \
845 .muxregs = sdhci_ext_muxreg, \ 845 .muxregs = sdhci_ext_muxreg, \
846 .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \ 846 .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \
847 } 847 }
848 848
849 static struct spear_modemux sdhci_modemux[][3] = { 849 static struct spear_modemux sdhci_modemux[][3] = {
850 { 850 {
851 /* select pin 12 for cd */ 851 /* select pin 12 for cd */
852 pmx_sdhci_common_modemux, 852 pmx_sdhci_common_modemux,
853 { 853 {
854 .modes = EXTENDED_MODE, 854 .modes = EXTENDED_MODE,
855 .muxregs = sdhci_cd_12_muxreg, 855 .muxregs = sdhci_cd_12_muxreg,
856 .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg), 856 .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
857 }, 857 },
858 }, { 858 }, {
859 /* select pin 51 for cd */ 859 /* select pin 51 for cd */
860 pmx_sdhci_common_modemux, 860 pmx_sdhci_common_modemux,
861 { 861 {
862 .modes = EXTENDED_MODE, 862 .modes = EXTENDED_MODE,
863 .muxregs = sdhci_cd_51_muxreg, 863 .muxregs = sdhci_cd_51_muxreg,
864 .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg), 864 .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
865 }, 865 },
866 } 866 }
867 }; 867 };
868 868
869 static struct spear_pingroup sdhci_pingroup[] = { 869 static struct spear_pingroup sdhci_pingroup[] = {
870 { 870 {
871 .name = "sdhci_cd_12_grp", 871 .name = "sdhci_cd_12_grp",
872 .pins = sdhci_cd_12_pins, 872 .pins = sdhci_cd_12_pins,
873 .npins = ARRAY_SIZE(sdhci_cd_12_pins), 873 .npins = ARRAY_SIZE(sdhci_cd_12_pins),
874 .modemuxs = sdhci_modemux[0], 874 .modemuxs = sdhci_modemux[0],
875 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]), 875 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
876 }, { 876 }, {
877 .name = "sdhci_cd_51_grp", 877 .name = "sdhci_cd_51_grp",
878 .pins = sdhci_cd_51_pins, 878 .pins = sdhci_cd_51_pins,
879 .npins = ARRAY_SIZE(sdhci_cd_51_pins), 879 .npins = ARRAY_SIZE(sdhci_cd_51_pins),
880 .modemuxs = sdhci_modemux[1], 880 .modemuxs = sdhci_modemux[1],
881 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]), 881 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
882 }, 882 },
883 }; 883 };
884 884
885 static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp", 885 static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
886 "sdhci_led_grp" }; 886 "sdhci_led_grp" };
887 887
888 static struct spear_function sdhci_function = { 888 static struct spear_function sdhci_function = {
889 .name = "sdhci", 889 .name = "sdhci",
890 .groups = sdhci_grps, 890 .groups = sdhci_grps,
891 .ngroups = ARRAY_SIZE(sdhci_grps), 891 .ngroups = ARRAY_SIZE(sdhci_grps),
892 }; 892 };
893 893
894 /* Pad multiplexing for I2S device */ 894 /* Pad multiplexing for I2S device */
895 static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 }; 895 static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
896 static struct spear_muxreg i2s_muxreg[] = { 896 static struct spear_muxreg i2s_muxreg[] = {
897 { 897 {
898 .reg = PMX_CONFIG_REG, 898 .reg = PMX_CONFIG_REG,
899 .mask = PMX_SSP_CS_MASK, 899 .mask = PMX_SSP_CS_MASK,
900 .val = 0, 900 .val = 0,
901 }, { 901 }, {
902 .reg = PMX_CONFIG_REG, 902 .reg = PMX_CONFIG_REG,
903 .mask = PMX_UART0_MODEM_MASK, 903 .mask = PMX_UART0_MODEM_MASK,
904 .val = 0, 904 .val = 0,
905 }, 905 },
906 }; 906 };
907 907
908 static struct spear_muxreg i2s_ext_muxreg[] = { 908 static struct spear_muxreg i2s_ext_muxreg[] = {
909 { 909 {
910 .reg = IP_SEL_PAD_30_39_REG, 910 .reg = IP_SEL_PAD_30_39_REG,
911 .mask = PMX_PL_35_MASK | PMX_PL_39_MASK, 911 .mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
912 .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL, 912 .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
913 }, { 913 }, {
914 .reg = IP_SEL_PAD_40_49_REG, 914 .reg = IP_SEL_PAD_40_49_REG,
915 .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK, 915 .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
916 .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL, 916 .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
917 }, 917 },
918 }; 918 };
919 919
920 static struct spear_modemux i2s_modemux[] = { 920 static struct spear_modemux i2s_modemux[] = {
921 { 921 {
922 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, 922 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
923 .muxregs = i2s_muxreg, 923 .muxregs = i2s_muxreg,
924 .nmuxregs = ARRAY_SIZE(i2s_muxreg), 924 .nmuxregs = ARRAY_SIZE(i2s_muxreg),
925 }, { 925 }, {
926 .modes = EXTENDED_MODE, 926 .modes = EXTENDED_MODE,
927 .muxregs = i2s_ext_muxreg, 927 .muxregs = i2s_ext_muxreg,
928 .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg), 928 .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
929 }, 929 },
930 }; 930 };
931 931
932 static struct spear_pingroup i2s_pingroup = { 932 static struct spear_pingroup i2s_pingroup = {
933 .name = "i2s_grp", 933 .name = "i2s_grp",
934 .pins = i2s_pins, 934 .pins = i2s_pins,
935 .npins = ARRAY_SIZE(i2s_pins), 935 .npins = ARRAY_SIZE(i2s_pins),
936 .modemuxs = i2s_modemux, 936 .modemuxs = i2s_modemux,
937 .nmodemuxs = ARRAY_SIZE(i2s_modemux), 937 .nmodemuxs = ARRAY_SIZE(i2s_modemux),
938 }; 938 };
939 939
940 static const char *const i2s_grps[] = { "i2s_grp" }; 940 static const char *const i2s_grps[] = { "i2s_grp" };
941 static struct spear_function i2s_function = { 941 static struct spear_function i2s_function = {
942 .name = "i2s", 942 .name = "i2s",
943 .groups = i2s_grps, 943 .groups = i2s_grps,
944 .ngroups = ARRAY_SIZE(i2s_grps), 944 .ngroups = ARRAY_SIZE(i2s_grps),
945 }; 945 };
946 946
947 /* Pad multiplexing for UART1 device */ 947 /* Pad multiplexing for UART1 device */
948 static const unsigned uart1_pins[] = { 28, 29 }; 948 static const unsigned uart1_pins[] = { 28, 29 };
949 static struct spear_muxreg uart1_muxreg[] = { 949 static struct spear_muxreg uart1_muxreg[] = {
950 { 950 {
951 .reg = PMX_CONFIG_REG, 951 .reg = PMX_CONFIG_REG,
952 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, 952 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
953 .val = 0, 953 .val = 0,
954 }, 954 },
955 }; 955 };
956 956
957 static struct spear_muxreg uart1_ext_muxreg[] = { 957 static struct spear_muxreg uart1_ext_muxreg[] = {
958 { 958 {
959 .reg = IP_SEL_PAD_20_29_REG, 959 .reg = IP_SEL_PAD_20_29_REG,
960 .mask = PMX_PL_28_29_MASK, 960 .mask = PMX_PL_28_29_MASK,
961 .val = PMX_UART1_PL_28_29_VAL, 961 .val = PMX_UART1_PL_28_29_VAL,
962 }, 962 },
963 }; 963 };
964 964
965 static struct spear_modemux uart1_modemux[] = { 965 static struct spear_modemux uart1_modemux[] = {
966 { 966 {
967 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE 967 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
968 | SMALL_PRINTERS_MODE | EXTENDED_MODE, 968 | SMALL_PRINTERS_MODE | EXTENDED_MODE,
969 .muxregs = uart1_muxreg, 969 .muxregs = uart1_muxreg,
970 .nmuxregs = ARRAY_SIZE(uart1_muxreg), 970 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
971 }, { 971 }, {
972 .modes = EXTENDED_MODE, 972 .modes = EXTENDED_MODE,
973 .muxregs = uart1_ext_muxreg, 973 .muxregs = uart1_ext_muxreg,
974 .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg), 974 .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
975 }, 975 },
976 }; 976 };
977 977
978 static struct spear_pingroup uart1_pingroup = { 978 static struct spear_pingroup uart1_pingroup = {
979 .name = "uart1_grp", 979 .name = "uart1_grp",
980 .pins = uart1_pins, 980 .pins = uart1_pins,
981 .npins = ARRAY_SIZE(uart1_pins), 981 .npins = ARRAY_SIZE(uart1_pins),
982 .modemuxs = uart1_modemux, 982 .modemuxs = uart1_modemux,
983 .nmodemuxs = ARRAY_SIZE(uart1_modemux), 983 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
984 }; 984 };
985 985
986 static const char *const uart1_grps[] = { "uart1_grp" }; 986 static const char *const uart1_grps[] = { "uart1_grp" };
987 static struct spear_function uart1_function = { 987 static struct spear_function uart1_function = {
988 .name = "uart1", 988 .name = "uart1",
989 .groups = uart1_grps, 989 .groups = uart1_grps,
990 .ngroups = ARRAY_SIZE(uart1_grps), 990 .ngroups = ARRAY_SIZE(uart1_grps),
991 }; 991 };
992 992
993 /* Pad multiplexing for UART1 Modem device */ 993 /* Pad multiplexing for UART1 Modem device */
994 static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 }; 994 static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
995 static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 }; 995 static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
996 static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 }; 996 static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
997 static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 }; 997 static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
998 998
999 static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = { 999 static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
1000 { 1000 {
1001 .reg = PMX_CONFIG_REG, 1001 .reg = PMX_CONFIG_REG,
1002 .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK, 1002 .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
1003 .val = 0, 1003 .val = 0,
1004 }, { 1004 }, {
1005 .reg = IP_SEL_PAD_0_9_REG, 1005 .reg = IP_SEL_PAD_0_9_REG,
1006 .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK, 1006 .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
1007 .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL | 1007 .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
1008 PMX_UART1_ENH_PL_6_7_VAL, 1008 PMX_UART1_ENH_PL_6_7_VAL,
1009 }, { 1009 }, {
1010 .reg = IP_SEL_MIX_PAD_REG, 1010 .reg = IP_SEL_MIX_PAD_REG,
1011 .mask = PMX_UART1_ENH_PORT_SEL_MASK, 1011 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1012 .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL, 1012 .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
1013 }, 1013 },
1014 }; 1014 };
1015 1015
1016 static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = { 1016 static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
1017 { 1017 {
1018 .reg = PMX_CONFIG_REG, 1018 .reg = PMX_CONFIG_REG,
1019 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | 1019 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
1020 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, 1020 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
1021 .val = 0, 1021 .val = 0,
1022 }, 1022 },
1023 }; 1023 };
1024 1024
1025 static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = { 1025 static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
1026 { 1026 {
1027 .reg = IP_SEL_PAD_30_39_REG, 1027 .reg = IP_SEL_PAD_30_39_REG,
1028 .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK | 1028 .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
1029 PMX_PL_35_MASK | PMX_PL_36_MASK, 1029 PMX_PL_35_MASK | PMX_PL_36_MASK,
1030 .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL | 1030 .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
1031 PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | 1031 PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1032 PMX_UART1_ENH_PL_36_VAL, 1032 PMX_UART1_ENH_PL_36_VAL,
1033 }, { 1033 }, {
1034 .reg = IP_SEL_MIX_PAD_REG, 1034 .reg = IP_SEL_MIX_PAD_REG,
1035 .mask = PMX_UART1_ENH_PORT_SEL_MASK, 1035 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1036 .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL, 1036 .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
1037 }, 1037 },
1038 }; 1038 };
1039 1039
1040 static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = { 1040 static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
1041 { 1041 {
1042 .reg = PMX_CONFIG_REG, 1042 .reg = PMX_CONFIG_REG,
1043 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | 1043 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
1044 PMX_SSP_CS_MASK, 1044 PMX_SSP_CS_MASK,
1045 .val = 0, 1045 .val = 0,
1046 }, 1046 },
1047 }; 1047 };
1048 1048
1049 static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = { 1049 static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
1050 { 1050 {
1051 .reg = IP_SEL_PAD_30_39_REG, 1051 .reg = IP_SEL_PAD_30_39_REG,
1052 .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK, 1052 .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
1053 .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | 1053 .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1054 PMX_UART1_ENH_PL_36_VAL, 1054 PMX_UART1_ENH_PL_36_VAL,
1055 }, { 1055 }, {
1056 .reg = IP_SEL_PAD_40_49_REG, 1056 .reg = IP_SEL_PAD_40_49_REG,
1057 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, 1057 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1058 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, 1058 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1059 }, { 1059 }, {
1060 .reg = IP_SEL_MIX_PAD_REG, 1060 .reg = IP_SEL_MIX_PAD_REG,
1061 .mask = PMX_UART1_ENH_PORT_SEL_MASK, 1061 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1062 .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL, 1062 .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
1063 }, 1063 },
1064 }; 1064 };
1065 1065
1066 static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = { 1066 static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
1067 { 1067 {
1068 .reg = IP_SEL_PAD_80_89_REG, 1068 .reg = IP_SEL_PAD_80_89_REG,
1069 .mask = PMX_PL_80_TO_85_MASK, 1069 .mask = PMX_PL_80_TO_85_MASK,
1070 .val = PMX_UART1_ENH_PL_80_TO_85_VAL, 1070 .val = PMX_UART1_ENH_PL_80_TO_85_VAL,
1071 }, { 1071 }, {
1072 .reg = IP_SEL_PAD_40_49_REG, 1072 .reg = IP_SEL_PAD_40_49_REG,
1073 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, 1073 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1074 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, 1074 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1075 }, { 1075 }, {
1076 .reg = IP_SEL_MIX_PAD_REG, 1076 .reg = IP_SEL_MIX_PAD_REG,
1077 .mask = PMX_UART1_ENH_PORT_SEL_MASK, 1077 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1078 .val = PMX_UART1_ENH_PORT_81_TO_85_VAL, 1078 .val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
1079 }, 1079 },
1080 }; 1080 };
1081 1081
1082 static struct spear_modemux uart1_modem_2_to_7_modemux[] = { 1082 static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
1083 { 1083 {
1084 .modes = EXTENDED_MODE, 1084 .modes = EXTENDED_MODE,
1085 .muxregs = uart1_modem_ext_2_to_7_muxreg, 1085 .muxregs = uart1_modem_ext_2_to_7_muxreg,
1086 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg), 1086 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
1087 }, 1087 },
1088 }; 1088 };
1089 1089
1090 static struct spear_modemux uart1_modem_31_to_36_modemux[] = { 1090 static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
1091 { 1091 {
1092 .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE, 1092 .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
1093 .muxregs = uart1_modem_31_to_36_muxreg, 1093 .muxregs = uart1_modem_31_to_36_muxreg,
1094 .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg), 1094 .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
1095 }, { 1095 }, {
1096 .modes = EXTENDED_MODE, 1096 .modes = EXTENDED_MODE,
1097 .muxregs = uart1_modem_ext_31_to_36_muxreg, 1097 .muxregs = uart1_modem_ext_31_to_36_muxreg,
1098 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg), 1098 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
1099 }, 1099 },
1100 }; 1100 };
1101 1101
1102 static struct spear_modemux uart1_modem_34_to_45_modemux[] = { 1102 static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
1103 { 1103 {
1104 .modes = AUTO_EXP_MODE | EXTENDED_MODE, 1104 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
1105 .muxregs = uart1_modem_34_to_45_muxreg, 1105 .muxregs = uart1_modem_34_to_45_muxreg,
1106 .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg), 1106 .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
1107 }, { 1107 }, {
1108 .modes = EXTENDED_MODE, 1108 .modes = EXTENDED_MODE,
1109 .muxregs = uart1_modem_ext_34_to_45_muxreg, 1109 .muxregs = uart1_modem_ext_34_to_45_muxreg,
1110 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg), 1110 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
1111 }, 1111 },
1112 }; 1112 };
1113 1113
1114 static struct spear_modemux uart1_modem_80_to_85_modemux[] = { 1114 static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
1115 { 1115 {
1116 .modes = EXTENDED_MODE, 1116 .modes = EXTENDED_MODE,
1117 .muxregs = uart1_modem_ext_80_to_85_muxreg, 1117 .muxregs = uart1_modem_ext_80_to_85_muxreg,
1118 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg), 1118 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
1119 }, 1119 },
1120 }; 1120 };
1121 1121
1122 static struct spear_pingroup uart1_modem_pingroup[] = { 1122 static struct spear_pingroup uart1_modem_pingroup[] = {
1123 { 1123 {
1124 .name = "uart1_modem_2_to_7_grp", 1124 .name = "uart1_modem_2_to_7_grp",
1125 .pins = uart1_modem_2_to_7_pins, 1125 .pins = uart1_modem_2_to_7_pins,
1126 .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins), 1126 .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
1127 .modemuxs = uart1_modem_2_to_7_modemux, 1127 .modemuxs = uart1_modem_2_to_7_modemux,
1128 .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux), 1128 .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
1129 }, { 1129 }, {
1130 .name = "uart1_modem_31_to_36_grp", 1130 .name = "uart1_modem_31_to_36_grp",
1131 .pins = uart1_modem_31_to_36_pins, 1131 .pins = uart1_modem_31_to_36_pins,
1132 .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins), 1132 .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
1133 .modemuxs = uart1_modem_31_to_36_modemux, 1133 .modemuxs = uart1_modem_31_to_36_modemux,
1134 .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux), 1134 .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
1135 }, { 1135 }, {
1136 .name = "uart1_modem_34_to_45_grp", 1136 .name = "uart1_modem_34_to_45_grp",
1137 .pins = uart1_modem_34_to_45_pins, 1137 .pins = uart1_modem_34_to_45_pins,
1138 .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins), 1138 .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
1139 .modemuxs = uart1_modem_34_to_45_modemux, 1139 .modemuxs = uart1_modem_34_to_45_modemux,
1140 .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux), 1140 .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
1141 }, { 1141 }, {
1142 .name = "uart1_modem_80_to_85_grp", 1142 .name = "uart1_modem_80_to_85_grp",
1143 .pins = uart1_modem_80_to_85_pins, 1143 .pins = uart1_modem_80_to_85_pins,
1144 .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins), 1144 .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
1145 .modemuxs = uart1_modem_80_to_85_modemux, 1145 .modemuxs = uart1_modem_80_to_85_modemux,
1146 .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux), 1146 .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
1147 }, 1147 },
1148 }; 1148 };
1149 1149
1150 static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp", 1150 static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
1151 "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp", 1151 "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
1152 "uart1_modem_80_to_85_grp" }; 1152 "uart1_modem_80_to_85_grp" };
1153 static struct spear_function uart1_modem_function = { 1153 static struct spear_function uart1_modem_function = {
1154 .name = "uart1_modem", 1154 .name = "uart1_modem",
1155 .groups = uart1_modem_grps, 1155 .groups = uart1_modem_grps,
1156 .ngroups = ARRAY_SIZE(uart1_modem_grps), 1156 .ngroups = ARRAY_SIZE(uart1_modem_grps),
1157 }; 1157 };
1158 1158
1159 /* Pad multiplexing for UART2 device */ 1159 /* Pad multiplexing for UART2 device */
1160 static const unsigned uart2_pins[] = { 0, 1 }; 1160 static const unsigned uart2_pins[] = { 0, 1 };
1161 static struct spear_muxreg uart2_muxreg[] = { 1161 static struct spear_muxreg uart2_muxreg[] = {
1162 { 1162 {
1163 .reg = PMX_CONFIG_REG, 1163 .reg = PMX_CONFIG_REG,
1164 .mask = PMX_FIRDA_MASK, 1164 .mask = PMX_FIRDA_MASK,
1165 .val = 0, 1165 .val = 0,
1166 }, 1166 },
1167 }; 1167 };
1168 1168
1169 static struct spear_muxreg uart2_ext_muxreg[] = { 1169 static struct spear_muxreg uart2_ext_muxreg[] = {
1170 { 1170 {
1171 .reg = IP_SEL_PAD_0_9_REG, 1171 .reg = IP_SEL_PAD_0_9_REG,
1172 .mask = PMX_PL_0_1_MASK, 1172 .mask = PMX_PL_0_1_MASK,
1173 .val = PMX_UART2_PL_0_1_VAL, 1173 .val = PMX_UART2_PL_0_1_VAL,
1174 }, 1174 },
1175 }; 1175 };
1176 1176
1177 static struct spear_modemux uart2_modemux[] = { 1177 static struct spear_modemux uart2_modemux[] = {
1178 { 1178 {
1179 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE 1179 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1180 | SMALL_PRINTERS_MODE | EXTENDED_MODE, 1180 | SMALL_PRINTERS_MODE | EXTENDED_MODE,
1181 .muxregs = uart2_muxreg, 1181 .muxregs = uart2_muxreg,
1182 .nmuxregs = ARRAY_SIZE(uart2_muxreg), 1182 .nmuxregs = ARRAY_SIZE(uart2_muxreg),
1183 }, { 1183 }, {
1184 .modes = EXTENDED_MODE, 1184 .modes = EXTENDED_MODE,
1185 .muxregs = uart2_ext_muxreg, 1185 .muxregs = uart2_ext_muxreg,
1186 .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg), 1186 .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
1187 }, 1187 },
1188 }; 1188 };
1189 1189
1190 static struct spear_pingroup uart2_pingroup = { 1190 static struct spear_pingroup uart2_pingroup = {
1191 .name = "uart2_grp", 1191 .name = "uart2_grp",
1192 .pins = uart2_pins, 1192 .pins = uart2_pins,
1193 .npins = ARRAY_SIZE(uart2_pins), 1193 .npins = ARRAY_SIZE(uart2_pins),
1194 .modemuxs = uart2_modemux, 1194 .modemuxs = uart2_modemux,
1195 .nmodemuxs = ARRAY_SIZE(uart2_modemux), 1195 .nmodemuxs = ARRAY_SIZE(uart2_modemux),
1196 }; 1196 };
1197 1197
1198 static const char *const uart2_grps[] = { "uart2_grp" }; 1198 static const char *const uart2_grps[] = { "uart2_grp" };
1199 static struct spear_function uart2_function = { 1199 static struct spear_function uart2_function = {
1200 .name = "uart2", 1200 .name = "uart2",
1201 .groups = uart2_grps, 1201 .groups = uart2_grps,
1202 .ngroups = ARRAY_SIZE(uart2_grps), 1202 .ngroups = ARRAY_SIZE(uart2_grps),
1203 }; 1203 };
1204 1204
1205 /* Pad multiplexing for uart3 device */ 1205 /* Pad multiplexing for uart3 device */
1206 static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 }, 1206 static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
1207 { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } }; 1207 { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
1208 1208
1209 static struct spear_muxreg uart3_ext_8_9_muxreg[] = { 1209 static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
1210 { 1210 {
1211 .reg = PMX_CONFIG_REG, 1211 .reg = PMX_CONFIG_REG,
1212 .mask = PMX_SSP_MASK, 1212 .mask = PMX_SSP_MASK,
1213 .val = 0, 1213 .val = 0,
1214 }, { 1214 }, {
1215 .reg = IP_SEL_PAD_0_9_REG, 1215 .reg = IP_SEL_PAD_0_9_REG,
1216 .mask = PMX_PL_8_9_MASK, 1216 .mask = PMX_PL_8_9_MASK,
1217 .val = PMX_UART3_PL_8_9_VAL, 1217 .val = PMX_UART3_PL_8_9_VAL,
1218 }, { 1218 }, {
1219 .reg = IP_SEL_MIX_PAD_REG, 1219 .reg = IP_SEL_MIX_PAD_REG,
1220 .mask = PMX_UART3_PORT_SEL_MASK, 1220 .mask = PMX_UART3_PORT_SEL_MASK,
1221 .val = PMX_UART3_PORT_8_VAL, 1221 .val = PMX_UART3_PORT_8_VAL,
1222 }, 1222 },
1223 }; 1223 };
1224 1224
1225 static struct spear_muxreg uart3_ext_15_16_muxreg[] = { 1225 static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
1226 { 1226 {
1227 .reg = PMX_CONFIG_REG, 1227 .reg = PMX_CONFIG_REG,
1228 .mask = PMX_MII_MASK, 1228 .mask = PMX_MII_MASK,
1229 .val = 0, 1229 .val = 0,
1230 }, { 1230 }, {
1231 .reg = IP_SEL_PAD_10_19_REG, 1231 .reg = IP_SEL_PAD_10_19_REG,
1232 .mask = PMX_PL_15_16_MASK, 1232 .mask = PMX_PL_15_16_MASK,
1233 .val = PMX_UART3_PL_15_16_VAL, 1233 .val = PMX_UART3_PL_15_16_VAL,
1234 }, { 1234 }, {
1235 .reg = IP_SEL_MIX_PAD_REG, 1235 .reg = IP_SEL_MIX_PAD_REG,
1236 .mask = PMX_UART3_PORT_SEL_MASK, 1236 .mask = PMX_UART3_PORT_SEL_MASK,
1237 .val = PMX_UART3_PORT_15_VAL, 1237 .val = PMX_UART3_PORT_15_VAL,
1238 }, 1238 },
1239 }; 1239 };
1240 1240
1241 static struct spear_muxreg uart3_ext_41_42_muxreg[] = { 1241 static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
1242 { 1242 {
1243 .reg = PMX_CONFIG_REG, 1243 .reg = PMX_CONFIG_REG,
1244 .mask = PMX_UART0_MODEM_MASK, 1244 .mask = PMX_UART0_MODEM_MASK,
1245 .val = 0, 1245 .val = 0,
1246 }, { 1246 }, {
1247 .reg = IP_SEL_PAD_40_49_REG, 1247 .reg = IP_SEL_PAD_40_49_REG,
1248 .mask = PMX_PL_41_42_MASK, 1248 .mask = PMX_PL_41_42_MASK,
1249 .val = PMX_UART3_PL_41_42_VAL, 1249 .val = PMX_UART3_PL_41_42_VAL,
1250 }, { 1250 }, {
1251 .reg = IP_SEL_MIX_PAD_REG, 1251 .reg = IP_SEL_MIX_PAD_REG,
1252 .mask = PMX_UART3_PORT_SEL_MASK, 1252 .mask = PMX_UART3_PORT_SEL_MASK,
1253 .val = PMX_UART3_PORT_41_VAL, 1253 .val = PMX_UART3_PORT_41_VAL,
1254 }, 1254 },
1255 }; 1255 };
1256 1256
1257 static struct spear_muxreg uart3_ext_52_53_muxreg[] = { 1257 static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
1258 { 1258 {
1259 .reg = IP_SEL_PAD_50_59_REG, 1259 .reg = IP_SEL_PAD_50_59_REG,
1260 .mask = PMX_PL_52_53_MASK, 1260 .mask = PMX_PL_52_53_MASK,
1261 .val = PMX_UART3_PL_52_53_VAL, 1261 .val = PMX_UART3_PL_52_53_VAL,
1262 }, { 1262 }, {
1263 .reg = IP_SEL_MIX_PAD_REG, 1263 .reg = IP_SEL_MIX_PAD_REG,
1264 .mask = PMX_UART3_PORT_SEL_MASK, 1264 .mask = PMX_UART3_PORT_SEL_MASK,
1265 .val = PMX_UART3_PORT_52_VAL, 1265 .val = PMX_UART3_PORT_52_VAL,
1266 }, 1266 },
1267 }; 1267 };
1268 1268
1269 static struct spear_muxreg uart3_ext_73_74_muxreg[] = { 1269 static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
1270 { 1270 {
1271 .reg = IP_SEL_PAD_70_79_REG, 1271 .reg = IP_SEL_PAD_70_79_REG,
1272 .mask = PMX_PL_73_MASK | PMX_PL_74_MASK, 1272 .mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
1273 .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL, 1273 .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
1274 }, { 1274 }, {
1275 .reg = IP_SEL_MIX_PAD_REG, 1275 .reg = IP_SEL_MIX_PAD_REG,
1276 .mask = PMX_UART3_PORT_SEL_MASK, 1276 .mask = PMX_UART3_PORT_SEL_MASK,
1277 .val = PMX_UART3_PORT_73_VAL, 1277 .val = PMX_UART3_PORT_73_VAL,
1278 }, 1278 },
1279 }; 1279 };
1280 1280
1281 static struct spear_muxreg uart3_ext_94_95_muxreg[] = { 1281 static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
1282 { 1282 {
1283 .reg = IP_SEL_PAD_90_99_REG, 1283 .reg = IP_SEL_PAD_90_99_REG,
1284 .mask = PMX_PL_94_95_MASK, 1284 .mask = PMX_PL_94_95_MASK,
1285 .val = PMX_UART3_PL_94_95_VAL, 1285 .val = PMX_UART3_PL_94_95_VAL,
1286 }, { 1286 }, {
1287 .reg = IP_SEL_MIX_PAD_REG, 1287 .reg = IP_SEL_MIX_PAD_REG,
1288 .mask = PMX_UART3_PORT_SEL_MASK, 1288 .mask = PMX_UART3_PORT_SEL_MASK,
1289 .val = PMX_UART3_PORT_94_VAL, 1289 .val = PMX_UART3_PORT_94_VAL,
1290 }, 1290 },
1291 }; 1291 };
1292 1292
1293 static struct spear_muxreg uart3_ext_98_99_muxreg[] = { 1293 static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
1294 { 1294 {
1295 .reg = IP_SEL_PAD_90_99_REG, 1295 .reg = IP_SEL_PAD_90_99_REG,
1296 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, 1296 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
1297 .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL, 1297 .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
1298 }, { 1298 }, {
1299 .reg = IP_SEL_MIX_PAD_REG, 1299 .reg = IP_SEL_MIX_PAD_REG,
1300 .mask = PMX_UART3_PORT_SEL_MASK, 1300 .mask = PMX_UART3_PORT_SEL_MASK,
1301 .val = PMX_UART3_PORT_99_VAL, 1301 .val = PMX_UART3_PORT_99_VAL,
1302 }, 1302 },
1303 }; 1303 };
1304 1304
1305 static struct spear_modemux uart3_modemux[][1] = { 1305 static struct spear_modemux uart3_modemux[][1] = {
1306 { 1306 {
1307 /* Select signals on pins 8_9 */ 1307 /* Select signals on pins 8_9 */
1308 { 1308 {
1309 .modes = EXTENDED_MODE, 1309 .modes = EXTENDED_MODE,
1310 .muxregs = uart3_ext_8_9_muxreg, 1310 .muxregs = uart3_ext_8_9_muxreg,
1311 .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg), 1311 .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
1312 }, 1312 },
1313 }, { 1313 }, {
1314 /* Select signals on pins 15_16 */ 1314 /* Select signals on pins 15_16 */
1315 { 1315 {
1316 .modes = EXTENDED_MODE, 1316 .modes = EXTENDED_MODE,
1317 .muxregs = uart3_ext_15_16_muxreg, 1317 .muxregs = uart3_ext_15_16_muxreg,
1318 .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg), 1318 .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
1319 }, 1319 },
1320 }, { 1320 }, {
1321 /* Select signals on pins 41_42 */ 1321 /* Select signals on pins 41_42 */
1322 { 1322 {
1323 .modes = EXTENDED_MODE, 1323 .modes = EXTENDED_MODE,
1324 .muxregs = uart3_ext_41_42_muxreg, 1324 .muxregs = uart3_ext_41_42_muxreg,
1325 .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg), 1325 .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
1326 }, 1326 },
1327 }, { 1327 }, {
1328 /* Select signals on pins 52_53 */ 1328 /* Select signals on pins 52_53 */
1329 { 1329 {
1330 .modes = EXTENDED_MODE, 1330 .modes = EXTENDED_MODE,
1331 .muxregs = uart3_ext_52_53_muxreg, 1331 .muxregs = uart3_ext_52_53_muxreg,
1332 .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg), 1332 .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
1333 }, 1333 },
1334 }, { 1334 }, {
1335 /* Select signals on pins 73_74 */ 1335 /* Select signals on pins 73_74 */
1336 { 1336 {
1337 .modes = EXTENDED_MODE, 1337 .modes = EXTENDED_MODE,
1338 .muxregs = uart3_ext_73_74_muxreg, 1338 .muxregs = uart3_ext_73_74_muxreg,
1339 .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg), 1339 .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
1340 }, 1340 },
1341 }, { 1341 }, {
1342 /* Select signals on pins 94_95 */ 1342 /* Select signals on pins 94_95 */
1343 { 1343 {
1344 .modes = EXTENDED_MODE, 1344 .modes = EXTENDED_MODE,
1345 .muxregs = uart3_ext_94_95_muxreg, 1345 .muxregs = uart3_ext_94_95_muxreg,
1346 .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg), 1346 .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
1347 }, 1347 },
1348 }, { 1348 }, {
1349 /* Select signals on pins 98_99 */ 1349 /* Select signals on pins 98_99 */
1350 { 1350 {
1351 .modes = EXTENDED_MODE, 1351 .modes = EXTENDED_MODE,
1352 .muxregs = uart3_ext_98_99_muxreg, 1352 .muxregs = uart3_ext_98_99_muxreg,
1353 .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg), 1353 .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
1354 }, 1354 },
1355 }, 1355 },
1356 }; 1356 };
1357 1357
1358 static struct spear_pingroup uart3_pingroup[] = { 1358 static struct spear_pingroup uart3_pingroup[] = {
1359 { 1359 {
1360 .name = "uart3_8_9_grp", 1360 .name = "uart3_8_9_grp",
1361 .pins = uart3_pins[0], 1361 .pins = uart3_pins[0],
1362 .npins = ARRAY_SIZE(uart3_pins[0]), 1362 .npins = ARRAY_SIZE(uart3_pins[0]),
1363 .modemuxs = uart3_modemux[0], 1363 .modemuxs = uart3_modemux[0],
1364 .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]), 1364 .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
1365 }, { 1365 }, {
1366 .name = "uart3_15_16_grp", 1366 .name = "uart3_15_16_grp",
1367 .pins = uart3_pins[1], 1367 .pins = uart3_pins[1],
1368 .npins = ARRAY_SIZE(uart3_pins[1]), 1368 .npins = ARRAY_SIZE(uart3_pins[1]),
1369 .modemuxs = uart3_modemux[1], 1369 .modemuxs = uart3_modemux[1],
1370 .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]), 1370 .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
1371 }, { 1371 }, {
1372 .name = "uart3_41_42_grp", 1372 .name = "uart3_41_42_grp",
1373 .pins = uart3_pins[2], 1373 .pins = uart3_pins[2],
1374 .npins = ARRAY_SIZE(uart3_pins[2]), 1374 .npins = ARRAY_SIZE(uart3_pins[2]),
1375 .modemuxs = uart3_modemux[2], 1375 .modemuxs = uart3_modemux[2],
1376 .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]), 1376 .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
1377 }, { 1377 }, {
1378 .name = "uart3_52_53_grp", 1378 .name = "uart3_52_53_grp",
1379 .pins = uart3_pins[3], 1379 .pins = uart3_pins[3],
1380 .npins = ARRAY_SIZE(uart3_pins[3]), 1380 .npins = ARRAY_SIZE(uart3_pins[3]),
1381 .modemuxs = uart3_modemux[3], 1381 .modemuxs = uart3_modemux[3],
1382 .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]), 1382 .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
1383 }, { 1383 }, {
1384 .name = "uart3_73_74_grp", 1384 .name = "uart3_73_74_grp",
1385 .pins = uart3_pins[4], 1385 .pins = uart3_pins[4],
1386 .npins = ARRAY_SIZE(uart3_pins[4]), 1386 .npins = ARRAY_SIZE(uart3_pins[4]),
1387 .modemuxs = uart3_modemux[4], 1387 .modemuxs = uart3_modemux[4],
1388 .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]), 1388 .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
1389 }, { 1389 }, {
1390 .name = "uart3_94_95_grp", 1390 .name = "uart3_94_95_grp",
1391 .pins = uart3_pins[5], 1391 .pins = uart3_pins[5],
1392 .npins = ARRAY_SIZE(uart3_pins[5]), 1392 .npins = ARRAY_SIZE(uart3_pins[5]),
1393 .modemuxs = uart3_modemux[5], 1393 .modemuxs = uart3_modemux[5],
1394 .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]), 1394 .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
1395 }, { 1395 }, {
1396 .name = "uart3_98_99_grp", 1396 .name = "uart3_98_99_grp",
1397 .pins = uart3_pins[6], 1397 .pins = uart3_pins[6],
1398 .npins = ARRAY_SIZE(uart3_pins[6]), 1398 .npins = ARRAY_SIZE(uart3_pins[6]),
1399 .modemuxs = uart3_modemux[6], 1399 .modemuxs = uart3_modemux[6],
1400 .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]), 1400 .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
1401 }, 1401 },
1402 }; 1402 };
1403 1403
1404 static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp", 1404 static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
1405 "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp", 1405 "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
1406 "uart3_94_95_grp", "uart3_98_99_grp" }; 1406 "uart3_94_95_grp", "uart3_98_99_grp" };
1407 1407
1408 static struct spear_function uart3_function = { 1408 static struct spear_function uart3_function = {
1409 .name = "uart3", 1409 .name = "uart3",
1410 .groups = uart3_grps, 1410 .groups = uart3_grps,
1411 .ngroups = ARRAY_SIZE(uart3_grps), 1411 .ngroups = ARRAY_SIZE(uart3_grps),
1412 }; 1412 };
1413 1413
1414 /* Pad multiplexing for uart4 device */ 1414 /* Pad multiplexing for uart4 device */
1415 static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 }, 1415 static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
1416 { 71, 72 }, { 92, 93 }, { 100, 101 } }; 1416 { 71, 72 }, { 92, 93 }, { 100, 101 } };
1417 1417
1418 static struct spear_muxreg uart4_ext_6_7_muxreg[] = { 1418 static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
1419 { 1419 {
1420 .reg = PMX_CONFIG_REG, 1420 .reg = PMX_CONFIG_REG,
1421 .mask = PMX_SSP_MASK, 1421 .mask = PMX_SSP_MASK,
1422 .val = 0, 1422 .val = 0,
1423 }, { 1423 }, {
1424 .reg = IP_SEL_PAD_0_9_REG, 1424 .reg = IP_SEL_PAD_0_9_REG,
1425 .mask = PMX_PL_6_7_MASK, 1425 .mask = PMX_PL_6_7_MASK,
1426 .val = PMX_UART4_PL_6_7_VAL, 1426 .val = PMX_UART4_PL_6_7_VAL,
1427 }, { 1427 }, {
1428 .reg = IP_SEL_MIX_PAD_REG, 1428 .reg = IP_SEL_MIX_PAD_REG,
1429 .mask = PMX_UART4_PORT_SEL_MASK, 1429 .mask = PMX_UART4_PORT_SEL_MASK,
1430 .val = PMX_UART4_PORT_6_VAL, 1430 .val = PMX_UART4_PORT_6_VAL,
1431 }, 1431 },
1432 }; 1432 };
1433 1433
1434 static struct spear_muxreg uart4_ext_13_14_muxreg[] = { 1434 static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
1435 { 1435 {
1436 .reg = PMX_CONFIG_REG, 1436 .reg = PMX_CONFIG_REG,
1437 .mask = PMX_MII_MASK, 1437 .mask = PMX_MII_MASK,
1438 .val = 0, 1438 .val = 0,
1439 }, { 1439 }, {
1440 .reg = IP_SEL_PAD_10_19_REG, 1440 .reg = IP_SEL_PAD_10_19_REG,
1441 .mask = PMX_PL_13_14_MASK, 1441 .mask = PMX_PL_13_14_MASK,
1442 .val = PMX_UART4_PL_13_14_VAL, 1442 .val = PMX_UART4_PL_13_14_VAL,
1443 }, { 1443 }, {
1444 .reg = IP_SEL_MIX_PAD_REG, 1444 .reg = IP_SEL_MIX_PAD_REG,
1445 .mask = PMX_UART4_PORT_SEL_MASK, 1445 .mask = PMX_UART4_PORT_SEL_MASK,
1446 .val = PMX_UART4_PORT_13_VAL, 1446 .val = PMX_UART4_PORT_13_VAL,
1447 }, 1447 },
1448 }; 1448 };
1449 1449
1450 static struct spear_muxreg uart4_ext_39_40_muxreg[] = { 1450 static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
1451 { 1451 {
1452 .reg = PMX_CONFIG_REG, 1452 .reg = PMX_CONFIG_REG,
1453 .mask = PMX_UART0_MODEM_MASK, 1453 .mask = PMX_UART0_MODEM_MASK,
1454 .val = 0, 1454 .val = 0,
1455 }, { 1455 }, {
1456 .reg = IP_SEL_PAD_30_39_REG, 1456 .reg = IP_SEL_PAD_30_39_REG,
1457 .mask = PMX_PL_39_MASK, 1457 .mask = PMX_PL_39_MASK,
1458 .val = PMX_UART4_PL_39_VAL, 1458 .val = PMX_UART4_PL_39_VAL,
1459 }, { 1459 }, {
1460 .reg = IP_SEL_PAD_40_49_REG, 1460 .reg = IP_SEL_PAD_40_49_REG,
1461 .mask = PMX_PL_40_MASK, 1461 .mask = PMX_PL_40_MASK,
1462 .val = PMX_UART4_PL_40_VAL, 1462 .val = PMX_UART4_PL_40_VAL,
1463 }, { 1463 }, {
1464 .reg = IP_SEL_MIX_PAD_REG, 1464 .reg = IP_SEL_MIX_PAD_REG,
1465 .mask = PMX_UART4_PORT_SEL_MASK, 1465 .mask = PMX_UART4_PORT_SEL_MASK,
1466 .val = PMX_UART4_PORT_39_VAL, 1466 .val = PMX_UART4_PORT_39_VAL,
1467 }, 1467 },
1468 }; 1468 };
1469 1469
1470 static struct spear_muxreg uart4_ext_71_72_muxreg[] = { 1470 static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
1471 { 1471 {
1472 .reg = IP_SEL_PAD_70_79_REG, 1472 .reg = IP_SEL_PAD_70_79_REG,
1473 .mask = PMX_PL_71_72_MASK, 1473 .mask = PMX_PL_71_72_MASK,
1474 .val = PMX_UART4_PL_71_72_VAL, 1474 .val = PMX_UART4_PL_71_72_VAL,
1475 }, { 1475 }, {
1476 .reg = IP_SEL_MIX_PAD_REG, 1476 .reg = IP_SEL_MIX_PAD_REG,
1477 .mask = PMX_UART4_PORT_SEL_MASK, 1477 .mask = PMX_UART4_PORT_SEL_MASK,
1478 .val = PMX_UART4_PORT_71_VAL, 1478 .val = PMX_UART4_PORT_71_VAL,
1479 }, 1479 },
1480 }; 1480 };
1481 1481
1482 static struct spear_muxreg uart4_ext_92_93_muxreg[] = { 1482 static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
1483 { 1483 {
1484 .reg = IP_SEL_PAD_90_99_REG, 1484 .reg = IP_SEL_PAD_90_99_REG,
1485 .mask = PMX_PL_92_93_MASK, 1485 .mask = PMX_PL_92_93_MASK,
1486 .val = PMX_UART4_PL_92_93_VAL, 1486 .val = PMX_UART4_PL_92_93_VAL,
1487 }, { 1487 }, {
1488 .reg = IP_SEL_MIX_PAD_REG, 1488 .reg = IP_SEL_MIX_PAD_REG,
1489 .mask = PMX_UART4_PORT_SEL_MASK, 1489 .mask = PMX_UART4_PORT_SEL_MASK,
1490 .val = PMX_UART4_PORT_92_VAL, 1490 .val = PMX_UART4_PORT_92_VAL,
1491 }, 1491 },
1492 }; 1492 };
1493 1493
1494 static struct spear_muxreg uart4_ext_100_101_muxreg[] = { 1494 static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
1495 { 1495 {
1496 .reg = IP_SEL_MIX_PAD_REG, 1496 .reg = IP_SEL_MIX_PAD_REG,
1497 .mask = PMX_PL_100_101_MASK | 1497 .mask = PMX_PL_100_101_MASK |
1498 PMX_UART4_PORT_SEL_MASK, 1498 PMX_UART4_PORT_SEL_MASK,
1499 .val = PMX_UART4_PL_100_101_VAL | 1499 .val = PMX_UART4_PL_100_101_VAL |
1500 PMX_UART4_PORT_101_VAL, 1500 PMX_UART4_PORT_101_VAL,
1501 }, 1501 },
1502 }; 1502 };
1503 1503
1504 static struct spear_modemux uart4_modemux[][1] = { 1504 static struct spear_modemux uart4_modemux[][1] = {
1505 { 1505 {
1506 /* Select signals on pins 6_7 */ 1506 /* Select signals on pins 6_7 */
1507 { 1507 {
1508 .modes = EXTENDED_MODE, 1508 .modes = EXTENDED_MODE,
1509 .muxregs = uart4_ext_6_7_muxreg, 1509 .muxregs = uart4_ext_6_7_muxreg,
1510 .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg), 1510 .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
1511 }, 1511 },
1512 }, { 1512 }, {
1513 /* Select signals on pins 13_14 */ 1513 /* Select signals on pins 13_14 */
1514 { 1514 {
1515 .modes = EXTENDED_MODE, 1515 .modes = EXTENDED_MODE,
1516 .muxregs = uart4_ext_13_14_muxreg, 1516 .muxregs = uart4_ext_13_14_muxreg,
1517 .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg), 1517 .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
1518 }, 1518 },
1519 }, { 1519 }, {
1520 /* Select signals on pins 39_40 */ 1520 /* Select signals on pins 39_40 */
1521 { 1521 {
1522 .modes = EXTENDED_MODE, 1522 .modes = EXTENDED_MODE,
1523 .muxregs = uart4_ext_39_40_muxreg, 1523 .muxregs = uart4_ext_39_40_muxreg,
1524 .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg), 1524 .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
1525 }, 1525 },
1526 }, { 1526 }, {
1527 /* Select signals on pins 71_72 */ 1527 /* Select signals on pins 71_72 */
1528 { 1528 {
1529 .modes = EXTENDED_MODE, 1529 .modes = EXTENDED_MODE,
1530 .muxregs = uart4_ext_71_72_muxreg, 1530 .muxregs = uart4_ext_71_72_muxreg,
1531 .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg), 1531 .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
1532 }, 1532 },
1533 }, { 1533 }, {
1534 /* Select signals on pins 92_93 */ 1534 /* Select signals on pins 92_93 */
1535 { 1535 {
1536 .modes = EXTENDED_MODE, 1536 .modes = EXTENDED_MODE,
1537 .muxregs = uart4_ext_92_93_muxreg, 1537 .muxregs = uart4_ext_92_93_muxreg,
1538 .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg), 1538 .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
1539 }, 1539 },
1540 }, { 1540 }, {
1541 /* Select signals on pins 100_101_ */ 1541 /* Select signals on pins 100_101_ */
1542 { 1542 {
1543 .modes = EXTENDED_MODE, 1543 .modes = EXTENDED_MODE,
1544 .muxregs = uart4_ext_100_101_muxreg, 1544 .muxregs = uart4_ext_100_101_muxreg,
1545 .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg), 1545 .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
1546 }, 1546 },
1547 }, 1547 },
1548 }; 1548 };
1549 1549
1550 static struct spear_pingroup uart4_pingroup[] = { 1550 static struct spear_pingroup uart4_pingroup[] = {
1551 { 1551 {
1552 .name = "uart4_6_7_grp", 1552 .name = "uart4_6_7_grp",
1553 .pins = uart4_pins[0], 1553 .pins = uart4_pins[0],
1554 .npins = ARRAY_SIZE(uart4_pins[0]), 1554 .npins = ARRAY_SIZE(uart4_pins[0]),
1555 .modemuxs = uart4_modemux[0], 1555 .modemuxs = uart4_modemux[0],
1556 .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]), 1556 .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
1557 }, { 1557 }, {
1558 .name = "uart4_13_14_grp", 1558 .name = "uart4_13_14_grp",
1559 .pins = uart4_pins[1], 1559 .pins = uart4_pins[1],
1560 .npins = ARRAY_SIZE(uart4_pins[1]), 1560 .npins = ARRAY_SIZE(uart4_pins[1]),
1561 .modemuxs = uart4_modemux[1], 1561 .modemuxs = uart4_modemux[1],
1562 .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]), 1562 .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
1563 }, { 1563 }, {
1564 .name = "uart4_39_40_grp", 1564 .name = "uart4_39_40_grp",
1565 .pins = uart4_pins[2], 1565 .pins = uart4_pins[2],
1566 .npins = ARRAY_SIZE(uart4_pins[2]), 1566 .npins = ARRAY_SIZE(uart4_pins[2]),
1567 .modemuxs = uart4_modemux[2], 1567 .modemuxs = uart4_modemux[2],
1568 .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]), 1568 .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
1569 }, { 1569 }, {
1570 .name = "uart4_71_72_grp", 1570 .name = "uart4_71_72_grp",
1571 .pins = uart4_pins[3], 1571 .pins = uart4_pins[3],
1572 .npins = ARRAY_SIZE(uart4_pins[3]), 1572 .npins = ARRAY_SIZE(uart4_pins[3]),
1573 .modemuxs = uart4_modemux[3], 1573 .modemuxs = uart4_modemux[3],
1574 .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]), 1574 .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
1575 }, { 1575 }, {
1576 .name = "uart4_92_93_grp", 1576 .name = "uart4_92_93_grp",
1577 .pins = uart4_pins[4], 1577 .pins = uart4_pins[4],
1578 .npins = ARRAY_SIZE(uart4_pins[4]), 1578 .npins = ARRAY_SIZE(uart4_pins[4]),
1579 .modemuxs = uart4_modemux[4], 1579 .modemuxs = uart4_modemux[4],
1580 .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]), 1580 .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
1581 }, { 1581 }, {
1582 .name = "uart4_100_101_grp", 1582 .name = "uart4_100_101_grp",
1583 .pins = uart4_pins[5], 1583 .pins = uart4_pins[5],
1584 .npins = ARRAY_SIZE(uart4_pins[5]), 1584 .npins = ARRAY_SIZE(uart4_pins[5]),
1585 .modemuxs = uart4_modemux[5], 1585 .modemuxs = uart4_modemux[5],
1586 .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]), 1586 .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
1587 }, 1587 },
1588 }; 1588 };
1589 1589
1590 static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp", 1590 static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
1591 "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp", 1591 "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
1592 "uart4_100_101_grp" }; 1592 "uart4_100_101_grp" };
1593 1593
1594 static struct spear_function uart4_function = { 1594 static struct spear_function uart4_function = {
1595 .name = "uart4", 1595 .name = "uart4",
1596 .groups = uart4_grps, 1596 .groups = uart4_grps,
1597 .ngroups = ARRAY_SIZE(uart4_grps), 1597 .ngroups = ARRAY_SIZE(uart4_grps),
1598 }; 1598 };
1599 1599
1600 /* Pad multiplexing for uart5 device */ 1600 /* Pad multiplexing for uart5 device */
1601 static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 }, 1601 static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
1602 { 90, 91 } }; 1602 { 90, 91 } };
1603 1603
1604 static struct spear_muxreg uart5_ext_4_5_muxreg[] = { 1604 static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
1605 { 1605 {
1606 .reg = PMX_CONFIG_REG, 1606 .reg = PMX_CONFIG_REG,
1607 .mask = PMX_I2C_MASK, 1607 .mask = PMX_I2C_MASK,
1608 .val = 0, 1608 .val = 0,
1609 }, { 1609 }, {
1610 .reg = IP_SEL_PAD_0_9_REG, 1610 .reg = IP_SEL_PAD_0_9_REG,
1611 .mask = PMX_PL_4_5_MASK, 1611 .mask = PMX_PL_4_5_MASK,
1612 .val = PMX_UART5_PL_4_5_VAL, 1612 .val = PMX_UART5_PL_4_5_VAL,
1613 }, { 1613 }, {
1614 .reg = IP_SEL_MIX_PAD_REG, 1614 .reg = IP_SEL_MIX_PAD_REG,
1615 .mask = PMX_UART5_PORT_SEL_MASK, 1615 .mask = PMX_UART5_PORT_SEL_MASK,
1616 .val = PMX_UART5_PORT_4_VAL, 1616 .val = PMX_UART5_PORT_4_VAL,
1617 }, 1617 },
1618 }; 1618 };
1619 1619
1620 static struct spear_muxreg uart5_ext_37_38_muxreg[] = { 1620 static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
1621 { 1621 {
1622 .reg = PMX_CONFIG_REG, 1622 .reg = PMX_CONFIG_REG,
1623 .mask = PMX_UART0_MODEM_MASK, 1623 .mask = PMX_UART0_MODEM_MASK,
1624 .val = 0, 1624 .val = 0,
1625 }, { 1625 }, {
1626 .reg = IP_SEL_PAD_30_39_REG, 1626 .reg = IP_SEL_PAD_30_39_REG,
1627 .mask = PMX_PL_37_38_MASK, 1627 .mask = PMX_PL_37_38_MASK,
1628 .val = PMX_UART5_PL_37_38_VAL, 1628 .val = PMX_UART5_PL_37_38_VAL,
1629 }, { 1629 }, {
1630 .reg = IP_SEL_MIX_PAD_REG, 1630 .reg = IP_SEL_MIX_PAD_REG,
1631 .mask = PMX_UART5_PORT_SEL_MASK, 1631 .mask = PMX_UART5_PORT_SEL_MASK,
1632 .val = PMX_UART5_PORT_37_VAL, 1632 .val = PMX_UART5_PORT_37_VAL,
1633 }, 1633 },
1634 }; 1634 };
1635 1635
1636 static struct spear_muxreg uart5_ext_69_70_muxreg[] = { 1636 static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
1637 { 1637 {
1638 .reg = IP_SEL_PAD_60_69_REG, 1638 .reg = IP_SEL_PAD_60_69_REG,
1639 .mask = PMX_PL_69_MASK, 1639 .mask = PMX_PL_69_MASK,
1640 .val = PMX_UART5_PL_69_VAL, 1640 .val = PMX_UART5_PL_69_VAL,
1641 }, { 1641 }, {
1642 .reg = IP_SEL_PAD_70_79_REG, 1642 .reg = IP_SEL_PAD_70_79_REG,
1643 .mask = PMX_PL_70_MASK, 1643 .mask = PMX_PL_70_MASK,
1644 .val = PMX_UART5_PL_70_VAL, 1644 .val = PMX_UART5_PL_70_VAL,
1645 }, { 1645 }, {
1646 .reg = IP_SEL_MIX_PAD_REG, 1646 .reg = IP_SEL_MIX_PAD_REG,
1647 .mask = PMX_UART5_PORT_SEL_MASK, 1647 .mask = PMX_UART5_PORT_SEL_MASK,
1648 .val = PMX_UART5_PORT_69_VAL, 1648 .val = PMX_UART5_PORT_69_VAL,
1649 }, 1649 },
1650 }; 1650 };
1651 1651
1652 static struct spear_muxreg uart5_ext_90_91_muxreg[] = { 1652 static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
1653 { 1653 {
1654 .reg = IP_SEL_PAD_90_99_REG, 1654 .reg = IP_SEL_PAD_90_99_REG,
1655 .mask = PMX_PL_90_91_MASK, 1655 .mask = PMX_PL_90_91_MASK,
1656 .val = PMX_UART5_PL_90_91_VAL, 1656 .val = PMX_UART5_PL_90_91_VAL,
1657 }, { 1657 }, {
1658 .reg = IP_SEL_MIX_PAD_REG, 1658 .reg = IP_SEL_MIX_PAD_REG,
1659 .mask = PMX_UART5_PORT_SEL_MASK, 1659 .mask = PMX_UART5_PORT_SEL_MASK,
1660 .val = PMX_UART5_PORT_90_VAL, 1660 .val = PMX_UART5_PORT_90_VAL,
1661 }, 1661 },
1662 }; 1662 };
1663 1663
1664 static struct spear_modemux uart5_modemux[][1] = { 1664 static struct spear_modemux uart5_modemux[][1] = {
1665 { 1665 {
1666 /* Select signals on pins 4_5 */ 1666 /* Select signals on pins 4_5 */
1667 { 1667 {
1668 .modes = EXTENDED_MODE, 1668 .modes = EXTENDED_MODE,
1669 .muxregs = uart5_ext_4_5_muxreg, 1669 .muxregs = uart5_ext_4_5_muxreg,
1670 .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg), 1670 .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
1671 }, 1671 },
1672 }, { 1672 }, {
1673 /* Select signals on pins 37_38 */ 1673 /* Select signals on pins 37_38 */
1674 { 1674 {
1675 .modes = EXTENDED_MODE, 1675 .modes = EXTENDED_MODE,
1676 .muxregs = uart5_ext_37_38_muxreg, 1676 .muxregs = uart5_ext_37_38_muxreg,
1677 .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg), 1677 .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
1678 }, 1678 },
1679 }, { 1679 }, {
1680 /* Select signals on pins 69_70 */ 1680 /* Select signals on pins 69_70 */
1681 { 1681 {
1682 .modes = EXTENDED_MODE, 1682 .modes = EXTENDED_MODE,
1683 .muxregs = uart5_ext_69_70_muxreg, 1683 .muxregs = uart5_ext_69_70_muxreg,
1684 .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg), 1684 .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
1685 }, 1685 },
1686 }, { 1686 }, {
1687 /* Select signals on pins 90_91 */ 1687 /* Select signals on pins 90_91 */
1688 { 1688 {
1689 .modes = EXTENDED_MODE, 1689 .modes = EXTENDED_MODE,
1690 .muxregs = uart5_ext_90_91_muxreg, 1690 .muxregs = uart5_ext_90_91_muxreg,
1691 .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg), 1691 .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
1692 }, 1692 },
1693 }, 1693 },
1694 }; 1694 };
1695 1695
1696 static struct spear_pingroup uart5_pingroup[] = { 1696 static struct spear_pingroup uart5_pingroup[] = {
1697 { 1697 {
1698 .name = "uart5_4_5_grp", 1698 .name = "uart5_4_5_grp",
1699 .pins = uart5_pins[0], 1699 .pins = uart5_pins[0],
1700 .npins = ARRAY_SIZE(uart5_pins[0]), 1700 .npins = ARRAY_SIZE(uart5_pins[0]),
1701 .modemuxs = uart5_modemux[0], 1701 .modemuxs = uart5_modemux[0],
1702 .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]), 1702 .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
1703 }, { 1703 }, {
1704 .name = "uart5_37_38_grp", 1704 .name = "uart5_37_38_grp",
1705 .pins = uart5_pins[1], 1705 .pins = uart5_pins[1],
1706 .npins = ARRAY_SIZE(uart5_pins[1]), 1706 .npins = ARRAY_SIZE(uart5_pins[1]),
1707 .modemuxs = uart5_modemux[1], 1707 .modemuxs = uart5_modemux[1],
1708 .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]), 1708 .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
1709 }, { 1709 }, {
1710 .name = "uart5_69_70_grp", 1710 .name = "uart5_69_70_grp",
1711 .pins = uart5_pins[2], 1711 .pins = uart5_pins[2],
1712 .npins = ARRAY_SIZE(uart5_pins[2]), 1712 .npins = ARRAY_SIZE(uart5_pins[2]),
1713 .modemuxs = uart5_modemux[2], 1713 .modemuxs = uart5_modemux[2],
1714 .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]), 1714 .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
1715 }, { 1715 }, {
1716 .name = "uart5_90_91_grp", 1716 .name = "uart5_90_91_grp",
1717 .pins = uart5_pins[3], 1717 .pins = uart5_pins[3],
1718 .npins = ARRAY_SIZE(uart5_pins[3]), 1718 .npins = ARRAY_SIZE(uart5_pins[3]),
1719 .modemuxs = uart5_modemux[3], 1719 .modemuxs = uart5_modemux[3],
1720 .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]), 1720 .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
1721 }, 1721 },
1722 }; 1722 };
1723 1723
1724 static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp", 1724 static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
1725 "uart5_69_70_grp", "uart5_90_91_grp" }; 1725 "uart5_69_70_grp", "uart5_90_91_grp" };
1726 static struct spear_function uart5_function = { 1726 static struct spear_function uart5_function = {
1727 .name = "uart5", 1727 .name = "uart5",
1728 .groups = uart5_grps, 1728 .groups = uart5_grps,
1729 .ngroups = ARRAY_SIZE(uart5_grps), 1729 .ngroups = ARRAY_SIZE(uart5_grps),
1730 }; 1730 };
1731 1731
1732 /* Pad multiplexing for uart6 device */ 1732 /* Pad multiplexing for uart6 device */
1733 static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } }; 1733 static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
1734 static struct spear_muxreg uart6_ext_2_3_muxreg[] = { 1734 static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
1735 { 1735 {
1736 .reg = PMX_CONFIG_REG, 1736 .reg = PMX_CONFIG_REG,
1737 .mask = PMX_UART0_MASK, 1737 .mask = PMX_UART0_MASK,
1738 .val = 0, 1738 .val = 0,
1739 }, { 1739 }, {
1740 .reg = IP_SEL_PAD_0_9_REG, 1740 .reg = IP_SEL_PAD_0_9_REG,
1741 .mask = PMX_PL_2_3_MASK, 1741 .mask = PMX_PL_2_3_MASK,
1742 .val = PMX_UART6_PL_2_3_VAL, 1742 .val = PMX_UART6_PL_2_3_VAL,
1743 }, { 1743 }, {
1744 .reg = IP_SEL_MIX_PAD_REG, 1744 .reg = IP_SEL_MIX_PAD_REG,
1745 .mask = PMX_UART6_PORT_SEL_MASK, 1745 .mask = PMX_UART6_PORT_SEL_MASK,
1746 .val = PMX_UART6_PORT_2_VAL, 1746 .val = PMX_UART6_PORT_2_VAL,
1747 }, 1747 },
1748 }; 1748 };
1749 1749
1750 static struct spear_muxreg uart6_ext_88_89_muxreg[] = { 1750 static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
1751 { 1751 {
1752 .reg = IP_SEL_PAD_80_89_REG, 1752 .reg = IP_SEL_PAD_80_89_REG,
1753 .mask = PMX_PL_88_89_MASK, 1753 .mask = PMX_PL_88_89_MASK,
1754 .val = PMX_UART6_PL_88_89_VAL, 1754 .val = PMX_UART6_PL_88_89_VAL,
1755 }, { 1755 }, {
1756 .reg = IP_SEL_MIX_PAD_REG, 1756 .reg = IP_SEL_MIX_PAD_REG,
1757 .mask = PMX_UART6_PORT_SEL_MASK, 1757 .mask = PMX_UART6_PORT_SEL_MASK,
1758 .val = PMX_UART6_PORT_88_VAL, 1758 .val = PMX_UART6_PORT_88_VAL,
1759 }, 1759 },
1760 }; 1760 };
1761 1761
1762 static struct spear_modemux uart6_modemux[][1] = { 1762 static struct spear_modemux uart6_modemux[][1] = {
1763 { 1763 {
1764 /* Select signals on pins 2_3 */ 1764 /* Select signals on pins 2_3 */
1765 { 1765 {
1766 .modes = EXTENDED_MODE, 1766 .modes = EXTENDED_MODE,
1767 .muxregs = uart6_ext_2_3_muxreg, 1767 .muxregs = uart6_ext_2_3_muxreg,
1768 .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg), 1768 .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
1769 }, 1769 },
1770 }, { 1770 }, {
1771 /* Select signals on pins 88_89 */ 1771 /* Select signals on pins 88_89 */
1772 { 1772 {
1773 .modes = EXTENDED_MODE, 1773 .modes = EXTENDED_MODE,
1774 .muxregs = uart6_ext_88_89_muxreg, 1774 .muxregs = uart6_ext_88_89_muxreg,
1775 .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg), 1775 .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
1776 }, 1776 },
1777 }, 1777 },
1778 }; 1778 };
1779 1779
1780 static struct spear_pingroup uart6_pingroup[] = { 1780 static struct spear_pingroup uart6_pingroup[] = {
1781 { 1781 {
1782 .name = "uart6_2_3_grp", 1782 .name = "uart6_2_3_grp",
1783 .pins = uart6_pins[0], 1783 .pins = uart6_pins[0],
1784 .npins = ARRAY_SIZE(uart6_pins[0]), 1784 .npins = ARRAY_SIZE(uart6_pins[0]),
1785 .modemuxs = uart6_modemux[0], 1785 .modemuxs = uart6_modemux[0],
1786 .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]), 1786 .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
1787 }, { 1787 }, {
1788 .name = "uart6_88_89_grp", 1788 .name = "uart6_88_89_grp",
1789 .pins = uart6_pins[1], 1789 .pins = uart6_pins[1],
1790 .npins = ARRAY_SIZE(uart6_pins[1]), 1790 .npins = ARRAY_SIZE(uart6_pins[1]),
1791 .modemuxs = uart6_modemux[1], 1791 .modemuxs = uart6_modemux[1],
1792 .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]), 1792 .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
1793 }, 1793 },
1794 }; 1794 };
1795 1795
1796 static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" }; 1796 static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
1797 static struct spear_function uart6_function = { 1797 static struct spear_function uart6_function = {
1798 .name = "uart6", 1798 .name = "uart6",
1799 .groups = uart6_grps, 1799 .groups = uart6_grps,
1800 .ngroups = ARRAY_SIZE(uart6_grps), 1800 .ngroups = ARRAY_SIZE(uart6_grps),
1801 }; 1801 };
1802 1802
1803 /* UART - RS485 pmx */ 1803 /* UART - RS485 pmx */
1804 static const unsigned rs485_pins[] = { 77, 78, 79 }; 1804 static const unsigned rs485_pins[] = { 77, 78, 79 };
1805 static struct spear_muxreg rs485_muxreg[] = { 1805 static struct spear_muxreg rs485_muxreg[] = {
1806 { 1806 {
1807 .reg = IP_SEL_PAD_70_79_REG, 1807 .reg = IP_SEL_PAD_70_79_REG,
1808 .mask = PMX_PL_77_78_79_MASK, 1808 .mask = PMX_PL_77_78_79_MASK,
1809 .val = PMX_RS485_PL_77_78_79_VAL, 1809 .val = PMX_RS485_PL_77_78_79_VAL,
1810 }, 1810 },
1811 }; 1811 };
1812 1812
1813 static struct spear_modemux rs485_modemux[] = { 1813 static struct spear_modemux rs485_modemux[] = {
1814 { 1814 {
1815 .modes = EXTENDED_MODE, 1815 .modes = EXTENDED_MODE,
1816 .muxregs = rs485_muxreg, 1816 .muxregs = rs485_muxreg,
1817 .nmuxregs = ARRAY_SIZE(rs485_muxreg), 1817 .nmuxregs = ARRAY_SIZE(rs485_muxreg),
1818 }, 1818 },
1819 }; 1819 };
1820 1820
1821 static struct spear_pingroup rs485_pingroup = { 1821 static struct spear_pingroup rs485_pingroup = {
1822 .name = "rs485_grp", 1822 .name = "rs485_grp",
1823 .pins = rs485_pins, 1823 .pins = rs485_pins,
1824 .npins = ARRAY_SIZE(rs485_pins), 1824 .npins = ARRAY_SIZE(rs485_pins),
1825 .modemuxs = rs485_modemux, 1825 .modemuxs = rs485_modemux,
1826 .nmodemuxs = ARRAY_SIZE(rs485_modemux), 1826 .nmodemuxs = ARRAY_SIZE(rs485_modemux),
1827 }; 1827 };
1828 1828
1829 static const char *const rs485_grps[] = { "rs485_grp" }; 1829 static const char *const rs485_grps[] = { "rs485_grp" };
1830 static struct spear_function rs485_function = { 1830 static struct spear_function rs485_function = {
1831 .name = "rs485", 1831 .name = "rs485",
1832 .groups = rs485_grps, 1832 .groups = rs485_grps,
1833 .ngroups = ARRAY_SIZE(rs485_grps), 1833 .ngroups = ARRAY_SIZE(rs485_grps),
1834 }; 1834 };
1835 1835
1836 /* Pad multiplexing for Touchscreen device */ 1836 /* Pad multiplexing for Touchscreen device */
1837 static const unsigned touchscreen_pins[] = { 5, 36 }; 1837 static const unsigned touchscreen_pins[] = { 5, 36 };
1838 static struct spear_muxreg touchscreen_muxreg[] = { 1838 static struct spear_muxreg touchscreen_muxreg[] = {
1839 { 1839 {
1840 .reg = PMX_CONFIG_REG, 1840 .reg = PMX_CONFIG_REG,
1841 .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK, 1841 .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
1842 .val = 0, 1842 .val = 0,
1843 }, 1843 },
1844 }; 1844 };
1845 1845
1846 static struct spear_muxreg touchscreen_ext_muxreg[] = { 1846 static struct spear_muxreg touchscreen_ext_muxreg[] = {
1847 { 1847 {
1848 .reg = IP_SEL_PAD_0_9_REG, 1848 .reg = IP_SEL_PAD_0_9_REG,
1849 .mask = PMX_PL_5_MASK, 1849 .mask = PMX_PL_5_MASK,
1850 .val = PMX_TOUCH_Y_PL_5_VAL, 1850 .val = PMX_TOUCH_Y_PL_5_VAL,
1851 }, { 1851 }, {
1852 .reg = IP_SEL_PAD_30_39_REG, 1852 .reg = IP_SEL_PAD_30_39_REG,
1853 .mask = PMX_PL_36_MASK, 1853 .mask = PMX_PL_36_MASK,
1854 .val = PMX_TOUCH_X_PL_36_VAL, 1854 .val = PMX_TOUCH_X_PL_36_VAL,
1855 }, 1855 },
1856 }; 1856 };
1857 1857
1858 static struct spear_modemux touchscreen_modemux[] = { 1858 static struct spear_modemux touchscreen_modemux[] = {
1859 { 1859 {
1860 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, 1860 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
1861 .muxregs = touchscreen_muxreg, 1861 .muxregs = touchscreen_muxreg,
1862 .nmuxregs = ARRAY_SIZE(touchscreen_muxreg), 1862 .nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
1863 }, { 1863 }, {
1864 .modes = EXTENDED_MODE, 1864 .modes = EXTENDED_MODE,
1865 .muxregs = touchscreen_ext_muxreg, 1865 .muxregs = touchscreen_ext_muxreg,
1866 .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg), 1866 .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
1867 }, 1867 },
1868 }; 1868 };
1869 1869
1870 static struct spear_pingroup touchscreen_pingroup = { 1870 static struct spear_pingroup touchscreen_pingroup = {
1871 .name = "touchscreen_grp", 1871 .name = "touchscreen_grp",
1872 .pins = touchscreen_pins, 1872 .pins = touchscreen_pins,
1873 .npins = ARRAY_SIZE(touchscreen_pins), 1873 .npins = ARRAY_SIZE(touchscreen_pins),
1874 .modemuxs = touchscreen_modemux, 1874 .modemuxs = touchscreen_modemux,
1875 .nmodemuxs = ARRAY_SIZE(touchscreen_modemux), 1875 .nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
1876 }; 1876 };
1877 1877
1878 static const char *const touchscreen_grps[] = { "touchscreen_grp" }; 1878 static const char *const touchscreen_grps[] = { "touchscreen_grp" };
1879 static struct spear_function touchscreen_function = { 1879 static struct spear_function touchscreen_function = {
1880 .name = "touchscreen", 1880 .name = "touchscreen",
1881 .groups = touchscreen_grps, 1881 .groups = touchscreen_grps,
1882 .ngroups = ARRAY_SIZE(touchscreen_grps), 1882 .ngroups = ARRAY_SIZE(touchscreen_grps),
1883 }; 1883 };
1884 1884
1885 /* Pad multiplexing for CAN device */ 1885 /* Pad multiplexing for CAN device */
1886 static const unsigned can0_pins[] = { 32, 33 }; 1886 static const unsigned can0_pins[] = { 32, 33 };
1887 static struct spear_muxreg can0_muxreg[] = { 1887 static struct spear_muxreg can0_muxreg[] = {
1888 { 1888 {
1889 .reg = PMX_CONFIG_REG, 1889 .reg = PMX_CONFIG_REG,
1890 .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, 1890 .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
1891 .val = 0, 1891 .val = 0,
1892 }, 1892 },
1893 }; 1893 };
1894 1894
1895 static struct spear_muxreg can0_ext_muxreg[] = { 1895 static struct spear_muxreg can0_ext_muxreg[] = {
1896 { 1896 {
1897 .reg = IP_SEL_PAD_30_39_REG, 1897 .reg = IP_SEL_PAD_30_39_REG,
1898 .mask = PMX_PL_32_33_MASK, 1898 .mask = PMX_PL_32_33_MASK,
1899 .val = PMX_CAN0_PL_32_33_VAL, 1899 .val = PMX_CAN0_PL_32_33_VAL,
1900 }, 1900 },
1901 }; 1901 };
1902 1902
1903 static struct spear_modemux can0_modemux[] = { 1903 static struct spear_modemux can0_modemux[] = {
1904 { 1904 {
1905 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE 1905 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1906 | EXTENDED_MODE, 1906 | EXTENDED_MODE,
1907 .muxregs = can0_muxreg, 1907 .muxregs = can0_muxreg,
1908 .nmuxregs = ARRAY_SIZE(can0_muxreg), 1908 .nmuxregs = ARRAY_SIZE(can0_muxreg),
1909 }, { 1909 }, {
1910 .modes = EXTENDED_MODE, 1910 .modes = EXTENDED_MODE,
1911 .muxregs = can0_ext_muxreg, 1911 .muxregs = can0_ext_muxreg,
1912 .nmuxregs = ARRAY_SIZE(can0_ext_muxreg), 1912 .nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
1913 }, 1913 },
1914 }; 1914 };
1915 1915
1916 static struct spear_pingroup can0_pingroup = { 1916 static struct spear_pingroup can0_pingroup = {
1917 .name = "can0_grp", 1917 .name = "can0_grp",
1918 .pins = can0_pins, 1918 .pins = can0_pins,
1919 .npins = ARRAY_SIZE(can0_pins), 1919 .npins = ARRAY_SIZE(can0_pins),
1920 .modemuxs = can0_modemux, 1920 .modemuxs = can0_modemux,
1921 .nmodemuxs = ARRAY_SIZE(can0_modemux), 1921 .nmodemuxs = ARRAY_SIZE(can0_modemux),
1922 }; 1922 };
1923 1923
1924 static const char *const can0_grps[] = { "can0_grp" }; 1924 static const char *const can0_grps[] = { "can0_grp" };
1925 static struct spear_function can0_function = { 1925 static struct spear_function can0_function = {
1926 .name = "can0", 1926 .name = "can0",
1927 .groups = can0_grps, 1927 .groups = can0_grps,
1928 .ngroups = ARRAY_SIZE(can0_grps), 1928 .ngroups = ARRAY_SIZE(can0_grps),
1929 }; 1929 };
1930 1930
1931 static const unsigned can1_pins[] = { 30, 31 }; 1931 static const unsigned can1_pins[] = { 30, 31 };
1932 static struct spear_muxreg can1_muxreg[] = { 1932 static struct spear_muxreg can1_muxreg[] = {
1933 { 1933 {
1934 .reg = PMX_CONFIG_REG, 1934 .reg = PMX_CONFIG_REG,
1935 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, 1935 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
1936 .val = 0, 1936 .val = 0,
1937 }, 1937 },
1938 }; 1938 };
1939 1939
1940 static struct spear_muxreg can1_ext_muxreg[] = { 1940 static struct spear_muxreg can1_ext_muxreg[] = {
1941 { 1941 {
1942 .reg = IP_SEL_PAD_30_39_REG, 1942 .reg = IP_SEL_PAD_30_39_REG,
1943 .mask = PMX_PL_30_31_MASK, 1943 .mask = PMX_PL_30_31_MASK,
1944 .val = PMX_CAN1_PL_30_31_VAL, 1944 .val = PMX_CAN1_PL_30_31_VAL,
1945 }, 1945 },
1946 }; 1946 };
1947 1947
1948 static struct spear_modemux can1_modemux[] = { 1948 static struct spear_modemux can1_modemux[] = {
1949 { 1949 {
1950 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE 1950 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1951 | EXTENDED_MODE, 1951 | EXTENDED_MODE,
1952 .muxregs = can1_muxreg, 1952 .muxregs = can1_muxreg,
1953 .nmuxregs = ARRAY_SIZE(can1_muxreg), 1953 .nmuxregs = ARRAY_SIZE(can1_muxreg),
1954 }, { 1954 }, {
1955 .modes = EXTENDED_MODE, 1955 .modes = EXTENDED_MODE,
1956 .muxregs = can1_ext_muxreg, 1956 .muxregs = can1_ext_muxreg,
1957 .nmuxregs = ARRAY_SIZE(can1_ext_muxreg), 1957 .nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
1958 }, 1958 },
1959 }; 1959 };
1960 1960
1961 static struct spear_pingroup can1_pingroup = { 1961 static struct spear_pingroup can1_pingroup = {
1962 .name = "can1_grp", 1962 .name = "can1_grp",
1963 .pins = can1_pins, 1963 .pins = can1_pins,
1964 .npins = ARRAY_SIZE(can1_pins), 1964 .npins = ARRAY_SIZE(can1_pins),
1965 .modemuxs = can1_modemux, 1965 .modemuxs = can1_modemux,
1966 .nmodemuxs = ARRAY_SIZE(can1_modemux), 1966 .nmodemuxs = ARRAY_SIZE(can1_modemux),
1967 }; 1967 };
1968 1968
1969 static const char *const can1_grps[] = { "can1_grp" }; 1969 static const char *const can1_grps[] = { "can1_grp" };
1970 static struct spear_function can1_function = { 1970 static struct spear_function can1_function = {
1971 .name = "can1", 1971 .name = "can1",
1972 .groups = can1_grps, 1972 .groups = can1_grps,
1973 .ngroups = ARRAY_SIZE(can1_grps), 1973 .ngroups = ARRAY_SIZE(can1_grps),
1974 }; 1974 };
1975 1975
1976 /* Pad multiplexing for PWM0_1 device */ 1976 /* Pad multiplexing for PWM0_1 device */
1977 static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 }, 1977 static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
1978 { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } }; 1978 { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
1979 1979
1980 static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = { 1980 static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
1981 { 1981 {
1982 .reg = PMX_CONFIG_REG, 1982 .reg = PMX_CONFIG_REG,
1983 .mask = PMX_SSP_MASK, 1983 .mask = PMX_SSP_MASK,
1984 .val = 0, 1984 .val = 0,
1985 }, { 1985 }, {
1986 .reg = IP_SEL_PAD_0_9_REG, 1986 .reg = IP_SEL_PAD_0_9_REG,
1987 .mask = PMX_PL_8_9_MASK, 1987 .mask = PMX_PL_8_9_MASK,
1988 .val = PMX_PWM_0_1_PL_8_9_VAL, 1988 .val = PMX_PWM_0_1_PL_8_9_VAL,
1989 }, 1989 },
1990 }; 1990 };
1991 1991
1992 static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = { 1992 static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
1993 { 1993 {
1994 .reg = PMX_CONFIG_REG, 1994 .reg = PMX_CONFIG_REG,
1995 .mask = PMX_MII_MASK, 1995 .mask = PMX_MII_MASK,
1996 .val = 0, 1996 .val = 0,
1997 }, 1997 },
1998 }; 1998 };
1999 1999
2000 static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = { 2000 static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
2001 { 2001 {
2002 .reg = IP_SEL_PAD_10_19_REG, 2002 .reg = IP_SEL_PAD_10_19_REG,
2003 .mask = PMX_PL_14_MASK | PMX_PL_15_MASK, 2003 .mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
2004 .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL, 2004 .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
2005 }, 2005 },
2006 }; 2006 };
2007 2007
2008 static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = { 2008 static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
2009 { 2009 {
2010 .reg = PMX_CONFIG_REG, 2010 .reg = PMX_CONFIG_REG,
2011 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, 2011 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
2012 .val = 0, 2012 .val = 0,
2013 }, { 2013 }, {
2014 .reg = IP_SEL_PAD_30_39_REG, 2014 .reg = IP_SEL_PAD_30_39_REG,
2015 .mask = PMX_PL_30_MASK | PMX_PL_31_MASK, 2015 .mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
2016 .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL, 2016 .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
2017 }, 2017 },
2018 }; 2018 };
2019 2019
2020 static struct spear_muxreg pwm0_1_net_muxreg[] = { 2020 static struct spear_muxreg pwm0_1_net_muxreg[] = {
2021 { 2021 {
2022 .reg = PMX_CONFIG_REG, 2022 .reg = PMX_CONFIG_REG,
2023 .mask = PMX_UART0_MODEM_MASK, 2023 .mask = PMX_UART0_MODEM_MASK,
2024 .val = 0, 2024 .val = 0,
2025 }, 2025 },
2026 }; 2026 };
2027 2027
2028 static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = { 2028 static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
2029 { 2029 {
2030 .reg = IP_SEL_PAD_30_39_REG, 2030 .reg = IP_SEL_PAD_30_39_REG,
2031 .mask = PMX_PL_37_38_MASK, 2031 .mask = PMX_PL_37_38_MASK,
2032 .val = PMX_PWM0_1_PL_37_38_VAL, 2032 .val = PMX_PWM0_1_PL_37_38_VAL,
2033 }, 2033 },
2034 }; 2034 };
2035 2035
2036 static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = { 2036 static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
2037 { 2037 {
2038 .reg = PMX_CONFIG_REG, 2038 .reg = PMX_CONFIG_REG,
2039 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK , 2039 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
2040 .val = 0, 2040 .val = 0,
2041 }, { 2041 }, {
2042 .reg = IP_SEL_PAD_40_49_REG, 2042 .reg = IP_SEL_PAD_40_49_REG,
2043 .mask = PMX_PL_42_MASK | PMX_PL_43_MASK, 2043 .mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
2044 .val = PMX_PWM1_PL_42_VAL | 2044 .val = PMX_PWM1_PL_42_VAL |
2045 PMX_PWM0_PL_43_VAL, 2045 PMX_PWM0_PL_43_VAL,
2046 }, 2046 },
2047 }; 2047 };
2048 2048
2049 static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = { 2049 static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
2050 { 2050 {
2051 .reg = IP_SEL_PAD_50_59_REG, 2051 .reg = IP_SEL_PAD_50_59_REG,
2052 .mask = PMX_PL_59_MASK, 2052 .mask = PMX_PL_59_MASK,
2053 .val = PMX_PWM1_PL_59_VAL, 2053 .val = PMX_PWM1_PL_59_VAL,
2054 }, { 2054 }, {
2055 .reg = IP_SEL_PAD_60_69_REG, 2055 .reg = IP_SEL_PAD_60_69_REG,
2056 .mask = PMX_PL_60_MASK, 2056 .mask = PMX_PL_60_MASK,
2057 .val = PMX_PWM0_PL_60_VAL, 2057 .val = PMX_PWM0_PL_60_VAL,
2058 }, 2058 },
2059 }; 2059 };
2060 2060
2061 static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = { 2061 static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
2062 { 2062 {
2063 .reg = IP_SEL_PAD_80_89_REG, 2063 .reg = IP_SEL_PAD_80_89_REG,
2064 .mask = PMX_PL_88_89_MASK, 2064 .mask = PMX_PL_88_89_MASK,
2065 .val = PMX_PWM0_1_PL_88_89_VAL, 2065 .val = PMX_PWM0_1_PL_88_89_VAL,
2066 }, 2066 },
2067 }; 2067 };
2068 2068
2069 static struct spear_modemux pwm0_1_pin_8_9_modemux[] = { 2069 static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
2070 { 2070 {
2071 .modes = EXTENDED_MODE, 2071 .modes = EXTENDED_MODE,
2072 .muxregs = pwm0_1_pin_8_9_muxreg, 2072 .muxregs = pwm0_1_pin_8_9_muxreg,
2073 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg), 2073 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
2074 }, 2074 },
2075 }; 2075 };
2076 2076
2077 static struct spear_modemux pwm0_1_pin_14_15_modemux[] = { 2077 static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
2078 { 2078 {
2079 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, 2079 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2080 .muxregs = pwm0_1_autoexpsmallpri_muxreg, 2080 .muxregs = pwm0_1_autoexpsmallpri_muxreg,
2081 .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg), 2081 .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
2082 }, { 2082 }, {
2083 .modes = EXTENDED_MODE, 2083 .modes = EXTENDED_MODE,
2084 .muxregs = pwm0_1_pin_14_15_muxreg, 2084 .muxregs = pwm0_1_pin_14_15_muxreg,
2085 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg), 2085 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
2086 }, 2086 },
2087 }; 2087 };
2088 2088
2089 static struct spear_modemux pwm0_1_pin_30_31_modemux[] = { 2089 static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
2090 { 2090 {
2091 .modes = EXTENDED_MODE, 2091 .modes = EXTENDED_MODE,
2092 .muxregs = pwm0_1_pin_30_31_muxreg, 2092 .muxregs = pwm0_1_pin_30_31_muxreg,
2093 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg), 2093 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
2094 }, 2094 },
2095 }; 2095 };
2096 2096
2097 static struct spear_modemux pwm0_1_pin_37_38_modemux[] = { 2097 static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
2098 { 2098 {
2099 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, 2099 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2100 .muxregs = pwm0_1_net_muxreg, 2100 .muxregs = pwm0_1_net_muxreg,
2101 .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg), 2101 .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
2102 }, { 2102 }, {
2103 .modes = EXTENDED_MODE, 2103 .modes = EXTENDED_MODE,
2104 .muxregs = pwm0_1_pin_37_38_muxreg, 2104 .muxregs = pwm0_1_pin_37_38_muxreg,
2105 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg), 2105 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
2106 }, 2106 },
2107 }; 2107 };
2108 2108
2109 static struct spear_modemux pwm0_1_pin_42_43_modemux[] = { 2109 static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
2110 { 2110 {
2111 .modes = EXTENDED_MODE, 2111 .modes = EXTENDED_MODE,
2112 .muxregs = pwm0_1_pin_42_43_muxreg, 2112 .muxregs = pwm0_1_pin_42_43_muxreg,
2113 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg), 2113 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
2114 }, 2114 },
2115 }; 2115 };
2116 2116
2117 static struct spear_modemux pwm0_1_pin_59_60_modemux[] = { 2117 static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
2118 { 2118 {
2119 .modes = EXTENDED_MODE, 2119 .modes = EXTENDED_MODE,
2120 .muxregs = pwm0_1_pin_59_60_muxreg, 2120 .muxregs = pwm0_1_pin_59_60_muxreg,
2121 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg), 2121 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
2122 }, 2122 },
2123 }; 2123 };
2124 2124
2125 static struct spear_modemux pwm0_1_pin_88_89_modemux[] = { 2125 static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
2126 { 2126 {
2127 .modes = EXTENDED_MODE, 2127 .modes = EXTENDED_MODE,
2128 .muxregs = pwm0_1_pin_88_89_muxreg, 2128 .muxregs = pwm0_1_pin_88_89_muxreg,
2129 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg), 2129 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
2130 }, 2130 },
2131 }; 2131 };
2132 2132
2133 static struct spear_pingroup pwm0_1_pingroup[] = { 2133 static struct spear_pingroup pwm0_1_pingroup[] = {
2134 { 2134 {
2135 .name = "pwm0_1_pin_8_9_grp", 2135 .name = "pwm0_1_pin_8_9_grp",
2136 .pins = pwm0_1_pins[0], 2136 .pins = pwm0_1_pins[0],
2137 .npins = ARRAY_SIZE(pwm0_1_pins[0]), 2137 .npins = ARRAY_SIZE(pwm0_1_pins[0]),
2138 .modemuxs = pwm0_1_pin_8_9_modemux, 2138 .modemuxs = pwm0_1_pin_8_9_modemux,
2139 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux), 2139 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
2140 }, { 2140 }, {
2141 .name = "pwm0_1_pin_14_15_grp", 2141 .name = "pwm0_1_pin_14_15_grp",
2142 .pins = pwm0_1_pins[1], 2142 .pins = pwm0_1_pins[1],
2143 .npins = ARRAY_SIZE(pwm0_1_pins[1]), 2143 .npins = ARRAY_SIZE(pwm0_1_pins[1]),
2144 .modemuxs = pwm0_1_pin_14_15_modemux, 2144 .modemuxs = pwm0_1_pin_14_15_modemux,
2145 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux), 2145 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
2146 }, { 2146 }, {
2147 .name = "pwm0_1_pin_30_31_grp", 2147 .name = "pwm0_1_pin_30_31_grp",
2148 .pins = pwm0_1_pins[2], 2148 .pins = pwm0_1_pins[2],
2149 .npins = ARRAY_SIZE(pwm0_1_pins[2]), 2149 .npins = ARRAY_SIZE(pwm0_1_pins[2]),
2150 .modemuxs = pwm0_1_pin_30_31_modemux, 2150 .modemuxs = pwm0_1_pin_30_31_modemux,
2151 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux), 2151 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
2152 }, { 2152 }, {
2153 .name = "pwm0_1_pin_37_38_grp", 2153 .name = "pwm0_1_pin_37_38_grp",
2154 .pins = pwm0_1_pins[3], 2154 .pins = pwm0_1_pins[3],
2155 .npins = ARRAY_SIZE(pwm0_1_pins[3]), 2155 .npins = ARRAY_SIZE(pwm0_1_pins[3]),
2156 .modemuxs = pwm0_1_pin_37_38_modemux, 2156 .modemuxs = pwm0_1_pin_37_38_modemux,
2157 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux), 2157 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
2158 }, { 2158 }, {
2159 .name = "pwm0_1_pin_42_43_grp", 2159 .name = "pwm0_1_pin_42_43_grp",
2160 .pins = pwm0_1_pins[4], 2160 .pins = pwm0_1_pins[4],
2161 .npins = ARRAY_SIZE(pwm0_1_pins[4]), 2161 .npins = ARRAY_SIZE(pwm0_1_pins[4]),
2162 .modemuxs = pwm0_1_pin_42_43_modemux, 2162 .modemuxs = pwm0_1_pin_42_43_modemux,
2163 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux), 2163 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
2164 }, { 2164 }, {
2165 .name = "pwm0_1_pin_59_60_grp", 2165 .name = "pwm0_1_pin_59_60_grp",
2166 .pins = pwm0_1_pins[5], 2166 .pins = pwm0_1_pins[5],
2167 .npins = ARRAY_SIZE(pwm0_1_pins[5]), 2167 .npins = ARRAY_SIZE(pwm0_1_pins[5]),
2168 .modemuxs = pwm0_1_pin_59_60_modemux, 2168 .modemuxs = pwm0_1_pin_59_60_modemux,
2169 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux), 2169 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
2170 }, { 2170 }, {
2171 .name = "pwm0_1_pin_88_89_grp", 2171 .name = "pwm0_1_pin_88_89_grp",
2172 .pins = pwm0_1_pins[6], 2172 .pins = pwm0_1_pins[6],
2173 .npins = ARRAY_SIZE(pwm0_1_pins[6]), 2173 .npins = ARRAY_SIZE(pwm0_1_pins[6]),
2174 .modemuxs = pwm0_1_pin_88_89_modemux, 2174 .modemuxs = pwm0_1_pin_88_89_modemux,
2175 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux), 2175 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
2176 }, 2176 },
2177 }; 2177 };
2178 2178
2179 static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp", 2179 static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
2180 "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", 2180 "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
2181 "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp" 2181 "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
2182 }; 2182 };
2183 2183
2184 static struct spear_function pwm0_1_function = { 2184 static struct spear_function pwm0_1_function = {
2185 .name = "pwm0_1", 2185 .name = "pwm0_1",
2186 .groups = pwm0_1_grps, 2186 .groups = pwm0_1_grps,
2187 .ngroups = ARRAY_SIZE(pwm0_1_grps), 2187 .ngroups = ARRAY_SIZE(pwm0_1_grps),
2188 }; 2188 };
2189 2189
2190 /* Pad multiplexing for PWM2 device */ 2190 /* Pad multiplexing for PWM2 device */
2191 static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 }, 2191 static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
2192 { 58 }, { 87 } }; 2192 { 58 }, { 87 } };
2193 static struct spear_muxreg pwm2_net_muxreg[] = { 2193 static struct spear_muxreg pwm2_net_muxreg[] = {
2194 { 2194 {
2195 .reg = PMX_CONFIG_REG, 2195 .reg = PMX_CONFIG_REG,
2196 .mask = PMX_SSP_CS_MASK, 2196 .mask = PMX_SSP_CS_MASK,
2197 .val = 0, 2197 .val = 0,
2198 }, 2198 },
2199 }; 2199 };
2200 2200
2201 static struct spear_muxreg pwm2_pin_7_muxreg[] = { 2201 static struct spear_muxreg pwm2_pin_7_muxreg[] = {
2202 { 2202 {
2203 .reg = IP_SEL_PAD_0_9_REG, 2203 .reg = IP_SEL_PAD_0_9_REG,
2204 .mask = PMX_PL_7_MASK, 2204 .mask = PMX_PL_7_MASK,
2205 .val = PMX_PWM_2_PL_7_VAL, 2205 .val = PMX_PWM_2_PL_7_VAL,
2206 }, 2206 },
2207 }; 2207 };
2208 2208
2209 static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = { 2209 static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
2210 { 2210 {
2211 .reg = PMX_CONFIG_REG, 2211 .reg = PMX_CONFIG_REG,
2212 .mask = PMX_MII_MASK, 2212 .mask = PMX_MII_MASK,
2213 .val = 0, 2213 .val = 0,
2214 }, 2214 },
2215 }; 2215 };
2216 2216
2217 static struct spear_muxreg pwm2_pin_13_muxreg[] = { 2217 static struct spear_muxreg pwm2_pin_13_muxreg[] = {
2218 { 2218 {
2219 .reg = IP_SEL_PAD_10_19_REG, 2219 .reg = IP_SEL_PAD_10_19_REG,
2220 .mask = PMX_PL_13_MASK, 2220 .mask = PMX_PL_13_MASK,
2221 .val = PMX_PWM2_PL_13_VAL, 2221 .val = PMX_PWM2_PL_13_VAL,
2222 }, 2222 },
2223 }; 2223 };
2224 2224
2225 static struct spear_muxreg pwm2_pin_29_muxreg[] = { 2225 static struct spear_muxreg pwm2_pin_29_muxreg[] = {
2226 { 2226 {
2227 .reg = PMX_CONFIG_REG, 2227 .reg = PMX_CONFIG_REG,
2228 .mask = PMX_GPIO_PIN1_MASK, 2228 .mask = PMX_GPIO_PIN1_MASK,
2229 .val = 0, 2229 .val = 0,
2230 }, { 2230 }, {
2231 .reg = IP_SEL_PAD_20_29_REG, 2231 .reg = IP_SEL_PAD_20_29_REG,
2232 .mask = PMX_PL_29_MASK, 2232 .mask = PMX_PL_29_MASK,
2233 .val = PMX_PWM_2_PL_29_VAL, 2233 .val = PMX_PWM_2_PL_29_VAL,
2234 }, 2234 },
2235 }; 2235 };
2236 2236
2237 static struct spear_muxreg pwm2_pin_34_muxreg[] = { 2237 static struct spear_muxreg pwm2_pin_34_muxreg[] = {
2238 { 2238 {
2239 .reg = PMX_CONFIG_REG, 2239 .reg = PMX_CONFIG_REG,
2240 .mask = PMX_SSP_CS_MASK, 2240 .mask = PMX_SSP_CS_MASK,
2241 .val = 0, 2241 .val = 0,
2242 }, { 2242 }, {
2243 .reg = MODE_CONFIG_REG, 2243 .reg = MODE_CONFIG_REG,
2244 .mask = PMX_PWM_MASK, 2244 .mask = PMX_PWM_MASK,
2245 .val = PMX_PWM_MASK, 2245 .val = PMX_PWM_MASK,
2246 }, { 2246 }, {
2247 .reg = IP_SEL_PAD_30_39_REG, 2247 .reg = IP_SEL_PAD_30_39_REG,
2248 .mask = PMX_PL_34_MASK, 2248 .mask = PMX_PL_34_MASK,
2249 .val = PMX_PWM2_PL_34_VAL, 2249 .val = PMX_PWM2_PL_34_VAL,
2250 }, 2250 },
2251 }; 2251 };
2252 2252
2253 static struct spear_muxreg pwm2_pin_41_muxreg[] = { 2253 static struct spear_muxreg pwm2_pin_41_muxreg[] = {
2254 { 2254 {
2255 .reg = PMX_CONFIG_REG, 2255 .reg = PMX_CONFIG_REG,
2256 .mask = PMX_UART0_MODEM_MASK, 2256 .mask = PMX_UART0_MODEM_MASK,
2257 .val = 0, 2257 .val = 0,
2258 }, { 2258 }, {
2259 .reg = IP_SEL_PAD_40_49_REG, 2259 .reg = IP_SEL_PAD_40_49_REG,
2260 .mask = PMX_PL_41_MASK, 2260 .mask = PMX_PL_41_MASK,
2261 .val = PMX_PWM2_PL_41_VAL, 2261 .val = PMX_PWM2_PL_41_VAL,
2262 }, 2262 },
2263 }; 2263 };
2264 2264
2265 static struct spear_muxreg pwm2_pin_58_muxreg[] = { 2265 static struct spear_muxreg pwm2_pin_58_muxreg[] = {
2266 { 2266 {
2267 .reg = IP_SEL_PAD_50_59_REG, 2267 .reg = IP_SEL_PAD_50_59_REG,
2268 .mask = PMX_PL_58_MASK, 2268 .mask = PMX_PL_58_MASK,
2269 .val = PMX_PWM2_PL_58_VAL, 2269 .val = PMX_PWM2_PL_58_VAL,
2270 }, 2270 },
2271 }; 2271 };
2272 2272
2273 static struct spear_muxreg pwm2_pin_87_muxreg[] = { 2273 static struct spear_muxreg pwm2_pin_87_muxreg[] = {
2274 { 2274 {
2275 .reg = IP_SEL_PAD_80_89_REG, 2275 .reg = IP_SEL_PAD_80_89_REG,
2276 .mask = PMX_PL_87_MASK, 2276 .mask = PMX_PL_87_MASK,
2277 .val = PMX_PWM2_PL_87_VAL, 2277 .val = PMX_PWM2_PL_87_VAL,
2278 }, 2278 },
2279 }; 2279 };
2280 2280
2281 static struct spear_modemux pwm2_pin_7_modemux[] = { 2281 static struct spear_modemux pwm2_pin_7_modemux[] = {
2282 { 2282 {
2283 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, 2283 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2284 .muxregs = pwm2_net_muxreg, 2284 .muxregs = pwm2_net_muxreg,
2285 .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg), 2285 .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
2286 }, { 2286 }, {
2287 .modes = EXTENDED_MODE, 2287 .modes = EXTENDED_MODE,
2288 .muxregs = pwm2_pin_7_muxreg, 2288 .muxregs = pwm2_pin_7_muxreg,
2289 .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg), 2289 .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
2290 }, 2290 },
2291 }; 2291 };
2292 static struct spear_modemux pwm2_pin_13_modemux[] = { 2292 static struct spear_modemux pwm2_pin_13_modemux[] = {
2293 { 2293 {
2294 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, 2294 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2295 .muxregs = pwm2_autoexpsmallpri_muxreg, 2295 .muxregs = pwm2_autoexpsmallpri_muxreg,
2296 .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg), 2296 .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
2297 }, { 2297 }, {
2298 .modes = EXTENDED_MODE, 2298 .modes = EXTENDED_MODE,
2299 .muxregs = pwm2_pin_13_muxreg, 2299 .muxregs = pwm2_pin_13_muxreg,
2300 .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg), 2300 .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
2301 }, 2301 },
2302 }; 2302 };
2303 static struct spear_modemux pwm2_pin_29_modemux[] = { 2303 static struct spear_modemux pwm2_pin_29_modemux[] = {
2304 { 2304 {
2305 .modes = EXTENDED_MODE, 2305 .modes = EXTENDED_MODE,
2306 .muxregs = pwm2_pin_29_muxreg, 2306 .muxregs = pwm2_pin_29_muxreg,
2307 .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg), 2307 .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
2308 }, 2308 },
2309 }; 2309 };
2310 static struct spear_modemux pwm2_pin_34_modemux[] = { 2310 static struct spear_modemux pwm2_pin_34_modemux[] = {
2311 { 2311 {
2312 .modes = EXTENDED_MODE, 2312 .modes = EXTENDED_MODE,
2313 .muxregs = pwm2_pin_34_muxreg, 2313 .muxregs = pwm2_pin_34_muxreg,
2314 .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg), 2314 .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
2315 }, 2315 },
2316 }; 2316 };
2317 2317
2318 static struct spear_modemux pwm2_pin_41_modemux[] = { 2318 static struct spear_modemux pwm2_pin_41_modemux[] = {
2319 { 2319 {
2320 .modes = EXTENDED_MODE, 2320 .modes = EXTENDED_MODE,
2321 .muxregs = pwm2_pin_41_muxreg, 2321 .muxregs = pwm2_pin_41_muxreg,
2322 .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg), 2322 .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
2323 }, 2323 },
2324 }; 2324 };
2325 2325
2326 static struct spear_modemux pwm2_pin_58_modemux[] = { 2326 static struct spear_modemux pwm2_pin_58_modemux[] = {
2327 { 2327 {
2328 .modes = EXTENDED_MODE, 2328 .modes = EXTENDED_MODE,
2329 .muxregs = pwm2_pin_58_muxreg, 2329 .muxregs = pwm2_pin_58_muxreg,
2330 .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg), 2330 .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
2331 }, 2331 },
2332 }; 2332 };
2333 2333
2334 static struct spear_modemux pwm2_pin_87_modemux[] = { 2334 static struct spear_modemux pwm2_pin_87_modemux[] = {
2335 { 2335 {
2336 .modes = EXTENDED_MODE, 2336 .modes = EXTENDED_MODE,
2337 .muxregs = pwm2_pin_87_muxreg, 2337 .muxregs = pwm2_pin_87_muxreg,
2338 .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg), 2338 .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
2339 }, 2339 },
2340 }; 2340 };
2341 2341
2342 static struct spear_pingroup pwm2_pingroup[] = { 2342 static struct spear_pingroup pwm2_pingroup[] = {
2343 { 2343 {
2344 .name = "pwm2_pin_7_grp", 2344 .name = "pwm2_pin_7_grp",
2345 .pins = pwm2_pins[0], 2345 .pins = pwm2_pins[0],
2346 .npins = ARRAY_SIZE(pwm2_pins[0]), 2346 .npins = ARRAY_SIZE(pwm2_pins[0]),
2347 .modemuxs = pwm2_pin_7_modemux, 2347 .modemuxs = pwm2_pin_7_modemux,
2348 .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux), 2348 .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
2349 }, { 2349 }, {
2350 .name = "pwm2_pin_13_grp", 2350 .name = "pwm2_pin_13_grp",
2351 .pins = pwm2_pins[1], 2351 .pins = pwm2_pins[1],
2352 .npins = ARRAY_SIZE(pwm2_pins[1]), 2352 .npins = ARRAY_SIZE(pwm2_pins[1]),
2353 .modemuxs = pwm2_pin_13_modemux, 2353 .modemuxs = pwm2_pin_13_modemux,
2354 .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux), 2354 .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
2355 }, { 2355 }, {
2356 .name = "pwm2_pin_29_grp", 2356 .name = "pwm2_pin_29_grp",
2357 .pins = pwm2_pins[2], 2357 .pins = pwm2_pins[2],
2358 .npins = ARRAY_SIZE(pwm2_pins[2]), 2358 .npins = ARRAY_SIZE(pwm2_pins[2]),
2359 .modemuxs = pwm2_pin_29_modemux, 2359 .modemuxs = pwm2_pin_29_modemux,
2360 .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux), 2360 .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
2361 }, { 2361 }, {
2362 .name = "pwm2_pin_34_grp", 2362 .name = "pwm2_pin_34_grp",
2363 .pins = pwm2_pins[3], 2363 .pins = pwm2_pins[3],
2364 .npins = ARRAY_SIZE(pwm2_pins[3]), 2364 .npins = ARRAY_SIZE(pwm2_pins[3]),
2365 .modemuxs = pwm2_pin_34_modemux, 2365 .modemuxs = pwm2_pin_34_modemux,
2366 .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux), 2366 .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
2367 }, { 2367 }, {
2368 .name = "pwm2_pin_41_grp", 2368 .name = "pwm2_pin_41_grp",
2369 .pins = pwm2_pins[4], 2369 .pins = pwm2_pins[4],
2370 .npins = ARRAY_SIZE(pwm2_pins[4]), 2370 .npins = ARRAY_SIZE(pwm2_pins[4]),
2371 .modemuxs = pwm2_pin_41_modemux, 2371 .modemuxs = pwm2_pin_41_modemux,
2372 .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux), 2372 .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
2373 }, { 2373 }, {
2374 .name = "pwm2_pin_58_grp", 2374 .name = "pwm2_pin_58_grp",
2375 .pins = pwm2_pins[5], 2375 .pins = pwm2_pins[5],
2376 .npins = ARRAY_SIZE(pwm2_pins[5]), 2376 .npins = ARRAY_SIZE(pwm2_pins[5]),
2377 .modemuxs = pwm2_pin_58_modemux, 2377 .modemuxs = pwm2_pin_58_modemux,
2378 .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux), 2378 .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
2379 }, { 2379 }, {
2380 .name = "pwm2_pin_87_grp", 2380 .name = "pwm2_pin_87_grp",
2381 .pins = pwm2_pins[6], 2381 .pins = pwm2_pins[6],
2382 .npins = ARRAY_SIZE(pwm2_pins[6]), 2382 .npins = ARRAY_SIZE(pwm2_pins[6]),
2383 .modemuxs = pwm2_pin_87_modemux, 2383 .modemuxs = pwm2_pin_87_modemux,
2384 .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux), 2384 .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
2385 }, 2385 },
2386 }; 2386 };
2387 2387
2388 static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp", 2388 static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
2389 "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp", 2389 "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
2390 "pwm2_pin_58_grp", "pwm2_pin_87_grp" }; 2390 "pwm2_pin_58_grp", "pwm2_pin_87_grp" };
2391 static struct spear_function pwm2_function = { 2391 static struct spear_function pwm2_function = {
2392 .name = "pwm2", 2392 .name = "pwm2",
2393 .groups = pwm2_grps, 2393 .groups = pwm2_grps,
2394 .ngroups = ARRAY_SIZE(pwm2_grps), 2394 .ngroups = ARRAY_SIZE(pwm2_grps),
2395 }; 2395 };
2396 2396
2397 /* Pad multiplexing for PWM3 device */ 2397 /* Pad multiplexing for PWM3 device */
2398 static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 }, 2398 static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
2399 { 86 } }; 2399 { 86 } };
2400 static struct spear_muxreg pwm3_pin_6_muxreg[] = { 2400 static struct spear_muxreg pwm3_pin_6_muxreg[] = {
2401 { 2401 {
2402 .reg = PMX_CONFIG_REG, 2402 .reg = PMX_CONFIG_REG,
2403 .mask = PMX_SSP_MASK, 2403 .mask = PMX_SSP_MASK,
2404 .val = 0, 2404 .val = 0,
2405 }, { 2405 }, {
2406 .reg = IP_SEL_PAD_0_9_REG, 2406 .reg = IP_SEL_PAD_0_9_REG,
2407 .mask = PMX_PL_6_MASK, 2407 .mask = PMX_PL_6_MASK,
2408 .val = PMX_PWM_3_PL_6_VAL, 2408 .val = PMX_PWM_3_PL_6_VAL,
2409 }, 2409 },
2410 }; 2410 };
2411 2411
2412 static struct spear_muxreg pwm3_muxreg[] = { 2412 static struct spear_muxreg pwm3_muxreg[] = {
2413 { 2413 {
2414 .reg = PMX_CONFIG_REG, 2414 .reg = PMX_CONFIG_REG,
2415 .mask = PMX_MII_MASK, 2415 .mask = PMX_MII_MASK,
2416 .val = 0, 2416 .val = 0,
2417 }, 2417 },
2418 }; 2418 };
2419 2419
2420 static struct spear_muxreg pwm3_pin_12_muxreg[] = { 2420 static struct spear_muxreg pwm3_pin_12_muxreg[] = {
2421 { 2421 {
2422 .reg = IP_SEL_PAD_10_19_REG, 2422 .reg = IP_SEL_PAD_10_19_REG,
2423 .mask = PMX_PL_12_MASK, 2423 .mask = PMX_PL_12_MASK,
2424 .val = PMX_PWM3_PL_12_VAL, 2424 .val = PMX_PWM3_PL_12_VAL,
2425 }, 2425 },
2426 }; 2426 };
2427 2427
2428 static struct spear_muxreg pwm3_pin_28_muxreg[] = { 2428 static struct spear_muxreg pwm3_pin_28_muxreg[] = {
2429 { 2429 {
2430 .reg = PMX_CONFIG_REG, 2430 .reg = PMX_CONFIG_REG,
2431 .mask = PMX_GPIO_PIN0_MASK, 2431 .mask = PMX_GPIO_PIN0_MASK,
2432 .val = 0, 2432 .val = 0,
2433 }, { 2433 }, {
2434 .reg = IP_SEL_PAD_20_29_REG, 2434 .reg = IP_SEL_PAD_20_29_REG,
2435 .mask = PMX_PL_28_MASK, 2435 .mask = PMX_PL_28_MASK,
2436 .val = PMX_PWM_3_PL_28_VAL, 2436 .val = PMX_PWM_3_PL_28_VAL,
2437 }, 2437 },
2438 }; 2438 };
2439 2439
2440 static struct spear_muxreg pwm3_pin_40_muxreg[] = { 2440 static struct spear_muxreg pwm3_pin_40_muxreg[] = {
2441 { 2441 {
2442 .reg = PMX_CONFIG_REG, 2442 .reg = PMX_CONFIG_REG,
2443 .mask = PMX_UART0_MODEM_MASK, 2443 .mask = PMX_UART0_MODEM_MASK,
2444 .val = 0, 2444 .val = 0,
2445 }, { 2445 }, {
2446 .reg = IP_SEL_PAD_40_49_REG, 2446 .reg = IP_SEL_PAD_40_49_REG,
2447 .mask = PMX_PL_40_MASK, 2447 .mask = PMX_PL_40_MASK,
2448 .val = PMX_PWM3_PL_40_VAL, 2448 .val = PMX_PWM3_PL_40_VAL,
2449 }, 2449 },
2450 }; 2450 };
2451 2451
2452 static struct spear_muxreg pwm3_pin_57_muxreg[] = { 2452 static struct spear_muxreg pwm3_pin_57_muxreg[] = {
2453 { 2453 {
2454 .reg = IP_SEL_PAD_50_59_REG, 2454 .reg = IP_SEL_PAD_50_59_REG,
2455 .mask = PMX_PL_57_MASK, 2455 .mask = PMX_PL_57_MASK,
2456 .val = PMX_PWM3_PL_57_VAL, 2456 .val = PMX_PWM3_PL_57_VAL,
2457 }, 2457 },
2458 }; 2458 };
2459 2459
2460 static struct spear_muxreg pwm3_pin_86_muxreg[] = { 2460 static struct spear_muxreg pwm3_pin_86_muxreg[] = {
2461 { 2461 {
2462 .reg = IP_SEL_PAD_80_89_REG, 2462 .reg = IP_SEL_PAD_80_89_REG,
2463 .mask = PMX_PL_86_MASK, 2463 .mask = PMX_PL_86_MASK,
2464 .val = PMX_PWM3_PL_86_VAL, 2464 .val = PMX_PWM3_PL_86_VAL,
2465 }, 2465 },
2466 }; 2466 };
2467 2467
2468 static struct spear_modemux pwm3_pin_6_modemux[] = { 2468 static struct spear_modemux pwm3_pin_6_modemux[] = {
2469 { 2469 {
2470 .modes = EXTENDED_MODE, 2470 .modes = EXTENDED_MODE,
2471 .muxregs = pwm3_pin_6_muxreg, 2471 .muxregs = pwm3_pin_6_muxreg,
2472 .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg), 2472 .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
2473 }, 2473 },
2474 }; 2474 };
2475 2475
2476 static struct spear_modemux pwm3_pin_12_modemux[] = { 2476 static struct spear_modemux pwm3_pin_12_modemux[] = {
2477 { 2477 {
2478 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | 2478 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
2479 AUTO_NET_SMII_MODE | EXTENDED_MODE, 2479 AUTO_NET_SMII_MODE | EXTENDED_MODE,
2480 .muxregs = pwm3_muxreg, 2480 .muxregs = pwm3_muxreg,
2481 .nmuxregs = ARRAY_SIZE(pwm3_muxreg), 2481 .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
2482 }, { 2482 }, {
2483 .modes = EXTENDED_MODE, 2483 .modes = EXTENDED_MODE,
2484 .muxregs = pwm3_pin_12_muxreg, 2484 .muxregs = pwm3_pin_12_muxreg,
2485 .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg), 2485 .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
2486 }, 2486 },
2487 }; 2487 };
2488 2488
2489 static struct spear_modemux pwm3_pin_28_modemux[] = { 2489 static struct spear_modemux pwm3_pin_28_modemux[] = {
2490 { 2490 {
2491 .modes = EXTENDED_MODE, 2491 .modes = EXTENDED_MODE,
2492 .muxregs = pwm3_pin_28_muxreg, 2492 .muxregs = pwm3_pin_28_muxreg,
2493 .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg), 2493 .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
2494 }, 2494 },
2495 }; 2495 };
2496 2496
2497 static struct spear_modemux pwm3_pin_40_modemux[] = { 2497 static struct spear_modemux pwm3_pin_40_modemux[] = {
2498 { 2498 {
2499 .modes = EXTENDED_MODE, 2499 .modes = EXTENDED_MODE,
2500 .muxregs = pwm3_pin_40_muxreg, 2500 .muxregs = pwm3_pin_40_muxreg,
2501 .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg), 2501 .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
2502 }, 2502 },
2503 }; 2503 };
2504 2504
2505 static struct spear_modemux pwm3_pin_57_modemux[] = { 2505 static struct spear_modemux pwm3_pin_57_modemux[] = {
2506 { 2506 {
2507 .modes = EXTENDED_MODE, 2507 .modes = EXTENDED_MODE,
2508 .muxregs = pwm3_pin_57_muxreg, 2508 .muxregs = pwm3_pin_57_muxreg,
2509 .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg), 2509 .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
2510 }, 2510 },
2511 }; 2511 };
2512 2512
2513 static struct spear_modemux pwm3_pin_86_modemux[] = { 2513 static struct spear_modemux pwm3_pin_86_modemux[] = {
2514 { 2514 {
2515 .modes = EXTENDED_MODE, 2515 .modes = EXTENDED_MODE,
2516 .muxregs = pwm3_pin_86_muxreg, 2516 .muxregs = pwm3_pin_86_muxreg,
2517 .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg), 2517 .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
2518 }, 2518 },
2519 }; 2519 };
2520 2520
2521 static struct spear_pingroup pwm3_pingroup[] = { 2521 static struct spear_pingroup pwm3_pingroup[] = {
2522 { 2522 {
2523 .name = "pwm3_pin_6_grp", 2523 .name = "pwm3_pin_6_grp",
2524 .pins = pwm3_pins[0], 2524 .pins = pwm3_pins[0],
2525 .npins = ARRAY_SIZE(pwm3_pins[0]), 2525 .npins = ARRAY_SIZE(pwm3_pins[0]),
2526 .modemuxs = pwm3_pin_6_modemux, 2526 .modemuxs = pwm3_pin_6_modemux,
2527 .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux), 2527 .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
2528 }, { 2528 }, {
2529 .name = "pwm3_pin_12_grp", 2529 .name = "pwm3_pin_12_grp",
2530 .pins = pwm3_pins[1], 2530 .pins = pwm3_pins[1],
2531 .npins = ARRAY_SIZE(pwm3_pins[1]), 2531 .npins = ARRAY_SIZE(pwm3_pins[1]),
2532 .modemuxs = pwm3_pin_12_modemux, 2532 .modemuxs = pwm3_pin_12_modemux,
2533 .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux), 2533 .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
2534 }, { 2534 }, {
2535 .name = "pwm3_pin_28_grp", 2535 .name = "pwm3_pin_28_grp",
2536 .pins = pwm3_pins[2], 2536 .pins = pwm3_pins[2],
2537 .npins = ARRAY_SIZE(pwm3_pins[2]), 2537 .npins = ARRAY_SIZE(pwm3_pins[2]),
2538 .modemuxs = pwm3_pin_28_modemux, 2538 .modemuxs = pwm3_pin_28_modemux,
2539 .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux), 2539 .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
2540 }, { 2540 }, {
2541 .name = "pwm3_pin_40_grp", 2541 .name = "pwm3_pin_40_grp",
2542 .pins = pwm3_pins[3], 2542 .pins = pwm3_pins[3],
2543 .npins = ARRAY_SIZE(pwm3_pins[3]), 2543 .npins = ARRAY_SIZE(pwm3_pins[3]),
2544 .modemuxs = pwm3_pin_40_modemux, 2544 .modemuxs = pwm3_pin_40_modemux,
2545 .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux), 2545 .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
2546 }, { 2546 }, {
2547 .name = "pwm3_pin_57_grp", 2547 .name = "pwm3_pin_57_grp",
2548 .pins = pwm3_pins[4], 2548 .pins = pwm3_pins[4],
2549 .npins = ARRAY_SIZE(pwm3_pins[4]), 2549 .npins = ARRAY_SIZE(pwm3_pins[4]),
2550 .modemuxs = pwm3_pin_57_modemux, 2550 .modemuxs = pwm3_pin_57_modemux,
2551 .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux), 2551 .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
2552 }, { 2552 }, {
2553 .name = "pwm3_pin_86_grp", 2553 .name = "pwm3_pin_86_grp",
2554 .pins = pwm3_pins[5], 2554 .pins = pwm3_pins[5],
2555 .npins = ARRAY_SIZE(pwm3_pins[5]), 2555 .npins = ARRAY_SIZE(pwm3_pins[5]),
2556 .modemuxs = pwm3_pin_86_modemux, 2556 .modemuxs = pwm3_pin_86_modemux,
2557 .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux), 2557 .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
2558 }, 2558 },
2559 }; 2559 };
2560 2560
2561 static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp", 2561 static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
2562 "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp", 2562 "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
2563 "pwm3_pin_86_grp" }; 2563 "pwm3_pin_86_grp" };
2564 static struct spear_function pwm3_function = { 2564 static struct spear_function pwm3_function = {
2565 .name = "pwm3", 2565 .name = "pwm3",
2566 .groups = pwm3_grps, 2566 .groups = pwm3_grps,
2567 .ngroups = ARRAY_SIZE(pwm3_grps), 2567 .ngroups = ARRAY_SIZE(pwm3_grps),
2568 }; 2568 };
2569 2569
2570 /* Pad multiplexing for SSP1 device */ 2570 /* Pad multiplexing for SSP1 device */
2571 static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 }, 2571 static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
2572 { 65, 68 }, { 94, 97 } }; 2572 { 65, 68 }, { 94, 97 } };
2573 static struct spear_muxreg ssp1_muxreg[] = { 2573 static struct spear_muxreg ssp1_muxreg[] = {
2574 { 2574 {
2575 .reg = PMX_CONFIG_REG, 2575 .reg = PMX_CONFIG_REG,
2576 .mask = PMX_MII_MASK, 2576 .mask = PMX_MII_MASK,
2577 .val = 0, 2577 .val = 0,
2578 }, 2578 },
2579 }; 2579 };
2580 2580
2581 static struct spear_muxreg ssp1_ext_17_20_muxreg[] = { 2581 static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
2582 { 2582 {
2583 .reg = IP_SEL_PAD_10_19_REG, 2583 .reg = IP_SEL_PAD_10_19_REG,
2584 .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK, 2584 .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2585 .val = PMX_SSP1_PL_17_18_19_20_VAL, 2585 .val = PMX_SSP1_PL_17_18_19_20_VAL,
2586 }, { 2586 }, {
2587 .reg = IP_SEL_PAD_20_29_REG, 2587 .reg = IP_SEL_PAD_20_29_REG,
2588 .mask = PMX_PL_20_MASK, 2588 .mask = PMX_PL_20_MASK,
2589 .val = PMX_SSP1_PL_17_18_19_20_VAL, 2589 .val = PMX_SSP1_PL_17_18_19_20_VAL,
2590 }, { 2590 }, {
2591 .reg = IP_SEL_MIX_PAD_REG, 2591 .reg = IP_SEL_MIX_PAD_REG,
2592 .mask = PMX_SSP1_PORT_SEL_MASK, 2592 .mask = PMX_SSP1_PORT_SEL_MASK,
2593 .val = PMX_SSP1_PORT_17_TO_20_VAL, 2593 .val = PMX_SSP1_PORT_17_TO_20_VAL,
2594 }, 2594 },
2595 }; 2595 };
2596 2596
2597 static struct spear_muxreg ssp1_ext_36_39_muxreg[] = { 2597 static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
2598 { 2598 {
2599 .reg = PMX_CONFIG_REG, 2599 .reg = PMX_CONFIG_REG,
2600 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, 2600 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
2601 .val = 0, 2601 .val = 0,
2602 }, { 2602 }, {
2603 .reg = IP_SEL_PAD_30_39_REG, 2603 .reg = IP_SEL_PAD_30_39_REG,
2604 .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK, 2604 .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
2605 .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL | 2605 .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
2606 PMX_SSP1_PL_39_VAL, 2606 PMX_SSP1_PL_39_VAL,
2607 }, { 2607 }, {
2608 .reg = IP_SEL_MIX_PAD_REG, 2608 .reg = IP_SEL_MIX_PAD_REG,
2609 .mask = PMX_SSP1_PORT_SEL_MASK, 2609 .mask = PMX_SSP1_PORT_SEL_MASK,
2610 .val = PMX_SSP1_PORT_36_TO_39_VAL, 2610 .val = PMX_SSP1_PORT_36_TO_39_VAL,
2611 }, 2611 },
2612 }; 2612 };
2613 2613
2614 static struct spear_muxreg ssp1_ext_48_51_muxreg[] = { 2614 static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
2615 { 2615 {
2616 .reg = PMX_CONFIG_REG, 2616 .reg = PMX_CONFIG_REG,
2617 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 2617 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2618 .val = 0, 2618 .val = 0,
2619 }, { 2619 }, {
2620 .reg = IP_SEL_PAD_40_49_REG, 2620 .reg = IP_SEL_PAD_40_49_REG,
2621 .mask = PMX_PL_48_49_MASK, 2621 .mask = PMX_PL_48_49_MASK,
2622 .val = PMX_SSP1_PL_48_49_VAL, 2622 .val = PMX_SSP1_PL_48_49_VAL,
2623 }, { 2623 }, {
2624 .reg = IP_SEL_PAD_50_59_REG, 2624 .reg = IP_SEL_PAD_50_59_REG,
2625 .mask = PMX_PL_50_51_MASK, 2625 .mask = PMX_PL_50_51_MASK,
2626 .val = PMX_SSP1_PL_50_51_VAL, 2626 .val = PMX_SSP1_PL_50_51_VAL,
2627 }, { 2627 }, {
2628 .reg = IP_SEL_MIX_PAD_REG, 2628 .reg = IP_SEL_MIX_PAD_REG,
2629 .mask = PMX_SSP1_PORT_SEL_MASK, 2629 .mask = PMX_SSP1_PORT_SEL_MASK,
2630 .val = PMX_SSP1_PORT_48_TO_51_VAL, 2630 .val = PMX_SSP1_PORT_48_TO_51_VAL,
2631 }, 2631 },
2632 }; 2632 };
2633 2633
2634 static struct spear_muxreg ssp1_ext_65_68_muxreg[] = { 2634 static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
2635 { 2635 {
2636 .reg = IP_SEL_PAD_60_69_REG, 2636 .reg = IP_SEL_PAD_60_69_REG,
2637 .mask = PMX_PL_65_TO_68_MASK, 2637 .mask = PMX_PL_65_TO_68_MASK,
2638 .val = PMX_SSP1_PL_65_TO_68_VAL, 2638 .val = PMX_SSP1_PL_65_TO_68_VAL,
2639 }, { 2639 }, {
2640 .reg = IP_SEL_MIX_PAD_REG, 2640 .reg = IP_SEL_MIX_PAD_REG,
2641 .mask = PMX_SSP1_PORT_SEL_MASK, 2641 .mask = PMX_SSP1_PORT_SEL_MASK,
2642 .val = PMX_SSP1_PORT_65_TO_68_VAL, 2642 .val = PMX_SSP1_PORT_65_TO_68_VAL,
2643 }, 2643 },
2644 }; 2644 };
2645 2645
2646 static struct spear_muxreg ssp1_ext_94_97_muxreg[] = { 2646 static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
2647 { 2647 {
2648 .reg = IP_SEL_PAD_90_99_REG, 2648 .reg = IP_SEL_PAD_90_99_REG,
2649 .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, 2649 .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2650 .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL, 2650 .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
2651 }, { 2651 }, {
2652 .reg = IP_SEL_MIX_PAD_REG, 2652 .reg = IP_SEL_MIX_PAD_REG,
2653 .mask = PMX_SSP1_PORT_SEL_MASK, 2653 .mask = PMX_SSP1_PORT_SEL_MASK,
2654 .val = PMX_SSP1_PORT_94_TO_97_VAL, 2654 .val = PMX_SSP1_PORT_94_TO_97_VAL,
2655 }, 2655 },
2656 }; 2656 };
2657 2657
2658 static struct spear_modemux ssp1_17_20_modemux[] = { 2658 static struct spear_modemux ssp1_17_20_modemux[] = {
2659 { 2659 {
2660 .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE | 2660 .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
2661 EXTENDED_MODE, 2661 EXTENDED_MODE,
2662 .muxregs = ssp1_muxreg, 2662 .muxregs = ssp1_muxreg,
2663 .nmuxregs = ARRAY_SIZE(ssp1_muxreg), 2663 .nmuxregs = ARRAY_SIZE(ssp1_muxreg),
2664 }, { 2664 }, {
2665 .modes = EXTENDED_MODE, 2665 .modes = EXTENDED_MODE,
2666 .muxregs = ssp1_ext_17_20_muxreg, 2666 .muxregs = ssp1_ext_17_20_muxreg,
2667 .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg), 2667 .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
2668 }, 2668 },
2669 }; 2669 };
2670 2670
2671 static struct spear_modemux ssp1_36_39_modemux[] = { 2671 static struct spear_modemux ssp1_36_39_modemux[] = {
2672 { 2672 {
2673 .modes = EXTENDED_MODE, 2673 .modes = EXTENDED_MODE,
2674 .muxregs = ssp1_ext_36_39_muxreg, 2674 .muxregs = ssp1_ext_36_39_muxreg,
2675 .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg), 2675 .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
2676 }, 2676 },
2677 }; 2677 };
2678 2678
2679 static struct spear_modemux ssp1_48_51_modemux[] = { 2679 static struct spear_modemux ssp1_48_51_modemux[] = {
2680 { 2680 {
2681 .modes = EXTENDED_MODE, 2681 .modes = EXTENDED_MODE,
2682 .muxregs = ssp1_ext_48_51_muxreg, 2682 .muxregs = ssp1_ext_48_51_muxreg,
2683 .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg), 2683 .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
2684 }, 2684 },
2685 }; 2685 };
2686 static struct spear_modemux ssp1_65_68_modemux[] = { 2686 static struct spear_modemux ssp1_65_68_modemux[] = {
2687 { 2687 {
2688 .modes = EXTENDED_MODE, 2688 .modes = EXTENDED_MODE,
2689 .muxregs = ssp1_ext_65_68_muxreg, 2689 .muxregs = ssp1_ext_65_68_muxreg,
2690 .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg), 2690 .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
2691 }, 2691 },
2692 }; 2692 };
2693 2693
2694 static struct spear_modemux ssp1_94_97_modemux[] = { 2694 static struct spear_modemux ssp1_94_97_modemux[] = {
2695 { 2695 {
2696 .modes = EXTENDED_MODE, 2696 .modes = EXTENDED_MODE,
2697 .muxregs = ssp1_ext_94_97_muxreg, 2697 .muxregs = ssp1_ext_94_97_muxreg,
2698 .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg), 2698 .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
2699 }, 2699 },
2700 }; 2700 };
2701 2701
2702 static struct spear_pingroup ssp1_pingroup[] = { 2702 static struct spear_pingroup ssp1_pingroup[] = {
2703 { 2703 {
2704 .name = "ssp1_17_20_grp", 2704 .name = "ssp1_17_20_grp",
2705 .pins = ssp1_pins[0], 2705 .pins = ssp1_pins[0],
2706 .npins = ARRAY_SIZE(ssp1_pins[0]), 2706 .npins = ARRAY_SIZE(ssp1_pins[0]),
2707 .modemuxs = ssp1_17_20_modemux, 2707 .modemuxs = ssp1_17_20_modemux,
2708 .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux), 2708 .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
2709 }, { 2709 }, {
2710 .name = "ssp1_36_39_grp", 2710 .name = "ssp1_36_39_grp",
2711 .pins = ssp1_pins[1], 2711 .pins = ssp1_pins[1],
2712 .npins = ARRAY_SIZE(ssp1_pins[1]), 2712 .npins = ARRAY_SIZE(ssp1_pins[1]),
2713 .modemuxs = ssp1_36_39_modemux, 2713 .modemuxs = ssp1_36_39_modemux,
2714 .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux), 2714 .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
2715 }, { 2715 }, {
2716 .name = "ssp1_48_51_grp", 2716 .name = "ssp1_48_51_grp",
2717 .pins = ssp1_pins[2], 2717 .pins = ssp1_pins[2],
2718 .npins = ARRAY_SIZE(ssp1_pins[2]), 2718 .npins = ARRAY_SIZE(ssp1_pins[2]),
2719 .modemuxs = ssp1_48_51_modemux, 2719 .modemuxs = ssp1_48_51_modemux,
2720 .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux), 2720 .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
2721 }, { 2721 }, {
2722 .name = "ssp1_65_68_grp", 2722 .name = "ssp1_65_68_grp",
2723 .pins = ssp1_pins[3], 2723 .pins = ssp1_pins[3],
2724 .npins = ARRAY_SIZE(ssp1_pins[3]), 2724 .npins = ARRAY_SIZE(ssp1_pins[3]),
2725 .modemuxs = ssp1_65_68_modemux, 2725 .modemuxs = ssp1_65_68_modemux,
2726 .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux), 2726 .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
2727 }, { 2727 }, {
2728 .name = "ssp1_94_97_grp", 2728 .name = "ssp1_94_97_grp",
2729 .pins = ssp1_pins[4], 2729 .pins = ssp1_pins[4],
2730 .npins = ARRAY_SIZE(ssp1_pins[4]), 2730 .npins = ARRAY_SIZE(ssp1_pins[4]),
2731 .modemuxs = ssp1_94_97_modemux, 2731 .modemuxs = ssp1_94_97_modemux,
2732 .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux), 2732 .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
2733 }, 2733 },
2734 }; 2734 };
2735 2735
2736 static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp", 2736 static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
2737 "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp" 2737 "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
2738 }; 2738 };
2739 static struct spear_function ssp1_function = { 2739 static struct spear_function ssp1_function = {
2740 .name = "ssp1", 2740 .name = "ssp1",
2741 .groups = ssp1_grps, 2741 .groups = ssp1_grps,
2742 .ngroups = ARRAY_SIZE(ssp1_grps), 2742 .ngroups = ARRAY_SIZE(ssp1_grps),
2743 }; 2743 };
2744 2744
2745 /* Pad multiplexing for SSP2 device */ 2745 /* Pad multiplexing for SSP2 device */
2746 static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 }, 2746 static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
2747 { 61, 64 }, { 90, 93 } }; 2747 { 61, 64 }, { 90, 93 } };
2748 static struct spear_muxreg ssp2_muxreg[] = { 2748 static struct spear_muxreg ssp2_muxreg[] = {
2749 { 2749 {
2750 .reg = PMX_CONFIG_REG, 2750 .reg = PMX_CONFIG_REG,
2751 .mask = PMX_MII_MASK, 2751 .mask = PMX_MII_MASK,
2752 .val = 0, 2752 .val = 0,
2753 }, 2753 },
2754 }; 2754 };
2755 2755
2756 static struct spear_muxreg ssp2_ext_13_16_muxreg[] = { 2756 static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
2757 { 2757 {
2758 .reg = IP_SEL_PAD_10_19_REG, 2758 .reg = IP_SEL_PAD_10_19_REG,
2759 .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK, 2759 .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
2760 .val = PMX_SSP2_PL_13_14_15_16_VAL, 2760 .val = PMX_SSP2_PL_13_14_15_16_VAL,
2761 }, { 2761 }, {
2762 .reg = IP_SEL_MIX_PAD_REG, 2762 .reg = IP_SEL_MIX_PAD_REG,
2763 .mask = PMX_SSP2_PORT_SEL_MASK, 2763 .mask = PMX_SSP2_PORT_SEL_MASK,
2764 .val = PMX_SSP2_PORT_13_TO_16_VAL, 2764 .val = PMX_SSP2_PORT_13_TO_16_VAL,
2765 }, 2765 },
2766 }; 2766 };
2767 2767
2768 static struct spear_muxreg ssp2_ext_32_35_muxreg[] = { 2768 static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
2769 { 2769 {
2770 .reg = PMX_CONFIG_REG, 2770 .reg = PMX_CONFIG_REG,
2771 .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK | 2771 .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
2772 PMX_GPIO_PIN5_MASK, 2772 PMX_GPIO_PIN5_MASK,
2773 .val = 0, 2773 .val = 0,
2774 }, { 2774 }, {
2775 .reg = IP_SEL_PAD_30_39_REG, 2775 .reg = IP_SEL_PAD_30_39_REG,
2776 .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK, 2776 .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
2777 .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL | 2777 .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
2778 PMX_SSP2_PL_35_VAL, 2778 PMX_SSP2_PL_35_VAL,
2779 }, { 2779 }, {
2780 .reg = IP_SEL_MIX_PAD_REG, 2780 .reg = IP_SEL_MIX_PAD_REG,
2781 .mask = PMX_SSP2_PORT_SEL_MASK, 2781 .mask = PMX_SSP2_PORT_SEL_MASK,
2782 .val = PMX_SSP2_PORT_32_TO_35_VAL, 2782 .val = PMX_SSP2_PORT_32_TO_35_VAL,
2783 }, 2783 },
2784 }; 2784 };
2785 2785
2786 static struct spear_muxreg ssp2_ext_44_47_muxreg[] = { 2786 static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
2787 { 2787 {
2788 .reg = PMX_CONFIG_REG, 2788 .reg = PMX_CONFIG_REG,
2789 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 2789 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2790 .val = 0, 2790 .val = 0,
2791 }, { 2791 }, {
2792 .reg = IP_SEL_PAD_40_49_REG, 2792 .reg = IP_SEL_PAD_40_49_REG,
2793 .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK, 2793 .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
2794 .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL, 2794 .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
2795 }, { 2795 }, {
2796 .reg = IP_SEL_MIX_PAD_REG, 2796 .reg = IP_SEL_MIX_PAD_REG,
2797 .mask = PMX_SSP2_PORT_SEL_MASK, 2797 .mask = PMX_SSP2_PORT_SEL_MASK,
2798 .val = PMX_SSP2_PORT_44_TO_47_VAL, 2798 .val = PMX_SSP2_PORT_44_TO_47_VAL,
2799 }, 2799 },
2800 }; 2800 };
2801 2801
2802 static struct spear_muxreg ssp2_ext_61_64_muxreg[] = { 2802 static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
2803 { 2803 {
2804 .reg = IP_SEL_PAD_60_69_REG, 2804 .reg = IP_SEL_PAD_60_69_REG,
2805 .mask = PMX_PL_61_TO_64_MASK, 2805 .mask = PMX_PL_61_TO_64_MASK,
2806 .val = PMX_SSP2_PL_61_TO_64_VAL, 2806 .val = PMX_SSP2_PL_61_TO_64_VAL,
2807 }, { 2807 }, {
2808 .reg = IP_SEL_MIX_PAD_REG, 2808 .reg = IP_SEL_MIX_PAD_REG,
2809 .mask = PMX_SSP2_PORT_SEL_MASK, 2809 .mask = PMX_SSP2_PORT_SEL_MASK,
2810 .val = PMX_SSP2_PORT_61_TO_64_VAL, 2810 .val = PMX_SSP2_PORT_61_TO_64_VAL,
2811 }, 2811 },
2812 }; 2812 };
2813 2813
2814 static struct spear_muxreg ssp2_ext_90_93_muxreg[] = { 2814 static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
2815 { 2815 {
2816 .reg = IP_SEL_PAD_90_99_REG, 2816 .reg = IP_SEL_PAD_90_99_REG,
2817 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK, 2817 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
2818 .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL, 2818 .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
2819 }, { 2819 }, {
2820 .reg = IP_SEL_MIX_PAD_REG, 2820 .reg = IP_SEL_MIX_PAD_REG,
2821 .mask = PMX_SSP2_PORT_SEL_MASK, 2821 .mask = PMX_SSP2_PORT_SEL_MASK,
2822 .val = PMX_SSP2_PORT_90_TO_93_VAL, 2822 .val = PMX_SSP2_PORT_90_TO_93_VAL,
2823 }, 2823 },
2824 }; 2824 };
2825 2825
2826 static struct spear_modemux ssp2_13_16_modemux[] = { 2826 static struct spear_modemux ssp2_13_16_modemux[] = {
2827 { 2827 {
2828 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, 2828 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
2829 .muxregs = ssp2_muxreg, 2829 .muxregs = ssp2_muxreg,
2830 .nmuxregs = ARRAY_SIZE(ssp2_muxreg), 2830 .nmuxregs = ARRAY_SIZE(ssp2_muxreg),
2831 }, { 2831 }, {
2832 .modes = EXTENDED_MODE, 2832 .modes = EXTENDED_MODE,
2833 .muxregs = ssp2_ext_13_16_muxreg, 2833 .muxregs = ssp2_ext_13_16_muxreg,
2834 .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg), 2834 .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
2835 }, 2835 },
2836 }; 2836 };
2837 2837
2838 static struct spear_modemux ssp2_32_35_modemux[] = { 2838 static struct spear_modemux ssp2_32_35_modemux[] = {
2839 { 2839 {
2840 .modes = EXTENDED_MODE, 2840 .modes = EXTENDED_MODE,
2841 .muxregs = ssp2_ext_32_35_muxreg, 2841 .muxregs = ssp2_ext_32_35_muxreg,
2842 .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg), 2842 .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
2843 }, 2843 },
2844 }; 2844 };
2845 2845
2846 static struct spear_modemux ssp2_44_47_modemux[] = { 2846 static struct spear_modemux ssp2_44_47_modemux[] = {
2847 { 2847 {
2848 .modes = EXTENDED_MODE, 2848 .modes = EXTENDED_MODE,
2849 .muxregs = ssp2_ext_44_47_muxreg, 2849 .muxregs = ssp2_ext_44_47_muxreg,
2850 .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg), 2850 .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
2851 }, 2851 },
2852 }; 2852 };
2853 2853
2854 static struct spear_modemux ssp2_61_64_modemux[] = { 2854 static struct spear_modemux ssp2_61_64_modemux[] = {
2855 { 2855 {
2856 .modes = EXTENDED_MODE, 2856 .modes = EXTENDED_MODE,
2857 .muxregs = ssp2_ext_61_64_muxreg, 2857 .muxregs = ssp2_ext_61_64_muxreg,
2858 .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg), 2858 .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
2859 }, 2859 },
2860 }; 2860 };
2861 2861
2862 static struct spear_modemux ssp2_90_93_modemux[] = { 2862 static struct spear_modemux ssp2_90_93_modemux[] = {
2863 { 2863 {
2864 .modes = EXTENDED_MODE, 2864 .modes = EXTENDED_MODE,
2865 .muxregs = ssp2_ext_90_93_muxreg, 2865 .muxregs = ssp2_ext_90_93_muxreg,
2866 .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg), 2866 .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
2867 }, 2867 },
2868 }; 2868 };
2869 2869
2870 static struct spear_pingroup ssp2_pingroup[] = { 2870 static struct spear_pingroup ssp2_pingroup[] = {
2871 { 2871 {
2872 .name = "ssp2_13_16_grp", 2872 .name = "ssp2_13_16_grp",
2873 .pins = ssp2_pins[0], 2873 .pins = ssp2_pins[0],
2874 .npins = ARRAY_SIZE(ssp2_pins[0]), 2874 .npins = ARRAY_SIZE(ssp2_pins[0]),
2875 .modemuxs = ssp2_13_16_modemux, 2875 .modemuxs = ssp2_13_16_modemux,
2876 .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux), 2876 .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
2877 }, { 2877 }, {
2878 .name = "ssp2_32_35_grp", 2878 .name = "ssp2_32_35_grp",
2879 .pins = ssp2_pins[1], 2879 .pins = ssp2_pins[1],
2880 .npins = ARRAY_SIZE(ssp2_pins[1]), 2880 .npins = ARRAY_SIZE(ssp2_pins[1]),
2881 .modemuxs = ssp2_32_35_modemux, 2881 .modemuxs = ssp2_32_35_modemux,
2882 .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux), 2882 .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
2883 }, { 2883 }, {
2884 .name = "ssp2_44_47_grp", 2884 .name = "ssp2_44_47_grp",
2885 .pins = ssp2_pins[2], 2885 .pins = ssp2_pins[2],
2886 .npins = ARRAY_SIZE(ssp2_pins[2]), 2886 .npins = ARRAY_SIZE(ssp2_pins[2]),
2887 .modemuxs = ssp2_44_47_modemux, 2887 .modemuxs = ssp2_44_47_modemux,
2888 .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux), 2888 .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
2889 }, { 2889 }, {
2890 .name = "ssp2_61_64_grp", 2890 .name = "ssp2_61_64_grp",
2891 .pins = ssp2_pins[3], 2891 .pins = ssp2_pins[3],
2892 .npins = ARRAY_SIZE(ssp2_pins[3]), 2892 .npins = ARRAY_SIZE(ssp2_pins[3]),
2893 .modemuxs = ssp2_61_64_modemux, 2893 .modemuxs = ssp2_61_64_modemux,
2894 .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux), 2894 .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
2895 }, { 2895 }, {
2896 .name = "ssp2_90_93_grp", 2896 .name = "ssp2_90_93_grp",
2897 .pins = ssp2_pins[4], 2897 .pins = ssp2_pins[4],
2898 .npins = ARRAY_SIZE(ssp2_pins[4]), 2898 .npins = ARRAY_SIZE(ssp2_pins[4]),
2899 .modemuxs = ssp2_90_93_modemux, 2899 .modemuxs = ssp2_90_93_modemux,
2900 .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux), 2900 .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
2901 }, 2901 },
2902 }; 2902 };
2903 2903
2904 static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp", 2904 static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
2905 "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" }; 2905 "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
2906 static struct spear_function ssp2_function = { 2906 static struct spear_function ssp2_function = {
2907 .name = "ssp2", 2907 .name = "ssp2",
2908 .groups = ssp2_grps, 2908 .groups = ssp2_grps,
2909 .ngroups = ARRAY_SIZE(ssp2_grps), 2909 .ngroups = ARRAY_SIZE(ssp2_grps),
2910 }; 2910 };
2911 2911
2912 /* Pad multiplexing for cadence mii2 as mii device */ 2912 /* Pad multiplexing for cadence mii2 as mii device */
2913 static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 2913 static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
2914 90, 91, 92, 93, 94, 95, 96, 97 }; 2914 90, 91, 92, 93, 94, 95, 96, 97 };
2915 static struct spear_muxreg mii2_muxreg[] = { 2915 static struct spear_muxreg mii2_muxreg[] = {
2916 { 2916 {
2917 .reg = IP_SEL_PAD_80_89_REG, 2917 .reg = IP_SEL_PAD_80_89_REG,
2918 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | 2918 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
2919 PMX_PL_88_89_MASK, 2919 PMX_PL_88_89_MASK,
2920 .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL | 2920 .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
2921 PMX_MII2_PL_88_89_VAL, 2921 PMX_MII2_PL_88_89_VAL,
2922 }, { 2922 }, {
2923 .reg = IP_SEL_PAD_90_99_REG, 2923 .reg = IP_SEL_PAD_90_99_REG,
2924 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | 2924 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
2925 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, 2925 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2926 .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL | 2926 .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
2927 PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL, 2927 PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
2928 }, { 2928 }, {
2929 .reg = EXT_CTRL_REG, 2929 .reg = EXT_CTRL_REG,
2930 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | 2930 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2931 (MAC_MODE_MASK << MAC1_MODE_SHIFT) | 2931 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2932 MII_MDIO_MASK, 2932 MII_MDIO_MASK,
2933 .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) | 2933 .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
2934 (MAC_MODE_MII << MAC1_MODE_SHIFT) | 2934 (MAC_MODE_MII << MAC1_MODE_SHIFT) |
2935 MII_MDIO_81_VAL, 2935 MII_MDIO_81_VAL,
2936 }, 2936 },
2937 }; 2937 };
2938 2938
2939 static struct spear_modemux mii2_modemux[] = { 2939 static struct spear_modemux mii2_modemux[] = {
2940 { 2940 {
2941 .modes = EXTENDED_MODE, 2941 .modes = EXTENDED_MODE,
2942 .muxregs = mii2_muxreg, 2942 .muxregs = mii2_muxreg,
2943 .nmuxregs = ARRAY_SIZE(mii2_muxreg), 2943 .nmuxregs = ARRAY_SIZE(mii2_muxreg),
2944 }, 2944 },
2945 }; 2945 };
2946 2946
2947 static struct spear_pingroup mii2_pingroup = { 2947 static struct spear_pingroup mii2_pingroup = {
2948 .name = "mii2_grp", 2948 .name = "mii2_grp",
2949 .pins = mii2_pins, 2949 .pins = mii2_pins,
2950 .npins = ARRAY_SIZE(mii2_pins), 2950 .npins = ARRAY_SIZE(mii2_pins),
2951 .modemuxs = mii2_modemux, 2951 .modemuxs = mii2_modemux,
2952 .nmodemuxs = ARRAY_SIZE(mii2_modemux), 2952 .nmodemuxs = ARRAY_SIZE(mii2_modemux),
2953 }; 2953 };
2954 2954
2955 static const char *const mii2_grps[] = { "mii2_grp" }; 2955 static const char *const mii2_grps[] = { "mii2_grp" };
2956 static struct spear_function mii2_function = { 2956 static struct spear_function mii2_function = {
2957 .name = "mii2", 2957 .name = "mii2",
2958 .groups = mii2_grps, 2958 .groups = mii2_grps,
2959 .ngroups = ARRAY_SIZE(mii2_grps), 2959 .ngroups = ARRAY_SIZE(mii2_grps),
2960 }; 2960 };
2961 2961
2962 /* Pad multiplexing for cadence mii 1_2 as smii or rmii device */ 2962 /* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
2963 static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 2963 static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
2964 21, 22, 23, 24, 25, 26, 27 }; 2964 21, 22, 23, 24, 25, 26, 27 };
2965 static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 }; 2965 static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
2966 static struct spear_muxreg mii0_1_muxreg[] = { 2966 static struct spear_muxreg mii0_1_muxreg[] = {
2967 { 2967 {
2968 .reg = PMX_CONFIG_REG, 2968 .reg = PMX_CONFIG_REG,
2969 .mask = PMX_MII_MASK, 2969 .mask = PMX_MII_MASK,
2970 .val = 0, 2970 .val = 0,
2971 }, 2971 },
2972 }; 2972 };
2973 2973
2974 static struct spear_muxreg smii0_1_ext_muxreg[] = { 2974 static struct spear_muxreg smii0_1_ext_muxreg[] = {
2975 { 2975 {
2976 .reg = IP_SEL_PAD_10_19_REG, 2976 .reg = IP_SEL_PAD_10_19_REG,
2977 .mask = PMX_PL_10_11_MASK, 2977 .mask = PMX_PL_10_11_MASK,
2978 .val = PMX_SMII_PL_10_11_VAL, 2978 .val = PMX_SMII_PL_10_11_VAL,
2979 }, { 2979 }, {
2980 .reg = IP_SEL_PAD_20_29_REG, 2980 .reg = IP_SEL_PAD_20_29_REG,
2981 .mask = PMX_PL_21_TO_27_MASK, 2981 .mask = PMX_PL_21_TO_27_MASK,
2982 .val = PMX_SMII_PL_21_TO_27_VAL, 2982 .val = PMX_SMII_PL_21_TO_27_VAL,
2983 }, { 2983 }, {
2984 .reg = EXT_CTRL_REG, 2984 .reg = EXT_CTRL_REG,
2985 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | 2985 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2986 (MAC_MODE_MASK << MAC1_MODE_SHIFT) | 2986 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2987 MII_MDIO_MASK, 2987 MII_MDIO_MASK,
2988 .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT) 2988 .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
2989 | (MAC_MODE_SMII << MAC1_MODE_SHIFT) 2989 | (MAC_MODE_SMII << MAC1_MODE_SHIFT)
2990 | MII_MDIO_10_11_VAL, 2990 | MII_MDIO_10_11_VAL,
2991 }, 2991 },
2992 }; 2992 };
2993 2993
2994 static struct spear_muxreg rmii0_1_ext_muxreg[] = { 2994 static struct spear_muxreg rmii0_1_ext_muxreg[] = {
2995 { 2995 {
2996 .reg = IP_SEL_PAD_10_19_REG, 2996 .reg = IP_SEL_PAD_10_19_REG,
2997 .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK | 2997 .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
2998 PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK, 2998 PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2999 .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL | 2999 .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
3000 PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL | 3000 PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
3001 PMX_RMII_PL_19_VAL, 3001 PMX_RMII_PL_19_VAL,
3002 }, { 3002 }, {
3003 .reg = IP_SEL_PAD_20_29_REG, 3003 .reg = IP_SEL_PAD_20_29_REG,
3004 .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK, 3004 .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
3005 .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL, 3005 .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
3006 }, { 3006 }, {
3007 .reg = EXT_CTRL_REG, 3007 .reg = EXT_CTRL_REG,
3008 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | 3008 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
3009 (MAC_MODE_MASK << MAC1_MODE_SHIFT) | 3009 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
3010 MII_MDIO_MASK, 3010 MII_MDIO_MASK,
3011 .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT) 3011 .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
3012 | (MAC_MODE_RMII << MAC1_MODE_SHIFT) 3012 | (MAC_MODE_RMII << MAC1_MODE_SHIFT)
3013 | MII_MDIO_10_11_VAL, 3013 | MII_MDIO_10_11_VAL,
3014 }, 3014 },
3015 }; 3015 };
3016 3016
3017 static struct spear_modemux mii0_1_modemux[][2] = { 3017 static struct spear_modemux mii0_1_modemux[][2] = {
3018 { 3018 {
3019 /* configure as smii */ 3019 /* configure as smii */
3020 { 3020 {
3021 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | 3021 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3022 SMALL_PRINTERS_MODE | EXTENDED_MODE, 3022 SMALL_PRINTERS_MODE | EXTENDED_MODE,
3023 .muxregs = mii0_1_muxreg, 3023 .muxregs = mii0_1_muxreg,
3024 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), 3024 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3025 }, { 3025 }, {
3026 .modes = EXTENDED_MODE, 3026 .modes = EXTENDED_MODE,
3027 .muxregs = smii0_1_ext_muxreg, 3027 .muxregs = smii0_1_ext_muxreg,
3028 .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg), 3028 .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
3029 }, 3029 },
3030 }, { 3030 }, {
3031 /* configure as rmii */ 3031 /* configure as rmii */
3032 { 3032 {
3033 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | 3033 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3034 SMALL_PRINTERS_MODE | EXTENDED_MODE, 3034 SMALL_PRINTERS_MODE | EXTENDED_MODE,
3035 .muxregs = mii0_1_muxreg, 3035 .muxregs = mii0_1_muxreg,
3036 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), 3036 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3037 }, { 3037 }, {
3038 .modes = EXTENDED_MODE, 3038 .modes = EXTENDED_MODE,
3039 .muxregs = rmii0_1_ext_muxreg, 3039 .muxregs = rmii0_1_ext_muxreg,
3040 .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg), 3040 .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
3041 }, 3041 },
3042 }, 3042 },
3043 }; 3043 };
3044 3044
3045 static struct spear_pingroup mii0_1_pingroup[] = { 3045 static struct spear_pingroup mii0_1_pingroup[] = {
3046 { 3046 {
3047 .name = "smii0_1_grp", 3047 .name = "smii0_1_grp",
3048 .pins = smii0_1_pins, 3048 .pins = smii0_1_pins,
3049 .npins = ARRAY_SIZE(smii0_1_pins), 3049 .npins = ARRAY_SIZE(smii0_1_pins),
3050 .modemuxs = mii0_1_modemux[0], 3050 .modemuxs = mii0_1_modemux[0],
3051 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]), 3051 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
3052 }, { 3052 }, {
3053 .name = "rmii0_1_grp", 3053 .name = "rmii0_1_grp",
3054 .pins = rmii0_1_pins, 3054 .pins = rmii0_1_pins,
3055 .npins = ARRAY_SIZE(rmii0_1_pins), 3055 .npins = ARRAY_SIZE(rmii0_1_pins),
3056 .modemuxs = mii0_1_modemux[1], 3056 .modemuxs = mii0_1_modemux[1],
3057 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]), 3057 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
3058 }, 3058 },
3059 }; 3059 };
3060 3060
3061 static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" }; 3061 static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
3062 static struct spear_function mii0_1_function = { 3062 static struct spear_function mii0_1_function = {
3063 .name = "mii0_1", 3063 .name = "mii0_1",
3064 .groups = mii0_1_grps, 3064 .groups = mii0_1_grps,
3065 .ngroups = ARRAY_SIZE(mii0_1_grps), 3065 .ngroups = ARRAY_SIZE(mii0_1_grps),
3066 }; 3066 };
3067 3067
3068 /* Pad multiplexing for i2c1 device */ 3068 /* Pad multiplexing for i2c1 device */
3069 static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } }; 3069 static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
3070 static struct spear_muxreg i2c1_ext_8_9_muxreg[] = { 3070 static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
3071 { 3071 {
3072 .reg = PMX_CONFIG_REG, 3072 .reg = PMX_CONFIG_REG,
3073 .mask = PMX_SSP_CS_MASK, 3073 .mask = PMX_SSP_CS_MASK,
3074 .val = 0, 3074 .val = 0,
3075 }, { 3075 }, {
3076 .reg = IP_SEL_PAD_0_9_REG, 3076 .reg = IP_SEL_PAD_0_9_REG,
3077 .mask = PMX_PL_8_9_MASK, 3077 .mask = PMX_PL_8_9_MASK,
3078 .val = PMX_I2C1_PL_8_9_VAL, 3078 .val = PMX_I2C1_PL_8_9_VAL,
3079 }, { 3079 }, {
3080 .reg = IP_SEL_MIX_PAD_REG, 3080 .reg = IP_SEL_MIX_PAD_REG,
3081 .mask = PMX_I2C1_PORT_SEL_MASK, 3081 .mask = PMX_I2C1_PORT_SEL_MASK,
3082 .val = PMX_I2C1_PORT_8_9_VAL, 3082 .val = PMX_I2C1_PORT_8_9_VAL,
3083 }, 3083 },
3084 }; 3084 };
3085 3085
3086 static struct spear_muxreg i2c1_ext_98_99_muxreg[] = { 3086 static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
3087 { 3087 {
3088 .reg = IP_SEL_PAD_90_99_REG, 3088 .reg = IP_SEL_PAD_90_99_REG,
3089 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, 3089 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
3090 .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL, 3090 .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
3091 }, { 3091 }, {
3092 .reg = IP_SEL_MIX_PAD_REG, 3092 .reg = IP_SEL_MIX_PAD_REG,
3093 .mask = PMX_I2C1_PORT_SEL_MASK, 3093 .mask = PMX_I2C1_PORT_SEL_MASK,
3094 .val = PMX_I2C1_PORT_98_99_VAL, 3094 .val = PMX_I2C1_PORT_98_99_VAL,
3095 }, 3095 },
3096 }; 3096 };
3097 3097
3098 static struct spear_modemux i2c1_modemux[][1] = { 3098 static struct spear_modemux i2c1_modemux[][1] = {
3099 { 3099 {
3100 /* Select signals on pins 8-9 */ 3100 /* Select signals on pins 8-9 */
3101 { 3101 {
3102 .modes = EXTENDED_MODE, 3102 .modes = EXTENDED_MODE,
3103 .muxregs = i2c1_ext_8_9_muxreg, 3103 .muxregs = i2c1_ext_8_9_muxreg,
3104 .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg), 3104 .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
3105 }, 3105 },
3106 }, { 3106 }, {
3107 /* Select signals on pins 98-99 */ 3107 /* Select signals on pins 98-99 */
3108 { 3108 {
3109 .modes = EXTENDED_MODE, 3109 .modes = EXTENDED_MODE,
3110 .muxregs = i2c1_ext_98_99_muxreg, 3110 .muxregs = i2c1_ext_98_99_muxreg,
3111 .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg), 3111 .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
3112 }, 3112 },
3113 }, 3113 },
3114 }; 3114 };
3115 3115
3116 static struct spear_pingroup i2c1_pingroup[] = { 3116 static struct spear_pingroup i2c1_pingroup[] = {
3117 { 3117 {
3118 .name = "i2c1_8_9_grp", 3118 .name = "i2c1_8_9_grp",
3119 .pins = i2c1_pins[0], 3119 .pins = i2c1_pins[0],
3120 .npins = ARRAY_SIZE(i2c1_pins[0]), 3120 .npins = ARRAY_SIZE(i2c1_pins[0]),
3121 .modemuxs = i2c1_modemux[0], 3121 .modemuxs = i2c1_modemux[0],
3122 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]), 3122 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
3123 }, { 3123 }, {
3124 .name = "i2c1_98_99_grp", 3124 .name = "i2c1_98_99_grp",
3125 .pins = i2c1_pins[1], 3125 .pins = i2c1_pins[1],
3126 .npins = ARRAY_SIZE(i2c1_pins[1]), 3126 .npins = ARRAY_SIZE(i2c1_pins[1]),
3127 .modemuxs = i2c1_modemux[1], 3127 .modemuxs = i2c1_modemux[1],
3128 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]), 3128 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
3129 }, 3129 },
3130 }; 3130 };
3131 3131
3132 static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" }; 3132 static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
3133 static struct spear_function i2c1_function = { 3133 static struct spear_function i2c1_function = {
3134 .name = "i2c1", 3134 .name = "i2c1",
3135 .groups = i2c1_grps, 3135 .groups = i2c1_grps,
3136 .ngroups = ARRAY_SIZE(i2c1_grps), 3136 .ngroups = ARRAY_SIZE(i2c1_grps),
3137 }; 3137 };
3138 3138
3139 /* Pad multiplexing for i2c2 device */ 3139 /* Pad multiplexing for i2c2 device */
3140 static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 }, 3140 static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
3141 { 75, 76 }, { 96, 97 } }; 3141 { 75, 76 }, { 96, 97 } };
3142 static struct spear_muxreg i2c2_ext_0_1_muxreg[] = { 3142 static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
3143 { 3143 {
3144 .reg = PMX_CONFIG_REG, 3144 .reg = PMX_CONFIG_REG,
3145 .mask = PMX_FIRDA_MASK, 3145 .mask = PMX_FIRDA_MASK,
3146 .val = 0, 3146 .val = 0,
3147 }, { 3147 }, {
3148 .reg = IP_SEL_PAD_0_9_REG, 3148 .reg = IP_SEL_PAD_0_9_REG,
3149 .mask = PMX_PL_0_1_MASK, 3149 .mask = PMX_PL_0_1_MASK,
3150 .val = PMX_I2C2_PL_0_1_VAL, 3150 .val = PMX_I2C2_PL_0_1_VAL,
3151 }, { 3151 }, {
3152 .reg = IP_SEL_MIX_PAD_REG, 3152 .reg = IP_SEL_MIX_PAD_REG,
3153 .mask = PMX_I2C2_PORT_SEL_MASK, 3153 .mask = PMX_I2C2_PORT_SEL_MASK,
3154 .val = PMX_I2C2_PORT_0_1_VAL, 3154 .val = PMX_I2C2_PORT_0_1_VAL,
3155 }, 3155 },
3156 }; 3156 };
3157 3157
3158 static struct spear_muxreg i2c2_ext_2_3_muxreg[] = { 3158 static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
3159 { 3159 {
3160 .reg = PMX_CONFIG_REG, 3160 .reg = PMX_CONFIG_REG,
3161 .mask = PMX_UART0_MASK, 3161 .mask = PMX_UART0_MASK,
3162 .val = 0, 3162 .val = 0,
3163 }, { 3163 }, {
3164 .reg = IP_SEL_PAD_0_9_REG, 3164 .reg = IP_SEL_PAD_0_9_REG,
3165 .mask = PMX_PL_2_3_MASK, 3165 .mask = PMX_PL_2_3_MASK,
3166 .val = PMX_I2C2_PL_2_3_VAL, 3166 .val = PMX_I2C2_PL_2_3_VAL,
3167 }, { 3167 }, {
3168 .reg = IP_SEL_MIX_PAD_REG, 3168 .reg = IP_SEL_MIX_PAD_REG,
3169 .mask = PMX_I2C2_PORT_SEL_MASK, 3169 .mask = PMX_I2C2_PORT_SEL_MASK,
3170 .val = PMX_I2C2_PORT_2_3_VAL, 3170 .val = PMX_I2C2_PORT_2_3_VAL,
3171 }, 3171 },
3172 }; 3172 };
3173 3173
3174 static struct spear_muxreg i2c2_ext_19_20_muxreg[] = { 3174 static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
3175 { 3175 {
3176 .reg = PMX_CONFIG_REG, 3176 .reg = PMX_CONFIG_REG,
3177 .mask = PMX_MII_MASK, 3177 .mask = PMX_MII_MASK,
3178 .val = 0, 3178 .val = 0,
3179 }, { 3179 }, {
3180 .reg = IP_SEL_PAD_10_19_REG, 3180 .reg = IP_SEL_PAD_10_19_REG,
3181 .mask = PMX_PL_19_MASK, 3181 .mask = PMX_PL_19_MASK,
3182 .val = PMX_I2C2_PL_19_VAL, 3182 .val = PMX_I2C2_PL_19_VAL,
3183 }, { 3183 }, {
3184 .reg = IP_SEL_PAD_20_29_REG, 3184 .reg = IP_SEL_PAD_20_29_REG,
3185 .mask = PMX_PL_20_MASK, 3185 .mask = PMX_PL_20_MASK,
3186 .val = PMX_I2C2_PL_20_VAL, 3186 .val = PMX_I2C2_PL_20_VAL,
3187 }, { 3187 }, {
3188 .reg = IP_SEL_MIX_PAD_REG, 3188 .reg = IP_SEL_MIX_PAD_REG,
3189 .mask = PMX_I2C2_PORT_SEL_MASK, 3189 .mask = PMX_I2C2_PORT_SEL_MASK,
3190 .val = PMX_I2C2_PORT_19_20_VAL, 3190 .val = PMX_I2C2_PORT_19_20_VAL,
3191 }, 3191 },
3192 }; 3192 };
3193 3193
3194 static struct spear_muxreg i2c2_ext_75_76_muxreg[] = { 3194 static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
3195 { 3195 {
3196 .reg = IP_SEL_PAD_70_79_REG, 3196 .reg = IP_SEL_PAD_70_79_REG,
3197 .mask = PMX_PL_75_76_MASK, 3197 .mask = PMX_PL_75_76_MASK,
3198 .val = PMX_I2C2_PL_75_76_VAL, 3198 .val = PMX_I2C2_PL_75_76_VAL,
3199 }, { 3199 }, {
3200 .reg = IP_SEL_MIX_PAD_REG, 3200 .reg = IP_SEL_MIX_PAD_REG,
3201 .mask = PMX_I2C2_PORT_SEL_MASK, 3201 .mask = PMX_I2C2_PORT_SEL_MASK,
3202 .val = PMX_I2C2_PORT_75_76_VAL, 3202 .val = PMX_I2C2_PORT_75_76_VAL,
3203 }, 3203 },
3204 }; 3204 };
3205 3205
3206 static struct spear_muxreg i2c2_ext_96_97_muxreg[] = { 3206 static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
3207 { 3207 {
3208 .reg = IP_SEL_PAD_90_99_REG, 3208 .reg = IP_SEL_PAD_90_99_REG,
3209 .mask = PMX_PL_96_97_MASK, 3209 .mask = PMX_PL_96_97_MASK,
3210 .val = PMX_I2C2_PL_96_97_VAL, 3210 .val = PMX_I2C2_PL_96_97_VAL,
3211 }, { 3211 }, {
3212 .reg = IP_SEL_MIX_PAD_REG, 3212 .reg = IP_SEL_MIX_PAD_REG,
3213 .mask = PMX_I2C2_PORT_SEL_MASK, 3213 .mask = PMX_I2C2_PORT_SEL_MASK,
3214 .val = PMX_I2C2_PORT_96_97_VAL, 3214 .val = PMX_I2C2_PORT_96_97_VAL,
3215 }, 3215 },
3216 }; 3216 };
3217 3217
3218 static struct spear_modemux i2c2_modemux[][1] = { 3218 static struct spear_modemux i2c2_modemux[][1] = {
3219 { 3219 {
3220 /* Select signals on pins 0_1 */ 3220 /* Select signals on pins 0_1 */
3221 { 3221 {
3222 .modes = EXTENDED_MODE, 3222 .modes = EXTENDED_MODE,
3223 .muxregs = i2c2_ext_0_1_muxreg, 3223 .muxregs = i2c2_ext_0_1_muxreg,
3224 .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg), 3224 .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
3225 }, 3225 },
3226 }, { 3226 }, {
3227 /* Select signals on pins 2_3 */ 3227 /* Select signals on pins 2_3 */
3228 { 3228 {
3229 .modes = EXTENDED_MODE, 3229 .modes = EXTENDED_MODE,
3230 .muxregs = i2c2_ext_2_3_muxreg, 3230 .muxregs = i2c2_ext_2_3_muxreg,
3231 .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg), 3231 .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
3232 }, 3232 },
3233 }, { 3233 }, {
3234 /* Select signals on pins 19_20 */ 3234 /* Select signals on pins 19_20 */
3235 { 3235 {
3236 .modes = EXTENDED_MODE, 3236 .modes = EXTENDED_MODE,
3237 .muxregs = i2c2_ext_19_20_muxreg, 3237 .muxregs = i2c2_ext_19_20_muxreg,
3238 .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg), 3238 .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
3239 }, 3239 },
3240 }, { 3240 }, {
3241 /* Select signals on pins 75_76 */ 3241 /* Select signals on pins 75_76 */
3242 { 3242 {
3243 .modes = EXTENDED_MODE, 3243 .modes = EXTENDED_MODE,
3244 .muxregs = i2c2_ext_75_76_muxreg, 3244 .muxregs = i2c2_ext_75_76_muxreg,
3245 .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg), 3245 .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
3246 }, 3246 },
3247 }, { 3247 }, {
3248 /* Select signals on pins 96_97 */ 3248 /* Select signals on pins 96_97 */
3249 { 3249 {
3250 .modes = EXTENDED_MODE, 3250 .modes = EXTENDED_MODE,
3251 .muxregs = i2c2_ext_96_97_muxreg, 3251 .muxregs = i2c2_ext_96_97_muxreg,
3252 .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg), 3252 .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
3253 }, 3253 },
3254 }, 3254 },
3255 }; 3255 };
3256 3256
3257 static struct spear_pingroup i2c2_pingroup[] = { 3257 static struct spear_pingroup i2c2_pingroup[] = {
3258 { 3258 {
3259 .name = "i2c2_0_1_grp", 3259 .name = "i2c2_0_1_grp",
3260 .pins = i2c2_pins[0], 3260 .pins = i2c2_pins[0],
3261 .npins = ARRAY_SIZE(i2c2_pins[0]), 3261 .npins = ARRAY_SIZE(i2c2_pins[0]),
3262 .modemuxs = i2c2_modemux[0], 3262 .modemuxs = i2c2_modemux[0],
3263 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]), 3263 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
3264 }, { 3264 }, {
3265 .name = "i2c2_2_3_grp", 3265 .name = "i2c2_2_3_grp",
3266 .pins = i2c2_pins[1], 3266 .pins = i2c2_pins[1],
3267 .npins = ARRAY_SIZE(i2c2_pins[1]), 3267 .npins = ARRAY_SIZE(i2c2_pins[1]),
3268 .modemuxs = i2c2_modemux[1], 3268 .modemuxs = i2c2_modemux[1],
3269 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]), 3269 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
3270 }, { 3270 }, {
3271 .name = "i2c2_19_20_grp", 3271 .name = "i2c2_19_20_grp",
3272 .pins = i2c2_pins[2], 3272 .pins = i2c2_pins[2],
3273 .npins = ARRAY_SIZE(i2c2_pins[2]), 3273 .npins = ARRAY_SIZE(i2c2_pins[2]),
3274 .modemuxs = i2c2_modemux[2], 3274 .modemuxs = i2c2_modemux[2],
3275 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]), 3275 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
3276 }, { 3276 }, {
3277 .name = "i2c2_75_76_grp", 3277 .name = "i2c2_75_76_grp",
3278 .pins = i2c2_pins[3], 3278 .pins = i2c2_pins[3],
3279 .npins = ARRAY_SIZE(i2c2_pins[3]), 3279 .npins = ARRAY_SIZE(i2c2_pins[3]),
3280 .modemuxs = i2c2_modemux[3], 3280 .modemuxs = i2c2_modemux[3],
3281 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]), 3281 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
3282 }, { 3282 }, {
3283 .name = "i2c2_96_97_grp", 3283 .name = "i2c2_96_97_grp",
3284 .pins = i2c2_pins[4], 3284 .pins = i2c2_pins[4],
3285 .npins = ARRAY_SIZE(i2c2_pins[4]), 3285 .npins = ARRAY_SIZE(i2c2_pins[4]),
3286 .modemuxs = i2c2_modemux[4], 3286 .modemuxs = i2c2_modemux[4],
3287 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]), 3287 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
3288 }, 3288 },
3289 }; 3289 };
3290 3290
3291 static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp", 3291 static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
3292 "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" }; 3292 "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
3293 static struct spear_function i2c2_function = { 3293 static struct spear_function i2c2_function = {
3294 .name = "i2c2", 3294 .name = "i2c2",
3295 .groups = i2c2_grps, 3295 .groups = i2c2_grps,
3296 .ngroups = ARRAY_SIZE(i2c2_grps), 3296 .ngroups = ARRAY_SIZE(i2c2_grps),
3297 }; 3297 };
3298 3298
3299 /* pingroups */ 3299 /* pingroups */
3300 static struct spear_pingroup *spear320_pingroups[] = { 3300 static struct spear_pingroup *spear320_pingroups[] = {
3301 SPEAR3XX_COMMON_PINGROUPS, 3301 SPEAR3XX_COMMON_PINGROUPS,
3302 &clcd_pingroup, 3302 &clcd_pingroup,
3303 &emi_pingroup, 3303 &emi_pingroup,
3304 &fsmc_8bit_pingroup, 3304 &fsmc_8bit_pingroup,
3305 &fsmc_16bit_pingroup, 3305 &fsmc_16bit_pingroup,
3306 &spp_pingroup, 3306 &spp_pingroup,
3307 &sdhci_led_pingroup, 3307 &sdhci_led_pingroup,
3308 &sdhci_pingroup[0], 3308 &sdhci_pingroup[0],
3309 &sdhci_pingroup[1], 3309 &sdhci_pingroup[1],
3310 &i2s_pingroup, 3310 &i2s_pingroup,
3311 &uart1_pingroup, 3311 &uart1_pingroup,
3312 &uart1_modem_pingroup[0], 3312 &uart1_modem_pingroup[0],
3313 &uart1_modem_pingroup[1], 3313 &uart1_modem_pingroup[1],
3314 &uart1_modem_pingroup[2], 3314 &uart1_modem_pingroup[2],
3315 &uart1_modem_pingroup[3], 3315 &uart1_modem_pingroup[3],
3316 &uart2_pingroup, 3316 &uart2_pingroup,
3317 &uart3_pingroup[0], 3317 &uart3_pingroup[0],
3318 &uart3_pingroup[1], 3318 &uart3_pingroup[1],
3319 &uart3_pingroup[2], 3319 &uart3_pingroup[2],
3320 &uart3_pingroup[3], 3320 &uart3_pingroup[3],
3321 &uart3_pingroup[4], 3321 &uart3_pingroup[4],
3322 &uart3_pingroup[5], 3322 &uart3_pingroup[5],
3323 &uart3_pingroup[6], 3323 &uart3_pingroup[6],
3324 &uart4_pingroup[0], 3324 &uart4_pingroup[0],
3325 &uart4_pingroup[1], 3325 &uart4_pingroup[1],
3326 &uart4_pingroup[2], 3326 &uart4_pingroup[2],
3327 &uart4_pingroup[3], 3327 &uart4_pingroup[3],
3328 &uart4_pingroup[4], 3328 &uart4_pingroup[4],
3329 &uart4_pingroup[5], 3329 &uart4_pingroup[5],
3330 &uart5_pingroup[0], 3330 &uart5_pingroup[0],
3331 &uart5_pingroup[1], 3331 &uart5_pingroup[1],
3332 &uart5_pingroup[2], 3332 &uart5_pingroup[2],
3333 &uart5_pingroup[3], 3333 &uart5_pingroup[3],
3334 &uart6_pingroup[0], 3334 &uart6_pingroup[0],
3335 &uart6_pingroup[1], 3335 &uart6_pingroup[1],
3336 &rs485_pingroup, 3336 &rs485_pingroup,
3337 &touchscreen_pingroup, 3337 &touchscreen_pingroup,
3338 &can0_pingroup, 3338 &can0_pingroup,
3339 &can1_pingroup, 3339 &can1_pingroup,
3340 &pwm0_1_pingroup[0], 3340 &pwm0_1_pingroup[0],
3341 &pwm0_1_pingroup[1], 3341 &pwm0_1_pingroup[1],
3342 &pwm0_1_pingroup[2], 3342 &pwm0_1_pingroup[2],
3343 &pwm0_1_pingroup[3], 3343 &pwm0_1_pingroup[3],
3344 &pwm0_1_pingroup[4], 3344 &pwm0_1_pingroup[4],
3345 &pwm0_1_pingroup[5], 3345 &pwm0_1_pingroup[5],
3346 &pwm0_1_pingroup[6], 3346 &pwm0_1_pingroup[6],
3347 &pwm2_pingroup[0], 3347 &pwm2_pingroup[0],
3348 &pwm2_pingroup[1], 3348 &pwm2_pingroup[1],
3349 &pwm2_pingroup[2], 3349 &pwm2_pingroup[2],
3350 &pwm2_pingroup[3], 3350 &pwm2_pingroup[3],
3351 &pwm2_pingroup[4], 3351 &pwm2_pingroup[4],
3352 &pwm2_pingroup[5], 3352 &pwm2_pingroup[5],
3353 &pwm2_pingroup[6], 3353 &pwm2_pingroup[6],
3354 &pwm3_pingroup[0], 3354 &pwm3_pingroup[0],
3355 &pwm3_pingroup[1], 3355 &pwm3_pingroup[1],
3356 &pwm3_pingroup[2], 3356 &pwm3_pingroup[2],
3357 &pwm3_pingroup[3], 3357 &pwm3_pingroup[3],
3358 &pwm3_pingroup[4], 3358 &pwm3_pingroup[4],
3359 &pwm3_pingroup[5], 3359 &pwm3_pingroup[5],
3360 &ssp1_pingroup[0], 3360 &ssp1_pingroup[0],
3361 &ssp1_pingroup[1], 3361 &ssp1_pingroup[1],
3362 &ssp1_pingroup[2], 3362 &ssp1_pingroup[2],
3363 &ssp1_pingroup[3], 3363 &ssp1_pingroup[3],
3364 &ssp1_pingroup[4], 3364 &ssp1_pingroup[4],
3365 &ssp2_pingroup[0], 3365 &ssp2_pingroup[0],
3366 &ssp2_pingroup[1], 3366 &ssp2_pingroup[1],
3367 &ssp2_pingroup[2], 3367 &ssp2_pingroup[2],
3368 &ssp2_pingroup[3], 3368 &ssp2_pingroup[3],
3369 &ssp2_pingroup[4], 3369 &ssp2_pingroup[4],
3370 &mii2_pingroup, 3370 &mii2_pingroup,
3371 &mii0_1_pingroup[0], 3371 &mii0_1_pingroup[0],
3372 &mii0_1_pingroup[1], 3372 &mii0_1_pingroup[1],
3373 &i2c1_pingroup[0], 3373 &i2c1_pingroup[0],
3374 &i2c1_pingroup[1], 3374 &i2c1_pingroup[1],
3375 &i2c2_pingroup[0], 3375 &i2c2_pingroup[0],
3376 &i2c2_pingroup[1], 3376 &i2c2_pingroup[1],
3377 &i2c2_pingroup[2], 3377 &i2c2_pingroup[2],
3378 &i2c2_pingroup[3], 3378 &i2c2_pingroup[3],
3379 &i2c2_pingroup[4], 3379 &i2c2_pingroup[4],
3380 }; 3380 };
3381 3381
3382 /* functions */ 3382 /* functions */
3383 static struct spear_function *spear320_functions[] = { 3383 static struct spear_function *spear320_functions[] = {
3384 SPEAR3XX_COMMON_FUNCTIONS, 3384 SPEAR3XX_COMMON_FUNCTIONS,
3385 &clcd_function, 3385 &clcd_function,
3386 &emi_function, 3386 &emi_function,
3387 &fsmc_function, 3387 &fsmc_function,
3388 &spp_function, 3388 &spp_function,
3389 &sdhci_function, 3389 &sdhci_function,
3390 &i2s_function, 3390 &i2s_function,
3391 &uart1_function, 3391 &uart1_function,
3392 &uart1_modem_function, 3392 &uart1_modem_function,
3393 &uart2_function, 3393 &uart2_function,
3394 &uart3_function, 3394 &uart3_function,
3395 &uart4_function, 3395 &uart4_function,
3396 &uart5_function, 3396 &uart5_function,
3397 &uart6_function, 3397 &uart6_function,
3398 &rs485_function, 3398 &rs485_function,
3399 &touchscreen_function, 3399 &touchscreen_function,
3400 &can0_function, 3400 &can0_function,
3401 &can1_function, 3401 &can1_function,
3402 &pwm0_1_function, 3402 &pwm0_1_function,
3403 &pwm2_function, 3403 &pwm2_function,
3404 &pwm3_function, 3404 &pwm3_function,
3405 &ssp1_function, 3405 &ssp1_function,
3406 &ssp2_function, 3406 &ssp2_function,
3407 &mii2_function, 3407 &mii2_function,
3408 &mii0_1_function, 3408 &mii0_1_function,
3409 &i2c1_function, 3409 &i2c1_function,
3410 &i2c2_function, 3410 &i2c2_function,
3411 }; 3411 };
3412 3412
3413 static struct of_device_id spear320_pinctrl_of_match[] = { 3413 static struct of_device_id spear320_pinctrl_of_match[] = {
3414 { 3414 {
3415 .compatible = "st,spear320-pinmux", 3415 .compatible = "st,spear320-pinmux",
3416 }, 3416 },
3417 {}, 3417 {},
3418 }; 3418 };
3419 3419
3420 static int __devinit spear320_pinctrl_probe(struct platform_device *pdev) 3420 static int __devinit spear320_pinctrl_probe(struct platform_device *pdev)
3421 { 3421 {
3422 int ret; 3422 int ret;
3423 3423
3424 spear3xx_machdata.groups = spear320_pingroups; 3424 spear3xx_machdata.groups = spear320_pingroups;
3425 spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups); 3425 spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
3426 spear3xx_machdata.functions = spear320_functions; 3426 spear3xx_machdata.functions = spear320_functions;
3427 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions); 3427 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
3428 3428
3429 spear3xx_machdata.modes_supported = true; 3429 spear3xx_machdata.modes_supported = true;
3430 spear3xx_machdata.pmx_modes = spear320_pmx_modes; 3430 spear3xx_machdata.pmx_modes = spear320_pmx_modes;
3431 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes); 3431 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
3432 3432
3433 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); 3433 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
3434 3434
3435 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); 3435 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
3436 if (ret) 3436 if (ret)
3437 return ret; 3437 return ret;
3438 3438
3439 return 0; 3439 return 0;
3440 } 3440 }
3441 3441
3442 static int __devexit spear320_pinctrl_remove(struct platform_device *pdev) 3442 static int spear320_pinctrl_remove(struct platform_device *pdev)
3443 { 3443 {
3444 return spear_pinctrl_remove(pdev); 3444 return spear_pinctrl_remove(pdev);
3445 } 3445 }
3446 3446
3447 static struct platform_driver spear320_pinctrl_driver = { 3447 static struct platform_driver spear320_pinctrl_driver = {
3448 .driver = { 3448 .driver = {
3449 .name = DRIVER_NAME, 3449 .name = DRIVER_NAME,
3450 .owner = THIS_MODULE, 3450 .owner = THIS_MODULE,
3451 .of_match_table = spear320_pinctrl_of_match, 3451 .of_match_table = spear320_pinctrl_of_match,
3452 }, 3452 },
3453 .probe = spear320_pinctrl_probe, 3453 .probe = spear320_pinctrl_probe,
3454 .remove = spear320_pinctrl_remove, 3454 .remove = spear320_pinctrl_remove,
3455 }; 3455 };
3456 3456
3457 static int __init spear320_pinctrl_init(void) 3457 static int __init spear320_pinctrl_init(void)
3458 { 3458 {
3459 return platform_driver_register(&spear320_pinctrl_driver); 3459 return platform_driver_register(&spear320_pinctrl_driver);
3460 } 3460 }
3461 arch_initcall(spear320_pinctrl_init); 3461 arch_initcall(spear320_pinctrl_init);
3462 3462
3463 static void __exit spear320_pinctrl_exit(void) 3463 static void __exit spear320_pinctrl_exit(void)
3464 { 3464 {
3465 platform_driver_unregister(&spear320_pinctrl_driver); 3465 platform_driver_unregister(&spear320_pinctrl_driver);
3466 } 3466 }
3467 module_exit(spear320_pinctrl_exit); 3467 module_exit(spear320_pinctrl_exit);
3468 3468
3469 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); 3469 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
3470 MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver"); 3470 MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver");
3471 MODULE_LICENSE("GPL v2"); 3471 MODULE_LICENSE("GPL v2");
3472 MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match); 3472 MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match);
3473 3473