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Commit ff7cbc4b5c6276865a6db594c4b8459ebad457a4

Authored by Mike Frysinger
1 parent 10cbb0ba42
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

Blackfin: ppi/spi/twi headers: add missing __BFP undef 

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Showing 3 changed files with 6 additions and 0 deletions Inline Diff

arch/blackfin/include/asm/bfin5xx_spi.h
Diff comments   View file @ ff7cbc4
1 /* 1 /*
2 * Blackfin On-Chip SPI Driver 2 * Blackfin On-Chip SPI Driver
3 * 3 *
4 * Copyright 2004-2008 Analog Devices Inc. 4 * Copyright 2004-2008 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9 #ifndef _SPI_CHANNEL_H_ 9 #ifndef _SPI_CHANNEL_H_
10 #define _SPI_CHANNEL_H_ 10 #define _SPI_CHANNEL_H_
11 11
12 #define MIN_SPI_BAUD_VAL 2 12 #define MIN_SPI_BAUD_VAL 2
13 13
14 #define BIT_CTL_ENABLE 0x4000 14 #define BIT_CTL_ENABLE 0x4000
15 #define BIT_CTL_OPENDRAIN 0x2000 15 #define BIT_CTL_OPENDRAIN 0x2000
16 #define BIT_CTL_MASTER 0x1000 16 #define BIT_CTL_MASTER 0x1000
17 #define BIT_CTL_CPOL 0x0800 17 #define BIT_CTL_CPOL 0x0800
18 #define BIT_CTL_CPHA 0x0400 18 #define BIT_CTL_CPHA 0x0400
19 #define BIT_CTL_LSBF 0x0200 19 #define BIT_CTL_LSBF 0x0200
20 #define BIT_CTL_WORDSIZE 0x0100 20 #define BIT_CTL_WORDSIZE 0x0100
21 #define BIT_CTL_EMISO 0x0020 21 #define BIT_CTL_EMISO 0x0020
22 #define BIT_CTL_PSSE 0x0010 22 #define BIT_CTL_PSSE 0x0010
23 #define BIT_CTL_GM 0x0008 23 #define BIT_CTL_GM 0x0008
24 #define BIT_CTL_SZ 0x0004 24 #define BIT_CTL_SZ 0x0004
25 #define BIT_CTL_RXMOD 0x0000 25 #define BIT_CTL_RXMOD 0x0000
26 #define BIT_CTL_TXMOD 0x0001 26 #define BIT_CTL_TXMOD 0x0001
27 #define BIT_CTL_TIMOD_DMA_TX 0x0003 27 #define BIT_CTL_TIMOD_DMA_TX 0x0003
28 #define BIT_CTL_TIMOD_DMA_RX 0x0002 28 #define BIT_CTL_TIMOD_DMA_RX 0x0002
29 #define BIT_CTL_SENDOPT 0x0004 29 #define BIT_CTL_SENDOPT 0x0004
30 #define BIT_CTL_TIMOD 0x0003 30 #define BIT_CTL_TIMOD 0x0003
31 31
32 #define BIT_STAT_SPIF 0x0001 32 #define BIT_STAT_SPIF 0x0001
33 #define BIT_STAT_MODF 0x0002 33 #define BIT_STAT_MODF 0x0002
34 #define BIT_STAT_TXE 0x0004 34 #define BIT_STAT_TXE 0x0004
35 #define BIT_STAT_TXS 0x0008 35 #define BIT_STAT_TXS 0x0008
36 #define BIT_STAT_RBSY 0x0010 36 #define BIT_STAT_RBSY 0x0010
37 #define BIT_STAT_RXS 0x0020 37 #define BIT_STAT_RXS 0x0020
38 #define BIT_STAT_TXCOL 0x0040 38 #define BIT_STAT_TXCOL 0x0040
39 #define BIT_STAT_CLR 0xFFFF 39 #define BIT_STAT_CLR 0xFFFF
40 40
41 #define BIT_STU_SENDOVER 0x0001 41 #define BIT_STU_SENDOVER 0x0001
42 #define BIT_STU_RECVFULL 0x0020 42 #define BIT_STU_RECVFULL 0x0020
43 43
44 /* 44 /*
45 * All Blackfin system MMRs are padded to 32bits even if the register 45 * All Blackfin system MMRs are padded to 32bits even if the register
46 * itself is only 16bits. So use a helper macro to streamline this. 46 * itself is only 16bits. So use a helper macro to streamline this.
47 */ 47 */
48 #define __BFP(m) u16 m; u16 __pad_##m 48 #define __BFP(m) u16 m; u16 __pad_##m
49 49
50 /* 50 /*
51 * bfin spi registers layout 51 * bfin spi registers layout
52 */ 52 */
53 struct bfin_spi_regs { 53 struct bfin_spi_regs {
54 __BFP(ctl); 54 __BFP(ctl);
55 __BFP(flg); 55 __BFP(flg);
56 __BFP(stat); 56 __BFP(stat);
57 __BFP(tdbr); 57 __BFP(tdbr);
58 __BFP(rdbr); 58 __BFP(rdbr);
59 __BFP(baud); 59 __BFP(baud);
60 __BFP(shadow); 60 __BFP(shadow);
61 }; 61 };
62 62
63 #undef __BFP
64
63 #define MAX_CTRL_CS 8 /* cs in spi controller */ 65 #define MAX_CTRL_CS 8 /* cs in spi controller */
64 66
65 /* device.platform_data for SSP controller devices */ 67 /* device.platform_data for SSP controller devices */
66 struct bfin5xx_spi_master { 68 struct bfin5xx_spi_master {
67 u16 num_chipselect; 69 u16 num_chipselect;
68 u8 enable_dma; 70 u8 enable_dma;
69 u16 pin_req[7]; 71 u16 pin_req[7];
70 }; 72 };
71 73
72 /* spi_board_info.controller_data for SPI slave devices, 74 /* spi_board_info.controller_data for SPI slave devices,
73 * copied to spi_device.platform_data ... mostly for dma tuning 75 * copied to spi_device.platform_data ... mostly for dma tuning
74 */ 76 */
75 struct bfin5xx_spi_chip { 77 struct bfin5xx_spi_chip {
76 u16 ctl_reg; 78 u16 ctl_reg;
77 u8 enable_dma; 79 u8 enable_dma;
78 u8 bits_per_word; 80 u8 bits_per_word;
79 u16 cs_chg_udelay; /* Some devices require 16-bit delays */ 81 u16 cs_chg_udelay; /* Some devices require 16-bit delays */
80 /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */ 82 /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
81 u16 idle_tx_val; 83 u16 idle_tx_val;
82 u8 pio_interrupt; /* Enable spi data irq */ 84 u8 pio_interrupt; /* Enable spi data irq */
83 }; 85 };
84 86
85 #endif /* _SPI_CHANNEL_H_ */ 87 #endif /* _SPI_CHANNEL_H_ */
86 88
arch/blackfin/include/asm/bfin_ppi.h
Diff comments   View file @ ff7cbc4
1 /* 1 /*
2 * bfin_ppi.h - interface to Blackfin PPIs 2 * bfin_ppi.h - interface to Blackfin PPIs
3 * 3 *
4 * Copyright 2005-2010 Analog Devices Inc. 4 * Copyright 2005-2010 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9 #ifndef __ASM_BFIN_PPI_H__ 9 #ifndef __ASM_BFIN_PPI_H__
10 #define __ASM_BFIN_PPI_H__ 10 #define __ASM_BFIN_PPI_H__
11 11
12 #include <linux/types.h> 12 #include <linux/types.h>
13 13
14 /* 14 /*
15 * All Blackfin system MMRs are padded to 32bits even if the register 15 * All Blackfin system MMRs are padded to 32bits even if the register
16 * itself is only 16bits. So use a helper macro to streamline this. 16 * itself is only 16bits. So use a helper macro to streamline this.
17 */ 17 */
18 #define __BFP(m) u16 m; u16 __pad_##m 18 #define __BFP(m) u16 m; u16 __pad_##m
19 19
20 /* 20 /*
21 * bfin ppi registers layout 21 * bfin ppi registers layout
22 */ 22 */
23 struct bfin_ppi_regs { 23 struct bfin_ppi_regs {
24 __BFP(control); 24 __BFP(control);
25 __BFP(status); 25 __BFP(status);
26 __BFP(count); 26 __BFP(count);
27 __BFP(delay); 27 __BFP(delay);
28 __BFP(frame); 28 __BFP(frame);
29 }; 29 };
30 30
31 /* 31 /*
32 * bfin eppi registers layout 32 * bfin eppi registers layout
33 */ 33 */
34 struct bfin_eppi_regs { 34 struct bfin_eppi_regs {
35 __BFP(status); 35 __BFP(status);
36 __BFP(hcount); 36 __BFP(hcount);
37 __BFP(hdelay); 37 __BFP(hdelay);
38 __BFP(vcount); 38 __BFP(vcount);
39 __BFP(vdelay); 39 __BFP(vdelay);
40 __BFP(frame); 40 __BFP(frame);
41 __BFP(line); 41 __BFP(line);
42 __BFP(clkdiv); 42 __BFP(clkdiv);
43 u32 control; 43 u32 control;
44 u32 fs1w_hbl; 44 u32 fs1w_hbl;
45 u32 fs1p_avpl; 45 u32 fs1p_avpl;
46 u32 fs2w_lvb; 46 u32 fs2w_lvb;
47 u32 fs2p_lavf; 47 u32 fs2p_lavf;
48 u32 clip; 48 u32 clip;
49 }; 49 };
50 50
51 #undef __BFP
52
51 #endif 53 #endif
52 54
arch/blackfin/include/asm/bfin_twi.h
Diff comments   View file @ ff7cbc4
1 /* 1 /*
2 * bfin_twi.h - interface to Blackfin TWIs 2 * bfin_twi.h - interface to Blackfin TWIs
3 * 3 *
4 * Copyright 2005-2010 Analog Devices Inc. 4 * Copyright 2005-2010 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9 #ifndef __ASM_BFIN_TWI_H__ 9 #ifndef __ASM_BFIN_TWI_H__
10 #define __ASM_BFIN_TWI_H__ 10 #define __ASM_BFIN_TWI_H__
11 11
12 #include <linux/types.h> 12 #include <linux/types.h>
13 13
14 /* 14 /*
15 * All Blackfin system MMRs are padded to 32bits even if the register 15 * All Blackfin system MMRs are padded to 32bits even if the register
16 * itself is only 16bits. So use a helper macro to streamline this. 16 * itself is only 16bits. So use a helper macro to streamline this.
17 */ 17 */
18 #define __BFP(m) u16 m; u16 __pad_##m 18 #define __BFP(m) u16 m; u16 __pad_##m
19 19
20 /* 20 /*
21 * bfin twi registers layout 21 * bfin twi registers layout
22 */ 22 */
23 struct bfin_twi_regs { 23 struct bfin_twi_regs {
24 __BFP(clkdiv); 24 __BFP(clkdiv);
25 __BFP(control); 25 __BFP(control);
26 __BFP(slave_ctl); 26 __BFP(slave_ctl);
27 __BFP(slave_stat); 27 __BFP(slave_stat);
28 __BFP(slave_addr); 28 __BFP(slave_addr);
29 __BFP(master_ctl); 29 __BFP(master_ctl);
30 __BFP(master_stat); 30 __BFP(master_stat);
31 __BFP(master_addr); 31 __BFP(master_addr);
32 __BFP(int_stat); 32 __BFP(int_stat);
33 __BFP(int_mask); 33 __BFP(int_mask);
34 __BFP(fifo_ctl); 34 __BFP(fifo_ctl);
35 __BFP(fifo_stat); 35 __BFP(fifo_stat);
36 u32 __pad[20]; 36 u32 __pad[20];
37 __BFP(xmt_data8); 37 __BFP(xmt_data8);
38 __BFP(xmt_data16); 38 __BFP(xmt_data16);
39 __BFP(rcv_data8); 39 __BFP(rcv_data8);
40 __BFP(rcv_data16); 40 __BFP(rcv_data16);
41 }; 41 };
42 42
43 #undef __BFP
44
43 #endif 45 #endif
44 46